diff options
| -rw-r--r-- | target/microblaze/cpu.c | 24 | ||||
| -rw-r--r-- | target/microblaze/cpu.h | 6 | ||||
| -rw-r--r-- | target/microblaze/op_helper.c | 5 | ||||
| -rw-r--r-- | target/microblaze/translate.c | 8 |
4 files changed, 35 insertions, 8 deletions
diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index c9cf2364ca..aa9983069a 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -193,8 +193,10 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.use_mmu ? PVR0_USE_MMU_MASK : 0) | (cpu->cfg.endi ? PVR0_ENDI_MASK : 0) | (version_code << PVR0_VERSION_SHIFT) | - (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0); + (cpu->cfg.pvr == C_PVR_FULL ? PVR0_PVR_FULL_MASK : 0) | + cpu->cfg.pvr_user1; + env->pvr.regs[1] = cpu->cfg.pvr_user2; env->pvr.regs[2] |= (cpu->cfg.use_fpu ? PVR2_USE_FPU_MASK : 0) | (cpu->cfg.use_fpu > 1 ? PVR2_USE_FPU2_MASK : 0) | (cpu->cfg.use_hw_mul ? PVR2_USE_HW_MUL_MASK : 0) | @@ -206,7 +208,15 @@ static void mb_cpu_realizefn(DeviceState *dev, Error **errp) (cpu->cfg.dopb_bus_exception ? PVR2_DOPB_BUS_EXC_MASK : 0) | (cpu->cfg.iopb_bus_exception ? - PVR2_IOPB_BUS_EXC_MASK : 0); + PVR2_IOPB_BUS_EXC_MASK : 0) | + (cpu->cfg.div_zero_exception ? + PVR2_DIV_ZERO_EXC_MASK : 0) | + (cpu->cfg.illegal_opcode_exception ? + PVR2_ILL_OPCODE_EXC_MASK : 0) | + (cpu->cfg.unaligned_exceptions ? + PVR2_UNALIGNED_EXC_MASK : 0) | + (cpu->cfg.opcode_0_illegal ? + PVR2_OPCODE_0x0_ILL_MASK : 0); env->pvr.regs[5] |= cpu->cfg.dcache_writeback ? PVR5_DCACHE_WRITEBACK_MASK : 0; @@ -274,8 +284,18 @@ static Property mb_properties[] = { /* Enables bus exceptions on failed instruction fetches. */ DEFINE_PROP_BOOL("iopb-bus-exception", MicroBlazeCPU, cfg.iopb_bus_exception, false), + DEFINE_PROP_BOOL("ill-opcode-exception", MicroBlazeCPU, + cfg.illegal_opcode_exception, false), + DEFINE_PROP_BOOL("div-zero-exception", MicroBlazeCPU, + cfg.div_zero_exception, false), + DEFINE_PROP_BOOL("unaligned-exceptions", MicroBlazeCPU, + cfg.unaligned_exceptions, false), + DEFINE_PROP_BOOL("opcode-0x0-illegal", MicroBlazeCPU, + cfg.opcode_0_illegal, false), DEFINE_PROP_STRING("version", MicroBlazeCPU, cfg.version), DEFINE_PROP_UINT8("pvr", MicroBlazeCPU, cfg.pvr, C_PVR_FULL), + DEFINE_PROP_UINT8("pvr-user1", MicroBlazeCPU, cfg.pvr_user1, 0), + DEFINE_PROP_UINT32("pvr-user2", MicroBlazeCPU, cfg.pvr_user2, 0), DEFINE_PROP_END_OF_LIST(), }; diff --git a/target/microblaze/cpu.h b/target/microblaze/cpu.h index 1a700a880c..a31134b65c 100644 --- a/target/microblaze/cpu.h +++ b/target/microblaze/cpu.h @@ -303,6 +303,12 @@ struct MicroBlazeCPU { bool endi; bool dopb_bus_exception; bool iopb_bus_exception; + bool illegal_opcode_exception; + bool opcode_0_illegal; + bool div_zero_exception; + bool unaligned_exceptions; + uint8_t pvr_user1; + uint32_t pvr_user2; char *version; uint8_t pvr; } cfg; diff --git a/target/microblaze/op_helper.c b/target/microblaze/op_helper.c index 18677ddfca..f3b17a95b3 100644 --- a/target/microblaze/op_helper.c +++ b/target/microblaze/op_helper.c @@ -132,11 +132,12 @@ uint32_t helper_carry(uint32_t a, uint32_t b, uint32_t cf) static inline int div_prepare(CPUMBState *env, uint32_t a, uint32_t b) { + MicroBlazeCPU *cpu = env_archcpu(env); + if (b == 0) { env->sregs[SR_MSR] |= MSR_DZ; - if ((env->sregs[SR_MSR] & MSR_EE) - && !(env->pvr.regs[2] & PVR2_DIV_ZERO_EXC_MASK)) { + if ((env->sregs[SR_MSR] & MSR_EE) && cpu->cfg.div_zero_exception) { env->sregs[SR_ESR] = ESR_EC_DIVZERO; helper_raise_exception(env, EXCP_HW_EXCP); } diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 37a844db99..20b7427811 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -185,7 +185,7 @@ static void write_carryi(DisasContext *dc, bool carry) static bool trap_illegal(DisasContext *dc, bool cond) { if (cond && (dc->tb_flags & MSR_EE_FLAG) - && (dc->cpu->env.pvr.regs[2] & PVR2_ILL_OPCODE_EXC_MASK)) { + && dc->cpu->cfg.illegal_opcode_exception) { tcg_gen_movi_i64(cpu_SR[SR_ESR], ESR_EC_ILLEGAL_OP); t_gen_raise_exception(dc, EXCP_HW_EXCP); } @@ -995,7 +995,7 @@ static void dec_load(DisasContext *dc) v = tcg_temp_new_i32(); tcg_gen_qemu_ld_i32(v, addr, mem_index, mop); - if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { + if (dc->cpu->cfg.unaligned_exceptions && size > 1) { TCGv_i32 t0 = tcg_const_i32(0); TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); @@ -1110,7 +1110,7 @@ static void dec_store(DisasContext *dc) tcg_gen_qemu_st_i32(cpu_R[dc->rd], addr, mem_index, mop); /* Verify alignment if needed. */ - if ((dc->cpu->env.pvr.regs[2] & PVR2_UNALIGNED_EXC_MASK) && size > 1) { + if (dc->cpu->cfg.unaligned_exceptions && size > 1) { TCGv_i32 t1 = tcg_const_i32(1); TCGv_i32 treg = tcg_const_i32(dc->rd); TCGv_i32 tsize = tcg_const_i32(size - 1); @@ -1573,7 +1573,7 @@ static inline void decode(DisasContext *dc, uint32_t ir) LOG_DIS("%8.8x\t", dc->ir); if (ir == 0) { - trap_illegal(dc, dc->cpu->env.pvr.regs[2] & PVR2_OPCODE_0x0_ILL_MASK); + trap_illegal(dc, dc->cpu->cfg.opcode_0_illegal); /* Don't decode nop/zero instructions any further. */ return; } |