diff options
| -rw-r--r-- | target/riscv/cpu.h | 4 | ||||
| -rw-r--r-- | target/riscv/machine.c | 2 |
2 files changed, 6 insertions, 0 deletions
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index b9dee7d147..e8c664a956 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -195,6 +195,10 @@ struct CPURISCVState { target_ulong hgatp; uint64_t htimedelta; + /* Upper 64-bits of 128-bit CSRs */ + uint64_t mscratchh; + uint64_t sscratchh; + /* Virtual CSRs */ /* * For RV32 this is 32-bit vsstatus and 32-bit vsstatush. diff --git a/target/riscv/machine.c b/target/riscv/machine.c index 8af9caabf5..13b9ab375b 100644 --- a/target/riscv/machine.c +++ b/target/riscv/machine.c @@ -179,6 +179,8 @@ static const VMStateDescription vmstate_rv128 = { .needed = rv128_needed, .fields = (VMStateField[]) { VMSTATE_UINTTL_ARRAY(env.gprh, RISCVCPU, 32), + VMSTATE_UINT64(env.mscratchh, RISCVCPU), + VMSTATE_UINT64(env.sscratchh, RISCVCPU), VMSTATE_END_OF_LIST() } }; |