diff options
25 files changed, 149 insertions, 296 deletions
diff --git a/linux-user/hexagon/cpu_loop.c b/linux-user/hexagon/cpu_loop.c index d41159e52a..40db596301 100644 --- a/linux-user/hexagon/cpu_loop.c +++ b/linux-user/hexagon/cpu_loop.c @@ -42,7 +42,7 @@ void cpu_loop(CPUHexagonState *env) case EXCP_INTERRUPT: /* just indicate that signals should be handled asap */ break; - case HEX_EXCP_TRAP0: + case HEX_EVENT_TRAP0: syscallnum = env->gpr[6]; env->gpr[HEX_REG_PC] += 4; ret = do_syscall(env, @@ -60,7 +60,7 @@ void cpu_loop(CPUHexagonState *env) env->gpr[0] = ret; } break; - case HEX_EXCP_PC_NOT_ALIGNED: + case HEX_CAUSE_PC_NOT_ALIGNED: force_sig_fault(TARGET_SIGBUS, TARGET_BUS_ADRALN, env->gpr[HEX_REG_R31]); break; diff --git a/target/hexagon/README b/target/hexagon/README index 7ffd517d70..ca617e3364 100644 --- a/target/hexagon/README +++ b/target/hexagon/README @@ -282,10 +282,6 @@ For Hexagon Vector eXtensions (HVX), the following fields are used *** Debugging *** -You can turn on a lot of debugging by changing the HEX_DEBUG macro to 1 in -internal.h. This will stream a lot of information as it generates TCG and -executes the code. - To track down nasty issues with Hexagon->TCG generation, we compare the execution results with actual hardware running on a Hexagon Linux target. Run qemu with the "-d cpu" option. Then, we can diff the results and figure @@ -305,8 +301,3 @@ Here are some handy places to set breakpoints The helper function for each instruction is named helper_<TAG>, so here's an example that will set a breakpoint at the start br helper_A2_add - If you have the HEX_DEBUG macro set, the following will be useful - At the start of execution of a packet for a given PC - br helper_debug_start_packet if env->gpr[41] == 0xdeadbeef - At the end of execution of a packet for a given PC - br helper_debug_commit_end if this_PC == 0xdeadbeef diff --git a/target/hexagon/cpu.h b/target/hexagon/cpu.h index 764f3c38cc..14e6e819c2 100644 --- a/target/hexagon/cpu.h +++ b/target/hexagon/cpu.h @@ -79,12 +79,6 @@ typedef struct CPUArchState { uint8_t slot_cancelled; target_ulong new_value_usr; - /* - * Only used when HEX_DEBUG is on, but unconditionally included - * to reduce recompile time when turning HEX_DEBUG on/off. - */ - target_ulong reg_written[TOTAL_PER_THREAD_REGS]; - MemLog mem_log_stores[STORES_MAX]; float_status fp_status; @@ -149,7 +143,7 @@ static inline void cpu_get_tb_cpu_state(CPUHexagonState *env, vaddr *pc, } *flags = hex_flags; if (*pc & PCALIGN_MASK) { - hexagon_raise_exception_err(env, HEX_EXCP_PC_NOT_ALIGNED, 0); + hexagon_raise_exception_err(env, HEX_CAUSE_PC_NOT_ALIGNED, 0); } } diff --git a/target/hexagon/cpu_bits.h b/target/hexagon/cpu_bits.h index 4279281a71..ff596e2a94 100644 --- a/target/hexagon/cpu_bits.h +++ b/target/hexagon/cpu_bits.h @@ -23,14 +23,21 @@ #define PCALIGN 4 #define PCALIGN_MASK (PCALIGN - 1) -#define HEX_EXCP_FETCH_NO_UPAGE 0x012 -#define HEX_EXCP_INVALID_PACKET 0x015 -#define HEX_EXCP_INVALID_OPCODE 0x015 -#define HEX_EXCP_PC_NOT_ALIGNED 0x01e -#define HEX_EXCP_PRIV_NO_UREAD 0x024 -#define HEX_EXCP_PRIV_NO_UWRITE 0x025 - -#define HEX_EXCP_TRAP0 0x172 +enum hex_event { + HEX_EVENT_NONE = -1, + HEX_EVENT_TRAP0 = 0x008, +}; + +enum hex_cause { + HEX_CAUSE_NONE = -1, + HEX_CAUSE_TRAP0 = 0x172, + HEX_CAUSE_FETCH_NO_UPAGE = 0x012, + HEX_CAUSE_INVALID_PACKET = 0x015, + HEX_CAUSE_INVALID_OPCODE = 0x015, + HEX_CAUSE_PC_NOT_ALIGNED = 0x01e, + HEX_CAUSE_PRIV_NO_UREAD = 0x024, + HEX_CAUSE_PRIV_NO_UWRITE = 0x025, +}; #define PACKET_WORDS_MAX 4 diff --git a/target/hexagon/gen_analyze_funcs.py b/target/hexagon/gen_analyze_funcs.py index 54bac19724..3ac7cc2cfe 100755 --- a/target/hexagon/gen_analyze_funcs.py +++ b/target/hexagon/gen_analyze_funcs.py @@ -78,11 +78,13 @@ def gen_analyze_func(f, tag, regs, imms): def main(): - hex_common.read_common_files() + args = hex_common.parse_common_args( + "Emit functions analyzing register accesses" + ) tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() - with open(sys.argv[-1], "w") as f: + with open(args.out, "w") as f: f.write("#ifndef HEXAGON_ANALYZE_FUNCS_C_INC\n") f.write("#define HEXAGON_ANALYZE_FUNCS_C_INC\n\n") diff --git a/target/hexagon/gen_decodetree.py b/target/hexagon/gen_decodetree.py index a4fcd622c5..ce703af41d 100755 --- a/target/hexagon/gen_decodetree.py +++ b/target/hexagon/gen_decodetree.py @@ -24,6 +24,7 @@ import sys import textwrap import iset import hex_common +import argparse encs = { tag: "".join(reversed(iset.iset[tag]["enc"].replace(" ", ""))) @@ -191,8 +192,18 @@ def gen_decodetree_file(f, class_to_decode): f.write(f"{tag}\t{enc_str} @{tag}\n") +def main(): + parser = argparse.ArgumentParser( + description="Emit opaque macro calls with instruction semantics" + ) + parser.add_argument("semantics", help="semantics file") + parser.add_argument("class_to_decode", help="instruction class to decode") + parser.add_argument("out", help="output file") + args = parser.parse_args() + + hex_common.read_semantics_file(args.semantics) + with open(args.out, "w") as f: + gen_decodetree_file(f, args.class_to_decode) + if __name__ == "__main__": - hex_common.read_semantics_file(sys.argv[1]) - class_to_decode = sys.argv[2] - with open(sys.argv[3], "w") as f: - gen_decodetree_file(f, class_to_decode) + main() diff --git a/target/hexagon/gen_helper_funcs.py b/target/hexagon/gen_helper_funcs.py index e9685bff2f..c1f806ac4b 100755 --- a/target/hexagon/gen_helper_funcs.py +++ b/target/hexagon/gen_helper_funcs.py @@ -102,12 +102,13 @@ def gen_helper_function(f, tag, tagregs, tagimms): def main(): - hex_common.read_common_files() + args = hex_common.parse_common_args( + "Emit helper function definitions for each instruction" + ) tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() - output_file = sys.argv[-1] - with open(output_file, "w") as f: + with open(args.out, "w") as f: for tag in hex_common.tags: ## Skip the priv instructions if "A_PRIV" in hex_common.attribdict[tag]: diff --git a/target/hexagon/gen_helper_protos.py b/target/hexagon/gen_helper_protos.py index fd2bfd0f36..77f8e0a6a3 100755 --- a/target/hexagon/gen_helper_protos.py +++ b/target/hexagon/gen_helper_protos.py @@ -52,12 +52,13 @@ def gen_helper_prototype(f, tag, tagregs, tagimms): def main(): - hex_common.read_common_files() + args = hex_common.parse_common_args( + "Emit helper function prototypes for each instruction" + ) tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() - output_file = sys.argv[-1] - with open(output_file, "w") as f: + with open(args.out, "w") as f: for tag in hex_common.tags: ## Skip the priv instructions if "A_PRIV" in hex_common.attribdict[tag]: diff --git a/target/hexagon/gen_idef_parser_funcs.py b/target/hexagon/gen_idef_parser_funcs.py index 72f11c68ca..2f6e826f76 100644 --- a/target/hexagon/gen_idef_parser_funcs.py +++ b/target/hexagon/gen_idef_parser_funcs.py @@ -20,6 +20,7 @@ import sys import re import string +import argparse from io import StringIO import hex_common @@ -43,13 +44,19 @@ import hex_common ## them are inputs ("in" prefix), while some others are outputs. ## def main(): - hex_common.read_semantics_file(sys.argv[1]) + parser = argparse.ArgumentParser( + "Emit instruction implementations that can be fed to idef-parser" + ) + parser.add_argument("semantics", help="semantics file") + parser.add_argument("out", help="output file") + args = parser.parse_args() + hex_common.read_semantics_file(args.semantics) hex_common.calculate_attribs() hex_common.init_registers() tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() - with open(sys.argv[-1], "w") as f: + with open(args.out, "w") as f: f.write('#include "macros.h.inc"\n\n') for tag in hex_common.tags: diff --git a/target/hexagon/gen_op_attribs.py b/target/hexagon/gen_op_attribs.py index 99448220da..bbbb02df3a 100755 --- a/target/hexagon/gen_op_attribs.py +++ b/target/hexagon/gen_op_attribs.py @@ -21,16 +21,23 @@ import sys import re import string import hex_common +import argparse def main(): - hex_common.read_semantics_file(sys.argv[1]) + parser = argparse.ArgumentParser( + "Emit opaque macro calls containing instruction attributes" + ) + parser.add_argument("semantics", help="semantics file") + parser.add_argument("out", help="output file") + args = parser.parse_args() + hex_common.read_semantics_file(args.semantics) hex_common.calculate_attribs() ## ## Generate all the attributes associated with each instruction ## - with open(sys.argv[-1], "w") as f: + with open(args.out, "w") as f: for tag in hex_common.tags: f.write( f"OP_ATTRIB({tag},ATTRIBS(" diff --git a/target/hexagon/gen_opcodes_def.py b/target/hexagon/gen_opcodes_def.py index 536f0eb68a..94a19ff412 100755 --- a/target/hexagon/gen_opcodes_def.py +++ b/target/hexagon/gen_opcodes_def.py @@ -21,15 +21,22 @@ import sys import re import string import hex_common +import argparse def main(): - hex_common.read_semantics_file(sys.argv[1]) + parser = argparse.ArgumentParser( + description="Emit opaque macro calls with instruction names" + ) + parser.add_argument("semantics", help="semantics file") + parser.add_argument("out", help="output file") + args = parser.parse_args() + hex_common.read_semantics_file(args.semantics) ## ## Generate a list of all the opcodes ## - with open(sys.argv[-1], "w") as f: + with open(args.out, "w") as f: for tag in hex_common.tags: f.write(f"OPCODE({tag}),\n") diff --git a/target/hexagon/gen_printinsn.py b/target/hexagon/gen_printinsn.py index 8bf4d0985c..d5f969960a 100755 --- a/target/hexagon/gen_printinsn.py +++ b/target/hexagon/gen_printinsn.py @@ -21,6 +21,7 @@ import sys import re import string import hex_common +import argparse ## @@ -96,11 +97,17 @@ def spacify(s): def main(): - hex_common.read_semantics_file(sys.argv[1]) + parser = argparse.ArgumentParser( + "Emit opaque macro calls with information for printing string representations of instrucions" + ) + parser.add_argument("semantics", help="semantics file") + parser.add_argument("out", help="output file") + args = parser.parse_args() + hex_common.read_semantics_file(args.semantics) immext_casere = re.compile(r"IMMEXT\(([A-Za-z])") - with open(sys.argv[-1], "w") as f: + with open(args.out, "w") as f: for tag in hex_common.tags: if not hex_common.behdict[tag]: continue diff --git a/target/hexagon/gen_tcg.h b/target/hexagon/gen_tcg.h index 3fc1f4e281..8a3b801287 100644 --- a/target/hexagon/gen_tcg.h +++ b/target/hexagon/gen_tcg.h @@ -1365,7 +1365,7 @@ do { \ uiV = uiV; \ tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], ctx->pkt->pc); \ - TCGv excp = tcg_constant_tl(HEX_EXCP_TRAP0); \ + TCGv excp = tcg_constant_tl(HEX_EVENT_TRAP0); \ gen_helper_raise_exception(tcg_env, excp); \ } while (0) #endif diff --git a/target/hexagon/gen_tcg_func_table.py b/target/hexagon/gen_tcg_func_table.py index 978ac1819b..299a39b1aa 100755 --- a/target/hexagon/gen_tcg_func_table.py +++ b/target/hexagon/gen_tcg_func_table.py @@ -21,15 +21,22 @@ import sys import re import string import hex_common +import argparse def main(): - hex_common.read_semantics_file(sys.argv[1]) + parser = argparse.ArgumentParser( + "Emit opaque macro calls with instruction semantics" + ) + parser.add_argument("semantics", help="semantics file") + parser.add_argument("out", help="output file") + args = parser.parse_args() + hex_common.read_semantics_file(args.semantics) hex_common.calculate_attribs() tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() - with open(sys.argv[-1], "w") as f: + with open(args.out, "w") as f: f.write("#ifndef HEXAGON_FUNC_TABLE_H\n") f.write("#define HEXAGON_FUNC_TABLE_H\n\n") diff --git a/target/hexagon/gen_tcg_funcs.py b/target/hexagon/gen_tcg_funcs.py index 05aa0a7855..c2ba91ddc0 100755 --- a/target/hexagon/gen_tcg_funcs.py +++ b/target/hexagon/gen_tcg_funcs.py @@ -108,15 +108,16 @@ def gen_def_tcg_func(f, tag, tagregs, tagimms): def main(): - is_idef_parser_enabled = hex_common.read_common_files() + args = hex_common.parse_common_args( + "Emit functions calling generated code implementing instruction semantics (helpers, idef-parser)" + ) tagregs = hex_common.get_tagregs() tagimms = hex_common.get_tagimms() - output_file = sys.argv[-1] - with open(output_file, "w") as f: + with open(args.out, "w") as f: f.write("#ifndef HEXAGON_TCG_FUNCS_H\n") f.write("#define HEXAGON_TCG_FUNCS_H\n\n") - if is_idef_parser_enabled: + if args.idef_parser: f.write('#include "idef-generated-emitter.h.inc"\n\n') for tag in hex_common.tags: diff --git a/target/hexagon/gen_trans_funcs.py b/target/hexagon/gen_trans_funcs.py index 30f0c73e0c..45da1b7b5d 100755 --- a/target/hexagon/gen_trans_funcs.py +++ b/target/hexagon/gen_trans_funcs.py @@ -24,6 +24,7 @@ import sys import textwrap import iset import hex_common +import argparse encs = { tag: "".join(reversed(iset.iset[tag]["enc"].replace(" ", ""))) @@ -136,8 +137,19 @@ def gen_trans_funcs(f): """)) -if __name__ == "__main__": - hex_common.read_semantics_file(sys.argv[1]) +def main(): + parser = argparse.ArgumentParser( + description="Emit trans_*() functions to be called by " \ + "instruction decoder" + ) + parser.add_argument("semantics", help="semantics file") + parser.add_argument("out", help="output file") + args = parser.parse_args() + hex_common.read_semantics_file(args.semantics) hex_common.init_registers() - with open(sys.argv[2], "w") as f: + with open(args.out, "w") as f: gen_trans_funcs(f) + + +if __name__ == "__main__": + main() diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index dbae6c570a..2c5e15cfcf 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -100,10 +100,6 @@ void gen_log_reg_write(DisasContext *ctx, int rnum, TCGv val) gen_masked_reg_write(val, hex_gpr[rnum], reg_mask); tcg_gen_mov_tl(get_result_gpr(ctx, rnum), val); - if (HEX_DEBUG) { - /* Do this so HELPER(debug_commit_end) will know */ - tcg_gen_movi_tl(hex_reg_written[rnum], 1); - } } static void gen_log_reg_write_pair(DisasContext *ctx, int rnum, TCGv_i64 val) @@ -151,9 +147,6 @@ void gen_log_pred_write(DisasContext *ctx, int pnum, TCGv val) } else { tcg_gen_and_tl(pred, pred, base_val); } - if (HEX_DEBUG) { - tcg_gen_ori_tl(ctx->pred_written, ctx->pred_written, 1 << pnum); - } set_bit(pnum, ctx->pregs_written); } diff --git a/target/hexagon/helper.h b/target/hexagon/helper.h index fa0ebaf7c8..f8baa599c8 100644 --- a/target/hexagon/helper.h +++ b/target/hexagon/helper.h @@ -19,9 +19,6 @@ #include "helper_protos_generated.h.inc" DEF_HELPER_FLAGS_2(raise_exception, TCG_CALL_NO_RETURN, noreturn, env, i32) -DEF_HELPER_1(debug_start_packet, void, env) -DEF_HELPER_FLAGS_3(debug_check_store_width, TCG_CALL_NO_WG, void, env, int, int) -DEF_HELPER_FLAGS_5(debug_commit_end, TCG_CALL_NO_WG, void, env, i32, int, int, int) DEF_HELPER_2(commit_store, void, env, int) DEF_HELPER_3(gather_store, void, env, i32, int) DEF_HELPER_1(commit_hvx_stores, void, env) diff --git a/target/hexagon/hex_common.py b/target/hexagon/hex_common.py index 15ed4980e4..758e5fd12d 100755 --- a/target/hexagon/hex_common.py +++ b/target/hexagon/hex_common.py @@ -21,6 +21,7 @@ import sys import re import string import textwrap +import argparse behdict = {} # tag ->behavior semdict = {} # tag -> semantics @@ -1181,22 +1182,20 @@ def helper_args(tag, regs, imms): return args -def read_common_files(): - read_semantics_file(sys.argv[1]) - read_overrides_file(sys.argv[2]) - read_overrides_file(sys.argv[3]) - ## Whether or not idef-parser is enabled is - ## determined by the number of arguments to - ## this script: - ## - ## 4 args. -> not enabled, - ## 5 args. -> idef-parser enabled. - ## - ## The 5:th arg. then holds a list of the successfully - ## parsed instructions. - is_idef_parser_enabled = len(sys.argv) > 5 - if is_idef_parser_enabled: - read_idef_parser_enabled_file(sys.argv[4]) +def parse_common_args(desc): + parser = argparse.ArgumentParser(desc) + parser.add_argument("semantics", help="semantics file") + parser.add_argument("overrides", help="overrides file") + parser.add_argument("overrides_vec", help="vector overrides file") + parser.add_argument("out", help="output file") + parser.add_argument("--idef-parser", + help="file of instructions translated by idef-parser") + args = parser.parse_args() + read_semantics_file(args.semantics) + read_overrides_file(args.overrides) + read_overrides_file(args.overrides_vec) + if args.idef_parser: + read_idef_parser_enabled_file(args.idef_parser) calculate_attribs() init_registers() - return is_idef_parser_enabled + return args diff --git a/target/hexagon/internal.h b/target/hexagon/internal.h index beb08cb7e3..32e96f00d9 100644 --- a/target/hexagon/internal.h +++ b/target/hexagon/internal.h @@ -20,17 +20,6 @@ #include "qemu/log.h" -/* - * Change HEX_DEBUG to 1 to turn on debugging output - */ -#define HEX_DEBUG 0 -#define HEX_DEBUG_LOG(...) \ - do { \ - if (HEX_DEBUG) { \ - qemu_log(__VA_ARGS__); \ - } \ - } while (0) - int hexagon_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int hexagon_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); int hexagon_hvx_gdb_read_register(CPUState *env, GByteArray *mem_buf, int n); diff --git a/target/hexagon/meson.build b/target/hexagon/meson.build index f1723778a6..bb4ebaae81 100644 --- a/target/hexagon/meson.build +++ b/target/hexagon/meson.build @@ -346,7 +346,7 @@ if idef_parser_enabled and 'hexagon-linux-user' in target_dirs # Setup input and dependencies for the next step, this depends on whether or # not idef-parser is enabled helper_dep = [semantics_generated, idef_generated_tcg_c, idef_generated_tcg] - helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, idef_generated_list] + helper_in = [semantics_generated, gen_tcg_h, gen_tcg_hvx_h, '--idef-parser', idef_generated_list] else # Setup input and dependencies for the next step, this depends on whether or # not idef-parser is enabled diff --git a/target/hexagon/mmvec/macros.h b/target/hexagon/mmvec/macros.h index 1ceb9453ee..bcd4a1e897 100644 --- a/target/hexagon/mmvec/macros.h +++ b/target/hexagon/mmvec/macros.h @@ -23,26 +23,26 @@ #include "mmvec/system_ext_mmvec.h" #ifndef QEMU_GENERATE -#define VdV (*(MMVector *)(VdV_void)) -#define VsV (*(MMVector *)(VsV_void)) -#define VuV (*(MMVector *)(VuV_void)) -#define VvV (*(MMVector *)(VvV_void)) -#define VwV (*(MMVector *)(VwV_void)) -#define VxV (*(MMVector *)(VxV_void)) -#define VyV (*(MMVector *)(VyV_void)) +#define VdV (*(MMVector *restrict)(VdV_void)) +#define VsV (*(MMVector *restrict)(VsV_void)) +#define VuV (*(MMVector *restrict)(VuV_void)) +#define VvV (*(MMVector *restrict)(VvV_void)) +#define VwV (*(MMVector *restrict)(VwV_void)) +#define VxV (*(MMVector *restrict)(VxV_void)) +#define VyV (*(MMVector *restrict)(VyV_void)) -#define VddV (*(MMVectorPair *)(VddV_void)) -#define VuuV (*(MMVectorPair *)(VuuV_void)) -#define VvvV (*(MMVectorPair *)(VvvV_void)) -#define VxxV (*(MMVectorPair *)(VxxV_void)) +#define VddV (*(MMVectorPair *restrict)(VddV_void)) +#define VuuV (*(MMVectorPair *restrict)(VuuV_void)) +#define VvvV (*(MMVectorPair *restrict)(VvvV_void)) +#define VxxV (*(MMVectorPair *restrict)(VxxV_void)) -#define QeV (*(MMQReg *)(QeV_void)) -#define QdV (*(MMQReg *)(QdV_void)) -#define QsV (*(MMQReg *)(QsV_void)) -#define QtV (*(MMQReg *)(QtV_void)) -#define QuV (*(MMQReg *)(QuV_void)) -#define QvV (*(MMQReg *)(QvV_void)) -#define QxV (*(MMQReg *)(QxV_void)) +#define QeV (*(MMQReg *restrict)(QeV_void)) +#define QdV (*(MMQReg *restrict)(QdV_void)) +#define QsV (*(MMQReg *restrict)(QsV_void)) +#define QtV (*(MMQReg *restrict)(QtV_void)) +#define QuV (*(MMQReg *restrict)(QuV_void)) +#define QvV (*(MMQReg *restrict)(QvV_void)) +#define QxV (*(MMQReg *restrict)(QxV_void)) #endif #define LOG_VTCM_BYTE(VA, MASK, VAL, IDX) \ diff --git a/target/hexagon/op_helper.c b/target/hexagon/op_helper.c index 90e7aaa097..01d1a1b1a7 100644 --- a/target/hexagon/op_helper.c +++ b/target/hexagon/op_helper.c @@ -54,9 +54,6 @@ G_NORETURN void HELPER(raise_exception)(CPUHexagonState *env, uint32_t excp) void log_store32(CPUHexagonState *env, target_ulong addr, target_ulong val, int width, int slot) { - HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx - ", %" PRId32 " [0x08%" PRIx32 "])\n", - width, addr, val, val); env->mem_log_stores[slot].va = addr; env->mem_log_stores[slot].width = width; env->mem_log_stores[slot].data32 = val; @@ -65,35 +62,11 @@ void log_store32(CPUHexagonState *env, target_ulong addr, void log_store64(CPUHexagonState *env, target_ulong addr, int64_t val, int width, int slot) { - HEX_DEBUG_LOG("log_store%d(0x" TARGET_FMT_lx - ", %" PRId64 " [0x016%" PRIx64 "])\n", - width, addr, val, val); env->mem_log_stores[slot].va = addr; env->mem_log_stores[slot].width = width; env->mem_log_stores[slot].data64 = val; } -/* Handy place to set a breakpoint */ -void HELPER(debug_start_packet)(CPUHexagonState *env) -{ - HEX_DEBUG_LOG("Start packet: pc = 0x" TARGET_FMT_lx "\n", - env->gpr[HEX_REG_PC]); - - for (int i = 0; i < TOTAL_PER_THREAD_REGS; i++) { - env->reg_written[i] = 0; - } -} - -/* Checks for bookkeeping errors between disassembly context and runtime */ -void HELPER(debug_check_store_width)(CPUHexagonState *env, int slot, int check) -{ - if (env->mem_log_stores[slot].width != check) { - HEX_DEBUG_LOG("ERROR: %d != %d\n", - env->mem_log_stores[slot].width, check); - g_assert_not_reached(); - } -} - static void commit_store(CPUHexagonState *env, int slot_num, uintptr_t ra) { uint8_t width = env->mem_log_stores[slot_num].width; @@ -173,91 +146,6 @@ void HELPER(commit_hvx_stores)(CPUHexagonState *env) } } -static void print_store(CPUHexagonState *env, int slot) -{ - if (!(env->slot_cancelled & (1 << slot))) { - uint8_t width = env->mem_log_stores[slot].width; - if (width == 1) { - uint32_t data = env->mem_log_stores[slot].data32 & 0xff; - HEX_DEBUG_LOG("\tmemb[0x" TARGET_FMT_lx "] = %" PRId32 - " (0x%02" PRIx32 ")\n", - env->mem_log_stores[slot].va, data, data); - } else if (width == 2) { - uint32_t data = env->mem_log_stores[slot].data32 & 0xffff; - HEX_DEBUG_LOG("\tmemh[0x" TARGET_FMT_lx "] = %" PRId32 - " (0x%04" PRIx32 ")\n", - env->mem_log_stores[slot].va, data, data); - } else if (width == 4) { - uint32_t data = env->mem_log_stores[slot].data32; - HEX_DEBUG_LOG("\tmemw[0x" TARGET_FMT_lx "] = %" PRId32 - " (0x%08" PRIx32 ")\n", - env->mem_log_stores[slot].va, data, data); - } else if (width == 8) { - HEX_DEBUG_LOG("\tmemd[0x" TARGET_FMT_lx "] = %" PRId64 - " (0x%016" PRIx64 ")\n", - env->mem_log_stores[slot].va, - env->mem_log_stores[slot].data64, - env->mem_log_stores[slot].data64); - } else { - HEX_DEBUG_LOG("\tBad store width %d\n", width); - g_assert_not_reached(); - } - } -} - -/* This function is a handy place to set a breakpoint */ -void HELPER(debug_commit_end)(CPUHexagonState *env, uint32_t this_PC, - int pred_written, int has_st0, int has_st1) -{ - bool reg_printed = false; - bool pred_printed = false; - int i; - - HEX_DEBUG_LOG("Packet committed: pc = 0x" TARGET_FMT_lx "\n", this_PC); - HEX_DEBUG_LOG("slot_cancelled = %d\n", env->slot_cancelled); - - for (i = 0; i < TOTAL_PER_THREAD_REGS; i++) { - if (env->reg_written[i]) { - if (!reg_printed) { - HEX_DEBUG_LOG("Regs written\n"); - reg_printed = true; - } - HEX_DEBUG_LOG("\tr%d = " TARGET_FMT_ld " (0x" TARGET_FMT_lx ")\n", - i, env->gpr[i], env->gpr[i]); - } - } - - for (i = 0; i < NUM_PREGS; i++) { - if (pred_written & (1 << i)) { - if (!pred_printed) { - HEX_DEBUG_LOG("Predicates written\n"); - pred_printed = true; - } - HEX_DEBUG_LOG("\tp%d = 0x" TARGET_FMT_lx "\n", - i, env->pred[i]); - } - } - - if (has_st0 || has_st1) { - HEX_DEBUG_LOG("Stores\n"); - if (has_st0) { - print_store(env, 0); - } - if (has_st1) { - print_store(env, 1); - } - } - - HEX_DEBUG_LOG("Next PC = " TARGET_FMT_lx "\n", env->gpr[HEX_REG_PC]); - HEX_DEBUG_LOG("Exec counters: pkt = " TARGET_FMT_lx - ", insn = " TARGET_FMT_lx - ", hvx = " TARGET_FMT_lx "\n", - env->gpr[HEX_REG_QEMU_PKT_CNT], - env->gpr[HEX_REG_QEMU_INSN_CNT], - env->gpr[HEX_REG_QEMU_HVX_CNT]); - -} - int32_t HELPER(fcircadd)(int32_t RxV, int32_t offset, int32_t M, int32_t CS) { uint32_t K_const = extract32(M, 24, 4); diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 4b1bee3c6d..562105705a 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -50,7 +50,6 @@ TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; TCGv hex_pred[NUM_PREGS]; TCGv hex_slot_cancelled; TCGv hex_new_value_usr; -TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; TCGv hex_store_addr[STORES_MAX]; TCGv hex_store_width[STORES_MAX]; TCGv hex_store_val32[STORES_MAX]; @@ -195,21 +194,6 @@ static void gen_exception_end_tb(DisasContext *ctx, int excp) } -#define PACKET_BUFFER_LEN 1028 -static void print_pkt(Packet *pkt) -{ - GString *buf = g_string_sized_new(PACKET_BUFFER_LEN); - snprint_a_pkt_debug(buf, pkt); - HEX_DEBUG_LOG("%s", buf->str); - g_string_free(buf, true); -} -#define HEX_DEBUG_PRINT_PKT(pkt) \ - do { \ - if (HEX_DEBUG) { \ - print_pkt(pkt); \ - } \ - } while (0) - static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, uint32_t words[]) { @@ -235,14 +219,6 @@ static int read_packet_words(CPUHexagonState *env, DisasContext *ctx, g_assert(ctx->base.num_insns == 1); } - HEX_DEBUG_LOG("decode_packet: pc = 0x%" VADDR_PRIx "\n", - ctx->base.pc_next); - HEX_DEBUG_LOG(" words = { "); - for (int i = 0; i < nwords; i++) { - HEX_DEBUG_LOG("0x%x, ", words[i]); - } - HEX_DEBUG_LOG("}\n"); - return nwords; } @@ -465,11 +441,6 @@ static void gen_start_packet(DisasContext *ctx) */ bitmap_zero(ctx->pregs_written, NUM_PREGS); - if (HEX_DEBUG) { - /* Handy place to set a breakpoint before the packet executes */ - gen_helper_debug_start_packet(tcg_env); - } - /* Initialize the runtime state for packet semantics */ if (need_slot_cancelled(pkt)) { tcg_gen_movi_tl(hex_slot_cancelled, 0); @@ -484,10 +455,6 @@ static void gen_start_packet(DisasContext *ctx) tcg_gen_movi_tl(hex_gpr[HEX_REG_PC], next_PC); } } - if (HEX_DEBUG) { - ctx->pred_written = tcg_temp_new(); - tcg_gen_movi_tl(ctx->pred_written, 0); - } /* Preload the predicated registers into get_result_gpr(ctx, i) */ if (ctx->need_commit && @@ -591,7 +558,7 @@ static void gen_insn(DisasContext *ctx) ctx->insn->generate(ctx); mark_store_width(ctx); } else { - gen_exception_end_tb(ctx, HEX_EXCP_INVALID_OPCODE); + gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_OPCODE); } } @@ -635,15 +602,6 @@ static void gen_pred_writes(DisasContext *ctx) } } -static void gen_check_store_width(DisasContext *ctx, int slot_num) -{ - if (HEX_DEBUG) { - TCGv slot = tcg_constant_tl(slot_num); - TCGv check = tcg_constant_tl(ctx->store_width[slot_num]); - gen_helper_debug_check_store_width(tcg_env, slot, check); - } -} - static bool slot_is_predicated(Packet *pkt, int slot_num) { for (int i = 0; i < pkt->num_insns; i++) { @@ -691,25 +649,21 @@ void process_store(DisasContext *ctx, int slot_num) */ switch (ctx->store_width[slot_num]) { case 1: - gen_check_store_width(ctx, slot_num); tcg_gen_qemu_st_tl(hex_store_val32[slot_num], hex_store_addr[slot_num], ctx->mem_idx, MO_UB); break; case 2: - gen_check_store_width(ctx, slot_num); tcg_gen_qemu_st_tl(hex_store_val32[slot_num], hex_store_addr[slot_num], ctx->mem_idx, MO_TEUW); break; case 4: - gen_check_store_width(ctx, slot_num); tcg_gen_qemu_st_tl(hex_store_val32[slot_num], hex_store_addr[slot_num], ctx->mem_idx, MO_TEUL); break; case 8: - gen_check_store_width(ctx, slot_num); tcg_gen_qemu_st_i64(hex_store_val64[slot_num], hex_store_addr[slot_num], ctx->mem_idx, MO_TEUQ); @@ -937,16 +891,6 @@ static void gen_commit_packet(DisasContext *ctx) gen_commit_hvx(ctx); } update_exec_counters(ctx); - if (HEX_DEBUG) { - TCGv has_st0 = - tcg_constant_tl(pkt->pkt_has_store_s0 && !pkt->pkt_has_dczeroa); - TCGv has_st1 = - tcg_constant_tl(pkt->pkt_has_store_s1 && !pkt->pkt_has_dczeroa); - - /* Handy place to set a breakpoint at the end of execution */ - gen_helper_debug_commit_end(tcg_env, tcg_constant_tl(ctx->pkt->pc), - ctx->pred_written, has_st0, has_st1); - } if (pkt->vhist_insn != NULL) { ctx->pre_commit = false; @@ -968,14 +912,13 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) nwords = read_packet_words(env, ctx, words); if (!nwords) { - gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); + gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET); return; } ctx->pkt = &pkt; if (decode_packet(ctx, nwords, words, &pkt, false) > 0) { pkt.pc = ctx->base.pc_next; - HEX_DEBUG_PRINT_PKT(&pkt); gen_start_packet(ctx); for (i = 0; i < pkt.num_insns; i++) { ctx->insn = &pkt.insn[i]; @@ -984,7 +927,7 @@ static void decode_and_translate_packet(CPUHexagonState *env, DisasContext *ctx) gen_commit_packet(ctx); ctx->base.pc_next += pkt.encod_pkt_size_in_bytes; } else { - gen_exception_end_tb(ctx, HEX_EXCP_INVALID_PACKET); + gen_exception_end_tb(ctx, HEX_CAUSE_INVALID_PACKET); } } @@ -1093,7 +1036,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int *max_insns, } #define NAME_LEN 64 -static char reg_written_names[TOTAL_PER_THREAD_REGS][NAME_LEN]; static char store_addr_names[STORES_MAX][NAME_LEN]; static char store_width_names[STORES_MAX][NAME_LEN]; static char store_val32_names[STORES_MAX][NAME_LEN]; @@ -1112,14 +1054,6 @@ void hexagon_translate_init(void) hex_gpr[i] = tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, gpr[i]), hexagon_regnames[i]); - - if (HEX_DEBUG) { - snprintf(reg_written_names[i], NAME_LEN, "reg_written_%s", - hexagon_regnames[i]); - hex_reg_written[i] = tcg_global_mem_new(tcg_env, - offsetof(CPUHexagonState, reg_written[i]), - reg_written_names[i]); - } } hex_new_value_usr = tcg_global_mem_new(tcg_env, offsetof(CPUHexagonState, new_value_usr), "new_value_usr"); diff --git a/target/hexagon/translate.h b/target/hexagon/translate.h index 00cc2bcd63..d251e2233f 100644 --- a/target/hexagon/translate.h +++ b/target/hexagon/translate.h @@ -73,7 +73,6 @@ typedef struct DisasContext { bool has_hvx_overlap; TCGv new_value[TOTAL_PER_THREAD_REGS]; TCGv new_pred_value[NUM_PREGS]; - TCGv pred_written; TCGv branch_taken; TCGv dczero_addr; } DisasContext; @@ -271,7 +270,6 @@ extern TCGv hex_gpr[TOTAL_PER_THREAD_REGS]; extern TCGv hex_pred[NUM_PREGS]; extern TCGv hex_slot_cancelled; extern TCGv hex_new_value_usr; -extern TCGv hex_reg_written[TOTAL_PER_THREAD_REGS]; extern TCGv hex_store_addr[STORES_MAX]; extern TCGv hex_store_width[STORES_MAX]; extern TCGv hex_store_val32[STORES_MAX]; |