diff options
| -rw-r--r-- | target/loongarch/cpu.c | 2 | ||||
| -rw-r--r-- | target/loongarch/insn_trans/trans_lsx.c.inc | 39 | ||||
| -rw-r--r-- | target/loongarch/op_helper.c | 6 |
3 files changed, 31 insertions, 16 deletions
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index c0afc21b2f..ad93ecac92 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -187,10 +187,10 @@ static void loongarch_cpu_do_interrupt(CPUState *cs) case EXCCODE_IPE: case EXCCODE_FPD: case EXCCODE_FPE: - case EXCCODE_BCE: case EXCCODE_SXD: env->CSR_BADV = env->pc; QEMU_FALLTHROUGH; + case EXCCODE_BCE: case EXCCODE_ADEM: case EXCCODE_PIL: case EXCCODE_PIS: diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc index 0be2b5a3a8..68779daff6 100644 --- a/target/loongarch/insn_trans/trans_lsx.c.inc +++ b/target/loongarch/insn_trans/trans_lsx.c.inc @@ -3963,106 +3963,119 @@ TRANS(vsetallnez_d, gen_cv, gen_helper_vsetallnez_d) static bool trans_vinsgr2vr_b(DisasContext *ctx, arg_vr_i *a) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; - tcg_gen_st8_i64(cpu_gpr[a->rj], cpu_env, + tcg_gen_st8_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.B(a->imm))); return true; } static bool trans_vinsgr2vr_h(DisasContext *ctx, arg_vr_i *a) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; - tcg_gen_st16_i64(cpu_gpr[a->rj], cpu_env, + tcg_gen_st16_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.H(a->imm))); return true; } static bool trans_vinsgr2vr_w(DisasContext *ctx, arg_vr_i *a) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; - tcg_gen_st32_i64(cpu_gpr[a->rj], cpu_env, + tcg_gen_st32_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.W(a->imm))); return true; } static bool trans_vinsgr2vr_d(DisasContext *ctx, arg_vr_i *a) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; - tcg_gen_st_i64(cpu_gpr[a->rj], cpu_env, + tcg_gen_st_i64(src, cpu_env, offsetof(CPULoongArchState, fpr[a->vd].vreg.D(a->imm))); return true; } static bool trans_vpickve2gr_b(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld8s_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld8s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm))); return true; } static bool trans_vpickve2gr_h(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld16s_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld16s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm))); return true; } static bool trans_vpickve2gr_w(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld32s_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld32s_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm))); return true; } static bool trans_vpickve2gr_d(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); return true; } static bool trans_vpickve2gr_bu(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld8u_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld8u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.B(a->imm))); return true; } static bool trans_vpickve2gr_hu(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld16u_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld16u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.H(a->imm))); return true; } static bool trans_vpickve2gr_wu(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld32u_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld32u_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.W(a->imm))); return true; } static bool trans_vpickve2gr_du(DisasContext *ctx, arg_rv_i *a) { + TCGv dst = gpr_dst(ctx, a->rd, EXT_NONE); CHECK_SXE; - tcg_gen_ld_i64(cpu_gpr[a->rd], cpu_env, + tcg_gen_ld_i64(dst, cpu_env, offsetof(CPULoongArchState, fpr[a->vj].vreg.D(a->imm))); return true; } static bool gvec_dup(DisasContext *ctx, arg_vr *a, MemOp mop) { + TCGv src = gpr_src(ctx, a->rj, EXT_NONE); CHECK_SXE; tcg_gen_gvec_dup_i64(mop, vec_full_offset(a->vd), - 16, ctx->vl/8, cpu_gpr[a->rj]); + 16, ctx->vl/8, src); return true; } diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c index 568c071601..60335a05e2 100644 --- a/target/loongarch/op_helper.c +++ b/target/loongarch/op_helper.c @@ -49,14 +49,16 @@ target_ulong helper_bitswap(target_ulong v) void helper_asrtle_d(CPULoongArchState *env, target_ulong rj, target_ulong rk) { if (rj > rk) { - do_raise_exception(env, EXCCODE_BCE, 0); + env->CSR_BADV = rj; + do_raise_exception(env, EXCCODE_BCE, GETPC()); } } void helper_asrtgt_d(CPULoongArchState *env, target_ulong rj, target_ulong rk) { if (rj <= rk) { - do_raise_exception(env, EXCCODE_BCE, 0); + env->CSR_BADV = rj; + do_raise_exception(env, EXCCODE_BCE, GETPC()); } } |