diff options
| -rw-r--r-- | target/mips/translate.c | 2 | ||||
| -rw-r--r-- | target/mips/translate.h | 2 |
2 files changed, 3 insertions, 1 deletions
diff --git a/target/mips/translate.c b/target/mips/translate.c index 256e2956c4..d4316c15d1 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -12349,7 +12349,7 @@ static void gen_flt3_arith(DisasContext *ctx, uint32_t opc, } } -static void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) +void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel) { TCGv t0; diff --git a/target/mips/translate.h b/target/mips/translate.h index e4f2f26de8..2b3c7a69ec 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -148,6 +148,8 @@ void gen_op_addr_add(DisasContext *ctx, TCGv ret, TCGv arg0, TCGv arg1); bool gen_lsa(DisasContext *ctx, int rd, int rt, int rs, int sa); bool gen_dlsa(DisasContext *ctx, int rd, int rt, int rs, int sa); +void gen_rdhwr(DisasContext *ctx, int rt, int rd, int sel); + extern TCGv cpu_gpr[32], cpu_PC; #if defined(TARGET_MIPS64) extern TCGv_i64 cpu_gpr_hi[32]; |