diff options
56 files changed, 1415 insertions, 1433 deletions
diff --git a/Makefile b/Makefile index d835bb92e7..af31e8981f 100644 --- a/Makefile +++ b/Makefile @@ -232,10 +232,18 @@ KEYCODEMAP_GEN = $(SRC_PATH)/ui/keycodemapdb/tools/keymap-gen KEYCODEMAP_CSV = $(SRC_PATH)/ui/keycodemapdb/data/keymaps.csv KEYCODEMAP_FILES = \ + ui/input-keymap-atset1-to-qcode.c \ ui/input-keymap-linux-to-qcode.c \ ui/input-keymap-qcode-to-qnum.c \ ui/input-keymap-qnum-to-qcode.c \ ui/input-keymap-qcode-to-linux.c \ + ui/input-keymap-usb-to-qcode.c \ + ui/input-keymap-win32-to-qcode.c \ + ui/input-keymap-x11-to-qcode.c \ + ui/input-keymap-xorgevdev-to-qcode.c \ + ui/input-keymap-xorgkbd-to-qcode.c \ + ui/input-keymap-xorgxquartz-to-qcode.c \ + ui/input-keymap-xorgxwin-to-qcode.c \ $(NULL) GENERATED_FILES += $(KEYCODEMAP_FILES) diff --git a/Makefile.objs b/Makefile.objs index 669d8d684d..323ef12384 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -150,6 +150,7 @@ trace-events-subdirs += hw/i386/xen trace-events-subdirs += hw/9pfs trace-events-subdirs += hw/ppc trace-events-subdirs += hw/pci +trace-events-subdirs += hw/pci-host trace-events-subdirs += hw/s390x trace-events-subdirs += hw/vfio trace-events-subdirs += hw/acpi diff --git a/configure b/configure index 044c6fafe2..96dee6572c 100755 --- a/configure +++ b/configure @@ -5668,6 +5668,12 @@ if test "$gtkabi" = "2.0"; then echo "WARNING: future releases. Please switch to using GTK 3.0" fi +if test "$sdlabi" = "1.2"; then + echo + echo "WARNING: Use of SDL 1.2 is deprecated and will be removed in" + echo "WARNING: future releases. Please switch to using SDL 2.0" +fi + if test "$supported_cpu" = "no"; then echo echo "WARNING: SUPPORT FOR THIS HOST CPU WILL GO AWAY IN FUTURE RELEASES!" diff --git a/default-configs/sparc64-softmmu.mak b/default-configs/sparc64-softmmu.mak index 3e177bbd7b..52edafe547 100644 --- a/default-configs/sparc64-softmmu.mak +++ b/default-configs/sparc64-softmmu.mak @@ -11,7 +11,8 @@ CONFIG_PCKBD=y CONFIG_FDC=y CONFIG_IDE_ISA=y CONFIG_IDE_CMD646=y -CONFIG_PCI_APB=y +CONFIG_PCI_SABRE=y +CONFIG_SIMBA=y CONFIG_SUNHME=y CONFIG_MC146818RTC=y CONFIG_ISA_TESTDEV=y diff --git a/hw/arm/virt.c b/hw/arm/virt.c index a4537af400..b334c82eda 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -1404,7 +1404,7 @@ static void machvirt_init(MachineState *machine) "secure-memory", &error_abort); } - object_property_set_bool(cpuobj, true, "realized", NULL); + object_property_set_bool(cpuobj, true, "realized", &error_fatal); object_unref(cpuobj); } fdt_add_timer_nodes(vms); diff --git a/hw/display/pl110.c b/hw/display/pl110.c index 8c7dcc6f0a..cf68457fd1 100644 --- a/hw/display/pl110.c +++ b/hw/display/pl110.c @@ -12,6 +12,7 @@ #include "ui/console.h" #include "framebuffer.h" #include "ui/pixel_ops.h" +#include "qemu/timer.h" #include "qemu/log.h" #define PL110_CR_EN 0x001 @@ -19,6 +20,8 @@ #define PL110_CR_BEBO 0x200 #define PL110_CR_BEPO 0x400 #define PL110_CR_PWR 0x800 +#define PL110_IE_NB 0x004 +#define PL110_IE_VC 0x008 enum pl110_bppmode { @@ -50,6 +53,7 @@ typedef struct PL110State { MemoryRegion iomem; MemoryRegionSection fbsection; QemuConsole *con; + QEMUTimer *vblank_timer; int version; uint32_t timing[4]; @@ -320,7 +324,24 @@ static void pl110_resize(PL110State *s, int width, int height) /* Update interrupts. */ static void pl110_update(PL110State *s) { - /* TODO: Implement interrupts. */ + /* Raise IRQ if enabled and any status bit is 1 */ + if (s->int_status & s->int_mask) { + qemu_irq_raise(s->irq); + } else { + qemu_irq_lower(s->irq); + } +} + +static void pl110_vblank_interrupt(void *opaque) +{ + PL110State *s = opaque; + + /* Fire the vertical compare and next base IRQs and re-arm */ + s->int_status |= (PL110_IE_NB | PL110_IE_VC); + timer_mod(s->vblank_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + NANOSECONDS_PER_SECOND / 60); + pl110_update(s); } static uint64_t pl110_read(void *opaque, hwaddr offset, @@ -429,6 +450,11 @@ static void pl110_write(void *opaque, hwaddr offset, s->bpp = (val >> 1) & 7; if (pl110_enabled(s)) { qemu_console_resize(s->con, s->cols, s->rows); + timer_mod(s->vblank_timer, + qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) + + NANOSECONDS_PER_SECOND / 60); + } else { + timer_del(s->vblank_timer); } break; case 10: /* LCDICR */ @@ -474,6 +500,8 @@ static void pl110_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->iomem, OBJECT(s), &pl110_ops, s, "pl110", 0x1000); sysbus_init_mmio(sbd, &s->iomem); sysbus_init_irq(sbd, &s->irq); + s->vblank_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + pl110_vblank_interrupt, s); qdev_init_gpio_in(dev, pl110_mux_ctrl_set, 1); s->con = graphic_console_init(dev, 0, &pl110_gfx_ops, s); } diff --git a/hw/display/vga.c b/hw/display/vga.c index a0412000a5..6e78a4e156 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -1279,6 +1279,9 @@ static void vga_draw_text(VGACommonState *s, int full_update) cx_min = width; cx_max = -1; for(cx = 0; cx < width; cx++) { + if (src + sizeof(uint16_t) > s->vram_ptr + s->vram_size) { + break; + } ch_attr = *(uint16_t *)src; if (full_update || ch_attr != *ch_attr_ptr || src == cursor_ptr) { if (cx < cx_min) diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index d701e49ff9..724bc9fa61 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -93,6 +93,7 @@ void gic_update(GICState *s) best_irq = 1023; for (irq = 0; irq < s->num_irq; irq++) { if (GIC_TEST_ENABLED(irq, cm) && gic_test_pending(s, irq, cm) && + (!GIC_TEST_ACTIVE(irq, cm)) && (irq < GIC_INTERNAL || GIC_TARGET(irq) & cm)) { if (GIC_GET_PRIORITY(irq, cpu) < best_prio) { best_prio = GIC_GET_PRIORITY(irq, cpu); @@ -255,7 +256,8 @@ static int gic_get_group_priority(GICState *s, int cpu, int irq) if (gic_has_groups(s) && !(s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) && GIC_TEST_GROUP(irq, (1 << cpu))) { - bpr = s->abpr[cpu]; + bpr = s->abpr[cpu] - 1; + assert(bpr >= 0); } else { bpr = s->bpr[cpu]; } @@ -503,6 +505,11 @@ static void gic_set_cpu_control(GICState *s, int cpu, uint32_t value, static uint8_t gic_get_running_priority(GICState *s, int cpu, MemTxAttrs attrs) { + if ((s->revision != REV_11MPCORE) && (s->running_priority[cpu] > 0xff)) { + /* Idle priority */ + return 0xff; + } + if (s->security_extn && !attrs.secure) { if (s->running_priority[cpu] & 0x80) { /* Running priority in upper half of range: return the Non-secure @@ -1205,8 +1212,13 @@ static MemTxResult gic_cpu_read(GICState *s, int cpu, int offset, break; case 0x08: /* Binary Point */ if (s->security_extn && !attrs.secure) { - /* BPR is banked. Non-secure copy stored in ABPR. */ - *data = s->abpr[cpu]; + if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { + /* NS view of BPR when CBPR is 1 */ + *data = MIN(s->bpr[cpu] + 1, 7); + } else { + /* BPR is banked. Non-secure copy stored in ABPR. */ + *data = s->abpr[cpu]; + } } else { *data = s->bpr[cpu]; } @@ -1279,7 +1291,12 @@ static MemTxResult gic_cpu_write(GICState *s, int cpu, int offset, break; case 0x08: /* Binary Point */ if (s->security_extn && !attrs.secure) { - s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); + if (s->cpu_ctlr[cpu] & GICC_CTLR_CBPR) { + /* WI when CBPR is 1 */ + return MEMTX_OK; + } else { + s->abpr[cpu] = MAX(value & 0x7, GIC_MIN_ABPR); + } } else { s->bpr[cpu] = MAX(value & 0x7, GIC_MIN_BPR); } diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 94659ee256..d6f9cb3692 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -106,6 +106,15 @@ static void grlib_irqmp_check_irqs(IRQMPState *state) } } +static void grlib_irqmp_ack_mask(IRQMPState *state, uint32_t mask) +{ + /* Clear registers */ + state->pending &= ~mask; + state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */ + + grlib_irqmp_check_irqs(state); +} + void grlib_irqmp_ack(DeviceState *dev, int intno) { IRQMP *irqmp = GRLIB_IRQMP(dev); @@ -120,11 +129,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno) trace_grlib_irqmp_ack(intno); - /* Clear registers */ - state->pending &= ~mask; - state->force[0] &= ~mask; /* Only CPU 0 (No SMP support) */ - - grlib_irqmp_check_irqs(state); + grlib_irqmp_ack_mask(state, mask); } void grlib_irqmp_set_irq(void *opaque, int irq, int level) @@ -251,7 +256,7 @@ static void grlib_irqmp_write(void *opaque, hwaddr addr, case CLEAR_OFFSET: value &= ~1; /* clean up the value */ - state->pending &= ~value; + grlib_irqmp_ack_mask(state, value); return; case MP_STATUS_OFFSET: diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index 4fb48f62ba..9506f9b69f 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -595,19 +595,16 @@ static void imx_eth_do_tx(IMXFECState *s, uint32_t index) static void imx_eth_enable_rx(IMXFECState *s, bool flush) { IMXFECBufDesc bd; - bool rx_ring_full; imx_fec_read_bd(&bd, s->rx_descriptor); - rx_ring_full = !(bd.flags & ENET_BD_E); + s->regs[ENET_RDAR] = (bd.flags & ENET_BD_E) ? ENET_RDAR_RDAR : 0; - if (rx_ring_full) { + if (!s->regs[ENET_RDAR]) { FEC_PRINTF("RX buffer full\n"); } else if (flush) { qemu_flush_queued_packets(qemu_get_queue(s->nic)); } - - s->regs[ENET_RDAR] = rx_ring_full ? 0 : ENET_RDAR_RDAR; } static void imx_eth_reset(DeviceState *d) @@ -866,7 +863,6 @@ static void imx_eth_write(void *opaque, hwaddr offset, uint64_t value, case ENET_RDAR: if (s->regs[ENET_ECR] & ENET_ECR_ETHEREN) { if (!s->regs[index]) { - s->regs[index] = ENET_RDAR_RDAR; imx_eth_enable_rx(s, true); } } else { diff --git a/hw/pci-bridge/Makefile.objs b/hw/pci-bridge/Makefile.objs index 1b05023662..47065f87d9 100644 --- a/hw/pci-bridge/Makefile.objs +++ b/hw/pci-bridge/Makefile.objs @@ -6,3 +6,5 @@ common-obj-$(CONFIG_IOH3420) += ioh3420.o common-obj-$(CONFIG_I82801B11) += i82801b11.o # NewWorld PowerMac common-obj-$(CONFIG_DEC_PCI) += dec.o +# Sun4u +common-obj-$(CONFIG_SIMBA) += simba.o diff --git a/hw/pci-bridge/simba.c b/hw/pci-bridge/simba.c new file mode 100644 index 0000000000..dea4c8c5e7 --- /dev/null +++ b/hw/pci-bridge/simba.c @@ -0,0 +1,101 @@ +/* + * QEMU Simba PCI bridge + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2018 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "hw/pci/pci_bridge.h" +#include "hw/pci/pci_bus.h" +#include "hw/pci-bridge/simba.h" + +/* + * Chipset docs: + * APB: "Advanced PCI Bridge (APB) User's Manual", + * http://www.sun.com/processors/manuals/805-1251.pdf + */ + +static void simba_pci_bridge_realize(PCIDevice *dev, Error **errp) +{ + /* + * command register: + * According to PCI bridge spec, after reset + * bus master bit is off + * memory space enable bit is off + * According to manual (805-1251.pdf). + * the reset value should be zero unless the boot pin is tied high + * (which is true) and thus it should be PCI_COMMAND_MEMORY. + */ + SimbaPCIBridge *br = SIMBA_PCI_BRIDGE(dev); + + pci_bridge_initfn(dev, TYPE_PCI_BUS); + + pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); + pci_set_word(dev->config + PCI_STATUS, + PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | + PCI_STATUS_DEVSEL_MEDIUM); + + /* Allow 32-bit IO addresses */ + pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32); + pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32); + pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); + pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); + + pci_bridge_update_mappings(PCI_BRIDGE(br)); +} + +static void simba_pci_bridge_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->realize = simba_pci_bridge_realize; + k->exit = pci_bridge_exitfn; + k->vendor_id = PCI_VENDOR_ID_SUN; + k->device_id = PCI_DEVICE_ID_SUN_SIMBA; + k->revision = 0x11; + k->config_write = pci_bridge_write_config; + k->is_bridge = 1; + set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); + dc->reset = pci_bridge_reset; + dc->vmsd = &vmstate_pci_device; +} + +static const TypeInfo simba_pci_bridge_info = { + .name = TYPE_SIMBA_PCI_BRIDGE, + .parent = TYPE_PCI_BRIDGE, + .class_init = simba_pci_bridge_class_init, + .instance_size = sizeof(SimbaPCIBridge), + .interfaces = (InterfaceInfo[]) { + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { }, + }, +}; + +static void simba_register_types(void) +{ + type_register_static(&simba_pci_bridge_info); +} + +type_init(simba_register_types) diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs index 9c7909cf44..4b69f737b5 100644 --- a/hw/pci-host/Makefile.objs +++ b/hw/pci-host/Makefile.objs @@ -11,7 +11,7 @@ common-obj-$(CONFIG_PPCE500_PCI) += ppce500.o # ARM devices common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o -common-obj-$(CONFIG_PCI_APB) += apb.o +common-obj-$(CONFIG_PCI_SABRE) += sabre.o common-obj-$(CONFIG_FULONG) += bonito.o common-obj-$(CONFIG_PCI_PIIX) += piix.o common-obj-$(CONFIG_PCI_Q35) += q35.o diff --git a/hw/pci-host/apb.c b/hw/pci-host/sabre.c index ec676f94b6..2268a41dd9 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/sabre.c @@ -1,8 +1,9 @@ /* - * QEMU Ultrasparc APB PCI host + * QEMU Ultrasparc Sabre PCI host (PBM) * * Copyright (c) 2006 Fabrice Bellard * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2018 Mark Cave-Ayland * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,39 +24,24 @@ * THE SOFTWARE. */ -/* XXX This file and most of its contents are somewhat misnamed. The - Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is - the secondary PCI bridge. */ - #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" -#include "hw/pci-host/apb.h" +#include "hw/pci-bridge/simba.h" +#include "hw/pci-host/sabre.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/log.h" - -/* debug APB */ -//#define DEBUG_APB - -#ifdef DEBUG_APB -#define APB_DPRINTF(fmt, ...) \ -do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) -#else -#define APB_DPRINTF(fmt, ...) -#endif +#include "trace.h" /* * Chipset docs: * PBM: "UltraSPARC IIi User's Manual", * http://www.sun.com/processors/manuals/805-0087.pdf - * - * APB: "Advanced PCI Bridge (APB) User's Manual", - * http://www.sun.com/processors/manuals/805-1251.pdf */ #define PBM_PCI_IMR_MASK 0x7fffffff @@ -72,22 +58,20 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define NO_IRQ_REQUEST (MAX_IVEC + 1) -static inline void pbm_set_request(APBState *s, unsigned int irq_num) +static inline void sabre_set_request(SabreState *s, unsigned int irq_num) { - APB_DPRINTF("%s: request irq %d\n", __func__, irq_num); - + trace_sabre_set_request(irq_num); s->irq_request = irq_num; qemu_set_irq(s->ivec_irqs[irq_num], 1); } -static inline void pbm_check_irqs(APBState *s) +static inline void sabre_check_irqs(SabreState *s) { - unsigned int i; /* Previous request is not acknowledged, resubmit */ if (s->irq_request != NO_IRQ_REQUEST) { - pbm_set_request(s, s->irq_request); + sabre_set_request(s, s->irq_request); return; } /* no request pending */ @@ -97,7 +81,7 @@ static inline void pbm_check_irqs(APBState *s) for (i = 0; i < 32; i++) { if (s->pci_irq_in & (1ULL << i)) { if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { - pbm_set_request(s, i); + sabre_set_request(s, i); return; } } @@ -105,33 +89,33 @@ static inline void pbm_check_irqs(APBState *s) for (i = 32; i < 64; i++) { if (s->pci_irq_in & (1ULL << i)) { if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { - pbm_set_request(s, i); + sabre_set_request(s, i); break; } } } } -static inline void pbm_clear_request(APBState *s, unsigned int irq_num) +static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) { - APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); + trace_sabre_clear_request(irq_num); qemu_set_irq(s->ivec_irqs[irq_num], 0); s->irq_request = NO_IRQ_REQUEST; } -static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) +static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) { IOMMUState *is = opaque; return &is->iommu_as; } -static void apb_config_writel (void *opaque, hwaddr addr, +static void sabre_config_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - APBState *s = opaque; + SabreState *s = opaque; - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val); + trace_sabre_config_write(addr, val); switch (addr & 0xffff) { case 0x30 ... 0x4f: /* DMA error registers */ @@ -143,9 +127,9 @@ static void apb_config_writel (void *opaque, hwaddr addr, s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK; s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) { - pbm_clear_request(s, ino); + sabre_clear_request(s, ino); } - pbm_check_irqs(s); + sabre_check_irqs(s); } break; case 0x1000 ... 0x107f: /* OBIO interrupt control */ @@ -155,17 +139,17 @@ static void apb_config_writel (void *opaque, hwaddr addr, s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; if ((s->irq_request == (ino | 0x20)) && !(val & ~PBM_PCI_IMR_MASK)) { - pbm_clear_request(s, ino | 0x20); + sabre_clear_request(s, ino | 0x20); } - pbm_check_irqs(s); + sabre_check_irqs(s); } break; case 0x1400 ... 0x14ff: /* PCI interrupt clear */ if (addr & 4) { unsigned int ino = (addr & 0xff) >> 5; if ((s->irq_request / 4) == ino) { - pbm_clear_request(s, s->irq_request); - pbm_check_irqs(s); + sabre_clear_request(s, s->irq_request); + sabre_check_irqs(s); } } break; @@ -173,8 +157,8 @@ static void apb_config_writel (void *opaque, hwaddr addr, if (addr & 4) { unsigned int ino = ((addr & 0xff) >> 3) | 0x20; if (s->irq_request == ino) { - pbm_clear_request(s, ino); - pbm_check_irqs(s); + sabre_clear_request(s, ino); + sabre_check_irqs(s); } } break; @@ -204,10 +188,10 @@ static void apb_config_writel (void *opaque, hwaddr addr, } } -static uint64_t apb_config_readl (void *opaque, +static uint64_t sabre_config_read(void *opaque, hwaddr addr, unsigned size) { - APBState *s = opaque; + SabreState *s = opaque; uint32_t val; switch (addr & 0xffff) { @@ -255,47 +239,47 @@ static uint64_t apb_config_readl (void *opaque, val = 0; break; } - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val); + trace_sabre_config_read(addr, val); return val; } -static const MemoryRegionOps apb_config_ops = { - .read = apb_config_readl, - .write = apb_config_writel, +static const MemoryRegionOps sabre_config_ops = { + .read = sabre_config_read, + .write = sabre_config_write, .endianness = DEVICE_BIG_ENDIAN, }; -static void apb_pci_config_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void sabre_pci_config_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { - APBState *s = opaque; + SabreState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val); + trace_sabre_pci_config_write(addr, val); pci_data_write(phb->bus, addr, val, size); } -static uint64_t apb_pci_config_read(void *opaque, hwaddr addr, - unsigned size) +static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, + unsigned size) { uint32_t ret; - APBState *s = opaque; + SabreState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); ret = pci_data_read(phb->bus, addr, size); - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret); + trace_sabre_pci_config_read(addr, ret); return ret; } -/* The APB host has an IRQ line for each IRQ line of each slot. */ -static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num) +/* The sabre host has an IRQ line for each IRQ line of each slot. */ +static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) { /* Return the irq as swizzled by the PBM */ return irq_num; } -static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num) +static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) { /* The on-board devices have fixed (legacy) OBIO intnos */ switch (PCI_SLOT(pci_dev->devfn)) { @@ -313,22 +297,23 @@ static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num) return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; } -static int pci_pbmB_map_irq(PCIDevice *pci_dev, int irq_num) +static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) { return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; } -static void pci_apb_set_irq(void *opaque, int irq_num, int level) +static void pci_sabre_set_irq(void *opaque, int irq_num, int level) { - APBState *s = opaque; + SabreState *s = opaque; + + trace_sabre_pci_set_irq(irq_num, level); - APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level); /* PCI IRQ map onto the first 32 INO. */ if (irq_num < 32) { if (level) { s->pci_irq_in |= 1ULL << irq_num; if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { - pbm_set_request(s, irq_num); + sabre_set_request(s, irq_num); } } else { s->pci_irq_in &= ~(1ULL << irq_num); @@ -336,11 +321,11 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level) } else { /* OBIO IRQ map onto the next 32 INO. */ if (level) { - APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level); + trace_sabre_pci_set_obio_irq(irq_num, level); s->pci_irq_in |= 1ULL << irq_num; if ((s->irq_request == NO_IRQ_REQUEST) && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { - pbm_set_request(s, irq_num); + sabre_set_request(s, irq_num); } } else { s->pci_irq_in &= ~(1ULL << irq_num); @@ -348,38 +333,9 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level) } } -static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) +static void sabre_reset(DeviceState *d) { - /* - * command register: - * According to PCI bridge spec, after reset - * bus master bit is off - * memory space enable bit is off - * According to manual (805-1251.pdf). - * the reset value should be zero unless the boot pin is tied high - * (which is true) and thus it should be PCI_COMMAND_MEMORY. - */ - PBMPCIBridge *br = PBM_PCI_BRIDGE(dev); - - pci_bridge_initfn(dev, TYPE_PCI_BUS); - - pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); - pci_set_word(dev->config + PCI_STATUS, - PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | - PCI_STATUS_DEVSEL_MEDIUM); - - /* Allow 32-bit IO addresses */ - pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32); - pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32); - pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); - pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); - - pci_bridge_update_mappings(PCI_BRIDGE(br)); -} - -static void pci_pbm_reset(DeviceState *d) -{ - APBState *s = APB_DEVICE(d); + SabreState *s = SABRE_DEVICE(d); PCIDevice *pci_dev; unsigned int i; uint16_t cmd; @@ -410,19 +366,19 @@ static void pci_pbm_reset(DeviceState *d) } static const MemoryRegionOps pci_config_ops = { - .read = apb_pci_config_read, - .write = apb_pci_config_write, + .read = sabre_pci_config_read, + .write = sabre_pci_config_write, .endianness = DEVICE_LITTLE_ENDIAN, }; -static void pci_pbm_realize(DeviceState *dev, Error **errp) +static void sabre_realize(DeviceState *dev, Error **errp) { - APBState *s = APB_DEVICE(dev); + SabreState *s = SABRE_DEVICE(dev); PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(s); PCIDevice *pci_dev; - /* apb_config */ + /* sabre_config */ sysbus_mmio_map(sbd, 0, s->special_base); /* PCI configuration space */ sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); @@ -434,35 +390,35 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp) &s->pci_mmio); phb->bus = pci_register_root_bus(dev, "pci", - pci_apb_set_irq, pci_apb_map_irq, s, + pci_sabre_set_irq, pci_sabre_map_irq, s, &s->pci_mmio, &s->pci_ioport, 0, 32, TYPE_PCI_BUS); - pci_create_simple(phb->bus, 0, "pbm-pci"); + pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); - /* APB IOMMU */ - memory_region_add_subregion_overlap(&s->apb_config, 0x200, + /* IOMMU */ + memory_region_add_subregion_overlap(&s->sabre_config, 0x200, sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1); - pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, s->iommu); + pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); /* APB secondary busses */ pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, - TYPE_PBM_PCI_BRIDGE); + TYPE_SIMBA_PCI_BRIDGE); s->bridgeB = PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(s->bridgeB, "pciB", pci_pbmB_map_irq); + pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq); qdev_init_nofail(&pci_dev->qdev); pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, - TYPE_PBM_PCI_BRIDGE); + TYPE_SIMBA_PCI_BRIDGE); s->bridgeA = PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbmA_map_irq); + pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq); qdev_init_nofail(&pci_dev->qdev); } -static void pci_pbm_init(Object *obj) +static void sabre_init(Object *obj) { - APBState *s = APB_DEVICE(obj); + SabreState *s = SABRE_DEVICE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); unsigned int i; @@ -475,7 +431,7 @@ static void pci_pbm_init(Object *obj) for (i = 0; i < 32; i++) { s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; } - qdev_init_gpio_in_named(DEVICE(s), pci_apb_set_irq, "pbm-irq", MAX_IVEC); + qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC); qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC); s->irq_request = NO_IRQ_REQUEST; s->pci_irq_in = 0ULL; @@ -486,25 +442,26 @@ static void pci_pbm_init(Object *obj) qdev_prop_allow_set_link_before_realize, 0, NULL); - /* apb_config */ - memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s, - "apb-config", 0x10000); + /* sabre_config */ + memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s, + "sabre-config", 0x10000); /* at region 0 */ - sysbus_init_mmio(sbd, &s->apb_config); + sysbus_init_mmio(sbd, &s->sabre_config); memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, - "apb-pci-config", 0x1000000); + "sabre-pci-config", 0x1000000); /* at region 1 */ sysbus_init_mmio(sbd, &s->pci_config); /* pci_ioport */ - memory_region_init(&s->pci_ioport, OBJECT(s), "apb-pci-ioport", 0x1000000); + memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", + 0x1000000); /* at region 2 */ sysbus_init_mmio(sbd, &s->pci_ioport); } -static void pbm_pci_host_realize(PCIDevice *d, Error **errp) +static void sabre_pci_realize(PCIDevice *d, Error **errp) { pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); @@ -513,12 +470,12 @@ static void pbm_pci_host_realize(PCIDevice *d, Error **errp) PCI_STATUS_DEVSEL_MEDIUM); } -static void pbm_pci_host_class_init(ObjectClass *klass, void *data) +static void sabre_pci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); - k->realize = pbm_pci_host_realize; + k->realize = sabre_pci_realize; k->vendor_id = PCI_VENDOR_ID_SUN; k->device_id = PCI_DEVICE_ID_SUN_SABRE; k->class_id = PCI_CLASS_BRIDGE_HOST; @@ -529,74 +486,45 @@ static void pbm_pci_host_class_init(ObjectClass *klass, void *data) dc->user_creatable = false; } -static const TypeInfo pbm_pci_host_info = { - .name = "pbm-pci", +static const TypeInfo sabre_pci_info = { + .name = TYPE_SABRE_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PCIDevice), - .class_init = pbm_pci_host_class_init, + .instance_size = sizeof(SabrePCIState), + .class_init = sabre_pci_class_init, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, }, }; -static Property pbm_pci_host_properties[] = { - DEFINE_PROP_UINT64("special-base", APBState, special_base, 0), - DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0), +static Property sabre_properties[] = { + DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), + DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), DEFINE_PROP_END_OF_LIST(), }; -static void pbm_host_class_init(ObjectClass *klass, void *data) +static void sabre_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - dc->realize = pci_pbm_realize; - dc->reset = pci_pbm_reset; - dc->props = pbm_pci_host_properties; + dc->realize = sabre_realize; + dc->reset = sabre_reset; + dc->props = sabre_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } -static const TypeInfo pbm_host_info = { - .name = TYPE_APB, +static const TypeInfo sabre_info = { + .name = TYPE_SABRE, .parent = TYPE_PCI_HOST_BRIDGE, - .instance_size = sizeof(APBState), - .instance_init = pci_pbm_init, - .class_init = pbm_host_class_init, -}; - -static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = apb_pci_bridge_realize; - k->exit = pci_bridge_exitfn; - k->vendor_id = PCI_VENDOR_ID_SUN; - k->device_id = PCI_DEVICE_ID_SUN_SIMBA; - k->revision = 0x11; - k->config_write = pci_bridge_write_config; - k->is_bridge = 1; - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->reset = pci_bridge_reset; - dc->vmsd = &vmstate_pci_device; -} - -static const TypeInfo pbm_pci_bridge_info = { - .name = TYPE_PBM_PCI_BRIDGE, - .parent = TYPE_PCI_BRIDGE, - .class_init = pbm_pci_bridge_class_init, - .instance_size = sizeof(PBMPCIBridge), - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, + .instance_size = sizeof(SabreState), + .instance_init = sabre_init, + .class_init = sabre_class_init, }; -static void pbm_register_types(void) +static void sabre_register_types(void) { - type_register_static(&pbm_host_info); - type_register_static(&pbm_pci_host_info); - type_register_static(&pbm_pci_bridge_info); + type_register_static(&sabre_info); + type_register_static(&sabre_pci_info); } -type_init(pbm_register_types) +type_init(sabre_register_types) diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events new file mode 100644 index 0000000000..32dfc84692 --- /dev/null +++ b/hw/pci-host/trace-events @@ -0,0 +1,11 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/pci-host/sabre.c +sabre_set_request(int irq_num) "request irq %d" +sabre_clear_request(int irq_num) "clear request irq %d" +sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 +sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 +sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 +sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 +sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d" +sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d" diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index f9264d3be5..fac7fa5c72 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1388,6 +1388,7 @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) } if (s->dma_mr) { + s->dma_as = &s->sysbus_dma_as; address_space_init(s->dma_as, s->dma_mr, "sdhci-dma"); } else { /* use system_memory() if property "dma" not set */ diff --git a/hw/sparc64/sparc64.c b/hw/sparc64/sparc64.c index 95a06f00b2..408388945e 100644 --- a/hw/sparc64/sparc64.c +++ b/hw/sparc64/sparc64.c @@ -28,25 +28,9 @@ #include "hw/char/serial.h" #include "hw/sparc/sparc64.h" #include "qemu/timer.h" +#include "trace.h" -//#define DEBUG_IRQ -//#define DEBUG_TIMER - -#ifdef DEBUG_IRQ -#define CPUIRQ_DPRINTF(fmt, ...) \ - do { printf("CPUIRQ: " fmt , ## __VA_ARGS__); } while (0) -#else -#define CPUIRQ_DPRINTF(fmt, ...) -#endif - -#ifdef DEBUG_TIMER -#define TIMER_DPRINTF(fmt, ...) \ - do { printf("TIMER: " fmt , ## __VA_ARGS__); } while (0) -#else -#define TIMER_DPRINTF(fmt, ...) -#endif - #define TICK_MAX 0x7fffffffffffffffULL void cpu_check_irqs(CPUSPARCState *env) @@ -73,8 +57,7 @@ void cpu_check_irqs(CPUSPARCState *env) is (2 << psrpil). */ if (pil < (2 << env->psrpil)) { if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - CPUIRQ_DPRINTF("Reset CPU IRQ (current interrupt %x)\n", - env->interrupt_index); + trace_sparc64_cpu_check_irqs_reset_irq(env->interrupt_index); env->interrupt_index = 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -92,22 +75,21 @@ void cpu_check_irqs(CPUSPARCState *env) if (unlikely(env->tl > 0 && cpu_tsptr(env)->tt > new_interrupt && ((cpu_tsptr(env)->tt & 0x1f0) == TT_EXTINT))) { - CPUIRQ_DPRINTF("Not setting CPU IRQ: TL=%d " - "current %x >= pending %x\n", - env->tl, cpu_tsptr(env)->tt, new_interrupt); + trace_sparc64_cpu_check_irqs_noset_irq(env->tl, + cpu_tsptr(env)->tt, + new_interrupt); } else if (old_interrupt != new_interrupt) { env->interrupt_index = new_interrupt; - CPUIRQ_DPRINTF("Set CPU IRQ %d old=%x new=%x\n", i, - old_interrupt, new_interrupt); + trace_sparc64_cpu_check_irqs_set_irq(i, old_interrupt, + new_interrupt); cpu_interrupt(cs, CPU_INTERRUPT_HARD); } break; } } } else if (cs->interrupt_request & CPU_INTERRUPT_HARD) { - CPUIRQ_DPRINTF("Interrupts disabled, pil=%08x pil_in=%08x softint=%08x " - "current interrupt %x\n", - pil, env->pil_in, env->softint, env->interrupt_index); + trace_sparc64_cpu_check_irqs_disabled(pil, env->pil_in, env->softint, + env->interrupt_index); env->interrupt_index = 0; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); } @@ -131,7 +113,7 @@ void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level) if (level) { if (!(env->ivec_status & 0x20)) { - CPUIRQ_DPRINTF("Raise IVEC IRQ %d\n", irq); + trace_sparc64_cpu_ivec_raise_irq(irq); cs = CPU(cpu); cs->halted = 0; env->interrupt_index = TT_IVEC; @@ -143,7 +125,7 @@ void sparc64_cpu_set_ivec_irq(void *opaque, int irq, int level) } } else { if (env->ivec_status & 0x20) { - CPUIRQ_DPRINTF("Lower IVEC IRQ %d\n", irq); + trace_sparc64_cpu_ivec_lower_irq(irq); cs = CPU(cpu); env->ivec_status &= ~0x20; cpu_reset_interrupt(cs, CPU_INTERRUPT_HARD); @@ -216,10 +198,10 @@ static void tick_irq(void *opaque) CPUTimer *timer = env->tick; if (timer->disabled) { - CPUIRQ_DPRINTF("tick_irq: softint disabled\n"); + trace_sparc64_cpu_tick_irq_disabled(); return; } else { - CPUIRQ_DPRINTF("tick: fire\n"); + trace_sparc64_cpu_tick_irq_fire(); } env->softint |= SOFTINT_TIMER; @@ -234,10 +216,10 @@ static void stick_irq(void *opaque) CPUTimer *timer = env->stick; if (timer->disabled) { - CPUIRQ_DPRINTF("stick_irq: softint disabled\n"); + trace_sparc64_cpu_stick_irq_disabled(); return; } else { - CPUIRQ_DPRINTF("stick: fire\n"); + trace_sparc64_cpu_stick_irq_fire(); } env->softint |= SOFTINT_STIMER; @@ -252,10 +234,10 @@ static void hstick_irq(void *opaque) CPUTimer *timer = env->hstick; if (timer->disabled) { - CPUIRQ_DPRINTF("hstick_irq: softint disabled\n"); + trace_sparc64_cpu_hstick_irq_disabled(); return; } else { - CPUIRQ_DPRINTF("hstick: fire\n"); + trace_sparc64_cpu_hstick_irq_fire(); } env->softint |= SOFTINT_STIMER; @@ -280,9 +262,9 @@ void cpu_tick_set_count(CPUTimer *timer, uint64_t count) int64_t vm_clock_offset = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - cpu_to_timer_ticks(real_count, timer->frequency); - TIMER_DPRINTF("%s set_count count=0x%016lx (npt %s) p=%p\n", - timer->name, real_count, - timer->npt ? "disabled" : "enabled", timer); + trace_sparc64_cpu_tick_set_count(timer->name, real_count, + timer->npt ? "disabled" : "enabled", + timer); timer->npt = npt_bit ? 1 : 0; timer->clock_offset = vm_clock_offset; @@ -294,9 +276,9 @@ uint64_t cpu_tick_get_count(CPUTimer *timer) qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - timer->clock_offset, timer->frequency); - TIMER_DPRINTF("%s get_count count=0x%016lx (npt %s) p=%p\n", - timer->name, real_count, - timer->npt ? "disabled" : "enabled", timer); + trace_sparc64_cpu_tick_get_count(timer->name, real_count, + timer->npt ? "disabled" : "enabled", + timer); if (timer->npt) { real_count |= timer->npt_mask; @@ -319,18 +301,19 @@ void cpu_tick_set_limit(CPUTimer *timer, uint64_t limit) expires = now + 1; } - TIMER_DPRINTF("%s set_limit limit=0x%016lx (%s) p=%p " - "called with limit=0x%016lx at 0x%016lx (delta=0x%016lx)\n", - timer->name, real_limit, - timer->disabled ? "disabled" : "enabled", - timer, limit, - timer_to_cpu_ticks(now - timer->clock_offset, - timer->frequency), - timer_to_cpu_ticks(expires - now, timer->frequency)); + trace_sparc64_cpu_tick_set_limit(timer->name, real_limit, + timer->disabled ? "disabled" : "enabled", + timer, limit, + timer_to_cpu_ticks( + now - timer->clock_offset, + timer->frequency + ), + timer_to_cpu_ticks( + expires - now, timer->frequency + )); if (!real_limit) { - TIMER_DPRINTF("%s set_limit limit=ZERO - not starting timer\n", - timer->name); + trace_sparc64_cpu_tick_set_limit_zero(timer->name); timer_del(timer->qtimer); } else if (timer->disabled) { timer_del(timer->qtimer); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index ec45ec2801..a23cb26b0d 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -30,7 +30,7 @@ #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" #include "hw/pci/pci_host.h" -#include "hw/pci-host/apb.h" +#include "hw/pci-host/sabre.h" #include "hw/i386/pc.h" #include "hw/char/serial.h" #include "hw/timer/m48t59.h" @@ -55,9 +55,9 @@ #define CMDLINE_ADDR 0x003ff000 #define PROM_SIZE_MAX (4 * 1024 * 1024) #define PROM_VADDR 0x000ffd00000ULL -#define APB_SPECIAL_BASE 0x1fe00000000ULL -#define APB_MEM_BASE 0x1ff00000000ULL -#define APB_PCI_IO_BASE (APB_SPECIAL_BASE + 0x02000000ULL) +#define PBM_SPECIAL_BASE 0x1fe00000000ULL +#define PBM_MEM_BASE 0x1ff00000000ULL +#define PBM_PCI_IO_BASE (PBM_SPECIAL_BASE + 0x02000000ULL) #define PROM_FILENAME "openbios-sparc64" #define NVRAM_SIZE 0x2000 #define MAX_IDE_BUS 2 @@ -205,6 +205,59 @@ typedef struct ResetData { uint64_t prom_addr; } ResetData; +#define TYPE_SUN4U_POWER "power" +#define SUN4U_POWER(obj) OBJECT_CHECK(PowerDevice, (obj), TYPE_SUN4U_POWER) + +typedef struct PowerDevice { + SysBusDevice parent_obj; + + MemoryRegion power_mmio; +} PowerDevice; + +/* Power */ +static void power_mem_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + /* According to a real Ultra 5, bit 24 controls the power */ + if (val & 0x1000000) { + qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); + } +} + +static const MemoryRegionOps power_mem_ops = { + .write = power_mem_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4, + }, +}; + +static void power_realize(DeviceState *dev, Error **errp) +{ + PowerDevice *d = SUN4U_POWER(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + memory_region_init_io(&d->power_mmio, OBJECT(dev), &power_mem_ops, d, + "power", sizeof(uint32_t)); + + sysbus_init_mmio(sbd, &d->power_mmio); +} + +static void power_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = power_realize; +} + +static const TypeInfo power_info = { + .name = TYPE_SUN4U_POWER, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PowerDevice), + .class_init = power_class_init, +}; + static void ebus_isa_irq_handler(void *opaque, int n, int level) { EbusState *s = EBUS(opaque); @@ -221,6 +274,7 @@ static void ebus_isa_irq_handler(void *opaque, int n, int level) static void ebus_realize(PCIDevice *pci_dev, Error **errp) { EbusState *s = EBUS(pci_dev); + SysBusDevice *sbd; DeviceState *dev; qemu_irq *isa_irq; DriveInfo *fd[MAX_FD]; @@ -270,6 +324,13 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp) qdev_prop_set_uint32(dev, "dma", -1); qdev_init_nofail(dev); + /* Power */ + dev = qdev_create(NULL, TYPE_SUN4U_POWER); + qdev_init_nofail(dev); + sbd = SYS_BUS_DEVICE(dev); + memory_region_add_subregion(pci_address_space_io(pci_dev), 0x7240, + sysbus_mmio_get_region(sbd, 0)); + /* PCI */ pci_dev->config[0x04] = 0x06; // command = bus master, pci mem pci_dev->config[0x05] = 0x00; @@ -282,7 +343,7 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp) 0, 0x1000000); pci_register_bar(pci_dev, 0, PCI_BASE_ADDRESS_SPACE_MEMORY, &s->bar0); memory_region_init_alias(&s->bar1, OBJECT(s), "bar1", get_system_io(), - 0, 0x4000); + 0, 0x8000); pci_register_bar(pci_dev, 1, PCI_BASE_ADDRESS_SPACE_IO, &s->bar1); } @@ -465,7 +526,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, Nvram *nvram; unsigned int i; uint64_t initrd_addr, initrd_size, kernel_addr, kernel_size, kernel_entry; - APBState *apb; + SabreState *sabre; PCIBus *pci_bus, *pci_busA, *pci_busB; PCIDevice *ebus, *pci_dev; SysBusDevice *s; @@ -488,24 +549,25 @@ static void sun4uv_init(MemoryRegion *address_space_mem, prom_init(hwdef->prom_addr, bios_name); - /* Init APB (PCI host bridge) */ - apb = APB_DEVICE(qdev_create(NULL, TYPE_APB)); - qdev_prop_set_uint64(DEVICE(apb), "special-base", APB_SPECIAL_BASE); - qdev_prop_set_uint64(DEVICE(apb), "mem-base", APB_MEM_BASE); - object_property_set_link(OBJECT(apb), OBJECT(iommu), "iommu", &error_abort); - qdev_init_nofail(DEVICE(apb)); + /* Init sabre (PCI host bridge) */ + sabre = SABRE_DEVICE(qdev_create(NULL, TYPE_SABRE)); + qdev_prop_set_uint64(DEVICE(sabre), "special-base", PBM_SPECIAL_BASE); + qdev_prop_set_uint64(DEVICE(sabre), "mem-base", PBM_MEM_BASE); + object_property_set_link(OBJECT(sabre), OBJECT(iommu), "iommu", + &error_abort); + qdev_init_nofail(DEVICE(sabre)); /* Wire up PCI interrupts to CPU */ for (i = 0; i < IVEC_MAX; i++) { - qdev_connect_gpio_out_named(DEVICE(apb), "ivec-irq", i, + qdev_connect_gpio_out_named(DEVICE(sabre), "ivec-irq", i, qdev_get_gpio_in_named(DEVICE(cpu), "ivec-irq", i)); } - pci_bus = PCI_HOST_BRIDGE(apb)->bus; - pci_busA = pci_bridge_get_sec_bus(apb->bridgeA); - pci_busB = pci_bridge_get_sec_bus(apb->bridgeB); + pci_bus = PCI_HOST_BRIDGE(sabre)->bus; + pci_busA = pci_bridge_get_sec_bus(sabre->bridgeA); + pci_busB = pci_bridge_get_sec_bus(sabre->bridgeB); - /* Only in-built Simba PBMs can exist on the root bus, slot 0 on busA is + /* Only in-built Simba APBs can exist on the root bus, slot 0 on busA is reserved (leaving no slots free after on-board devices) however slots 0-3 are free on busB */ pci_bus->slot_reserved_mask = 0xfffffffc; @@ -517,17 +579,17 @@ static void sun4uv_init(MemoryRegion *address_space_mem, hwdef->console_serial_base); qdev_init_nofail(DEVICE(ebus)); - /* Wire up "well-known" ISA IRQs to APB legacy obio IRQs */ + /* Wire up "well-known" ISA IRQs to PBM legacy obio IRQs */ qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 7, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_LPT_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_LPT_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 6, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_FDD_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_FDD_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 1, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_KBD_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_KBD_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 12, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_MSE_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_MSE_IRQ)); qdev_connect_gpio_out_named(DEVICE(ebus), "isa-irq", 4, - qdev_get_gpio_in_named(DEVICE(apb), "pbm-irq", OBIO_SER_IRQ)); + qdev_get_gpio_in_named(DEVICE(sabre), "pbm-irq", OBIO_SER_IRQ)); pci_dev = pci_create_simple(pci_busA, PCI_DEVFN(2, 0), "VGA"); @@ -693,6 +755,7 @@ static const TypeInfo sun4v_type = { static void sun4u_register_types(void) { + type_register_static(&power_info); type_register_static(&ebus_info); type_register_static(&prom_info); type_register_static(&ram_info); diff --git a/hw/sparc64/trace-events b/hw/sparc64/trace-events index 2ee2d75f70..ce597a6e9d 100644 --- a/hw/sparc64/trace-events +++ b/hw/sparc64/trace-events @@ -7,3 +7,21 @@ ebus_isa_irq_handler(int n, int level) "Set ISA IRQ %d level %d" sun4u_iommu_mem_read(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d" sun4u_iommu_mem_write(uint64_t addr, uint64_t val, int size) "addr: 0x%"PRIx64" val: 0x%"PRIx64" size: %d" sun4u_iommu_translate(uint64_t addr, uint64_t trans_addr, uint64_t tte) "xlate 0x%"PRIx64" => pa 0x%"PRIx64" tte: 0x%"PRIx64 + +# hw/sparc64/sparc64.c +sparc64_cpu_check_irqs_reset_irq(int intno) "Reset CPU IRQ (current interrupt 0x%x)" +sparc64_cpu_check_irqs_noset_irq(uint32_t tl, uint32_t tt, int intno) "Not setting CPU IRQ: TL=%d current 0x%x >= pending 0x%x" +sparc64_cpu_check_irqs_set_irq(unsigned int i, int old, int new) "Set CPU IRQ %d old=0x%x new=0x%x" +sparc64_cpu_check_irqs_disabled(uint32_t pil, uint32_t pil_in, uint32_t softint, int intno) "Interrupts disabled, pil=0x%08x pil_in=0x%08x softint=0x%08x current interrupt 0x%x" +sparc64_cpu_ivec_raise_irq(int irq) "Raise IVEC IRQ %d" +sparc64_cpu_ivec_lower_irq(int irq) "Lower IVEC IRQ %d" +sparc64_cpu_tick_irq_disabled(void) "tick_irq: softint disabled" +sparc64_cpu_tick_irq_fire(void) "tick_irq: fire" +sparc64_cpu_stick_irq_disabled(void) "stick_irq: softint disabled" +sparc64_cpu_stick_irq_fire(void) "stick_irq: fire" +sparc64_cpu_hstick_irq_disabled(void) "hstick_irq: softint disabled" +sparc64_cpu_hstick_irq_fire(void) "hstick_irq: fire" +sparc64_cpu_tick_set_count(const char *name, uint64_t real_count, const char *npt, void *p) "%s set_count count=0x%"PRIx64" (npt %s) p=%p" +sparc64_cpu_tick_get_count(const char *name, uint64_t real_count, const char *npt, void *p) "%s get_count count=0x%"PRIx64" (npt %s) p=%p" +sparc64_cpu_tick_set_limit(const char *name, uint64_t real_limit, const char *dis, void *p, uint64_t limit, uint64_t t, uint64_t dt) "%s set_limit limit=0x%"PRIx64 " (%s) p=%p called with limit=0x%"PRIx64" at 0x%"PRIx64" (delta=0x%"PRIx64")" +sparc64_cpu_tick_set_limit_zero(const char *name) "%s set_limit limit=ZERO - not starting timer" diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 85c5d0cb92..8af36ca3d4 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -210,6 +210,9 @@ #define SNOOP_NONE 0xEE #define SNOOP_STRIPING 0 +#define MIN_NUM_BUSSES 1 +#define MAX_NUM_BUSSES 2 + static inline int num_effective_busses(XilinxSPIPS *s) { return (s->regs[R_LQSPI_CFG] & LQSPI_CFG_SEP_BUS && @@ -573,7 +576,7 @@ static void xilinx_spips_flush_txfifo(XilinxSPIPS *s) for (;;) { int i; uint8_t tx = 0; - uint8_t tx_rx[num_effective_busses(s)]; + uint8_t tx_rx[MAX_NUM_BUSSES] = { 0 }; uint8_t dummy_cycles = 0; uint8_t addr_length; @@ -1221,6 +1224,19 @@ static void xilinx_spips_realize(DeviceState *dev, Error **errp) DB_PRINT_L(0, "realized spips\n"); + if (s->num_busses > MAX_NUM_BUSSES) { + error_setg(errp, + "requested number of SPI busses %u exceeds maximum %d", + s->num_busses, MAX_NUM_BUSSES); + return; + } + if (s->num_busses < MIN_NUM_BUSSES) { + error_setg(errp, + "requested number of SPI busses %u is below minimum %d", + s->num_busses, MIN_NUM_BUSSES); + return; + } + s->spi = g_new(SSIBus *, s->num_busses); for (i = 0; i < s->num_busses; ++i) { char bus_name[16]; diff --git a/include/hw/pci-bridge/simba.h b/include/hw/pci-bridge/simba.h new file mode 100644 index 0000000000..fac56ab1cf --- /dev/null +++ b/include/hw/pci-bridge/simba.h @@ -0,0 +1,38 @@ +/* + * QEMU Simba PCI bridge + * + * Copyright (c) 2006 Fabrice Bellard + * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2017 Mark Cave-Ayland + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/pci/pci_bridge.h" + + +typedef struct SimbaPCIBridge { + /*< private >*/ + PCIBridge parent_obj; +} SimbaPCIBridge; + +#define TYPE_SIMBA_PCI_BRIDGE "pbm-bridge" +#define SIMBA_PCI_BRIDGE(obj) \ + OBJECT_CHECK(SimbaPCIBridge, (obj), TYPE_SIMBA_PCI_BRIDGE) diff --git a/include/hw/pci-host/apb.h b/include/hw/pci-host/sabre.h index 604d899b1e..0f2ccc01c6 100644 --- a/include/hw/pci-host/apb.h +++ b/include/hw/pci-host/sabre.h @@ -14,17 +14,20 @@ #define OBIO_MSE_IRQ 0x2a #define OBIO_SER_IRQ 0x2b -#define TYPE_APB "pbm" +typedef struct SabrePCIState { + PCIDevice parent_obj; +} SabrePCIState; -#define APB_DEVICE(obj) \ - OBJECT_CHECK(APBState, (obj), TYPE_APB) +#define TYPE_SABRE_PCI_DEVICE "sabre-pci" +#define SABRE_PCI_DEVICE(obj) \ + OBJECT_CHECK(SabrePCIState, (obj), TYPE_SABRE_PCI_DEVICE) -typedef struct APBState { +typedef struct SabreState { PCIHostState parent_obj; hwaddr special_base; hwaddr mem_base; - MemoryRegion apb_config; + MemoryRegion sabre_config; MemoryRegion pci_config; MemoryRegion pci_mmio; MemoryRegion pci_ioport; @@ -40,15 +43,10 @@ typedef struct APBState { unsigned int irq_request; uint32_t reset_control; unsigned int nr_resets; -} APBState; +} SabreState; -typedef struct PBMPCIBridge { - /*< private >*/ - PCIBridge parent_obj; -} PBMPCIBridge; - -#define TYPE_PBM_PCI_BRIDGE "pbm-bridge" -#define PBM_PCI_BRIDGE(obj) \ - OBJECT_CHECK(PBMPCIBridge, (obj), TYPE_PBM_PCI_BRIDGE) +#define TYPE_SABRE "sabre" +#define SABRE_DEVICE(obj) \ + OBJECT_CHECK(SabreState, (obj), TYPE_SABRE) #endif diff --git a/include/hw/sd/sdhci.h b/include/hw/sd/sdhci.h index cb37182536..1cf70f8c23 100644 --- a/include/hw/sd/sdhci.h +++ b/include/hw/sd/sdhci.h @@ -41,6 +41,7 @@ typedef struct SDHCIState { /*< public >*/ SDBus sdbus; MemoryRegion iomem; + AddressSpace sysbus_dma_as; AddressSpace *dma_as; MemoryRegion *dma_mr; diff --git a/include/migration/vmstate.h b/include/migration/vmstate.h index 88b55df5ae..8c3889433c 100644 --- a/include/migration/vmstate.h +++ b/include/migration/vmstate.h @@ -905,6 +905,9 @@ extern const VMStateInfo vmstate_info_qtailq; #define VMSTATE_UINT32_ARRAY(_f, _s, _n) \ VMSTATE_UINT32_ARRAY_V(_f, _s, _n, 0) +#define VMSTATE_UINT32_SUB_ARRAY(_f, _s, _start, _num) \ + VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_uint32, uint32_t) + #define VMSTATE_UINT32_2DARRAY(_f, _s, _n1, _n2) \ VMSTATE_UINT32_2DARRAY_V(_f, _s, _n1, _n2, 0) @@ -914,6 +917,9 @@ extern const VMStateInfo vmstate_info_qtailq; #define VMSTATE_UINT64_ARRAY(_f, _s, _n) \ VMSTATE_UINT64_ARRAY_V(_f, _s, _n, 0) +#define VMSTATE_UINT64_SUB_ARRAY(_f, _s, _start, _num) \ + VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_uint64, uint64_t) + #define VMSTATE_UINT64_2DARRAY(_f, _s, _n1, _n2) \ VMSTATE_UINT64_2DARRAY_V(_f, _s, _n1, _n2, 0) @@ -932,9 +938,6 @@ extern const VMStateInfo vmstate_info_qtailq; #define VMSTATE_INT32_ARRAY(_f, _s, _n) \ VMSTATE_INT32_ARRAY_V(_f, _s, _n, 0) -#define VMSTATE_UINT32_SUB_ARRAY(_f, _s, _start, _num) \ - VMSTATE_SUB_ARRAY(_f, _s, _start, _num, 0, vmstate_info_uint32, uint32_t) - #define VMSTATE_INT64_ARRAY_V(_f, _s, _n, _v) \ VMSTATE_ARRAY(_f, _s, _n, _v, vmstate_info_int64, int64_t) diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index 31612caf10..1c925309e3 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -112,6 +112,7 @@ extern const char *keyboard_layout; extern int win2k_install_hack; extern int alt_grab; extern int ctrl_grab; +extern int no_frame; extern int smp_cpus; extern unsigned int max_cpus; extern int cursor_hide; diff --git a/include/ui/console.h b/include/ui/console.h index 580dfc57ee..7b35778444 100644 --- a/include/ui/console.h +++ b/include/ui/console.h @@ -436,7 +436,7 @@ void surface_gl_setup_viewport(QemuGLShader *gls, /* sdl.c */ #ifdef CONFIG_SDL void sdl_display_early_init(int opengl); -void sdl_display_init(DisplayState *ds, int full_screen, int no_frame); +void sdl_display_init(DisplayState *ds, int full_screen); #else static inline void sdl_display_early_init(int opengl) { @@ -444,8 +444,7 @@ static inline void sdl_display_early_init(int opengl) error_report("SDL support is disabled"); abort(); } -static inline void sdl_display_init(DisplayState *ds, int full_screen, - int no_frame) +static inline void sdl_display_init(DisplayState *ds, int full_screen) { /* This must never be called if CONFIG_SDL is disabled */ error_report("SDL support is disabled"); diff --git a/include/ui/input.h b/include/ui/input.h index 5cc76d6e41..05aab2db5c 100644 --- a/include/ui/input.h +++ b/include/ui/input.h @@ -68,6 +68,9 @@ void qemu_input_check_mode_change(void); void qemu_add_mouse_mode_change_notifier(Notifier *notify); void qemu_remove_mouse_mode_change_notifier(Notifier *notify); +extern const guint qemu_input_map_atset1_to_qcode_len; +extern const guint16 qemu_input_map_atset1_to_qcode[]; + extern const guint qemu_input_map_linux_to_qcode_len; extern const guint16 qemu_input_map_linux_to_qcode[]; @@ -80,4 +83,25 @@ extern const guint16 qemu_input_map_qnum_to_qcode[]; extern const guint qemu_input_map_qcode_to_linux_len; extern const guint16 qemu_input_map_qcode_to_linux[]; +extern const guint qemu_input_map_usb_to_qcode_len; +extern const guint16 qemu_input_map_usb_to_qcode[]; + +extern const guint qemu_input_map_win32_to_qcode_len; +extern const guint16 qemu_input_map_win32_to_qcode[]; + +extern const guint qemu_input_map_x11_to_qcode_len; +extern const guint16 qemu_input_map_x11_to_qcode[]; + +extern const guint qemu_input_map_xorgevdev_to_qcode_len; +extern const guint16 qemu_input_map_xorgevdev_to_qcode[]; + +extern const guint qemu_input_map_xorgkbd_to_qcode_len; +extern const guint16 qemu_input_map_xorgkbd_to_qcode[]; + +extern const guint qemu_input_map_xorgxquartz_to_qcode_len; +extern const guint16 qemu_input_map_xorgxquartz_to_qcode[]; + +extern const guint qemu_input_map_xorgxwin_to_qcode_len; +extern const guint16 qemu_input_map_xorgxwin_to_qcode[]; + #endif /* INPUT_H */ diff --git a/linux-user/signal.c b/linux-user/signal.c index f85f0dd780..5321f9e795 100644 --- a/linux-user/signal.c +++ b/linux-user/signal.c @@ -1487,12 +1487,13 @@ static int target_setup_sigframe(struct target_rt_sigframe *sf, } for (i = 0; i < 32; i++) { + uint64_t *q = aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __put_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2 + 1]); - __put_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2]); + __put_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); + __put_user(q[1], &aux->fpsimd.vregs[i * 2]); #else - __put_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2]); - __put_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2 + 1]); + __put_user(q[0], &aux->fpsimd.vregs[i * 2]); + __put_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); #endif } __put_user(vfp_get_fpsr(env), &aux->fpsimd.fpsr); @@ -1539,12 +1540,13 @@ static int target_restore_sigframe(CPUARMState *env, } for (i = 0; i < 32; i++) { + uint64_t *q = aa64_vfp_qreg(env, i); #ifdef TARGET_WORDS_BIGENDIAN - __get_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2 + 1]); - __get_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2]); + __get_user(q[0], &aux->fpsimd.vregs[i * 2 + 1]); + __get_user(q[1], &aux->fpsimd.vregs[i * 2]); #else - __get_user(env->vfp.regs[i * 2], &aux->fpsimd.vregs[i * 2]); - __get_user(env->vfp.regs[i * 2 + 1], &aux->fpsimd.vregs[i * 2 + 1]); + __get_user(q[0], &aux->fpsimd.vregs[i * 2]); + __get_user(q[1], &aux->fpsimd.vregs[i * 2 + 1]); #endif } __get_user(fpsr, &aux->fpsimd.fpsr); @@ -1903,7 +1905,7 @@ static abi_ulong *setup_sigframe_v2_vfp(abi_ulong *regspace, CPUARMState *env) __put_user(TARGET_VFP_MAGIC, &vfpframe->magic); __put_user(sizeof(*vfpframe), &vfpframe->size); for (i = 0; i < 32; i++) { - __put_user(float64_val(env->vfp.regs[i]), &vfpframe->ufp.fpregs[i]); + __put_user(*aa32_vfp_dreg(env, i), &vfpframe->ufp.fpregs[i]); } __put_user(vfp_get_fpscr(env), &vfpframe->ufp.fpscr); __put_user(env->vfp.xregs[ARM_VFP_FPEXC], &vfpframe->ufp_exc.fpexc); @@ -2210,7 +2212,7 @@ static abi_ulong *restore_sigframe_v2_vfp(CPUARMState *env, abi_ulong *regspace) return 0; } for (i = 0; i < 32; i++) { - __get_user(float64_val(env->vfp.regs[i]), &vfpframe->ufp.fpregs[i]); + __get_user(*aa32_vfp_dreg(env, i), &vfpframe->ufp.fpregs[i]); } __get_user(fpscr, &vfpframe->ufp.fpscr); vfp_set_fpscr(env, fpscr); diff --git a/qemu-doc.texi b/qemu-doc.texi index 3e9eb819a6..79d08b3f04 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -2596,6 +2596,13 @@ and 3.x series APIs. Support for the GTK 2.x builds will be discontinued, so maintainers should switch to using GTK 3.x, which is the default. +@subsection SDL 1.2 + +Previously QEMU has supported building against both SDL 1.2 +and 2.0 series APIs. Support for the SDL 1.2 builds will be +discontinued, so maintainers should switch to using SDL 2.0, +which is the default. + @section System emulator command line arguments @subsection -tdf (since 1.3.0) diff --git a/target/arm/arch_dump.c b/target/arm/arch_dump.c index 9e5b2fb31c..26a2c09868 100644 --- a/target/arm/arch_dump.c +++ b/target/arm/arch_dump.c @@ -99,8 +99,10 @@ static int aarch64_write_elf64_prfpreg(WriteCoreDumpFunction f, aarch64_note_init(¬e, s, "CORE", 5, NT_PRFPREG, sizeof(note.vfp)); - for (i = 0; i < 64; ++i) { - note.vfp.vregs[i] = cpu_to_dump64(s, float64_val(env->vfp.regs[i])); + for (i = 0; i < 32; ++i) { + uint64_t *q = aa64_vfp_qreg(env, i); + note.vfp.vregs[2*i + 0] = cpu_to_dump64(s, q[0]); + note.vfp.vregs[2*i + 1] = cpu_to_dump64(s, q[1]); } if (s->dump_info.d_endian == ELFDATA2MSB) { @@ -229,7 +231,7 @@ static int arm_write_elf32_vfp(WriteCoreDumpFunction f, CPUARMState *env, arm_note_init(¬e, s, "LINUX", 6, NT_ARM_VFP, sizeof(note.vfp)); for (i = 0; i < 32; ++i) { - note.vfp.vregs[i] = cpu_to_dump64(s, float64_val(env->vfp.regs[i])); + note.vfp.vregs[i] = cpu_to_dump64(s, *aa32_vfp_dreg(env, i)); } note.vfp.fpscr = cpu_to_dump32(s, vfp_get_fpscr(env)); diff --git a/target/arm/cpu.h b/target/arm/cpu.h index 96316700dd..d2bb59eded 100644 --- a/target/arm/cpu.h +++ b/target/arm/cpu.h @@ -492,7 +492,7 @@ typedef struct CPUARMState { * the two execution states, and means we do not need to explicitly * map these registers when changing states. */ - float64 regs[64]; + uint64_t regs[64]; uint32_t xregs[16]; /* We store these fpcsr fields separately for convenience. */ @@ -1340,6 +1340,7 @@ enum arm_features { ARM_FEATURE_VBAR, /* has cp15 VBAR */ ARM_FEATURE_M_SECURITY, /* M profile Security Extension */ ARM_FEATURE_JAZELLE, /* has (trivial) Jazelle implementation */ + ARM_FEATURE_SVE, /* has Scalable Vector Extension */ }; static inline int arm_feature(CPUARMState *env, int feature) @@ -2666,71 +2667,6 @@ static inline bool bswap_code(bool sctlr_b) #endif } -/* Return the exception level to which FP-disabled exceptions should - * be taken, or 0 if FP is enabled. - */ -static inline int fp_exception_el(CPUARMState *env) -{ - int fpen; - int cur_el = arm_current_el(env); - - /* CPACR and the CPTR registers don't exist before v6, so FP is - * always accessible - */ - if (!arm_feature(env, ARM_FEATURE_V6)) { - return 0; - } - - /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: - * 0, 2 : trap EL0 and EL1/PL1 accesses - * 1 : trap only EL0 accesses - * 3 : trap no accesses - */ - fpen = extract32(env->cp15.cpacr_el1, 20, 2); - switch (fpen) { - case 0: - case 2: - if (cur_el == 0 || cur_el == 1) { - /* Trap to PL1, which might be EL1 or EL3 */ - if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { - return 3; - } - return 1; - } - if (cur_el == 3 && !is_a64(env)) { - /* Secure PL1 running at EL3 */ - return 3; - } - break; - case 1: - if (cur_el == 0) { - return 1; - } - break; - case 3: - break; - } - - /* For the CPTR registers we don't need to guard with an ARM_FEATURE - * check because zero bits in the registers mean "don't trap". - */ - - /* CPTR_EL2 : present in v7VE or v8 */ - if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) - && !arm_is_secure_below_el3(env)) { - /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ - return 2; - } - - /* CPTR_EL3 : present in v8 */ - if (extract32(env->cp15.cptr_el[3], 10, 1)) { - /* Trap all FP ops to EL3 */ - return 3; - } - - return 0; -} - #ifdef CONFIG_USER_ONLY static inline bool arm_cpu_bswap_data(CPUARMState *env) { @@ -2777,66 +2713,8 @@ static inline uint32_t arm_regime_tbi1(CPUARMState *env, ARMMMUIdx mmu_idx) } #endif -static inline void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, - target_ulong *cs_base, uint32_t *flags) -{ - ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); - if (is_a64(env)) { - *pc = env->pc; - *flags = ARM_TBFLAG_AARCH64_STATE_MASK; - /* Get control bits for tagged addresses */ - *flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); - *flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); - } else { - *pc = env->regs[15]; - *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) - | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) - | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) - | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) - | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); - if (!(access_secure_reg(env))) { - *flags |= ARM_TBFLAG_NS_MASK; - } - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) - || arm_el_is_aa64(env, 1)) { - *flags |= ARM_TBFLAG_VFPEN_MASK; - } - *flags |= (extract32(env->cp15.c15_cpar, 0, 2) - << ARM_TBFLAG_XSCALE_CPAR_SHIFT); - } - - *flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); - - /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine - * states defined in the ARM ARM for software singlestep: - * SS_ACTIVE PSTATE.SS State - * 0 x Inactive (the TB flag for SS is always 0) - * 1 0 Active-pending - * 1 1 Active-not-pending - */ - if (arm_singlestep_active(env)) { - *flags |= ARM_TBFLAG_SS_ACTIVE_MASK; - if (is_a64(env)) { - if (env->pstate & PSTATE_SS) { - *flags |= ARM_TBFLAG_PSTATE_SS_MASK; - } - } else { - if (env->uncached_cpsr & PSTATE_SS) { - *flags |= ARM_TBFLAG_PSTATE_SS_MASK; - } - } - } - if (arm_cpu_data_is_big_endian(env)) { - *flags |= ARM_TBFLAG_BE_DATA_MASK; - } - *flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; - - if (arm_v7m_is_handler_mode(env)) { - *flags |= ARM_TBFLAG_HANDLER_MASK; - } - - *cs_base = 0; -} +void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *flags); enum { QEMU_PSCI_CONDUIT_DISABLED = 0, @@ -2885,4 +2763,31 @@ static inline void *arm_get_el_change_hook_opaque(ARMCPU *cpu) return cpu->el_change_hook_opaque; } +/** + * aa32_vfp_dreg: + * Return a pointer to the Dn register within env in 32-bit mode. + */ +static inline uint64_t *aa32_vfp_dreg(CPUARMState *env, unsigned regno) +{ + return &env->vfp.regs[regno]; +} + +/** + * aa32_vfp_qreg: + * Return a pointer to the Qn register within env in 32-bit mode. + */ +static inline uint64_t *aa32_vfp_qreg(CPUARMState *env, unsigned regno) +{ + return &env->vfp.regs[2 * regno]; +} + +/** + * aa64_vfp_qreg: + * Return a pointer to the Qn register within env in 64-bit mode. + */ +static inline uint64_t *aa64_vfp_qreg(CPUARMState *env, unsigned regno) +{ + return &env->vfp.regs[2 * regno]; +} + #endif diff --git a/target/arm/crypto_helper.c b/target/arm/crypto_helper.c index 3b6df3f41a..9ca0bdead7 100644 --- a/target/arm/crypto_helper.c +++ b/target/arm/crypto_helper.c @@ -30,20 +30,14 @@ union CRYPTO_STATE { #define CR_ST_WORD(state, i) (state.words[i]) #endif -void HELPER(crypto_aese)(CPUARMState *env, uint32_t rd, uint32_t rm, - uint32_t decrypt) +void HELPER(crypto_aese)(void *vd, void *vm, uint32_t decrypt) { static uint8_t const * const sbox[2] = { AES_sbox, AES_isbox }; static uint8_t const * const shift[2] = { AES_shifts, AES_ishifts }; - - union CRYPTO_STATE rk = { .l = { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; - union CRYPTO_STATE st = { .l = { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; + uint64_t *rd = vd; + uint64_t *rm = vm; + union CRYPTO_STATE rk = { .l = { rm[0], rm[1] } }; + union CRYPTO_STATE st = { .l = { rd[0], rd[1] } }; int i; assert(decrypt < 2); @@ -57,12 +51,11 @@ void HELPER(crypto_aese)(CPUARMState *env, uint32_t rd, uint32_t rm, CR_ST_BYTE(st, i) = sbox[decrypt][CR_ST_BYTE(rk, shift[decrypt][i])]; } - env->vfp.regs[rd] = make_float64(st.l[0]); - env->vfp.regs[rd + 1] = make_float64(st.l[1]); + rd[0] = st.l[0]; + rd[1] = st.l[1]; } -void HELPER(crypto_aesmc)(CPUARMState *env, uint32_t rd, uint32_t rm, - uint32_t decrypt) +void HELPER(crypto_aesmc)(void *vd, void *vm, uint32_t decrypt) { static uint32_t const mc[][256] = { { /* MixColumns lookup table */ @@ -197,10 +190,10 @@ void HELPER(crypto_aesmc)(CPUARMState *env, uint32_t rd, uint32_t rm, 0x92b479a7, 0x99b970a9, 0x84ae6bbb, 0x8fa362b5, 0xbe805d9f, 0xb58d5491, 0xa89a4f83, 0xa397468d, } }; - union CRYPTO_STATE st = { .l = { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + + uint64_t *rd = vd; + uint64_t *rm = vm; + union CRYPTO_STATE st = { .l = { rm[0], rm[1] } }; int i; assert(decrypt < 2); @@ -213,8 +206,8 @@ void HELPER(crypto_aesmc)(CPUARMState *env, uint32_t rd, uint32_t rm, rol32(mc[decrypt][CR_ST_BYTE(st, i + 3)], 24); } - env->vfp.regs[rd] = make_float64(st.l[0]); - env->vfp.regs[rd + 1] = make_float64(st.l[1]); + rd[0] = st.l[0]; + rd[1] = st.l[1]; } /* @@ -236,21 +229,14 @@ static uint32_t maj(uint32_t x, uint32_t y, uint32_t z) return (x & y) | ((x | y) & z); } -void HELPER(crypto_sha1_3reg)(CPUARMState *env, uint32_t rd, uint32_t rn, - uint32_t rm, uint32_t op) +void HELPER(crypto_sha1_3reg)(void *vd, void *vn, void *vm, uint32_t op) { - union CRYPTO_STATE d = { .l = { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE n = { .l = { - float64_val(env->vfp.regs[rn]), - float64_val(env->vfp.regs[rn + 1]) - } }; - union CRYPTO_STATE m = { .l = { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd = vd; + uint64_t *rn = vn; + uint64_t *rm = vm; + union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; + union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; + union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; if (op == 3) { /* sha1su0 */ d.l[0] ^= d.l[1] ^ m.l[0]; @@ -284,42 +270,37 @@ void HELPER(crypto_sha1_3reg)(CPUARMState *env, uint32_t rd, uint32_t rn, CR_ST_WORD(d, 0) = t; } } - env->vfp.regs[rd] = make_float64(d.l[0]); - env->vfp.regs[rd + 1] = make_float64(d.l[1]); + rd[0] = d.l[0]; + rd[1] = d.l[1]; } -void HELPER(crypto_sha1h)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(crypto_sha1h)(void *vd, void *vm) { - union CRYPTO_STATE m = { .l = { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd = vd; + uint64_t *rm = vm; + union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; CR_ST_WORD(m, 0) = ror32(CR_ST_WORD(m, 0), 2); CR_ST_WORD(m, 1) = CR_ST_WORD(m, 2) = CR_ST_WORD(m, 3) = 0; - env->vfp.regs[rd] = make_float64(m.l[0]); - env->vfp.regs[rd + 1] = make_float64(m.l[1]); + rd[0] = m.l[0]; + rd[1] = m.l[1]; } -void HELPER(crypto_sha1su1)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(crypto_sha1su1)(void *vd, void *vm) { - union CRYPTO_STATE d = { .l = { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE m = { .l = { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd = vd; + uint64_t *rm = vm; + union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; + union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; CR_ST_WORD(d, 0) = rol32(CR_ST_WORD(d, 0) ^ CR_ST_WORD(m, 1), 1); CR_ST_WORD(d, 1) = rol32(CR_ST_WORD(d, 1) ^ CR_ST_WORD(m, 2), 1); CR_ST_WORD(d, 2) = rol32(CR_ST_WORD(d, 2) ^ CR_ST_WORD(m, 3), 1); CR_ST_WORD(d, 3) = rol32(CR_ST_WORD(d, 3) ^ CR_ST_WORD(d, 0), 1); - env->vfp.regs[rd] = make_float64(d.l[0]); - env->vfp.regs[rd + 1] = make_float64(d.l[1]); + rd[0] = d.l[0]; + rd[1] = d.l[1]; } /* @@ -347,21 +328,14 @@ static uint32_t s1(uint32_t x) return ror32(x, 17) ^ ror32(x, 19) ^ (x >> 10); } -void HELPER(crypto_sha256h)(CPUARMState *env, uint32_t rd, uint32_t rn, - uint32_t rm) +void HELPER(crypto_sha256h)(void *vd, void *vn, void *vm) { - union CRYPTO_STATE d = { .l = { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE n = { .l = { - float64_val(env->vfp.regs[rn]), - float64_val(env->vfp.regs[rn + 1]) - } }; - union CRYPTO_STATE m = { .l = { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd = vd; + uint64_t *rn = vn; + uint64_t *rm = vm; + union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; + union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; + union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; int i; for (i = 0; i < 4; i++) { @@ -383,25 +357,18 @@ void HELPER(crypto_sha256h)(CPUARMState *env, uint32_t rd, uint32_t rn, CR_ST_WORD(d, 0) = t; } - env->vfp.regs[rd] = make_float64(d.l[0]); - env->vfp.regs[rd + 1] = make_float64(d.l[1]); + rd[0] = d.l[0]; + rd[1] = d.l[1]; } -void HELPER(crypto_sha256h2)(CPUARMState *env, uint32_t rd, uint32_t rn, - uint32_t rm) +void HELPER(crypto_sha256h2)(void *vd, void *vn, void *vm) { - union CRYPTO_STATE d = { .l = { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE n = { .l = { - float64_val(env->vfp.regs[rn]), - float64_val(env->vfp.regs[rn + 1]) - } }; - union CRYPTO_STATE m = { .l = { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd = vd; + uint64_t *rn = vn; + uint64_t *rm = vm; + union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; + union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; + union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; int i; for (i = 0; i < 4; i++) { @@ -415,51 +382,40 @@ void HELPER(crypto_sha256h2)(CPUARMState *env, uint32_t rd, uint32_t rn, CR_ST_WORD(d, 0) = CR_ST_WORD(n, 3 - i) + t; } - env->vfp.regs[rd] = make_float64(d.l[0]); - env->vfp.regs[rd + 1] = make_float64(d.l[1]); + rd[0] = d.l[0]; + rd[1] = d.l[1]; } -void HELPER(crypto_sha256su0)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(crypto_sha256su0)(void *vd, void *vm) { - union CRYPTO_STATE d = { .l = { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE m = { .l = { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd = vd; + uint64_t *rm = vm; + union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; + union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; CR_ST_WORD(d, 0) += s0(CR_ST_WORD(d, 1)); CR_ST_WORD(d, 1) += s0(CR_ST_WORD(d, 2)); CR_ST_WORD(d, 2) += s0(CR_ST_WORD(d, 3)); CR_ST_WORD(d, 3) += s0(CR_ST_WORD(m, 0)); - env->vfp.regs[rd] = make_float64(d.l[0]); - env->vfp.regs[rd + 1] = make_float64(d.l[1]); + rd[0] = d.l[0]; + rd[1] = d.l[1]; } -void HELPER(crypto_sha256su1)(CPUARMState *env, uint32_t rd, uint32_t rn, - uint32_t rm) +void HELPER(crypto_sha256su1)(void *vd, void *vn, void *vm) { - union CRYPTO_STATE d = { .l = { - float64_val(env->vfp.regs[rd]), - float64_val(env->vfp.regs[rd + 1]) - } }; - union CRYPTO_STATE n = { .l = { - float64_val(env->vfp.regs[rn]), - float64_val(env->vfp.regs[rn + 1]) - } }; - union CRYPTO_STATE m = { .l = { - float64_val(env->vfp.regs[rm]), - float64_val(env->vfp.regs[rm + 1]) - } }; + uint64_t *rd = vd; + uint64_t *rn = vn; + uint64_t *rm = vm; + union CRYPTO_STATE d = { .l = { rd[0], rd[1] } }; + union CRYPTO_STATE n = { .l = { rn[0], rn[1] } }; + union CRYPTO_STATE m = { .l = { rm[0], rm[1] } }; CR_ST_WORD(d, 0) += s1(CR_ST_WORD(m, 2)) + CR_ST_WORD(n, 1); CR_ST_WORD(d, 1) += s1(CR_ST_WORD(m, 3)) + CR_ST_WORD(n, 2); CR_ST_WORD(d, 2) += s1(CR_ST_WORD(d, 0)) + CR_ST_WORD(n, 3); CR_ST_WORD(d, 3) += s1(CR_ST_WORD(d, 1)) + CR_ST_WORD(m, 0); - env->vfp.regs[rd] = make_float64(d.l[0]); - env->vfp.regs[rd + 1] = make_float64(d.l[1]); + rd[0] = d.l[0]; + rd[1] = d.l[1]; } diff --git a/target/arm/helper-a64.c b/target/arm/helper-a64.c index 3e00a9ead1..06fd321fae 100644 --- a/target/arm/helper-a64.c +++ b/target/arm/helper-a64.c @@ -153,13 +153,14 @@ uint64_t HELPER(simd_tbl)(CPUARMState *env, uint64_t result, uint64_t indices, if (index < 16 * numregs) { /* Convert index (a byte offset into the virtual table * which is a series of 128-bit vectors concatenated) - * into the correct vfp.regs[] element plus a bit offset + * into the correct register element plus a bit offset * into that element, bearing in mind that the table * can wrap around from V31 to V0. */ int elt = (rn * 2 + (index >> 3)) % 64; int bitidx = (index & 7) * 8; - uint64_t val = extract64(env->vfp.regs[elt], bitidx, 8); + uint64_t *q = aa64_vfp_qreg(env, elt >> 1); + uint64_t val = extract64(q[elt & 1], bitidx, 8); result = deposit64(result, shift, 8, val); } diff --git a/target/arm/helper.c b/target/arm/helper.c index c83c901a86..bfce09643b 100644 --- a/target/arm/helper.c +++ b/target/arm/helper.c @@ -64,15 +64,16 @@ static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) /* VFP data registers are always little-endian. */ nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - stfq_le_p(buf, env->vfp.regs[reg]); + stq_le_p(buf, *aa32_vfp_dreg(env, reg)); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { /* Aliases for Q regs. */ nregs += 16; if (reg < nregs) { - stfq_le_p(buf, env->vfp.regs[(reg - 32) * 2]); - stfq_le_p(buf + 8, env->vfp.regs[(reg - 32) * 2 + 1]); + uint64_t *q = aa32_vfp_qreg(env, reg - 32); + stq_le_p(buf, q[0]); + stq_le_p(buf + 8, q[1]); return 16; } } @@ -90,14 +91,15 @@ static int vfp_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) nregs = arm_feature(env, ARM_FEATURE_VFP3) ? 32 : 16; if (reg < nregs) { - env->vfp.regs[reg] = ldfq_le_p(buf); + *aa32_vfp_dreg(env, reg) = ldq_le_p(buf); return 8; } if (arm_feature(env, ARM_FEATURE_NEON)) { nregs += 16; if (reg < nregs) { - env->vfp.regs[(reg - 32) * 2] = ldfq_le_p(buf); - env->vfp.regs[(reg - 32) * 2 + 1] = ldfq_le_p(buf + 8); + uint64_t *q = aa32_vfp_qreg(env, reg - 32); + q[0] = ldq_le_p(buf); + q[1] = ldq_le_p(buf + 8); return 16; } } @@ -114,9 +116,12 @@ static int aarch64_fpu_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - stfq_le_p(buf, env->vfp.regs[reg * 2]); - stfq_le_p(buf + 8, env->vfp.regs[reg * 2 + 1]); - return 16; + { + uint64_t *q = aa64_vfp_qreg(env, reg); + stq_le_p(buf, q[0]); + stq_le_p(buf + 8, q[1]); + return 16; + } case 32: /* FPSR */ stl_p(buf, vfp_get_fpsr(env)); @@ -135,9 +140,12 @@ static int aarch64_fpu_gdb_set_reg(CPUARMState *env, uint8_t *buf, int reg) switch (reg) { case 0 ... 31: /* 128 bit FP register */ - env->vfp.regs[reg * 2] = ldfq_le_p(buf); - env->vfp.regs[reg * 2 + 1] = ldfq_le_p(buf + 8); - return 16; + { + uint64_t *q = aa64_vfp_qreg(env, reg); + q[0] = ldq_le_p(buf); + q[1] = ldq_le_p(buf + 8); + return 16; + } case 32: /* FPSR */ vfp_set_fpsr(env, ldl_p(buf)); @@ -8360,7 +8368,7 @@ static uint64_t arm_ldq_ptw(CPUState *cs, hwaddr addr, bool is_secure, MemTxAttrs attrs = {}; MemTxResult result = MEMTX_OK; AddressSpace *as; - uint32_t data; + uint64_t data; attrs.secure = is_secure; as = arm_addressspace(cs, attrs); @@ -11613,3 +11621,133 @@ uint32_t HELPER(crc32c)(uint32_t acc, uint32_t val, uint32_t bytes) /* Linux crc32c converts the output to one's complement. */ return crc32c(acc, buf, bytes) ^ 0xffffffff; } + +/* Return the exception level to which FP-disabled exceptions should + * be taken, or 0 if FP is enabled. + */ +static inline int fp_exception_el(CPUARMState *env) +{ +#ifndef CONFIG_USER_ONLY + int fpen; + int cur_el = arm_current_el(env); + + /* CPACR and the CPTR registers don't exist before v6, so FP is + * always accessible + */ + if (!arm_feature(env, ARM_FEATURE_V6)) { + return 0; + } + + /* The CPACR controls traps to EL1, or PL1 if we're 32 bit: + * 0, 2 : trap EL0 and EL1/PL1 accesses + * 1 : trap only EL0 accesses + * 3 : trap no accesses + */ + fpen = extract32(env->cp15.cpacr_el1, 20, 2); + switch (fpen) { + case 0: + case 2: + if (cur_el == 0 || cur_el == 1) { + /* Trap to PL1, which might be EL1 or EL3 */ + if (arm_is_secure(env) && !arm_el_is_aa64(env, 3)) { + return 3; + } + return 1; + } + if (cur_el == 3 && !is_a64(env)) { + /* Secure PL1 running at EL3 */ + return 3; + } + break; + case 1: + if (cur_el == 0) { + return 1; + } + break; + case 3: + break; + } + + /* For the CPTR registers we don't need to guard with an ARM_FEATURE + * check because zero bits in the registers mean "don't trap". + */ + + /* CPTR_EL2 : present in v7VE or v8 */ + if (cur_el <= 2 && extract32(env->cp15.cptr_el[2], 10, 1) + && !arm_is_secure_below_el3(env)) { + /* Trap FP ops at EL2, NS-EL1 or NS-EL0 to EL2 */ + return 2; + } + + /* CPTR_EL3 : present in v8 */ + if (extract32(env->cp15.cptr_el[3], 10, 1)) { + /* Trap all FP ops to EL3 */ + return 3; + } +#endif + return 0; +} + +void cpu_get_tb_cpu_state(CPUARMState *env, target_ulong *pc, + target_ulong *cs_base, uint32_t *pflags) +{ + ARMMMUIdx mmu_idx = core_to_arm_mmu_idx(env, cpu_mmu_index(env, false)); + uint32_t flags; + + if (is_a64(env)) { + *pc = env->pc; + flags = ARM_TBFLAG_AARCH64_STATE_MASK; + /* Get control bits for tagged addresses */ + flags |= (arm_regime_tbi0(env, mmu_idx) << ARM_TBFLAG_TBI0_SHIFT); + flags |= (arm_regime_tbi1(env, mmu_idx) << ARM_TBFLAG_TBI1_SHIFT); + } else { + *pc = env->regs[15]; + flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) + | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) + | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) + | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT) + | (arm_sctlr_b(env) << ARM_TBFLAG_SCTLR_B_SHIFT); + if (!(access_secure_reg(env))) { + flags |= ARM_TBFLAG_NS_MASK; + } + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30) + || arm_el_is_aa64(env, 1)) { + flags |= ARM_TBFLAG_VFPEN_MASK; + } + flags |= (extract32(env->cp15.c15_cpar, 0, 2) + << ARM_TBFLAG_XSCALE_CPAR_SHIFT); + } + + flags |= (arm_to_core_mmu_idx(mmu_idx) << ARM_TBFLAG_MMUIDX_SHIFT); + + /* The SS_ACTIVE and PSTATE_SS bits correspond to the state machine + * states defined in the ARM ARM for software singlestep: + * SS_ACTIVE PSTATE.SS State + * 0 x Inactive (the TB flag for SS is always 0) + * 1 0 Active-pending + * 1 1 Active-not-pending + */ + if (arm_singlestep_active(env)) { + flags |= ARM_TBFLAG_SS_ACTIVE_MASK; + if (is_a64(env)) { + if (env->pstate & PSTATE_SS) { + flags |= ARM_TBFLAG_PSTATE_SS_MASK; + } + } else { + if (env->uncached_cpsr & PSTATE_SS) { + flags |= ARM_TBFLAG_PSTATE_SS_MASK; + } + } + } + if (arm_cpu_data_is_big_endian(env)) { + flags |= ARM_TBFLAG_BE_DATA_MASK; + } + flags |= fp_exception_el(env) << ARM_TBFLAG_FPEXC_EL_SHIFT; + + if (arm_v7m_is_handler_mode(env)) { + flags |= ARM_TBFLAG_HANDLER_MASK; + } + + *pflags = flags; + *cs_base = 0; +} diff --git a/target/arm/helper.h b/target/arm/helper.h index 066729e8ad..5dec2e6262 100644 --- a/target/arm/helper.h +++ b/target/arm/helper.h @@ -188,7 +188,7 @@ DEF_HELPER_FLAGS_2(rsqrte_f32, TCG_CALL_NO_RWG, f32, f32, ptr) DEF_HELPER_FLAGS_2(rsqrte_f64, TCG_CALL_NO_RWG, f64, f64, ptr) DEF_HELPER_2(recpe_u32, i32, i32, ptr) DEF_HELPER_FLAGS_2(rsqrte_u32, TCG_CALL_NO_RWG, i32, i32, ptr) -DEF_HELPER_5(neon_tbl, i32, env, i32, i32, i32, i32) +DEF_HELPER_FLAGS_4(neon_tbl, TCG_CALL_NO_RWG, i32, i32, i32, ptr, i32) DEF_HELPER_3(shl_cc, i32, env, i32, i32) DEF_HELPER_3(shr_cc, i32, env, i32, i32) @@ -511,28 +511,28 @@ DEF_HELPER_3(iwmmxt_muladdsl, i64, i64, i32, i32) DEF_HELPER_3(iwmmxt_muladdsw, i64, i64, i32, i32) DEF_HELPER_3(iwmmxt_muladdswl, i64, i64, i32, i32) -DEF_HELPER_3(neon_unzip8, void, env, i32, i32) -DEF_HELPER_3(neon_unzip16, void, env, i32, i32) -DEF_HELPER_3(neon_qunzip8, void, env, i32, i32) -DEF_HELPER_3(neon_qunzip16, void, env, i32, i32) -DEF_HELPER_3(neon_qunzip32, void, env, i32, i32) -DEF_HELPER_3(neon_zip8, void, env, i32, i32) -DEF_HELPER_3(neon_zip16, void, env, i32, i32) -DEF_HELPER_3(neon_qzip8, void, env, i32, i32) -DEF_HELPER_3(neon_qzip16, void, env, i32, i32) -DEF_HELPER_3(neon_qzip32, void, env, i32, i32) - -DEF_HELPER_4(crypto_aese, void, env, i32, i32, i32) -DEF_HELPER_4(crypto_aesmc, void, env, i32, i32, i32) - -DEF_HELPER_5(crypto_sha1_3reg, void, env, i32, i32, i32, i32) -DEF_HELPER_3(crypto_sha1h, void, env, i32, i32) -DEF_HELPER_3(crypto_sha1su1, void, env, i32, i32) - -DEF_HELPER_4(crypto_sha256h, void, env, i32, i32, i32) -DEF_HELPER_4(crypto_sha256h2, void, env, i32, i32, i32) -DEF_HELPER_3(crypto_sha256su0, void, env, i32, i32) -DEF_HELPER_4(crypto_sha256su1, void, env, i32, i32, i32) +DEF_HELPER_FLAGS_2(neon_unzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_unzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qunzip32, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_zip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip8, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip16, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(neon_qzip32, TCG_CALL_NO_RWG, void, ptr, ptr) + +DEF_HELPER_FLAGS_3(crypto_aese, TCG_CALL_NO_RWG, void, ptr, ptr, i32) +DEF_HELPER_FLAGS_3(crypto_aesmc, TCG_CALL_NO_RWG, void, ptr, ptr, i32) + +DEF_HELPER_FLAGS_4(crypto_sha1_3reg, TCG_CALL_NO_RWG, void, ptr, ptr, ptr, i32) +DEF_HELPER_FLAGS_2(crypto_sha1h, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_2(crypto_sha1su1, TCG_CALL_NO_RWG, void, ptr, ptr) + +DEF_HELPER_FLAGS_3(crypto_sha256h, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sha256h2, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) +DEF_HELPER_FLAGS_2(crypto_sha256su0, TCG_CALL_NO_RWG, void, ptr, ptr) +DEF_HELPER_FLAGS_3(crypto_sha256su1, TCG_CALL_NO_RWG, void, ptr, ptr, ptr) DEF_HELPER_FLAGS_3(crc32, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) DEF_HELPER_FLAGS_3(crc32c, TCG_CALL_NO_RWG_SE, i32, i32, i32, i32) diff --git a/target/arm/kvm32.c b/target/arm/kvm32.c index f925a21481..f77c9c494b 100644 --- a/target/arm/kvm32.c +++ b/target/arm/kvm32.c @@ -358,7 +358,7 @@ int kvm_arch_put_registers(CPUState *cs, int level) /* VFP registers */ r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; for (i = 0; i < 32; i++) { - r.addr = (uintptr_t)(&env->vfp.regs[i]); + r.addr = (uintptr_t)aa32_vfp_dreg(env, i); ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, &r); if (ret) { return ret; @@ -445,7 +445,7 @@ int kvm_arch_get_registers(CPUState *cs) /* VFP registers */ r.id = KVM_REG_ARM | KVM_REG_SIZE_U64 | KVM_REG_ARM_VFP; for (i = 0; i < 32; i++) { - r.addr = (uintptr_t)(&env->vfp.regs[i]); + r.addr = (uintptr_t)aa32_vfp_dreg(env, i); ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, &r); if (ret) { return ret; diff --git a/target/arm/kvm64.c b/target/arm/kvm64.c index 6554c30007..ac728494a4 100644 --- a/target/arm/kvm64.c +++ b/target/arm/kvm64.c @@ -696,21 +696,16 @@ int kvm_arch_put_registers(CPUState *cs, int level) } } - /* Advanced SIMD and FP registers - * We map Qn = regs[2n+1]:regs[2n] - */ + /* Advanced SIMD and FP registers. */ for (i = 0; i < 32; i++) { - int rd = i << 1; - uint64_t fp_val[2]; + uint64_t *q = aa64_vfp_qreg(env, i); #ifdef HOST_WORDS_BIGENDIAN - fp_val[0] = env->vfp.regs[rd + 1]; - fp_val[1] = env->vfp.regs[rd]; + uint64_t fp_val[2] = { q[1], q[0] }; + reg.addr = (uintptr_t)fp_val; #else - fp_val[1] = env->vfp.regs[rd + 1]; - fp_val[0] = env->vfp.regs[rd]; + reg.addr = (uintptr_t)q; #endif reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr = (uintptr_t)(&fp_val); ret = kvm_vcpu_ioctl(cs, KVM_SET_ONE_REG, ®); if (ret) { return ret; @@ -837,24 +832,18 @@ int kvm_arch_get_registers(CPUState *cs) env->spsr = env->banked_spsr[i]; } - /* Advanced SIMD and FP registers - * We map Qn = regs[2n+1]:regs[2n] - */ + /* Advanced SIMD and FP registers */ for (i = 0; i < 32; i++) { - uint64_t fp_val[2]; + uint64_t *q = aa64_vfp_qreg(env, i); reg.id = AARCH64_SIMD_CORE_REG(fp_regs.vregs[i]); - reg.addr = (uintptr_t)(&fp_val); + reg.addr = (uintptr_t)q; ret = kvm_vcpu_ioctl(cs, KVM_GET_ONE_REG, ®); if (ret) { return ret; } else { - int rd = i << 1; #ifdef HOST_WORDS_BIGENDIAN - env->vfp.regs[rd + 1] = fp_val[0]; - env->vfp.regs[rd] = fp_val[1]; -#else - env->vfp.regs[rd + 1] = fp_val[1]; - env->vfp.regs[rd] = fp_val[0]; + uint64_t t; + t = q[0], q[0] = q[1], q[1] = t; #endif } } diff --git a/target/arm/machine.c b/target/arm/machine.c index 176274629c..a85c2430d3 100644 --- a/target/arm/machine.c +++ b/target/arm/machine.c @@ -50,7 +50,7 @@ static const VMStateDescription vmstate_vfp = { .minimum_version_id = 3, .needed = vfp_needed, .fields = (VMStateField[]) { - VMSTATE_FLOAT64_ARRAY(env.vfp.regs, ARMCPU, 64), + VMSTATE_UINT64_ARRAY(env.vfp.regs, ARMCPU, 64), /* The xregs array is a little awkward because element 1 (FPSCR) * requires a specific accessor, so we have to split it up in * the vmstate: diff --git a/target/arm/neon_helper.c b/target/arm/neon_helper.c index ebdf7c9b10..689491cad3 100644 --- a/target/arm/neon_helper.c +++ b/target/arm/neon_helper.c @@ -2027,12 +2027,12 @@ uint64_t HELPER(neon_acgt_f64)(uint64_t a, uint64_t b, void *fpstp) #define ELEM(V, N, SIZE) (((V) >> ((N) * (SIZE))) & ((1ull << (SIZE)) - 1)) -void HELPER(neon_qunzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qunzip8)(void *vd, void *vm) { - uint64_t zm0 = float64_val(env->vfp.regs[rm]); - uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 = float64_val(env->vfp.regs[rd]); - uint64_t zd1 = float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd0 = rd[0], zd1 = rd[1]; + uint64_t zm0 = rm[0], zm1 = rm[1]; + uint64_t d0 = ELEM(zd0, 0, 8) | (ELEM(zd0, 2, 8) << 8) | (ELEM(zd0, 4, 8) << 16) | (ELEM(zd0, 6, 8) << 24) | (ELEM(zd1, 0, 8) << 32) | (ELEM(zd1, 2, 8) << 40) @@ -2049,18 +2049,19 @@ void HELPER(neon_qunzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) | (ELEM(zm0, 5, 8) << 16) | (ELEM(zm0, 7, 8) << 24) | (ELEM(zm1, 1, 8) << 32) | (ELEM(zm1, 3, 8) << 40) | (ELEM(zm1, 5, 8) << 48) | (ELEM(zm1, 7, 8) << 56); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rm + 1] = make_float64(m1); - env->vfp.regs[rd] = make_float64(d0); - env->vfp.regs[rd + 1] = make_float64(d1); + + rm[0] = m0; + rm[1] = m1; + rd[0] = d0; + rd[1] = d1; } -void HELPER(neon_qunzip16)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qunzip16)(void *vd, void *vm) { - uint64_t zm0 = float64_val(env->vfp.regs[rm]); - uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 = float64_val(env->vfp.regs[rd]); - uint64_t zd1 = float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd0 = rd[0], zd1 = rd[1]; + uint64_t zm0 = rm[0], zm1 = rm[1]; + uint64_t d0 = ELEM(zd0, 0, 16) | (ELEM(zd0, 2, 16) << 16) | (ELEM(zd1, 0, 16) << 32) | (ELEM(zd1, 2, 16) << 48); uint64_t d1 = ELEM(zm0, 0, 16) | (ELEM(zm0, 2, 16) << 16) @@ -2069,32 +2070,35 @@ void HELPER(neon_qunzip16)(CPUARMState *env, uint32_t rd, uint32_t rm) | (ELEM(zd1, 1, 16) << 32) | (ELEM(zd1, 3, 16) << 48); uint64_t m1 = ELEM(zm0, 1, 16) | (ELEM(zm0, 3, 16) << 16) | (ELEM(zm1, 1, 16) << 32) | (ELEM(zm1, 3, 16) << 48); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rm + 1] = make_float64(m1); - env->vfp.regs[rd] = make_float64(d0); - env->vfp.regs[rd + 1] = make_float64(d1); + + rm[0] = m0; + rm[1] = m1; + rd[0] = d0; + rd[1] = d1; } -void HELPER(neon_qunzip32)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qunzip32)(void *vd, void *vm) { - uint64_t zm0 = float64_val(env->vfp.regs[rm]); - uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 = float64_val(env->vfp.regs[rd]); - uint64_t zd1 = float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd0 = rd[0], zd1 = rd[1]; + uint64_t zm0 = rm[0], zm1 = rm[1]; + uint64_t d0 = ELEM(zd0, 0, 32) | (ELEM(zd1, 0, 32) << 32); uint64_t d1 = ELEM(zm0, 0, 32) | (ELEM(zm1, 0, 32) << 32); uint64_t m0 = ELEM(zd0, 1, 32) | (ELEM(zd1, 1, 32) << 32); uint64_t m1 = ELEM(zm0, 1, 32) | (ELEM(zm1, 1, 32) << 32); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rm + 1] = make_float64(m1); - env->vfp.regs[rd] = make_float64(d0); - env->vfp.regs[rd + 1] = make_float64(d1); + + rm[0] = m0; + rm[1] = m1; + rd[0] = d0; + rd[1] = d1; } -void HELPER(neon_unzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_unzip8)(void *vd, void *vm) { - uint64_t zm = float64_val(env->vfp.regs[rm]); - uint64_t zd = float64_val(env->vfp.regs[rd]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd = rd[0], zm = rm[0]; + uint64_t d0 = ELEM(zd, 0, 8) | (ELEM(zd, 2, 8) << 8) | (ELEM(zd, 4, 8) << 16) | (ELEM(zd, 6, 8) << 24) | (ELEM(zm, 0, 8) << 32) | (ELEM(zm, 2, 8) << 40) @@ -2103,28 +2107,31 @@ void HELPER(neon_unzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) | (ELEM(zd, 5, 8) << 16) | (ELEM(zd, 7, 8) << 24) | (ELEM(zm, 1, 8) << 32) | (ELEM(zm, 3, 8) << 40) | (ELEM(zm, 5, 8) << 48) | (ELEM(zm, 7, 8) << 56); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rd] = make_float64(d0); + + rm[0] = m0; + rd[0] = d0; } -void HELPER(neon_unzip16)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_unzip16)(void *vd, void *vm) { - uint64_t zm = float64_val(env->vfp.regs[rm]); - uint64_t zd = float64_val(env->vfp.regs[rd]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd = rd[0], zm = rm[0]; + uint64_t d0 = ELEM(zd, 0, 16) | (ELEM(zd, 2, 16) << 16) | (ELEM(zm, 0, 16) << 32) | (ELEM(zm, 2, 16) << 48); uint64_t m0 = ELEM(zd, 1, 16) | (ELEM(zd, 3, 16) << 16) | (ELEM(zm, 1, 16) << 32) | (ELEM(zm, 3, 16) << 48); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rd] = make_float64(d0); + + rm[0] = m0; + rd[0] = d0; } -void HELPER(neon_qzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qzip8)(void *vd, void *vm) { - uint64_t zm0 = float64_val(env->vfp.regs[rm]); - uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 = float64_val(env->vfp.regs[rd]); - uint64_t zd1 = float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd0 = rd[0], zd1 = rd[1]; + uint64_t zm0 = rm[0], zm1 = rm[1]; + uint64_t d0 = ELEM(zd0, 0, 8) | (ELEM(zm0, 0, 8) << 8) | (ELEM(zd0, 1, 8) << 16) | (ELEM(zm0, 1, 8) << 24) | (ELEM(zd0, 2, 8) << 32) | (ELEM(zm0, 2, 8) << 40) @@ -2141,18 +2148,19 @@ void HELPER(neon_qzip8)(CPUARMState *env, uint32_t rd, uint32_t rm) | (ELEM(zd1, 5, 8) << 16) | (ELEM(zm1, 5, 8) << 24) | (ELEM(zd1, 6, 8) << 32) | (ELEM(zm1, 6, 8) << 40) | (ELEM(zd1, 7, 8) << 48) | (ELEM(zm1, 7, 8) << 56); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rm + 1] = make_float64(m1); - env->vfp.regs[rd] = make_float64(d0); - env->vfp.regs[rd + 1] = make_float64(d1); + + rm[0] = m0; + rm[1] = m1; + rd[0] = d0; + rd[1] = d1; } -void HELPER(neon_qzip16)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qzip16)(void *vd, void *vm) { - uint64_t zm0 = float64_val(env->vfp.regs[rm]); - uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 = float64_val(env->vfp.regs[rd]); - uint64_t zd1 = float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd0 = rd[0], zd1 = rd[1]; + uint64_t zm0 = rm[0], zm1 = rm[1]; + uint64_t d0 = ELEM(zd0, 0, 16) | (ELEM(zm0, 0, 16) << 16) | (ELEM(zd0, 1, 16) << 32) | (ELEM(zm0, 1, 16) << 48); uint64_t d1 = ELEM(zd0, 2, 16) | (ELEM(zm0, 2, 16) << 16) @@ -2161,32 +2169,35 @@ void HELPER(neon_qzip16)(CPUARMState *env, uint32_t rd, uint32_t rm) | (ELEM(zd1, 1, 16) << 32) | (ELEM(zm1, 1, 16) << 48); uint64_t m1 = ELEM(zd1, 2, 16) | (ELEM(zm1, 2, 16) << 16) | (ELEM(zd1, 3, 16) << 32) | (ELEM(zm1, 3, 16) << 48); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rm + 1] = make_float64(m1); - env->vfp.regs[rd] = make_float64(d0); - env->vfp.regs[rd + 1] = make_float64(d1); + + rm[0] = m0; + rm[1] = m1; + rd[0] = d0; + rd[1] = d1; } -void HELPER(neon_qzip32)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_qzip32)(void *vd, void *vm) { - uint64_t zm0 = float64_val(env->vfp.regs[rm]); - uint64_t zm1 = float64_val(env->vfp.regs[rm + 1]); - uint64_t zd0 = float64_val(env->vfp.regs[rd]); - uint64_t zd1 = float64_val(env->vfp.regs[rd + 1]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd0 = rd[0], zd1 = rd[1]; + uint64_t zm0 = rm[0], zm1 = rm[1]; + uint64_t d0 = ELEM(zd0, 0, 32) | (ELEM(zm0, 0, 32) << 32); uint64_t d1 = ELEM(zd0, 1, 32) | (ELEM(zm0, 1, 32) << 32); uint64_t m0 = ELEM(zd1, 0, 32) | (ELEM(zm1, 0, 32) << 32); uint64_t m1 = ELEM(zd1, 1, 32) | (ELEM(zm1, 1, 32) << 32); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rm + 1] = make_float64(m1); - env->vfp.regs[rd] = make_float64(d0); - env->vfp.regs[rd + 1] = make_float64(d1); + + rm[0] = m0; + rm[1] = m1; + rd[0] = d0; + rd[1] = d1; } -void HELPER(neon_zip8)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_zip8)(void *vd, void *vm) { - uint64_t zm = float64_val(env->vfp.regs[rm]); - uint64_t zd = float64_val(env->vfp.regs[rd]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd = rd[0], zm = rm[0]; + uint64_t d0 = ELEM(zd, 0, 8) | (ELEM(zm, 0, 8) << 8) | (ELEM(zd, 1, 8) << 16) | (ELEM(zm, 1, 8) << 24) | (ELEM(zd, 2, 8) << 32) | (ELEM(zm, 2, 8) << 40) @@ -2195,20 +2206,23 @@ void HELPER(neon_zip8)(CPUARMState *env, uint32_t rd, uint32_t rm) | (ELEM(zd, 5, 8) << 16) | (ELEM(zm, 5, 8) << 24) | (ELEM(zd, 6, 8) << 32) | (ELEM(zm, 6, 8) << 40) | (ELEM(zd, 7, 8) << 48) | (ELEM(zm, 7, 8) << 56); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rd] = make_float64(d0); + + rm[0] = m0; + rd[0] = d0; } -void HELPER(neon_zip16)(CPUARMState *env, uint32_t rd, uint32_t rm) +void HELPER(neon_zip16)(void *vd, void *vm) { - uint64_t zm = float64_val(env->vfp.regs[rm]); - uint64_t zd = float64_val(env->vfp.regs[rd]); + uint64_t *rd = vd, *rm = vm; + uint64_t zd = rd[0], zm = rm[0]; + uint64_t d0 = ELEM(zd, 0, 16) | (ELEM(zm, 0, 16) << 16) | (ELEM(zd, 1, 16) << 32) | (ELEM(zm, 1, 16) << 48); uint64_t m0 = ELEM(zd, 2, 16) | (ELEM(zm, 2, 16) << 16) | (ELEM(zd, 3, 16) << 32) | (ELEM(zm, 3, 16) << 48); - env->vfp.regs[rm] = make_float64(m0); - env->vfp.regs[rd] = make_float64(d0); + + rm[0] = m0; + rd[0] = d0; } /* Helper function for 64 bit polynomial multiply case: diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index abd00f845d..7a88fd2c92 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -54,20 +54,17 @@ static int exception_target_el(CPUARMState *env) return target_el; } -uint32_t HELPER(neon_tbl)(CPUARMState *env, uint32_t ireg, uint32_t def, - uint32_t rn, uint32_t maxindex) +uint32_t HELPER(neon_tbl)(uint32_t ireg, uint32_t def, void *vn, + uint32_t maxindex) { - uint32_t val; - uint32_t tmp; - int index; - int shift; - uint64_t *table; - table = (uint64_t *)&env->vfp.regs[rn]; + uint32_t val, shift; + uint64_t *table = vn; + val = 0; for (shift = 0; shift < 32; shift += 8) { - index = (ireg >> shift) & 0xff; + uint32_t index = (ireg >> shift) & 0xff; if (index < maxindex) { - tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; + uint32_t tmp = (table[index >> 3] >> ((index & 7) << 3)) & 0xff; val |= tmp << shift; } else { val |= def & (0xff << shift); diff --git a/target/arm/translate-a64.c b/target/arm/translate-a64.c index 70c1e08a36..eed64c73e5 100644 --- a/target/arm/translate-a64.c +++ b/target/arm/translate-a64.c @@ -80,8 +80,9 @@ typedef void NeonGenWidenFn(TCGv_i64, TCGv_i32); typedef void NeonGenTwoSingleOPFn(TCGv_i32, TCGv_i32, TCGv_i32, TCGv_ptr); typedef void NeonGenTwoDoubleOPFn(TCGv_i64, TCGv_i64, TCGv_i64, TCGv_ptr); typedef void NeonGenOneOpFn(TCGv_i64, TCGv_i64); -typedef void CryptoTwoOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32); -typedef void CryptoThreeOpEnvFn(TCGv_ptr, TCGv_i32, TCGv_i32, TCGv_i32); +typedef void CryptoTwoOpFn(TCGv_ptr, TCGv_ptr); +typedef void CryptoThreeOpIntFn(TCGv_ptr, TCGv_ptr, TCGv_i32); +typedef void CryptoThreeOpFn(TCGv_ptr, TCGv_ptr, TCGv_ptr); /* initialize TCG globals. */ void a64_translate_init(void) @@ -163,15 +164,12 @@ void aarch64_cpu_dump_state(CPUState *cs, FILE *f, if (flags & CPU_DUMP_FPU) { int numvfpregs = 32; - for (i = 0; i < numvfpregs; i += 2) { - uint64_t vlo = float64_val(env->vfp.regs[i * 2]); - uint64_t vhi = float64_val(env->vfp.regs[(i * 2) + 1]); - cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 " ", - i, vhi, vlo); - vlo = float64_val(env->vfp.regs[(i + 1) * 2]); - vhi = float64_val(env->vfp.regs[((i + 1) * 2) + 1]); - cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "\n", - i + 1, vhi, vlo); + for (i = 0; i < numvfpregs; i++) { + uint64_t *q = aa64_vfp_qreg(env, i); + uint64_t vlo = q[0]; + uint64_t vhi = q[1]; + cpu_fprintf(f, "q%02d=%016" PRIx64 ":%016" PRIx64 "%c", + i, vhi, vlo, (i & 1 ? '\n' : ' ')); } cpu_fprintf(f, "FPCR: %08x FPSR: %08x\n", vfp_get_fpcr(env), vfp_get_fpsr(env)); @@ -535,6 +533,21 @@ static inline int vec_reg_offset(DisasContext *s, int regno, return offs; } +/* Return the offset info CPUARMState of the "whole" vector register Qn. */ +static inline int vec_full_reg_offset(DisasContext *s, int regno) +{ + assert_fp_access_checked(s); + return offsetof(CPUARMState, vfp.regs[regno * 2]); +} + +/* Return a newly allocated pointer to the vector register. */ +static TCGv_ptr vec_full_reg_ptr(DisasContext *s, int regno) +{ + TCGv_ptr ret = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, vec_full_reg_offset(s, regno)); + return ret; +} + /* Return the offset into CPUARMState of a slice (from * the least significant end) of FP register Qn (ie * Dn, Sn, Hn or Bn). @@ -542,19 +555,13 @@ static inline int vec_reg_offset(DisasContext *s, int regno, */ static inline int fp_reg_offset(DisasContext *s, int regno, TCGMemOp size) { - int offs = offsetof(CPUARMState, vfp.regs[regno * 2]); -#ifdef HOST_WORDS_BIGENDIAN - offs += (8 - (1 << size)); -#endif - assert_fp_access_checked(s); - return offs; + return vec_reg_offset(s, regno, 0, size); } /* Offset of the high half of the 128 bit vector Qn */ static inline int fp_reg_hi_offset(DisasContext *s, int regno) { - assert_fp_access_checked(s); - return offsetof(CPUARMState, vfp.regs[regno * 2 + 1]); + return vec_reg_offset(s, regno, 1, MO_64); } /* Convenience accessors for reading and writing single and double @@ -10949,8 +10956,9 @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn) int rn = extract32(insn, 5, 5); int rd = extract32(insn, 0, 5); int decrypt; - TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_decrypt; - CryptoThreeOpEnvFn *genfn; + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; + TCGv_i32 tcg_decrypt; + CryptoThreeOpIntFn *genfn; if (!arm_dc_feature(s, ARM_FEATURE_V8_AES) || size != 0) { @@ -10984,18 +10992,14 @@ static void disas_crypto_aes(DisasContext *s, uint32_t insn) return; } - /* Note that we convert the Vx register indexes into the - * index within the vfp.regs[] array, so we can share the - * helper with the AArch32 instructions. - */ - tcg_rd_regno = tcg_const_i32(rd << 1); - tcg_rn_regno = tcg_const_i32(rn << 1); + tcg_rd_ptr = vec_full_reg_ptr(s, rd); + tcg_rn_ptr = vec_full_reg_ptr(s, rn); tcg_decrypt = tcg_const_i32(decrypt); - genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_decrypt); + genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_decrypt); - tcg_temp_free_i32(tcg_rd_regno); - tcg_temp_free_i32(tcg_rn_regno); + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); tcg_temp_free_i32(tcg_decrypt); } @@ -11012,8 +11016,8 @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) int rm = extract32(insn, 16, 5); int rn = extract32(insn, 5, 5); int rd = extract32(insn, 0, 5); - CryptoThreeOpEnvFn *genfn; - TCGv_i32 tcg_rd_regno, tcg_rn_regno, tcg_rm_regno; + CryptoThreeOpFn *genfn; + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr; int feature = ARM_FEATURE_V8_SHA256; if (size != 0) { @@ -11052,23 +11056,23 @@ static void disas_crypto_three_reg_sha(DisasContext *s, uint32_t insn) return; } - tcg_rd_regno = tcg_const_i32(rd << 1); - tcg_rn_regno = tcg_const_i32(rn << 1); - tcg_rm_regno = tcg_const_i32(rm << 1); + tcg_rd_ptr = vec_full_reg_ptr(s, rd); + tcg_rn_ptr = vec_full_reg_ptr(s, rn); + tcg_rm_ptr = vec_full_reg_ptr(s, rm); if (genfn) { - genfn(cpu_env, tcg_rd_regno, tcg_rn_regno, tcg_rm_regno); + genfn(tcg_rd_ptr, tcg_rn_ptr, tcg_rm_ptr); } else { TCGv_i32 tcg_opcode = tcg_const_i32(opcode); - gen_helper_crypto_sha1_3reg(cpu_env, tcg_rd_regno, - tcg_rn_regno, tcg_rm_regno, tcg_opcode); + gen_helper_crypto_sha1_3reg(tcg_rd_ptr, tcg_rn_ptr, + tcg_rm_ptr, tcg_opcode); tcg_temp_free_i32(tcg_opcode); } - tcg_temp_free_i32(tcg_rd_regno); - tcg_temp_free_i32(tcg_rn_regno); - tcg_temp_free_i32(tcg_rm_regno); + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); + tcg_temp_free_ptr(tcg_rm_ptr); } /* Crypto two-reg SHA @@ -11083,9 +11087,9 @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) int opcode = extract32(insn, 12, 5); int rn = extract32(insn, 5, 5); int rd = extract32(insn, 0, 5); - CryptoTwoOpEnvFn *genfn; + CryptoTwoOpFn *genfn; int feature; - TCGv_i32 tcg_rd_regno, tcg_rn_regno; + TCGv_ptr tcg_rd_ptr, tcg_rn_ptr; if (size != 0) { unallocated_encoding(s); @@ -11119,13 +11123,13 @@ static void disas_crypto_two_reg_sha(DisasContext *s, uint32_t insn) return; } - tcg_rd_regno = tcg_const_i32(rd << 1); - tcg_rn_regno = tcg_const_i32(rn << 1); + tcg_rd_ptr = vec_full_reg_ptr(s, rd); + tcg_rn_ptr = vec_full_reg_ptr(s, rn); - genfn(cpu_env, tcg_rd_regno, tcg_rn_regno); + genfn(tcg_rd_ptr, tcg_rn_ptr); - tcg_temp_free_i32(tcg_rd_regno); - tcg_temp_free_i32(tcg_rn_regno); + tcg_temp_free_ptr(tcg_rd_ptr); + tcg_temp_free_ptr(tcg_rn_ptr); } /* C3.6 Data processing - SIMD, inc Crypto diff --git a/target/arm/translate.c b/target/arm/translate.c index 781be1e219..55826b7e5a 100644 --- a/target/arm/translate.c +++ b/target/arm/translate.c @@ -1515,14 +1515,16 @@ static inline void gen_vfp_st(DisasContext *s, int dp, TCGv_i32 addr) static inline long vfp_reg_offset (int dp, int reg) { - if (dp) + if (dp) { return offsetof(CPUARMState, vfp.regs[reg]); - else if (reg & 1) { - return offsetof(CPUARMState, vfp.regs[reg >> 1]) - + offsetof(CPU_DoubleU, l.upper); } else { - return offsetof(CPUARMState, vfp.regs[reg >> 1]) - + offsetof(CPU_DoubleU, l.lower); + long ofs = offsetof(CPUARMState, vfp.regs[reg >> 1]); + if (reg & 1) { + ofs += offsetof(CPU_DoubleU, l.upper); + } else { + ofs += offsetof(CPU_DoubleU, l.lower); + } + return ofs; } } @@ -1559,6 +1561,13 @@ static inline void neon_store_reg64(TCGv_i64 var, int reg) tcg_gen_st_i64(var, cpu_env, vfp_reg_offset(1, reg)); } +static TCGv_ptr vfp_reg_ptr(bool dp, int reg) +{ + TCGv_ptr ret = tcg_temp_new_ptr(); + tcg_gen_addi_ptr(ret, cpu_env, vfp_reg_offset(dp, reg)); + return ret; +} + #define tcg_gen_ld_f32 tcg_gen_ld_i32 #define tcg_gen_ld_f64 tcg_gen_ld_i64 #define tcg_gen_st_f32 tcg_gen_st_i32 @@ -4680,22 +4689,23 @@ static inline TCGv_i32 neon_get_scalar(int size, int reg) static int gen_neon_unzip(int rd, int rm, int size, int q) { - TCGv_i32 tmp, tmp2; + TCGv_ptr pd, pm; + if (!q && size == 2) { return 1; } - tmp = tcg_const_i32(rd); - tmp2 = tcg_const_i32(rm); + pd = vfp_reg_ptr(true, rd); + pm = vfp_reg_ptr(true, rm); if (q) { switch (size) { case 0: - gen_helper_neon_qunzip8(cpu_env, tmp, tmp2); + gen_helper_neon_qunzip8(pd, pm); break; case 1: - gen_helper_neon_qunzip16(cpu_env, tmp, tmp2); + gen_helper_neon_qunzip16(pd, pm); break; case 2: - gen_helper_neon_qunzip32(cpu_env, tmp, tmp2); + gen_helper_neon_qunzip32(pd, pm); break; default: abort(); @@ -4703,38 +4713,39 @@ static int gen_neon_unzip(int rd, int rm, int size, int q) } else { switch (size) { case 0: - gen_helper_neon_unzip8(cpu_env, tmp, tmp2); + gen_helper_neon_unzip8(pd, pm); break; case 1: - gen_helper_neon_unzip16(cpu_env, tmp, tmp2); + gen_helper_neon_unzip16(pd, pm); break; default: abort(); } } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(pd); + tcg_temp_free_ptr(pm); return 0; } static int gen_neon_zip(int rd, int rm, int size, int q) { - TCGv_i32 tmp, tmp2; + TCGv_ptr pd, pm; + if (!q && size == 2) { return 1; } - tmp = tcg_const_i32(rd); - tmp2 = tcg_const_i32(rm); + pd = vfp_reg_ptr(true, rd); + pm = vfp_reg_ptr(true, rm); if (q) { switch (size) { case 0: - gen_helper_neon_qzip8(cpu_env, tmp, tmp2); + gen_helper_neon_qzip8(pd, pm); break; case 1: - gen_helper_neon_qzip16(cpu_env, tmp, tmp2); + gen_helper_neon_qzip16(pd, pm); break; case 2: - gen_helper_neon_qzip32(cpu_env, tmp, tmp2); + gen_helper_neon_qzip32(pd, pm); break; default: abort(); @@ -4742,17 +4753,17 @@ static int gen_neon_zip(int rd, int rm, int size, int q) } else { switch (size) { case 0: - gen_helper_neon_zip8(cpu_env, tmp, tmp2); + gen_helper_neon_zip8(pd, pm); break; case 1: - gen_helper_neon_zip16(cpu_env, tmp, tmp2); + gen_helper_neon_zip16(pd, pm); break; default: abort(); } } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(pd); + tcg_temp_free_ptr(pm); return 0; } @@ -5597,6 +5608,7 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) int u; uint32_t imm, mask; TCGv_i32 tmp, tmp2, tmp3, tmp4, tmp5; + TCGv_ptr ptr1, ptr2, ptr3; TCGv_i64 tmp64; /* FIXME: this access check should not take precedence over UNDEF @@ -5643,34 +5655,34 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) { return 1; } - tmp = tcg_const_i32(rd); - tmp2 = tcg_const_i32(rn); - tmp3 = tcg_const_i32(rm); + ptr1 = vfp_reg_ptr(true, rd); + ptr2 = vfp_reg_ptr(true, rn); + ptr3 = vfp_reg_ptr(true, rm); tmp4 = tcg_const_i32(size); - gen_helper_crypto_sha1_3reg(cpu_env, tmp, tmp2, tmp3, tmp4); + gen_helper_crypto_sha1_3reg(ptr1, ptr2, ptr3, tmp4); tcg_temp_free_i32(tmp4); } else { /* SHA-256 */ if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA256) || size == 3) { return 1; } - tmp = tcg_const_i32(rd); - tmp2 = tcg_const_i32(rn); - tmp3 = tcg_const_i32(rm); + ptr1 = vfp_reg_ptr(true, rd); + ptr2 = vfp_reg_ptr(true, rn); + ptr3 = vfp_reg_ptr(true, rm); switch (size) { case 0: - gen_helper_crypto_sha256h(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_sha256h(ptr1, ptr2, ptr3); break; case 1: - gen_helper_crypto_sha256h2(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_sha256h2(ptr1, ptr2, ptr3); break; case 2: - gen_helper_crypto_sha256su1(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_sha256su1(ptr1, ptr2, ptr3); break; } } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); - tcg_temp_free_i32(tmp3); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); + tcg_temp_free_ptr(ptr3); return 0; } if (size == 3 && op != NEON_3R_LOGIC) { @@ -7159,8 +7171,8 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) || ((rm | rd) & 1)) { return 1; } - tmp = tcg_const_i32(rd); - tmp2 = tcg_const_i32(rm); + ptr1 = vfp_reg_ptr(true, rd); + ptr2 = vfp_reg_ptr(true, rm); /* Bit 6 is the lowest opcode bit; it distinguishes between * encryption (AESE/AESMC) and decryption (AESD/AESIMC) @@ -7168,12 +7180,12 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tmp3 = tcg_const_i32(extract32(insn, 6, 1)); if (op == NEON_2RM_AESE) { - gen_helper_crypto_aese(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_aese(ptr1, ptr2, tmp3); } else { - gen_helper_crypto_aesmc(cpu_env, tmp, tmp2, tmp3); + gen_helper_crypto_aesmc(ptr1, ptr2, tmp3); } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); tcg_temp_free_i32(tmp3); break; case NEON_2RM_SHA1H: @@ -7181,13 +7193,13 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) || ((rm | rd) & 1)) { return 1; } - tmp = tcg_const_i32(rd); - tmp2 = tcg_const_i32(rm); + ptr1 = vfp_reg_ptr(true, rd); + ptr2 = vfp_reg_ptr(true, rm); - gen_helper_crypto_sha1h(cpu_env, tmp, tmp2); + gen_helper_crypto_sha1h(ptr1, ptr2); - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); break; case NEON_2RM_SHA1SU1: if ((rm | rd) & 1) { @@ -7201,15 +7213,15 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) } else if (!arm_dc_feature(s, ARM_FEATURE_V8_SHA1)) { return 1; } - tmp = tcg_const_i32(rd); - tmp2 = tcg_const_i32(rm); + ptr1 = vfp_reg_ptr(true, rd); + ptr2 = vfp_reg_ptr(true, rm); if (q) { - gen_helper_crypto_sha256su0(cpu_env, tmp, tmp2); + gen_helper_crypto_sha256su0(ptr1, ptr2); } else { - gen_helper_crypto_sha1su1(cpu_env, tmp, tmp2); + gen_helper_crypto_sha1su1(ptr1, ptr2); } - tcg_temp_free_i32(tmp); - tcg_temp_free_i32(tmp2); + tcg_temp_free_ptr(ptr1); + tcg_temp_free_ptr(ptr2); break; default: elementwise: @@ -7534,9 +7546,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_movi_i32(tmp, 0); } tmp2 = neon_load_reg(rm, 0); - tmp4 = tcg_const_i32(rn); + ptr1 = vfp_reg_ptr(true, rn); tmp5 = tcg_const_i32(n); - gen_helper_neon_tbl(tmp2, cpu_env, tmp2, tmp, tmp4, tmp5); + gen_helper_neon_tbl(tmp2, tmp2, tmp, ptr1, tmp5); tcg_temp_free_i32(tmp); if (insn & (1 << 6)) { tmp = neon_load_reg(rd, 1); @@ -7545,9 +7557,9 @@ static int disas_neon_data_insn(DisasContext *s, uint32_t insn) tcg_gen_movi_i32(tmp, 0); } tmp3 = neon_load_reg(rm, 1); - gen_helper_neon_tbl(tmp3, cpu_env, tmp3, tmp, tmp4, tmp5); + gen_helper_neon_tbl(tmp3, tmp3, tmp, ptr1, tmp5); tcg_temp_free_i32(tmp5); - tcg_temp_free_i32(tmp4); + tcg_temp_free_ptr(ptr1); neon_store_reg(rd, 0, tmp2); neon_store_reg(rd, 1, tmp3); tcg_temp_free_i32(tmp); @@ -12562,7 +12574,7 @@ void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, numvfpregs += 16; } for (i = 0; i < numvfpregs; i++) { - uint64_t v = float64_val(env->vfp.regs[i]); + uint64_t v = *aa32_vfp_dreg(env, i); cpu_fprintf(f, "s%02d=%08x s%02d=%08x d%02d=%016" PRIx64 "\n", i * 2, (uint32_t)v, i * 2 + 1, (uint32_t)(v >> 32), diff --git a/target/arm/translate.h b/target/arm/translate.h index cd7313ace7..3f4df91e5e 100644 --- a/target/arm/translate.h +++ b/target/arm/translate.h @@ -108,7 +108,7 @@ static inline int default_exception_el(DisasContext *s) ? 3 : MAX(1, s->current_el); } -static void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) +static inline void disas_set_insn_syndrome(DisasContext *s, uint32_t syn) { /* We don't need to save all of the syndrome so we mask and shift * out unneeded bits to help the sleb128 encoder do a better job. diff --git a/ui/Makefile.objs b/ui/Makefile.objs index ec8533d6d9..99195884b0 100644 --- a/ui/Makefile.objs +++ b/ui/Makefile.objs @@ -11,11 +11,12 @@ common-obj-y += keymaps.o console.o cursor.o qemu-pixman.o common-obj-y += input.o input-keymap.o input-legacy.o common-obj-$(CONFIG_LINUX) += input-linux.o common-obj-$(CONFIG_SPICE) += spice-core.o spice-input.o spice-display.o -common-obj-$(CONFIG_SDL) += sdl.mo x_keymap.o +common-obj-$(CONFIG_SDL) += sdl.mo common-obj-$(CONFIG_COCOA) += cocoa.o common-obj-$(CONFIG_CURSES) += curses.o common-obj-$(CONFIG_VNC) += $(vnc-obj-y) -common-obj-$(CONFIG_GTK) += gtk.o x_keymap.o +common-obj-$(CONFIG_GTK) += gtk.o +common-obj-$(if $(CONFIG_WIN32),n,$(if $(CONFIG_SDL),y,$(CONFIG_GTK))) += x_keymap.o ifeq ($(CONFIG_SDLABI),1.2) sdl.mo-objs := sdl.o sdl_zoom.o diff --git a/ui/gtk.c b/ui/gtk.c index f3b7567984..f0ad63e431 100644 --- a/ui/gtk.c +++ b/ui/gtk.c @@ -52,7 +52,6 @@ #include "ui/input.h" #include "sysemu/sysemu.h" #include "qmp-commands.h" -#include "x_keymap.h" #include "keymaps.h" #include "chardev/char.h" #include "qom/object.h" @@ -65,6 +64,48 @@ #define VC_SCALE_MIN 0.25 #define VC_SCALE_STEP 0.25 +#ifdef GDK_WINDOWING_X11 +#include "ui/x_keymap.h" + +/* Gtk2 compat */ +#ifndef GDK_IS_X11_DISPLAY +#define GDK_IS_X11_DISPLAY(dpy) (dpy != NULL) +#endif +#endif + + +#ifdef GDK_WINDOWING_WAYLAND +/* Gtk2 compat */ +#ifndef GDK_IS_WAYLAND_DISPLAY +#define GDK_IS_WAYLAND_DISPLAY(dpy) (dpy != NULL) +#endif +#endif + + +#ifdef GDK_WINDOWING_WIN32 +/* Gtk2 compat */ +#ifndef GDK_IS_WIN32_DISPLAY +#define GDK_IS_WIN32_DISPLAY(dpy) (dpy != NULL) +#endif +#endif + + +#ifdef GDK_WINDOWING_BROADWAY +/* Gtk2 compat */ +#ifndef GDK_IS_BROADWAY_DISPLAY +#define GDK_IS_BROADWAY_DISPLAY(dpy) (dpy != NULL) +#endif +#endif + + +#ifdef GDK_WINDOWING_QUARTZ +/* Gtk2 compat */ +#ifndef GDK_IS_QUARTZ_DISPLAY +#define GDK_IS_QUARTZ_DISPLAY(dpy) (dpy != NULL) +#endif +#endif + + #if !defined(CONFIG_VTE) # define VTE_CHECK_VERSION(a, b, c) 0 #endif @@ -123,10 +164,19 @@ #define HOTKEY_MODIFIERS (GDK_CONTROL_MASK | GDK_MOD1_MASK) static const int modifier_keycode[] = { - /* shift, control, alt keys, meta keys, both left & right */ - 0x2a, 0x36, 0x1d, 0x9d, 0x38, 0xb8, 0xdb, 0xdd, + Q_KEY_CODE_SHIFT, + Q_KEY_CODE_SHIFT_R, + Q_KEY_CODE_CTRL, + Q_KEY_CODE_CTRL_R, + Q_KEY_CODE_ALT, + Q_KEY_CODE_ALT_R, + Q_KEY_CODE_META_L, + Q_KEY_CODE_META_R, }; +static const guint16 *keycode_map; +static size_t keycode_maplen; + struct GtkDisplayState { GtkWidget *window; @@ -178,7 +228,6 @@ struct GtkDisplayState { bool external_pause_update; bool modifier_pressed[ARRAY_SIZE(modifier_keycode)]; - bool has_evdev; bool ignore_keys; }; @@ -412,18 +461,18 @@ static void gd_update_full_redraw(VirtualConsole *vc) static void gtk_release_modifiers(GtkDisplayState *s) { VirtualConsole *vc = gd_vc_find_current(s); - int i, keycode; + int i, qcode; if (vc->type != GD_VC_GFX || !qemu_console_is_graphic(vc->gfx.dcl.con)) { return; } for (i = 0; i < ARRAY_SIZE(modifier_keycode); i++) { - keycode = modifier_keycode[i]; + qcode = modifier_keycode[i]; if (!s->modifier_pressed[i]) { continue; } - qemu_input_event_send_key_number(vc->gfx.dcl.con, keycode, false); + qemu_input_event_send_key_qcode(vc->gfx.dcl.con, qcode, false); s->modifier_pressed[i] = false; } } @@ -1057,47 +1106,75 @@ static gboolean gd_scroll_event(GtkWidget *widget, GdkEventScroll *scroll, return TRUE; } -static int gd_map_keycode(GtkDisplayState *s, GdkDisplay *dpy, int gdk_keycode) + +static const guint16 *gd_get_keymap(size_t *maplen) { - int qemu_keycode; + GdkDisplay *dpy = gdk_display_get_default(); + +#ifdef GDK_WINDOWING_X11 + if (GDK_IS_X11_DISPLAY(dpy)) { + trace_gd_keymap_windowing("x11"); + return qemu_xkeymap_mapping_table( + gdk_x11_display_get_xdisplay(dpy), maplen); + } +#endif + +#ifdef GDK_WINDOWING_WAYLAND + if (GDK_IS_WAYLAND_DISPLAY(dpy)) { + trace_gd_keymap_windowing("wayland"); + *maplen = qemu_input_map_xorgevdev_to_qcode_len; + return qemu_input_map_xorgevdev_to_qcode; + } +#endif #ifdef GDK_WINDOWING_WIN32 if (GDK_IS_WIN32_DISPLAY(dpy)) { - qemu_keycode = MapVirtualKey(gdk_keycode, MAPVK_VK_TO_VSC); - switch (qemu_keycode) { - case 103: /* alt gr */ - qemu_keycode = 56 | SCANCODE_GREY; - break; - } - return qemu_keycode; + trace_gd_keymap_windowing("win32"); + *maplen = qemu_input_map_win32_to_qcode_len; + return qemu_input_map_win32_to_qcode; } #endif - if (gdk_keycode < 9) { - qemu_keycode = 0; - } else if (gdk_keycode < 97) { - qemu_keycode = gdk_keycode - 8; -#ifdef GDK_WINDOWING_X11 - } else if (GDK_IS_X11_DISPLAY(dpy) && gdk_keycode < 158) { - if (s->has_evdev) { - qemu_keycode = translate_evdev_keycode(gdk_keycode - 97); - } else { - qemu_keycode = translate_xfree86_keycode(gdk_keycode - 97); - } +#ifdef GDK_WINDOWING_QUARTZ + if (GDK_IS_QUARTZ_DISPLAY(dpy)) { + trace_gd_keymap_windowing("quartz"); + *maplen = qemu_input_map_osx_to_qcode_len; + return qemu_input_map_osx_to_qcode; + } #endif -#ifdef GDK_WINDOWING_WAYLAND - } else if (GDK_IS_WAYLAND_DISPLAY(dpy) && gdk_keycode < 158) { - qemu_keycode = translate_evdev_keycode(gdk_keycode - 97); + +#ifdef GDK_WINDOWING_BROADWAY + if (GDK_IS_BROADWAY_DISPLAY(dpy)) { + trace_gd_keymap_windowing("broadway"); + g_warning("experimental: using broadway, x11 virtual keysym\n" + "mapping - with very limited support. See also\n" + "https://bugzilla.gnome.org/show_bug.cgi?id=700105"); + *maplen = qemu_input_map_x11_to_qcode_len; + return qemu_input_map_x11_to_qcode; + } #endif - } else if (gdk_keycode == 208) { /* Hiragana_Katakana */ - qemu_keycode = 0x70; - } else if (gdk_keycode == 211) { /* backslash */ - qemu_keycode = 0x73; - } else { - qemu_keycode = 0; + + g_warning("Unsupported GDK Windowing platform.\n" + "Disabling extended keycode tables.\n" + "Please report to qemu-devel@nongnu.org\n" + "including the following information:\n" + "\n" + " - Operating system\n" + " - GDK Windowing system build\n"); + return NULL; +} + + +static int gd_map_keycode(int scancode) +{ + if (!keycode_map) { + return 0; + } + if (scancode > keycode_maplen) { + return 0; } - return qemu_keycode; + return keycode_map[scancode]; } static gboolean gd_text_key_down(GtkWidget *widget, @@ -1111,9 +1188,7 @@ static gboolean gd_text_key_down(GtkWidget *widget, } else if (key->length) { kbd_put_string_console(con, key->string, key->length); } else { - int num = gd_map_keycode(vc->s, gtk_widget_get_display(widget), - key->hardware_keycode); - int qcode = qemu_input_key_number_to_qcode(num); + int qcode = gd_map_keycode(key->hardware_keycode); kbd_put_qcode_console(con, qcode); } return TRUE; @@ -1123,8 +1198,7 @@ static gboolean gd_key_event(GtkWidget *widget, GdkEventKey *key, void *opaque) { VirtualConsole *vc = opaque; GtkDisplayState *s = vc->s; - int gdk_keycode = key->hardware_keycode; - int qemu_keycode; + int qcode; int i; if (s->ignore_keys) { @@ -1132,26 +1206,38 @@ static gboolean gd_key_event(GtkWidget *widget, GdkEventKey *key, void *opaque) return TRUE; } - if (key->keyval == GDK_KEY_Pause) { +#ifdef WIN32 + /* on windows, we ought to ignore the reserved key event? */ + if (key->hardware_keycode == 0xff) + return false; +#endif + + if (key->keyval == GDK_KEY_Pause +#ifdef G_OS_WIN32 + /* for some reason GDK does not fill keyval for VK_PAUSE + * See https://bugzilla.gnome.org/show_bug.cgi?id=769214 + */ + || key->hardware_keycode == VK_PAUSE +#endif + ) { qemu_input_event_send_key_qcode(vc->gfx.dcl.con, Q_KEY_CODE_PAUSE, key->type == GDK_KEY_PRESS); return TRUE; } - qemu_keycode = gd_map_keycode(s, gtk_widget_get_display(widget), - gdk_keycode); + qcode = gd_map_keycode(key->hardware_keycode); - trace_gd_key_event(vc->label, gdk_keycode, qemu_keycode, + trace_gd_key_event(vc->label, key->hardware_keycode, qcode, (key->type == GDK_KEY_PRESS) ? "down" : "up"); for (i = 0; i < ARRAY_SIZE(modifier_keycode); i++) { - if (qemu_keycode == modifier_keycode[i]) { + if (qcode == modifier_keycode[i]) { s->modifier_pressed[i] = (key->type == GDK_KEY_PRESS); } } - qemu_input_event_send_key_number(vc->gfx.dcl.con, qemu_keycode, - key->type == GDK_KEY_PRESS); + qemu_input_event_send_key_qcode(vc->gfx.dcl.con, qcode, + key->type == GDK_KEY_PRESS); return TRUE; } @@ -2200,38 +2286,6 @@ static void gd_create_menus(GtkDisplayState *s) gtk_window_add_accel_group(GTK_WINDOW(s->window), s->accel_group); } -static void gd_set_keycode_type(GtkDisplayState *s) -{ -#ifdef GDK_WINDOWING_X11 - GdkDisplay *display = gtk_widget_get_display(s->window); - if (GDK_IS_X11_DISPLAY(display)) { - Display *x11_display = gdk_x11_display_get_xdisplay(display); - XkbDescPtr desc = XkbGetMap(x11_display, XkbGBN_AllComponentsMask, - XkbUseCoreKbd); - char *keycodes = NULL; - - if (desc && - (XkbGetNames(x11_display, XkbKeycodesNameMask, desc) == Success)) { - keycodes = XGetAtomName(x11_display, desc->names->keycodes); - } - if (keycodes == NULL) { - fprintf(stderr, "could not lookup keycode name\n"); - } else if (strstart(keycodes, "evdev", NULL)) { - s->has_evdev = true; - } else if (!strstart(keycodes, "xfree86", NULL)) { - fprintf(stderr, "unknown keycodes `%s', please report to " - "qemu-devel@nongnu.org\n", keycodes); - } - - if (desc) { - XkbFreeKeyboard(desc, XkbGBN_AllComponentsMask, True); - } - if (keycodes) { - XFree(keycodes); - } - } -#endif -} static gboolean gtkinit; @@ -2339,8 +2393,6 @@ void gtk_display_init(DisplayState *ds, bool full_screen, bool grab_on_hover) if (grab_on_hover) { gtk_menu_item_activate(GTK_MENU_ITEM(s->grab_on_hover_item)); } - - gd_set_keycode_type(s); } void early_gtk_display_init(int opengl) @@ -2387,6 +2439,8 @@ void early_gtk_display_init(int opengl) break; } + keycode_map = gd_get_keymap(&keycode_maplen); + #if defined(CONFIG_VTE) type_register(&char_gd_vc_type_info); #endif diff --git a/ui/input-keymap.c b/ui/input-keymap.c index 663986a17b..95b1e0cbfa 100644 --- a/ui/input-keymap.c +++ b/ui/input-keymap.c @@ -5,10 +5,18 @@ #include "standard-headers/linux/input.h" +#include "ui/input-keymap-atset1-to-qcode.c" #include "ui/input-keymap-linux-to-qcode.c" #include "ui/input-keymap-qcode-to-qnum.c" #include "ui/input-keymap-qnum-to-qcode.c" #include "ui/input-keymap-qcode-to-linux.c" +#include "ui/input-keymap-usb-to-qcode.c" +#include "ui/input-keymap-win32-to-qcode.c" +#include "ui/input-keymap-x11-to-qcode.c" +#include "ui/input-keymap-xorgevdev-to-qcode.c" +#include "ui/input-keymap-xorgkbd-to-qcode.c" +#include "ui/input-keymap-xorgxquartz-to-qcode.c" +#include "ui/input-keymap-xorgxwin-to-qcode.c" int qemu_input_linux_to_qcode(unsigned int lnx) { diff --git a/ui/sdl.c b/ui/sdl.c index 7b71a9ac58..c8f102bb9f 100644 --- a/ui/sdl.c +++ b/ui/sdl.c @@ -34,7 +34,9 @@ #include "ui/console.h" #include "ui/input.h" #include "sysemu/sysemu.h" +#ifndef WIN32 #include "x_keymap.h" +#endif #include "sdl_zoom.h" static DisplayChangeListener *dcl; @@ -48,7 +50,6 @@ static int gui_saved_width; static int gui_saved_height; static int gui_saved_grab; static int gui_fullscreen; -static int gui_noframe; static int gui_key_modifier_pressed; static int gui_keysym; static int gui_grab_code = KMOD_LALT | KMOD_LCTRL; @@ -63,6 +64,8 @@ static SDL_PixelFormat host_format; static int scaling_active = 0; static Notifier mouse_mode_notifier; static int idle_counter; +static const guint16 *keycode_map; +static size_t keycode_maplen; #define SDL_REFRESH_INTERVAL_BUSY 10 #define SDL_MAX_IDLE_COUNT (2 * GUI_REFRESH_INTERVAL_DEFAULT \ @@ -114,8 +117,9 @@ static void do_sdl_resize(int width, int height, int bpp) } else { flags |= SDL_RESIZABLE; } - if (gui_noframe) + if (no_frame) { flags |= SDL_NOFRAME; + } tmp_screen = SDL_SetVideoMode(width, height, bpp, flags); if (!real_screen) { @@ -208,94 +212,45 @@ static uint8_t sdl_keyevent_to_keycode_generic(const SDL_KeyboardEvent *ev) return keysym2scancode(kbd_layout, keysym) & SCANCODE_KEYMASK; } -/* specific keyboard conversions from scan codes */ -#if defined(_WIN32) - -static uint8_t sdl_keyevent_to_keycode(const SDL_KeyboardEvent *ev) +static const guint16 *sdl_get_keymap(size_t *maplen) { - return ev->keysym.scancode; -} - +#if defined(WIN32) + *maplen = qemu_input_map_atset1_to_qcode_len; + return qemu_input_map_atset1_to_qcode; #else - #if defined(SDL_VIDEO_DRIVER_X11) -#include <X11/XKBlib.h> - -static int check_for_evdev(void) -{ SDL_SysWMinfo info; - XkbDescPtr desc = NULL; - int has_evdev = 0; - char *keycodes = NULL; SDL_VERSION(&info.version); - if (!SDL_GetWMInfo(&info)) { - return 0; - } - desc = XkbGetMap(info.info.x11.display, - XkbGBN_AllComponentsMask, - XkbUseCoreKbd); - if (desc && - (XkbGetNames(info.info.x11.display, - XkbKeycodesNameMask, desc) == Success)) { - keycodes = XGetAtomName(info.info.x11.display, desc->names->keycodes); - if (keycodes == NULL) { - fprintf(stderr, "could not lookup keycode name\n"); - } else if (strstart(keycodes, "evdev", NULL)) { - has_evdev = 1; - } else if (!strstart(keycodes, "xfree86", NULL)) { - fprintf(stderr, "unknown keycodes `%s', please report to " - "qemu-devel@nongnu.org\n", keycodes); - } - } - - if (desc) { - XkbFreeKeyboard(desc, XkbGBN_AllComponentsMask, True); + if (SDL_GetWMInfo(&info) > 0) { + return qemu_xkeymap_mapping_table( + info.info.x11.display, maplen); } - if (keycodes) { - XFree(keycodes); - } - return has_evdev; -} -#else -static int check_for_evdev(void) -{ - return 0; -} #endif + g_warning("Unsupported SDL video driver / platform.\n" + "Assuming Linux KBD scancodes, but probably wrong.\n" + "Please report to qemu-devel@nongnu.org\n" + "including the following information:\n" + "\n" + " - Operating system\n" + " - SDL video driver\n"); + *maplen = qemu_input_map_xorgkbd_to_qcode_len; + return qemu_input_map_xorgkbd_to_qcode; +#endif +} static uint8_t sdl_keyevent_to_keycode(const SDL_KeyboardEvent *ev) { - int keycode; - static int has_evdev = -1; - - if (has_evdev == -1) - has_evdev = check_for_evdev(); - - keycode = ev->keysym.scancode; - - if (keycode < 9) { - keycode = 0; - } else if (keycode < 97) { - keycode -= 8; /* just an offset */ - } else if (keycode < 158) { - /* use conversion table */ - if (has_evdev) - keycode = translate_evdev_keycode(keycode - 97); - else - keycode = translate_xfree86_keycode(keycode - 97); - } else if (keycode == 208) { /* Hiragana_Katakana */ - keycode = 0x70; - } else if (keycode == 211) { /* backslash */ - keycode = 0x73; - } else { - keycode = 0; + if (!keycode_map) { + return 0; + } + if (ev->keysym.scancode > keycode_maplen) { + return 0; } - return keycode; -} -#endif + return keycode_map[ev->keysym.scancode]; +} static void reset_keys(void) { @@ -368,11 +323,11 @@ static void sdl_update_caption(void) status = " [Stopped]"; else if (gui_grab) { if (alt_grab) - status = " - Press Ctrl-Alt-Shift to exit mouse grab"; + status = " - Press Ctrl-Alt-Shift-G to exit mouse grab"; else if (ctrl_grab) - status = " - Press Right-Ctrl to exit mouse grab"; + status = " - Press Right-Ctrl-G to exit mouse grab"; else - status = " - Press Ctrl-Alt to exit mouse grab"; + status = " - Press Ctrl-Alt-G to exit mouse grab"; } if (qemu_name) { @@ -576,6 +531,16 @@ static void handle_keydown(SDL_Event *ev) toggle_full_screen(); gui_keysym = 1; break; + case 0x22: /* 'g' key */ + if (!gui_grab) { + if (qemu_console_is_graphic(NULL)) { + sdl_grab_start(); + } + } else if (!gui_fullscreen) { + sdl_grab_end(); + } + gui_keysym = 1; + break; case 0x16: /* 'u' key on US keyboard */ if (scaling_active) { scaling_active = 0; @@ -711,20 +676,6 @@ static void handle_keyup(SDL_Event *ev) } if (!mod_state && gui_key_modifier_pressed) { gui_key_modifier_pressed = 0; - if (gui_keysym == 0) { - /* exit/enter grab if pressing Ctrl-Alt */ - if (!gui_grab) { - if (qemu_console_is_graphic(NULL)) { - sdl_grab_start(); - } - } else if (!gui_fullscreen) { - sdl_grab_end(); - } - /* SDL does not send back all the modifiers key, so we must - * correct it. */ - reset_keys(); - return; - } gui_keysym = 0; } if (qemu_console_is_graphic(NULL) && !gui_keysym) { @@ -944,7 +895,7 @@ void sdl_display_early_init(int opengl) } } -void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) +void sdl_display_init(DisplayState *ds, int full_screen) { int flags; uint8_t data = 0; @@ -963,8 +914,8 @@ void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) exit(1); } - if (no_frame) - gui_noframe = 1; + g_printerr("Running QEMU with SDL 1.2 is deprecated, and will be removed\n" + "in a future release. Please switch to SDL 2.0 instead\n"); if (!full_screen) { setenv("SDL_VIDEO_ALLOW_SCREENSAVER", "1", 0); @@ -995,6 +946,8 @@ void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) vi = SDL_GetVideoInfo(); host_format = *(vi->vfmt); + keycode_map = sdl_get_keymap(&keycode_maplen); + /* Load a 32x32x4 image. White pixels are transparent. */ filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, "qemu-icon.bmp"); if (filename) { diff --git a/ui/sdl2-input.c b/ui/sdl2-input.c index 6e315ae800..605d781971 100644 --- a/ui/sdl2-input.c +++ b/ui/sdl2-input.c @@ -30,8 +30,6 @@ #include "ui/sdl2.h" #include "sysemu/sysemu.h" -#include "sdl2-keymap.h" - static uint8_t modifiers_state[SDL_NUM_SCANCODES]; void sdl2_reset_keys(struct sdl2_console *scon) @@ -39,9 +37,11 @@ void sdl2_reset_keys(struct sdl2_console *scon) QemuConsole *con = scon ? scon->dcl.con : NULL; int i; - for (i = 0; i < SDL_NUM_SCANCODES; i++) { + for (i = 0 ; + i < SDL_NUM_SCANCODES && i < qemu_input_map_usb_to_qcode_len ; + i++) { if (modifiers_state[i]) { - int qcode = sdl2_scancode_to_qcode[i]; + int qcode = qemu_input_map_usb_to_qcode[i]; qemu_input_event_send_key_qcode(con, qcode, false); modifiers_state[i] = 0; } @@ -51,9 +51,15 @@ void sdl2_reset_keys(struct sdl2_console *scon) void sdl2_process_key(struct sdl2_console *scon, SDL_KeyboardEvent *ev) { - int qcode = sdl2_scancode_to_qcode[ev->keysym.scancode]; + int qcode; QemuConsole *con = scon ? scon->dcl.con : NULL; + if (ev->keysym.scancode >= qemu_input_map_usb_to_qcode_len) { + return; + } + + qcode = qemu_input_map_usb_to_qcode[ev->keysym.scancode]; + if (!qemu_console_is_graphic(con)) { if (ev->type == SDL_KEYDOWN) { switch (ev->keysym.scancode) { diff --git a/ui/sdl2-keymap.h b/ui/sdl2-keymap.h deleted file mode 100644 index cbedaa477d..0000000000 --- a/ui/sdl2-keymap.h +++ /dev/null @@ -1,267 +0,0 @@ - -/* map SDL2 scancodes to QKeyCode */ - -static const int sdl2_scancode_to_qcode[SDL_NUM_SCANCODES] = { - [SDL_SCANCODE_A] = Q_KEY_CODE_A, - [SDL_SCANCODE_B] = Q_KEY_CODE_B, - [SDL_SCANCODE_C] = Q_KEY_CODE_C, - [SDL_SCANCODE_D] = Q_KEY_CODE_D, - [SDL_SCANCODE_E] = Q_KEY_CODE_E, - [SDL_SCANCODE_F] = Q_KEY_CODE_F, - [SDL_SCANCODE_G] = Q_KEY_CODE_G, - [SDL_SCANCODE_H] = Q_KEY_CODE_H, - [SDL_SCANCODE_I] = Q_KEY_CODE_I, - [SDL_SCANCODE_J] = Q_KEY_CODE_J, - [SDL_SCANCODE_K] = Q_KEY_CODE_K, - [SDL_SCANCODE_L] = Q_KEY_CODE_L, - [SDL_SCANCODE_M] = Q_KEY_CODE_M, - [SDL_SCANCODE_N] = Q_KEY_CODE_N, - [SDL_SCANCODE_O] = Q_KEY_CODE_O, - [SDL_SCANCODE_P] = Q_KEY_CODE_P, - [SDL_SCANCODE_Q] = Q_KEY_CODE_Q, - [SDL_SCANCODE_R] = Q_KEY_CODE_R, - [SDL_SCANCODE_S] = Q_KEY_CODE_S, - [SDL_SCANCODE_T] = Q_KEY_CODE_T, - [SDL_SCANCODE_U] = Q_KEY_CODE_U, - [SDL_SCANCODE_V] = Q_KEY_CODE_V, - [SDL_SCANCODE_W] = Q_KEY_CODE_W, - [SDL_SCANCODE_X] = Q_KEY_CODE_X, - [SDL_SCANCODE_Y] = Q_KEY_CODE_Y, - [SDL_SCANCODE_Z] = Q_KEY_CODE_Z, - - [SDL_SCANCODE_1] = Q_KEY_CODE_1, - [SDL_SCANCODE_2] = Q_KEY_CODE_2, - [SDL_SCANCODE_3] = Q_KEY_CODE_3, - [SDL_SCANCODE_4] = Q_KEY_CODE_4, - [SDL_SCANCODE_5] = Q_KEY_CODE_5, - [SDL_SCANCODE_6] = Q_KEY_CODE_6, - [SDL_SCANCODE_7] = Q_KEY_CODE_7, - [SDL_SCANCODE_8] = Q_KEY_CODE_8, - [SDL_SCANCODE_9] = Q_KEY_CODE_9, - [SDL_SCANCODE_0] = Q_KEY_CODE_0, - - [SDL_SCANCODE_RETURN] = Q_KEY_CODE_RET, - [SDL_SCANCODE_ESCAPE] = Q_KEY_CODE_ESC, - [SDL_SCANCODE_BACKSPACE] = Q_KEY_CODE_BACKSPACE, - [SDL_SCANCODE_TAB] = Q_KEY_CODE_TAB, - [SDL_SCANCODE_SPACE] = Q_KEY_CODE_SPC, - [SDL_SCANCODE_MINUS] = Q_KEY_CODE_MINUS, - [SDL_SCANCODE_EQUALS] = Q_KEY_CODE_EQUAL, - [SDL_SCANCODE_LEFTBRACKET] = Q_KEY_CODE_BRACKET_LEFT, - [SDL_SCANCODE_RIGHTBRACKET] = Q_KEY_CODE_BRACKET_RIGHT, - [SDL_SCANCODE_BACKSLASH] = Q_KEY_CODE_BACKSLASH, -#if 0 - [SDL_SCANCODE_NONUSHASH] = Q_KEY_CODE_NONUSHASH, -#endif - [SDL_SCANCODE_SEMICOLON] = Q_KEY_CODE_SEMICOLON, - [SDL_SCANCODE_APOSTROPHE] = Q_KEY_CODE_APOSTROPHE, - [SDL_SCANCODE_GRAVE] = Q_KEY_CODE_GRAVE_ACCENT, - [SDL_SCANCODE_COMMA] = Q_KEY_CODE_COMMA, - [SDL_SCANCODE_PERIOD] = Q_KEY_CODE_DOT, - [SDL_SCANCODE_SLASH] = Q_KEY_CODE_SLASH, - [SDL_SCANCODE_CAPSLOCK] = Q_KEY_CODE_CAPS_LOCK, - - [SDL_SCANCODE_F1] = Q_KEY_CODE_F1, - [SDL_SCANCODE_F2] = Q_KEY_CODE_F2, - [SDL_SCANCODE_F3] = Q_KEY_CODE_F3, - [SDL_SCANCODE_F4] = Q_KEY_CODE_F4, - [SDL_SCANCODE_F5] = Q_KEY_CODE_F5, - [SDL_SCANCODE_F6] = Q_KEY_CODE_F6, - [SDL_SCANCODE_F7] = Q_KEY_CODE_F7, - [SDL_SCANCODE_F8] = Q_KEY_CODE_F8, - [SDL_SCANCODE_F9] = Q_KEY_CODE_F9, - [SDL_SCANCODE_F10] = Q_KEY_CODE_F10, - [SDL_SCANCODE_F11] = Q_KEY_CODE_F11, - [SDL_SCANCODE_F12] = Q_KEY_CODE_F12, - - [SDL_SCANCODE_PRINTSCREEN] = Q_KEY_CODE_PRINT, - [SDL_SCANCODE_SCROLLLOCK] = Q_KEY_CODE_SCROLL_LOCK, - [SDL_SCANCODE_PAUSE] = Q_KEY_CODE_PAUSE, - [SDL_SCANCODE_INSERT] = Q_KEY_CODE_INSERT, - [SDL_SCANCODE_HOME] = Q_KEY_CODE_HOME, - [SDL_SCANCODE_PAGEUP] = Q_KEY_CODE_PGUP, - [SDL_SCANCODE_DELETE] = Q_KEY_CODE_DELETE, - [SDL_SCANCODE_END] = Q_KEY_CODE_END, - [SDL_SCANCODE_PAGEDOWN] = Q_KEY_CODE_PGDN, - [SDL_SCANCODE_RIGHT] = Q_KEY_CODE_RIGHT, - [SDL_SCANCODE_LEFT] = Q_KEY_CODE_LEFT, - [SDL_SCANCODE_DOWN] = Q_KEY_CODE_DOWN, - [SDL_SCANCODE_UP] = Q_KEY_CODE_UP, - [SDL_SCANCODE_NUMLOCKCLEAR] = Q_KEY_CODE_NUM_LOCK, - - [SDL_SCANCODE_KP_DIVIDE] = Q_KEY_CODE_KP_DIVIDE, - [SDL_SCANCODE_KP_MULTIPLY] = Q_KEY_CODE_KP_MULTIPLY, - [SDL_SCANCODE_KP_MINUS] = Q_KEY_CODE_KP_SUBTRACT, - [SDL_SCANCODE_KP_PLUS] = Q_KEY_CODE_KP_ADD, - [SDL_SCANCODE_KP_ENTER] = Q_KEY_CODE_KP_ENTER, - [SDL_SCANCODE_KP_1] = Q_KEY_CODE_KP_1, - [SDL_SCANCODE_KP_2] = Q_KEY_CODE_KP_2, - [SDL_SCANCODE_KP_3] = Q_KEY_CODE_KP_3, - [SDL_SCANCODE_KP_4] = Q_KEY_CODE_KP_4, - [SDL_SCANCODE_KP_5] = Q_KEY_CODE_KP_5, - [SDL_SCANCODE_KP_6] = Q_KEY_CODE_KP_6, - [SDL_SCANCODE_KP_7] = Q_KEY_CODE_KP_7, - [SDL_SCANCODE_KP_8] = Q_KEY_CODE_KP_8, - [SDL_SCANCODE_KP_9] = Q_KEY_CODE_KP_9, - [SDL_SCANCODE_KP_0] = Q_KEY_CODE_KP_0, - [SDL_SCANCODE_KP_PERIOD] = Q_KEY_CODE_KP_DECIMAL, - - [SDL_SCANCODE_NONUSBACKSLASH] = Q_KEY_CODE_LESS, - [SDL_SCANCODE_APPLICATION] = Q_KEY_CODE_MENU, -#if 0 - [SDL_SCANCODE_POWER] = Q_KEY_CODE_POWER, - [SDL_SCANCODE_KP_EQUALS] = Q_KEY_CODE_KP_EQUALS, - - [SDL_SCANCODE_F13] = Q_KEY_CODE_F13, - [SDL_SCANCODE_F14] = Q_KEY_CODE_F14, - [SDL_SCANCODE_F15] = Q_KEY_CODE_F15, - [SDL_SCANCODE_F16] = Q_KEY_CODE_F16, - [SDL_SCANCODE_F17] = Q_KEY_CODE_F17, - [SDL_SCANCODE_F18] = Q_KEY_CODE_F18, - [SDL_SCANCODE_F19] = Q_KEY_CODE_F19, - [SDL_SCANCODE_F20] = Q_KEY_CODE_F20, - [SDL_SCANCODE_F21] = Q_KEY_CODE_F21, - [SDL_SCANCODE_F22] = Q_KEY_CODE_F22, - [SDL_SCANCODE_F23] = Q_KEY_CODE_F23, - [SDL_SCANCODE_F24] = Q_KEY_CODE_F24, - - [SDL_SCANCODE_EXECUTE] = Q_KEY_CODE_EXECUTE, -#endif - [SDL_SCANCODE_HELP] = Q_KEY_CODE_HELP, - [SDL_SCANCODE_MENU] = Q_KEY_CODE_MENU, -#if 0 - [SDL_SCANCODE_SELECT] = Q_KEY_CODE_SELECT, -#endif - [SDL_SCANCODE_STOP] = Q_KEY_CODE_STOP, - [SDL_SCANCODE_AGAIN] = Q_KEY_CODE_AGAIN, - [SDL_SCANCODE_UNDO] = Q_KEY_CODE_UNDO, - [SDL_SCANCODE_CUT] = Q_KEY_CODE_CUT, - [SDL_SCANCODE_COPY] = Q_KEY_CODE_COPY, - [SDL_SCANCODE_PASTE] = Q_KEY_CODE_PASTE, - [SDL_SCANCODE_FIND] = Q_KEY_CODE_FIND, -#if 0 - [SDL_SCANCODE_MUTE] = Q_KEY_CODE_MUTE, - [SDL_SCANCODE_VOLUMEUP] = Q_KEY_CODE_VOLUMEUP, - [SDL_SCANCODE_VOLUMEDOWN] = Q_KEY_CODE_VOLUMEDOWN, - - [SDL_SCANCODE_KP_COMMA] = Q_KEY_CODE_KP_COMMA, - [SDL_SCANCODE_KP_EQUALSAS400] = Q_KEY_CODE_KP_EQUALSAS400, - - [SDL_SCANCODE_INTERNATIONAL1] = Q_KEY_CODE_INTERNATIONAL1, - [SDL_SCANCODE_INTERNATIONAL2] = Q_KEY_CODE_INTERNATIONAL2, - [SDL_SCANCODE_INTERNATIONAL3] = Q_KEY_CODE_INTERNATIONAL3, - [SDL_SCANCODE_INTERNATIONAL4] = Q_KEY_CODE_INTERNATIONAL4, - [SDL_SCANCODE_INTERNATIONAL5] = Q_KEY_CODE_INTERNATIONAL5, - [SDL_SCANCODE_INTERNATIONAL6] = Q_KEY_CODE_INTERNATIONAL6, - [SDL_SCANCODE_INTERNATIONAL7] = Q_KEY_CODE_INTERNATIONAL7, - [SDL_SCANCODE_INTERNATIONAL8] = Q_KEY_CODE_INTERNATIONAL8, - [SDL_SCANCODE_INTERNATIONAL9] = Q_KEY_CODE_INTERNATIONAL9, - [SDL_SCANCODE_LANG1] = Q_KEY_CODE_LANG1, - [SDL_SCANCODE_LANG2] = Q_KEY_CODE_LANG2, - [SDL_SCANCODE_LANG3] = Q_KEY_CODE_LANG3, - [SDL_SCANCODE_LANG4] = Q_KEY_CODE_LANG4, - [SDL_SCANCODE_LANG5] = Q_KEY_CODE_LANG5, - [SDL_SCANCODE_LANG6] = Q_KEY_CODE_LANG6, - [SDL_SCANCODE_LANG7] = Q_KEY_CODE_LANG7, - [SDL_SCANCODE_LANG8] = Q_KEY_CODE_LANG8, - [SDL_SCANCODE_LANG9] = Q_KEY_CODE_LANG9, - [SDL_SCANCODE_ALTERASE] = Q_KEY_CODE_ALTERASE, -#endif - [SDL_SCANCODE_SYSREQ] = Q_KEY_CODE_SYSRQ, -#if 0 - [SDL_SCANCODE_CANCEL] = Q_KEY_CODE_CANCEL, - [SDL_SCANCODE_CLEAR] = Q_KEY_CODE_CLEAR, - [SDL_SCANCODE_PRIOR] = Q_KEY_CODE_PRIOR, - [SDL_SCANCODE_RETURN2] = Q_KEY_CODE_RETURN2, - [SDL_SCANCODE_SEPARATOR] = Q_KEY_CODE_SEPARATOR, - [SDL_SCANCODE_OUT] = Q_KEY_CODE_OUT, - [SDL_SCANCODE_OPER] = Q_KEY_CODE_OPER, - [SDL_SCANCODE_CLEARAGAIN] = Q_KEY_CODE_CLEARAGAIN, - [SDL_SCANCODE_CRSEL] = Q_KEY_CODE_CRSEL, - [SDL_SCANCODE_EXSEL] = Q_KEY_CODE_EXSEL, - [SDL_SCANCODE_KP_00] = Q_KEY_CODE_KP_00, - [SDL_SCANCODE_KP_000] = Q_KEY_CODE_KP_000, - [SDL_SCANCODE_THOUSANDSSEPARATOR] = Q_KEY_CODE_THOUSANDSSEPARATOR, - [SDL_SCANCODE_DECIMALSEPARATOR] = Q_KEY_CODE_DECIMALSEPARATOR, - [SDL_SCANCODE_CURRENCYUNIT] = Q_KEY_CODE_CURRENCYUNIT, - [SDL_SCANCODE_CURRENCYSUBUNIT] = Q_KEY_CODE_CURRENCYSUBUNIT, - [SDL_SCANCODE_KP_LEFTPAREN] = Q_KEY_CODE_KP_LEFTPAREN, - [SDL_SCANCODE_KP_RIGHTPAREN] = Q_KEY_CODE_KP_RIGHTPAREN, - [SDL_SCANCODE_KP_LEFTBRACE] = Q_KEY_CODE_KP_LEFTBRACE, - [SDL_SCANCODE_KP_RIGHTBRACE] = Q_KEY_CODE_KP_RIGHTBRACE, - [SDL_SCANCODE_KP_TAB] = Q_KEY_CODE_KP_TAB, - [SDL_SCANCODE_KP_BACKSPACE] = Q_KEY_CODE_KP_BACKSPACE, - [SDL_SCANCODE_KP_A] = Q_KEY_CODE_KP_A, - [SDL_SCANCODE_KP_B] = Q_KEY_CODE_KP_B, - [SDL_SCANCODE_KP_C] = Q_KEY_CODE_KP_C, - [SDL_SCANCODE_KP_D] = Q_KEY_CODE_KP_D, - [SDL_SCANCODE_KP_E] = Q_KEY_CODE_KP_E, - [SDL_SCANCODE_KP_F] = Q_KEY_CODE_KP_F, - [SDL_SCANCODE_KP_XOR] = Q_KEY_CODE_KP_XOR, - [SDL_SCANCODE_KP_POWER] = Q_KEY_CODE_KP_POWER, - [SDL_SCANCODE_KP_PERCENT] = Q_KEY_CODE_KP_PERCENT, - [SDL_SCANCODE_KP_LESS] = Q_KEY_CODE_KP_LESS, - [SDL_SCANCODE_KP_GREATER] = Q_KEY_CODE_KP_GREATER, - [SDL_SCANCODE_KP_AMPERSAND] = Q_KEY_CODE_KP_AMPERSAND, - [SDL_SCANCODE_KP_DBLAMPERSAND] = Q_KEY_CODE_KP_DBLAMPERSAND, - [SDL_SCANCODE_KP_VERTICALBAR] = Q_KEY_CODE_KP_VERTICALBAR, - [SDL_SCANCODE_KP_DBLVERTICALBAR] = Q_KEY_CODE_KP_DBLVERTICALBAR, - [SDL_SCANCODE_KP_COLON] = Q_KEY_CODE_KP_COLON, - [SDL_SCANCODE_KP_HASH] = Q_KEY_CODE_KP_HASH, - [SDL_SCANCODE_KP_SPACE] = Q_KEY_CODE_KP_SPACE, - [SDL_SCANCODE_KP_AT] = Q_KEY_CODE_KP_AT, - [SDL_SCANCODE_KP_EXCLAM] = Q_KEY_CODE_KP_EXCLAM, - [SDL_SCANCODE_KP_MEMSTORE] = Q_KEY_CODE_KP_MEMSTORE, - [SDL_SCANCODE_KP_MEMRECALL] = Q_KEY_CODE_KP_MEMRECALL, - [SDL_SCANCODE_KP_MEMCLEAR] = Q_KEY_CODE_KP_MEMCLEAR, - [SDL_SCANCODE_KP_MEMADD] = Q_KEY_CODE_KP_MEMADD, - [SDL_SCANCODE_KP_MEMSUBTRACT] = Q_KEY_CODE_KP_MEMSUBTRACT, - [SDL_SCANCODE_KP_MEMMULTIPLY] = Q_KEY_CODE_KP_MEMMULTIPLY, - [SDL_SCANCODE_KP_MEMDIVIDE] = Q_KEY_CODE_KP_MEMDIVIDE, - [SDL_SCANCODE_KP_PLUSMINUS] = Q_KEY_CODE_KP_PLUSMINUS, - [SDL_SCANCODE_KP_CLEAR] = Q_KEY_CODE_KP_CLEAR, - [SDL_SCANCODE_KP_CLEARENTRY] = Q_KEY_CODE_KP_CLEARENTRY, - [SDL_SCANCODE_KP_BINARY] = Q_KEY_CODE_KP_BINARY, - [SDL_SCANCODE_KP_OCTAL] = Q_KEY_CODE_KP_OCTAL, - [SDL_SCANCODE_KP_DECIMAL] = Q_KEY_CODE_KP_DECIMAL, - [SDL_SCANCODE_KP_HEXADECIMAL] = Q_KEY_CODE_KP_HEXADECIMAL, -#endif - [SDL_SCANCODE_LCTRL] = Q_KEY_CODE_CTRL, - [SDL_SCANCODE_LSHIFT] = Q_KEY_CODE_SHIFT, - [SDL_SCANCODE_LALT] = Q_KEY_CODE_ALT, - [SDL_SCANCODE_LGUI] = Q_KEY_CODE_META_L, - [SDL_SCANCODE_RCTRL] = Q_KEY_CODE_CTRL_R, - [SDL_SCANCODE_RSHIFT] = Q_KEY_CODE_SHIFT_R, - [SDL_SCANCODE_RALT] = Q_KEY_CODE_ALT_R, - [SDL_SCANCODE_RGUI] = Q_KEY_CODE_META_R, -#if 0 - [SDL_SCANCODE_MODE] = Q_KEY_CODE_MODE, - [SDL_SCANCODE_AUDIONEXT] = Q_KEY_CODE_AUDIONEXT, - [SDL_SCANCODE_AUDIOPREV] = Q_KEY_CODE_AUDIOPREV, - [SDL_SCANCODE_AUDIOSTOP] = Q_KEY_CODE_AUDIOSTOP, - [SDL_SCANCODE_AUDIOPLAY] = Q_KEY_CODE_AUDIOPLAY, - [SDL_SCANCODE_AUDIOMUTE] = Q_KEY_CODE_AUDIOMUTE, - [SDL_SCANCODE_MEDIASELECT] = Q_KEY_CODE_MEDIASELECT, - [SDL_SCANCODE_WWW] = Q_KEY_CODE_WWW, - [SDL_SCANCODE_MAIL] = Q_KEY_CODE_MAIL, - [SDL_SCANCODE_CALCULATOR] = Q_KEY_CODE_CALCULATOR, - [SDL_SCANCODE_COMPUTER] = Q_KEY_CODE_COMPUTER, - [SDL_SCANCODE_AC_SEARCH] = Q_KEY_CODE_AC_SEARCH, - [SDL_SCANCODE_AC_HOME] = Q_KEY_CODE_AC_HOME, - [SDL_SCANCODE_AC_BACK] = Q_KEY_CODE_AC_BACK, - [SDL_SCANCODE_AC_FORWARD] = Q_KEY_CODE_AC_FORWARD, - [SDL_SCANCODE_AC_STOP] = Q_KEY_CODE_AC_STOP, - [SDL_SCANCODE_AC_REFRESH] = Q_KEY_CODE_AC_REFRESH, - [SDL_SCANCODE_AC_BOOKMARKS] = Q_KEY_CODE_AC_BOOKMARKS, - [SDL_SCANCODE_BRIGHTNESSDOWN] = Q_KEY_CODE_BRIGHTNESSDOWN, - [SDL_SCANCODE_BRIGHTNESSUP] = Q_KEY_CODE_BRIGHTNESSUP, - [SDL_SCANCODE_DISPLAYSWITCH] = Q_KEY_CODE_DISPLAYSWITCH, - [SDL_SCANCODE_KBDILLUMTOGGLE] = Q_KEY_CODE_KBDILLUMTOGGLE, - [SDL_SCANCODE_KBDILLUMDOWN] = Q_KEY_CODE_KBDILLUMDOWN, - [SDL_SCANCODE_KBDILLUMUP] = Q_KEY_CODE_KBDILLUMUP, - [SDL_SCANCODE_EJECT] = Q_KEY_CODE_EJECT, - [SDL_SCANCODE_SLEEP] = Q_KEY_CODE_SLEEP, - [SDL_SCANCODE_APP1] = Q_KEY_CODE_APP1, - [SDL_SCANCODE_APP2] = Q_KEY_CODE_APP2, -#endif -}; diff --git a/ui/sdl2.c b/ui/sdl2.c index 89c6a2633c..812c315891 100644 --- a/ui/sdl2.c +++ b/ui/sdl2.c @@ -38,7 +38,6 @@ static int gui_grab; /* if true, all keyboard/mouse events are grabbed */ static int gui_saved_grab; static int gui_fullscreen; -static int gui_noframe; static int gui_key_modifier_pressed; static int gui_keysym; static int gui_grab_code = KMOD_LALT | KMOD_LCTRL; @@ -141,11 +140,11 @@ static void sdl_update_caption(struct sdl2_console *scon) status = " [Stopped]"; } else if (gui_grab) { if (alt_grab) { - status = " - Press Ctrl-Alt-Shift to exit grab"; + status = " - Press Ctrl-Alt-Shift-G to exit grab"; } else if (ctrl_grab) { - status = " - Press Right-Ctrl to exit grab"; + status = " - Press Right-Ctrl-G to exit grab"; } else { - status = " - Press Ctrl-Alt to exit grab"; + status = " - Press Ctrl-Alt-G to exit grab"; } } @@ -364,6 +363,14 @@ static void handle_keydown(SDL_Event *ev) toggle_full_screen(scon); gui_keysym = 1; break; + case SDL_SCANCODE_G: + gui_keysym = 1; + if (!gui_grab) { + sdl_grab_start(scon); + } else if (!gui_fullscreen) { + sdl_grab_end(scon); + } + break; case SDL_SCANCODE_U: sdl2_window_destroy(scon); sdl2_window_create(scon); @@ -416,19 +423,6 @@ static void handle_keyup(SDL_Event *ev) } if (!mod_state && gui_key_modifier_pressed) { gui_key_modifier_pressed = 0; - if (gui_keysym == 0) { - /* exit/enter grab if pressing Ctrl-Alt */ - if (!gui_grab) { - sdl_grab_start(scon); - } else if (!gui_fullscreen) { - sdl_grab_end(scon); - } - /* SDL does not send back all the modifiers key, so we must - * correct it. */ - sdl2_reset_keys(scon); - return; - } - sdl2_reset_keys(scon); gui_keysym = 0; } if (!gui_keysym) { @@ -772,7 +766,7 @@ void sdl_display_early_init(int opengl) } } -void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) +void sdl_display_init(DisplayState *ds, int full_screen) { int flags; uint8_t data = 0; @@ -780,10 +774,6 @@ void sdl_display_init(DisplayState *ds, int full_screen, int no_frame) int i; SDL_SysWMinfo info; - if (no_frame) { - gui_noframe = 1; - } - #ifdef __linux__ /* on Linux, SDL may use fbcon|directfb|svgalib when run without * accessible $DISPLAY to open X11 window. This is often the case diff --git a/ui/trace-events b/ui/trace-events index 85f74f948b..34229e6747 100644 --- a/ui/trace-events +++ b/ui/trace-events @@ -18,9 +18,10 @@ ppm_save(const char *filename, void *display_surface) "%s surface=%p" # ui/gtk.c gd_switch(const char *tab, int width, int height) "tab=%s, width=%d, height=%d" gd_update(const char *tab, int x, int y, int w, int h) "tab=%s, x=%d, y=%d, w=%d, h=%d" -gd_key_event(const char *tab, int gdk_keycode, int qemu_keycode, const char *action) "tab=%s, translated GDK keycode %d to QEMU keycode %d (%s)" +gd_key_event(const char *tab, int gdk_keycode, int qkeycode, const char *action) "tab=%s, translated GDK keycode %d to QKeyCode %d (%s)" gd_grab(const char *tab, const char *device, const char *reason) "tab=%s, dev=%s, reason=%s" gd_ungrab(const char *tab, const char *device) "tab=%s, dev=%s" +gd_keymap_windowing(const char *name) "backend=%s" # ui/vnc.c vnc_key_guest_leds(bool caps, bool num, bool scroll) "caps %d, num %d, scroll %d" @@ -79,3 +80,9 @@ qemu_spice_create_update(uint32_t left, uint32_t right, uint32_t top, uint32_t b keymap_parse(const char *file) "file %s" keymap_add(const char *type, int sym, int code, const char *line) "%-6s sym=0x%04x code=0x%04x (line: %s)" keymap_unmapped(int sym) "sym=0x%04x" + +# ui/x_keymap.c +xkeymap_extension(const char *name) "extension '%s'" +xkeymap_vendor(const char *name) "vendor '%s'" +xkeymap_keycodes(const char *name) "keycodes '%s'" +xkeymap_keymap(const char *name) "keymap '%s'" diff --git a/ui/vnc.c b/ui/vnc.c index 665a143578..33b087221f 100644 --- a/ui/vnc.c +++ b/ui/vnc.c @@ -672,6 +672,11 @@ static void vnc_desktop_resize(VncState *vs) vs->client_height == pixman_image_get_height(vs->vd->server)) { return; } + + assert(pixman_image_get_width(vs->vd->server) < 65536 && + pixman_image_get_width(vs->vd->server) >= 0); + assert(pixman_image_get_height(vs->vd->server) < 65536 && + pixman_image_get_height(vs->vd->server) >= 0); vs->client_width = pixman_image_get_width(vs->vd->server); vs->client_height = pixman_image_get_height(vs->vd->server); vnc_lock_output(vs); @@ -2490,6 +2495,10 @@ static int protocol_client_init(VncState *vs, uint8_t *data, size_t len) return 0; } + assert(pixman_image_get_width(vs->vd->server) < 65536 && + pixman_image_get_width(vs->vd->server) >= 0); + assert(pixman_image_get_height(vs->vd->server) < 65536 && + pixman_image_get_height(vs->vd->server) >= 0); vs->client_width = pixman_image_get_width(vs->vd->server); vs->client_height = pixman_image_get_height(vs->vd->server); vnc_write_u16(vs, vs->client_width); diff --git a/ui/vnc.h b/ui/vnc.h index 0c33a5f7fe..bbda0540a7 100644 --- a/ui/vnc.h +++ b/ui/vnc.h @@ -278,8 +278,8 @@ struct VncState int last_x; int last_y; uint32_t last_bmask; - int client_width; - int client_height; + size_t client_width; /* limited to u16 by RFB proto */ + size_t client_height; /* limited to u16 by RFB proto */ VncShareMode share_mode; uint32_t vnc_encoding; diff --git a/ui/x_keymap.c b/ui/x_keymap.c index 27884851de..22e0e77c4d 100644 --- a/ui/x_keymap.c +++ b/ui/x_keymap.c @@ -1,169 +1,111 @@ /* - * QEMU SDL display driver + * QEMU X11 keymaps * - * Copyright (c) 2003 Fabrice Bellard + * Copyright (C) 2009-2010 Daniel P. Berrange <dan@berrange.com> + * Copyright (C) 2017 Red Hat, Inc * - * Permission is hereby granted, free of charge, to any person obtaining a copy - * of this software and associated documentation files (the "Software"), to deal - * in the Software without restriction, including without limitation the rights - * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell - * copies of the Software, and to permit persons to whom the Software is - * furnished to do so, subject to the following conditions: - * - * The above copyright notice and this permission notice shall be included in - * all copies or substantial portions of the Software. - * - * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR - * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, - * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL - * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER - * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, - * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN - * THE SOFTWARE. + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU Lesser General Public License version 2 as + * published by the Free Software Foundation. */ + #include "qemu/osdep.h" -#include "qemu-common.h" + #include "x_keymap.h" +#include "trace.h" +#include "qemu/notify.h" +#include "ui/input.h" -static const uint8_t x_keycode_to_pc_keycode[115] = { - 0xc7, /* 97 Home */ - 0xc8, /* 98 Up */ - 0xc9, /* 99 PgUp */ - 0xcb, /* 100 Left */ - 0x4c, /* 101 KP-5 */ - 0xcd, /* 102 Right */ - 0xcf, /* 103 End */ - 0xd0, /* 104 Down */ - 0xd1, /* 105 PgDn */ - 0xd2, /* 106 Ins */ - 0xd3, /* 107 Del */ - 0x9c, /* 108 Enter */ - 0x9d, /* 109 Ctrl-R */ - 0x0, /* 110 Pause */ - 0xb7, /* 111 Print */ - 0xb5, /* 112 Divide */ - 0xb8, /* 113 Alt-R */ - 0xc6, /* 114 Break */ - 0x0, /* 115 */ - 0x0, /* 116 */ - 0x0, /* 117 */ - 0x0, /* 118 */ - 0x0, /* 119 */ - 0x0, /* 120 */ - 0x0, /* 121 */ - 0x0, /* 122 */ - 0x0, /* 123 */ - 0x0, /* 124 */ - 0x0, /* 125 */ - 0x0, /* 126 */ - 0x0, /* 127 */ - 0x0, /* 128 */ - 0x79, /* 129 Henkan */ - 0x0, /* 130 */ - 0x7b, /* 131 Muhenkan */ - 0x0, /* 132 */ - 0x7d, /* 133 Yen */ - 0x0, /* 134 */ - 0x0, /* 135 */ - 0x47, /* 136 KP_7 */ - 0x48, /* 137 KP_8 */ - 0x49, /* 138 KP_9 */ - 0x4b, /* 139 KP_4 */ - 0x4c, /* 140 KP_5 */ - 0x4d, /* 141 KP_6 */ - 0x4f, /* 142 KP_1 */ - 0x50, /* 143 KP_2 */ - 0x51, /* 144 KP_3 */ - 0x52, /* 145 KP_0 */ - 0x53, /* 146 KP_. */ - 0x47, /* 147 KP_HOME */ - 0x48, /* 148 KP_UP */ - 0x49, /* 149 KP_PgUp */ - 0x4b, /* 150 KP_Left */ - 0x4c, /* 151 KP_ */ - 0x4d, /* 152 KP_Right */ - 0x4f, /* 153 KP_End */ - 0x50, /* 154 KP_Down */ - 0x51, /* 155 KP_PgDn */ - 0x52, /* 156 KP_Ins */ - 0x53, /* 157 KP_Del */ -}; +#include <X11/XKBlib.h> -/* This table is generated based off the xfree86 -> scancode mapping above - * and the keycode mappings in /usr/share/X11/xkb/keycodes/evdev - * and /usr/share/X11/xkb/keycodes/xfree86 - */ +static gboolean check_for_xwin(Display *dpy) +{ + const char *vendor = ServerVendor(dpy); + + trace_xkeymap_vendor(vendor); -static const uint8_t evdev_keycode_to_pc_keycode[61] = { - 0x73, /* 97 EVDEV - RO ("Internet" Keyboards) */ - 0, /* 98 EVDEV - KATA (Katakana) */ - 0, /* 99 EVDEV - HIRA (Hiragana) */ - 0x79, /* 100 EVDEV - HENK (Henkan) */ - 0x70, /* 101 EVDEV - HKTG (Hiragana/Katakana toggle) */ - 0x7b, /* 102 EVDEV - MUHE (Muhenkan) */ - 0, /* 103 EVDEV - JPCM (KPJPComma) */ - 0x9c, /* 104 KPEN */ - 0x9d, /* 105 RCTL */ - 0xb5, /* 106 KPDV */ - 0xb7, /* 107 PRSC */ - 0xb8, /* 108 RALT */ - 0, /* 109 EVDEV - LNFD ("Internet" Keyboards) */ - 0xc7, /* 110 HOME */ - 0xc8, /* 111 UP */ - 0xc9, /* 112 PGUP */ - 0xcb, /* 113 LEFT */ - 0xcd, /* 114 RGHT */ - 0xcf, /* 115 END */ - 0xd0, /* 116 DOWN */ - 0xd1, /* 117 PGDN */ - 0xd2, /* 118 INS */ - 0xd3, /* 119 DELE */ - 0, /* 120 EVDEV - I120 ("Internet" Keyboards) */ - 0, /* 121 EVDEV - MUTE */ - 0, /* 122 EVDEV - VOL- */ - 0, /* 123 EVDEV - VOL+ */ - 0, /* 124 EVDEV - POWR */ - 0, /* 125 EVDEV - KPEQ */ - 0, /* 126 EVDEV - I126 ("Internet" Keyboards) */ - 0, /* 127 EVDEV - PAUS */ - 0, /* 128 EVDEV - ???? */ - 0x7e, /* 129 EVDEV - KP_COMMA (brazilian) */ - 0xf1, /* 130 EVDEV - HNGL (Korean Hangul Latin toggle) */ - 0xf2, /* 131 EVDEV - HJCV (Korean Hangul Hanja toggle) */ - 0x7d, /* 132 AE13 (Yen)*/ - 0xdb, /* 133 EVDEV - LWIN */ - 0xdc, /* 134 EVDEV - RWIN */ - 0xdd, /* 135 EVDEV - MENU */ - 0, /* 136 EVDEV - STOP */ - 0, /* 137 EVDEV - AGAI */ - 0, /* 138 EVDEV - PROP */ - 0, /* 139 EVDEV - UNDO */ - 0, /* 140 EVDEV - FRNT */ - 0, /* 141 EVDEV - COPY */ - 0, /* 142 EVDEV - OPEN */ - 0, /* 143 EVDEV - PAST */ - 0, /* 144 EVDEV - FIND */ - 0, /* 145 EVDEV - CUT */ - 0, /* 146 EVDEV - HELP */ - 0, /* 147 EVDEV - I147 */ - 0, /* 148 EVDEV - I148 */ - 0, /* 149 EVDEV - I149 */ - 0, /* 150 EVDEV - I150 */ - 0, /* 151 EVDEV - I151 */ - 0, /* 152 EVDEV - I152 */ - 0, /* 153 EVDEV - I153 */ - 0, /* 154 EVDEV - I154 */ - 0, /* 155 EVDEV - I156 */ - 0, /* 156 EVDEV - I157 */ - 0, /* 157 EVDEV - I158 */ -}; + if (strstr(vendor, "Cygwin/X")) { + return TRUE; + } -uint8_t translate_xfree86_keycode(const int key) + return FALSE; +} + +static gboolean check_for_xquartz(Display *dpy) { - return x_keycode_to_pc_keycode[key]; + int nextensions; + int i; + gboolean match = FALSE; + char **extensions = XListExtensions(dpy, &nextensions); + for (i = 0 ; extensions != NULL && i < nextensions ; i++) { + trace_xkeymap_extension(extensions[i]); + if (strcmp(extensions[i], "Apple-WM") == 0 || + strcmp(extensions[i], "Apple-DRI") == 0) { + match = TRUE; + } + } + if (extensions) { + XFreeExtensionList(extensions); + } + + return match; } -uint8_t translate_evdev_keycode(const int key) +const guint16 *qemu_xkeymap_mapping_table(Display *dpy, size_t *maplen) { - return evdev_keycode_to_pc_keycode[key]; + XkbDescPtr desc; + const gchar *keycodes = NULL; + + /* There is no easy way to determine what X11 server + * and platform & keyboard driver is in use. Thus we + * do best guess heuristics. + * + * This will need more work for people with other + * X servers..... patches welcomed. + */ + + desc = XkbGetMap(dpy, + XkbGBN_AllComponentsMask, + XkbUseCoreKbd); + if (desc) { + if (XkbGetNames(dpy, XkbKeycodesNameMask, desc) == Success) { + keycodes = XGetAtomName (dpy, desc->names->keycodes); + if (!keycodes) { + g_warning("could not lookup keycode name"); + } else { + trace_xkeymap_keycodes(keycodes); + } + } + XkbFreeKeyboard(desc, XkbGBN_AllComponentsMask, True); + } + + if (check_for_xwin(dpy)) { + trace_xkeymap_keymap("xwin"); + *maplen = qemu_input_map_xorgxwin_to_qcode_len; + return qemu_input_map_xorgxwin_to_qcode; + } else if (check_for_xquartz(dpy)) { + trace_xkeymap_keymap("xquartz"); + *maplen = qemu_input_map_xorgxquartz_to_qcode_len; + return qemu_input_map_xorgxquartz_to_qcode; + } else if (keycodes && g_str_has_prefix(keycodes, "evdev")) { + trace_xkeymap_keymap("evdev"); + *maplen = qemu_input_map_xorgevdev_to_qcode_len; + return qemu_input_map_xorgevdev_to_qcode; + } else if (keycodes && g_str_has_prefix(keycodes, "xfree86")) { + trace_xkeymap_keymap("kbd"); + *maplen = qemu_input_map_xorgkbd_to_qcode_len; + return qemu_input_map_xorgkbd_to_qcode; + } else { + trace_xkeymap_keymap("NULL"); + g_warning("Unknown X11 keycode mapping '%s'.\n" + "Please report to qemu-devel@nongnu.org\n" + "including the following information:\n" + "\n" + " - Operating system\n" + " - X11 Server\n" + " - xprop -root\n" + " - xdpyinfo\n", + keycodes ? keycodes : "<null>"); + return NULL; + } } diff --git a/ui/x_keymap.h b/ui/x_keymap.h index afde2e94bf..0395e335ff 100644 --- a/ui/x_keymap.h +++ b/ui/x_keymap.h @@ -1,7 +1,7 @@ /* - * QEMU SDL display driver + * QEMU X11 keymaps * - * Copyright (c) 2003 Fabrice Bellard + * Copyright (c) 2017 Red Hat, Inc. * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -25,8 +25,8 @@ #ifndef QEMU_X_KEYMAP_H #define QEMU_X_KEYMAP_H -uint8_t translate_xfree86_keycode(const int key); +#include <X11/Xlib.h> -uint8_t translate_evdev_keycode(const int key); +const guint16 *qemu_xkeymap_mapping_table(Display *dpy, size_t *maplen); #endif diff --git a/vl.c b/vl.c index e725ecbc08..6ab232095c 100644 --- a/vl.c +++ b/vl.c @@ -150,7 +150,7 @@ static int rtc_date_offset = -1; /* -1 means no change */ QEMUClockType rtc_clock; int vga_interface_type = VGA_NONE; static int full_screen = 0; -static int no_frame = 0; +int no_frame; int no_quit = 0; static bool grab_on_hover; Chardev *serial_hds[MAX_SERIAL_PORTS]; @@ -4694,7 +4694,7 @@ int main(int argc, char **argv, char **envp) curses_display_init(ds, full_screen); break; case DT_SDL: - sdl_display_init(ds, full_screen, no_frame); + sdl_display_init(ds, full_screen); break; case DT_COCOA: cocoa_display_init(ds, full_screen); |