diff options
| -rw-r--r-- | target/i386/cpu.c | 36 |
1 files changed, 31 insertions, 5 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index e98ffb11c3..b557fd01c0 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7983,8 +7983,33 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *edx = encode_cache_cpuid80000005(caches->l1i_cache); break; } - case 0x80000006: - /* cache info (L2 cache/TLB/L3 cache) */ + case 0x80000006: { /* cache info (L2 cache/TLB/L3 cache) */ + const CPUCaches *caches; + + if (env->enable_legacy_vendor_cache) { + caches = &legacy_amd_cache_info; + } else { + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * This condition covers the following cases (with + * enable_legacy_vendor_cache=false): + * - When CPU model has its own cache model and doesn't uses legacy + * cache model (legacy_model=off). Then cache_info_amd and + * cache_info_cpuid4 are the same. + * + * - For v10.1 and newer machines, when CPU model uses legacy cache + * model. AMD CPUs use cache_info_amd like before and non-AMD + * CPU (Intel & Zhaoxin) will use cache_info_cpuid4 as expected. + */ + if (IS_AMD_CPU(env)) { + caches = &env->cache_info_amd; + } else { + caches = &env->cache_info_cpuid4; + } + } + if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; @@ -7993,7 +8018,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, if (cpu->vendor_cpuid_only_v2 && (IS_INTEL_CPU(env) || IS_ZHAOXIN_CPU(env))) { *eax = *ebx = 0; - encode_cache_cpuid80000006(env->cache_info_cpuid4.l2_cache, + encode_cache_cpuid80000006(caches->l2_cache, NULL, ecx, edx); break; } @@ -8007,11 +8032,12 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, (X86_ENC_ASSOC(L2_ITLB_4K_ASSOC) << 12) | (L2_ITLB_4K_ENTRIES); - encode_cache_cpuid80000006(env->cache_info_amd.l2_cache, + encode_cache_cpuid80000006(caches->l2_cache, cpu->enable_l3_cache ? - env->cache_info_amd.l3_cache : NULL, + caches->l3_cache : NULL, ecx, edx); break; + } case 0x80000007: *eax = 0; *ebx = env->features[FEAT_8000_0007_EBX]; |