diff options
299 files changed, 4051 insertions, 5145 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 6111b6b4d9..b471973e1e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -543,14 +543,6 @@ F: include/sysemu/xen.h F: include/sysemu/xen-mapcache.h F: stubs/xen-hw-stub.c -Guest CPU Cores (HAXM) ---------------------- -X86 HAXM CPUs -S: Orphan -F: accel/stubs/hax-stub.c -F: include/sysemu/hax.h -F: target/i386/hax/ - Guest CPU Cores (NVMM) ---------------------- NetBSD Virtual Machine Monitor (NVMM) CPU support @@ -3701,6 +3693,7 @@ S: Supported F: block/parallels.c F: block/parallels-ext.c F: docs/interop/parallels.txt +T: git https://src.openvz.org/scm/~den/qemu.git parallels qed M: Stefan Hajnoczi <stefanha@redhat.com> diff --git a/accel/Kconfig b/accel/Kconfig index 8bdedb7d15..a30cf2eb48 100644 --- a/accel/Kconfig +++ b/accel/Kconfig @@ -4,9 +4,6 @@ config WHPX config NVMM bool -config HAX - bool - config HVF bool diff --git a/accel/stubs/hax-stub.c b/accel/stubs/hax-stub.c deleted file mode 100644 index 2fe31aaa9a..0000000000 --- a/accel/stubs/hax-stub.c +++ /dev/null @@ -1,24 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2015, Intel Corporation - * - * Copyright 2016 Google, Inc. - * - * This software is licensed under the terms of the GNU General Public - * License version 2, as published by the Free Software Foundation, and - * may be copied, distributed, and modified under those terms. - * - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include "sysemu/hax.h" - -bool hax_allowed; - -int hax_sync_vcpus(void) -{ - return 0; -} diff --git a/accel/stubs/meson.build b/accel/stubs/meson.build index f7a9486e06..6b0f200efe 100644 --- a/accel/stubs/meson.build +++ b/accel/stubs/meson.build @@ -1,5 +1,4 @@ sysemu_stubs_ss = ss.source_set() -sysemu_stubs_ss.add(when: 'CONFIG_HAX', if_false: files('hax-stub.c')) sysemu_stubs_ss.add(when: 'CONFIG_XEN', if_false: files('xen-stub.c')) sysemu_stubs_ss.add(when: 'CONFIG_KVM', if_false: files('kvm-stub.c')) sysemu_stubs_ss.add(when: 'CONFIG_TCG', if_false: files('tcg-stub.c')) diff --git a/accel/tcg/tb-maint.c b/accel/tcg/tb-maint.c index c406b2f7b7..32ae8af61c 100644 --- a/accel/tcg/tb-maint.c +++ b/accel/tcg/tb-maint.c @@ -1,5 +1,5 @@ /* - * Translation Block Maintaince + * Translation Block Maintenance * * Copyright (c) 2003 Fabrice Bellard * diff --git a/block/parallels.c b/block/parallels.c index 18e34aef28..48c32d6821 100644 --- a/block/parallels.c +++ b/block/parallels.c @@ -136,6 +136,12 @@ static int cluster_remainder(BDRVParallelsState *s, int64_t sector_num, return MIN(nb_sectors, ret); } +static uint32_t host_cluster_index(BDRVParallelsState *s, int64_t off) +{ + off -= s->data_start << BDRV_SECTOR_BITS; + return off / s->cluster_size; +} + static int64_t block_status(BDRVParallelsState *s, int64_t sector_num, int nb_sectors, int *pnum) { @@ -188,7 +194,8 @@ allocate_clusters(BlockDriverState *bs, int64_t sector_num, idx = sector_num / s->tracks; to_allocate = DIV_ROUND_UP(sector_num + *pnum, s->tracks) - idx; - /* This function is called only by parallels_co_writev(), which will never + /* + * This function is called only by parallels_co_writev(), which will never * pass a sector_num at or beyond the end of the image (because the block * layer never passes such a sector_num to that function). Therefore, idx * is always below s->bat_size. @@ -196,7 +203,8 @@ allocate_clusters(BlockDriverState *bs, int64_t sector_num, * exceed the image end. Therefore, idx + to_allocate cannot exceed * s->bat_size. * Note that s->bat_size is an unsigned int, therefore idx + to_allocate - * will always fit into a uint32_t. */ + * will always fit into a uint32_t. + */ assert(idx < s->bat_size && idx + to_allocate <= s->bat_size); space = to_allocate * s->tracks; @@ -230,13 +238,15 @@ allocate_clusters(BlockDriverState *bs, int64_t sector_num, } } - /* Try to read from backing to fill empty clusters + /* + * Try to read from backing to fill empty clusters * FIXME: 1. previous write_zeroes may be redundant * 2. most of data we read from backing will be rewritten by * parallels_co_writev. On aligned-to-cluster write we do not need * this read at all. * 3. it would be good to combine write of data from backing and new - * data into one write call */ + * data into one write call. + */ if (bs->backing) { int64_t nb_cow_sectors = to_allocate * s->tracks; int64_t nb_cow_bytes = nb_cow_sectors << BDRV_SECTOR_BITS; @@ -440,6 +450,81 @@ static void parallels_check_unclean(BlockDriverState *bs, } } +/* + * Returns true if data_off is correct, otherwise false. In both cases + * correct_offset is set to the proper value. + */ +static bool parallels_test_data_off(BDRVParallelsState *s, + int64_t file_nb_sectors, + uint32_t *correct_offset) +{ + uint32_t data_off, min_off; + bool old_magic; + + /* + * There are two slightly different image formats: with "WithoutFreeSpace" + * or "WithouFreSpacExt" magic words. Call the first one as "old magic". + * In such images data_off field can be zero. In this case the offset is + * calculated as the end of BAT table plus some padding to ensure sector + * size alignment. + */ + old_magic = !memcmp(s->header->magic, HEADER_MAGIC, 16); + + min_off = DIV_ROUND_UP(bat_entry_off(s->bat_size), BDRV_SECTOR_SIZE); + if (!old_magic) { + min_off = ROUND_UP(min_off, s->cluster_size / BDRV_SECTOR_SIZE); + } + + if (correct_offset) { + *correct_offset = min_off; + } + + data_off = le32_to_cpu(s->header->data_off); + if (data_off == 0 && old_magic) { + return true; + } + + if (data_off < min_off || data_off > file_nb_sectors) { + return false; + } + + if (correct_offset) { + *correct_offset = data_off; + } + + return true; +} + +static int coroutine_fn GRAPH_RDLOCK +parallels_check_data_off(BlockDriverState *bs, BdrvCheckResult *res, + BdrvCheckMode fix) +{ + BDRVParallelsState *s = bs->opaque; + int64_t file_size; + uint32_t data_off; + + file_size = bdrv_co_nb_sectors(bs->file->bs); + if (file_size < 0) { + res->check_errors++; + return file_size; + } + + if (parallels_test_data_off(s, file_size, &data_off)) { + return 0; + } + + res->corruptions++; + if (fix & BDRV_FIX_ERRORS) { + s->header->data_off = cpu_to_le32(data_off); + res->corruptions_fixed++; + } + + fprintf(stderr, "%s data_off field has incorrect value\n", + fix & BDRV_FIX_ERRORS ? "Repairing" : "ERROR"); + + return 0; +} + static int coroutine_fn GRAPH_RDLOCK parallels_check_outside_image(BlockDriverState *bs, BdrvCheckResult *res, BdrvCheckMode fix) @@ -484,13 +569,13 @@ parallels_check_outside_image(BlockDriverState *bs, BdrvCheckResult *res, static int coroutine_fn GRAPH_RDLOCK parallels_check_leak(BlockDriverState *bs, BdrvCheckResult *res, - BdrvCheckMode fix) + BdrvCheckMode fix, bool explicit) { BDRVParallelsState *s = bs->opaque; int64_t size; int ret; - size = bdrv_getlength(bs->file->bs); + size = bdrv_co_getlength(bs->file->bs); if (size < 0) { res->check_errors++; return size; @@ -499,10 +584,13 @@ parallels_check_leak(BlockDriverState *bs, BdrvCheckResult *res, if (size > res->image_end_offset) { int64_t count; count = DIV_ROUND_UP(size - res->image_end_offset, s->cluster_size); - fprintf(stderr, "%s space leaked at the end of the image %" PRId64 "\n", - fix & BDRV_FIX_LEAKS ? "Repairing" : "ERROR", - size - res->image_end_offset); - res->leaks += count; + if (explicit) { + fprintf(stderr, + "%s space leaked at the end of the image %" PRId64 "\n", + fix & BDRV_FIX_LEAKS ? "Repairing" : "ERROR", + size - res->image_end_offset); + res->leaks += count; + } if (fix & BDRV_FIX_LEAKS) { Error *local_err = NULL; @@ -517,13 +605,148 @@ parallels_check_leak(BlockDriverState *bs, BdrvCheckResult *res, res->check_errors++; return ret; } - res->leaks_fixed += count; + if (explicit) { + res->leaks_fixed += count; + } } } return 0; } +static int coroutine_fn GRAPH_RDLOCK +parallels_check_duplicate(BlockDriverState *bs, BdrvCheckResult *res, + BdrvCheckMode fix) +{ + BDRVParallelsState *s = bs->opaque; + int64_t host_off, host_sector, guest_sector; + unsigned long *bitmap; + uint32_t i, bitmap_size, cluster_index, bat_entry; + int n, ret = 0; + uint64_t *buf = NULL; + bool fixed = false; + + /* + * Create a bitmap of used clusters. + * If a bit is set, there is a BAT entry pointing to this cluster. + * Loop through the BAT entries, check bits relevant to an entry offset. + * If bit is set, this entry is duplicated. Otherwise set the bit. + * + * We shouldn't worry about newly allocated clusters outside the image + * because they are created higher then any existing cluster pointed by + * a BAT entry. + */ + bitmap_size = host_cluster_index(s, res->image_end_offset); + if (bitmap_size == 0) { + return 0; + } + if (res->image_end_offset % s->cluster_size) { + /* A not aligned image end leads to a bitmap shorter by 1 */ + bitmap_size++; + } + + bitmap = bitmap_new(bitmap_size); + + buf = qemu_blockalign(bs, s->cluster_size); + + for (i = 0; i < s->bat_size; i++) { + host_off = bat2sect(s, i) << BDRV_SECTOR_BITS; + if (host_off == 0) { + continue; + } + + cluster_index = host_cluster_index(s, host_off); + assert(cluster_index < bitmap_size); + if (!test_bit(cluster_index, bitmap)) { + bitmap_set(bitmap, cluster_index, 1); + continue; + } + + /* this cluster duplicates another one */ + fprintf(stderr, "%s duplicate offset in BAT entry %u\n", + fix & BDRV_FIX_ERRORS ? "Repairing" : "ERROR", i); + + res->corruptions++; + + if (!(fix & BDRV_FIX_ERRORS)) { + continue; + } + + /* + * Reset the entry and allocate a new cluster + * for the relevant guest offset. In this way we let + * the lower layer to place the new cluster properly. + * Copy the original cluster to the allocated one. + * But before save the old offset value for repairing + * if we have an error. + */ + bat_entry = s->bat_bitmap[i]; + parallels_set_bat_entry(s, i, 0); + + ret = bdrv_co_pread(bs->file, host_off, s->cluster_size, buf, 0); + if (ret < 0) { + res->check_errors++; + goto out_repair_bat; + } + + guest_sector = (i * (int64_t)s->cluster_size) >> BDRV_SECTOR_BITS; + host_sector = allocate_clusters(bs, guest_sector, s->tracks, &n); + if (host_sector < 0) { + res->check_errors++; + goto out_repair_bat; + } + host_off = host_sector << BDRV_SECTOR_BITS; + + ret = bdrv_co_pwrite(bs->file, host_off, s->cluster_size, buf, 0); + if (ret < 0) { + res->check_errors++; + goto out_repair_bat; + } + + if (host_off + s->cluster_size > res->image_end_offset) { + res->image_end_offset = host_off + s->cluster_size; + } + + /* + * In the future allocate_cluster() will reuse holed offsets + * inside the image. Keep the used clusters bitmap content + * consistent for the new allocated clusters too. + * + * Note, clusters allocated outside the current image are not + * considered, and the bitmap size doesn't change. + */ + cluster_index = host_cluster_index(s, host_off); + if (cluster_index < bitmap_size) { + bitmap_set(bitmap, cluster_index, 1); + } + + fixed = true; + res->corruptions_fixed++; + + } + + if (fixed) { + /* + * When new clusters are allocated, the file size increases by + * 128 Mb. We need to truncate the file to the right size. Let + * the leak fix code make its job without res changing. + */ + ret = parallels_check_leak(bs, res, fix, false); + } + +out_free: + g_free(buf); + g_free(bitmap); + return ret; +/* + * We can get here only from places where index and old_offset have + * meaningful values. + */ +out_repair_bat: + s->bat_bitmap[i] = bat_entry; + goto out_free; +} + static void parallels_collect_statistics(BlockDriverState *bs, BdrvCheckResult *res, BdrvCheckMode fix) @@ -565,12 +788,22 @@ parallels_co_check(BlockDriverState *bs, BdrvCheckResult *res, WITH_QEMU_LOCK_GUARD(&s->lock) { parallels_check_unclean(bs, res, fix); + ret = parallels_check_data_off(bs, res, fix); + if (ret < 0) { + return ret; + } + ret = parallels_check_outside_image(bs, res, fix); if (ret < 0) { return ret; } - ret = parallels_check_leak(bs, res, fix); + ret = parallels_check_leak(bs, res, fix, true); + if (ret < 0) { + return ret; + } + + ret = parallels_check_duplicate(bs, res, fix); if (ret < 0) { return ret; } @@ -798,10 +1031,12 @@ static int parallels_open(BlockDriverState *bs, QDict *options, int flags, BDRVParallelsState *s = bs->opaque; ParallelsHeader ph; int ret, size, i; - int64_t file_nb_sectors; + int64_t file_nb_sectors, sector; + uint32_t data_start; QemuOpts *opts = NULL; Error *local_err = NULL; char *buf; + bool data_off_is_correct; ret = bdrv_open_file_child(NULL, options, "file", bs, errp); if (ret < 0) { @@ -859,15 +1094,6 @@ static int parallels_open(BlockDriverState *bs, QDict *options, int flags, ret = -ENOMEM; goto fail; } - s->data_end = le32_to_cpu(ph.data_off); - if (s->data_end == 0) { - s->data_end = ROUND_UP(bat_entry_off(s->bat_size), BDRV_SECTOR_SIZE); - } - if (s->data_end < s->header_size) { - /* there is not enough unused space to fit to block align between BAT - and actual data. We can't avoid read-modify-write... */ - s->header_size = size; - } ret = bdrv_pread(bs->file, 0, s->header_size, s->header, 0); if (ret < 0) { @@ -875,33 +1101,20 @@ static int parallels_open(BlockDriverState *bs, QDict *options, int flags, } s->bat_bitmap = (uint32_t *)(s->header + 1); - for (i = 0; i < s->bat_size; i++) { - int64_t off = bat2sect(s, i); - if (off >= file_nb_sectors) { - if (flags & BDRV_O_CHECK) { - continue; - } - error_setg(errp, "parallels: Offset %" PRIi64 " in BAT[%d] entry " - "is larger than file size (%" PRIi64 ")", - off << BDRV_SECTOR_BITS, i, - file_nb_sectors << BDRV_SECTOR_BITS); - ret = -EINVAL; - goto fail; - } - if (off >= s->data_end) { - s->data_end = off + s->tracks; - } - } - if (le32_to_cpu(ph.inuse) == HEADER_INUSE_MAGIC) { - /* Image was not closed correctly. The check is mandatory */ s->header_unclean = true; - if ((flags & BDRV_O_RDWR) && !(flags & BDRV_O_CHECK)) { - error_setg(errp, "parallels: Image was not closed correctly; " - "cannot be opened read/write"); - ret = -EACCES; - goto fail; - } + } + + data_off_is_correct = parallels_test_data_off(s, file_nb_sectors, + &data_start); + s->data_start = data_start; + s->data_end = s->data_start; + if (s->data_end < (s->header_size >> BDRV_SECTOR_BITS)) { + /* + * There is not enough unused space to fit to block align between BAT + * and actual data. We can't avoid read-modify-write... + */ + s->header_size = size; } opts = qemu_opts_create(¶llels_runtime_opts, NULL, 0, errp); @@ -962,10 +1175,41 @@ static int parallels_open(BlockDriverState *bs, QDict *options, int flags, bdrv_get_device_or_node_name(bs)); ret = migrate_add_blocker(s->migration_blocker, errp); if (ret < 0) { - error_free(s->migration_blocker); + error_setg(errp, "Migration blocker error"); goto fail; } qemu_co_mutex_init(&s->lock); + + for (i = 0; i < s->bat_size; i++) { + sector = bat2sect(s, i); + if (sector + s->tracks > s->data_end) { + s->data_end = sector + s->tracks; + } + } + + /* + * We don't repair the image here if it's opened for checks. Also we don't + * want to change inactive images and can't change readonly images. + */ + if ((flags & (BDRV_O_CHECK | BDRV_O_INACTIVE)) || !(flags & BDRV_O_RDWR)) { + return 0; + } + + /* + * Repair the image if it's dirty or + * out-of-image corruption was detected. + */ + if (s->data_end > file_nb_sectors || s->header_unclean + || !data_off_is_correct) { + BdrvCheckResult res; + ret = bdrv_check(bs, &res, BDRV_FIX_ERRORS | BDRV_FIX_LEAKS); + if (ret < 0) { + error_setg_errno(errp, -ret, "Could not repair corrupted image"); + migrate_del_blocker(s->migration_blocker); + goto fail; + } + } + return 0; fail_format: @@ -973,6 +1217,12 @@ fail_format: fail_options: ret = -EINVAL; fail: + /* + * "s" object was allocated by g_malloc0 so we can safely + * try to free its fields even they were not allocated. + */ + error_free(s->migration_blocker); + g_free(s->bat_dirty_bmap); qemu_vfree(s->header); return ret; } diff --git a/block/parallels.h b/block/parallels.h index f22f43f988..4e53e9572d 100644 --- a/block/parallels.h +++ b/block/parallels.h @@ -75,6 +75,7 @@ typedef struct BDRVParallelsState { uint32_t *bat_bitmap; unsigned int bat_size; + int64_t data_start; int64_t data_end; uint64_t prealloc_size; ParallelsPreallocMode prealloc_mode; diff --git a/bsd-user/bsd-file.h b/bsd-user/bsd-file.h index 588e0c50d4..3c00dc0056 100644 --- a/bsd-user/bsd-file.h +++ b/bsd-user/bsd-file.h @@ -51,10 +51,8 @@ do { \ unlock_user(p1, arg1, 0); \ } while (0) -extern struct iovec *lock_iovec(int type, abi_ulong target_addr, int count, - int copy); -extern void unlock_iovec(struct iovec *vec, abi_ulong target_addr, int count, - int copy); +struct iovec *lock_iovec(int type, abi_ulong target_addr, int count, int copy); +void unlock_iovec(struct iovec *vec, abi_ulong target_addr, int count, int copy); int safe_open(const char *path, int flags, mode_t mode); int safe_openat(int fd, const char *path, int flags, mode_t mode); diff --git a/contrib/plugins/cache.c b/contrib/plugins/cache.c index 0b636d53ae..4fca3edd07 100644 --- a/contrib/plugins/cache.c +++ b/contrib/plugins/cache.c @@ -350,7 +350,7 @@ static int in_cache(Cache *cache, uint64_t addr) * @cache: The cache under simulation * @addr: The address of the requested memory location * - * Returns true if the requsted data is hit in the cache and false when missed. + * Returns true if the requested data is hit in the cache and false when missed. * The cache is updated on miss for the next access. */ static bool access_cache(Cache *cache, uint64_t addr) diff --git a/contrib/plugins/lockstep.c b/contrib/plugins/lockstep.c index 57748e86eb..682b11feb2 100644 --- a/contrib/plugins/lockstep.c +++ b/contrib/plugins/lockstep.c @@ -108,7 +108,7 @@ static void report_divergance(ExecState *us, ExecState *them) /* * If we have diverged before did we get back on track or are we - * totally loosing it? + * totally losing it? */ if (divergence_log) { DivergeState *last = (DivergeState *) divergence_log->data; diff --git a/crypto/hmacpriv.h b/crypto/hmacpriv.h index 4387ca2587..62dfe8257a 100644 --- a/crypto/hmacpriv.h +++ b/crypto/hmacpriv.h @@ -28,19 +28,18 @@ struct QCryptoHmacDriver { void (*hmac_free)(QCryptoHmac *hmac); }; -extern void *qcrypto_hmac_ctx_new(QCryptoHashAlgorithm alg, - const uint8_t *key, size_t nkey, - Error **errp); +void *qcrypto_hmac_ctx_new(QCryptoHashAlgorithm alg, + const uint8_t *key, size_t nkey, + Error **errp); extern QCryptoHmacDriver qcrypto_hmac_lib_driver; #ifdef CONFIG_AF_ALG #include "afalgpriv.h" -extern QCryptoAFAlg * -qcrypto_afalg_hmac_ctx_new(QCryptoHashAlgorithm alg, - const uint8_t *key, size_t nkey, - Error **errp); +QCryptoAFAlg *qcrypto_afalg_hmac_ctx_new(QCryptoHashAlgorithm alg, + const uint8_t *key, size_t nkey, + Error **errp); extern QCryptoHmacDriver qcrypto_hmac_afalg_driver; #endif diff --git a/docs/about/build-platforms.rst b/docs/about/build-platforms.rst index 0e2cb9e770..f2a7aec56f 100644 --- a/docs/about/build-platforms.rst +++ b/docs/about/build-platforms.rst @@ -52,7 +52,7 @@ Those hosts are officially supported, with various accelerators: * - SPARC - tcg * - x86 - - hax, hvf (64 bit only), kvm, nvmm, tcg, whpx (64 bit only), xen + - hvf (64 bit only), kvm, nvmm, tcg, whpx (64 bit only), xen Other host architectures are not supported. It is possible to build QEMU system emulation on an unsupported host architecture using the configure diff --git a/docs/about/deprecated.rst b/docs/about/deprecated.rst index 92a2bafd2b..dc4da95329 100644 --- a/docs/about/deprecated.rst +++ b/docs/about/deprecated.rst @@ -105,12 +105,6 @@ Use ``-machine hpet=off`` instead. The ``-no-acpi`` setting has been turned into a machine property. Use ``-machine acpi=off`` instead. -``-accel hax`` (since 8.0) -'''''''''''''''''''''''''' - -The HAXM project has been retired (see https://github.com/intel/haxm#status). -Use "whpx" (on Windows) or "hvf" (on macOS) instead. - ``-async-teardown`` (since 8.1) ''''''''''''''''''''''''''''''' diff --git a/docs/about/index.rst b/docs/about/index.rst index b00b584b31..4f96ab5d91 100644 --- a/docs/about/index.rst +++ b/docs/about/index.rst @@ -8,7 +8,7 @@ QEMU can be used in several different ways. The most common is for :ref:`System Emulation`, where it provides a virtual model of an entire machine (CPU, memory and emulated devices) to run a guest OS. In this mode the CPU may be fully emulated, or it may work with a -hypervisor such as KVM, Xen, Hax or Hypervisor.Framework to allow the +hypervisor such as KVM, Xen or Hypervisor.Framework to allow the guest to run directly on the host CPU. The second supported way to use QEMU is :ref:`User Mode Emulation`, diff --git a/docs/about/removed-features.rst b/docs/about/removed-features.rst index 5b258b446b..c2043fd415 100644 --- a/docs/about/removed-features.rst +++ b/docs/about/removed-features.rst @@ -659,15 +659,18 @@ Use ``Icelake-Server`` instead. System accelerators ------------------- -Userspace local APIC with KVM (x86, removed 8.0) -'''''''''''''''''''''''''''''''''''''''''''''''' +Userspace local APIC with KVM (x86, removed in 8.0) +''''''''''''''''''''''''''''''''''''''''''''''''''' ``-M kernel-irqchip=off`` cannot be used on KVM if the CPU model includes a local APIC. The ``split`` setting is supported, as is using ``-M kernel-irqchip=off`` when the CPU does not have a local APIC. -System accelerators -------------------- +HAXM (``-accel hax``) (removed in 8.2) +'''''''''''''''''''''''''''''''''''''' + +The HAXM project has been retired (see https://github.com/intel/haxm#status). +Use "whpx" (on Windows) or "hvf" (on macOS) instead. MIPS "Trap-and-Emulate" KVM support (removed in 8.0) '''''''''''''''''''''''''''''''''''''''''''''''''''' diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index 80538422a1..b2dea54eed 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -104,7 +104,7 @@ To boot a kernel directly from a Linux build tree: -dtb arch/arm/boot/dts/aspeed-ast2600-evb.dtb \ -initrd rootfs.cpio -The image should be attached as an MTD drive. Run : +To boot the machine from the flash image, use an MTD drive : .. code-block:: bash @@ -117,23 +117,46 @@ Options specific to Aspeed machines are : device by using the FMC controller to load the instructions, and not simply from RAM. This takes a little longer. - * ``fmc-model`` to change the FMC Flash model. FW needs support for - the chip model to boot. + * ``fmc-model`` to change the default FMC Flash model. FW needs + support for the chip model to boot. - * ``spi-model`` to change the SPI Flash model. + * ``spi-model`` to change the default SPI Flash model. * ``bmc-console`` to change the default console device. Most of the machines use the ``UART5`` device for a boot console, which is mapped on ``/dev/ttyS4`` under Linux, but it is not always the case. -For instance, to start the ``ast2500-evb`` machine with a different -FMC chip and a bigger (64M) SPI chip, use : +To use other flash models, for instance a different FMC chip and a +bigger (64M) SPI for the ``ast2500-evb`` machine, run : .. code-block:: bash -M ast2500-evb,fmc-model=mx25l25635e,spi-model=mx66u51235f +When more flexibility is needed to define the flash devices, to use +different flash models or define all flash devices (up to 8), the +``-nodefaults`` QEMU option can be used to avoid creating the default +flash devices. + +Flash devices should then be created from the command line and attached +to a block device : + +.. code-block:: bash + + $ qemu-system-arm -M ast2600-evb \ + -blockdev node-name=fmc0,driver=file,filename=/path/to/fmc0.img \ + -device mx66u51235f,bus=ssi.0,cs=0x0,drive=fmc0 \ + -blockdev node-name=fmc1,driver=file,filename=/path/to/fmc1.img \ + -device mx66u51235f,bus=ssi.0,cs=0x1,drive=fmc1 \ + -blockdev node-name=spi1,driver=file,filename=/path/to/spi1.img \ + -device mx66u51235f,cs=0x0,bus=ssi.1,drive=spi1 \ + -nographic -nodefaults + +In that case, the machine boots fetching instructions from the FMC0 +device. It is slower to start but closer to what HW does. Using the +machine option ``execute-in-place`` has a similar effect. + To change the boot console and use device ``UART3`` (``/dev/ttyS2`` under Linux), use : diff --git a/docs/system/index.rst b/docs/system/index.rst index 3605bbe1ce..45bf1f19e7 100644 --- a/docs/system/index.rst +++ b/docs/system/index.rst @@ -6,7 +6,7 @@ System Emulation This section of the manual is the overall guide for users using QEMU for full system emulation (as opposed to user-mode emulation). -This includes working with hypervisors such as KVM, Xen, Hax +This includes working with hypervisors such as KVM, Xen or Hypervisor.Framework. .. toctree:: diff --git a/docs/system/introduction.rst b/docs/system/introduction.rst index 3e256f8326..51ac132d6c 100644 --- a/docs/system/introduction.rst +++ b/docs/system/introduction.rst @@ -21,9 +21,6 @@ Tiny Code Generator (TCG) capable of emulating many CPUs. * - Xen - Linux (as dom0) - Arm, x86 - * - Intel HAXM (hax) - - Linux, Windows - - x86 * - Hypervisor Framework (hvf) - MacOS - x86 (64 bit only), Arm (64 bit only) diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 263626abea..f8ba67531a 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -15,6 +15,7 @@ #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" #include "hw/arm/aspeed_eeprom.h" +#include "hw/block/flash.h" #include "hw/i2c/i2c_mux_pca954x.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/misc/pca9552.h" @@ -47,6 +48,13 @@ struct AspeedMachineState { char *spi_model; }; +/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ +#if HOST_LONG_BITS == 32 +#define ASPEED_RAM_SIZE(sz) MIN((sz), 1 * GiB) +#else +#define ASPEED_RAM_SIZE(sz) (sz) +#endif + /* Palmetto hardware value: 0x120CE416 */ #define PALMETTO_BMC_HW_STRAP1 ( \ SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_256MB) | \ @@ -300,17 +308,14 @@ void aspeed_board_init_flashes(AspeedSMCState *s, const char *flashtype, for (i = 0; i < count; ++i) { DriveInfo *dinfo = drive_get(IF_MTD, 0, unit0 + i); - qemu_irq cs_line; DeviceState *dev; dev = qdev_new(flashtype); if (dinfo) { qdev_prop_set_drive(dev, "drive", blk_by_legacy_dinfo(dinfo)); } + qdev_prop_set_uint8(dev, "cs", i); qdev_realize_and_unref(dev, BUS(s->spi), &error_fatal); - - cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); - qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line); } } @@ -392,12 +397,14 @@ static void aspeed_machine_init(MachineState *machine) connect_serial_hds_to_uarts(bmc); qdev_realize(DEVICE(&bmc->soc), NULL, &error_abort); - aspeed_board_init_flashes(&bmc->soc.fmc, + if (defaults_enabled()) { + aspeed_board_init_flashes(&bmc->soc.fmc, bmc->fmc_model ? bmc->fmc_model : amc->fmc_model, amc->num_cs, 0); - aspeed_board_init_flashes(&bmc->soc.spi[0], + aspeed_board_init_flashes(&bmc->soc.spi[0], bmc->spi_model ? bmc->spi_model : amc->spi_model, 1, amc->num_cs); + } if (machine->kernel_filename && sc->num_cpus > 1) { /* With no u-boot we must set up a boot stub for the secondary CPU */ @@ -430,11 +437,12 @@ static void aspeed_machine_init(MachineState *machine) } if (!bmc->mmio_exec) { - DriveInfo *mtd0 = drive_get(IF_MTD, 0, 0); + DeviceState *dev = ssi_get_cs(bmc->soc.fmc.spi, 0); + BlockBackend *fmc0 = dev ? m25p80_get_blk(dev) : NULL; - if (mtd0) { + if (fmc0) { uint64_t rom_size = memory_region_size(&bmc->soc.spi_boot); - aspeed_install_boot_rom(bmc, blk_by_legacy_dinfo(mtd0), rom_size); + aspeed_install_boot_rom(bmc, fmc0, rom_size); } } @@ -1423,12 +1431,7 @@ static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) aspeed_soc_num_cpus(amc->soc_name); }; -/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ -#if HOST_LONG_BITS == 32 -#define FUJI_BMC_RAM_SIZE (1 * GiB) -#else -#define FUJI_BMC_RAM_SIZE (2 * GiB) -#endif +#define FUJI_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) { @@ -1450,12 +1453,7 @@ static void aspeed_machine_fuji_class_init(ObjectClass *oc, void *data) aspeed_soc_num_cpus(amc->soc_name); }; -/* On 32-bit hosts, lower RAM to 1G because of the 2047 MB limit */ -#if HOST_LONG_BITS == 32 -#define BLETCHLEY_BMC_RAM_SIZE (1 * GiB) -#else -#define BLETCHLEY_BMC_RAM_SIZE (2 * GiB) -#endif +#define BLETCHLEY_BMC_RAM_SIZE ASPEED_RAM_SIZE(2 * GiB) static void aspeed_machine_bletchley_class_init(ObjectClass *oc, void *data) { diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index f7e99baf62..aa5b0ddfaa 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1235,14 +1235,15 @@ static void stellaris_init(MachineState *ms, stellaris_board_info *board) dinfo = drive_get(IF_SD, 0, 0); blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; - carddev = qdev_new(TYPE_SD_CARD); + carddev = qdev_new(TYPE_SD_CARD_SPI); qdev_prop_set_drive_err(carddev, "drive", blk, &error_fatal); - qdev_prop_set_bit(carddev, "spi", true); qdev_realize_and_unref(carddev, qdev_get_child_bus(sddev, "sd-bus"), &error_fatal); - ssddev = ssi_create_peripheral(bus, "ssd0323"); + ssddev = qdev_new("ssd0323"); + qdev_prop_set_uint8(ssddev, "cs", 1); + qdev_realize_and_unref(ssddev, bus, &error_fatal); gpio_d_splitter = qdev_new(TYPE_SPLIT_IRQ); qdev_prop_set_uint32(gpio_d_splitter, "num-lines", 2); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 3190cc0b8d..8dc2ea83a9 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -164,6 +164,7 @@ static inline int zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, blk_by_legacy_dinfo(dinfo), &error_fatal); } + qdev_prop_set_uint8(flash_dev, "cs", j); qdev_realize_and_unref(flash_dev, BUS(spi), &error_fatal); cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 1ee2b8697f..88c561ff63 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -740,6 +740,7 @@ static void versal_virt_init(MachineState *machine) qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), &error_fatal); } + qdev_prop_set_uint8(flash_dev, "cs", i); qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index 4c84bb932a..21483f75fd 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -201,6 +201,7 @@ static void xlnx_zcu102_init(MachineState *machine) qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), &error_fatal); } + qdev_prop_set_uint8(flash_dev, "cs", i); qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); @@ -224,6 +225,7 @@ static void xlnx_zcu102_init(MachineState *machine) qdev_prop_set_drive_err(flash_dev, "drive", blk_by_legacy_dinfo(dinfo), &error_fatal); } + qdev_prop_set_uint8(flash_dev, "cs", i); qdev_realize_and_unref(flash_dev, spi_bus, &error_fatal); cs_line = qdev_get_gpio_in_named(flash_dev, SSI_GPIO_CS, 0); diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index dc5ffbc4ff..afc3fdf4d6 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -25,6 +25,7 @@ #include "qemu/units.h" #include "sysemu/block-backend.h" #include "hw/block/block.h" +#include "hw/block/flash.h" #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" #include "hw/ssi/ssi.h" @@ -1830,3 +1831,8 @@ static void m25p80_register_types(void) } type_init(m25p80_register_types) + +BlockBackend *m25p80_get_blk(DeviceState *dev) +{ + return M25P80(dev)->blk; +} diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 807e398541..eff0304a18 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -307,11 +307,11 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond, /* instant drain the fifo when there's no back-end */ if (!qemu_chr_fe_backend_connected(&s->chr)) { s->tx_count = 0; - return FALSE; + return G_SOURCE_REMOVE; } if (!s->tx_count) { - return FALSE; + return G_SOURCE_REMOVE; } ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_count); @@ -326,12 +326,12 @@ static gboolean cadence_uart_xmit(void *do_not_use, GIOCondition cond, cadence_uart_xmit, s); if (!r) { s->tx_count = 0; - return FALSE; + return G_SOURCE_REMOVE; } } uart_update_status(s); - return FALSE; + return G_SOURCE_REMOVE; } static void uart_write_tx_fifo(CadenceUARTState *s, const uint8_t *buf, diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c index f8dc89ee3d..d466cd93de 100644 --- a/hw/char/cmsdk-apb-uart.c +++ b/hw/char/cmsdk-apb-uart.c @@ -199,7 +199,7 @@ static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque) s->watch_tag = 0; if (!(s->ctrl & R_CTRL_TX_EN_MASK) || !(s->state & R_STATE_TXFULL_MASK)) { - return FALSE; + return G_SOURCE_REMOVE; } ret = qemu_chr_fe_write(&s->chr, &s->txbuf, 1); @@ -215,7 +215,7 @@ static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque) } /* Transmit pending */ trace_cmsdk_apb_uart_tx_pending(); - return FALSE; + return G_SOURCE_REMOVE; } buffer_drained: @@ -227,7 +227,7 @@ buffer_drained: s->intstatus |= R_INTSTATUS_TX_MASK; } cmsdk_apb_uart_update(s); - return FALSE; + return G_SOURCE_REMOVE; } static void uart_cancel_transmit(CMSDKAPBUART *s) diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index f70adb5308..51708c0836 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -147,7 +147,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond, /* instant drain the fifo when there's no back-end */ if (!qemu_chr_fe_backend_connected(&s->chr)) { s->tx_level = 0; - return FALSE; + return G_SOURCE_REMOVE; } if (!s->tx_level) { @@ -156,7 +156,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond, s->uart_intr_state |= R_INTR_STATE_TX_EMPTY_MASK; s->uart_intr_state &= ~R_INTR_STATE_TX_WATERMARK_MASK; ibex_uart_update_irqs(s); - return FALSE; + return G_SOURCE_REMOVE; } ret = qemu_chr_fe_write(&s->chr, s->tx_fifo, s->tx_level); @@ -171,7 +171,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond, ibex_uart_xmit, s); if (!r) { s->tx_level = 0; - return FALSE; + return G_SOURCE_REMOVE; } } @@ -192,7 +192,7 @@ static gboolean ibex_uart_xmit(void *do_not_use, GIOCondition cond, } ibex_uart_update_irqs(s); - return FALSE; + return G_SOURCE_REMOVE; } static void uart_write_tx_fifo(IbexUartState *s, const uint8_t *buf, diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c index 3c6f982de9..dfe2276d71 100644 --- a/hw/char/nrf51_uart.c +++ b/hw/char/nrf51_uart.c @@ -93,13 +93,13 @@ static gboolean uart_transmit(void *do_not_use, GIOCondition cond, void *opaque) */ goto buffer_drained; } - return FALSE; + return G_SOURCE_REMOVE; } buffer_drained: s->reg[R_UART_TXDRDY] = 1; s->pending_tx_byte = false; - return FALSE; + return G_SOURCE_REMOVE; } static void uart_cancel_transmit(NRF51UARTState *s) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 77bbc2a982..58edeb9ddb 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -48,14 +48,15 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) return dev; } -#define PL011_INT_TX 0x20 -#define PL011_INT_RX 0x10 - +/* Flag Register, UARTFR */ #define PL011_FLAG_TXFE 0x80 #define PL011_FLAG_RXFF 0x40 #define PL011_FLAG_TXFF 0x20 #define PL011_FLAG_RXFE 0x10 +/* Data Register, UARTDR */ +#define DR_BE (1 << 10) + /* Interrupt status bits in UARTRIS, UARTMIS, UARTIMSC */ #define INT_OE (1 << 10) #define INT_BE (1 << 9) @@ -71,11 +72,33 @@ DeviceState *pl011_create(hwaddr addr, qemu_irq irq, Chardev *chr) #define INT_E (INT_OE | INT_BE | INT_PE | INT_FE) #define INT_MS (INT_RI | INT_DSR | INT_DCD | INT_CTS) +/* Line Control Register, UARTLCR_H */ +#define LCR_FEN (1 << 4) +#define LCR_BRK (1 << 0) + static const unsigned char pl011_id_arm[8] = { 0x11, 0x10, 0x14, 0x00, 0x0d, 0xf0, 0x05, 0xb1 }; static const unsigned char pl011_id_luminary[8] = { 0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1 }; +static const char *pl011_regname(hwaddr offset) +{ + static const char *const rname[] = { + [0] = "DR", [1] = "RSR", [6] = "FR", [8] = "ILPR", [9] = "IBRD", + [10] = "FBRD", [11] = "LCRH", [12] = "CR", [13] = "IFLS", [14] = "IMSC", + [15] = "RIS", [16] = "MIS", [17] = "ICR", [18] = "DMACR", + }; + unsigned idx = offset >> 2; + + if (idx < ARRAY_SIZE(rname) && rname[idx]) { + return rname[idx]; + } + if (idx >= 0x3f8 && idx <= 0x400) { + return "ID"; + } + return "UNKN"; +} + /* Which bits in the interrupt status matter for each outbound IRQ line ? */ static const uint32_t irqmask[] = { INT_E | INT_MS | INT_RT | INT_TX | INT_RX, /* combined IRQ */ @@ -100,7 +123,7 @@ static void pl011_update(PL011State *s) static bool pl011_is_fifo_enabled(PL011State *s) { - return (s->lcr & 0x10) != 0; + return (s->lcr & LCR_FEN) != 0; } static inline unsigned pl011_get_fifo_depth(PL011State *s) @@ -138,7 +161,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, s->flags |= PL011_FLAG_RXFE; } if (s->read_count == s->read_trigger - 1) - s->int_level &= ~ PL011_INT_RX; + s->int_level &= ~ INT_RX; trace_pl011_read_fifo(s->read_count); s->rsr = c >> 8; pl011_update(s); @@ -191,7 +214,7 @@ static uint64_t pl011_read(void *opaque, hwaddr offset, break; } - trace_pl011_read(offset, r); + trace_pl011_read(offset, r, pl011_regname(offset)); return r; } @@ -202,7 +225,7 @@ static void pl011_set_read_trigger(PL011State *s) the threshold. However linux only reads the FIFO in response to an interrupt. Triggering the interrupt when the FIFO is non-empty seems to make things work. */ - if (s->lcr & 0x10) + if (s->lcr & LCR_FEN) s->read_trigger = (s->ifl >> 1) & 0x1c; else #endif @@ -234,7 +257,7 @@ static void pl011_write(void *opaque, hwaddr offset, PL011State *s = (PL011State *)opaque; unsigned char ch; - trace_pl011_write(offset, value); + trace_pl011_write(offset, value, pl011_regname(offset)); switch (offset >> 2) { case 0: /* UARTDR */ @@ -243,7 +266,7 @@ static void pl011_write(void *opaque, hwaddr offset, /* XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks */ qemu_chr_fe_write_all(&s->chr, &ch, 1); - s->int_level |= PL011_INT_TX; + s->int_level |= INT_TX; pl011_update(s); break; case 1: /* UARTRSR/UARTECR */ @@ -252,7 +275,7 @@ static void pl011_write(void *opaque, hwaddr offset, case 6: /* UARTFR */ /* Writes to Flag register are ignored. */ break; - case 8: /* UARTUARTILPR */ + case 8: /* UARTILPR */ s->ilpr = value; break; case 9: /* UARTIBRD */ @@ -265,11 +288,11 @@ static void pl011_write(void *opaque, hwaddr offset, break; case 11: /* UARTLCR_H */ /* Reset the FIFO state on FIFO enable or disable */ - if ((s->lcr ^ value) & 0x10) { + if ((s->lcr ^ value) & LCR_FEN) { pl011_reset_fifo(s); } - if ((s->lcr ^ value) & 0x1) { - int break_enable = value & 0x1; + if ((s->lcr ^ value) & LCR_BRK) { + int break_enable = value & LCR_BRK; qemu_chr_fe_ioctl(&s->chr, CHR_IOCTL_SERIAL_SET_BREAK, &break_enable); } @@ -331,7 +354,7 @@ static void pl011_put_fifo(void *opaque, uint32_t value) s->flags |= PL011_FLAG_RXFF; } if (s->read_count == s->read_trigger) { - s->int_level |= PL011_INT_RX; + s->int_level |= INT_RX; pl011_update(s); } } @@ -343,8 +366,9 @@ static void pl011_receive(void *opaque, const uint8_t *buf, int size) static void pl011_event(void *opaque, QEMUChrEvent event) { - if (event == CHR_EVENT_BREAK) - pl011_put_fifo(opaque, 0x400); + if (event == CHR_EVENT_BREAK) { + pl011_put_fifo(opaque, DR_BE); + } } static void pl011_clock_update(void *opaque, ClockEvent event) @@ -358,6 +382,8 @@ static const MemoryRegionOps pl011_ops = { .read = pl011_read, .write = pl011_write, .endianness = DEVICE_NATIVE_ENDIAN, + .impl.min_access_size = 4, + .impl.max_access_size = 4, }; static bool pl011_clock_needed(void *opaque) diff --git a/hw/char/serial.c b/hw/char/serial.c index 270e1b1094..f3094f860f 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -226,7 +226,7 @@ static gboolean serial_watch_cb(void *do_not_use, GIOCondition cond, SerialState *s = opaque; s->watch_tag = 0; serial_xmit(s); - return FALSE; + return G_SOURCE_REMOVE; } static void serial_xmit(SerialState *s) diff --git a/hw/char/trace-events b/hw/char/trace-events index 2ecb36232e..babf4d35ea 100644 --- a/hw/char/trace-events +++ b/hw/char/trace-events @@ -54,9 +54,9 @@ escc_sunmouse_event(int dx, int dy, int buttons_state) "dx=%d dy=%d buttons=0x%0 # pl011.c pl011_irq_state(int level) "irq state %d" -pl011_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_read(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" pl011_read_fifo(int read_count) "FIFO read, read_count now %d" -pl011_write(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" +pl011_write(uint32_t addr, uint32_t value, const char *regname) "addr 0x%03x value 0x%08x reg %s" pl011_can_receive(uint32_t lcr, int read_count, int r) "LCR 0x%08x read_count %d returning %d" pl011_put_fifo(uint32_t c, int read_count) "new char 0x%x read_count now %d" pl011_put_fifo_full(void) "FIFO now full, RXFF set" diff --git a/hw/char/virtio-console.c b/hw/char/virtio-console.c index dd5a02e339..dbe0b28e60 100644 --- a/hw/char/virtio-console.c +++ b/hw/char/virtio-console.c @@ -45,7 +45,7 @@ static gboolean chr_write_unblocked(void *do_not_use, GIOCondition cond, vcon->watch = 0; virtio_serial_throttle_port(VIRTIO_SERIAL_PORT(vcon), false); - return FALSE; + return G_SOURCE_REMOVE; } /* Callback function that's called when the guest sends us data */ diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index e7ec268184..9138e98c3b 100644 --- a/hw/display/bochs-display.c +++ b/hw/display/bochs-display.c @@ -164,7 +164,7 @@ static int bochs_display_get_mode(BochsDisplayState *s, memset(mode, 0, sizeof(*mode)); switch (vbe[VBE_DISPI_INDEX_BPP]) { case 16: - /* best effort: support native endianess only */ + /* best effort: support native endianness only */ mode->format = PIXMAN_r5g6b5; mode->bytepp = 2; break; diff --git a/hw/display/qxl.c b/hw/display/qxl.c index f1c0eb7dfc..af941fb0c2 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -1544,7 +1544,7 @@ static void qxl_create_guest_primary(PCIQXLDevice *qxl, int loadvm, } } -/* return 1 if surface destoy was initiated (in QXL_ASYNC case) or +/* return 1 if surface destroy was initiated (in QXL_ASYNC case) or * done (in QXL_SYNC case), 0 otherwise. */ static int qxl_destroy_primary(PCIQXLDevice *d, qxl_async_io async) { diff --git a/hw/display/ssd0303.c b/hw/display/ssd0303.c index d67b0ad7b5..32b32a3044 100644 --- a/hw/display/ssd0303.c +++ b/hw/display/ssd0303.c @@ -8,7 +8,7 @@ */ /* The controller can support a variety of different displays, but we only - implement one. Most of the commends relating to brightness and geometry + implement one. Most of the commands relating to brightness and geometry setup are ignored. */ #include "qemu/osdep.h" diff --git a/hw/display/ssd0323.c b/hw/display/ssd0323.c index ab229d32b7..09b1bbed0a 100644 --- a/hw/display/ssd0323.c +++ b/hw/display/ssd0323.c @@ -8,7 +8,7 @@ */ /* The controller can support a variety of different displays, but we only - implement one. Most of the commends relating to brightness and geometry + implement one. Most of the commands relating to brightness and geometry setup are ignored. */ #include "qemu/osdep.h" diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index b0828d65aa..822355ecc6 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -380,7 +380,7 @@ static inline void xlnx_dp_audio_mix_buffer(XlnxDPState *s) static void xlnx_dp_audio_callback(void *opaque, int avail) { /* - * Get some data from the DPDMA and compute these datas. + * Get some data from the DPDMA and compute these data. * Then wait for QEMU's audio subsystem to call this callback. */ XlnxDPState *s = XLNX_DP(opaque); diff --git a/hw/dma/etraxfs_dma.c b/hw/dma/etraxfs_dma.c index a1068b19ea..9c0003de51 100644 --- a/hw/dma/etraxfs_dma.c +++ b/hw/dma/etraxfs_dma.c @@ -28,6 +28,7 @@ #include "qemu/main-loop.h" #include "sysemu/runstate.h" #include "exec/address-spaces.h" +#include "exec/memory.h" #include "hw/cris/etraxfs_dma.h" diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 1f071a3811..7275d40749 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -226,7 +226,7 @@ static int aspeed_i2c_dma_read(AspeedI2CBus *bus, uint8_t *data) return 0; } -static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) +static int aspeed_i2c_bus_send(AspeedI2CBus *bus) { AspeedI2CClass *aic = ASPEED_I2C_GET_CLASS(bus->controller); int ret = -1; @@ -236,10 +236,10 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) uint32_t reg_byte_buf = aspeed_i2c_bus_byte_buf_offset(bus); uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); int pool_tx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, - TX_COUNT); + TX_COUNT) + 1; if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { - for (i = pool_start; i < pool_tx_count; i++) { + for (i = 0; i < pool_tx_count; i++) { uint8_t *pool_base = aic->bus_pool_base(bus); trace_aspeed_i2c_bus_send("BUF", i + 1, pool_tx_count, @@ -273,7 +273,7 @@ static int aspeed_i2c_bus_send(AspeedI2CBus *bus, uint8_t pool_start) } SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, TX_DMA_EN, 0); } else { - trace_aspeed_i2c_bus_send("BYTE", pool_start, 1, + trace_aspeed_i2c_bus_send("BYTE", 0, 1, bus->regs[reg_byte_buf]); ret = i2c_send(bus->bus, bus->regs[reg_byte_buf]); } @@ -293,10 +293,14 @@ static void aspeed_i2c_bus_recv(AspeedI2CBus *bus) uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); uint32_t reg_dma_addr = aspeed_i2c_bus_dma_addr_offset(bus); int pool_rx_count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, - RX_COUNT); + RX_SIZE) + 1; if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { uint8_t *pool_base = aic->bus_pool_base(bus); + if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, + BUF_ORGANIZATION)) { + pool_base += 16; + } for (i = 0; i < pool_rx_count; i++) { pool_base[i] = i2c_recv(bus->bus); @@ -418,7 +422,7 @@ static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_BUFF_EN)) { - count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT); + count = SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) + 1; } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, RX_DMA_EN)) { count = bus->regs[reg_dma_len]; } else { /* BYTE mode */ @@ -446,10 +450,8 @@ static void aspeed_i2c_bus_cmd_dump(AspeedI2CBus *bus) */ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) { - uint8_t pool_start = 0; uint32_t reg_intr_sts = aspeed_i2c_bus_intr_sts_offset(bus); uint32_t reg_cmd = aspeed_i2c_bus_cmd_offset(bus); - uint32_t reg_pool_ctrl = aspeed_i2c_bus_pool_ctrl_offset(bus); uint32_t reg_dma_len = aspeed_i2c_bus_dma_len_offset(bus); if (!aspeed_i2c_check_sram(bus)) { @@ -483,27 +485,11 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_START_CMD, 0); - /* - * The START command is also a TX command, as the slave - * address is sent on the bus. Drop the TX flag if nothing - * else needs to be sent in this sequence. - */ - if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { - if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_pool_ctrl, TX_COUNT) - == 1) { - SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); - } else { - /* - * Increase the start index in the TX pool buffer to - * skip the address byte. - */ - pool_start++; - } - } else if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { + if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_DMA_EN)) { if (bus->regs[reg_dma_len] == 0) { SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); } - } else { + } else if (!SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, TX_BUFF_EN)) { SHARED_ARRAY_FIELD_DP32(bus->regs, reg_cmd, M_TX_CMD, 0); } @@ -520,7 +506,7 @@ static void aspeed_i2c_bus_handle_cmd(AspeedI2CBus *bus, uint64_t value) if (SHARED_ARRAY_FIELD_EX32(bus->regs, reg_cmd, M_TX_CMD)) { aspeed_i2c_set_state(bus, I2CD_MTXD); - if (aspeed_i2c_bus_send(bus, pool_start)) { + if (aspeed_i2c_bus_send(bus)) { SHARED_ARRAY_FIELD_DP32(bus->regs, reg_intr_sts, TX_NAK, 1); i2c_end_transfer(bus->bus); } else { diff --git a/hw/i2c/pm_smbus.c b/hw/i2c/pm_smbus.c index d7eae548cb..9ad6a47739 100644 --- a/hw/i2c/pm_smbus.c +++ b/hw/i2c/pm_smbus.c @@ -1,6 +1,6 @@ /* * PC SMBus implementation - * splitted from acpi.c + * split from acpi.c * * Copyright (c) 2006 Fabrice Bellard * diff --git a/hw/i2c/pmbus_device.c b/hw/i2c/pmbus_device.c index 44fe4eddbb..cef51663d0 100644 --- a/hw/i2c/pmbus_device.c +++ b/hw/i2c/pmbus_device.c @@ -190,15 +190,18 @@ static void pmbus_quick_cmd(SMBusDevice *smd, uint8_t read) } } -static void pmbus_pages_alloc(PMBusDevice *pmdev) +static uint8_t pmbus_pages_num(PMBusDevice *pmdev) { + const PMBusDeviceClass *k = PMBUS_DEVICE_GET_CLASS(pmdev); + /* some PMBus devices don't use the PAGE command, so they get 1 page */ - PMBusDeviceClass *k = PMBUS_DEVICE_GET_CLASS(pmdev); - if (k->device_num_pages == 0) { - k->device_num_pages = 1; - } - pmdev->num_pages = k->device_num_pages; - pmdev->pages = g_new0(PMBusPage, k->device_num_pages); + return k->device_num_pages ? : 1; +} + +static void pmbus_pages_alloc(PMBusDevice *pmdev) +{ + pmdev->num_pages = pmbus_pages_num(pmdev); + pmdev->pages = g_new0(PMBusPage, pmdev->num_pages); } void pmbus_check_limits(PMBusDevice *pmdev) @@ -1623,7 +1626,7 @@ static int pmbus_write_data(SMBusDevice *smd, uint8_t *buf, uint8_t len) break; passthrough: - /* Unimplimented registers get passed to the device */ + /* Unimplemented registers get passed to the device */ default: if (pmdc->write_data) { ret = pmdc->write_data(pmdev, buf, len); diff --git a/hw/i2c/smbus_slave.c b/hw/i2c/smbus_slave.c index feb3ec6333..2ef2c7c5f6 100644 --- a/hw/i2c/smbus_slave.c +++ b/hw/i2c/smbus_slave.c @@ -2,7 +2,7 @@ * QEMU SMBus device emulation. * * This code is a helper for SMBus device emulation. It implements an - * I2C device inteface and runs the SMBus protocol from the device + * I2C device interface and runs the SMBus protocol from the device * point of view and maps those to simple calls to emulate. * * Copyright (c) 2007 CodeSourcery. diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index df70b4a033..34348a3324 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -22,7 +22,7 @@ #include "kvm/kvm_i386.h" #include "migration/vmstate.h" #include "hw/sysbus.h" -#include "hw/kvm/clock.h" +#include "hw/i386/kvm/clock.h" #include "hw/qdev-properties.h" #include "qapi/error.h" @@ -332,8 +332,10 @@ void kvmclock_create(bool create_always) { X86CPU *cpu = X86_CPU(first_cpu); - if (!kvm_enabled() || !kvm_has_adjust_clock()) + assert(kvm_enabled()); + if (!kvm_has_adjust_clock()) { return; + } if (create_always || cpu->env.features[FEAT_KVM] & ((1ULL << KVM_FEATURE_CLOCKSOURCE) | diff --git a/include/hw/kvm/clock.h b/hw/i386/kvm/clock.h index 7994071c4f..401c7e445b 100644 --- a/include/hw/kvm/clock.h +++ b/hw/i386/kvm/clock.h @@ -10,19 +10,9 @@ * See the COPYING file in the top-level directory. */ -#ifndef HW_KVM_CLOCK_H -#define HW_KVM_CLOCK_H - -#ifdef CONFIG_KVM +#ifndef HW_I386_KVM_CLOCK_H +#define HW_I386_KVM_CLOCK_H void kvmclock_create(bool create_always); -#else /* CONFIG_KVM */ - -static inline void kvmclock_create(bool create_always) -{ -} - -#endif /* !CONFIG_KVM */ - #endif diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index 7227a2156c..8deeb62774 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -32,7 +32,7 @@ #include "hw/loader.h" #include "hw/irq.h" -#include "hw/kvm/clock.h" +#include "hw/i386/kvm/clock.h" #include "hw/i386/microvm.h" #include "hw/i386/x86.h" #include "target/i386/cpu.h" @@ -180,7 +180,9 @@ static void microvm_devices_init(MicrovmMachineState *mms) x86ms->ioapic2 = ioapic_init_secondary(gsi_state); } - kvmclock_create(true); + if (kvm_enabled()) { + kvmclock_create(true); + } mms->virtio_irq_base = 5; mms->virtio_num_transports = 8; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index f0df12f6fa..8321f36f97 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -46,7 +46,7 @@ #include "hw/ide/piix.h" #include "hw/irq.h" #include "sysemu/kvm.h" -#include "hw/kvm/clock.h" +#include "hw/i386/kvm/clock.h" #include "hw/sysbus.h" #include "hw/i2c/smbus_eeprom.h" #include "exec/memory.h" @@ -193,7 +193,7 @@ static void pc_init1(MachineState *machine, pc_machine_init_sgx_epc(pcms); x86_cpus_init(x86ms, pcmc->default_cpu_version); - if (pcmc->kvmclock_enabled) { + if (kvm_enabled() && pcmc->kvmclock_enabled) { kvmclock_create(pcmc->kvmclock_create_always); } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 8ecc78c822..2dd1158b70 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -36,7 +36,7 @@ #include "hw/rtc/mc146818rtc.h" #include "sysemu/tcg.h" #include "sysemu/kvm.h" -#include "hw/kvm/clock.h" +#include "hw/i386/kvm/clock.h" #include "hw/pci-host/q35.h" #include "hw/pci/pcie_port.h" #include "hw/qdev-properties.h" @@ -185,7 +185,9 @@ static void pc_q35_init(MachineState *machine) pc_machine_init_sgx_epc(pcms); x86_cpus_init(x86ms, pcmc->default_cpu_version); - kvmclock_create(pcmc->kvmclock_create_always); + if (kvm_enabled()) { + kvmclock_create(pcmc->kvmclock_create_always); + } /* pci enabled */ if (pcmc->pci_enabled) { diff --git a/hw/ide/ahci.c b/hw/ide/ahci.c index 48d550f633..d0a774bc17 100644 --- a/hw/ide/ahci.c +++ b/hw/ide/ahci.c @@ -41,9 +41,10 @@ #include "trace.h" static void check_cmd(AHCIState *s, int port); -static int handle_cmd(AHCIState *s, int port, uint8_t slot); +static void handle_cmd(AHCIState *s, int port, uint8_t slot); static void ahci_reset_port(AHCIState *s, int port); -static bool ahci_write_fis_d2h(AHCIDevice *ad); +static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i); +static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot); static void ahci_init_d2h(AHCIDevice *ad); static int ahci_dma_prepare_buf(const IDEDMA *dma, int32_t limit); static bool ahci_map_clb_address(AHCIDevice *ad); @@ -328,6 +329,11 @@ static void ahci_port_write(AHCIState *s, int port, int offset, uint32_t val) ahci_check_irq(s); break; case AHCI_PORT_REG_CMD: + if ((pr->cmd & PORT_CMD_START) && !(val & PORT_CMD_START)) { + pr->scr_act = 0; + pr->cmd_issue = 0; + } + /* Block any Read-only fields from being set; * including LIST_ON and FIS_ON. * The spec requires to set ICC bits to zero after the ICC change @@ -591,9 +597,8 @@ static void check_cmd(AHCIState *s, int port) if ((pr->cmd & PORT_CMD_START) && pr->cmd_issue) { for (slot = 0; (slot < 32) && pr->cmd_issue; slot++) { - if ((pr->cmd_issue & (1U << slot)) && - !handle_cmd(s, port, slot)) { - pr->cmd_issue &= ~(1U << slot); + if (pr->cmd_issue & (1U << slot)) { + handle_cmd(s, port, slot); } } } @@ -618,7 +623,7 @@ static void ahci_init_d2h(AHCIDevice *ad) return; } - if (ahci_write_fis_d2h(ad)) { + if (ahci_write_fis_d2h(ad, true)) { ad->init_d2h_sent = true; /* We're emulating receiving the first Reg H2D Fis from the device; * Update the SIG register, but otherwise proceed as normal. */ @@ -801,8 +806,14 @@ static void ahci_write_fis_sdb(AHCIState *s, NCQTransferState *ncq_tfs) pr->scr_act &= ~ad->finished; ad->finished = 0; - /* Trigger IRQ if interrupt bit is set (which currently, it always is) */ - if (sdb_fis->flags & 0x40) { + /* + * TFES IRQ is always raised if ERR_STAT is set, regardless of I bit. + * If ERR_STAT is not set, trigger SDBS IRQ if interrupt bit is set + * (which currently, it always is). + */ + if (sdb_fis->status & ERR_STAT) { + ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_TFES); + } else if (sdb_fis->flags & 0x40) { ahci_trigger_irq(s, ad, AHCI_PORT_IRQ_BIT_SDBS); } } @@ -850,7 +861,7 @@ static void ahci_write_fis_pio(AHCIDevice *ad, uint16_t len, bool pio_fis_i) } } -static bool ahci_write_fis_d2h(AHCIDevice *ad) +static bool ahci_write_fis_d2h(AHCIDevice *ad, bool d2h_fis_i) { AHCIPortRegs *pr = &ad->port_regs; uint8_t *d2h_fis; @@ -864,7 +875,7 @@ static bool ahci_write_fis_d2h(AHCIDevice *ad) d2h_fis = &ad->res_fis[RES_FIS_RFIS]; d2h_fis[0] = SATA_FIS_TYPE_REGISTER_D2H; - d2h_fis[1] = (1 << 6); /* interrupt bit */ + d2h_fis[1] = d2h_fis_i ? (1 << 6) : 0; /* interrupt bit */ d2h_fis[2] = s->status; d2h_fis[3] = s->error; @@ -890,7 +901,10 @@ static bool ahci_write_fis_d2h(AHCIDevice *ad) ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_TFES); } - ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); + if (d2h_fis_i) { + ahci_trigger_irq(ad->hba, ad, AHCI_PORT_IRQ_BIT_DHRS); + } + return true; } @@ -998,7 +1012,6 @@ static void ncq_err(NCQTransferState *ncq_tfs) ide_state->error = ABRT_ERR; ide_state->status = READY_STAT | ERR_STAT; - ncq_tfs->drive->port_regs.scr_err |= (1 << ncq_tfs->tag); qemu_sglist_destroy(&ncq_tfs->sglist); ncq_tfs->used = 0; } @@ -1008,7 +1021,7 @@ static void ncq_finish(NCQTransferState *ncq_tfs) /* If we didn't error out, set our finished bit. Errored commands * do not get a bit set for the SDB FIS ACT register, nor do they * clear the outstanding bit in scr_act (PxSACT). */ - if (!(ncq_tfs->drive->port_regs.scr_err & (1 << ncq_tfs->tag))) { + if (ncq_tfs->used) { ncq_tfs->drive->finished |= (1 << ncq_tfs->tag); } @@ -1120,6 +1133,24 @@ static void process_ncq_command(AHCIState *s, int port, const uint8_t *cmd_fis, return; } + /* + * A NCQ command clears the bit in PxCI after the command has been QUEUED + * successfully (ERROR not set, BUSY and DRQ cleared). + * + * For NCQ commands, PxCI will always be cleared here. + * + * (Once the NCQ command is COMPLETED, the device will send a SDB FIS with + * the interrupt bit set, which will clear PxSACT and raise an interrupt.) + */ + ahci_clear_cmd_issue(ad, slot); + + /* + * In reality, for NCQ commands, PxCI is cleared after receiving a D2H FIS + * without the interrupt bit set, but since ahci_write_fis_d2h() can raise + * an IRQ on error, we need to call them in reverse order. + */ + ahci_write_fis_d2h(ad, false); + ncq_tfs->used = 1; ncq_tfs->drive = ad; ncq_tfs->slot = slot; @@ -1192,6 +1223,7 @@ static void handle_reg_h2d_fis(AHCIState *s, int port, { IDEState *ide_state = &s->dev[port].port.ifs[0]; AHCICmdHdr *cmd = get_cmd_header(s, port, slot); + AHCIDevice *ad = &s->dev[port]; uint16_t opts = le16_to_cpu(cmd->opts); if (cmd_fis[1] & 0x0F) { @@ -1268,11 +1300,19 @@ static void handle_reg_h2d_fis(AHCIState *s, int port, /* Reset transferred byte counter */ cmd->status = 0; + /* + * A non-NCQ command clears the bit in PxCI after the command has COMPLETED + * successfully (ERROR not set, BUSY and DRQ cleared). + * + * For non-NCQ commands, PxCI will always be cleared by ahci_cmd_done(). + */ + ad->busy_slot = slot; + /* We're ready to process the command in FIS byte 2. */ ide_bus_exec_cmd(&s->dev[port].port, cmd_fis[2]); } -static int handle_cmd(AHCIState *s, int port, uint8_t slot) +static void handle_cmd(AHCIState *s, int port, uint8_t slot) { IDEState *ide_state; uint64_t tbl_addr; @@ -1283,12 +1323,12 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot) if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { /* Engine currently busy, try again later */ trace_handle_cmd_busy(s, port); - return -1; + return; } if (!s->dev[port].lst) { trace_handle_cmd_nolist(s, port); - return -1; + return; } cmd = get_cmd_header(s, port, slot); /* remember current slot handle for later */ @@ -1298,7 +1338,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot) ide_state = &s->dev[port].port.ifs[0]; if (!ide_state->blk) { trace_handle_cmd_badport(s, port); - return -1; + return; } tbl_addr = le64_to_cpu(cmd->tbl_addr); @@ -1307,7 +1347,7 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot) DMA_DIRECTION_TO_DEVICE, MEMTXATTRS_UNSPECIFIED); if (!cmd_fis) { trace_handle_cmd_badfis(s, port); - return -1; + return; } else if (cmd_len != 0x80) { ahci_trigger_irq(s, &s->dev[port], AHCI_PORT_IRQ_BIT_HBFS); trace_handle_cmd_badmap(s, port, cmd_len); @@ -1331,15 +1371,6 @@ static int handle_cmd(AHCIState *s, int port, uint8_t slot) out: dma_memory_unmap(s->as, cmd_fis, cmd_len, DMA_DIRECTION_TO_DEVICE, cmd_len); - - if (s->dev[port].port.ifs[0].status & (BUSY_STAT|DRQ_STAT)) { - /* async command, complete later */ - s->dev[port].busy_slot = slot; - return -1; - } - - /* done handling the command */ - return 0; } /* Transfer PIO data between RAM and device */ @@ -1493,22 +1524,39 @@ static int ahci_dma_rw_buf(const IDEDMA *dma, bool is_write) return 1; } +static void ahci_clear_cmd_issue(AHCIDevice *ad, uint8_t slot) +{ + IDEState *ide_state = &ad->port.ifs[0]; + + if (!(ide_state->status & ERR_STAT) && + !(ide_state->status & (BUSY_STAT | DRQ_STAT))) { + ad->port_regs.cmd_issue &= ~(1 << slot); + } +} + +/* Non-NCQ command is done - This function is never called for NCQ commands. */ static void ahci_cmd_done(const IDEDMA *dma) { AHCIDevice *ad = DO_UPCAST(AHCIDevice, dma, dma); + IDEState *ide_state = &ad->port.ifs[0]; trace_ahci_cmd_done(ad->hba, ad->port_no); /* no longer busy */ if (ad->busy_slot != -1) { - ad->port_regs.cmd_issue &= ~(1 << ad->busy_slot); + ahci_clear_cmd_issue(ad, ad->busy_slot); ad->busy_slot = -1; } - /* update d2h status */ - ahci_write_fis_d2h(ad); + /* + * In reality, for non-NCQ commands, PxCI is cleared after receiving a D2H + * FIS with the interrupt bit set, but since ahci_write_fis_d2h() will raise + * an IRQ, we need to call them in reverse order. + */ + ahci_write_fis_d2h(ad, true); - if (ad->port_regs.cmd_issue && !ad->check_bh) { + if (!(ide_state->status & ERR_STAT) && + ad->port_regs.cmd_issue && !ad->check_bh) { ad->check_bh = qemu_bh_new_guarded(ahci_check_cmd_bh, ad, &ad->mem_reentrancy_guard); qemu_bh_schedule(ad->check_bh); diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h index 2480455372..c244bbd8be 100644 --- a/hw/ide/ahci_internal.h +++ b/hw/ide/ahci_internal.h @@ -61,13 +61,13 @@ enum AHCIHostReg { AHCI_HOST_REG_CTL = 1, /* GHC: global host control */ AHCI_HOST_REG_IRQ_STAT = 2, /* IS: interrupt status */ AHCI_HOST_REG_PORTS_IMPL = 3, /* PI: bitmap of implemented ports */ - AHCI_HOST_REG_VERSION = 4, /* VS: AHCI spec. version compliancy */ + AHCI_HOST_REG_VERSION = 4, /* VS: AHCI spec. version compliance */ AHCI_HOST_REG_CCC_CTL = 5, /* CCC_CTL: CCC Control */ AHCI_HOST_REG_CCC_PORTS = 6, /* CCC_PORTS: CCC Ports */ AHCI_HOST_REG_EM_LOC = 7, /* EM_LOC: Enclosure Mgmt Location */ AHCI_HOST_REG_EM_CTL = 8, /* EM_CTL: Enclosure Mgmt Control */ AHCI_HOST_REG_CAP2 = 9, /* CAP2: host capabilities, extended */ - AHCI_HOST_REG_BOHC = 10, /* BOHC: firmare/os handoff ctrl & status */ + AHCI_HOST_REG_BOHC = 10, /* BOHC: firmware/os handoff ctrl & status */ AHCI_HOST_REG__COUNT = 11 }; diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index cabe9048b1..c0bcfa4414 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -257,7 +257,7 @@ static void pci_cmd646_ide_realize(PCIDevice *dev, Error **errp) pci_conf[CNTRL] = CNTRL_EN_CH0; // enable IDE0 if (d->secondary) { - /* XXX: if not enabled, really disable the seconday IDE controller */ + /* XXX: if not enabled, really disable the secondary IDE controller */ pci_conf[CNTRL] |= CNTRL_EN_CH1; /* enable IDE1 */ } diff --git a/hw/ide/core.c b/hw/ide/core.c index de48ff9f86..b5e0dcd29b 100644 --- a/hw/ide/core.c +++ b/hw/ide/core.c @@ -533,9 +533,9 @@ BlockAIOCB *ide_issue_trim( void ide_abort_command(IDEState *s) { - ide_transfer_stop(s); s->status = READY_STAT | ERR_STAT; s->error = ABRT_ERR; + ide_transfer_stop(s); } static void ide_set_retry(IDEState *s) @@ -1698,7 +1698,7 @@ static bool cmd_set_features(IDEState *s, uint8_t cmd) put_le16(identify_data + 63, 0x07); put_le16(identify_data + 88, 0x3f); break; - case 0x02: /* sigle word dma mode*/ + case 0x02: /* single word dma mode */ put_le16(identify_data + 62, 0x07 | (1 << (val + 8))); put_le16(identify_data + 63, 0x07); put_le16(identify_data + 88, 0x3f); diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 4a34f03047..68ad30e2f5 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -28,7 +28,6 @@ #include "hw/intc/kvm_irqcount.h" #include "trace.h" #include "hw/boards.h" -#include "sysemu/hax.h" #include "sysemu/kvm.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" @@ -271,7 +270,7 @@ static void apic_common_realize(DeviceState *dev, Error **errp) /* Note: We need at least 1M to map the VAPIC option ROM */ if (!vapic && s->vapic_control & VAPIC_ENABLE_MASK && - !hax_enabled() && current_machine->ram_size >= 1024 * 1024) { + current_machine->ram_size >= 1024 * 1024) { vapic = sysbus_create_simple("kvmvapic", -1, NULL); } s->vapic = vapic; diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index e536b3ec26..9b10e90519 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -85,28 +85,6 @@ static uint8_t pnv_xive_block_id(PnvXive *xive) } /* - * Remote access to controllers. HW uses MMIOs. For now, a simple scan - * of the chips is good enough. - * - * TODO: Block scope support - */ -static PnvXive *pnv_xive_get_remote(uint8_t blk) -{ - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); - int i; - - for (i = 0; i < pnv->num_chips; i++) { - Pnv9Chip *chip9 = PNV9_CHIP(pnv->chips[i]); - PnvXive *xive = &chip9->xive; - - if (pnv_xive_block_id(xive) == blk) { - return xive; - } - } - return NULL; -} - -/* * VST accessors for SBE, EAT, ENDT, NVT * * Indirect VST tables are arrays of VSDs pointing to a page (of same @@ -209,6 +187,42 @@ static uint64_t pnv_xive_vst_addr_indirect(PnvXive *xive, uint32_t type, return pnv_xive_vst_addr_direct(xive, type, vsd, (idx % vst_per_page)); } +/* + * This is a simplified model of operation forwarding on a remote IC. + * + * A PC MMIO address is built to identify the NVT structure. The load + * on the remote IC will return the address of the structure in RAM, + * which will then be used by pnv_xive_vst_write/read to perform the + * RAM operation. + */ +static uint64_t pnv_xive_vst_addr_remote(PnvXive *xive, uint32_t type, + uint64_t vsd, uint8_t blk, + uint32_t idx) +{ + const XiveVstInfo *info = &vst_infos[type]; + uint64_t remote_addr = vsd & VSD_ADDRESS_MASK; + uint64_t vst_addr; + MemTxResult result; + + if (type != VST_TSEL_VPDT) { + xive_error(xive, "VST: invalid access on remote VST %s %x/%x !?", + info->name, blk, idx); + return 0; + } + + remote_addr |= idx << xive->pc_shift; + + vst_addr = address_space_ldq_be(&address_space_memory, remote_addr, + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + xive_error(xive, "VST: read failed at @0x%" HWADDR_PRIx + " for NVT %x/%x\n", remote_addr, blk, idx); + return 0; + } + + return vst_addr; +} + static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk, uint32_t idx) { @@ -225,9 +239,7 @@ static uint64_t pnv_xive_vst_addr(PnvXive *xive, uint32_t type, uint8_t blk, /* Remote VST access */ if (GETFIELD(VSD_MODE, vsd) == VSD_MODE_FORWARD) { - xive = pnv_xive_get_remote(blk); - - return xive ? pnv_xive_vst_addr(xive, type, blk, idx) : 0; + return pnv_xive_vst_addr_remote(xive, type, vsd, blk, idx); } if (VSD_INDIRECT & vsd) { @@ -242,12 +254,20 @@ static int pnv_xive_vst_read(PnvXive *xive, uint32_t type, uint8_t blk, { const XiveVstInfo *info = &vst_infos[type]; uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx); + MemTxResult result; if (!addr) { return -1; } - cpu_physical_memory_read(addr, data, info->size); + result = address_space_read(&address_space_memory, addr, + MEMTXATTRS_UNSPECIFIED, data, + info->size); + if (result != MEMTX_OK) { + xive_error(xive, "VST: read failed at @0x%" HWADDR_PRIx + " for VST %s %x/%x\n", addr, info->name, blk, idx); + return -1; + } return 0; } @@ -258,16 +278,27 @@ static int pnv_xive_vst_write(PnvXive *xive, uint32_t type, uint8_t blk, { const XiveVstInfo *info = &vst_infos[type]; uint64_t addr = pnv_xive_vst_addr(xive, type, blk, idx); + MemTxResult result; if (!addr) { return -1; } if (word_number == XIVE_VST_WORD_ALL) { - cpu_physical_memory_write(addr, data, info->size); + result = address_space_write(&address_space_memory, addr, + MEMTXATTRS_UNSPECIFIED, data, + info->size); } else { - cpu_physical_memory_write(addr + word_number * 4, - data + word_number * 4, 4); + result = address_space_write(&address_space_memory, + addr + word_number * 4, + MEMTXATTRS_UNSPECIFIED, + data + word_number * 4, 4); + } + + if (result != MEMTX_OK) { + xive_error(xive, "VST: write failed at @0x%" HWADDR_PRIx + "for VST %s %x/%x\n", addr, info->name, blk, idx); + return -1; } return 0; } @@ -275,12 +306,26 @@ static int pnv_xive_vst_write(PnvXive *xive, uint32_t type, uint8_t blk, static int pnv_xive_get_end(XiveRouter *xrtr, uint8_t blk, uint32_t idx, XiveEND *end) { + PnvXive *xive = PNV_XIVE(xrtr); + + if (pnv_xive_block_id(xive) != blk) { + xive_error(xive, "VST: END %x/%x is remote !?", blk, idx); + return -1; + } + return pnv_xive_vst_read(PNV_XIVE(xrtr), VST_TSEL_EQDT, blk, idx, end); } static int pnv_xive_write_end(XiveRouter *xrtr, uint8_t blk, uint32_t idx, XiveEND *end, uint8_t word_number) { + PnvXive *xive = PNV_XIVE(xrtr); + + if (pnv_xive_block_id(xive) != blk) { + xive_error(xive, "VST: END %x/%x is remote !?", blk, idx); + return -1; + } + return pnv_xive_vst_write(PNV_XIVE(xrtr), VST_TSEL_EQDT, blk, idx, end, word_number); } @@ -1349,6 +1394,50 @@ static const MemoryRegionOps pnv_xive_ic_reg_ops = { #define PNV_XIVE_SYNC_PUSH 0xf00 /* Sync push context */ #define PNV_XIVE_SYNC_VPC 0xf80 /* Sync remove VPC store */ +static void pnv_xive_end_notify(XiveRouter *xrtr, XiveEAS *eas) +{ + PnvXive *xive = PNV_XIVE(xrtr); + uint8_t end_blk = xive_get_field64(EAS_END_BLOCK, eas->w); + uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); + uint32_t end_data = xive_get_field64(EAS_END_DATA, eas->w); + uint64_t end_vsd = xive->vsds[VST_TSEL_EQDT][end_blk]; + + switch (GETFIELD(VSD_MODE, end_vsd)) { + case VSD_MODE_EXCLUSIVE: + /* Perform the END notification on the local IC. */ + xive_router_end_notify(xrtr, eas); + break; + + case VSD_MODE_FORWARD: { + MemTxResult result; + uint64_t notif_port = end_vsd & VSD_ADDRESS_MASK; + uint64_t data = XIVE_TRIGGER_END | XIVE_TRIGGER_PQ | + be64_to_cpu(eas->w); + + /* Forward the store on the remote IC notify page. */ + address_space_stq_be(&address_space_memory, notif_port, data, + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + xive_error(xive, "IC: Forward notif END %x/%x [%x] failed @%" + HWADDR_PRIx, end_blk, end_idx, end_data, notif_port); + return; + } + break; + } + + case VSD_MODE_INVALID: + default: + /* Set FIR */ + xive_error(xive, "IC: Invalid END VSD for block %x", end_blk); + return; + } +} + +/* + * The notify page can either be used to receive trigger events from + * the HW controllers (PHB, PSI) or to reroute interrupts between + * Interrupt controllers. + */ static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t val) { uint8_t blk; @@ -1357,8 +1446,8 @@ static void pnv_xive_ic_hw_trigger(PnvXive *xive, hwaddr addr, uint64_t val) trace_pnv_xive_ic_hw_trigger(addr, val); if (val & XIVE_TRIGGER_END) { - xive_error(xive, "IC: END trigger at @0x%"HWADDR_PRIx" data 0x%"PRIx64, - addr, val); + val = cpu_to_be64(val); + pnv_xive_end_notify(XIVE_ROUTER(xive), (XiveEAS *) &val); return; } @@ -1703,16 +1792,20 @@ static const MemoryRegionOps pnv_xive_vc_ops = { }; /* - * Presenter Controller MMIO region. The Virtualization Controller - * updates the IPB in the NVT table when required. Not modeled. + * Presenter Controller MMIO region. Points to the NVT sets. + * + * HW implements all possible mem ops to the underlying NVT structure + * but QEMU does not need to be so precise. The model implementation + * simply returns the RAM address of the NVT structure which is then + * used by pnv_xive_vst_write/read to perform the RAM operation. */ -static uint64_t pnv_xive_pc_read(void *opaque, hwaddr addr, - unsigned size) +static uint64_t pnv_xive_pc_read(void *opaque, hwaddr offset, unsigned size) { PnvXive *xive = PNV_XIVE(opaque); + uint32_t nvt_idx = offset >> xive->pc_shift; + uint8_t blk = pnv_xive_block_id(xive); /* TODO: VDT -> block xlate */ - xive_error(xive, "PC: invalid read @%"HWADDR_PRIx, addr); - return -1; + return pnv_xive_vst_addr(xive, VST_TSEL_VPDT, blk, nvt_idx); } static void pnv_xive_pc_write(void *opaque, hwaddr addr, @@ -1898,6 +1991,7 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp) memory_region_init_io(&xive->ic_notify_mmio, OBJECT(dev), &pnv_xive_ic_notify_ops, xive, "xive-ic-notify", 1 << xive->ic_shift); + xive->ic_notify_mmio.disable_reentrancy_guard = true; /* The Pervasive LSI trigger and EOI pages (not modeled) */ memory_region_init_io(&xive->ic_lsi_mmio, OBJECT(dev), &pnv_xive_ic_lsi_ops, @@ -1933,6 +2027,7 @@ static void pnv_xive_realize(DeviceState *dev, Error **errp) /* Presenter Controller MMIO region (not modeled) */ memory_region_init_io(&xive->pc_mmio, OBJECT(xive), &pnv_xive_pc_ops, xive, "xive-pc", PNV9_XIVE_PC_SIZE); + xive->pc_mmio.disable_reentrancy_guard = true; /* Thread Interrupt Management Area (Direct) */ memory_region_init_io(&xive->tm_mmio, OBJECT(xive), &pnv_xive_tm_ops, @@ -1998,6 +2093,7 @@ static void pnv_xive_class_init(ObjectClass *klass, void *data) xrc->get_nvt = pnv_xive_get_nvt; xrc->write_nvt = pnv_xive_write_nvt; xrc->get_block_id = pnv_xive_get_block_id; + xrc->end_notify = pnv_xive_end_notify; xnc->notify = pnv_xive_notify; xpc->match_nvt = pnv_xive_match_nvt; diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index bbb44a533c..4b8d0a5d81 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -240,12 +240,20 @@ static int pnv_xive2_vst_read(PnvXive2 *xive, uint32_t type, uint8_t blk, { const XiveVstInfo *info = &vst_infos[type]; uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); + MemTxResult result; if (!addr) { return -1; } - cpu_physical_memory_read(addr, data, info->size); + result = address_space_read(&address_space_memory, addr, + MEMTXATTRS_UNSPECIFIED, data, + info->size); + if (result != MEMTX_OK) { + xive2_error(xive, "VST: read failed at @0x%" HWADDR_PRIx + " for VST %s %x/%x\n", addr, info->name, blk, idx); + return -1; + } return 0; } @@ -256,16 +264,27 @@ static int pnv_xive2_vst_write(PnvXive2 *xive, uint32_t type, uint8_t blk, { const XiveVstInfo *info = &vst_infos[type]; uint64_t addr = pnv_xive2_vst_addr(xive, type, blk, idx); + MemTxResult result; if (!addr) { return -1; } if (word_number == XIVE_VST_WORD_ALL) { - cpu_physical_memory_write(addr, data, info->size); + result = address_space_write(&address_space_memory, addr, + MEMTXATTRS_UNSPECIFIED, data, + info->size); } else { - cpu_physical_memory_write(addr + word_number * 4, - data + word_number * 4, 4); + result = address_space_write(&address_space_memory, + addr + word_number * 4, + MEMTXATTRS_UNSPECIFIED, + data + word_number * 4, 4); + } + + if (result != MEMTX_OK) { + xive2_error(xive, "VST: write failed at @0x%" HWADDR_PRIx + "for VST %s %x/%x\n", addr, info->name, blk, idx); + return -1; } return 0; } diff --git a/hw/intc/pnv_xive_regs.h b/hw/intc/pnv_xive_regs.h index c78f030c02..793847638b 100644 --- a/hw/intc/pnv_xive_regs.h +++ b/hw/intc/pnv_xive_regs.h @@ -228,6 +228,7 @@ * VSD and is only meant to be used in indirect mode ! */ #define VSD_MODE PPC_BITMASK(0, 1) +#define VSD_MODE_INVALID 0 #define VSD_MODE_SHARED 1 #define VSD_MODE_EXCLUSIVE 2 #define VSD_MODE_FORWARD 3 diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 56670b2cac..df3ee0496f 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -1518,6 +1518,13 @@ static void xive_router_realize(DeviceState *dev, Error **errp) assert(xrtr->xfb); } +static void xive_router_end_notify_handler(XiveRouter *xrtr, XiveEAS *eas) +{ + XiveRouterClass *xrc = XIVE_ROUTER_GET_CLASS(xrtr); + + return xrc->end_notify(xrtr, eas); +} + /* * Encode the HW CAM line in the block group mode format : * @@ -1664,8 +1671,7 @@ static bool xive_router_end_es_notify(XiveRouter *xrtr, uint8_t end_blk, * another chip. We don't model the PowerBus but the END trigger * message has the same parameters than in the function below. */ -static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, - uint32_t end_idx, uint32_t end_data) +void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *eas) { XiveEND end; uint8_t priority; @@ -1675,6 +1681,10 @@ static void xive_router_end_notify(XiveRouter *xrtr, uint8_t end_blk, XiveNVT nvt; bool found; + uint8_t end_blk = xive_get_field64(EAS_END_BLOCK, eas->w); + uint32_t end_idx = xive_get_field64(EAS_END_INDEX, eas->w); + uint32_t end_data = xive_get_field64(EAS_END_DATA, eas->w); + /* END cache lookup */ if (xive_router_get_end(xrtr, end_blk, end_idx, &end)) { qemu_log_mask(LOG_GUEST_ERROR, "XIVE: No END %x/%x\n", end_blk, @@ -1817,10 +1827,7 @@ do_escalation: /* * The END trigger becomes an Escalation trigger */ - xive_router_end_notify(xrtr, - xive_get_field32(END_W4_ESC_END_BLOCK, end.w4), - xive_get_field32(END_W4_ESC_END_INDEX, end.w4), - xive_get_field32(END_W5_ESC_END_DATA, end.w5)); + xive_router_end_notify_handler(xrtr, (XiveEAS *) &end.w4); } void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) @@ -1871,10 +1878,7 @@ void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) /* * The event trigger becomes an END trigger */ - xive_router_end_notify(xrtr, - xive_get_field64(EAS_END_BLOCK, eas.w), - xive_get_field64(EAS_END_INDEX, eas.w), - xive_get_field64(EAS_END_DATA, eas.w)); + xive_router_end_notify_handler(xrtr, &eas); } static Property xive_router_properties[] = { @@ -1887,12 +1891,16 @@ static void xive_router_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); XiveNotifierClass *xnc = XIVE_NOTIFIER_CLASS(klass); + XiveRouterClass *xrc = XIVE_ROUTER_CLASS(klass); dc->desc = "XIVE Router Engine"; device_class_set_props(dc, xive_router_properties); /* Parent is SysBusDeviceClass. No need to call its realize hook */ dc->realize = xive_router_realize; xnc->notify = xive_router_notify; + + /* By default, the router handles END triggers locally */ + xrc->end_notify = xive_router_end_notify; } static const TypeInfo xive_router_info = { diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index babb053035..ea0fb68cf0 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -192,6 +192,7 @@ petalogix_ml605_init(MachineState *machine) blk_by_legacy_dinfo(dinfo), &error_fatal); } + qdev_prop_set_uint8(dev, "cs", i); qdev_realize_and_unref(dev, BUS(spi), &error_fatal); cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); diff --git a/hw/mips/malta.c b/hw/mips/malta.c index f9618fa5f5..16e9c4773f 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -627,7 +627,7 @@ static void bl_setup_gt64120_jump_kernel(void **p, uint64_t run_addr, 10, 10, 11, 11 /* PIIX IRQRC[A:D] */ }; - /* Bus endianess is always reversed */ + /* Bus endianness is always reversed */ #if TARGET_BIG_ENDIAN #define cpu_to_gt32(x) (x) #else diff --git a/hw/net/i82596.c b/hw/net/i82596.c index ab26f8bea1..6defa9d3a1 100644 --- a/hw/net/i82596.c +++ b/hw/net/i82596.c @@ -15,6 +15,7 @@ #include "hw/irq.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" +#include "exec/address-spaces.h" #include "qemu/module.h" #include "trace.h" #include "i82596.h" diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 67793a86f1..d5b6820d1d 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -712,7 +712,7 @@ static int ppce500_prep_device_tree(PPCE500MachineState *machine, p->kernel_base = kernel_base; p->kernel_size = kernel_size; - qemu_register_reset(ppce500_reset_device_tree, p); + qemu_register_reset_nosnapshotload(ppce500_reset_device_tree, p); p->notifier.notify = ppce500_init_notify; qemu_add_machine_init_done_notifier(&p->notifier); diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 510ff0eaaf..9acc7adfc9 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -81,6 +81,7 @@ static void ppc_heathrow_reset(void *opaque) { PowerPCCPU *cpu = opaque; + cpu_ppc_tb_reset(&cpu->env); cpu_reset(CPU(cpu)); } diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c index 075367d94d..bd397cf2b5 100644 --- a/hw/ppc/pegasos2.c +++ b/hw/ppc/pegasos2.c @@ -99,6 +99,7 @@ static void pegasos2_cpu_reset(void *opaque) cpu->env.gpr[1] = 2 * VOF_STACK_SIZE - 0x20; cpu->env.nip = 0x100; } + cpu_ppc_tb_reset(&cpu->env); } static void pegasos2_pci_irq(void *opaque, int n, int level) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 9b39d527de..8c7afe037f 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -61,6 +61,8 @@ static void pnv_core_cpu_reset(PnvCore *pc, PowerPCCPU *cpu) hreg_compute_hflags(env); ppc_maybe_interrupt(env); + cpu_ppc_tb_reset(env); + pcc->intc_reset(pc->chip, cpu); } diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index 0e0a3d93c3..aeb116d919 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -32,6 +32,7 @@ #include "qemu/main-loop.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" +#include "sysemu/replay.h" #include "sysemu/runstate.h" #include "kvm_ppc.h" #include "migration/vmstate.h" @@ -58,7 +59,9 @@ void ppc_set_irq(PowerPCCPU *cpu, int irq, int level) if (old_pending != env->pending_interrupts) { ppc_maybe_interrupt(env); - kvmppc_set_interrupt(cpu, irq, level); + if (kvm_enabled()) { + kvmppc_set_interrupt(cpu, irq, level); + } } trace_ppc_irq_set_exit(env, irq, level, env->pending_interrupts, @@ -482,10 +485,32 @@ void ppce500_set_mpic_proxy(bool enabled) /*****************************************************************************/ /* PowerPC time base and decrementer emulation */ +/* + * Conversion between QEMU_CLOCK_VIRTUAL ns and timebase (TB) ticks: + * TB ticks are arrived at by multiplying tb_freq then dividing by + * ns per second, and rounding down. TB ticks drive all clocks and + * timers in the target machine. + * + * Converting TB intervals to ns for the purpose of setting a + * QEMU_CLOCK_VIRTUAL timer should go the other way, but rounding + * up. Rounding down could cause the timer to fire before the TB + * value has been reached. + */ +static uint64_t ns_to_tb(uint32_t freq, int64_t clock) +{ + return muldiv64(clock, freq, NANOSECONDS_PER_SECOND); +} + +/* virtual clock in TB ticks, not adjusted by TB offset */ +static int64_t tb_to_ns_round_up(uint32_t freq, uint64_t tb) +{ + return muldiv64_round_up(tb, NANOSECONDS_PER_SECOND, freq); +} + uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset) { /* TB time in tb periods */ - return muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND) + tb_offset; + return ns_to_tb(tb_env->tb_freq, vmclk) + tb_offset; } uint64_t cpu_ppc_load_tbl (CPUPPCState *env) @@ -497,7 +522,8 @@ uint64_t cpu_ppc_load_tbl (CPUPPCState *env) return env->spr[SPR_TBL]; } - tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); + tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->tb_offset); trace_ppc_tb_load(tb); return tb; @@ -508,7 +534,8 @@ static inline uint32_t _cpu_ppc_load_tbu(CPUPPCState *env) ppc_tb_t *tb_env = env->tb_env; uint64_t tb; - tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->tb_offset); + tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->tb_offset); trace_ppc_tb_load(tb); return tb >> 32; @@ -526,8 +553,7 @@ uint32_t cpu_ppc_load_tbu (CPUPPCState *env) static inline void cpu_ppc_store_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t *tb_offsetp, uint64_t value) { - *tb_offsetp = value - - muldiv64(vmclk, tb_env->tb_freq, NANOSECONDS_PER_SECOND); + *tb_offsetp = value - ns_to_tb(tb_env->tb_freq, vmclk); trace_ppc_tb_store(value, *tb_offsetp); } @@ -565,7 +591,8 @@ uint64_t cpu_ppc_load_atbl (CPUPPCState *env) ppc_tb_t *tb_env = env->tb_env; uint64_t tb; - tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); + tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->atb_offset); trace_ppc_tb_load(tb); return tb; @@ -576,7 +603,8 @@ uint32_t cpu_ppc_load_atbu (CPUPPCState *env) ppc_tb_t *tb_env = env->tb_env; uint64_t tb; - tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), tb_env->atb_offset); + tb = cpu_ppc_get_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), + tb_env->atb_offset); trace_ppc_tb_load(tb); return tb >> 32; @@ -683,64 +711,77 @@ bool ppc_decr_clear_on_delivery(CPUPPCState *env) return ((tb_env->flags & flags) == PPC_DECR_UNDERFLOW_TRIGGERED); } -static inline int64_t _cpu_ppc_load_decr(CPUPPCState *env, uint64_t next) +static inline int64_t __cpu_ppc_load_decr(CPUPPCState *env, int64_t now, + uint64_t next) { ppc_tb_t *tb_env = env->tb_env; - int64_t decr, diff; + uint64_t n; + int64_t decr; - diff = next - qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - if (diff >= 0) { - decr = muldiv64(diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); - } else if (tb_env->flags & PPC_TIMER_BOOKE) { + n = ns_to_tb(tb_env->decr_freq, now); + if (next > n && tb_env->flags & PPC_TIMER_BOOKE) { decr = 0; - } else { - decr = -muldiv64(-diff, tb_env->decr_freq, NANOSECONDS_PER_SECOND); + } else { + decr = next - n; } + trace_ppc_decr_load(decr); return decr; } -target_ulong cpu_ppc_load_decr(CPUPPCState *env) +static target_ulong _cpu_ppc_load_decr(CPUPPCState *env, int64_t now) { ppc_tb_t *tb_env = env->tb_env; uint64_t decr; - if (kvm_enabled()) { - return env->spr[SPR_DECR]; - } - - decr = _cpu_ppc_load_decr(env, tb_env->decr_next); + decr = __cpu_ppc_load_decr(env, now, tb_env->decr_next); /* * If large decrementer is enabled then the decrementer is signed extened * to 64 bits, otherwise it is a 32 bit value. */ if (env->spr[SPR_LPCR] & LPCR_LD) { - return decr; + PowerPCCPU *cpu = env_archcpu(env); + PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + return sextract64(decr, 0, pcc->lrg_decr_bits); } return (uint32_t) decr; } -target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) +target_ulong cpu_ppc_load_decr(CPUPPCState *env) +{ + if (kvm_enabled()) { + return env->spr[SPR_DECR]; + } else { + return _cpu_ppc_load_decr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); + } +} + +static target_ulong _cpu_ppc_load_hdecr(CPUPPCState *env, int64_t now) { PowerPCCPU *cpu = env_archcpu(env); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); ppc_tb_t *tb_env = env->tb_env; uint64_t hdecr; - hdecr = _cpu_ppc_load_decr(env, tb_env->hdecr_next); + hdecr = __cpu_ppc_load_decr(env, now, tb_env->hdecr_next); /* * If we have a large decrementer (POWER9 or later) then hdecr is sign * extended to 64 bits, otherwise it is 32 bits. */ if (pcc->lrg_decr_bits > 32) { - return hdecr; + return sextract64(hdecr, 0, pcc->lrg_decr_bits); } return (uint32_t) hdecr; } +target_ulong cpu_ppc_load_hdecr(CPUPPCState *env) +{ + return _cpu_ppc_load_hdecr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL)); +} + uint64_t cpu_ppc_load_purr (CPUPPCState *env) { ppc_tb_t *tb_env = env->tb_env; @@ -785,7 +826,7 @@ static inline void cpu_ppc_hdecr_lower(PowerPCCPU *cpu) ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); } -static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, +static void __cpu_ppc_store_decr(PowerPCCPU *cpu, int64_t now, uint64_t *nextp, QEMUTimer *timer, void (*raise_excp)(void *), void (*lower_excp)(PowerPCCPU *), @@ -794,7 +835,7 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, { CPUPPCState *env = &cpu->env; ppc_tb_t *tb_env = env->tb_env; - uint64_t now, next; + uint64_t next; int64_t signed_value; int64_t signed_decr; @@ -806,10 +847,14 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, trace_ppc_decr_store(nr_bits, decr, value); - if (kvm_enabled()) { - /* KVM handles decrementer exceptions, we don't need our own timer */ - return; - } + /* + * Calculate the next decrementer event and set a timer. + * decr_next is in timebase units to keep rounding simple. Note it is + * not adjusted by tb_offset because if TB changes via tb_offset changing, + * decrementer does not change, so not directly comparable with TB. + */ + next = ns_to_tb(tb_env->decr_freq, now) + value; + *nextp = next; /* nextp is in timebase units */ /* * Going from 1 -> 0 or 0 -> -1 is the event to generate a DEC interrupt. @@ -832,21 +877,17 @@ static void __cpu_ppc_store_decr(PowerPCCPU *cpu, uint64_t *nextp, (*lower_excp)(cpu); } - /* Calculate the next timer event */ - now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - next = now + muldiv64(value, NANOSECONDS_PER_SECOND, tb_env->decr_freq); - *nextp = next; - /* Adjust timer */ - timer_mod(timer, next); + timer_mod(timer, tb_to_ns_round_up(tb_env->decr_freq, next)); } -static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, target_ulong decr, - target_ulong value, int nr_bits) +static inline void _cpu_ppc_store_decr(PowerPCCPU *cpu, int64_t now, + target_ulong decr, target_ulong value, + int nr_bits) { ppc_tb_t *tb_env = cpu->env.tb_env; - __cpu_ppc_store_decr(cpu, &tb_env->decr_next, tb_env->decr_timer, + __cpu_ppc_store_decr(cpu, now, &tb_env->decr_next, tb_env->decr_timer, tb_env->decr_timer->cb, &cpu_ppc_decr_lower, tb_env->flags, decr, value, nr_bits); } @@ -855,13 +896,22 @@ void cpu_ppc_store_decr(CPUPPCState *env, target_ulong value) { PowerPCCPU *cpu = env_archcpu(env); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + int64_t now; + target_ulong decr; int nr_bits = 32; + if (kvm_enabled()) { + /* KVM handles decrementer exceptions, we don't need our own timer */ + return; + } + if (env->spr[SPR_LPCR] & LPCR_LD) { nr_bits = pcc->lrg_decr_bits; } - _cpu_ppc_store_decr(cpu, cpu_ppc_load_decr(env), value, nr_bits); + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + decr = _cpu_ppc_load_decr(env, now); + _cpu_ppc_store_decr(cpu, now, decr, value, nr_bits); } static void cpu_ppc_decr_cb(void *opaque) @@ -871,14 +921,15 @@ static void cpu_ppc_decr_cb(void *opaque) cpu_ppc_decr_excp(cpu); } -static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, target_ulong hdecr, - target_ulong value, int nr_bits) +static inline void _cpu_ppc_store_hdecr(PowerPCCPU *cpu, int64_t now, + target_ulong hdecr, target_ulong value, + int nr_bits) { ppc_tb_t *tb_env = cpu->env.tb_env; if (tb_env->hdecr_timer != NULL) { /* HDECR (Book3S 64bit) is edge-based, not level like DECR */ - __cpu_ppc_store_decr(cpu, &tb_env->hdecr_next, tb_env->hdecr_timer, + __cpu_ppc_store_decr(cpu, now, &tb_env->hdecr_next, tb_env->hdecr_timer, tb_env->hdecr_timer->cb, &cpu_ppc_hdecr_lower, PPC_DECR_UNDERFLOW_TRIGGERED, hdecr, value, nr_bits); @@ -889,9 +940,12 @@ void cpu_ppc_store_hdecr(CPUPPCState *env, target_ulong value) { PowerPCCPU *cpu = env_archcpu(env); PowerPCCPUClass *pcc = POWERPC_CPU_GET_CLASS(cpu); + int64_t now; + target_ulong hdecr; - _cpu_ppc_store_hdecr(cpu, cpu_ppc_load_hdecr(env), value, - pcc->lrg_decr_bits); + now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); + hdecr = _cpu_ppc_load_hdecr(env, now); + _cpu_ppc_store_hdecr(cpu, now, hdecr, value, pcc->lrg_decr_bits); } static void cpu_ppc_hdecr_cb(void *opaque) @@ -901,29 +955,16 @@ static void cpu_ppc_hdecr_cb(void *opaque) cpu_ppc_hdecr_excp(cpu); } -void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) +static void _cpu_ppc_store_purr(CPUPPCState *env, int64_t now, uint64_t value) { ppc_tb_t *tb_env = env->tb_env; - cpu_ppc_store_tb(tb_env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), - &tb_env->purr_offset, value); + cpu_ppc_store_tb(tb_env, now, &tb_env->purr_offset, value); } -static void cpu_ppc_set_tb_clk (void *opaque, uint32_t freq) +void cpu_ppc_store_purr(CPUPPCState *env, uint64_t value) { - CPUPPCState *env = opaque; - PowerPCCPU *cpu = env_archcpu(env); - ppc_tb_t *tb_env = env->tb_env; - - tb_env->tb_freq = freq; - tb_env->decr_freq = freq; - /* There is a bug in Linux 2.4 kernels: - * if a decrementer exception is pending when it enables msr_ee at startup, - * it's not ready to handle it... - */ - _cpu_ppc_store_decr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); - _cpu_ppc_store_hdecr(cpu, 0xFFFFFFFF, 0xFFFFFFFF, 32); - cpu_ppc_store_purr(env, 0x0000000000000000ULL); + _cpu_ppc_store_purr(env, qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), value); } static void timebase_save(PPCTimebase *tb) @@ -936,8 +977,14 @@ static void timebase_save(PPCTimebase *tb) return; } - /* not used anymore, we keep it for compatibility */ - tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); + if (replay_mode == REPLAY_MODE_NONE) { + /* not used anymore, we keep it for compatibility */ + tb->time_of_the_day_ns = qemu_clock_get_ns(QEMU_CLOCK_HOST); + } else { + /* simpler for record-replay to avoid this event, compat not needed */ + tb->time_of_the_day_ns = 0; + } + /* * tb_offset is only expected to be changed by QEMU so * there is no need to update it from KVM here @@ -1027,7 +1074,7 @@ const VMStateDescription vmstate_ppc_timebase = { }; /* Set up (once) timebase frequency (in Hz) */ -clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) +void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq) { PowerPCCPU *cpu = env_archcpu(env); ppc_tb_t *tb_env; @@ -1040,16 +1087,41 @@ clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq) tb_env->flags |= PPC_DECR_UNDERFLOW_LEVEL; } /* Create new timer */ - tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_decr_cb, cpu); + tb_env->decr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + &cpu_ppc_decr_cb, cpu); if (env->has_hv_mode && !cpu->vhyp) { - tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, &cpu_ppc_hdecr_cb, - cpu); + tb_env->hdecr_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, + &cpu_ppc_hdecr_cb, cpu); } else { tb_env->hdecr_timer = NULL; } - cpu_ppc_set_tb_clk(env, freq); - return &cpu_ppc_set_tb_clk; + tb_env->tb_freq = freq; + tb_env->decr_freq = freq; +} + +void cpu_ppc_tb_reset(CPUPPCState *env) +{ + PowerPCCPU *cpu = env_archcpu(env); + ppc_tb_t *tb_env = env->tb_env; + + timer_del(tb_env->decr_timer); + ppc_set_irq(cpu, PPC_INTERRUPT_DECR, 0); + tb_env->decr_next = 0; + if (tb_env->hdecr_timer != NULL) { + timer_del(tb_env->hdecr_timer); + ppc_set_irq(cpu, PPC_INTERRUPT_HDECR, 0); + tb_env->hdecr_next = 0; + } + + /* + * There is a bug in Linux 2.4 kernels: + * if a decrementer exception is pending when it enables msr_ee at startup, + * it's not ready to handle it... + */ + cpu_ppc_store_decr(env, -1); + cpu_ppc_store_hdecr(env, -1); + cpu_ppc_store_purr(env, 0x0000000000000000ULL); } void cpu_ppc_tb_free(CPUPPCState *env) @@ -1125,9 +1197,7 @@ static void cpu_4xx_fit_cb (void *opaque) /* Cannot occur, but makes gcc happy */ return; } - next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->tb_freq); - if (next == now) - next++; + next = now + tb_to_ns_round_up(tb_env->tb_freq, next); timer_mod(ppc40x_timer->fit_timer, next); env->spr[SPR_40x_TSR] |= 1 << 26; if ((env->spr[SPR_40x_TCR] >> 23) & 0x1) { @@ -1153,14 +1223,15 @@ static void start_stop_pit (CPUPPCState *env, ppc_tb_t *tb_env, int is_excp) } else { trace_ppc4xx_pit_start(ppc40x_timer->pit_reload); now = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL); - next = now + muldiv64(ppc40x_timer->pit_reload, - NANOSECONDS_PER_SECOND, tb_env->decr_freq); - if (is_excp) - next += tb_env->decr_next - now; - if (next == now) - next++; + + if (is_excp) { + tb_env->decr_next += ppc40x_timer->pit_reload; + } else { + tb_env->decr_next = ns_to_tb(tb_env->decr_freq, now) + + ppc40x_timer->pit_reload; + } + next = tb_to_ns_round_up(tb_env->decr_freq, tb_env->decr_next); timer_mod(tb_env->decr_timer, next); - tb_env->decr_next = next; } } @@ -1213,9 +1284,7 @@ static void cpu_4xx_wdt_cb (void *opaque) /* Cannot occur, but makes gcc happy */ return; } - next = now + muldiv64(next, NANOSECONDS_PER_SECOND, tb_env->decr_freq); - if (next == now) - next++; + next = now + tb_to_ns_round_up(tb_env->decr_freq, next); trace_ppc4xx_wdt(env->spr[SPR_40x_TCR], env->spr[SPR_40x_TSR]); switch ((env->spr[SPR_40x_TSR] >> 30) & 0x3) { case 0x0: @@ -1465,5 +1534,7 @@ void ppc_irq_reset(PowerPCCPU *cpu) CPUPPCState *env = &cpu->env; env->irq_input_state = 0; - kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0); + if (kvm_enabled()) { + kvmppc_set_interrupt(cpu, PPC_INTERRUPT_EXT, 0); + } } diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index d9231c7317..f6fd35fcb9 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -67,6 +67,7 @@ static void ppc_prep_reset(void *opaque) PowerPCCPU *cpu = opaque; cpu_reset(CPU(cpu)); + cpu_ppc_tb_reset(&cpu->env); } diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 07e91e3800..f7cc6a890f 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -1022,7 +1022,6 @@ static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) { MachineState *machine = MACHINE(spapr); SpaprMachineClass *smc = SPAPR_MACHINE_GET_CLASS(machine); - uint8_t rng_seed[32]; int chosen; _FDT(chosen = fdt_add_subnode(fdt, 0, "chosen")); @@ -1100,8 +1099,7 @@ static void spapr_dt_chosen(SpaprMachineState *spapr, void *fdt, bool reset) spapr_dt_ov5_platform_support(spapr, fdt, chosen); } - qemu_guest_getrandom_nofail(rng_seed, sizeof(rng_seed)); - _FDT(fdt_setprop(fdt, chosen, "rng-seed", rng_seed, sizeof(rng_seed))); + _FDT(fdt_setprop(fdt, chosen, "rng-seed", spapr->fdt_rng_seed, 32)); _FDT(spapr_dt_ovec(fdt, chosen, spapr->ov5_cas, "ibm,architecture-vec-5")); } @@ -1322,6 +1320,22 @@ void spapr_set_all_lpcrs(target_ulong value, target_ulong mask) } } +/* May be used when the machine is not running */ +void spapr_init_all_lpcrs(target_ulong value, target_ulong mask) +{ + CPUState *cs; + CPU_FOREACH(cs) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + target_ulong lpcr; + + lpcr = env->spr[SPR_LPCR]; + lpcr &= ~(LPCR_HR | LPCR_UPRT); + ppc_store_lpcr(cpu, lpcr); + } +} + + static bool spapr_get_pate(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu, target_ulong lpid, ppc_v3_pate_t *entry) { @@ -1583,7 +1597,7 @@ int spapr_reallocate_hpt(SpaprMachineState *spapr, int shift, Error **errp) } /* We're setting up a hash table, so that means we're not radix */ spapr->patb_entry = 0; - spapr_set_all_lpcrs(0, LPCR_HR | LPCR_UPRT); + spapr_init_all_lpcrs(0, LPCR_HR | LPCR_UPRT); return 0; } @@ -1638,6 +1652,14 @@ static void spapr_machine_reset(MachineState *machine, ShutdownCause reason) void *fdt; int rc; + if (reason != SHUTDOWN_CAUSE_SNAPSHOT_LOAD) { + /* + * Record-replay snapshot load must not consume random, this was + * already replayed from initial machine reset. + */ + qemu_guest_getrandom_nofail(spapr->fdt_rng_seed, 32); + } + pef_kvm_reset(machine->cgs, &error_fatal); spapr_caps_apply(spapr); @@ -1661,7 +1683,7 @@ static void spapr_machine_reset(MachineState *machine, ShutdownCause reason) spapr_ovec_cleanup(spapr->ov5_cas); spapr->ov5_cas = spapr_ovec_new(); - ppc_set_compat_all(spapr->max_compat_pvr, &error_fatal); + ppc_init_compat_all(spapr->max_compat_pvr, &error_fatal); /* * This is fixing some of the default configuration of the XIVE diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index b482d9754a..91fae56573 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -74,6 +74,8 @@ static void spapr_reset_vcpu(PowerPCCPU *cpu) kvm_check_mmu(cpu, &error_fatal); + cpu_ppc_tb_reset(env); + spapr_irq_cpu_intc_reset(spapr, cpu); } diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 9b1f225d4a..b7dc388f2f 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -3,6 +3,7 @@ #include "qapi/error.h" #include "sysemu/hw_accel.h" #include "sysemu/runstate.h" +#include "sysemu/tcg.h" #include "qemu/log.h" #include "qemu/main-loop.h" #include "qemu/module.h" @@ -789,6 +790,54 @@ static target_ulong h_logical_dcbf(PowerPCCPU *cpu, SpaprMachineState *spapr, return H_SUCCESS; } +static target_ulong h_set_mode_resource_set_ciabr(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong mflags, + target_ulong value1, + target_ulong value2) +{ + CPUPPCState *env = &cpu->env; + + assert(tcg_enabled()); /* KVM will have handled this */ + + if (mflags) { + return H_UNSUPPORTED_FLAG; + } + if (value2) { + return H_P4; + } + if ((value1 & PPC_BITMASK(62, 63)) == 0x3) { + return H_P3; + } + + ppc_store_ciabr(env, value1); + + return H_SUCCESS; +} + +static target_ulong h_set_mode_resource_set_dawr0(PowerPCCPU *cpu, + SpaprMachineState *spapr, + target_ulong mflags, + target_ulong value1, + target_ulong value2) +{ + CPUPPCState *env = &cpu->env; + + assert(tcg_enabled()); /* KVM will have handled this */ + + if (mflags) { + return H_UNSUPPORTED_FLAG; + } + if (value2 & PPC_BIT(61)) { + return H_P4; + } + + ppc_store_dawr0(env, value1); + ppc_store_dawrx0(env, value2); + + return H_SUCCESS; +} + static target_ulong h_set_mode_resource_le(PowerPCCPU *cpu, SpaprMachineState *spapr, target_ulong mflags, @@ -858,6 +907,14 @@ static target_ulong h_set_mode(PowerPCCPU *cpu, SpaprMachineState *spapr, target_ulong ret = H_P2; switch (resource) { + case H_SET_MODE_RESOURCE_SET_CIABR: + ret = h_set_mode_resource_set_ciabr(cpu, spapr, args[0], args[2], + args[3]); + break; + case H_SET_MODE_RESOURCE_SET_DAWR0: + ret = h_set_mode_resource_set_dawr0(cpu, spapr, args[0], args[2], + args[3]); + break; case H_SET_MODE_RESOURCE_LE: ret = h_set_mode_resource_le(cpu, spapr, args[0], args[2], args[3]); break; diff --git a/hw/ppc/vof.c b/hw/ppc/vof.c index 18c3f92317..e3b430a81f 100644 --- a/hw/ppc/vof.c +++ b/hw/ppc/vof.c @@ -1024,6 +1024,8 @@ void vof_cleanup(Vof *vof) } vof->claimed = NULL; vof->of_instances = NULL; + vof->of_instance_last = 0; + vof->claimed_base = 0; } void vof_build_dt(void *fdt, Vof *vof) diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 35a335b8d0..ec76dce6c9 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -674,9 +674,8 @@ static void sifive_u_machine_init(MachineState *machine) dinfo = drive_get(IF_SD, 0, 0); blk = dinfo ? blk_by_legacy_dinfo(dinfo) : NULL; - card_dev = qdev_new(TYPE_SD_CARD); + card_dev = qdev_new(TYPE_SD_CARD_SPI); qdev_prop_set_drive_err(card_dev, "drive", blk, &error_fatal); - qdev_prop_set_bit(card_dev, "spi", true); qdev_realize_and_unref(card_dev, qdev_get_child_bus(sd_dev, "sd-bus"), &error_fatal); diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 77a717d355..4823befdef 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -87,6 +87,14 @@ enum SDCardStates { sd_disconnect_state, }; +typedef sd_rsp_type_t (*sd_cmd_handler)(SDState *sd, SDRequest req); + +typedef struct SDProto { + const char *name; + sd_cmd_handler cmd[SDMMC_CMD_MAX]; + sd_cmd_handler acmd[SDMMC_CMD_MAX]; +} SDProto; + struct SDState { DeviceState parent_obj; @@ -107,7 +115,6 @@ struct SDState { uint8_t spec_version; BlockBackend *blk; - bool spi; /* Runtime changeables */ @@ -137,7 +144,6 @@ struct SDState { qemu_irq readonly_cb; qemu_irq inserted_cb; QEMUTimer *ocr_power_timer; - const char *proto_name; bool enable; uint8_t dat_lines; bool cmd_line; @@ -145,6 +151,33 @@ struct SDState { static void sd_realize(DeviceState *dev, Error **errp); +static const struct SDProto *sd_proto(SDState *sd) +{ + SDCardClass *sc = SD_CARD_GET_CLASS(sd); + + return sc->proto; +} + +static const SDProto sd_proto_spi; + +static bool sd_is_spi(SDState *sd) +{ + return sd_proto(sd) == &sd_proto_spi; +} + +static const char *sd_version_str(enum SDPhySpecificationVersion version) +{ + static const char *sdphy_version[] = { + [SD_PHY_SPECv1_10_VERS] = "v1.10", + [SD_PHY_SPECv2_00_VERS] = "v2.00", + [SD_PHY_SPECv3_01_VERS] = "v3.01", + }; + if (version >= ARRAY_SIZE(sdphy_version)) { + return "unsupported version"; + } + return sdphy_version[version]; +} + static const char *sd_state_name(enum SDCardStates state) { static const char *state_name[] = { @@ -309,7 +342,7 @@ static void sd_set_ocr(SDState *sd) /* All voltages OK */ sd->ocr = R_OCR_VDD_VOLTAGE_WIN_HI_MASK; - if (sd->spi) { + if (sd_is_spi(sd)) { /* * We don't need to emulate power up sequence in SPI-mode. * Thus, the card's power up status bit should be set to 1 when reset. @@ -714,13 +747,12 @@ SDState *sd_init(BlockBackend *blk, bool is_spi) SDState *sd; Error *err = NULL; - obj = object_new(TYPE_SD_CARD); + obj = object_new(is_spi ? TYPE_SD_CARD_SPI : TYPE_SD_CARD); dev = DEVICE(obj); if (!qdev_prop_set_drive_err(dev, "drive", blk, &err)) { error_reportf_err(err, "sd_init failed: "); return NULL; } - qdev_prop_set_bit(dev, "spi", is_spi); /* * Realizing the device properly would put it into the QOM @@ -966,6 +998,106 @@ static bool address_in_range(SDState *sd, const char *desc, return true; } +static sd_rsp_type_t sd_invalid_state_for_cmd(SDState *sd, SDRequest req) +{ + qemu_log_mask(LOG_GUEST_ERROR, "%s: CMD%i in a wrong state: %s (spec %s)\n", + sd_proto(sd)->name, req.cmd, sd_state_name(sd->state), + sd_version_str(sd->spec_version)); + + return sd_illegal; +} + +static sd_rsp_type_t sd_cmd_illegal(SDState *sd, SDRequest req) +{ + qemu_log_mask(LOG_GUEST_ERROR, "%s: Unknown CMD%i for spec %s\n", + sd_proto(sd)->name, req.cmd, + sd_version_str(sd->spec_version)); + + return sd_illegal; +} + +/* Commands that are recognised but not yet implemented. */ +static sd_rsp_type_t sd_cmd_unimplemented(SDState *sd, SDRequest req) +{ + qemu_log_mask(LOG_UNIMP, "%s: CMD%i not implemented\n", + sd_proto(sd)->name, req.cmd); + + return sd_illegal; +} + +static sd_rsp_type_t sd_cmd_GO_IDLE_STATE(SDState *sd, SDRequest req) +{ + if (sd->state != sd_inactive_state) { + sd->state = sd_idle_state; + sd_reset(DEVICE(sd)); + } + + return sd_is_spi(sd) ? sd_r1 : sd_r0; +} + +static sd_rsp_type_t sd_cmd_SEND_OP_CMD(SDState *sd, SDRequest req) +{ + sd->state = sd_transfer_state; + + return sd_r1; +} + +static sd_rsp_type_t sd_cmd_ALL_SEND_CID(SDState *sd, SDRequest req) +{ + if (sd->state != sd_ready_state) { + return sd_invalid_state_for_cmd(sd, req); + } + + sd->state = sd_identification_state; + + return sd_r2_i; +} + +static sd_rsp_type_t sd_cmd_SEND_RELATIVE_ADDR(SDState *sd, SDRequest req) +{ + switch (sd->state) { + case sd_identification_state: + case sd_standby_state: + sd->state = sd_standby_state; + sd_set_rca(sd); + return sd_r6; + + default: + return sd_invalid_state_for_cmd(sd, req); + } +} + +static sd_rsp_type_t sd_cmd_SEND_TUNING_BLOCK(SDState *sd, SDRequest req) +{ + if (sd->spec_version < SD_PHY_SPECv3_01_VERS) { + return sd_cmd_illegal(sd, req); + } + + if (sd->state != sd_transfer_state) { + return sd_invalid_state_for_cmd(sd, req); + } + + sd->state = sd_sendingdata_state; + sd->data_offset = 0; + + return sd_r1; +} + +static sd_rsp_type_t sd_cmd_SET_BLOCK_COUNT(SDState *sd, SDRequest req) +{ + if (sd->spec_version < SD_PHY_SPECv3_01_VERS) { + return sd_cmd_illegal(sd, req); + } + + if (sd->state != sd_transfer_state) { + return sd_invalid_state_for_cmd(sd, req); + } + + sd->multi_blk_cnt = req.arg; + + return sd_r1; +} + static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) { uint32_t rca = 0x0000; @@ -975,7 +1107,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) * However there is no ACMD55, so we want to trace this particular case. */ if (req.cmd != 55 || sd->expecting_acmd) { - trace_sdcard_normal_command(sd->proto_name, + trace_sdcard_normal_command(sd_proto(sd)->name, sd_cmd_name(req.cmd), req.cmd, req.arg, sd_state_name(sd->state)); } @@ -999,58 +1131,13 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) return sd_illegal; } + if (sd_proto(sd)->cmd[req.cmd]) { + return sd_proto(sd)->cmd[req.cmd](sd, req); + } + switch (req.cmd) { /* Basic commands (Class 0 and Class 1) */ - case 0: /* CMD0: GO_IDLE_STATE */ - switch (sd->state) { - case sd_inactive_state: - return sd->spi ? sd_r1 : sd_r0; - - default: - sd->state = sd_idle_state; - sd_reset(DEVICE(sd)); - return sd->spi ? sd_r1 : sd_r0; - } - break; - - case 1: /* CMD1: SEND_OP_CMD */ - if (!sd->spi) - goto bad_cmd; - - sd->state = sd_transfer_state; - return sd_r1; - - case 2: /* CMD2: ALL_SEND_CID */ - if (sd->spi) - goto bad_cmd; - switch (sd->state) { - case sd_ready_state: - sd->state = sd_identification_state; - return sd_r2_i; - - default: - break; - } - break; - - case 3: /* CMD3: SEND_RELATIVE_ADDR */ - if (sd->spi) - goto bad_cmd; - switch (sd->state) { - case sd_identification_state: - case sd_standby_state: - sd->state = sd_standby_state; - sd_set_rca(sd); - return sd_r6; - - default: - break; - } - break; - case 4: /* CMD4: SEND_DSR */ - if (sd->spi) - goto bad_cmd; switch (sd->state) { case sd_standby_state: break; @@ -1060,9 +1147,6 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) } break; - case 5: /* CMD5: reserved for SDIO cards */ - return sd_illegal; - case 6: /* CMD6: SWITCH_FUNCTION */ switch (sd->mode) { case sd_data_transfer_mode: @@ -1078,8 +1162,6 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) break; case 7: /* CMD7: SELECT/DESELECT_CARD */ - if (sd->spi) - goto bad_cmd; switch (sd->state) { case sd_standby_state: if (sd->rca != rca) @@ -1126,7 +1208,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) /* No response if not exactly one VHS bit is set. */ if (!(req.arg >> 8) || (req.arg >> (ctz32(req.arg & ~0xff) + 1))) { - return sd->spi ? sd_r7 : sd_r0; + return sd_is_spi(sd) ? sd_r7 : sd_r0; } /* Accept. */ @@ -1142,8 +1224,9 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) return sd_r2_s; case sd_transfer_state: - if (!sd->spi) + if (!sd_is_spi(sd)) { break; + } sd->state = sd_sendingdata_state; memcpy(sd->data, sd->csd, 16); sd->data_start = addr; @@ -1164,8 +1247,9 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) return sd_r2_i; case sd_transfer_state: - if (!sd->spi) + if (!sd_is_spi(sd)) { break; + } sd->state = sd_sendingdata_state; memcpy(sd->data, sd->cid, 16); sd->data_start = addr; @@ -1197,7 +1281,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) case 13: /* CMD13: SEND_STATUS */ switch (sd->mode) { case sd_data_transfer_mode: - if (!sd->spi && sd->rca != rca) { + if (!sd_is_spi(sd) && sd->rca != rca) { return sd_r0; } @@ -1209,8 +1293,6 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) break; case 15: /* CMD15: GO_INACTIVE_STATE */ - if (sd->spi) - goto bad_cmd; switch (sd->mode) { case sd_data_transfer_mode: if (sd->rca != rca) @@ -1224,7 +1306,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) } break; - /* Block read commands (Classs 2) */ + /* Block read commands (Class 2) */ case 16: /* CMD16: SET_BLOCKLEN */ switch (sd->state) { case sd_transfer_state: @@ -1261,31 +1343,6 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) } break; - case 19: /* CMD19: SEND_TUNING_BLOCK (SD) */ - if (sd->spec_version < SD_PHY_SPECv3_01_VERS) { - break; - } - if (sd->state == sd_transfer_state) { - sd->state = sd_sendingdata_state; - sd->data_offset = 0; - return sd_r1; - } - break; - - case 23: /* CMD23: SET_BLOCK_COUNT */ - if (sd->spec_version < SD_PHY_SPECv3_01_VERS) { - break; - } - switch (sd->state) { - case sd_transfer_state: - sd->multi_blk_cnt = req.arg; - return sd_r1; - - default: - break; - } - break; - /* Block write commands (Class 4) */ case 24: /* CMD24: WRITE_SINGLE_BLOCK */ case 25: /* CMD25: WRITE_MULTIPLE_BLOCK */ @@ -1317,8 +1374,6 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) break; case 26: /* CMD26: PROGRAM_CID */ - if (sd->spi) - goto bad_cmd; switch (sd->state) { case sd_transfer_state: sd->state = sd_receivingdata_state; @@ -1468,15 +1523,6 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) } break; - case 52 ... 54: - /* CMD52, CMD53, CMD54: reserved for SDIO cards - * (see the SDIO Simplified Specification V2.0) - * Handle as illegal command but do not complain - * on stderr, as some OSes may use these in their - * probing for presence of an SDIO card. - */ - return sd_illegal; - /* Application specific commands (Class 8) */ case 55: /* CMD55: APP_CMD */ switch (sd->state) { @@ -1492,7 +1538,7 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) default: break; } - if (!sd->spi) { + if (!sd_is_spi(sd)) { if (sd->rca != rca) { return sd_r0; } @@ -1517,39 +1563,32 @@ static sd_rsp_type_t sd_normal_command(SDState *sd, SDRequest req) break; case 58: /* CMD58: READ_OCR (SPI) */ - if (!sd->spi) { - goto bad_cmd; - } return sd_r3; case 59: /* CMD59: CRC_ON_OFF (SPI) */ - if (!sd->spi) { - goto bad_cmd; - } return sd_r1; default: - bad_cmd: qemu_log_mask(LOG_GUEST_ERROR, "SD: Unknown CMD%i\n", req.cmd); return sd_illegal; } - qemu_log_mask(LOG_GUEST_ERROR, "SD: CMD%i in a wrong state: %s\n", - req.cmd, sd_state_name(sd->state)); - return sd_illegal; + return sd_invalid_state_for_cmd(sd, req); } static sd_rsp_type_t sd_app_command(SDState *sd, SDRequest req) { - trace_sdcard_app_command(sd->proto_name, sd_acmd_name(req.cmd), + trace_sdcard_app_command(sd_proto(sd)->name, sd_acmd_name(req.cmd), req.cmd, req.arg, sd_state_name(sd->state)); sd->card_status |= APP_CMD; + + if (sd_proto(sd)->acmd[req.cmd]) { + return sd_proto(sd)->acmd[req.cmd](sd, req); + } + switch (req.cmd) { case 6: /* ACMD6: SET_BUS_WIDTH */ - if (sd->spi) { - goto unimplemented_spi_cmd; - } switch (sd->state) { case sd_transfer_state: sd->sd_status[0] &= 0x3f; @@ -1600,11 +1639,6 @@ static sd_rsp_type_t sd_app_command(SDState *sd, break; case 41: /* ACMD41: SD_APP_OP_COND */ - if (sd->spi) { - /* SEND_OP_CMD */ - sd->state = sd_transfer_state; - return sd_r1; - } if (sd->state != sd_idle_state) { break; } @@ -1680,12 +1714,6 @@ static sd_rsp_type_t sd_app_command(SDState *sd, default: /* Fall back to standard commands. */ return sd_normal_command(sd, req); - - unimplemented_spi_cmd: - /* Commands that are recognised but not yet implemented in SPI mode. */ - qemu_log_mask(LOG_UNIMP, "SD: CMD%i not implemented in SPI mode\n", - req.cmd); - return sd_illegal; } qemu_log_mask(LOG_GUEST_ERROR, "SD: ACMD%i in a wrong state\n", req.cmd); @@ -1836,7 +1864,7 @@ void sd_write_byte(SDState *sd, uint8_t value) if (sd->card_status & (ADDRESS_ERROR | WP_VIOLATION)) return; - trace_sdcard_write_data(sd->proto_name, + trace_sdcard_write_data(sd_proto(sd)->name, sd_acmd_name(sd->current_cmd), sd->current_cmd, value); switch (sd->current_cmd) { @@ -1992,7 +2020,7 @@ uint8_t sd_read_byte(SDState *sd) io_len = (sd->ocr & (1 << 30)) ? 512 : sd->blk_len; - trace_sdcard_read_data(sd->proto_name, + trace_sdcard_read_data(sd_proto(sd)->name, sd_acmd_name(sd->current_cmd), sd->current_cmd, io_len); switch (sd->current_cmd) { @@ -2111,6 +2139,40 @@ void sd_enable(SDState *sd, bool enable) sd->enable = enable; } +static const SDProto sd_proto_spi = { + .name = "SPI", + .cmd = { + [0] = sd_cmd_GO_IDLE_STATE, + [1] = sd_cmd_SEND_OP_CMD, + [2 ... 4] = sd_cmd_illegal, + [5] = sd_cmd_illegal, + [7] = sd_cmd_illegal, + [15] = sd_cmd_illegal, + [26] = sd_cmd_illegal, + [52 ... 54] = sd_cmd_illegal, + }, + .acmd = { + [6] = sd_cmd_unimplemented, + [41] = sd_cmd_SEND_OP_CMD, + }, +}; + +static const SDProto sd_proto_sd = { + .name = "SD", + .cmd = { + [0] = sd_cmd_GO_IDLE_STATE, + [1] = sd_cmd_illegal, + [2] = sd_cmd_ALL_SEND_CID, + [3] = sd_cmd_SEND_RELATIVE_ADDR, + [5] = sd_cmd_illegal, + [19] = sd_cmd_SEND_TUNING_BLOCK, + [23] = sd_cmd_SET_BLOCK_COUNT, + [52 ... 54] = sd_cmd_illegal, + [58] = sd_cmd_illegal, + [59] = sd_cmd_illegal, + }, +}; + static void sd_instance_init(Object *obj) { SDState *sd = SD_CARD(obj); @@ -2131,8 +2193,6 @@ static void sd_realize(DeviceState *dev, Error **errp) SDState *sd = SD_CARD(dev); int ret; - sd->proto_name = sd->spi ? "SPI" : "SD"; - switch (sd->spec_version) { case SD_PHY_SPECv1_10_VERS ... SD_PHY_SPECv3_01_VERS: @@ -2189,7 +2249,6 @@ static Property sd_properties[] = { * whether card should be in SSI or MMC/SD mode. It is also up to the * board to ensure that ssi transfers only occur when the chip select * is asserted. */ - DEFINE_PROP_BOOL("spi", SDState, spi, false), DEFINE_PROP_END_OF_LIST() }; @@ -2216,6 +2275,7 @@ static void sd_class_init(ObjectClass *klass, void *data) sc->enable = sd_enable; sc->get_inserted = sd_get_inserted; sc->get_readonly = sd_get_readonly; + sc->proto = &sd_proto_sd; } static const TypeInfo sd_info = { @@ -2228,9 +2288,31 @@ static const TypeInfo sd_info = { .instance_finalize = sd_instance_finalize, }; +/* + * We do not model the chip select pin, so allow the board to select + * whether card should be in SSI or MMC/SD mode. It is also up to the + * board to ensure that ssi transfers only occur when the chip select + * is asserted. + */ +static void sd_spi_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + SDCardClass *sc = SD_CARD_CLASS(klass); + + dc->desc = "SD SPI"; + sc->proto = &sd_proto_spi; +} + +static const TypeInfo sd_spi_info = { + .name = TYPE_SD_CARD_SPI, + .parent = TYPE_SD_CARD, + .class_init = sd_spi_class_init, +}; + static void sd_register_types(void) { type_register_static(&sd_info); + type_register_static(&sd_spi_info); } type_init(sd_register_types) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 362c2c86aa..5564765a9b 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1811,7 +1811,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) * on i.MX, but since it is not used by QEMU we do not care. * * We don't want to call sdhci_write(.., SDHC_TRNMOD, ...) - * here becuase it will result in a call to + * here because it will result in a call to * sdhci_send_command(s) which we don't want. * */ diff --git a/hw/sd/sdmmc-internal.c b/hw/sd/sdmmc-internal.c index 2053def3f1..8648a7808d 100644 --- a/hw/sd/sdmmc-internal.c +++ b/hw/sd/sdmmc-internal.c @@ -14,7 +14,7 @@ const char *sd_cmd_name(uint8_t cmd) { static const char *cmd_abbrev[SDMMC_CMD_MAX] = { - [0] = "GO_IDLE_STATE", + [0] = "GO_IDLE_STATE", [1] = "SEND_OP_CMD", [2] = "ALL_SEND_CID", [3] = "SEND_RELATIVE_ADDR", [4] = "SET_DSR", [5] = "IO_SEND_OP_COND", [6] = "SWITCH_FUNC", [7] = "SELECT/DESELECT_CARD", diff --git a/hw/sensor/isl_pmbus_vr.c b/hw/sensor/isl_pmbus_vr.c index eb344dd5a9..e51269f6b8 100644 --- a/hw/sensor/isl_pmbus_vr.c +++ b/hw/sensor/isl_pmbus_vr.c @@ -101,7 +101,7 @@ static void isl_pmbus_vr_exit_reset(Object *obj) } } -/* The raa228000 uses different direct mode coefficents from most isl devices */ +/* The raa228000 uses different direct mode coefficients from most isl devices */ static void raa228000_exit_reset(Object *obj) { PMBusDevice *pmdev = PMBUS_DEVICE(obj); diff --git a/hw/sensor/max34451.c b/hw/sensor/max34451.c index a91d8bd487..9db52ef677 100644 --- a/hw/sensor/max34451.c +++ b/hw/sensor/max34451.c @@ -734,7 +734,7 @@ static void max34451_init(Object *obj) /* * get and set the temperature of the internal temperature sensor in - * centidegrees Celcius i.e.: 2500 -> 25.00 C, max is 327.67 C + * centidegrees Celsius i.e.: 2500 -> 25.00 C, max is 327.67 C */ for (int i = 0; i < MAX34451_NUM_TEMP_DEVICES; i++) { object_property_add(obj, "temperature[*]", "uint16", diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 7281169322..2a4001b774 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -692,6 +692,14 @@ static void aspeed_smc_reset(DeviceState *d) memset(s->regs, 0, sizeof s->regs); } + for (i = 0; i < asc->cs_num_max; i++) { + DeviceState *dev = ssi_get_cs(s->spi, i); + if (dev) { + qemu_irq cs_line = qdev_get_gpio_in_named(dev, SSI_GPIO_CS, 0); + qdev_connect_gpio_out_named(DEVICE(s), "cs", i, cs_line); + } + } + /* Unselect all peripherals */ for (i = 0; i < asc->cs_num_max; ++i) { s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c index d54a109bee..1f3e540ab8 100644 --- a/hw/ssi/ssi.c +++ b/hw/ssi/ssi.c @@ -13,6 +13,7 @@ */ #include "qemu/osdep.h" +#include "hw/qdev-properties.h" #include "hw/ssi/ssi.h" #include "migration/vmstate.h" #include "qemu/module.h" @@ -26,10 +27,46 @@ struct SSIBus { #define TYPE_SSI_BUS "SSI" OBJECT_DECLARE_SIMPLE_TYPE(SSIBus, SSI_BUS) +DeviceState *ssi_get_cs(SSIBus *bus, uint8_t cs_index) +{ + BusState *b = BUS(bus); + BusChild *kid; + + QTAILQ_FOREACH(kid, &b->children, sibling) { + SSIPeripheral *kid_ssi = SSI_PERIPHERAL(kid->child); + if (kid_ssi->cs_index == cs_index) { + return kid->child; + } + } + + return NULL; +} + +static bool ssi_bus_check_address(BusState *b, DeviceState *dev, Error **errp) +{ + SSIPeripheral *s = SSI_PERIPHERAL(dev); + + if (ssi_get_cs(SSI_BUS(b), s->cs_index)) { + error_setg(errp, "CS index '0x%x' in use by a %s device", s->cs_index, + object_get_typename(OBJECT(dev))); + return false; + } + + return true; +} + +static void ssi_bus_class_init(ObjectClass *klass, void *data) +{ + BusClass *k = BUS_CLASS(klass); + + k->check_address = ssi_bus_check_address; +} + static const TypeInfo ssi_bus_info = { .name = TYPE_SSI_BUS, .parent = TYPE_BUS, .instance_size = sizeof(SSIBus), + .class_init = ssi_bus_class_init, }; static void ssi_cs_default(void *opaque, int n, int level) @@ -71,6 +108,11 @@ static void ssi_peripheral_realize(DeviceState *dev, Error **errp) ssc->realize(s, errp); } +static Property ssi_peripheral_properties[] = { + DEFINE_PROP_UINT8("cs", SSIPeripheral, cs_index, 0), + DEFINE_PROP_END_OF_LIST(), +}; + static void ssi_peripheral_class_init(ObjectClass *klass, void *data) { SSIPeripheralClass *ssc = SSI_PERIPHERAL_CLASS(klass); @@ -81,6 +123,7 @@ static void ssi_peripheral_class_init(ObjectClass *klass, void *data) if (!ssc->transfer_raw) { ssc->transfer_raw = ssi_transfer_raw_default; } + device_class_set_props(dc, ssi_peripheral_properties); } static const TypeInfo ssi_peripheral_info = { diff --git a/hw/usb/ccid-card-emulated.c b/hw/usb/ccid-card-emulated.c index c328660075..3ee9c73b87 100644 --- a/hw/usb/ccid-card-emulated.c +++ b/hw/usb/ccid-card-emulated.c @@ -518,7 +518,7 @@ static void emulated_realize(CCIDCardState *base, Error **errp) goto out2; } - /* TODO: a passthru backened that works on local machine. third card type?*/ + /* TODO: a passthru backend that works on local machine. third card type?*/ if (card->backend == BACKEND_CERTIFICATES) { if (card->cert1 != NULL && card->cert2 != NULL && card->cert3 != NULL) { ret = emulated_initialize_vcard_from_certificates(card); diff --git a/hw/usb/hcd-ehci.c b/hw/usb/hcd-ehci.c index c930c60921..19b4534c20 100644 --- a/hw/usb/hcd-ehci.c +++ b/hw/usb/hcd-ehci.c @@ -1464,7 +1464,7 @@ static int ehci_process_itd(EHCIState *ehci, usb_handle_packet(dev, &ehci->ipacket); usb_packet_unmap(&ehci->ipacket, &ehci->isgl); } else { - DPRINTF("ISOCH: attempt to addess non-iso endpoint\n"); + DPRINTF("ISOCH: attempt to address non-iso endpoint\n"); ehci->ipacket.status = USB_RET_NAK; ehci->ipacket.actual_length = 0; } @@ -1513,7 +1513,7 @@ static int ehci_process_itd(EHCIState *ehci, /* This state is the entry point for asynchronous schedule - * processing. Entry here consitutes a EHCI start event state (4.8.5) + * processing. Entry here constitutes a EHCI start event state (4.8.5) */ static int ehci_state_waitlisthead(EHCIState *ehci, int async) { @@ -2458,7 +2458,7 @@ static void usb_ehci_vm_state_change(void *opaque, bool running, RunState state) /* * The schedule rebuilt from guest memory could cause the migration dest * to miss a QH unlink, and fail to cancel packets, since the unlinked QH - * will never have existed on the destination. Therefor we must flush the + * will never have existed on the destination. Therefore we must flush the * async schedule on savevm to catch any not yet noticed unlinks. */ if (state == RUN_STATE_SAVE_VM) { diff --git a/hw/usb/hcd-ohci.c b/hw/usb/hcd-ohci.c index cc5cde6983..7ff1b65ced 100644 --- a/hw/usb/hcd-ohci.c +++ b/hw/usb/hcd-ohci.c @@ -1355,7 +1355,7 @@ static uint32_t ohci_get_frame_remaining(OHCIState *ohci) if ((ohci->ctl & OHCI_CTL_HCFS) != OHCI_USB_OPERATIONAL) { return ohci->frt << 31; } - /* Being in USB operational state guarnatees sof_time was set already. */ + /* Being in USB operational state guarantees sof_time was set already. */ tks = qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL) - ohci->sof_time; if (tks < 0) { tks = 0; diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index b89b618ec2..324177ad5d 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -2434,7 +2434,6 @@ static void xhci_detach_slot(XHCIState *xhci, USBPort *uport) static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) { dma_addr_t ctx; - uint8_t bw_ctx[xhci->numports+1]; DPRINTF("xhci_get_port_bandwidth()\n"); @@ -2442,11 +2441,10 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) DPRINTF("xhci: bandwidth context at "DMA_ADDR_FMT"\n", ctx); - /* TODO: actually implement real values here */ - bw_ctx[0] = 0; - memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ - if (dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx), - MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) { + /* TODO: actually implement real values here. This is 80% for all ports. */ + if (stb_dma(xhci->as, ctx, 0, MEMTXATTRS_UNSPECIFIED) != MEMTX_OK || + dma_memory_set(xhci->as, ctx + 1, 80, xhci->numports, + MEMTXATTRS_UNSPECIFIED) != MEMTX_OK) { qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA memory write failed!\n", __func__); return CC_TRB_ERROR; diff --git a/hw/usb/quirks.h b/hw/usb/quirks.h index c3e595f40b..94b2c95341 100644 --- a/hw/usb/quirks.h +++ b/hw/usb/quirks.h @@ -67,7 +67,7 @@ static const struct usb_device_id usbredir_raw_serial_ids[] = { { USB_DEVICE(0x10C4, 0x800A) }, /* SPORTident BSM7-D-USB main station */ { USB_DEVICE(0x10C4, 0x803B) }, /* Pololu USB-serial converter */ { USB_DEVICE(0x10C4, 0x8044) }, /* Cygnal Debug Adapter */ - { USB_DEVICE(0x10C4, 0x804E) }, /* Software Bisque Paramount ME build-in converter */ + { USB_DEVICE(0x10C4, 0x804E) }, /* Software Bisque Paramount ME built-in converter */ { USB_DEVICE(0x10C4, 0x8053) }, /* Enfora EDG1228 */ { USB_DEVICE(0x10C4, 0x8054) }, /* Enfora GSM2228 */ { USB_DEVICE(0x10C4, 0x8066) }, /* Argussoft In-System Programmer */ diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 39fbaaab16..c9893df867 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -278,7 +278,7 @@ static gboolean usbredir_write_unblocked(void *do_not_use, GIOCondition cond, dev->watch = 0; usbredirparser_do_write(dev->parser); - return FALSE; + return G_SOURCE_REMOVE; } static int usbredir_write(void *priv, uint8_t *data, int count) @@ -471,7 +471,7 @@ static int bufp_alloc(USBRedirDevice *dev, uint8_t *data, uint16_t len, DPRINTF("bufpq overflow, dropping packets ep %02X\n", ep); dev->endpoint[EP2I(ep)].bufpq_dropping_packets = 1; } - /* Since we're interupting the stream anyways, drop enough packets to get + /* Since we're interrupting the stream anyways, drop enough packets to get back to our target buffer size */ if (dev->endpoint[EP2I(ep)].bufpq_dropping_packets) { if (dev->endpoint[EP2I(ep)].bufpq_size > diff --git a/hw/usb/trace-events b/hw/usb/trace-events index 6bb9655c8d..ed7dc210d3 100644 --- a/hw/usb/trace-events +++ b/hw/usb/trace-events @@ -248,7 +248,7 @@ usb_set_device_feature(int addr, int feature, int ret) "dev %d, feature %d, ret # dev-hub.c usb_hub_reset(int addr) "dev %d" -usb_hub_control(int addr, int request, int value, int index, int length) "dev %d, req 0x%x, value %d, index %d, langth %d" +usb_hub_control(int addr, int request, int value, int index, int length) "dev %d, req 0x%x, value %d, index %d, length %d" usb_hub_get_port_status(int addr, int nr, int status, int changed) "dev %d, port %d, status 0x%x, changed 0x%x" usb_hub_set_port_feature(int addr, int nr, const char *f) "dev %d, port %d, feature %s" usb_hub_clear_port_feature(int addr, int nr, const char *f) "dev %d, port %d, feature %s" diff --git a/hw/usb/xen-usb.c b/hw/usb/xen-usb.c index 38ee660a30..09ec326aea 100644 --- a/hw/usb/xen-usb.c +++ b/hw/usb/xen-usb.c @@ -451,7 +451,7 @@ static int usbback_check_and_submit(struct usbback_req *usbback_req) wValue = le16_to_cpu(ctrl->wValue); /* - * When the device is first connected or resetted, USB device has no + * When the device is first connected or reset, USB device has no * address. In this initial state, following requests are sent to device * address (#0), * diff --git a/hw/xen/xen_pt.h b/hw/xen/xen_pt.h index b20744f7c7..31bcfdf705 100644 --- a/hw/xen/xen_pt.h +++ b/hw/xen/xen_pt.h @@ -340,11 +340,9 @@ static inline bool xen_pt_has_msix_mapping(XenPCIPassthroughState *s, int bar) return s->msix && s->msix->bar_index == bar; } -extern void *pci_assign_dev_load_option_rom(PCIDevice *dev, - int *size, - unsigned int domain, - unsigned int bus, unsigned int slot, - unsigned int function); +void *pci_assign_dev_load_option_rom(PCIDevice *dev, int *size, + unsigned int domain, unsigned int bus, + unsigned int slot, unsigned int function); static inline bool is_igd_vga_passthrough(XenHostPCIDevice *dev) { return (xen_igd_gfx_pt_enabled() diff --git a/hw/xtensa/pic_cpu.c b/hw/xtensa/pic_cpu.c index 6c9447565d..8cef88c61b 100644 --- a/hw/xtensa/pic_cpu.c +++ b/hw/xtensa/pic_cpu.c @@ -30,6 +30,7 @@ #include "hw/irq.h" #include "qemu/log.h" #include "qemu/timer.h" +#include "qemu/atomic.h" void check_interrupts(CPUXtensaState *env) { diff --git a/include/chardev/char-fe.h b/include/chardev/char-fe.h index 8c420fa36e..0109602d63 100644 --- a/include/chardev/char-fe.h +++ b/include/chardev/char-fe.h @@ -175,6 +175,20 @@ void qemu_chr_fe_printf(CharBackend *be, const char *fmt, ...) G_GNUC_PRINTF(2, 3); +/** + * FEWatchFunc: a #GSourceFunc called when any conditions requested by + * qemu_chr_fe_add_watch() is satisfied. + * @do_not_use: depending on the underlying chardev, a GIOChannel or a + * QIOChannel. DO NOT USE! + * @cond: bitwise combination of conditions watched and satisfied + * before calling this callback. + * @data: user data passed at creation to qemu_chr_fe_add_watch(). Can + * be NULL. + * + * Returns: G_SOURCE_REMOVE if the GSource should be removed from the + * main loop, or G_SOURCE_CONTINUE to leave the GSource in + * the main loop. + */ typedef gboolean (*FEWatchFunc)(void *do_not_use, GIOCondition condition, void *data); /** diff --git a/include/chardev/char.h b/include/chardev/char.h index 44cd82e405..01df55f9e8 100644 --- a/include/chardev/char.h +++ b/include/chardev/char.h @@ -320,7 +320,4 @@ GSource *qemu_chr_timeout_add_ms(Chardev *chr, guint ms, void suspend_mux_open(void); void resume_mux_open(void); -/* console.c */ -void qemu_chr_parse_vc(QemuOpts *opts, ChardevBackend *backend, Error **errp); - #endif diff --git a/include/crypto/secret_common.h b/include/crypto/secret_common.h index 42c7ff7af6..a0a22e1abd 100644 --- a/include/crypto/secret_common.h +++ b/include/crypto/secret_common.h @@ -48,13 +48,11 @@ struct QCryptoSecretCommonClass { }; -extern int qcrypto_secret_lookup(const char *secretid, - uint8_t **data, - size_t *datalen, - Error **errp); -extern char *qcrypto_secret_lookup_as_utf8(const char *secretid, - Error **errp); -extern char *qcrypto_secret_lookup_as_base64(const char *secretid, - Error **errp); +int qcrypto_secret_lookup(const char *secretid, + uint8_t **data, + size_t *datalen, + Error **errp); +char *qcrypto_secret_lookup_as_utf8(const char *secretid, Error **errp); +char *qcrypto_secret_lookup_as_base64(const char *secretid, Error **errp); #endif /* QCRYPTO_SECRET_COMMON_H */ diff --git a/include/elf.h b/include/elf.h index ec9755e73b..e7259ec366 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1125,9 +1125,9 @@ typedef struct { #define EFA_PARISC_1_1 0x0210 /* PA-RISC 1.1 big-endian. */ #define EFA_PARISC_2_0 0x0214 /* PA-RISC 2.0 big-endian. */ -/* Additional section indeces. */ +/* Additional section indices. */ -#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tenatively declared +#define SHN_PARISC_ANSI_COMMON 0xff00 /* Section for tentatively declared symbols in ANSI C. */ #define SHN_PARISC_HUGE_COMMON 0xff01 /* Common blocks in huge model. */ diff --git a/include/exec/address-spaces.h b/include/exec/address-spaces.h index db8bfa9a92..0d0aa61d68 100644 --- a/include/exec/address-spaces.h +++ b/include/exec/address-spaces.h @@ -19,8 +19,6 @@ * you're one of them. */ -#include "exec/memory.h" - #ifndef CONFIG_USER_ONLY /* Get the root memory region. This interface should only be used temporarily diff --git a/include/exec/exec-all.h b/include/exec/exec-all.h index d02517e95f..b2f5cd4c2a 100644 --- a/include/exec/exec-all.h +++ b/include/exec/exec-all.h @@ -21,7 +21,7 @@ #define EXEC_ALL_H #include "cpu.h" -#ifdef CONFIG_TCG +#if defined(CONFIG_USER_ONLY) #include "exec/cpu_ldst.h" #endif #include "exec/translation-block.h" diff --git a/include/exec/memory_ldst.h.inc b/include/exec/memory_ldst.h.inc index 7c3a641f7e..92ad74e956 100644 --- a/include/exec/memory_ldst.h.inc +++ b/include/exec/memory_ldst.h.inc @@ -20,48 +20,48 @@ */ #ifdef TARGET_ENDIANNESS -extern uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, +uint16_t glue(address_space_lduw, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, +uint32_t glue(address_space_ldl, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL, +uint64_t glue(address_space_ldq, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, +void glue(address_space_stl_notdirty, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stw, SUFFIX)(ARG1_DECL, +void glue(address_space_stw, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl, SUFFIX)(ARG1_DECL, +void glue(address_space_stl, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stq, SUFFIX)(ARG1_DECL, +void glue(address_space_stq, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); #else -extern uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, +uint8_t glue(address_space_ldub, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, +uint16_t glue(address_space_lduw_le, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL, +uint16_t glue(address_space_lduw_be, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL, +uint32_t glue(address_space_ldl_le, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL, +uint32_t glue(address_space_ldl_be, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL, +uint64_t glue(address_space_ldq_le, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL, +uint64_t glue(address_space_ldq_be, SUFFIX)(ARG1_DECL, hwaddr addr, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stb, SUFFIX)(ARG1_DECL, +void glue(address_space_stb, SUFFIX)(ARG1_DECL, hwaddr addr, uint8_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stw_le, SUFFIX)(ARG1_DECL, +void glue(address_space_stw_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stw_be, SUFFIX)(ARG1_DECL, +void glue(address_space_stw_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint16_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl_le, SUFFIX)(ARG1_DECL, +void glue(address_space_stl_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stl_be, SUFFIX)(ARG1_DECL, +void glue(address_space_stl_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint32_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, +void glue(address_space_stq_le, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); -extern void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, +void glue(address_space_stq_be, SUFFIX)(ARG1_DECL, hwaddr addr, uint64_t val, MemTxAttrs attrs, MemTxResult *result); #endif diff --git a/include/exec/page-vary.h b/include/exec/page-vary.h index ebbe9b169b..54ddde308a 100644 --- a/include/exec/page-vary.h +++ b/include/exec/page-vary.h @@ -27,8 +27,8 @@ typedef struct { } TargetPageBits; #ifdef IN_PAGE_VARY -extern bool set_preferred_target_page_bits_common(int bits); -extern void finalize_target_page_bits_common(int min); +bool set_preferred_target_page_bits_common(int bits); +void finalize_target_page_bits_common(int min); #endif /** diff --git a/include/exec/poison.h b/include/exec/poison.h index e94ee8dfef..1ea5633eb3 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -81,7 +81,6 @@ #pragma GCC poison CONFIG_SPARC_DIS #pragma GCC poison CONFIG_XTENSA_DIS -#pragma GCC poison CONFIG_HAX #pragma GCC poison CONFIG_HVF #pragma GCC poison CONFIG_LINUX_USER #pragma GCC poison CONFIG_KVM diff --git a/include/exec/translation-block.h b/include/exec/translation-block.h index 5119924927..b785751774 100644 --- a/include/exec/translation-block.h +++ b/include/exec/translation-block.h @@ -7,11 +7,11 @@ #ifndef EXEC_TRANSLATION_BLOCK_H #define EXEC_TRANSLATION_BLOCK_H -#include "qemu/atomic.h" #include "qemu/thread.h" -#include "qemu/interval-tree.h" #include "exec/cpu-common.h" -#include "exec/target_page.h" +#ifdef CONFIG_USER_ONLY +#include "qemu/interval-tree.h" +#endif /* * Page tracking code uses ram addresses in system mode, and virtual diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 7198953702..de93756cbe 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -76,4 +76,8 @@ uint8_t ecc_digest(ECCState *s, uint8_t sample); void ecc_reset(ECCState *s); extern const VMStateDescription vmstate_ecc_state; +/* m25p80.c */ + +BlockBackend *m25p80_get_blk(DeviceState *dev); + #endif diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h index fdcbe87352..92a4234439 100644 --- a/include/hw/core/cpu.h +++ b/include/hw/core/cpu.h @@ -422,7 +422,7 @@ struct CPUState { int32_t exception_index; AccelCPUState *accel; - /* shared by kvm, hax and hvf */ + /* shared by kvm and hvf */ bool vcpu_dirty; /* Used to keep track of an outstanding cpu throttle thread for migration diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h index 3e8b1b737a..479713a36e 100644 --- a/include/hw/core/tcg-cpu-ops.h +++ b/include/hw/core/tcg-cpu-ops.h @@ -14,7 +14,7 @@ struct TCGCPUOps { /** - * @initialize: Initalize TCG state + * @initialize: Initialize TCG state * * Called when the first CPU is realized. */ diff --git a/include/hw/i2c/aspeed_i2c.h b/include/hw/i2c/aspeed_i2c.h index 51c944efea..a064479e59 100644 --- a/include/hw/i2c/aspeed_i2c.h +++ b/include/hw/i2c/aspeed_i2c.h @@ -139,10 +139,11 @@ REG32(I2CD_CMD, 0x14) /* I2CD Command/Status */ REG32(I2CD_DEV_ADDR, 0x18) /* Slave Device Address */ SHARED_FIELD(SLAVE_DEV_ADDR1, 0, 7) REG32(I2CD_POOL_CTRL, 0x1C) /* Pool Buffer Control */ - SHARED_FIELD(RX_COUNT, 24, 5) + SHARED_FIELD(RX_COUNT, 24, 6) SHARED_FIELD(RX_SIZE, 16, 5) - SHARED_FIELD(TX_COUNT, 9, 5) + SHARED_FIELD(TX_COUNT, 8, 5) FIELD(I2CD_POOL_CTRL, OFFSET, 2, 6) /* AST2400 */ + SHARED_FIELD(BUF_ORGANIZATION, 0, 1) /* AST2600 */ REG32(I2CD_BYTE_BUF, 0x20) /* Transmit/Receive Byte Buffer */ SHARED_FIELD(RX_BUF, 8, 8) SHARED_FIELD(TX_BUF, 0, 8) diff --git a/include/hw/i2c/npcm7xx_smbus.h b/include/hw/i2c/npcm7xx_smbus.h index 3555e6836f..dc45963c0e 100644 --- a/include/hw/i2c/npcm7xx_smbus.h +++ b/include/hw/i2c/npcm7xx_smbus.h @@ -58,7 +58,7 @@ typedef enum NPCM7xxSMBusStatus { * @sclht: The SCL high time register. * @fif_ctl: The FIFO control register. * @fif_cts: The FIFO control status register. - * @fair_per: The fair preriod register. + * @fair_per: The fair period register. * @txf_ctl: The transmit FIFO control register. * @t_out: The SMBus timeout register. * @txf_sts: The transmit FIFO status register. diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 5c7c04eedf..7cb6018dbc 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -51,7 +51,7 @@ struct AspeedSCUState { #define ASPEED_IS_AST2500(si_rev) ((((si_rev) >> 24) & 0xff) == 0x04) -extern bool is_supported_silicon_rev(uint32_t silicon_rev); +bool is_supported_silicon_rev(uint32_t silicon_rev); struct AspeedSCUClass { diff --git a/include/hw/misc/auxbus.h b/include/hw/misc/auxbus.h index b05799d2f7..03cacdee42 100644 --- a/include/hw/misc/auxbus.h +++ b/include/hw/misc/auxbus.h @@ -106,7 +106,7 @@ void aux_bus_realize(AUXBus *bus); * * Returns the reply of the request. * - * @bus Ths bus where the request happen. + * @bus The bus where the request happen. * @cmd The command requested. * @address The 20bits address of the slave. * @len The length of the read or write. diff --git a/include/hw/nvram/npcm7xx_otp.h b/include/hw/nvram/npcm7xx_otp.h index 156bbd151a..ea4b5d0731 100644 --- a/include/hw/nvram/npcm7xx_otp.h +++ b/include/hw/nvram/npcm7xx_otp.h @@ -73,7 +73,7 @@ typedef struct NPCM7xxOTPClass NPCM7xxOTPClass; * Each nibble of data is encoded into a byte, so the number of bytes written * to the array will be @len * 2. */ -extern void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data, - unsigned int offset, unsigned int len); +void npcm7xx_otp_array_write(NPCM7xxOTPState *s, const void *data, + unsigned int offset, unsigned int len); #endif /* NPCM7XX_OTP_H */ diff --git a/include/hw/ppc/ppc.h b/include/hw/ppc/ppc.h index e095c002dc..17a8dfc107 100644 --- a/include/hw/ppc/ppc.h +++ b/include/hw/ppc/ppc.h @@ -54,7 +54,8 @@ struct ppc_tb_t { */ uint64_t cpu_ppc_get_tb(ppc_tb_t *tb_env, uint64_t vmclk, int64_t tb_offset); -clk_setup_cb cpu_ppc_tb_init (CPUPPCState *env, uint32_t freq); +void cpu_ppc_tb_init(CPUPPCState *env, uint32_t freq); +void cpu_ppc_tb_reset(CPUPPCState *env); void cpu_ppc_tb_free(CPUPPCState *env); void cpu_ppc_hdecr_init(CPUPPCState *env); void cpu_ppc_hdecr_exit(CPUPPCState *env); diff --git a/include/hw/ppc/spapr.h b/include/hw/ppc/spapr.h index 538b2dfb89..f4bd204d86 100644 --- a/include/hw/ppc/spapr.h +++ b/include/hw/ppc/spapr.h @@ -204,6 +204,7 @@ struct SpaprMachineState { uint32_t fdt_size; uint32_t fdt_initial_size; void *fdt_blob; + uint8_t fdt_rng_seed[32]; long kernel_size; bool kernel_le; uint64_t kernel_addr; @@ -1012,6 +1013,7 @@ bool spapr_check_pagesize(SpaprMachineState *spapr, hwaddr pagesize, #define SPAPR_OV5_XIVE_BOTH 0x80 /* Only to advertise on the platform */ void spapr_set_all_lpcrs(target_ulong value, target_ulong mask); +void spapr_init_all_lpcrs(target_ulong value, target_ulong mask); hwaddr spapr_get_rtas_addr(void); bool spapr_memory_hot_unplug_supported(SpaprMachineState *spapr); diff --git a/include/hw/ppc/xive.h b/include/hw/ppc/xive.h index 9f580a2699..f120874e0f 100644 --- a/include/hw/ppc/xive.h +++ b/include/hw/ppc/xive.h @@ -401,6 +401,7 @@ struct XiveRouterClass { int (*write_nvt)(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); uint8_t (*get_block_id)(XiveRouter *xrtr); + void (*end_notify)(XiveRouter *xrtr, XiveEAS *eas); }; int xive_router_get_eas(XiveRouter *xrtr, uint8_t eas_blk, uint32_t eas_idx, @@ -414,6 +415,7 @@ int xive_router_get_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, int xive_router_write_nvt(XiveRouter *xrtr, uint8_t nvt_blk, uint32_t nvt_idx, XiveNVT *nvt, uint8_t word_number); void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked); +void xive_router_end_notify(XiveRouter *xrtr, XiveEAS *eas); /* * XIVE Presenter diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 884c726a87..151d968238 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -1086,7 +1086,7 @@ typedef enum MachineInitPhase { PHASE_MACHINE_READY, } MachineInitPhase; -extern bool phase_check(MachineInitPhase phase); -extern void phase_advance(MachineInitPhase phase); +bool phase_check(MachineInitPhase phase); +void phase_advance(MachineInitPhase phase); #endif diff --git a/include/hw/sd/sd.h b/include/hw/sd/sd.h index 3047adb2fc..2c8748fb9b 100644 --- a/include/hw/sd/sd.h +++ b/include/hw/sd/sd.h @@ -93,6 +93,9 @@ typedef struct { #define TYPE_SD_CARD "sd-card" OBJECT_DECLARE_TYPE(SDState, SDCardClass, SD_CARD) +#define TYPE_SD_CARD_SPI "sd-card-spi" +DECLARE_INSTANCE_CHECKER(SDState, SD_CARD_SPI, TYPE_SD_CARD_SPI) + struct SDCardClass { /*< private >*/ DeviceClass parent_class; @@ -124,6 +127,8 @@ struct SDCardClass { void (*enable)(SDState *sd, bool enable); bool (*get_inserted)(SDState *sd); bool (*get_readonly)(SDState *sd); + + const struct SDProto *proto; }; #define TYPE_SD_BUS "sd-bus" diff --git a/include/hw/ssi/ssi.h b/include/hw/ssi/ssi.h index 6950f86810..3cdcbd5390 100644 --- a/include/hw/ssi/ssi.h +++ b/include/hw/ssi/ssi.h @@ -64,6 +64,9 @@ struct SSIPeripheral { /* Chip select state */ bool cs; + + /* Chip select index */ + uint8_t cs_index; }; extern const VMStateDescription vmstate_ssi_peripheral; @@ -109,4 +112,6 @@ SSIBus *ssi_create_bus(DeviceState *parent, const char *name); uint32_t ssi_transfer(SSIBus *bus, uint32_t val); +DeviceState *ssi_get_cs(SSIBus *bus, uint8_t cs_index); + #endif diff --git a/include/io/channel-socket.h b/include/io/channel-socket.h index 513c428fe4..ab15577d38 100644 --- a/include/io/channel-socket.h +++ b/include/io/channel-socket.h @@ -124,7 +124,7 @@ void qio_channel_socket_connect_async(QIOChannelSocket *ioc, * qio_channel_socket_listen_sync: * @ioc: the socket channel object * @addr: the address to listen to - * @num: the expected ammount of connections + * @num: the expected amount of connections * @errp: pointer to a NULL-initialized error object * * Attempt to listen to the address @addr. This method @@ -141,7 +141,7 @@ int qio_channel_socket_listen_sync(QIOChannelSocket *ioc, * qio_channel_socket_listen_async: * @ioc: the socket channel object * @addr: the address to listen to - * @num: the expected ammount of connections + * @num: the expected amount of connections * @callback: the function to invoke on completion * @opaque: user data to pass to @callback * @destroy: the function to free @opaque diff --git a/include/io/task.h b/include/io/task.h index beec4f5cfd..dc7d32ebd0 100644 --- a/include/io/task.h +++ b/include/io/task.h @@ -145,7 +145,7 @@ typedef void (*QIOTaskWorker)(QIOTask *task, * The QIOTask module can also be used to perform operations * in a background thread context, while still reporting the * results in the main event thread. This allows code which - * cannot easily be rewritten to be asychronous (such as DNS + * cannot easily be rewritten to be asynchronous (such as DNS * lookups) to be easily run non-blocking. Reporting the * results in the main thread context means that the caller * typically does not need to be concerned about thread diff --git a/include/qemu/crc-ccitt.h b/include/qemu/crc-ccitt.h index d6eb49146d..8918dafe07 100644 --- a/include/qemu/crc-ccitt.h +++ b/include/qemu/crc-ccitt.h @@ -17,8 +17,8 @@ extern uint16_t const crc_ccitt_table[256]; extern uint16_t const crc_ccitt_false_table[256]; -extern uint16_t crc_ccitt(uint16_t crc, const uint8_t *buffer, size_t len); -extern uint16_t crc_ccitt_false(uint16_t crc, const uint8_t *buffer, size_t len); +uint16_t crc_ccitt(uint16_t crc, const uint8_t *buffer, size_t len); +uint16_t crc_ccitt_false(uint16_t crc, const uint8_t *buffer, size_t len); static inline uint16_t crc_ccitt_byte(uint16_t crc, const uint8_t c) { diff --git a/include/qemu/fifo8.h b/include/qemu/fifo8.h index 28bf2cee57..16be02f361 100644 --- a/include/qemu/fifo8.h +++ b/include/qemu/fifo8.h @@ -46,7 +46,7 @@ void fifo8_push(Fifo8 *fifo, uint8_t data); * fifo8_push_all: * @fifo: FIFO to push to * @data: data to push - * @size: number of bytes to push + * @num: number of bytes to push * * Push a byte array to the FIFO. Behaviour is undefined if the FIFO is full. * Clients are responsible for checking the space left in the FIFO using diff --git a/include/qemu/host-utils.h b/include/qemu/host-utils.h index 011618373e..ead97d354d 100644 --- a/include/qemu/host-utils.h +++ b/include/qemu/host-utils.h @@ -56,6 +56,11 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) return (__int128_t)a * b / c; } +static inline uint64_t muldiv64_round_up(uint64_t a, uint32_t b, uint32_t c) +{ + return ((__int128_t)a * b + c - 1) / c; +} + static inline uint64_t divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor) { @@ -83,7 +88,8 @@ void mulu64(uint64_t *plow, uint64_t *phigh, uint64_t a, uint64_t b); uint64_t divu128(uint64_t *plow, uint64_t *phigh, uint64_t divisor); int64_t divs128(uint64_t *plow, int64_t *phigh, int64_t divisor); -static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) +static inline uint64_t muldiv64_rounding(uint64_t a, uint32_t b, uint32_t c, + bool round_up) { union { uint64_t ll; @@ -99,12 +105,25 @@ static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) u.ll = a; rl = (uint64_t)u.l.low * (uint64_t)b; + if (round_up) { + rl += c - 1; + } rh = (uint64_t)u.l.high * (uint64_t)b; rh += (rl >> 32); res.l.high = rh / c; res.l.low = (((rh % c) << 32) + (rl & 0xffffffff)) / c; return res.ll; } + +static inline uint64_t muldiv64(uint64_t a, uint32_t b, uint32_t c) +{ + return muldiv64_rounding(a, b, c, false); +} + +static inline uint64_t muldiv64_round_up(uint64_t a, uint32_t b, uint32_t c) +{ + return muldiv64_rounding(a, b, c, true); +} #endif /** diff --git a/include/qemu/iova-tree.h b/include/qemu/iova-tree.h index 8528e5c98f..2a10a7052e 100644 --- a/include/qemu/iova-tree.h +++ b/include/qemu/iova-tree.h @@ -15,7 +15,7 @@ * Currently the iova tree will only allow to keep ranges * information, and no extra user data is allowed for each element. A * benefit is that we can merge adjacent ranges internally within the - * tree. It can save a lot of memory when the ranges are splitted but + * tree. It can save a lot of memory when the ranges are split but * mostly continuous. * * Note that current implementation does not provide any thread @@ -128,7 +128,7 @@ const DMAMap *iova_tree_find_address(const IOVATree *tree, hwaddr iova); * iova_tree_foreach: * * @tree: the iova tree to iterate on - * @iterator: the interator for the mappings, return true to stop + * @iterator: the iterator for the mappings, return true to stop * * Iterate over the iova tree. * diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index 2cae135280..2897720fac 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -250,7 +250,7 @@ extern "C" { * supports QEMU_ERROR, this will be reported at compile time; otherwise * this will be reported at link time due to the missing symbol. */ -G_NORETURN extern +G_NORETURN void QEMU_ERROR("code path is reachable") qemu_build_not_reached_always(void); #if defined(__OPTIMIZE__) && !defined(__NO_INLINE__) @@ -506,7 +506,7 @@ void qemu_anon_ram_free(void *ptr, size_t size); * See MySQL bug #7156 (http://bugs.mysql.com/bug.php?id=7156) for discussion * about Solaris missing the madvise() prototype. */ -extern int madvise(char *, size_t, int); +int madvise(char *, size_t, int); #endif #if defined(CONFIG_LINUX) diff --git a/include/qemu/processor.h b/include/qemu/processor.h index 8e16c9277d..9f0dcdf28f 100644 --- a/include/qemu/processor.h +++ b/include/qemu/processor.h @@ -7,8 +7,6 @@ #ifndef QEMU_PROCESSOR_H #define QEMU_PROCESSOR_H -#include "qemu/atomic.h" - #if defined(__i386__) || defined(__x86_64__) # define cpu_relax() asm volatile("rep; nop" ::: "memory") diff --git a/include/qemu/rcu.h b/include/qemu/rcu.h index 661c1a1468..fea058aa9f 100644 --- a/include/qemu/rcu.h +++ b/include/qemu/rcu.h @@ -118,19 +118,19 @@ static inline void rcu_read_unlock(void) } } -extern void synchronize_rcu(void); +void synchronize_rcu(void); /* * Reader thread registration. */ -extern void rcu_register_thread(void); -extern void rcu_unregister_thread(void); +void rcu_register_thread(void); +void rcu_unregister_thread(void); /* * Support for fork(). fork() support is enabled at startup. */ -extern void rcu_enable_atfork(void); -extern void rcu_disable_atfork(void); +void rcu_enable_atfork(void); +void rcu_disable_atfork(void); struct rcu_head; typedef void RCUCBFunc(struct rcu_head *head); @@ -140,8 +140,8 @@ struct rcu_head { RCUCBFunc *func; }; -extern void call_rcu1(struct rcu_head *head, RCUCBFunc *func); -extern void drain_call_rcu(void); +void call_rcu1(struct rcu_head *head, RCUCBFunc *func); +void drain_call_rcu(void); /* The operands of the minus operator must have the same type, * which must be the one that we specify in the cast. diff --git a/include/qemu/selfmap.h b/include/qemu/selfmap.h index 7d938945cb..1690a74f4b 100644 --- a/include/qemu/selfmap.h +++ b/include/qemu/selfmap.h @@ -20,10 +20,10 @@ typedef struct { bool is_exec; bool is_priv; + dev_t dev; + ino_t inode; uint64_t offset; - uint64_t inode; const char *path; - char dev[]; } MapInfo; /** diff --git a/include/qemu/sys_membarrier.h b/include/qemu/sys_membarrier.h index b5bfa21d52..e7774891f8 100644 --- a/include/qemu/sys_membarrier.h +++ b/include/qemu/sys_membarrier.h @@ -14,8 +14,8 @@ * side. The slow side forces processor-level ordering on all other cores * through a system call. */ -extern void smp_mb_global_init(void); -extern void smp_mb_global(void); +void smp_mb_global_init(void); +void smp_mb_global(void); #define smp_mb_placeholder() barrier() #else /* Keep it simple, execute a real memory barrier on both sides. */ diff --git a/include/qemu/uri.h b/include/qemu/uri.h index b43f35a6a6..1855b764f2 100644 --- a/include/qemu/uri.h +++ b/include/qemu/uri.h @@ -96,8 +96,8 @@ typedef struct QueryParams { QueryParam *p; /* array of parameters */ } QueryParams; -struct QueryParams *query_params_new (int init_alloc); -extern QueryParams *query_params_parse (const char *query); -extern void query_params_free (QueryParams *ps); +QueryParams *query_params_new(int init_alloc); +QueryParams *query_params_parse(const char *query); +void query_params_free(QueryParams *ps); #endif /* QEMU_URI_H */ diff --git a/include/qemu/yank.h b/include/qemu/yank.h index 5375a1f195..1907150933 100644 --- a/include/qemu/yank.h +++ b/include/qemu/yank.h @@ -25,7 +25,7 @@ typedef void (YankFn)(void *opaque); * @instance: The instance. * @errp: Error object. * - * Returns true on success or false if an error occured. + * Returns true on success or false if an error occurred. */ bool yank_register_instance(const YankInstance *instance, Error **errp); diff --git a/include/sysemu/accel-blocker.h b/include/sysemu/accel-blocker.h index 0733783bcc..f07f368358 100644 --- a/include/sysemu/accel-blocker.h +++ b/include/sysemu/accel-blocker.h @@ -16,7 +16,7 @@ #include "sysemu/cpus.h" -extern void accel_blocker_init(void); +void accel_blocker_init(void); /* * accel_{cpu_}ioctl_begin/end: @@ -26,10 +26,10 @@ extern void accel_blocker_init(void); * called, preventing new ioctls to run. They will continue only after * accel_ioctl_inibith_end(). */ -extern void accel_ioctl_begin(void); -extern void accel_ioctl_end(void); -extern void accel_cpu_ioctl_begin(CPUState *cpu); -extern void accel_cpu_ioctl_end(CPUState *cpu); +void accel_ioctl_begin(void); +void accel_ioctl_end(void); +void accel_cpu_ioctl_begin(CPUState *cpu); +void accel_cpu_ioctl_end(CPUState *cpu); /* * accel_ioctl_inhibit_begin: start critical section @@ -42,7 +42,7 @@ extern void accel_cpu_ioctl_end(CPUState *cpu); * This allows the caller to access shared data or perform operations without * worrying of concurrent vcpus accesses. */ -extern void accel_ioctl_inhibit_begin(void); +void accel_ioctl_inhibit_begin(void); /* * accel_ioctl_inhibit_end: end critical section started by @@ -50,6 +50,6 @@ extern void accel_ioctl_inhibit_begin(void); * * This function allows blocked accel_{cpu_}ioctl_begin() to continue. */ -extern void accel_ioctl_inhibit_end(void); +void accel_ioctl_inhibit_end(void); #endif /* ACCEL_BLOCKER_H */ diff --git a/include/sysemu/hax.h b/include/sysemu/hax.h deleted file mode 100644 index 80fc716f80..0000000000 --- a/include/sysemu/hax.h +++ /dev/null @@ -1,49 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright IBM, Corp. 2008 - * - * Authors: - * Anthony Liguori <aliguori@us.ibm.com> - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong<yunhong.jiang@intel.com> - * Xin Xiaohui<xiaohui.xin@intel.com> - * Zhang Xiantao<xiantao.zhang@intel.com> - * - * Copyright 2016 Google, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -/* header to be included in non-HAX-specific code */ - -#ifndef QEMU_HAX_H -#define QEMU_HAX_H - -int hax_sync_vcpus(void); - -#ifdef NEED_CPU_H -# ifdef CONFIG_HAX -# define CONFIG_HAX_IS_POSSIBLE -# endif -#else /* !NEED_CPU_H */ -# define CONFIG_HAX_IS_POSSIBLE -#endif - -#ifdef CONFIG_HAX_IS_POSSIBLE - -extern bool hax_allowed; - -#define hax_enabled() (hax_allowed) - -#else /* !CONFIG_HAX_IS_POSSIBLE */ - -#define hax_enabled() (0) - -#endif /* CONFIG_HAX_IS_POSSIBLE */ - -#endif /* QEMU_HAX_H */ diff --git a/include/sysemu/hw_accel.h b/include/sysemu/hw_accel.h index 22903a55f7..c71b77e71f 100644 --- a/include/sysemu/hw_accel.h +++ b/include/sysemu/hw_accel.h @@ -12,7 +12,6 @@ #define QEMU_HW_ACCEL_H #include "hw/core/cpu.h" -#include "sysemu/hax.h" #include "sysemu/kvm.h" #include "sysemu/hvf.h" #include "sysemu/whpx.h" diff --git a/include/sysemu/os-win32.h b/include/sysemu/os-win32.h index 8ae30fac15..1047d260cb 100644 --- a/include/sysemu/os-win32.h +++ b/include/sysemu/os-win32.h @@ -66,8 +66,8 @@ extern "C" { * setjmp to _setjmpex instead. However, they are still defined in libmingwex.a, * which gets linked automatically. */ -extern int __mingw_setjmp(jmp_buf); -extern void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int); +int __mingw_setjmp(jmp_buf); +void __attribute__((noreturn)) __mingw_longjmp(jmp_buf, int); #define setjmp(env) __mingw_setjmp(env) #define longjmp(env, val) __mingw_longjmp(env, val) #elif defined(_WIN64) diff --git a/include/tcg/helper-info.h b/include/tcg/helper-info.h index 4b6c9b43e8..7c27d6164a 100644 --- a/include/tcg/helper-info.h +++ b/include/tcg/helper-info.h @@ -1,5 +1,5 @@ /* - * TCG Helper Infomation Structure + * TCG Helper Information Structure * * Copyright (c) 2023 Linaro Ltd * diff --git a/include/tcg/tcg.h b/include/tcg/tcg.h index 61d7c81b44..c9c6d770d0 100644 --- a/include/tcg/tcg.h +++ b/include/tcg/tcg.h @@ -879,7 +879,7 @@ enum { /* Instruction operands are 64-bits (otherwise 32-bits). */ TCG_OPF_64BIT = 0x10, /* Instruction is optional and not implemented by the host, or insn - is generic and should not be implemened by the host. */ + is generic and should not be implemented by the host. */ TCG_OPF_NOT_PRESENT = 0x20, /* Instruction operands are vectors. */ TCG_OPF_VECTOR = 0x40, @@ -1123,7 +1123,7 @@ static inline int tcg_can_emit_vec_op(TCGOpcode o, TCGType t, unsigned ve) /* Expand the tuple (opc, type, vece) on the given arguments. */ void tcg_expand_vec_op(TCGOpcode, TCGType, unsigned, TCGArg, ...); -/* Replicate a constant C accoring to the log2 of the element size. */ +/* Replicate a constant C according to the log2 of the element size. */ uint64_t dup_const(unsigned vece, uint64_t c); #define dup_const(VECE, C) \ diff --git a/include/ui/console.h b/include/ui/console.h index 3e8b22d6c6..1ccd432b4d 100644 --- a/include/ui/console.h +++ b/include/ui/console.h @@ -12,6 +12,27 @@ # include "ui/shader.h" #endif +#define TYPE_QEMU_CONSOLE "qemu-console" +OBJECT_DECLARE_TYPE(QemuConsole, QemuConsoleClass, QEMU_CONSOLE) + +#define TYPE_QEMU_GRAPHIC_CONSOLE "qemu-graphic-console" +OBJECT_DECLARE_SIMPLE_TYPE(QemuGraphicConsole, QEMU_GRAPHIC_CONSOLE) + +#define TYPE_QEMU_TEXT_CONSOLE "qemu-text-console" +OBJECT_DECLARE_SIMPLE_TYPE(QemuTextConsole, QEMU_TEXT_CONSOLE) + +#define TYPE_QEMU_FIXED_TEXT_CONSOLE "qemu-fixed-text-console" +OBJECT_DECLARE_SIMPLE_TYPE(QemuFixedTextConsole, QEMU_FIXED_TEXT_CONSOLE) + +#define QEMU_IS_GRAPHIC_CONSOLE(c) \ + object_dynamic_cast(OBJECT(c), TYPE_QEMU_GRAPHIC_CONSOLE) + +#define QEMU_IS_TEXT_CONSOLE(c) \ + object_dynamic_cast(OBJECT(c), TYPE_QEMU_TEXT_CONSOLE) + +#define QEMU_IS_FIXED_TEXT_CONSOLE(c) \ + object_dynamic_cast(OBJECT(c), TYPE_QEMU_FIXED_TEXT_CONSOLE) + /* keyboard/mouse support */ #define MOUSE_EVENT_LBUTTON 0x01 @@ -91,9 +112,9 @@ bool qemu_mouse_set(int index, Error **errp); #define QEMU_KEY_CTRL_PAGEUP 0xe406 #define QEMU_KEY_CTRL_PAGEDOWN 0xe407 -void kbd_put_keysym_console(QemuConsole *s, int keysym); -bool kbd_put_qcode_console(QemuConsole *s, int qcode, bool ctrl); -void kbd_put_string_console(QemuConsole *s, const char *str, int len); +void kbd_put_keysym_console(QemuTextConsole *s, int keysym); +bool kbd_put_qcode_console(QemuTextConsole *s, int qcode, bool ctrl); +void kbd_put_string_console(QemuTextConsole *s, const char *str, int len); void kbd_put_keysym(int keysym); /* Touch devices */ @@ -112,10 +133,6 @@ void console_handle_touch_event(QemuConsole *con, Error **errp); /* consoles */ -#define TYPE_QEMU_CONSOLE "qemu-console" -OBJECT_DECLARE_TYPE(QemuConsole, QemuConsoleClass, QEMU_CONSOLE) - - struct QemuConsoleClass { ObjectClass parent_class; }; @@ -484,7 +501,6 @@ QemuConsole *qemu_console_lookup_by_index(unsigned int index); QemuConsole *qemu_console_lookup_by_device(DeviceState *dev, uint32_t head); QemuConsole *qemu_console_lookup_by_device_name(const char *device_id, uint32_t head, Error **errp); -QemuConsole *qemu_console_lookup_unused(void); QEMUCursor *qemu_console_get_cursor(QemuConsole *con); bool qemu_console_is_visible(QemuConsole *con); bool qemu_console_is_graphic(QemuConsole *con); @@ -504,6 +520,8 @@ void qemu_console_set_window_id(QemuConsole *con, int window_id); void console_select(unsigned int index); void qemu_console_resize(QemuConsole *con, int width, int height); DisplaySurface *qemu_console_surface(QemuConsole *con); +void coroutine_fn qemu_console_co_wait_update(QemuConsole *con); +int qemu_invalidate_text_consoles(void); /* console-gl.c */ #ifdef CONFIG_OPENGL diff --git a/include/ui/kbd-state.h b/include/ui/kbd-state.h index eb9067dd53..fb79776128 100644 --- a/include/ui/kbd-state.h +++ b/include/ui/kbd-state.h @@ -65,7 +65,7 @@ void qkbd_state_key_event(QKbdState *kbd, QKeyCode qcode, bool down); * using qemu_input_event_send_key_delay(). * * @kbd: state tracker state. - * @delay_ms: the delay in miliseconds. + * @delay_ms: the delay in milliseconds. */ void qkbd_state_set_delay(QKbdState *kbd, int delay_ms); diff --git a/include/ui/qemu-pixman.h b/include/ui/qemu-pixman.h index 0c775604d1..51f8709327 100644 --- a/include/ui/qemu-pixman.h +++ b/include/ui/qemu-pixman.h @@ -47,6 +47,12 @@ # define PIXMAN_LE_x8r8g8b8 PIXMAN_x8r8g8b8 #endif +#define QEMU_PIXMAN_COLOR(r, g, b) \ + { .red = r << 8, .green = g << 8, .blue = b << 8, .alpha = 0xffff } + +#define QEMU_PIXMAN_COLOR_BLACK QEMU_PIXMAN_COLOR(0x00, 0x00, 0x00) +#define QEMU_PIXMAN_COLOR_GRAY QEMU_PIXMAN_COLOR(0xaa, 0xaa, 0xaa) + /* -------------------------------------------------------------------- */ typedef struct PixelFormat { @@ -72,13 +78,10 @@ pixman_image_t *qemu_pixman_linebuf_create(pixman_format_code_t format, int width); void qemu_pixman_linebuf_fill(pixman_image_t *linebuf, pixman_image_t *fb, int width, int x, int y); -void qemu_pixman_linebuf_copy(pixman_image_t *fb, int width, int x, int y, - pixman_image_t *linebuf); pixman_image_t *qemu_pixman_mirror_create(pixman_format_code_t format, pixman_image_t *image); void qemu_pixman_image_unref(pixman_image_t *image); -pixman_color_t qemu_pixman_color(PixelFormat *pf, uint32_t color); pixman_image_t *qemu_pixman_glyph_from_vgafont(int height, const uint8_t *font, unsigned int ch); void qemu_pixman_glyph_render(pixman_image_t *glyph, diff --git a/include/ui/spice-display.h b/include/ui/spice-display.h index 5aa13664d6..e1a9b36185 100644 --- a/include/ui/spice-display.h +++ b/include/ui/spice-display.h @@ -42,7 +42,7 @@ #define NUM_MEMSLOTS_GROUPS 2 /* - * Internal enum to differenciate between options for + * Internal enum to differentiate between options for * io calls that have a sync (old) version and an _async (new) * version: * QXL_SYNC: use the old version diff --git a/include/user/safe-syscall.h b/include/user/safe-syscall.h index ddceef12e2..27b71cdbd8 100644 --- a/include/user/safe-syscall.h +++ b/include/user/safe-syscall.h @@ -91,7 +91,7 @@ * * The basic setup is that we make the host syscall via a known * section of host native assembly. If a signal occurs, our signal - * handler checks the interrupted host PC against the addresse of that + * handler checks the interrupted host PC against the address of that * known section. If the PC is before or at the address of the syscall * instruction then we change the PC to point at a "return * -QEMU_ERESTARTSYS" code path instead, and then exit the signal handler @@ -126,8 +126,8 @@ */ /* The core part of this function is implemented in assembly */ -extern long safe_syscall_base(int *pending, long number, ...); -extern long safe_syscall_set_errno_tail(int value); +long safe_syscall_base(int *pending, long number, ...); +long safe_syscall_set_errno_tail(int value); /* These are defined by the safe-syscall.inc.S file */ extern char safe_syscall_start[]; diff --git a/linux-user/aarch64/target_proc.h b/linux-user/aarch64/target_proc.h new file mode 100644 index 0000000000..907df4dcd2 --- /dev/null +++ b/linux-user/aarch64/target_proc.h @@ -0,0 +1 @@ +#include "../arm/target_proc.h" diff --git a/linux-user/alpha/target_proc.h b/linux-user/alpha/target_proc.h new file mode 100644 index 0000000000..dac37dffc9 --- /dev/null +++ b/linux-user/alpha/target_proc.h @@ -0,0 +1,67 @@ +/* + * Alpha specific proc functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ALPHA_TARGET_PROC_H +#define ALPHA_TARGET_PROC_H + +static int open_cpuinfo(CPUArchState *cpu_env, int fd) +{ + int max_cpus = sysconf(_SC_NPROCESSORS_CONF); + int num_cpus = sysconf(_SC_NPROCESSORS_ONLN); + unsigned long cpu_mask; + char model[32]; + const char *p, *q; + int t; + + p = object_class_get_name(OBJECT_CLASS(CPU_GET_CLASS(env_cpu(cpu_env)))); + q = strchr(p, '-'); + t = q - p; + assert(t < sizeof(model)); + memcpy(model, p, t); + model[t] = 0; + + t = sched_getaffinity(getpid(), sizeof(cpu_mask), (cpu_set_t *)&cpu_mask); + if (t < 0) { + if (num_cpus >= sizeof(cpu_mask) * 8) { + cpu_mask = -1; + } else { + cpu_mask = (1UL << num_cpus) - 1; + } + } + + dprintf(fd, + "cpu\t\t\t: Alpha\n" + "cpu model\t\t: %s\n" + "cpu variation\t\t: 0\n" + "cpu revision\t\t: 0\n" + "cpu serial number\t: JA00000000\n" + "system type\t\t: QEMU\n" + "system variation\t: QEMU_v" QEMU_VERSION "\n" + "system revision\t\t: 0\n" + "system serial number\t: AY00000000\n" + "cycle frequency [Hz]\t: 250000000\n" + "timer frequency [Hz]\t: 250.00\n" + "page size [bytes]\t: %d\n" + "phys. address bits\t: %d\n" + "max. addr. space #\t: 255\n" + "BogoMIPS\t\t: 2500.00\n" + "kernel unaligned acc\t: 0 (pc=0,va=0)\n" + "user unaligned acc\t: 0 (pc=0,va=0)\n" + "platform string\t\t: AlphaServer QEMU user-mode VM\n" + "cpus detected\t\t: %d\n" + "cpus active\t\t: %d\n" + "cpu active mask\t\t: %016lx\n" + "L1 Icache\t\t: n/a\n" + "L1 Dcache\t\t: n/a\n" + "L2 cache\t\t: n/a\n" + "L3 cache\t\t: n/a\n", + model, TARGET_PAGE_SIZE, TARGET_PHYS_ADDR_SPACE_BITS, + max_cpus, num_cpus, cpu_mask); + + return 0; +} +#define HAVE_ARCH_PROC_CPUINFO + +#endif /* ALPHA_TARGET_PROC_H */ diff --git a/linux-user/arm/target_proc.h b/linux-user/arm/target_proc.h new file mode 100644 index 0000000000..ac75af9ca6 --- /dev/null +++ b/linux-user/arm/target_proc.h @@ -0,0 +1,101 @@ +/* + * Arm specific proc functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef ARM_TARGET_PROC_H +#define ARM_TARGET_PROC_H + +static int open_cpuinfo(CPUArchState *cpu_env, int fd) +{ + ARMCPU *cpu = env_archcpu(cpu_env); + int arch, midr_rev, midr_part, midr_var, midr_impl; + target_ulong elf_hwcap = get_elf_hwcap(); + target_ulong elf_hwcap2 = get_elf_hwcap2(); + const char *elf_name; + int num_cpus, len_part, len_var; + +#if TARGET_BIG_ENDIAN +# define END_SUFFIX "b" +#else +# define END_SUFFIX "l" +#endif + + arch = 8; + elf_name = "v8" END_SUFFIX; + midr_rev = FIELD_EX32(cpu->midr, MIDR_EL1, REVISION); + midr_part = FIELD_EX32(cpu->midr, MIDR_EL1, PARTNUM); + midr_var = FIELD_EX32(cpu->midr, MIDR_EL1, VARIANT); + midr_impl = FIELD_EX32(cpu->midr, MIDR_EL1, IMPLEMENTER); + len_part = 3; + len_var = 1; + +#ifndef TARGET_AARCH64 + /* For simplicity, treat ARMv8 as an arm64 kernel with CONFIG_COMPAT. */ + if (!arm_feature(&cpu->env, ARM_FEATURE_V8)) { + if (arm_feature(&cpu->env, ARM_FEATURE_V7)) { + arch = 7; + midr_var = (cpu->midr >> 16) & 0x7f; + len_var = 2; + if (arm_feature(&cpu->env, ARM_FEATURE_M)) { + elf_name = "armv7m" END_SUFFIX; + } else { + elf_name = "armv7" END_SUFFIX; + } + } else { + midr_part = cpu->midr >> 4; + len_part = 7; + if (arm_feature(&cpu->env, ARM_FEATURE_V6)) { + arch = 6; + elf_name = "armv6" END_SUFFIX; + } else if (arm_feature(&cpu->env, ARM_FEATURE_V5)) { + arch = 5; + elf_name = "armv5t" END_SUFFIX; + } else { + arch = 4; + elf_name = "armv4" END_SUFFIX; + } + } + } +#endif + +#undef END_SUFFIX + + num_cpus = sysconf(_SC_NPROCESSORS_ONLN); + for (int i = 0; i < num_cpus; i++) { + dprintf(fd, + "processor\t: %d\n" + "model name\t: ARMv%d Processor rev %d (%s)\n" + "BogoMIPS\t: 100.00\n" + "Features\t:", + i, arch, midr_rev, elf_name); + + for (target_ulong j = elf_hwcap; j ; j &= j - 1) { + dprintf(fd, " %s", elf_hwcap_str(ctz64(j))); + } + for (target_ulong j = elf_hwcap2; j ; j &= j - 1) { + dprintf(fd, " %s", elf_hwcap2_str(ctz64(j))); + } + + dprintf(fd, "\n" + "CPU implementer\t: 0x%02x\n" + "CPU architecture: %d\n" + "CPU variant\t: 0x%0*x\n", + midr_impl, arch, len_var, midr_var); + if (arch >= 7) { + dprintf(fd, "CPU part\t: 0x%0*x\n", len_part, midr_part); + } + dprintf(fd, "CPU revision\t: %d\n\n", midr_rev); + } + + if (arch < 8) { + dprintf(fd, "Hardware\t: QEMU v%s %s\n", QEMU_VERSION, + cpu->dtb_compatible ? : ""); + dprintf(fd, "Revision\t: 0000\n"); + dprintf(fd, "Serial\t\t: 0000000000000000\n"); + } + return 0; +} +#define HAVE_ARCH_PROC_CPUINFO + +#endif /* ARM_TARGET_PROC_H */ diff --git a/linux-user/cris/target_proc.h b/linux-user/cris/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/cris/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 92b981c445..a5b28fa3e7 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -143,8 +143,6 @@ static uint32_t get_elf_hwcap(void) } #ifdef TARGET_X86_64 -#define ELF_START_MMAP 0x2aaaaab000ULL - #define ELF_CLASS ELFCLASS64 #define ELF_ARCH EM_X86_64 @@ -221,8 +219,6 @@ static bool init_guest_commpage(void) #endif #else -#define ELF_START_MMAP 0x80000000 - /* * This is used to ensure we don't load something for the wrong architecture. */ @@ -308,8 +304,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUX86State *en #ifndef TARGET_AARCH64 /* 32 bit ARM definitions */ -#define ELF_START_MMAP 0x80000000 - #define ELF_ARCH EM_ARM #define ELF_CLASS ELFCLASS32 #define EXSTACK_DEFAULT true @@ -466,7 +460,7 @@ static bool init_guest_commpage(void) #define ELF_HWCAP get_elf_hwcap() #define ELF_HWCAP2 get_elf_hwcap2() -static uint32_t get_elf_hwcap(void) +uint32_t get_elf_hwcap(void) { ARMCPU *cpu = ARM_CPU(thread_cpu); uint32_t hwcaps = 0; @@ -508,7 +502,7 @@ static uint32_t get_elf_hwcap(void) return hwcaps; } -static uint32_t get_elf_hwcap2(void) +uint32_t get_elf_hwcap2(void) { ARMCPU *cpu = ARM_CPU(thread_cpu); uint32_t hwcaps = 0; @@ -521,6 +515,49 @@ static uint32_t get_elf_hwcap2(void) return hwcaps; } +const char *elf_hwcap_str(uint32_t bit) +{ + static const char *hwcap_str[] = { + [__builtin_ctz(ARM_HWCAP_ARM_SWP )] = "swp", + [__builtin_ctz(ARM_HWCAP_ARM_HALF )] = "half", + [__builtin_ctz(ARM_HWCAP_ARM_THUMB )] = "thumb", + [__builtin_ctz(ARM_HWCAP_ARM_26BIT )] = "26bit", + [__builtin_ctz(ARM_HWCAP_ARM_FAST_MULT)] = "fast_mult", + [__builtin_ctz(ARM_HWCAP_ARM_FPA )] = "fpa", + [__builtin_ctz(ARM_HWCAP_ARM_VFP )] = "vfp", + [__builtin_ctz(ARM_HWCAP_ARM_EDSP )] = "edsp", + [__builtin_ctz(ARM_HWCAP_ARM_JAVA )] = "java", + [__builtin_ctz(ARM_HWCAP_ARM_IWMMXT )] = "iwmmxt", + [__builtin_ctz(ARM_HWCAP_ARM_CRUNCH )] = "crunch", + [__builtin_ctz(ARM_HWCAP_ARM_THUMBEE )] = "thumbee", + [__builtin_ctz(ARM_HWCAP_ARM_NEON )] = "neon", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv3 )] = "vfpv3", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv3D16 )] = "vfpv3d16", + [__builtin_ctz(ARM_HWCAP_ARM_TLS )] = "tls", + [__builtin_ctz(ARM_HWCAP_ARM_VFPv4 )] = "vfpv4", + [__builtin_ctz(ARM_HWCAP_ARM_IDIVA )] = "idiva", + [__builtin_ctz(ARM_HWCAP_ARM_IDIVT )] = "idivt", + [__builtin_ctz(ARM_HWCAP_ARM_VFPD32 )] = "vfpd32", + [__builtin_ctz(ARM_HWCAP_ARM_LPAE )] = "lpae", + [__builtin_ctz(ARM_HWCAP_ARM_EVTSTRM )] = "evtstrm", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + +const char *elf_hwcap2_str(uint32_t bit) +{ + static const char *hwcap_str[] = { + [__builtin_ctz(ARM_HWCAP2_ARM_AES )] = "aes", + [__builtin_ctz(ARM_HWCAP2_ARM_PMULL)] = "pmull", + [__builtin_ctz(ARM_HWCAP2_ARM_SHA1 )] = "sha1", + [__builtin_ctz(ARM_HWCAP2_ARM_SHA2 )] = "sha2", + [__builtin_ctz(ARM_HWCAP2_ARM_CRC32)] = "crc32", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + #undef GET_FEATURE #undef GET_FEATURE_ID @@ -557,7 +594,6 @@ static const char *get_elf_platform(void) #else /* 64 bit ARM definitions */ -#define ELF_START_MMAP 0x80000000 #define ELF_ARCH EM_AARCH64 #define ELF_CLASS ELFCLASS64 @@ -668,7 +704,7 @@ enum { #define GET_FEATURE_ID(feat, hwcap) \ do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0) -static uint32_t get_elf_hwcap(void) +uint32_t get_elf_hwcap(void) { ARMCPU *cpu = ARM_CPU(thread_cpu); uint32_t hwcaps = 0; @@ -706,7 +742,7 @@ static uint32_t get_elf_hwcap(void) return hwcaps; } -static uint32_t get_elf_hwcap2(void) +uint32_t get_elf_hwcap2(void) { ARMCPU *cpu = ARM_CPU(thread_cpu); uint32_t hwcaps = 0; @@ -741,6 +777,85 @@ static uint32_t get_elf_hwcap2(void) return hwcaps; } +const char *elf_hwcap_str(uint32_t bit) +{ + static const char *hwcap_str[] = { + [__builtin_ctz(ARM_HWCAP_A64_FP )] = "fp", + [__builtin_ctz(ARM_HWCAP_A64_ASIMD )] = "asimd", + [__builtin_ctz(ARM_HWCAP_A64_EVTSTRM )] = "evtstrm", + [__builtin_ctz(ARM_HWCAP_A64_AES )] = "aes", + [__builtin_ctz(ARM_HWCAP_A64_PMULL )] = "pmull", + [__builtin_ctz(ARM_HWCAP_A64_SHA1 )] = "sha1", + [__builtin_ctz(ARM_HWCAP_A64_SHA2 )] = "sha2", + [__builtin_ctz(ARM_HWCAP_A64_CRC32 )] = "crc32", + [__builtin_ctz(ARM_HWCAP_A64_ATOMICS )] = "atomics", + [__builtin_ctz(ARM_HWCAP_A64_FPHP )] = "fphp", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDHP )] = "asimdhp", + [__builtin_ctz(ARM_HWCAP_A64_CPUID )] = "cpuid", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDRDM)] = "asimdrdm", + [__builtin_ctz(ARM_HWCAP_A64_JSCVT )] = "jscvt", + [__builtin_ctz(ARM_HWCAP_A64_FCMA )] = "fcma", + [__builtin_ctz(ARM_HWCAP_A64_LRCPC )] = "lrcpc", + [__builtin_ctz(ARM_HWCAP_A64_DCPOP )] = "dcpop", + [__builtin_ctz(ARM_HWCAP_A64_SHA3 )] = "sha3", + [__builtin_ctz(ARM_HWCAP_A64_SM3 )] = "sm3", + [__builtin_ctz(ARM_HWCAP_A64_SM4 )] = "sm4", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDDP )] = "asimddp", + [__builtin_ctz(ARM_HWCAP_A64_SHA512 )] = "sha512", + [__builtin_ctz(ARM_HWCAP_A64_SVE )] = "sve", + [__builtin_ctz(ARM_HWCAP_A64_ASIMDFHM)] = "asimdfhm", + [__builtin_ctz(ARM_HWCAP_A64_DIT )] = "dit", + [__builtin_ctz(ARM_HWCAP_A64_USCAT )] = "uscat", + [__builtin_ctz(ARM_HWCAP_A64_ILRCPC )] = "ilrcpc", + [__builtin_ctz(ARM_HWCAP_A64_FLAGM )] = "flagm", + [__builtin_ctz(ARM_HWCAP_A64_SSBS )] = "ssbs", + [__builtin_ctz(ARM_HWCAP_A64_SB )] = "sb", + [__builtin_ctz(ARM_HWCAP_A64_PACA )] = "paca", + [__builtin_ctz(ARM_HWCAP_A64_PACG )] = "pacg", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + +const char *elf_hwcap2_str(uint32_t bit) +{ + static const char *hwcap_str[] = { + [__builtin_ctz(ARM_HWCAP2_A64_DCPODP )] = "dcpodp", + [__builtin_ctz(ARM_HWCAP2_A64_SVE2 )] = "sve2", + [__builtin_ctz(ARM_HWCAP2_A64_SVEAES )] = "sveaes", + [__builtin_ctz(ARM_HWCAP2_A64_SVEPMULL )] = "svepmull", + [__builtin_ctz(ARM_HWCAP2_A64_SVEBITPERM )] = "svebitperm", + [__builtin_ctz(ARM_HWCAP2_A64_SVESHA3 )] = "svesha3", + [__builtin_ctz(ARM_HWCAP2_A64_SVESM4 )] = "svesm4", + [__builtin_ctz(ARM_HWCAP2_A64_FLAGM2 )] = "flagm2", + [__builtin_ctz(ARM_HWCAP2_A64_FRINT )] = "frint", + [__builtin_ctz(ARM_HWCAP2_A64_SVEI8MM )] = "svei8mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEF32MM )] = "svef32mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEF64MM )] = "svef64mm", + [__builtin_ctz(ARM_HWCAP2_A64_SVEBF16 )] = "svebf16", + [__builtin_ctz(ARM_HWCAP2_A64_I8MM )] = "i8mm", + [__builtin_ctz(ARM_HWCAP2_A64_BF16 )] = "bf16", + [__builtin_ctz(ARM_HWCAP2_A64_DGH )] = "dgh", + [__builtin_ctz(ARM_HWCAP2_A64_RNG )] = "rng", + [__builtin_ctz(ARM_HWCAP2_A64_BTI )] = "bti", + [__builtin_ctz(ARM_HWCAP2_A64_MTE )] = "mte", + [__builtin_ctz(ARM_HWCAP2_A64_ECV )] = "ecv", + [__builtin_ctz(ARM_HWCAP2_A64_AFP )] = "afp", + [__builtin_ctz(ARM_HWCAP2_A64_RPRES )] = "rpres", + [__builtin_ctz(ARM_HWCAP2_A64_MTE3 )] = "mte3", + [__builtin_ctz(ARM_HWCAP2_A64_SME )] = "sme", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I16I64 )] = "sme_i16i64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F64F64 )] = "sme_f64f64", + [__builtin_ctz(ARM_HWCAP2_A64_SME_I8I32 )] = "sme_i8i32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F16F32 )] = "sme_f16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_B16F32 )] = "sme_b16f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_F32F32 )] = "sme_f32f32", + [__builtin_ctz(ARM_HWCAP2_A64_SME_FA64 )] = "sme_fa64", + }; + + return bit < ARRAY_SIZE(hwcap_str) ? hwcap_str[bit] : NULL; +} + #undef GET_FEATURE_ID #endif /* not TARGET_AARCH64 */ @@ -749,7 +864,6 @@ static uint32_t get_elf_hwcap2(void) #ifdef TARGET_SPARC #ifdef TARGET_SPARC64 -#define ELF_START_MMAP 0x80000000 #define ELF_HWCAP (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | HWCAP_SPARC_SWAP \ | HWCAP_SPARC_MULDIV | HWCAP_SPARC_V9) #ifndef TARGET_ABI32 @@ -761,7 +875,6 @@ static uint32_t get_elf_hwcap2(void) #define ELF_CLASS ELFCLASS64 #define ELF_ARCH EM_SPARCV9 #else -#define ELF_START_MMAP 0x80000000 #define ELF_HWCAP (HWCAP_SPARC_FLUSH | HWCAP_SPARC_STBAR | HWCAP_SPARC_SWAP \ | HWCAP_SPARC_MULDIV) #define ELF_CLASS ELFCLASS32 @@ -783,7 +896,6 @@ static inline void init_thread(struct target_pt_regs *regs, #ifdef TARGET_PPC #define ELF_MACHINE PPC_ELF_MACHINE -#define ELF_START_MMAP 0x80000000 #if defined(TARGET_PPC64) @@ -986,8 +1098,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUPPCState *en #ifdef TARGET_LOONGARCH64 -#define ELF_START_MMAP 0x80000000 - #define ELF_CLASS ELFCLASS64 #define ELF_ARCH EM_LOONGARCH #define EXSTACK_DEFAULT true @@ -1078,8 +1188,6 @@ static uint32_t get_elf_hwcap(void) #ifdef TARGET_MIPS -#define ELF_START_MMAP 0x80000000 - #ifdef TARGET_MIPS64 #define ELF_CLASS ELFCLASS64 #else @@ -1237,8 +1345,6 @@ static uint32_t get_elf_hwcap(void) #ifdef TARGET_MICROBLAZE -#define ELF_START_MMAP 0x80000000 - #define elf_check_arch(x) ( (x) == EM_MICROBLAZE || (x) == EM_MICROBLAZE_OLD) #define ELF_CLASS ELFCLASS32 @@ -1279,8 +1385,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUMBState *env #ifdef TARGET_NIOS2 -#define ELF_START_MMAP 0x80000000 - #define elf_check_arch(x) ((x) == EM_ALTERA_NIOS2) #define ELF_CLASS ELFCLASS32 @@ -1376,8 +1480,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, #ifdef TARGET_OPENRISC -#define ELF_START_MMAP 0x08000000 - #define ELF_ARCH EM_OPENRISC #define ELF_CLASS ELFCLASS32 #define ELF_DATA ELFDATA2MSB @@ -1414,8 +1516,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, #ifdef TARGET_SH4 -#define ELF_START_MMAP 0x80000000 - #define ELF_CLASS ELFCLASS32 #define ELF_ARCH EM_SH @@ -1496,8 +1596,6 @@ static uint32_t get_elf_hwcap(void) #ifdef TARGET_CRIS -#define ELF_START_MMAP 0x80000000 - #define ELF_CLASS ELFCLASS32 #define ELF_ARCH EM_CRIS @@ -1513,8 +1611,6 @@ static inline void init_thread(struct target_pt_regs *regs, #ifdef TARGET_M68K -#define ELF_START_MMAP 0x80000000 - #define ELF_CLASS ELFCLASS32 #define ELF_ARCH EM_68K @@ -1564,8 +1660,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, const CPUM68KState *e #ifdef TARGET_ALPHA -#define ELF_START_MMAP (0x30000000000ULL) - #define ELF_CLASS ELFCLASS64 #define ELF_ARCH EM_ALPHA @@ -1583,8 +1677,6 @@ static inline void init_thread(struct target_pt_regs *regs, #ifdef TARGET_S390X -#define ELF_START_MMAP (0x20000000000ULL) - #define ELF_CLASS ELFCLASS64 #define ELF_DATA ELFDATA2MSB #define ELF_ARCH EM_S390 @@ -1695,7 +1787,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, #ifdef TARGET_RISCV -#define ELF_START_MMAP 0x80000000 #define ELF_ARCH EM_RISCV #ifdef TARGET_RISCV32 @@ -1731,7 +1822,6 @@ static inline void init_thread(struct target_pt_regs *regs, #ifdef TARGET_HPPA -#define ELF_START_MMAP 0x80000000 #define ELF_CLASS ELFCLASS32 #define ELF_ARCH EM_PARISC #define ELF_PLATFORM "PARISC" @@ -1783,8 +1873,6 @@ static bool init_guest_commpage(void) #ifdef TARGET_XTENSA -#define ELF_START_MMAP 0x20000000 - #define ELF_CLASS ELFCLASS32 #define ELF_ARCH EM_XTENSA @@ -1850,8 +1938,6 @@ static void elf_core_copy_regs(target_elf_gregset_t *regs, #ifdef TARGET_HEXAGON -#define ELF_START_MMAP 0x20000000 - #define ELF_CLASS ELFCLASS32 #define ELF_ARCH EM_HEXAGON @@ -3205,7 +3291,7 @@ static void load_elf_image(const char *image_name, int image_fd, info->start_data = -1; info->end_data = 0; /* Usual start for brk is after all sections of the main executable. */ - info->brk = TARGET_PAGE_ALIGN(hiaddr); + info->brk = TARGET_PAGE_ALIGN(hiaddr + load_bias); info->elf_flags = ehdr->e_flags; prot_exec = PROT_EXEC; @@ -3568,8 +3654,6 @@ int load_elf_binary(struct linux_binprm *bprm, struct image_info *info) interp_info.fp_abi = MIPS_ABI_FP_UNKNOWN; #endif - info->start_mmap = (abi_ulong)ELF_START_MMAP; - load_elf_image(bprm->filename, bprm->fd, info, &elf_interpreter, bprm->buf); diff --git a/linux-user/flatload.c b/linux-user/flatload.c index 8f5e9f489b..4331a11bf0 100644 --- a/linux-user/flatload.c +++ b/linux-user/flatload.c @@ -780,7 +780,7 @@ int load_flt_binary(struct linux_binprm *bprm, struct image_info *info) /* Enforce final stack alignment of 16 bytes. This is sufficient for all current targets, and excess alignment is harmless. */ stack_len = bprm->envc + bprm->argc + 2; - stack_len += flat_argvp_envp_on_stack() ? 2 : 0; /* arvg, argp */ + stack_len += flat_argvp_envp_on_stack() ? 2 : 0; /* argv, argp */ stack_len += 1; /* argc */ stack_len *= sizeof(abi_ulong); sp -= (sp - stack_len) & 15; diff --git a/linux-user/hexagon/target_proc.h b/linux-user/hexagon/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/hexagon/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/hppa/target_proc.h b/linux-user/hppa/target_proc.h new file mode 100644 index 0000000000..9340c3b6af --- /dev/null +++ b/linux-user/hppa/target_proc.h @@ -0,0 +1,26 @@ +/* + * HPPA specific proc functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef HPPA_TARGET_PROC_H +#define HPPA_TARGET_PROC_H + +static int open_cpuinfo(CPUArchState *cpu_env, int fd) +{ + int i, num_cpus; + + num_cpus = sysconf(_SC_NPROCESSORS_ONLN); + for (i = 0; i < num_cpus; i++) { + dprintf(fd, "processor\t: %d\n", i); + dprintf(fd, "cpu family\t: PA-RISC 1.1e\n"); + dprintf(fd, "cpu\t\t: PA7300LC (PCX-L2)\n"); + dprintf(fd, "capabilities\t: os32\n"); + dprintf(fd, "model\t\t: 9000/778/B160L - " + "Merlin L2 160 QEMU (9000/778/B160L)\n\n"); + } + return 0; +} +#define HAVE_ARCH_PROC_CPUINFO + +#endif /* HPPA_TARGET_PROC_H */ diff --git a/linux-user/i386/target_proc.h b/linux-user/i386/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/i386/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/loader.h b/linux-user/loader.h index 59cbeacf24..324e5c872a 100644 --- a/linux-user/loader.h +++ b/linux-user/loader.h @@ -56,9 +56,13 @@ abi_long memcpy_to_target(abi_ulong dest, const void *src, extern unsigned long guest_stack_size; -#ifdef TARGET_S390X +#if defined(TARGET_S390X) || defined(TARGET_AARCH64) || defined(TARGET_ARM) uint32_t get_elf_hwcap(void); const char *elf_hwcap_str(uint32_t bit); #endif +#if defined(TARGET_AARCH64) || defined(TARGET_ARM) +uint32_t get_elf_hwcap2(void); +const char *elf_hwcap2_str(uint32_t bit); +#endif #endif /* LINUX_USER_LOADER_H */ diff --git a/linux-user/loongarch64/target_proc.h b/linux-user/loongarch64/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/loongarch64/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/m68k/target_proc.h b/linux-user/m68k/target_proc.h new file mode 100644 index 0000000000..3df8f28e22 --- /dev/null +++ b/linux-user/m68k/target_proc.h @@ -0,0 +1,16 @@ +/* + * M68K specific proc functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef M68K_TARGET_PROC_H +#define M68K_TARGET_PROC_H + +static int open_hardware(CPUArchState *cpu_env, int fd) +{ + dprintf(fd, "Model:\t\tqemu-m68k\n"); + return 0; +} +#define HAVE_ARCH_PROC_HARDWARE + +#endif /* M68K_TARGET_PROC_H */ diff --git a/linux-user/microblaze/target_proc.h b/linux-user/microblaze/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/microblaze/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/mips/target_proc.h b/linux-user/mips/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/mips/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/mips64/target_proc.h b/linux-user/mips64/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/mips64/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/mmap.c b/linux-user/mmap.c index 9aab48d4a3..8eaf57b208 100644 --- a/linux-user/mmap.c +++ b/linux-user/mmap.c @@ -17,12 +17,14 @@ * along with this program; if not, see <http://www.gnu.org/licenses/>. */ #include "qemu/osdep.h" +#include <sys/shm.h> #include "trace.h" #include "exec/log.h" #include "qemu.h" #include "user-internals.h" #include "user-mmap.h" #include "target_mman.h" +#include "qemu/interval-tree.h" static pthread_mutex_t mmap_mutex = PTHREAD_MUTEX_INITIALIZER; static __thread int mmap_lock_count; @@ -64,6 +66,44 @@ void mmap_fork_end(int child) } } +/* Protected by mmap_lock. */ +static IntervalTreeRoot shm_regions; + +static void shm_region_add(abi_ptr start, abi_ptr last) +{ + IntervalTreeNode *i = g_new0(IntervalTreeNode, 1); + + i->start = start; + i->last = last; + interval_tree_insert(i, &shm_regions); +} + +static abi_ptr shm_region_find(abi_ptr start) +{ + IntervalTreeNode *i; + + for (i = interval_tree_iter_first(&shm_regions, start, start); i; + i = interval_tree_iter_next(i, start, start)) { + if (i->start == start) { + return i->last; + } + } + return 0; +} + +static void shm_region_rm_complete(abi_ptr start, abi_ptr last) +{ + IntervalTreeNode *i, *n; + + for (i = interval_tree_iter_first(&shm_regions, start, last); i; i = n) { + n = interval_tree_iter_next(i, start, last); + if (i->start >= start && i->last <= last) { + interval_tree_remove(i, &shm_regions); + g_free(i); + } + } +} + /* * Validate target prot bitmask. * Return the prot bitmask for the host in *HOST_PROT. @@ -720,6 +760,7 @@ abi_long target_mmap(abi_ulong start, abi_ulong len, int target_prot, page_set_flags(passthrough_last + 1, last, page_flags); } } + shm_region_rm_complete(start, last); the_end: trace_target_mmap_complete(start); if (qemu_loglevel_mask(CPU_LOG_PAGE)) { @@ -817,6 +858,7 @@ int target_munmap(abi_ulong start, abi_ulong len) mmap_lock(); mmap_reserve_or_unmap(start, len); page_set_flags(start, start + len - 1, 0); + shm_region_rm_complete(start, start + len - 1); mmap_unlock(); return 0; @@ -906,8 +948,10 @@ abi_long target_mremap(abi_ulong old_addr, abi_ulong old_size, new_addr = h2g(host_addr); prot = page_get_flags(old_addr); page_set_flags(old_addr, old_addr + old_size - 1, 0); + shm_region_rm_complete(old_addr, old_addr + old_size - 1); page_set_flags(new_addr, new_addr + new_size - 1, prot | PAGE_VALID | PAGE_RESET); + shm_region_rm_complete(new_addr, new_addr + new_size - 1); } mmap_unlock(); return new_addr; @@ -981,3 +1025,127 @@ abi_long target_madvise(abi_ulong start, abi_ulong len_in, int advice) return ret; } + +#ifndef TARGET_FORCE_SHMLBA +/* + * For most architectures, SHMLBA is the same as the page size; + * some architectures have larger values, in which case they should + * define TARGET_FORCE_SHMLBA and provide a target_shmlba() function. + * This corresponds to the kernel arch code defining __ARCH_FORCE_SHMLBA + * and defining its own value for SHMLBA. + * + * The kernel also permits SHMLBA to be set by the architecture to a + * value larger than the page size without setting __ARCH_FORCE_SHMLBA; + * this means that addresses are rounded to the large size if + * SHM_RND is set but addresses not aligned to that size are not rejected + * as long as they are at least page-aligned. Since the only architecture + * which uses this is ia64 this code doesn't provide for that oddity. + */ +static inline abi_ulong target_shmlba(CPUArchState *cpu_env) +{ + return TARGET_PAGE_SIZE; +} +#endif + +abi_ulong target_shmat(CPUArchState *cpu_env, int shmid, + abi_ulong shmaddr, int shmflg) +{ + CPUState *cpu = env_cpu(cpu_env); + abi_ulong raddr; + struct shmid_ds shm_info; + int ret; + abi_ulong shmlba; + + /* shmat pointers are always untagged */ + + /* find out the length of the shared memory segment */ + ret = get_errno(shmctl(shmid, IPC_STAT, &shm_info)); + if (is_error(ret)) { + /* can't get length, bail out */ + return ret; + } + + shmlba = target_shmlba(cpu_env); + + if (shmaddr & (shmlba - 1)) { + if (shmflg & SHM_RND) { + shmaddr &= ~(shmlba - 1); + } else { + return -TARGET_EINVAL; + } + } + if (!guest_range_valid_untagged(shmaddr, shm_info.shm_segsz)) { + return -TARGET_EINVAL; + } + + WITH_MMAP_LOCK_GUARD() { + void *host_raddr; + abi_ulong last; + + if (shmaddr) { + host_raddr = shmat(shmid, (void *)g2h_untagged(shmaddr), shmflg); + } else { + abi_ulong mmap_start; + + /* In order to use the host shmat, we need to honor host SHMLBA. */ + mmap_start = mmap_find_vma(0, shm_info.shm_segsz, + MAX(SHMLBA, shmlba)); + + if (mmap_start == -1) { + return -TARGET_ENOMEM; + } + host_raddr = shmat(shmid, g2h_untagged(mmap_start), + shmflg | SHM_REMAP); + } + + if (host_raddr == (void *)-1) { + return get_errno(-1); + } + raddr = h2g(host_raddr); + last = raddr + shm_info.shm_segsz - 1; + + page_set_flags(raddr, last, + PAGE_VALID | PAGE_RESET | PAGE_READ | + (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); + + shm_region_rm_complete(raddr, last); + shm_region_add(raddr, last); + } + + /* + * We're mapping shared memory, so ensure we generate code for parallel + * execution and flush old translations. This will work up to the level + * supported by the host -- anything that requires EXCP_ATOMIC will not + * be atomic with respect to an external process. + */ + if (!(cpu->tcg_cflags & CF_PARALLEL)) { + cpu->tcg_cflags |= CF_PARALLEL; + tb_flush(cpu); + } + + return raddr; +} + +abi_long target_shmdt(abi_ulong shmaddr) +{ + abi_long rv; + + /* shmdt pointers are always untagged */ + + WITH_MMAP_LOCK_GUARD() { + abi_ulong last = shm_region_find(shmaddr); + if (last == 0) { + return -TARGET_EINVAL; + } + + rv = get_errno(shmdt(g2h_untagged(shmaddr))); + if (rv == 0) { + abi_ulong size = last - shmaddr + 1; + + page_set_flags(shmaddr, last, 0); + shm_region_rm_complete(shmaddr, last); + mmap_reserve_or_unmap(shmaddr, size); + } + } + return rv; +} diff --git a/linux-user/nios2/target_proc.h b/linux-user/nios2/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/nios2/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/openrisc/target_proc.h b/linux-user/openrisc/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/openrisc/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/ppc/target_proc.h b/linux-user/ppc/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/ppc/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/qemu.h b/linux-user/qemu.h index 4f8b55e2fb..12f638336a 100644 --- a/linux-user/qemu.h +++ b/linux-user/qemu.h @@ -30,7 +30,6 @@ struct image_info { abi_ulong start_data; abi_ulong end_data; abi_ulong brk; - abi_ulong start_mmap; abi_ulong start_stack; abi_ulong stack_limit; abi_ulong entry; diff --git a/linux-user/riscv/target_proc.h b/linux-user/riscv/target_proc.h new file mode 100644 index 0000000000..c77c003d65 --- /dev/null +++ b/linux-user/riscv/target_proc.h @@ -0,0 +1,37 @@ +/* + * RISC-V specific proc functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef RISCV_TARGET_PROC_H +#define RISCV_TARGET_PROC_H + +static int open_cpuinfo(CPUArchState *cpu_env, int fd) +{ + int i; + int num_cpus = sysconf(_SC_NPROCESSORS_ONLN); + RISCVCPU *cpu = env_archcpu(cpu_env); + const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env); + char *isa_string = riscv_isa_string(cpu); + const char *mmu; + + if (cfg->mmu) { + mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48"; + } else { + mmu = "none"; + } + + for (i = 0; i < num_cpus; i++) { + dprintf(fd, "processor\t: %d\n", i); + dprintf(fd, "hart\t\t: %d\n", i); + dprintf(fd, "isa\t\t: %s\n", isa_string); + dprintf(fd, "mmu\t\t: %s\n", mmu); + dprintf(fd, "uarch\t\t: qemu\n\n"); + } + + g_free(isa_string); + return 0; +} +#define HAVE_ARCH_PROC_CPUINFO + +#endif /* RISCV_TARGET_PROC_H */ diff --git a/linux-user/s390x/target_proc.h b/linux-user/s390x/target_proc.h new file mode 100644 index 0000000000..a4a4821ea5 --- /dev/null +++ b/linux-user/s390x/target_proc.h @@ -0,0 +1,109 @@ +/* + * S390X specific proc functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef S390X_TARGET_PROC_H +#define S390X_TARGET_PROC_H + +/* + * Emulate what a Linux kernel running in qemu-system-s390x -M accel=tcg would + * show in /proc/cpuinfo. + * + * Skip the following in order to match the missing support in op_ecag(): + * - show_cacheinfo(). + * - show_cpu_topology(). + * - show_cpu_mhz(). + * + * Use fixed values for certain fields: + * - bogomips per cpu - from a qemu-system-s390x run. + * - max thread id = 0, since SMT / SIGP_SET_MULTI_THREADING is not supported. + * + * Keep the code structure close to arch/s390/kernel/processor.c. + */ + +static void show_facilities(int fd) +{ + size_t sizeof_stfl_bytes = 2048; + g_autofree uint8_t *stfl_bytes = g_new0(uint8_t, sizeof_stfl_bytes); + unsigned int bit; + + dprintf(fd, "facilities :"); + s390_get_feat_block(S390_FEAT_TYPE_STFL, stfl_bytes); + for (bit = 0; bit < sizeof_stfl_bytes * 8; bit++) { + if (test_be_bit(bit, stfl_bytes)) { + dprintf(fd, " %d", bit); + } + } + dprintf(fd, "\n"); +} + +static int cpu_ident(unsigned long n) +{ + return deposit32(0, CPU_ID_BITS - CPU_PHYS_ADDR_BITS, CPU_PHYS_ADDR_BITS, + n); +} + +static void show_cpu_summary(CPUArchState *cpu_env, int fd) +{ + S390CPUModel *model = env_archcpu(cpu_env)->model; + int num_cpus = sysconf(_SC_NPROCESSORS_ONLN); + uint32_t elf_hwcap = get_elf_hwcap(); + const char *hwcap_str; + int i; + + dprintf(fd, "vendor_id : IBM/S390\n" + "# processors : %i\n" + "bogomips per cpu: 13370.00\n", + num_cpus); + dprintf(fd, "max thread id : 0\n"); + dprintf(fd, "features\t: "); + for (i = 0; i < sizeof(elf_hwcap) * 8; i++) { + if (!(elf_hwcap & (1 << i))) { + continue; + } + hwcap_str = elf_hwcap_str(i); + if (hwcap_str) { + dprintf(fd, "%s ", hwcap_str); + } + } + dprintf(fd, "\n"); + show_facilities(fd); + for (i = 0; i < num_cpus; i++) { + dprintf(fd, "processor %d: " + "version = %02X, " + "identification = %06X, " + "machine = %04X\n", + i, model->cpu_ver, cpu_ident(i), model->def->type); + } +} + +static void show_cpu_ids(CPUArchState *cpu_env, int fd, unsigned long n) +{ + S390CPUModel *model = env_archcpu(cpu_env)->model; + + dprintf(fd, "version : %02X\n", model->cpu_ver); + dprintf(fd, "identification : %06X\n", cpu_ident(n)); + dprintf(fd, "machine : %04X\n", model->def->type); +} + +static void show_cpuinfo(CPUArchState *cpu_env, int fd, unsigned long n) +{ + dprintf(fd, "\ncpu number : %ld\n", n); + show_cpu_ids(cpu_env, fd, n); +} + +static int open_cpuinfo(CPUArchState *cpu_env, int fd) +{ + int num_cpus = sysconf(_SC_NPROCESSORS_ONLN); + int i; + + show_cpu_summary(cpu_env, fd); + for (i = 0; i < num_cpus; i++) { + show_cpuinfo(cpu_env, fd, i); + } + return 0; +} +#define HAVE_ARCH_PROC_CPUINFO + +#endif /* S390X_TARGET_PROC_H */ diff --git a/linux-user/sh4/target_proc.h b/linux-user/sh4/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/sh4/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/sparc/target_proc.h b/linux-user/sparc/target_proc.h new file mode 100644 index 0000000000..3bb3134a47 --- /dev/null +++ b/linux-user/sparc/target_proc.h @@ -0,0 +1,16 @@ +/* + * Sparc specific proc functions for linux-user + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#ifndef SPARC_TARGET_PROC_H +#define SPARC_TARGET_PROC_H + +static int open_cpuinfo(CPUArchState *cpu_env, int fd) +{ + dprintf(fd, "type\t\t: sun4u\n"); + return 0; +} +#define HAVE_ARCH_PROC_CPUINFO + +#endif /* SPARC_TARGET_PROC_H */ diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 9353268cc1..dac0641bab 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -1809,7 +1809,7 @@ static inline abi_long target_to_host_cmsg(struct msghdr *msgh, uint32_t *dst = (uint32_t *)data; memcpy(dst, target_data, len); - /* fix endianess of first 32-bit word */ + /* fix endianness of first 32-bit word */ if (len >= sizeof(uint32_t)) { *dst = tswap32(*dst); } @@ -2920,7 +2920,7 @@ get_timeout: unlock_user(results, optval_addr, 0); return ret; } - /* swap host endianess to target endianess. */ + /* swap host endianness to target endianness. */ for (i = 0; i < (len / sizeof(uint32_t)); i++) { results[i] = tswap32(results[i]); } @@ -3725,14 +3725,6 @@ static abi_long do_socketcall(int num, abi_ulong vptr) } #endif -#define N_SHM_REGIONS 32 - -static struct shm_region { - abi_ulong start; - abi_ulong size; - bool in_use; -} shm_regions[N_SHM_REGIONS]; - #ifndef TARGET_SEMID64_DS /* asm-generic version of this struct */ struct target_semid64_ds @@ -4482,133 +4474,6 @@ static inline abi_long do_shmctl(int shmid, int cmd, abi_long buf) return ret; } -#ifndef TARGET_FORCE_SHMLBA -/* For most architectures, SHMLBA is the same as the page size; - * some architectures have larger values, in which case they should - * define TARGET_FORCE_SHMLBA and provide a target_shmlba() function. - * This corresponds to the kernel arch code defining __ARCH_FORCE_SHMLBA - * and defining its own value for SHMLBA. - * - * The kernel also permits SHMLBA to be set by the architecture to a - * value larger than the page size without setting __ARCH_FORCE_SHMLBA; - * this means that addresses are rounded to the large size if - * SHM_RND is set but addresses not aligned to that size are not rejected - * as long as they are at least page-aligned. Since the only architecture - * which uses this is ia64 this code doesn't provide for that oddity. - */ -static inline abi_ulong target_shmlba(CPUArchState *cpu_env) -{ - return TARGET_PAGE_SIZE; -} -#endif - -static abi_ulong do_shmat(CPUArchState *cpu_env, int shmid, - abi_ulong shmaddr, int shmflg) -{ - CPUState *cpu = env_cpu(cpu_env); - abi_ulong raddr; - void *host_raddr; - struct shmid_ds shm_info; - int i, ret; - abi_ulong shmlba; - - /* shmat pointers are always untagged */ - - /* find out the length of the shared memory segment */ - ret = get_errno(shmctl(shmid, IPC_STAT, &shm_info)); - if (is_error(ret)) { - /* can't get length, bail out */ - return ret; - } - - shmlba = target_shmlba(cpu_env); - - if (shmaddr & (shmlba - 1)) { - if (shmflg & SHM_RND) { - shmaddr &= ~(shmlba - 1); - } else { - return -TARGET_EINVAL; - } - } - if (!guest_range_valid_untagged(shmaddr, shm_info.shm_segsz)) { - return -TARGET_EINVAL; - } - - mmap_lock(); - - /* - * We're mapping shared memory, so ensure we generate code for parallel - * execution and flush old translations. This will work up to the level - * supported by the host -- anything that requires EXCP_ATOMIC will not - * be atomic with respect to an external process. - */ - if (!(cpu->tcg_cflags & CF_PARALLEL)) { - cpu->tcg_cflags |= CF_PARALLEL; - tb_flush(cpu); - } - - if (shmaddr) - host_raddr = shmat(shmid, (void *)g2h_untagged(shmaddr), shmflg); - else { - abi_ulong mmap_start; - - /* In order to use the host shmat, we need to honor host SHMLBA. */ - mmap_start = mmap_find_vma(0, shm_info.shm_segsz, MAX(SHMLBA, shmlba)); - - if (mmap_start == -1) { - errno = ENOMEM; - host_raddr = (void *)-1; - } else - host_raddr = shmat(shmid, g2h_untagged(mmap_start), - shmflg | SHM_REMAP); - } - - if (host_raddr == (void *)-1) { - mmap_unlock(); - return get_errno((intptr_t)host_raddr); - } - raddr = h2g((uintptr_t)host_raddr); - - page_set_flags(raddr, raddr + shm_info.shm_segsz - 1, - PAGE_VALID | PAGE_RESET | PAGE_READ | - (shmflg & SHM_RDONLY ? 0 : PAGE_WRITE)); - - for (i = 0; i < N_SHM_REGIONS; i++) { - if (!shm_regions[i].in_use) { - shm_regions[i].in_use = true; - shm_regions[i].start = raddr; - shm_regions[i].size = shm_info.shm_segsz; - break; - } - } - - mmap_unlock(); - return raddr; -} - -static inline abi_long do_shmdt(abi_ulong shmaddr) -{ - int i; - abi_long rv; - - /* shmdt pointers are always untagged */ - - mmap_lock(); - - for (i = 0; i < N_SHM_REGIONS; ++i) { - if (shm_regions[i].in_use && shm_regions[i].start == shmaddr) { - shm_regions[i].in_use = false; - page_set_flags(shmaddr, shmaddr + shm_regions[i].size - 1, 0); - break; - } - } - rv = get_errno(shmdt(g2h_untagged(shmaddr))); - - mmap_unlock(); - - return rv; -} - #ifdef TARGET_NR_ipc /* ??? This only works with linear mappings. */ /* do_ipc() must return target values and target errnos. */ @@ -4695,7 +4560,7 @@ static abi_long do_ipc(CPUArchState *cpu_env, default: { abi_ulong raddr; - raddr = do_shmat(cpu_env, first, ptr, second); + raddr = target_shmat(cpu_env, first, ptr, second); if (is_error(raddr)) return get_errno(raddr); if (put_user_ual(raddr, third)) @@ -4708,7 +4573,7 @@ static abi_long do_ipc(CPUArchState *cpu_env, } break; case IPCOP_shmdt: - ret = do_shmdt(ptr); + ret = target_shmdt(ptr); break; case IPCOP_shmget: @@ -8095,12 +7960,68 @@ static int open_self_cmdline(CPUArchState *cpu_env, int fd) return 0; } -static void show_smaps(int fd, unsigned long size) +struct open_self_maps_data { + TaskState *ts; + IntervalTreeRoot *host_maps; + int fd; + bool smaps; +}; + +/* + * Subroutine to output one line of /proc/self/maps, + * or one region of /proc/self/smaps. + */ + +#ifdef TARGET_HPPA +# define test_stack(S, E, L) (E == L) +#else +# define test_stack(S, E, L) (S == L) +#endif + +static void open_self_maps_4(const struct open_self_maps_data *d, + const MapInfo *mi, abi_ptr start, + abi_ptr end, unsigned flags) { - unsigned long page_size_kb = TARGET_PAGE_SIZE >> 10; - unsigned long size_kb = size >> 10; + const struct image_info *info = d->ts->info; + const char *path = mi->path; + uint64_t offset; + int fd = d->fd; + int count; + + if (test_stack(start, end, info->stack_limit)) { + path = "[stack]"; + } else if (start == info->brk) { + path = "[heap]"; + } + + /* Except null device (MAP_ANON), adjust offset for this fragment. */ + offset = mi->offset; + if (mi->dev) { + uintptr_t hstart = (uintptr_t)g2h_untagged(start); + offset += hstart - mi->itree.start; + } + + count = dprintf(fd, TARGET_ABI_FMT_ptr "-" TARGET_ABI_FMT_ptr + " %c%c%c%c %08" PRIx64 " %02x:%02x %"PRId64, + start, end, + (flags & PAGE_READ) ? 'r' : '-', + (flags & PAGE_WRITE_ORG) ? 'w' : '-', + (flags & PAGE_EXEC) ? 'x' : '-', + mi->is_priv ? 'p' : 's', + offset, major(mi->dev), minor(mi->dev), + (uint64_t)mi->inode); + if (path) { + dprintf(fd, "%*s%s\n", 73 - count, "", path); + } else { + dprintf(fd, "\n"); + } + + if (d->smaps) { + unsigned long size = end - start; + unsigned long page_size_kb = TARGET_PAGE_SIZE >> 10; + unsigned long size_kb = size >> 10; - dprintf(fd, "Size: %lu kB\n" + dprintf(fd, "Size: %lu kB\n" "KernelPageSize: %lu kB\n" "MMUPageSize: %lu kB\n" "Rss: 0 kB\n" @@ -8111,7 +8032,7 @@ static void show_smaps(int fd, unsigned long size) "Private_Clean: 0 kB\n" "Private_Dirty: 0 kB\n" "Referenced: 0 kB\n" - "Anonymous: 0 kB\n" + "Anonymous: %lu kB\n" "LazyFree: 0 kB\n" "AnonHugePages: 0 kB\n" "ShmemPmdMapped: 0 kB\n" @@ -8121,89 +8042,76 @@ static void show_smaps(int fd, unsigned long size) "Swap: 0 kB\n" "SwapPss: 0 kB\n" "Locked: 0 kB\n" - "THPeligible: 0\n", size_kb, page_size_kb, page_size_kb); + "THPeligible: 0\n" + "VmFlags:%s%s%s%s%s%s%s%s\n", + size_kb, page_size_kb, page_size_kb, + (flags & PAGE_ANON ? size_kb : 0), + (flags & PAGE_READ) ? " rd" : "", + (flags & PAGE_WRITE_ORG) ? " wr" : "", + (flags & PAGE_EXEC) ? " ex" : "", + mi->is_priv ? "" : " sh", + (flags & PAGE_READ) ? " mr" : "", + (flags & PAGE_WRITE_ORG) ? " mw" : "", + (flags & PAGE_EXEC) ? " me" : "", + mi->is_priv ? "" : " ms"); + } } -static int open_self_maps_1(CPUArchState *cpu_env, int fd, bool smaps) +/* + * Callback for walk_memory_regions, when read_self_maps() fails. + * Proceed without the benefit of host /proc/self/maps cross-check. + */ +static int open_self_maps_3(void *opaque, target_ulong guest_start, + target_ulong guest_end, unsigned long flags) { - CPUState *cpu = env_cpu(cpu_env); - TaskState *ts = cpu->opaque; - IntervalTreeRoot *map_info = read_self_maps(); - IntervalTreeNode *s; - int count; + static const MapInfo mi = { .is_priv = true }; - for (s = interval_tree_iter_first(map_info, 0, -1); s; - s = interval_tree_iter_next(s, 0, -1)) { - MapInfo *e = container_of(s, MapInfo, itree); + open_self_maps_4(opaque, &mi, guest_start, guest_end, flags); + return 0; +} - if (h2g_valid(e->itree.start)) { - unsigned long min = e->itree.start; - unsigned long max = e->itree.last + 1; - int flags = page_get_flags(h2g(min)); - const char *path; +/* + * Callback for walk_memory_regions, when read_self_maps() succeeds. + */ +static int open_self_maps_2(void *opaque, target_ulong guest_start, + target_ulong guest_end, unsigned long flags) +{ + const struct open_self_maps_data *d = opaque; + uintptr_t host_start = (uintptr_t)g2h_untagged(guest_start); + uintptr_t host_last = (uintptr_t)g2h_untagged(guest_end - 1); - max = h2g_valid(max - 1) ? - max : (uintptr_t) g2h_untagged(GUEST_ADDR_MAX) + 1; + while (1) { + IntervalTreeNode *n = + interval_tree_iter_first(d->host_maps, host_start, host_start); + MapInfo *mi = container_of(n, MapInfo, itree); + uintptr_t this_hlast = MIN(host_last, n->last); + target_ulong this_gend = h2g(this_hlast) + 1; - if (!page_check_range(h2g(min), max - min, flags)) { - continue; - } + open_self_maps_4(d, mi, guest_start, this_gend, flags); -#ifdef TARGET_HPPA - if (h2g(max) == ts->info->stack_limit) { -#else - if (h2g(min) == ts->info->stack_limit) { -#endif - path = "[stack]"; - } else { - path = e->path; - } - - count = dprintf(fd, TARGET_ABI_FMT_ptr "-" TARGET_ABI_FMT_ptr - " %c%c%c%c %08" PRIx64 " %s %"PRId64, - h2g(min), h2g(max - 1) + 1, - (flags & PAGE_READ) ? 'r' : '-', - (flags & PAGE_WRITE_ORG) ? 'w' : '-', - (flags & PAGE_EXEC) ? 'x' : '-', - e->is_priv ? 'p' : 's', - (uint64_t) e->offset, e->dev, e->inode); - if (path) { - dprintf(fd, "%*s%s\n", 73 - count, "", path); - } else { - dprintf(fd, "\n"); - } - if (smaps) { - show_smaps(fd, max - min); - dprintf(fd, "VmFlags:%s%s%s%s%s%s%s%s\n", - (flags & PAGE_READ) ? " rd" : "", - (flags & PAGE_WRITE_ORG) ? " wr" : "", - (flags & PAGE_EXEC) ? " ex" : "", - e->is_priv ? "" : " sh", - (flags & PAGE_READ) ? " mr" : "", - (flags & PAGE_WRITE_ORG) ? " mw" : "", - (flags & PAGE_EXEC) ? " me" : "", - e->is_priv ? "" : " ms"); - } + if (this_hlast == host_last) { + return 0; } + host_start = this_hlast + 1; + guest_start = h2g(host_start); } +} - free_self_maps(map_info); +static int open_self_maps_1(CPUArchState *env, int fd, bool smaps) +{ + struct open_self_maps_data d = { + .ts = env_cpu(env)->opaque, + .host_maps = read_self_maps(), + .fd = fd, + .smaps = smaps + }; -#ifdef TARGET_VSYSCALL_PAGE - /* - * We only support execution from the vsyscall page. - * This is as if CONFIG_LEGACY_VSYSCALL_XONLY=y from v5.3. - */ - count = dprintf(fd, TARGET_FMT_lx "-" TARGET_FMT_lx - " --xp 00000000 00:00 0", - TARGET_VSYSCALL_PAGE, TARGET_VSYSCALL_PAGE + TARGET_PAGE_SIZE); - dprintf(fd, "%*s%s\n", 73 - count, "", "[vsyscall]"); - if (smaps) { - show_smaps(fd, TARGET_PAGE_SIZE); - dprintf(fd, "VmFlags: ex\n"); + if (d.host_maps) { + walk_memory_regions(&d, open_self_maps_2); + free_self_maps(d.host_maps); + } else { + walk_memory_regions(&d, open_self_maps_3); } -#endif - return 0; } @@ -8339,9 +8247,11 @@ void target_exception_dump(CPUArchState *env, const char *fmt, int code) } } +#include "target_proc.h" + #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN || \ - defined(TARGET_SPARC) || defined(TARGET_M68K) || defined(TARGET_HPPA) || \ - defined(TARGET_RISCV) || defined(TARGET_S390X) + defined(HAVE_ARCH_PROC_CPUINFO) || \ + defined(HAVE_ARCH_PROC_HARDWARE) static int is_proc(const char *filename, const char *entry) { return strcmp(filename, entry) == 0; @@ -8393,171 +8303,6 @@ static int open_net_route(CPUArchState *cpu_env, int fd) } #endif -#if defined(TARGET_SPARC) -static int open_cpuinfo(CPUArchState *cpu_env, int fd) -{ - dprintf(fd, "type\t\t: sun4u\n"); - return 0; -} -#endif - -#if defined(TARGET_HPPA) -static int open_cpuinfo(CPUArchState *cpu_env, int fd) -{ - int i, num_cpus; - - num_cpus = sysconf(_SC_NPROCESSORS_ONLN); - for (i = 0; i < num_cpus; i++) { - dprintf(fd, "processor\t: %d\n", i); - dprintf(fd, "cpu family\t: PA-RISC 1.1e\n"); - dprintf(fd, "cpu\t\t: PA7300LC (PCX-L2)\n"); - dprintf(fd, "capabilities\t: os32\n"); - dprintf(fd, "model\t\t: 9000/778/B160L - " - "Merlin L2 160 QEMU (9000/778/B160L)\n\n"); - } - return 0; -} -#endif - -#if defined(TARGET_RISCV) -static int open_cpuinfo(CPUArchState *cpu_env, int fd) -{ - int i; - int num_cpus = sysconf(_SC_NPROCESSORS_ONLN); - RISCVCPU *cpu = env_archcpu(cpu_env); - const RISCVCPUConfig *cfg = riscv_cpu_cfg((CPURISCVState *) cpu_env); - char *isa_string = riscv_isa_string(cpu); - const char *mmu; - - if (cfg->mmu) { - mmu = (cpu_env->xl == MXL_RV32) ? "sv32" : "sv48"; - } else { - mmu = "none"; - } - - for (i = 0; i < num_cpus; i++) { - dprintf(fd, "processor\t: %d\n", i); - dprintf(fd, "hart\t\t: %d\n", i); - dprintf(fd, "isa\t\t: %s\n", isa_string); - dprintf(fd, "mmu\t\t: %s\n", mmu); - dprintf(fd, "uarch\t\t: qemu\n\n"); - } - - g_free(isa_string); - return 0; -} -#endif - -#if defined(TARGET_S390X) -/* - * Emulate what a Linux kernel running in qemu-system-s390x -M accel=tcg would - * show in /proc/cpuinfo. - * - * Skip the following in order to match the missing support in op_ecag(): - * - show_cacheinfo(). - * - show_cpu_topology(). - * - show_cpu_mhz(). - * - * Use fixed values for certain fields: - * - bogomips per cpu - from a qemu-system-s390x run. - * - max thread id = 0, since SMT / SIGP_SET_MULTI_THREADING is not supported. - * - * Keep the code structure close to arch/s390/kernel/processor.c. - */ - -static void show_facilities(int fd) -{ - size_t sizeof_stfl_bytes = 2048; - g_autofree uint8_t *stfl_bytes = g_new0(uint8_t, sizeof_stfl_bytes); - unsigned int bit; - - dprintf(fd, "facilities :"); - s390_get_feat_block(S390_FEAT_TYPE_STFL, stfl_bytes); - for (bit = 0; bit < sizeof_stfl_bytes * 8; bit++) { - if (test_be_bit(bit, stfl_bytes)) { - dprintf(fd, " %d", bit); - } - } - dprintf(fd, "\n"); -} - -static int cpu_ident(unsigned long n) -{ - return deposit32(0, CPU_ID_BITS - CPU_PHYS_ADDR_BITS, CPU_PHYS_ADDR_BITS, - n); -} - -static void show_cpu_summary(CPUArchState *cpu_env, int fd) -{ - S390CPUModel *model = env_archcpu(cpu_env)->model; - int num_cpus = sysconf(_SC_NPROCESSORS_ONLN); - uint32_t elf_hwcap = get_elf_hwcap(); - const char *hwcap_str; - int i; - - dprintf(fd, "vendor_id : IBM/S390\n" - "# processors : %i\n" - "bogomips per cpu: 13370.00\n", - num_cpus); - dprintf(fd, "max thread id : 0\n"); - dprintf(fd, "features\t: "); - for (i = 0; i < sizeof(elf_hwcap) * 8; i++) { - if (!(elf_hwcap & (1 << i))) { - continue; - } - hwcap_str = elf_hwcap_str(i); - if (hwcap_str) { - dprintf(fd, "%s ", hwcap_str); - } - } - dprintf(fd, "\n"); - show_facilities(fd); - for (i = 0; i < num_cpus; i++) { - dprintf(fd, "processor %d: " - "version = %02X, " - "identification = %06X, " - "machine = %04X\n", - i, model->cpu_ver, cpu_ident(i), model->def->type); - } -} - -static void show_cpu_ids(CPUArchState *cpu_env, int fd, unsigned long n) -{ - S390CPUModel *model = env_archcpu(cpu_env)->model; - - dprintf(fd, "version : %02X\n", model->cpu_ver); - dprintf(fd, "identification : %06X\n", cpu_ident(n)); - dprintf(fd, "machine : %04X\n", model->def->type); -} - -static void show_cpuinfo(CPUArchState *cpu_env, int fd, unsigned long n) -{ - dprintf(fd, "\ncpu number : %ld\n", n); - show_cpu_ids(cpu_env, fd, n); -} - -static int open_cpuinfo(CPUArchState *cpu_env, int fd) -{ - int num_cpus = sysconf(_SC_NPROCESSORS_ONLN); - int i; - - show_cpu_summary(cpu_env, fd); - for (i = 0; i < num_cpus; i++) { - show_cpuinfo(cpu_env, fd, i); - } - return 0; -} -#endif - -#if defined(TARGET_M68K) -static int open_hardware(CPUArchState *cpu_env, int fd) -{ - dprintf(fd, "Model:\t\tqemu-m68k\n"); - return 0; -} -#endif - - int do_guest_openat(CPUArchState *cpu_env, int dirfd, const char *fname, int flags, mode_t mode, bool safe) { @@ -8578,11 +8323,10 @@ int do_guest_openat(CPUArchState *cpu_env, int dirfd, const char *fname, #if HOST_BIG_ENDIAN != TARGET_BIG_ENDIAN { "/proc/net/route", open_net_route, is_proc }, #endif -#if defined(TARGET_SPARC) || defined(TARGET_HPPA) || \ - defined(TARGET_RISCV) || defined(TARGET_S390X) +#if defined(HAVE_ARCH_PROC_CPUINFO) { "/proc/cpuinfo", open_cpuinfo, is_proc }, #endif -#if defined(TARGET_M68K) +#if defined(HAVE_ARCH_PROC_HARDWARE) { "/proc/hardware", open_hardware, is_proc }, #endif { NULL, NULL, NULL } @@ -11129,11 +10873,11 @@ static abi_long do_syscall1(CPUArchState *cpu_env, int num, abi_long arg1, #endif #ifdef TARGET_NR_shmat case TARGET_NR_shmat: - return do_shmat(cpu_env, arg1, arg2, arg3); + return target_shmat(cpu_env, arg1, arg2, arg3); #endif #ifdef TARGET_NR_shmdt case TARGET_NR_shmdt: - return do_shmdt(arg1); + return target_shmdt(arg1); #endif case TARGET_NR_fsync: return get_errno(fsync(arg1)); diff --git a/linux-user/user-mmap.h b/linux-user/user-mmap.h index 0f4883eb57..b94bcdcf83 100644 --- a/linux-user/user-mmap.h +++ b/linux-user/user-mmap.h @@ -58,4 +58,8 @@ abi_ulong mmap_find_vma(abi_ulong, abi_ulong, abi_ulong); void mmap_fork_start(void); void mmap_fork_end(int child); +abi_ulong target_shmat(CPUArchState *cpu_env, int shmid, + abi_ulong shmaddr, int shmflg); +abi_long target_shmdt(abi_ulong shmaddr); + #endif /* LINUX_USER_USER_MMAP_H */ diff --git a/linux-user/x86_64/target_proc.h b/linux-user/x86_64/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/x86_64/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/linux-user/xtensa/target_proc.h b/linux-user/xtensa/target_proc.h new file mode 100644 index 0000000000..43fe29ca72 --- /dev/null +++ b/linux-user/xtensa/target_proc.h @@ -0,0 +1 @@ +/* No target-specific /proc support */ diff --git a/meson.build b/meson.build index c24ea69f77..bf9831c715 100644 --- a/meson.build +++ b/meson.build @@ -140,7 +140,6 @@ if cpu in ['x86', 'x86_64', 'arm', 'aarch64'] endif if cpu in ['x86', 'x86_64'] accelerator_targets += { - 'CONFIG_HAX': ['i386-softmmu', 'x86_64-softmmu'], 'CONFIG_HVF': ['x86_64-softmmu'], 'CONFIG_NVMM': ['i386-softmmu', 'x86_64-softmmu'], 'CONFIG_WHPX': ['i386-softmmu', 'x86_64-softmmu'], @@ -224,7 +223,9 @@ qemu_ldflags = [] if targetos == 'darwin' # Disable attempts to use ObjectiveC features in os/object.h since they # won't work when we're compiling with gcc as a C compiler. - qemu_common_flags += '-DOS_OBJECT_USE_OBJC=0' + if compiler.get_id() == 'gcc' + qemu_common_flags += '-DOS_OBJECT_USE_OBJC=0' + endif elif targetos == 'solaris' # needed for CMSG_ macros in sys/socket.h qemu_common_flags += '-D_XOPEN_SOURCE=600' @@ -663,11 +664,6 @@ if get_option('hvf').allowed() accelerators += 'CONFIG_HVF' endif endif -if get_option('hax').allowed() - if get_option('hax').enabled() or targetos in ['windows', 'darwin', 'netbsd'] - accelerators += 'CONFIG_HAX' - endif -endif if targetos == 'netbsd' nvmm = cc.find_library('nvmm', required: get_option('nvmm')) if nvmm.found() @@ -4154,7 +4150,6 @@ endif summary_info = {} if have_system summary_info += {'KVM support': config_all.has_key('CONFIG_KVM')} - summary_info += {'HAX support': config_all.has_key('CONFIG_HAX')} summary_info += {'HVF support': config_all.has_key('CONFIG_HVF')} summary_info += {'WHPX support': config_all.has_key('CONFIG_WHPX')} summary_info += {'NVMM support': config_all.has_key('CONFIG_NVMM')} diff --git a/meson_options.txt b/meson_options.txt index e48086e256..f82d88b7c6 100644 --- a/meson_options.txt +++ b/meson_options.txt @@ -69,8 +69,6 @@ option('malloc', type : 'combo', choices : ['system', 'tcmalloc', 'jemalloc'], option('kvm', type: 'feature', value: 'auto', description: 'KVM acceleration support') -option('hax', type: 'feature', value: 'auto', - description: 'HAX acceleration support') option('whpx', type: 'feature', value: 'auto', description: 'WHPX acceleration support') option('hvf', type: 'feature', value: 'auto', diff --git a/monitor/monitor.c b/monitor/monitor.c index dc352f9e9d..941f87815a 100644 --- a/monitor/monitor.c +++ b/monitor/monitor.c @@ -144,7 +144,7 @@ static gboolean monitor_unblocked(void *do_not_use, GIOCondition cond, QEMU_LOCK_GUARD(&mon->mon_lock); mon->out_watch = 0; monitor_flush_locked(mon); - return FALSE; + return G_SOURCE_REMOVE; } /* Caller must hold mon->mon_lock */ diff --git a/net/vhost-user.c b/net/vhost-user.c index 5993e4afca..12555518e8 100644 --- a/net/vhost-user.c +++ b/net/vhost-user.c @@ -239,7 +239,7 @@ static gboolean net_vhost_user_watch(void *do_not_use, GIOCondition cond, qemu_chr_fe_disconnect(&s->chr); - return TRUE; + return G_SOURCE_CONTINUE; } static void net_vhost_user_event(void *opaque, QEMUChrEvent event); diff --git a/qapi/char.json b/qapi/char.json index 52aaff25eb..c1bab7b855 100644 --- a/qapi/char.json +++ b/qapi/char.json @@ -390,6 +390,10 @@ # # @rows: console height, in chars # +# Note: the options are only effective when the VNC or SDL graphical +# display backend is active. They are ignored with the GTK, Spice, VNC +# and D-Bus display backends. +# # Since: 1.5 ## { 'struct': 'ChardevVC', diff --git a/qemu-options.hx b/qemu-options.hx index 29b98c3d4c..463f520c57 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -26,7 +26,7 @@ DEF("machine", HAS_ARG, QEMU_OPTION_machine, \ "-machine [type=]name[,prop[=value][,...]]\n" " selects emulated machine ('-machine help' for list)\n" " property accel=accel1[:accel2[:...]] selects accelerator\n" - " supported accelerators are kvm, xen, hax, hvf, nvmm, whpx or tcg (default: tcg)\n" + " supported accelerators are kvm, xen, hvf, nvmm, whpx or tcg (default: tcg)\n" " vmport=on|off|auto controls emulation of vmport (default: auto)\n" " dump-guest-core=on|off include guest memory in a core dump (default=on)\n" " mem-merge=on|off controls memory merge support (default: on)\n" @@ -59,7 +59,7 @@ SRST ``accel=accels1[:accels2[:...]]`` This is used to enable an accelerator. Depending on the target - architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be available. + architecture, kvm, xen, hvf, nvmm, whpx or tcg can be available. By default, tcg is used. If there is more than one accelerator specified, the next one is used if the previous one fails to initialize. @@ -178,7 +178,7 @@ ERST DEF("accel", HAS_ARG, QEMU_OPTION_accel, "-accel [accel=]accelerator[,prop[=value][,...]]\n" - " select accelerator (kvm, xen, hax, hvf, nvmm, whpx or tcg; use 'help' for a list)\n" + " select accelerator (kvm, xen, hvf, nvmm, whpx or tcg; use 'help' for a list)\n" " igd-passthru=on|off (enable Xen integrated Intel graphics passthrough, default=off)\n" " kernel-irqchip=on|off|split controls accelerated irqchip support (default=on)\n" " kvm-shadow-mem=size of KVM shadow MMU in bytes\n" @@ -191,7 +191,7 @@ DEF("accel", HAS_ARG, QEMU_OPTION_accel, SRST ``-accel name[,prop=value[,...]]`` This is used to enable an accelerator. Depending on the target - architecture, kvm, xen, hax, hvf, nvmm, whpx or tcg can be available. By + architecture, kvm, xen, hvf, nvmm, whpx or tcg can be available. By default, tcg is used. If there is more than one accelerator specified, the next one is used if the previous one fails to initialize. diff --git a/scripts/ci/org.centos/stream/8/x86_64/configure b/scripts/ci/org.centos/stream/8/x86_64/configure index d02b09a4b9..131f8ee5f3 100755 --- a/scripts/ci/org.centos/stream/8/x86_64/configure +++ b/scripts/ci/org.centos/stream/8/x86_64/configure @@ -68,7 +68,6 @@ --disable-gtk \ --disable-guest-agent \ --disable-guest-agent-msi \ ---disable-hax \ --disable-hvf \ --disable-iconv \ --disable-kvm \ diff --git a/scripts/meson-buildoptions.sh b/scripts/meson-buildoptions.sh index 6b16ad94f4..e1d178370c 100644 --- a/scripts/meson-buildoptions.sh +++ b/scripts/meson-buildoptions.sh @@ -112,7 +112,6 @@ meson_options_help() { printf "%s\n" ' gtk-clipboard clipboard support for the gtk UI (EXPERIMENTAL, MAY HANG)' printf "%s\n" ' guest-agent Build QEMU Guest Agent' printf "%s\n" ' guest-agent-msi Build MSI package for the QEMU Guest Agent' - printf "%s\n" ' hax HAX acceleration support' printf "%s\n" ' hvf HVF acceleration support' printf "%s\n" ' iconv Font glyph conversion support' printf "%s\n" ' jack JACK sound support' @@ -316,8 +315,6 @@ _meson_option_parse() { --disable-guest-agent) printf "%s" -Dguest_agent=disabled ;; --enable-guest-agent-msi) printf "%s" -Dguest_agent_msi=enabled ;; --disable-guest-agent-msi) printf "%s" -Dguest_agent_msi=disabled ;; - --enable-hax) printf "%s" -Dhax=enabled ;; - --disable-hax) printf "%s" -Dhax=disabled ;; --enable-hexagon-idef-parser) printf "%s" -Dhexagon_idef_parser=true ;; --disable-hexagon-idef-parser) printf "%s" -Dhexagon_idef_parser=false ;; --enable-hvf) printf "%s" -Dhvf=enabled ;; diff --git a/semihosting/config.c b/semihosting/config.c index 89a1759687..8ca569735d 100644 --- a/semihosting/config.c +++ b/semihosting/config.c @@ -8,7 +8,7 @@ * targets that support it. Architecture specific handling is handled * in target/HW/HW-semi.c * - * Semihosting is sightly strange in that it is also supported by some + * Semihosting is slightly strange in that it is also supported by some * linux-user targets. However in that use case no configuration of * the outputs and command lines is supported. * diff --git a/semihosting/syscalls.c b/semihosting/syscalls.c index 68899ebb1c..d27574a1e2 100644 --- a/semihosting/syscalls.c +++ b/semihosting/syscalls.c @@ -720,7 +720,7 @@ void semihost_sys_read_gf(CPUState *cs, gdb_syscall_complete_cb complete, GuestFD *gf, target_ulong buf, target_ulong len) { /* - * Bound length for 64-bit guests on 32-bit hosts, not overlowing ssize_t. + * Bound length for 64-bit guests on 32-bit hosts, not overflowing ssize_t. * Note the Linux kernel does this with MAX_RW_COUNT, so it's not a bad * idea to do this unconditionally. */ @@ -761,7 +761,7 @@ void semihost_sys_write_gf(CPUState *cs, gdb_syscall_complete_cb complete, GuestFD *gf, target_ulong buf, target_ulong len) { /* - * Bound length for 64-bit guests on 32-bit hosts, not overlowing ssize_t. + * Bound length for 64-bit guests on 32-bit hosts, not overflowing ssize_t. * Note the Linux kernel does this with MAX_RW_COUNT, so it's not a bad * idea to do this unconditionally. */ diff --git a/softmmu/cpus.c b/softmmu/cpus.c index fed20ffb5d..0848e0dbdb 100644 --- a/softmmu/cpus.c +++ b/softmmu/cpus.c @@ -427,12 +427,6 @@ void qemu_wait_io_event(CPUState *cpu) qemu_plugin_vcpu_resume_cb(cpu); } -#ifdef _WIN32 - /* Eat dummy APC queued by cpus_kick_thread. */ - if (hax_enabled()) { - SleepEx(0, TRUE); - } -#endif qemu_wait_io_event_common(cpu); } diff --git a/softmmu/icount.c b/softmmu/icount.c index a5cef9c60a..144e24829c 100644 --- a/softmmu/icount.c +++ b/softmmu/icount.c @@ -325,7 +325,7 @@ void icount_start_warp_timer(void) * vCPU is sleeping and warp can't be started. * It is probably a race condition: notification sent * to vCPU was processed in advance and vCPU went to sleep. - * Therefore we have to wake it up for doing someting. + * Therefore we have to wake it up for doing something. */ if (replay_has_event()) { qemu_clock_notify(QEMU_CLOCK_VIRTUAL); diff --git a/softmmu/ioport.c b/softmmu/ioport.c index b66e0a5a8e..1824aa808c 100644 --- a/softmmu/ioport.c +++ b/softmmu/ioport.c @@ -22,7 +22,7 @@ * THE SOFTWARE. */ /* - * splitted out ioport related stuffs from vl.c. + * split out ioport related stuffs from vl.c. */ #include "qemu/osdep.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index 78b6570f19..3db4fd2680 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -87,7 +87,6 @@ #include "migration/colo.h" #include "migration/postcopy-ram.h" #include "sysemu/kvm.h" -#include "sysemu/hax.h" #include "qapi/qobject-input-visitor.h" #include "qemu/option.h" #include "qemu/config-file.h" @@ -2583,11 +2582,6 @@ static void qemu_init_board(void) drive_check_orphaned(); realtime_init(); - - if (hax_enabled()) { - /* FIXME: why isn't cpu_synchronize_all_post_init enough? */ - hax_sync_vcpus(); - } } static void qemu_create_cli_devices(void) diff --git a/subprojects/berkeley-testfloat-3.wrap b/subprojects/berkeley-testfloat-3.wrap index 6ad80a37b2..c86dc078a8 100644 --- a/subprojects/berkeley-testfloat-3.wrap +++ b/subprojects/berkeley-testfloat-3.wrap @@ -1,5 +1,5 @@ [wrap-git] url = https://gitlab.com/qemu-project/berkeley-testfloat-3 -revision = 40619cbb3bf32872df8c53cc457039229428a263 +revision = e7af9751d9f9fd3b47911f51a5cfd08af256a9ab patch_directory = berkeley-testfloat-3 depth = 1 diff --git a/target/alpha/translate.c b/target/alpha/translate.c index 0839182a1f..9be912c50c 100644 --- a/target/alpha/translate.c +++ b/target/alpha/translate.c @@ -24,7 +24,6 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/translator.h" diff --git a/target/avr/helper.c b/target/avr/helper.c index e6e7d51487..fdc9884ea0 100644 --- a/target/avr/helper.c +++ b/target/avr/helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/address-spaces.h" #include "exec/helper-proto.h" diff --git a/target/cris/op_helper.c b/target/cris/op_helper.c index 40cb74ce73..98a9aaf504 100644 --- a/target/cris/op_helper.c +++ b/target/cris/op_helper.c @@ -24,7 +24,6 @@ #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" //#define CRIS_OP_HELPER_DEBUG diff --git a/target/hexagon/translate.c b/target/hexagon/translate.c index 708339198e..c00254e4d5 100644 --- a/target/hexagon/translate.c +++ b/target/hexagon/translate.c @@ -23,7 +23,6 @@ #include "exec/helper-gen.h" #include "exec/helper-proto.h" #include "exec/translation-block.h" -#include "exec/cpu_ldst.h" #include "exec/log.h" #include "internal.h" #include "attribs.h" diff --git a/target/hppa/translate.c b/target/hppa/translate.c index e3af668252..c04dc15228 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -23,7 +23,6 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/translator.h" diff --git a/target/i386/hax/hax-accel-ops.c b/target/i386/hax/hax-accel-ops.c deleted file mode 100644 index 5031096760..0000000000 --- a/target/i386/hax/hax-accel-ops.c +++ /dev/null @@ -1,105 +0,0 @@ -/* - * QEMU HAX support - * - * Copyright IBM, Corp. 2008 - * Red Hat, Inc. 2008 - * - * Authors: - * Anthony Liguori <aliguori@us.ibm.com> - * Glauber Costa <gcosta@redhat.com> - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong<yunhong.jiang@intel.com> - * Xin Xiaohui<xiaohui.xin@intel.com> - * Zhang Xiantao<xiantao.zhang@intel.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include "qemu/error-report.h" -#include "qemu/main-loop.h" -#include "sysemu/runstate.h" -#include "sysemu/cpus.h" -#include "qemu/guest-random.h" - -#include "hax-accel-ops.h" - -static void *hax_cpu_thread_fn(void *arg) -{ - CPUState *cpu = arg; - int r; - - rcu_register_thread(); - qemu_mutex_lock_iothread(); - qemu_thread_get_self(cpu->thread); - - cpu->thread_id = qemu_get_thread_id(); - current_cpu = cpu; - hax_init_vcpu(cpu); - cpu_thread_signal_created(cpu); - qemu_guest_random_seed_thread_part2(cpu->random_seed); - - do { - if (cpu_can_run(cpu)) { - r = hax_smp_cpu_exec(cpu); - if (r == EXCP_DEBUG) { - cpu_handle_guest_debug(cpu); - } - } - - qemu_wait_io_event(cpu); - } while (!cpu->unplug || cpu_can_run(cpu)); - hax_vcpu_destroy(cpu); - cpu_thread_signal_destroyed(cpu); - rcu_unregister_thread(); - return NULL; -} - -static void hax_start_vcpu_thread(CPUState *cpu) -{ - char thread_name[VCPU_THREAD_NAME_SIZE]; - - cpu->thread = g_new0(QemuThread, 1); - cpu->halt_cond = g_new0(QemuCond, 1); - qemu_cond_init(cpu->halt_cond); - - snprintf(thread_name, VCPU_THREAD_NAME_SIZE, "CPU %d/HAX", - cpu->cpu_index); - qemu_thread_create(cpu->thread, thread_name, hax_cpu_thread_fn, - cpu, QEMU_THREAD_JOINABLE); - assert(cpu->accel); -#ifdef _WIN32 - cpu->accel->hThread = qemu_thread_get_handle(cpu->thread); -#endif -} - -static void hax_accel_ops_class_init(ObjectClass *oc, void *data) -{ - AccelOpsClass *ops = ACCEL_OPS_CLASS(oc); - - ops->create_vcpu_thread = hax_start_vcpu_thread; - ops->kick_vcpu_thread = hax_kick_vcpu_thread; - - ops->synchronize_post_reset = hax_cpu_synchronize_post_reset; - ops->synchronize_post_init = hax_cpu_synchronize_post_init; - ops->synchronize_state = hax_cpu_synchronize_state; - ops->synchronize_pre_loadvm = hax_cpu_synchronize_pre_loadvm; -} - -static const TypeInfo hax_accel_ops_type = { - .name = ACCEL_OPS_NAME("hax"), - - .parent = TYPE_ACCEL_OPS, - .class_init = hax_accel_ops_class_init, - .abstract = true, -}; - -static void hax_accel_ops_register_types(void) -{ - type_register_static(&hax_accel_ops_type); -} -type_init(hax_accel_ops_register_types); diff --git a/target/i386/hax/hax-accel-ops.h b/target/i386/hax/hax-accel-ops.h deleted file mode 100644 index 9e357e7b40..0000000000 --- a/target/i386/hax/hax-accel-ops.h +++ /dev/null @@ -1,31 +0,0 @@ -/* - * Accelerator CPUS Interface - * - * Copyright 2020 SUSE LLC - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - */ - -#ifndef TARGET_I386_HAX_ACCEL_OPS_H -#define TARGET_I386_HAX_ACCEL_OPS_H - -#include "sysemu/cpus.h" - -#include "hax-interface.h" -#include "hax-i386.h" - -int hax_init_vcpu(CPUState *cpu); -int hax_smp_cpu_exec(CPUState *cpu); -int hax_populate_ram(uint64_t va, uint64_t size); - -void hax_cpu_synchronize_state(CPUState *cpu); -void hax_cpu_synchronize_post_reset(CPUState *cpu); -void hax_cpu_synchronize_post_init(CPUState *cpu); -void hax_cpu_synchronize_pre_loadvm(CPUState *cpu); - -int hax_vcpu_destroy(CPUState *cpu); -void hax_raise_event(CPUState *cpu); -void hax_reset_vcpu_state(void *opaque); - -#endif /* TARGET_I386_HAX_ACCEL_OPS_H */ diff --git a/target/i386/hax/hax-all.c b/target/i386/hax/hax-all.c deleted file mode 100644 index 18d78e5b6b..0000000000 --- a/target/i386/hax/hax-all.c +++ /dev/null @@ -1,1141 +0,0 @@ -/* - * QEMU HAX support - * - * Copyright IBM, Corp. 2008 - * Red Hat, Inc. 2008 - * - * Authors: - * Anthony Liguori <aliguori@us.ibm.com> - * Glauber Costa <gcosta@redhat.com> - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong<yunhong.jiang@intel.com> - * Xin Xiaohui<xiaohui.xin@intel.com> - * Zhang Xiantao<xiantao.zhang@intel.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -/* - * HAX common code for both windows and darwin - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/address-spaces.h" - -#include "qemu/accel.h" -#include "sysemu/reset.h" -#include "sysemu/runstate.h" -#include "hw/boards.h" - -#include "hax-accel-ops.h" - -#define DEBUG_HAX 0 - -#define DPRINTF(fmt, ...) \ - do { \ - if (DEBUG_HAX) { \ - fprintf(stdout, fmt, ## __VA_ARGS__); \ - } \ - } while (0) - -/* Current version */ -const uint32_t hax_cur_version = 0x4; /* API v4: unmapping and MMIO moves */ -/* Minimum HAX kernel version */ -const uint32_t hax_min_version = 0x4; /* API v4: supports unmapping */ - -bool hax_allowed; - -struct hax_state hax_global; - -static void hax_vcpu_sync_state(CPUArchState *env, int modified); -static int hax_arch_get_registers(CPUArchState *env); - -int valid_hax_tunnel_size(uint16_t size) -{ - return size >= sizeof(struct hax_tunnel); -} - -hax_fd hax_vcpu_get_fd(CPUArchState *env) -{ - AccelCPUState *vcpu = env_cpu(env)->accel; - if (!vcpu) { - return HAX_INVALID_FD; - } - return vcpu->fd; -} - -static int hax_get_capability(struct hax_state *hax) -{ - int ret; - struct hax_capabilityinfo capinfo, *cap = &capinfo; - - ret = hax_capability(hax, cap); - if (ret) { - return ret; - } - - if ((cap->wstatus & HAX_CAP_WORKSTATUS_MASK) == HAX_CAP_STATUS_NOTWORKING) { - if (cap->winfo & HAX_CAP_FAILREASON_VT) { - DPRINTF - ("VTX feature is not enabled, HAX driver will not work.\n"); - } else if (cap->winfo & HAX_CAP_FAILREASON_NX) { - DPRINTF - ("NX feature is not enabled, HAX driver will not work.\n"); - } - return -ENXIO; - - } - - if (!(cap->winfo & HAX_CAP_UG)) { - fprintf(stderr, "UG mode is not supported by the hardware.\n"); - return -ENOTSUP; - } - - hax->supports_64bit_ramblock = !!(cap->winfo & HAX_CAP_64BIT_RAMBLOCK); - - if (cap->wstatus & HAX_CAP_MEMQUOTA) { - if (cap->mem_quota < hax->mem_quota) { - fprintf(stderr, "The VM memory needed exceeds the driver limit.\n"); - return -ENOSPC; - } - } - return 0; -} - -static int hax_version_support(struct hax_state *hax) -{ - int ret; - struct hax_module_version version; - - ret = hax_mod_version(hax, &version); - if (ret < 0) { - return 0; - } - - if (hax_min_version > version.cur_version) { - fprintf(stderr, "Incompatible HAX module version %d,", - version.cur_version); - fprintf(stderr, "requires minimum version %d\n", hax_min_version); - return 0; - } - if (hax_cur_version < version.compat_version) { - fprintf(stderr, "Incompatible QEMU HAX API version %x,", - hax_cur_version); - fprintf(stderr, "requires minimum HAX API version %x\n", - version.compat_version); - return 0; - } - - return 1; -} - -int hax_vcpu_create(int id) -{ - AccelCPUState *vcpu = NULL; - int ret; - - if (!hax_global.vm) { - fprintf(stderr, "vcpu %x created failed, vm is null\n", id); - return -1; - } - - if (hax_global.vm->vcpus[id]) { - fprintf(stderr, "vcpu %x allocated already\n", id); - return 0; - } - - vcpu = g_new0(AccelCPUState, 1); - - ret = hax_host_create_vcpu(hax_global.vm->fd, id); - if (ret) { - fprintf(stderr, "Failed to create vcpu %x\n", id); - goto error; - } - - vcpu->vcpu_id = id; - vcpu->fd = hax_host_open_vcpu(hax_global.vm->id, id); - if (hax_invalid_fd(vcpu->fd)) { - fprintf(stderr, "Failed to open the vcpu\n"); - ret = -ENODEV; - goto error; - } - - hax_global.vm->vcpus[id] = vcpu; - - ret = hax_host_setup_vcpu_channel(vcpu); - if (ret) { - fprintf(stderr, "Invalid hax tunnel size\n"); - ret = -EINVAL; - goto error; - } - return 0; - - error: - /* vcpu and tunnel will be closed automatically */ - if (vcpu && !hax_invalid_fd(vcpu->fd)) { - hax_close_fd(vcpu->fd); - } - - hax_global.vm->vcpus[id] = NULL; - g_free(vcpu); - return -1; -} - -int hax_vcpu_destroy(CPUState *cpu) -{ - AccelCPUState *vcpu = cpu->accel; - - if (!hax_global.vm) { - fprintf(stderr, "vcpu %x destroy failed, vm is null\n", vcpu->vcpu_id); - return -1; - } - - if (!vcpu) { - return 0; - } - - /* - * 1. The hax_tunnel is also destroyed when vcpu is destroyed - * 2. close fd will cause hax module vcpu be cleaned - */ - hax_close_fd(vcpu->fd); - hax_global.vm->vcpus[vcpu->vcpu_id] = NULL; -#ifdef _WIN32 - CloseHandle(vcpu->hThread); -#endif - g_free(vcpu); - cpu->accel = NULL; - return 0; -} - -int hax_init_vcpu(CPUState *cpu) -{ - int ret; - - ret = hax_vcpu_create(cpu->cpu_index); - if (ret < 0) { - fprintf(stderr, "Failed to create HAX vcpu\n"); - exit(-1); - } - - cpu->accel = hax_global.vm->vcpus[cpu->cpu_index]; - cpu->vcpu_dirty = true; - qemu_register_reset(hax_reset_vcpu_state, cpu->env_ptr); - - return ret; -} - -struct hax_vm *hax_vm_create(struct hax_state *hax, int max_cpus) -{ - struct hax_vm *vm; - int vm_id = 0, ret, i; - - if (hax_invalid_fd(hax->fd)) { - return NULL; - } - - if (hax->vm) { - return hax->vm; - } - - if (max_cpus > HAX_MAX_VCPU) { - fprintf(stderr, "Maximum VCPU number QEMU supported is %d\n", HAX_MAX_VCPU); - return NULL; - } - - vm = g_new0(struct hax_vm, 1); - - ret = hax_host_create_vm(hax, &vm_id); - if (ret) { - fprintf(stderr, "Failed to create vm %x\n", ret); - goto error; - } - vm->id = vm_id; - vm->fd = hax_host_open_vm(hax, vm_id); - if (hax_invalid_fd(vm->fd)) { - fprintf(stderr, "Failed to open vm %d\n", vm_id); - goto error; - } - - vm->numvcpus = max_cpus; - vm->vcpus = g_new0(AccelCPUState *, vm->numvcpus); - for (i = 0; i < vm->numvcpus; i++) { - vm->vcpus[i] = NULL; - } - - hax->vm = vm; - return vm; - - error: - g_free(vm); - hax->vm = NULL; - return NULL; -} - -int hax_vm_destroy(struct hax_vm *vm) -{ - int i; - - for (i = 0; i < vm->numvcpus; i++) - if (vm->vcpus[i]) { - fprintf(stderr, "VCPU should be cleaned before vm clean\n"); - return -1; - } - hax_close_fd(vm->fd); - vm->numvcpus = 0; - g_free(vm->vcpus); - g_free(vm); - hax_global.vm = NULL; - return 0; -} - -static int hax_init(ram_addr_t ram_size, int max_cpus) -{ - struct hax_state *hax = NULL; - struct hax_qemu_version qversion; - int ret; - - hax = &hax_global; - - memset(hax, 0, sizeof(struct hax_state)); - hax->mem_quota = ram_size; - - hax->fd = hax_mod_open(); - if (hax_invalid_fd(hax->fd)) { - hax->fd = 0; - ret = -ENODEV; - goto error; - } - - ret = hax_get_capability(hax); - - if (ret) { - if (ret != -ENOSPC) { - ret = -EINVAL; - } - goto error; - } - - if (!hax_version_support(hax)) { - ret = -EINVAL; - goto error; - } - - hax->vm = hax_vm_create(hax, max_cpus); - if (!hax->vm) { - fprintf(stderr, "Failed to create HAX VM\n"); - ret = -EINVAL; - goto error; - } - - hax_memory_init(); - - qversion.cur_version = hax_cur_version; - qversion.min_version = hax_min_version; - hax_notify_qemu_version(hax->vm->fd, &qversion); - - return ret; - error: - if (hax->vm) { - hax_vm_destroy(hax->vm); - } - if (hax->fd) { - hax_mod_close(hax); - } - - return ret; -} - -static int hax_accel_init(MachineState *ms) -{ - int ret = hax_init(ms->ram_size, (int)ms->smp.max_cpus); - - if (ret && (ret != -ENOSPC)) { - fprintf(stderr, "No accelerator found.\n"); - } else { - fprintf(stdout, "HAX is %s and emulator runs in %s mode.\n", - !ret ? "working" : "not working", - !ret ? "fast virt" : "emulation"); - fprintf(stdout, - "NOTE: HAX is deprecated and will be removed in a future release.\n" - " Use 'whpx' (on Windows) or 'hvf' (on macOS) instead.\n"); - } - return ret; -} - -static int hax_handle_fastmmio(CPUArchState *env, struct hax_fastmmio *hft) -{ - if (hft->direction < 2) { - cpu_physical_memory_rw(hft->gpa, &hft->value, hft->size, - hft->direction); - } else { - /* - * HAX API v4 supports transferring data between two MMIO addresses, - * hft->gpa and hft->gpa2 (instructions such as MOVS require this): - * hft->direction == 2: gpa ==> gpa2 - */ - uint64_t value; - cpu_physical_memory_read(hft->gpa, &value, hft->size); - cpu_physical_memory_write(hft->gpa2, &value, hft->size); - } - - return 0; -} - -static int hax_handle_io(CPUArchState *env, uint32_t df, uint16_t port, - int direction, int size, int count, void *buffer) -{ - uint8_t *ptr; - int i; - MemTxAttrs attrs = { 0 }; - - if (!df) { - ptr = buffer; - } else { - ptr = buffer + size * count - size; - } - for (i = 0; i < count; i++) { - address_space_rw(&address_space_io, port, attrs, - ptr, size, direction == HAX_EXIT_IO_OUT); - if (!df) { - ptr += size; - } else { - ptr -= size; - } - } - - return 0; -} - -static int hax_vcpu_interrupt(CPUArchState *env) -{ - CPUState *cpu = env_cpu(env); - AccelCPUState *vcpu = cpu->accel; - struct hax_tunnel *ht = vcpu->tunnel; - - /* - * Try to inject an interrupt if the guest can accept it - * Unlike KVM, HAX kernel check for the eflags, instead of qemu - */ - if (ht->ready_for_interrupt_injection && - (cpu->interrupt_request & CPU_INTERRUPT_HARD)) { - int irq; - - irq = cpu_get_pic_interrupt(env); - if (irq >= 0) { - hax_inject_interrupt(env, irq); - cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; - } - } - - /* If we have an interrupt but the guest is not ready to receive an - * interrupt, request an interrupt window exit. This will - * cause a return to userspace as soon as the guest is ready to - * receive interrupts. */ - if ((cpu->interrupt_request & CPU_INTERRUPT_HARD)) { - ht->request_interrupt_window = 1; - } else { - ht->request_interrupt_window = 0; - } - return 0; -} - -void hax_raise_event(CPUState *cpu) -{ - AccelCPUState *vcpu = cpu->accel; - - if (!vcpu) { - return; - } - vcpu->tunnel->user_event_pending = 1; -} - -/* - * Ask hax kernel module to run the CPU for us till: - * 1. Guest crash or shutdown - * 2. Need QEMU's emulation like guest execute MMIO instruction - * 3. Guest execute HLT - * 4. QEMU have Signal/event pending - * 5. An unknown VMX exit happens - */ -static int hax_vcpu_hax_exec(CPUArchState *env) -{ - int ret = 0; - CPUState *cpu = env_cpu(env); - X86CPU *x86_cpu = X86_CPU(cpu); - AccelCPUState *vcpu = cpu->accel; - struct hax_tunnel *ht = vcpu->tunnel; - - if (!hax_enabled()) { - DPRINTF("Trying to vcpu execute at eip:" TARGET_FMT_lx "\n", env->eip); - return 0; - } - - if (cpu->interrupt_request & CPU_INTERRUPT_POLL) { - cpu->interrupt_request &= ~CPU_INTERRUPT_POLL; - apic_poll_irq(x86_cpu->apic_state); - } - - /* After a vcpu is halted (either because it is an AP and has just been - * reset, or because it has executed the HLT instruction), it will not be - * run (hax_vcpu_run()) until it is unhalted. The next few if blocks check - * for events that may change the halted state of this vcpu: - * a) Maskable interrupt, when RFLAGS.IF is 1; - * Note: env->eflags may not reflect the current RFLAGS state, because - * it is not updated after each hax_vcpu_run(). We cannot afford - * to fail to recognize any unhalt-by-maskable-interrupt event - * (in which case the vcpu will halt forever), and yet we cannot - * afford the overhead of hax_vcpu_sync_state(). The current - * solution is to err on the side of caution and have the HLT - * handler (see case HAX_EXIT_HLT below) unconditionally set the - * IF_MASK bit in env->eflags, which, in effect, disables the - * RFLAGS.IF check. - * b) NMI; - * c) INIT signal; - * d) SIPI signal. - */ - if (((cpu->interrupt_request & CPU_INTERRUPT_HARD) && - (env->eflags & IF_MASK)) || - (cpu->interrupt_request & CPU_INTERRUPT_NMI)) { - cpu->halted = 0; - } - - if (cpu->interrupt_request & CPU_INTERRUPT_INIT) { - DPRINTF("\nhax_vcpu_hax_exec: handling INIT for %d\n", - cpu->cpu_index); - do_cpu_init(x86_cpu); - hax_vcpu_sync_state(env, 1); - } - - if (cpu->interrupt_request & CPU_INTERRUPT_SIPI) { - DPRINTF("hax_vcpu_hax_exec: handling SIPI for %d\n", - cpu->cpu_index); - hax_vcpu_sync_state(env, 0); - do_cpu_sipi(x86_cpu); - hax_vcpu_sync_state(env, 1); - } - - if (cpu->halted) { - /* If this vcpu is halted, we must not ask HAXM to run it. Instead, we - * break out of hax_smp_cpu_exec() as if this vcpu had executed HLT. - * That way, this vcpu thread will be trapped in qemu_wait_io_event(), - * until the vcpu is unhalted. - */ - cpu->exception_index = EXCP_HLT; - return 0; - } - - do { - int hax_ret; - - if (cpu->exit_request) { - ret = 1; - break; - } - - hax_vcpu_interrupt(env); - - qemu_mutex_unlock_iothread(); - cpu_exec_start(cpu); - hax_ret = hax_vcpu_run(vcpu); - cpu_exec_end(cpu); - qemu_mutex_lock_iothread(); - - /* Simply continue the vcpu_run if system call interrupted */ - if (hax_ret == -EINTR || hax_ret == -EAGAIN) { - DPRINTF("io window interrupted\n"); - continue; - } - - if (hax_ret < 0) { - fprintf(stderr, "vcpu run failed for vcpu %x\n", vcpu->vcpu_id); - abort(); - } - switch (ht->_exit_status) { - case HAX_EXIT_IO: - ret = hax_handle_io(env, ht->pio._df, ht->pio._port, - ht->pio._direction, - ht->pio._size, ht->pio._count, vcpu->iobuf); - break; - case HAX_EXIT_FAST_MMIO: - ret = hax_handle_fastmmio(env, (struct hax_fastmmio *) vcpu->iobuf); - break; - /* Guest state changed, currently only for shutdown */ - case HAX_EXIT_STATECHANGE: - fprintf(stdout, "VCPU shutdown request\n"); - qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); - hax_vcpu_sync_state(env, 0); - ret = 1; - break; - case HAX_EXIT_UNKNOWN_VMEXIT: - fprintf(stderr, "Unknown VMX exit %x from guest\n", - ht->_exit_reason); - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - hax_vcpu_sync_state(env, 0); - cpu_dump_state(cpu, stderr, 0); - ret = -1; - break; - case HAX_EXIT_HLT: - if (!(cpu->interrupt_request & CPU_INTERRUPT_HARD) && - !(cpu->interrupt_request & CPU_INTERRUPT_NMI)) { - /* hlt instruction with interrupt disabled is shutdown */ - env->eflags |= IF_MASK; - cpu->halted = 1; - cpu->exception_index = EXCP_HLT; - ret = 1; - } - break; - /* these situations will continue to hax module */ - case HAX_EXIT_INTERRUPT: - case HAX_EXIT_PAUSED: - break; - case HAX_EXIT_MMIO: - /* Should not happen on UG system */ - fprintf(stderr, "HAX: unsupported MMIO emulation\n"); - ret = -1; - break; - case HAX_EXIT_REAL: - /* Should not happen on UG system */ - fprintf(stderr, "HAX: unimplemented real mode emulation\n"); - ret = -1; - break; - default: - fprintf(stderr, "Unknown exit %x from HAX\n", ht->_exit_status); - qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); - hax_vcpu_sync_state(env, 0); - cpu_dump_state(cpu, stderr, 0); - ret = 1; - break; - } - } while (!ret); - - if (cpu->exit_request) { - cpu->exit_request = 0; - cpu->exception_index = EXCP_INTERRUPT; - } - return ret < 0; -} - -static void do_hax_cpu_synchronize_state(CPUState *cpu, run_on_cpu_data arg) -{ - CPUArchState *env = cpu->env_ptr; - - hax_arch_get_registers(env); - cpu->vcpu_dirty = true; -} - -void hax_cpu_synchronize_state(CPUState *cpu) -{ - if (!cpu->vcpu_dirty) { - run_on_cpu(cpu, do_hax_cpu_synchronize_state, RUN_ON_CPU_NULL); - } -} - -static void do_hax_cpu_synchronize_post_reset(CPUState *cpu, - run_on_cpu_data arg) -{ - CPUArchState *env = cpu->env_ptr; - - hax_vcpu_sync_state(env, 1); - cpu->vcpu_dirty = false; -} - -void hax_cpu_synchronize_post_reset(CPUState *cpu) -{ - run_on_cpu(cpu, do_hax_cpu_synchronize_post_reset, RUN_ON_CPU_NULL); -} - -static void do_hax_cpu_synchronize_post_init(CPUState *cpu, run_on_cpu_data arg) -{ - CPUArchState *env = cpu->env_ptr; - - hax_vcpu_sync_state(env, 1); - cpu->vcpu_dirty = false; -} - -void hax_cpu_synchronize_post_init(CPUState *cpu) -{ - run_on_cpu(cpu, do_hax_cpu_synchronize_post_init, RUN_ON_CPU_NULL); -} - -static void do_hax_cpu_synchronize_pre_loadvm(CPUState *cpu, run_on_cpu_data arg) -{ - cpu->vcpu_dirty = true; -} - -void hax_cpu_synchronize_pre_loadvm(CPUState *cpu) -{ - run_on_cpu(cpu, do_hax_cpu_synchronize_pre_loadvm, RUN_ON_CPU_NULL); -} - -int hax_smp_cpu_exec(CPUState *cpu) -{ - CPUArchState *env = cpu->env_ptr; - int fatal; - int ret; - - while (1) { - if (cpu->exception_index >= EXCP_INTERRUPT) { - ret = cpu->exception_index; - cpu->exception_index = -1; - break; - } - - fatal = hax_vcpu_hax_exec(env); - - if (fatal) { - fprintf(stderr, "Unsupported HAX vcpu return\n"); - abort(); - } - } - - return ret; -} - -static void set_v8086_seg(struct segment_desc_t *lhs, const SegmentCache *rhs) -{ - memset(lhs, 0, sizeof(struct segment_desc_t)); - lhs->selector = rhs->selector; - lhs->base = rhs->base; - lhs->limit = rhs->limit; - lhs->type = 3; - lhs->present = 1; - lhs->dpl = 3; - lhs->operand_size = 0; - lhs->desc = 1; - lhs->long_mode = 0; - lhs->granularity = 0; - lhs->available = 0; -} - -static void get_seg(SegmentCache *lhs, const struct segment_desc_t *rhs) -{ - lhs->selector = rhs->selector; - lhs->base = rhs->base; - lhs->limit = rhs->limit; - lhs->flags = (rhs->type << DESC_TYPE_SHIFT) - | (rhs->present * DESC_P_MASK) - | (rhs->dpl << DESC_DPL_SHIFT) - | (rhs->operand_size << DESC_B_SHIFT) - | (rhs->desc * DESC_S_MASK) - | (rhs->long_mode << DESC_L_SHIFT) - | (rhs->granularity * DESC_G_MASK) | (rhs->available * DESC_AVL_MASK); -} - -static void set_seg(struct segment_desc_t *lhs, const SegmentCache *rhs) -{ - unsigned flags = rhs->flags; - - memset(lhs, 0, sizeof(struct segment_desc_t)); - lhs->selector = rhs->selector; - lhs->base = rhs->base; - lhs->limit = rhs->limit; - lhs->type = (flags >> DESC_TYPE_SHIFT) & 15; - lhs->present = (flags & DESC_P_MASK) != 0; - lhs->dpl = rhs->selector & 3; - lhs->operand_size = (flags >> DESC_B_SHIFT) & 1; - lhs->desc = (flags & DESC_S_MASK) != 0; - lhs->long_mode = (flags >> DESC_L_SHIFT) & 1; - lhs->granularity = (flags & DESC_G_MASK) != 0; - lhs->available = (flags & DESC_AVL_MASK) != 0; -} - -static void hax_getput_reg(uint64_t *hax_reg, target_ulong *qemu_reg, int set) -{ - target_ulong reg = *hax_reg; - - if (set) { - *hax_reg = *qemu_reg; - } else { - *qemu_reg = reg; - } -} - -/* The sregs has been synced with HAX kernel already before this call */ -static int hax_get_segments(CPUArchState *env, struct vcpu_state_t *sregs) -{ - get_seg(&env->segs[R_CS], &sregs->_cs); - get_seg(&env->segs[R_DS], &sregs->_ds); - get_seg(&env->segs[R_ES], &sregs->_es); - get_seg(&env->segs[R_FS], &sregs->_fs); - get_seg(&env->segs[R_GS], &sregs->_gs); - get_seg(&env->segs[R_SS], &sregs->_ss); - - get_seg(&env->tr, &sregs->_tr); - get_seg(&env->ldt, &sregs->_ldt); - env->idt.limit = sregs->_idt.limit; - env->idt.base = sregs->_idt.base; - env->gdt.limit = sregs->_gdt.limit; - env->gdt.base = sregs->_gdt.base; - return 0; -} - -static int hax_set_segments(CPUArchState *env, struct vcpu_state_t *sregs) -{ - if ((env->eflags & VM_MASK)) { - set_v8086_seg(&sregs->_cs, &env->segs[R_CS]); - set_v8086_seg(&sregs->_ds, &env->segs[R_DS]); - set_v8086_seg(&sregs->_es, &env->segs[R_ES]); - set_v8086_seg(&sregs->_fs, &env->segs[R_FS]); - set_v8086_seg(&sregs->_gs, &env->segs[R_GS]); - set_v8086_seg(&sregs->_ss, &env->segs[R_SS]); - } else { - set_seg(&sregs->_cs, &env->segs[R_CS]); - set_seg(&sregs->_ds, &env->segs[R_DS]); - set_seg(&sregs->_es, &env->segs[R_ES]); - set_seg(&sregs->_fs, &env->segs[R_FS]); - set_seg(&sregs->_gs, &env->segs[R_GS]); - set_seg(&sregs->_ss, &env->segs[R_SS]); - - if (env->cr[0] & CR0_PE_MASK) { - /* force ss cpl to cs cpl */ - sregs->_ss.selector = (sregs->_ss.selector & ~3) | - (sregs->_cs.selector & 3); - sregs->_ss.dpl = sregs->_ss.selector & 3; - } - } - - set_seg(&sregs->_tr, &env->tr); - set_seg(&sregs->_ldt, &env->ldt); - sregs->_idt.limit = env->idt.limit; - sregs->_idt.base = env->idt.base; - sregs->_gdt.limit = env->gdt.limit; - sregs->_gdt.base = env->gdt.base; - return 0; -} - -static int hax_sync_vcpu_register(CPUArchState *env, int set) -{ - struct vcpu_state_t regs; - int ret; - memset(®s, 0, sizeof(struct vcpu_state_t)); - - if (!set) { - ret = hax_sync_vcpu_state(env, ®s, 0); - if (ret < 0) { - return -1; - } - } - - /* generic register */ - hax_getput_reg(®s._rax, &env->regs[R_EAX], set); - hax_getput_reg(®s._rbx, &env->regs[R_EBX], set); - hax_getput_reg(®s._rcx, &env->regs[R_ECX], set); - hax_getput_reg(®s._rdx, &env->regs[R_EDX], set); - hax_getput_reg(®s._rsi, &env->regs[R_ESI], set); - hax_getput_reg(®s._rdi, &env->regs[R_EDI], set); - hax_getput_reg(®s._rsp, &env->regs[R_ESP], set); - hax_getput_reg(®s._rbp, &env->regs[R_EBP], set); -#ifdef TARGET_X86_64 - hax_getput_reg(®s._r8, &env->regs[8], set); - hax_getput_reg(®s._r9, &env->regs[9], set); - hax_getput_reg(®s._r10, &env->regs[10], set); - hax_getput_reg(®s._r11, &env->regs[11], set); - hax_getput_reg(®s._r12, &env->regs[12], set); - hax_getput_reg(®s._r13, &env->regs[13], set); - hax_getput_reg(®s._r14, &env->regs[14], set); - hax_getput_reg(®s._r15, &env->regs[15], set); -#endif - hax_getput_reg(®s._rflags, &env->eflags, set); - hax_getput_reg(®s._rip, &env->eip, set); - - if (set) { - regs._cr0 = env->cr[0]; - regs._cr2 = env->cr[2]; - regs._cr3 = env->cr[3]; - regs._cr4 = env->cr[4]; - hax_set_segments(env, ®s); - } else { - env->cr[0] = regs._cr0; - env->cr[2] = regs._cr2; - env->cr[3] = regs._cr3; - env->cr[4] = regs._cr4; - hax_get_segments(env, ®s); - } - - if (set) { - ret = hax_sync_vcpu_state(env, ®s, 1); - if (ret < 0) { - return -1; - } - } - return 0; -} - -static void hax_msr_entry_set(struct vmx_msr *item, uint32_t index, - uint64_t value) -{ - item->entry = index; - item->value = value; -} - -static int hax_get_msrs(CPUArchState *env) -{ - struct hax_msr_data md; - struct vmx_msr *msrs = md.entries; - int ret, i, n; - - n = 0; - msrs[n++].entry = MSR_IA32_SYSENTER_CS; - msrs[n++].entry = MSR_IA32_SYSENTER_ESP; - msrs[n++].entry = MSR_IA32_SYSENTER_EIP; - msrs[n++].entry = MSR_IA32_TSC; -#ifdef TARGET_X86_64 - msrs[n++].entry = MSR_EFER; - msrs[n++].entry = MSR_STAR; - msrs[n++].entry = MSR_LSTAR; - msrs[n++].entry = MSR_CSTAR; - msrs[n++].entry = MSR_FMASK; - msrs[n++].entry = MSR_KERNELGSBASE; -#endif - md.nr_msr = n; - ret = hax_sync_msr(env, &md, 0); - if (ret < 0) { - return ret; - } - - for (i = 0; i < md.done; i++) { - switch (msrs[i].entry) { - case MSR_IA32_SYSENTER_CS: - env->sysenter_cs = msrs[i].value; - break; - case MSR_IA32_SYSENTER_ESP: - env->sysenter_esp = msrs[i].value; - break; - case MSR_IA32_SYSENTER_EIP: - env->sysenter_eip = msrs[i].value; - break; - case MSR_IA32_TSC: - env->tsc = msrs[i].value; - break; -#ifdef TARGET_X86_64 - case MSR_EFER: - env->efer = msrs[i].value; - break; - case MSR_STAR: - env->star = msrs[i].value; - break; - case MSR_LSTAR: - env->lstar = msrs[i].value; - break; - case MSR_CSTAR: - env->cstar = msrs[i].value; - break; - case MSR_FMASK: - env->fmask = msrs[i].value; - break; - case MSR_KERNELGSBASE: - env->kernelgsbase = msrs[i].value; - break; -#endif - } - } - - return 0; -} - -static int hax_set_msrs(CPUArchState *env) -{ - struct hax_msr_data md; - struct vmx_msr *msrs; - msrs = md.entries; - int n = 0; - - memset(&md, 0, sizeof(struct hax_msr_data)); - hax_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_CS, env->sysenter_cs); - hax_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_ESP, env->sysenter_esp); - hax_msr_entry_set(&msrs[n++], MSR_IA32_SYSENTER_EIP, env->sysenter_eip); - hax_msr_entry_set(&msrs[n++], MSR_IA32_TSC, env->tsc); -#ifdef TARGET_X86_64 - hax_msr_entry_set(&msrs[n++], MSR_EFER, env->efer); - hax_msr_entry_set(&msrs[n++], MSR_STAR, env->star); - hax_msr_entry_set(&msrs[n++], MSR_LSTAR, env->lstar); - hax_msr_entry_set(&msrs[n++], MSR_CSTAR, env->cstar); - hax_msr_entry_set(&msrs[n++], MSR_FMASK, env->fmask); - hax_msr_entry_set(&msrs[n++], MSR_KERNELGSBASE, env->kernelgsbase); -#endif - md.nr_msr = n; - md.done = 0; - - return hax_sync_msr(env, &md, 1); -} - -static int hax_get_fpu(CPUArchState *env) -{ - struct fx_layout fpu; - int i, ret; - - ret = hax_sync_fpu(env, &fpu, 0); - if (ret < 0) { - return ret; - } - - env->fpstt = (fpu.fsw >> 11) & 7; - env->fpus = fpu.fsw; - env->fpuc = fpu.fcw; - for (i = 0; i < 8; ++i) { - env->fptags[i] = !((fpu.ftw >> i) & 1); - } - memcpy(env->fpregs, fpu.st_mm, sizeof(env->fpregs)); - - for (i = 0; i < 8; i++) { - env->xmm_regs[i].ZMM_Q(0) = ldq_p(&fpu.mmx_1[i][0]); - env->xmm_regs[i].ZMM_Q(1) = ldq_p(&fpu.mmx_1[i][8]); - if (CPU_NB_REGS > 8) { - env->xmm_regs[i + 8].ZMM_Q(0) = ldq_p(&fpu.mmx_2[i][0]); - env->xmm_regs[i + 8].ZMM_Q(1) = ldq_p(&fpu.mmx_2[i][8]); - } - } - env->mxcsr = fpu.mxcsr; - - return 0; -} - -static int hax_set_fpu(CPUArchState *env) -{ - struct fx_layout fpu; - int i; - - memset(&fpu, 0, sizeof(fpu)); - fpu.fsw = env->fpus & ~(7 << 11); - fpu.fsw |= (env->fpstt & 7) << 11; - fpu.fcw = env->fpuc; - - for (i = 0; i < 8; ++i) { - fpu.ftw |= (!env->fptags[i]) << i; - } - - memcpy(fpu.st_mm, env->fpregs, sizeof(env->fpregs)); - for (i = 0; i < 8; i++) { - stq_p(&fpu.mmx_1[i][0], env->xmm_regs[i].ZMM_Q(0)); - stq_p(&fpu.mmx_1[i][8], env->xmm_regs[i].ZMM_Q(1)); - if (CPU_NB_REGS > 8) { - stq_p(&fpu.mmx_2[i][0], env->xmm_regs[i + 8].ZMM_Q(0)); - stq_p(&fpu.mmx_2[i][8], env->xmm_regs[i + 8].ZMM_Q(1)); - } - } - - fpu.mxcsr = env->mxcsr; - - return hax_sync_fpu(env, &fpu, 1); -} - -static int hax_arch_get_registers(CPUArchState *env) -{ - int ret; - - ret = hax_sync_vcpu_register(env, 0); - if (ret < 0) { - return ret; - } - - ret = hax_get_fpu(env); - if (ret < 0) { - return ret; - } - - ret = hax_get_msrs(env); - if (ret < 0) { - return ret; - } - - x86_update_hflags(env); - return 0; -} - -static int hax_arch_set_registers(CPUArchState *env) -{ - int ret; - ret = hax_sync_vcpu_register(env, 1); - - if (ret < 0) { - fprintf(stderr, "Failed to sync vcpu reg\n"); - return ret; - } - ret = hax_set_fpu(env); - if (ret < 0) { - fprintf(stderr, "FPU failed\n"); - return ret; - } - ret = hax_set_msrs(env); - if (ret < 0) { - fprintf(stderr, "MSR failed\n"); - return ret; - } - - return 0; -} - -static void hax_vcpu_sync_state(CPUArchState *env, int modified) -{ - if (hax_enabled()) { - if (modified) { - hax_arch_set_registers(env); - } else { - hax_arch_get_registers(env); - } - } -} - -/* - * much simpler than kvm, at least in first stage because: - * We don't need consider the device pass-through, we don't need - * consider the framebuffer, and we may even remove the bios at all - */ -int hax_sync_vcpus(void) -{ - if (hax_enabled()) { - CPUState *cpu; - - cpu = first_cpu; - if (!cpu) { - return 0; - } - - for (; cpu != NULL; cpu = CPU_NEXT(cpu)) { - int ret; - - ret = hax_arch_set_registers(cpu->env_ptr); - if (ret < 0) { - return ret; - } - } - } - - return 0; -} - -void hax_reset_vcpu_state(void *opaque) -{ - CPUState *cpu; - for (cpu = first_cpu; cpu != NULL; cpu = CPU_NEXT(cpu)) { - cpu->accel->tunnel->user_event_pending = 0; - cpu->accel->tunnel->ready_for_interrupt_injection = 0; - } -} - -static void hax_accel_class_init(ObjectClass *oc, void *data) -{ - AccelClass *ac = ACCEL_CLASS(oc); - ac->name = "HAX"; - ac->init_machine = hax_accel_init; - ac->allowed = &hax_allowed; -} - -static const TypeInfo hax_accel_type = { - .name = ACCEL_CLASS_NAME("hax"), - .parent = TYPE_ACCEL, - .class_init = hax_accel_class_init, -}; - -static void hax_type_init(void) -{ - type_register_static(&hax_accel_type); -} - -type_init(hax_type_init); diff --git a/target/i386/hax/hax-i386.h b/target/i386/hax/hax-i386.h deleted file mode 100644 index 87153f40ab..0000000000 --- a/target/i386/hax/hax-i386.h +++ /dev/null @@ -1,98 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong<yunhong.jiang@intel.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -#ifndef HAX_I386_H -#define HAX_I386_H - -#include "cpu.h" -#include "sysemu/hax.h" - -#ifdef CONFIG_POSIX -typedef int hax_fd; -#endif - -#ifdef CONFIG_WIN32 -typedef HANDLE hax_fd; -#endif - -extern struct hax_state hax_global; - -struct AccelCPUState { -#ifdef _WIN32 - HANDLE hThread; -#endif - hax_fd fd; - int vcpu_id; - struct hax_tunnel *tunnel; - unsigned char *iobuf; -}; - -struct hax_state { - hax_fd fd; /* the global hax device interface */ - uint32_t version; - struct hax_vm *vm; - uint64_t mem_quota; - bool supports_64bit_ramblock; -}; - -#define HAX_MAX_VCPU 0x10 - -struct hax_vm { - hax_fd fd; - int id; - int numvcpus; - AccelCPUState **vcpus; -}; - -/* Functions exported to host specific mode */ -hax_fd hax_vcpu_get_fd(CPUArchState *env); -int valid_hax_tunnel_size(uint16_t size); - -/* Host specific functions */ -int hax_mod_version(struct hax_state *hax, struct hax_module_version *version); -int hax_inject_interrupt(CPUArchState *env, int vector); -struct hax_vm *hax_vm_create(struct hax_state *hax, int max_cpus); -int hax_vcpu_run(AccelCPUState *vcpu); -int hax_vcpu_create(int id); -void hax_kick_vcpu_thread(CPUState *cpu); - -int hax_sync_vcpu_state(CPUArchState *env, struct vcpu_state_t *state, - int set); -int hax_sync_msr(CPUArchState *env, struct hax_msr_data *msrs, int set); -int hax_sync_fpu(CPUArchState *env, struct fx_layout *fl, int set); - -int hax_vm_destroy(struct hax_vm *vm); -int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap); -int hax_notify_qemu_version(hax_fd vm_fd, struct hax_qemu_version *qversion); -int hax_set_ram(uint64_t start_pa, uint32_t size, uint64_t host_va, int flags); - -/* Common host function */ -int hax_host_create_vm(struct hax_state *hax, int *vm_id); -hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id); -int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid); -hax_fd hax_host_open_vcpu(int vmid, int vcpuid); -int hax_host_setup_vcpu_channel(AccelCPUState *vcpu); -hax_fd hax_mod_open(void); -void hax_memory_init(void); - - -#ifdef CONFIG_POSIX -#include "hax-posix.h" -#endif - -#ifdef CONFIG_WIN32 -#include "hax-windows.h" -#endif - -#include "hax-interface.h" - -#endif diff --git a/target/i386/hax/hax-interface.h b/target/i386/hax/hax-interface.h deleted file mode 100644 index 537ae084e9..0000000000 --- a/target/i386/hax/hax-interface.h +++ /dev/null @@ -1,369 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong<yunhong.jiang@intel.com> - * Xin Xiaohui<xiaohui.xin@intel.com> - * Zhang Xiantao<xiantao.zhang@intel.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -/* Interface with HAX kernel module */ - -#ifndef HAX_INTERFACE_H -#define HAX_INTERFACE_H - -/* fx_layout has 3 formats table 3-56, 512bytes */ -struct fx_layout { - uint16_t fcw; - uint16_t fsw; - uint8_t ftw; - uint8_t res1; - uint16_t fop; - union { - struct { - uint32_t fip; - uint16_t fcs; - uint16_t res2; - }; - uint64_t fpu_ip; - }; - union { - struct { - uint32_t fdp; - uint16_t fds; - uint16_t res3; - }; - uint64_t fpu_dp; - }; - uint32_t mxcsr; - uint32_t mxcsr_mask; - uint8_t st_mm[8][16]; - uint8_t mmx_1[8][16]; - uint8_t mmx_2[8][16]; - uint8_t pad[96]; -} __attribute__ ((aligned(8))); - -struct vmx_msr { - uint64_t entry; - uint64_t value; -} __attribute__ ((__packed__)); - -/* - * Fixed array is not good, but it makes Mac support a bit easier by avoiding - * memory map or copyin staff. - */ -#define HAX_MAX_MSR_ARRAY 0x20 -struct hax_msr_data { - uint16_t nr_msr; - uint16_t done; - uint16_t pad[2]; - struct vmx_msr entries[HAX_MAX_MSR_ARRAY]; -} __attribute__ ((__packed__)); - -union interruptibility_state_t { - uint32_t raw; - struct { - uint32_t sti_blocking:1; - uint32_t movss_blocking:1; - uint32_t smi_blocking:1; - uint32_t nmi_blocking:1; - uint32_t reserved:28; - }; - uint64_t pad; -}; - -typedef union interruptibility_state_t interruptibility_state_t; - -/* Segment descriptor */ -struct segment_desc_t { - uint16_t selector; - uint16_t _dummy; - uint32_t limit; - uint64_t base; - union { - struct { - uint32_t type:4; - uint32_t desc:1; - uint32_t dpl:2; - uint32_t present:1; - uint32_t:4; - uint32_t available:1; - uint32_t long_mode:1; - uint32_t operand_size:1; - uint32_t granularity:1; - uint32_t null:1; - uint32_t:15; - }; - uint32_t ar; - }; - uint32_t ipad; -}; - -typedef struct segment_desc_t segment_desc_t; - -struct vcpu_state_t { - union { - uint64_t _regs[16]; - struct { - union { - struct { - uint8_t _al, _ah; - }; - uint16_t _ax; - uint32_t _eax; - uint64_t _rax; - }; - union { - struct { - uint8_t _cl, _ch; - }; - uint16_t _cx; - uint32_t _ecx; - uint64_t _rcx; - }; - union { - struct { - uint8_t _dl, _dh; - }; - uint16_t _dx; - uint32_t _edx; - uint64_t _rdx; - }; - union { - struct { - uint8_t _bl, _bh; - }; - uint16_t _bx; - uint32_t _ebx; - uint64_t _rbx; - }; - union { - uint16_t _sp; - uint32_t _esp; - uint64_t _rsp; - }; - union { - uint16_t _bp; - uint32_t _ebp; - uint64_t _rbp; - }; - union { - uint16_t _si; - uint32_t _esi; - uint64_t _rsi; - }; - union { - uint16_t _di; - uint32_t _edi; - uint64_t _rdi; - }; - - uint64_t _r8; - uint64_t _r9; - uint64_t _r10; - uint64_t _r11; - uint64_t _r12; - uint64_t _r13; - uint64_t _r14; - uint64_t _r15; - }; - }; - - union { - uint32_t _eip; - uint64_t _rip; - }; - - union { - uint32_t _eflags; - uint64_t _rflags; - }; - - segment_desc_t _cs; - segment_desc_t _ss; - segment_desc_t _ds; - segment_desc_t _es; - segment_desc_t _fs; - segment_desc_t _gs; - segment_desc_t _ldt; - segment_desc_t _tr; - - segment_desc_t _gdt; - segment_desc_t _idt; - - uint64_t _cr0; - uint64_t _cr2; - uint64_t _cr3; - uint64_t _cr4; - - uint64_t _dr0; - uint64_t _dr1; - uint64_t _dr2; - uint64_t _dr3; - uint64_t _dr6; - uint64_t _dr7; - uint64_t _pde; - - uint32_t _efer; - - uint32_t _sysenter_cs; - uint64_t _sysenter_eip; - uint64_t _sysenter_esp; - - uint32_t _activity_state; - uint32_t pad; - interruptibility_state_t _interruptibility_state; -}; - -/* HAX exit status */ -enum exit_status { - /* IO port request */ - HAX_EXIT_IO = 1, - /* MMIO instruction emulation */ - HAX_EXIT_MMIO, - /* QEMU emulation mode request, currently means guest enter non-PG mode */ - HAX_EXIT_REAL, - /* - * Interrupt window open, qemu can inject interrupt now - * Also used when signal pending since at that time qemu usually need - * check interrupt - */ - HAX_EXIT_INTERRUPT, - /* Unknown vmexit, mostly trigger reboot */ - HAX_EXIT_UNKNOWN_VMEXIT, - /* HALT from guest */ - HAX_EXIT_HLT, - /* Reboot request, like because of tripple fault in guest */ - HAX_EXIT_STATECHANGE, - /* the vcpu is now only paused when destroy, so simply return to hax */ - HAX_EXIT_PAUSED, - HAX_EXIT_FAST_MMIO, -}; - -/* - * The interface definition: - * 1. vcpu_run execute will return 0 on success, otherwise mean failed - * 2. exit_status return the exit reason, as stated in enum exit_status - * 3. exit_reason is the vmx exit reason - */ -struct hax_tunnel { - uint32_t _exit_reason; - uint32_t _exit_flag; - uint32_t _exit_status; - uint32_t user_event_pending; - int ready_for_interrupt_injection; - int request_interrupt_window; - union { - struct { - /* 0: read, 1: write */ -#define HAX_EXIT_IO_IN 1 -#define HAX_EXIT_IO_OUT 0 - uint8_t _direction; - uint8_t _df; - uint16_t _size; - uint16_t _port; - uint16_t _count; - uint8_t _flags; - uint8_t _pad0; - uint16_t _pad1; - uint32_t _pad2; - uint64_t _vaddr; - } pio; - struct { - uint64_t gla; - } mmio; - struct { - } state; - }; -} __attribute__ ((__packed__)); - -struct hax_module_version { - uint32_t compat_version; - uint32_t cur_version; -} __attribute__ ((__packed__)); - -/* This interface is support only after API version 2 */ -struct hax_qemu_version { - /* Current API version in QEMU */ - uint32_t cur_version; - /* The minimum API version supported by QEMU */ - uint32_t min_version; -} __attribute__ ((__packed__)); - -/* The mac specfic interface to qemu, mostly is ioctl related */ -struct hax_tunnel_info { - uint64_t va; - uint64_t io_va; - uint16_t size; - uint16_t pad[3]; -} __attribute__ ((__packed__)); - -struct hax_alloc_ram_info { - uint32_t size; - uint32_t pad; - uint64_t va; -} __attribute__ ((__packed__)); - -struct hax_ramblock_info { - uint64_t start_va; - uint64_t size; - uint64_t reserved; -} __attribute__ ((__packed__)); - -#define HAX_RAM_INFO_ROM 0x01 /* Read-Only */ -#define HAX_RAM_INFO_INVALID 0x80 /* Unmapped, usually used for MMIO */ -struct hax_set_ram_info { - uint64_t pa_start; - uint32_t size; - uint8_t flags; - uint8_t pad[3]; - uint64_t va; -} __attribute__ ((__packed__)); - -#define HAX_CAP_STATUS_WORKING 0x1 -#define HAX_CAP_STATUS_NOTWORKING 0x0 -#define HAX_CAP_WORKSTATUS_MASK 0x1 - -#define HAX_CAP_FAILREASON_VT 0x1 -#define HAX_CAP_FAILREASON_NX 0x2 - -#define HAX_CAP_MEMQUOTA 0x2 -#define HAX_CAP_UG 0x4 -#define HAX_CAP_64BIT_RAMBLOCK 0x8 - -struct hax_capabilityinfo { - /* bit 0: 1 - working - * 0 - not working, possibly because NT/NX disabled - * bit 1: 1 - memory limitation working - * 0 - no memory limitation - */ - uint16_t wstatus; - /* valid when not working - * bit 0: VT not enabeld - * bit 1: NX not enabled*/ - uint16_t winfo; - uint32_t pad; - uint64_t mem_quota; -} __attribute__ ((__packed__)); - -struct hax_fastmmio { - uint64_t gpa; - union { - uint64_t value; - uint64_t gpa2; /* since HAX API v4 */ - }; - uint8_t size; - uint8_t direction; - uint16_t reg_index; - uint32_t pad0; - uint64_t _cr0; - uint64_t _cr2; - uint64_t _cr3; - uint64_t _cr4; -} __attribute__ ((__packed__)); -#endif diff --git a/target/i386/hax/hax-mem.c b/target/i386/hax/hax-mem.c deleted file mode 100644 index bb5ffbc9ac..0000000000 --- a/target/i386/hax/hax-mem.c +++ /dev/null @@ -1,323 +0,0 @@ -/* - * HAX memory mapping operations - * - * Copyright (c) 2015-16 Intel Corporation - * Copyright 2016 Google, Inc. - * - * This work is licensed under the terms of the GNU GPL, version 2. See - * the COPYING file in the top-level directory. - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "exec/address-spaces.h" -#include "qemu/error-report.h" - -#include "hax-accel-ops.h" -#include "qemu/queue.h" - -#define DEBUG_HAX_MEM 0 - -#define DPRINTF(fmt, ...) \ - do { \ - if (DEBUG_HAX_MEM) { \ - fprintf(stdout, fmt, ## __VA_ARGS__); \ - } \ - } while (0) - -/** - * HAXMapping: describes a pending guest physical memory mapping - * - * @start_pa: a guest physical address marking the start of the region; must be - * page-aligned - * @size: a guest physical address marking the end of the region; must be - * page-aligned - * @host_va: the host virtual address of the start of the mapping - * @flags: mapping parameters e.g. HAX_RAM_INFO_ROM or HAX_RAM_INFO_INVALID - * @entry: additional fields for linking #HAXMapping instances together - */ -typedef struct HAXMapping { - uint64_t start_pa; - uint32_t size; - uint64_t host_va; - int flags; - QTAILQ_ENTRY(HAXMapping) entry; -} HAXMapping; - -/* - * A doubly-linked list (actually a tail queue) of the pending page mappings - * for the ongoing memory transaction. - * - * It is used to optimize the number of page mapping updates done through the - * kernel module. For example, it's effective when a driver is digging an MMIO - * hole inside an existing memory mapping. It will get a deletion of the whole - * region, then the addition of the 2 remaining RAM areas around the hole and - * finally the memory transaction commit. During the commit, it will effectively - * send to the kernel only the removal of the pages from the MMIO hole after - * having computed locally the result of the deletion and additions. - */ -static QTAILQ_HEAD(, HAXMapping) mappings = - QTAILQ_HEAD_INITIALIZER(mappings); - -/** - * hax_mapping_dump_list: dumps @mappings to stdout (for debugging) - */ -static void hax_mapping_dump_list(void) -{ - HAXMapping *entry; - - DPRINTF("%s updates:\n", __func__); - QTAILQ_FOREACH(entry, &mappings, entry) { - DPRINTF("\t%c 0x%016" PRIx64 "->0x%016" PRIx64 " VA 0x%016" PRIx64 - "%s\n", entry->flags & HAX_RAM_INFO_INVALID ? '-' : '+', - entry->start_pa, entry->start_pa + entry->size, entry->host_va, - entry->flags & HAX_RAM_INFO_ROM ? " ROM" : ""); - } -} - -static void hax_insert_mapping_before(HAXMapping *next, uint64_t start_pa, - uint32_t size, uint64_t host_va, - uint8_t flags) -{ - HAXMapping *entry; - - entry = g_malloc0(sizeof(*entry)); - entry->start_pa = start_pa; - entry->size = size; - entry->host_va = host_va; - entry->flags = flags; - if (!next) { - QTAILQ_INSERT_TAIL(&mappings, entry, entry); - } else { - QTAILQ_INSERT_BEFORE(next, entry, entry); - } -} - -static bool hax_mapping_is_opposite(HAXMapping *entry, uint64_t host_va, - uint8_t flags) -{ - /* removed then added without change for the read-only flag */ - bool nop_flags = (entry->flags ^ flags) == HAX_RAM_INFO_INVALID; - - return (entry->host_va == host_va) && nop_flags; -} - -static void hax_update_mapping(uint64_t start_pa, uint32_t size, - uint64_t host_va, uint8_t flags) -{ - uint64_t end_pa = start_pa + size; - HAXMapping *entry, *next; - - QTAILQ_FOREACH_SAFE(entry, &mappings, entry, next) { - uint32_t chunk_sz; - if (start_pa >= entry->start_pa + entry->size) { - continue; - } - if (start_pa < entry->start_pa) { - chunk_sz = end_pa <= entry->start_pa ? size - : entry->start_pa - start_pa; - hax_insert_mapping_before(entry, start_pa, chunk_sz, - host_va, flags); - start_pa += chunk_sz; - host_va += chunk_sz; - size -= chunk_sz; - } else if (start_pa > entry->start_pa) { - /* split the existing chunk at start_pa */ - chunk_sz = start_pa - entry->start_pa; - hax_insert_mapping_before(entry, entry->start_pa, chunk_sz, - entry->host_va, entry->flags); - entry->start_pa += chunk_sz; - entry->host_va += chunk_sz; - entry->size -= chunk_sz; - } - /* now start_pa == entry->start_pa */ - chunk_sz = MIN(size, entry->size); - if (chunk_sz) { - bool nop = hax_mapping_is_opposite(entry, host_va, flags); - bool partial = chunk_sz < entry->size; - if (partial) { - /* remove the beginning of the existing chunk */ - entry->start_pa += chunk_sz; - entry->host_va += chunk_sz; - entry->size -= chunk_sz; - if (!nop) { - hax_insert_mapping_before(entry, start_pa, chunk_sz, - host_va, flags); - } - } else { /* affects the full mapping entry */ - if (nop) { /* no change to this mapping, remove it */ - QTAILQ_REMOVE(&mappings, entry, entry); - g_free(entry); - } else { /* update mapping properties */ - entry->host_va = host_va; - entry->flags = flags; - } - } - start_pa += chunk_sz; - host_va += chunk_sz; - size -= chunk_sz; - } - if (!size) { /* we are done */ - break; - } - } - if (size) { /* add the leftover */ - hax_insert_mapping_before(NULL, start_pa, size, host_va, flags); - } -} - -static void hax_process_section(MemoryRegionSection *section, uint8_t flags) -{ - MemoryRegion *mr = section->mr; - hwaddr start_pa = section->offset_within_address_space; - ram_addr_t size = int128_get64(section->size); - unsigned int delta; - uint64_t host_va; - uint32_t max_mapping_size; - - /* We only care about RAM and ROM regions */ - if (!memory_region_is_ram(mr)) { - if (memory_region_is_romd(mr)) { - /* HAXM kernel module does not support ROMD yet */ - warn_report("Ignoring ROMD region 0x%016" PRIx64 "->0x%016" PRIx64, - start_pa, start_pa + size); - } - return; - } - - /* Adjust start_pa and size so that they are page-aligned. (Cf - * kvm_set_phys_mem() in kvm-all.c). - */ - delta = qemu_real_host_page_size() - (start_pa & ~qemu_real_host_page_mask()); - delta &= ~qemu_real_host_page_mask(); - if (delta > size) { - return; - } - start_pa += delta; - size -= delta; - size &= qemu_real_host_page_mask(); - if (!size || (start_pa & ~qemu_real_host_page_mask())) { - return; - } - - host_va = (uintptr_t)memory_region_get_ram_ptr(mr) - + section->offset_within_region + delta; - if (memory_region_is_rom(section->mr)) { - flags |= HAX_RAM_INFO_ROM; - } - - /* - * The kernel module interface uses 32-bit sizes: - * https://github.com/intel/haxm/blob/master/API.md#hax_vm_ioctl_set_ram - * - * If the mapping size is longer than 32 bits, we can't process it in one - * call into the kernel. Instead, we split the mapping into smaller ones, - * and call hax_update_mapping() on each. - */ - max_mapping_size = UINT32_MAX & qemu_real_host_page_mask(); - while (size > max_mapping_size) { - hax_update_mapping(start_pa, max_mapping_size, host_va, flags); - start_pa += max_mapping_size; - size -= max_mapping_size; - host_va += max_mapping_size; - } - /* Now size <= max_mapping_size */ - hax_update_mapping(start_pa, (uint32_t)size, host_va, flags); -} - -static void hax_region_add(MemoryListener *listener, - MemoryRegionSection *section) -{ - memory_region_ref(section->mr); - hax_process_section(section, 0); -} - -static void hax_region_del(MemoryListener *listener, - MemoryRegionSection *section) -{ - hax_process_section(section, HAX_RAM_INFO_INVALID); - memory_region_unref(section->mr); -} - -static void hax_transaction_begin(MemoryListener *listener) -{ - g_assert(QTAILQ_EMPTY(&mappings)); -} - -static void hax_transaction_commit(MemoryListener *listener) -{ - if (!QTAILQ_EMPTY(&mappings)) { - HAXMapping *entry, *next; - - if (DEBUG_HAX_MEM) { - hax_mapping_dump_list(); - } - QTAILQ_FOREACH_SAFE(entry, &mappings, entry, next) { - if (entry->flags & HAX_RAM_INFO_INVALID) { - /* for unmapping, put the values expected by the kernel */ - entry->flags = HAX_RAM_INFO_INVALID; - entry->host_va = 0; - } - if (hax_set_ram(entry->start_pa, entry->size, - entry->host_va, entry->flags)) { - fprintf(stderr, "%s: Failed mapping @0x%016" PRIx64 "+0x%" - PRIx32 " flags %02x\n", __func__, entry->start_pa, - entry->size, entry->flags); - } - QTAILQ_REMOVE(&mappings, entry, entry); - g_free(entry); - } - } -} - -/* currently we fake the dirty bitmap sync, always dirty */ -static void hax_log_sync(MemoryListener *listener, - MemoryRegionSection *section) -{ - MemoryRegion *mr = section->mr; - - if (!memory_region_is_ram(mr)) { - /* Skip MMIO regions */ - return; - } - - memory_region_set_dirty(mr, 0, int128_get64(section->size)); -} - -static MemoryListener hax_memory_listener = { - .name = "hax", - .begin = hax_transaction_begin, - .commit = hax_transaction_commit, - .region_add = hax_region_add, - .region_del = hax_region_del, - .log_sync = hax_log_sync, - .priority = MEMORY_LISTENER_PRIORITY_ACCEL, -}; - -static void hax_ram_block_added(RAMBlockNotifier *n, void *host, size_t size, - size_t max_size) -{ - /* - * We must register each RAM block with the HAXM kernel module, or - * hax_set_ram() will fail for any mapping into the RAM block: - * https://github.com/intel/haxm/blob/master/API.md#hax_vm_ioctl_alloc_ram - * - * Old versions of the HAXM kernel module (< 6.2.0) used to preallocate all - * host physical pages for the RAM block as part of this registration - * process, hence the name hax_populate_ram(). - */ - if (hax_populate_ram((uint64_t)(uintptr_t)host, max_size) < 0) { - fprintf(stderr, "HAX failed to populate RAM\n"); - abort(); - } -} - -static struct RAMBlockNotifier hax_ram_notifier = { - .ram_block_added = hax_ram_block_added, -}; - -void hax_memory_init(void) -{ - ram_block_notifier_add(&hax_ram_notifier); - memory_listener_register(&hax_memory_listener, &address_space_memory); -} diff --git a/target/i386/hax/hax-posix.c b/target/i386/hax/hax-posix.c deleted file mode 100644 index a057a5bd94..0000000000 --- a/target/i386/hax/hax-posix.c +++ /dev/null @@ -1,305 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong<yunhong.jiang@intel.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -/* HAX module interface - darwin version */ -#include "qemu/osdep.h" -#include <sys/ioctl.h> - -#include "sysemu/cpus.h" -#include "hax-accel-ops.h" - -hax_fd hax_mod_open(void) -{ - int fd = open("/dev/HAX", O_RDWR); - if (fd == -1) { - fprintf(stderr, "Failed to open the hax module\n"); - } - - qemu_set_cloexec(fd); - - return fd; -} - -int hax_populate_ram(uint64_t va, uint64_t size) -{ - int ret; - - if (!hax_global.vm || !hax_global.vm->fd) { - fprintf(stderr, "Allocate memory before vm create?\n"); - return -EINVAL; - } - - if (hax_global.supports_64bit_ramblock) { - struct hax_ramblock_info ramblock = { - .start_va = va, - .size = size, - .reserved = 0 - }; - - ret = ioctl(hax_global.vm->fd, HAX_VM_IOCTL_ADD_RAMBLOCK, &ramblock); - } else { - struct hax_alloc_ram_info info = { - .size = (uint32_t)size, - .pad = 0, - .va = va - }; - - ret = ioctl(hax_global.vm->fd, HAX_VM_IOCTL_ALLOC_RAM, &info); - } - if (ret < 0) { - fprintf(stderr, "Failed to register RAM block: ret=%d, va=0x%" PRIx64 - ", size=0x%" PRIx64 ", method=%s\n", ret, va, size, - hax_global.supports_64bit_ramblock ? "new" : "legacy"); - return ret; - } - return 0; -} - -int hax_set_ram(uint64_t start_pa, uint32_t size, uint64_t host_va, int flags) -{ - struct hax_set_ram_info info; - int ret; - - info.pa_start = start_pa; - info.size = size; - info.va = host_va; - info.flags = (uint8_t) flags; - - ret = ioctl(hax_global.vm->fd, HAX_VM_IOCTL_SET_RAM, &info); - if (ret < 0) { - return -errno; - } - return 0; -} - -int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap) -{ - int ret; - - ret = ioctl(hax->fd, HAX_IOCTL_CAPABILITY, cap); - if (ret == -1) { - fprintf(stderr, "Failed to get HAX capability\n"); - return -errno; - } - - return 0; -} - -int hax_mod_version(struct hax_state *hax, struct hax_module_version *version) -{ - int ret; - - ret = ioctl(hax->fd, HAX_IOCTL_VERSION, version); - if (ret == -1) { - fprintf(stderr, "Failed to get HAX version\n"); - return -errno; - } - - return 0; -} - -static char *hax_vm_devfs_string(int vm_id) -{ - return g_strdup_printf("/dev/hax_vm/vm%02d", vm_id); -} - -static char *hax_vcpu_devfs_string(int vm_id, int vcpu_id) -{ - return g_strdup_printf("/dev/hax_vm%02d/vcpu%02d", vm_id, vcpu_id); -} - -int hax_host_create_vm(struct hax_state *hax, int *vmid) -{ - int ret; - int vm_id = 0; - - if (hax_invalid_fd(hax->fd)) { - return -EINVAL; - } - - if (hax->vm) { - return 0; - } - - ret = ioctl(hax->fd, HAX_IOCTL_CREATE_VM, &vm_id); - *vmid = vm_id; - return ret; -} - -hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id) -{ - hax_fd fd; - char *vm_name = NULL; - - vm_name = hax_vm_devfs_string(vm_id); - if (!vm_name) { - return -1; - } - - fd = open(vm_name, O_RDWR); - g_free(vm_name); - - qemu_set_cloexec(fd); - - return fd; -} - -int hax_notify_qemu_version(hax_fd vm_fd, struct hax_qemu_version *qversion) -{ - int ret; - - if (hax_invalid_fd(vm_fd)) { - return -EINVAL; - } - - ret = ioctl(vm_fd, HAX_VM_IOCTL_NOTIFY_QEMU_VERSION, qversion); - - if (ret < 0) { - fprintf(stderr, "Failed to notify qemu API version\n"); - return ret; - } - return 0; -} - -/* Simply assume the size should be bigger than the hax_tunnel, - * since the hax_tunnel can be extended later with compatibility considered - */ -int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid) -{ - int ret; - - ret = ioctl(vm_fd, HAX_VM_IOCTL_VCPU_CREATE, &vcpuid); - if (ret < 0) { - fprintf(stderr, "Failed to create vcpu %x\n", vcpuid); - } - - return ret; -} - -hax_fd hax_host_open_vcpu(int vmid, int vcpuid) -{ - char *devfs_path = NULL; - hax_fd fd; - - devfs_path = hax_vcpu_devfs_string(vmid, vcpuid); - if (!devfs_path) { - fprintf(stderr, "Failed to get the devfs\n"); - return -EINVAL; - } - - fd = open(devfs_path, O_RDWR); - g_free(devfs_path); - if (fd < 0) { - fprintf(stderr, "Failed to open the vcpu devfs\n"); - } - qemu_set_cloexec(fd); - return fd; -} - -int hax_host_setup_vcpu_channel(AccelCPUState *vcpu) -{ - int ret; - struct hax_tunnel_info info; - - ret = ioctl(vcpu->fd, HAX_VCPU_IOCTL_SETUP_TUNNEL, &info); - if (ret) { - fprintf(stderr, "Failed to setup the hax tunnel\n"); - return ret; - } - - if (!valid_hax_tunnel_size(info.size)) { - fprintf(stderr, "Invalid hax tunnel size %x\n", info.size); - ret = -EINVAL; - return ret; - } - - vcpu->tunnel = (struct hax_tunnel *) (intptr_t) (info.va); - vcpu->iobuf = (unsigned char *) (intptr_t) (info.io_va); - return 0; -} - -int hax_vcpu_run(AccelCPUState *vcpu) -{ - return ioctl(vcpu->fd, HAX_VCPU_IOCTL_RUN, NULL); -} - -int hax_sync_fpu(CPUArchState *env, struct fx_layout *fl, int set) -{ - int ret, fd; - - fd = hax_vcpu_get_fd(env); - if (fd <= 0) { - return -1; - } - - if (set) { - ret = ioctl(fd, HAX_VCPU_IOCTL_SET_FPU, fl); - } else { - ret = ioctl(fd, HAX_VCPU_IOCTL_GET_FPU, fl); - } - return ret; -} - -int hax_sync_msr(CPUArchState *env, struct hax_msr_data *msrs, int set) -{ - int ret, fd; - - fd = hax_vcpu_get_fd(env); - if (fd <= 0) { - return -1; - } - if (set) { - ret = ioctl(fd, HAX_VCPU_IOCTL_SET_MSRS, msrs); - } else { - ret = ioctl(fd, HAX_VCPU_IOCTL_GET_MSRS, msrs); - } - return ret; -} - -int hax_sync_vcpu_state(CPUArchState *env, struct vcpu_state_t *state, int set) -{ - int ret, fd; - - fd = hax_vcpu_get_fd(env); - if (fd <= 0) { - return -1; - } - - if (set) { - ret = ioctl(fd, HAX_VCPU_SET_REGS, state); - } else { - ret = ioctl(fd, HAX_VCPU_GET_REGS, state); - } - return ret; -} - -int hax_inject_interrupt(CPUArchState *env, int vector) -{ - int fd; - - fd = hax_vcpu_get_fd(env); - if (fd <= 0) { - return -1; - } - - return ioctl(fd, HAX_VCPU_IOCTL_INTERRUPT, &vector); -} - -void hax_kick_vcpu_thread(CPUState *cpu) -{ - /* - * FIXME: race condition with the exit_request check in - * hax_vcpu_hax_exec - */ - cpu->exit_request = 1; - cpus_kick_thread(cpu); -} diff --git a/target/i386/hax/hax-posix.h b/target/i386/hax/hax-posix.h deleted file mode 100644 index fb7c64426d..0000000000 --- a/target/i386/hax/hax-posix.h +++ /dev/null @@ -1,61 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong<yunhong.jiang@intel.com> - * Xin Xiaohui<xiaohui.xin@intel.com> - * Zhang Xiantao<xiantao.zhang@intel.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -#ifndef TARGET_I386_HAX_POSIX_H -#define TARGET_I386_HAX_POSIX_H - -#include <sys/ioctl.h> - -#define HAX_INVALID_FD (-1) -static inline int hax_invalid_fd(hax_fd fd) -{ - return fd <= 0; -} - -static inline void hax_mod_close(struct hax_state *hax) -{ - close(hax->fd); -} - -static inline void hax_close_fd(hax_fd fd) -{ - close(fd); -} - -/* HAX model level ioctl */ -#define HAX_IOCTL_VERSION _IOWR(0, 0x20, struct hax_module_version) -#define HAX_IOCTL_CREATE_VM _IOWR(0, 0x21, uint32_t) -#define HAX_IOCTL_DESTROY_VM _IOW(0, 0x22, uint32_t) -#define HAX_IOCTL_CAPABILITY _IOR(0, 0x23, struct hax_capabilityinfo) - -#define HAX_VM_IOCTL_VCPU_CREATE _IOWR(0, 0x80, uint32_t) -#define HAX_VM_IOCTL_ALLOC_RAM _IOWR(0, 0x81, struct hax_alloc_ram_info) -#define HAX_VM_IOCTL_SET_RAM _IOWR(0, 0x82, struct hax_set_ram_info) -#define HAX_VM_IOCTL_VCPU_DESTROY _IOW(0, 0x83, uint32_t) -#define HAX_VM_IOCTL_NOTIFY_QEMU_VERSION _IOW(0, 0x84, struct hax_qemu_version) -#define HAX_VM_IOCTL_ADD_RAMBLOCK _IOW(0, 0x85, struct hax_ramblock_info) - -#define HAX_VCPU_IOCTL_RUN _IO(0, 0xc0) -#define HAX_VCPU_IOCTL_SET_MSRS _IOWR(0, 0xc1, struct hax_msr_data) -#define HAX_VCPU_IOCTL_GET_MSRS _IOWR(0, 0xc2, struct hax_msr_data) - -#define HAX_VCPU_IOCTL_SET_FPU _IOW(0, 0xc3, struct fx_layout) -#define HAX_VCPU_IOCTL_GET_FPU _IOR(0, 0xc4, struct fx_layout) - -#define HAX_VCPU_IOCTL_SETUP_TUNNEL _IOWR(0, 0xc5, struct hax_tunnel_info) -#define HAX_VCPU_IOCTL_INTERRUPT _IOWR(0, 0xc6, uint32_t) -#define HAX_VCPU_SET_REGS _IOWR(0, 0xc7, struct vcpu_state_t) -#define HAX_VCPU_GET_REGS _IOWR(0, 0xc8, struct vcpu_state_t) - -#endif /* TARGET_I386_HAX_POSIX_H */ diff --git a/target/i386/hax/hax-windows.c b/target/i386/hax/hax-windows.c deleted file mode 100644 index 4bf6cc08d2..0000000000 --- a/target/i386/hax/hax-windows.c +++ /dev/null @@ -1,485 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong<yunhong.jiang@intel.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "hax-accel-ops.h" - -/* - * return 0 when success, -1 when driver not loaded, - * other negative value for other failure - */ -static int hax_open_device(hax_fd *fd) -{ - uint32_t errNum = 0; - HANDLE hDevice; - - if (!fd) { - return -2; - } - - hDevice = CreateFile("\\\\.\\HAX", - GENERIC_READ | GENERIC_WRITE, - 0, NULL, CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, NULL); - - if (hDevice == INVALID_HANDLE_VALUE) { - fprintf(stderr, "Failed to open the HAX device!\n"); - errNum = GetLastError(); - if (errNum == ERROR_FILE_NOT_FOUND) { - return -1; - } - return -2; - } - *fd = hDevice; - return 0; -} - -/* hax_fd hax_mod_open */ - hax_fd hax_mod_open(void) -{ - int ret; - hax_fd fd = NULL; - - ret = hax_open_device(&fd); - if (ret != 0) { - fprintf(stderr, "Open HAX device failed\n"); - } - - return fd; -} - -int hax_populate_ram(uint64_t va, uint64_t size) -{ - int ret; - HANDLE hDeviceVM; - DWORD dSize = 0; - - if (!hax_global.vm || !hax_global.vm->fd) { - fprintf(stderr, "Allocate memory before vm create?\n"); - return -EINVAL; - } - - hDeviceVM = hax_global.vm->fd; - if (hax_global.supports_64bit_ramblock) { - struct hax_ramblock_info ramblock = { - .start_va = va, - .size = size, - .reserved = 0 - }; - - ret = DeviceIoControl(hDeviceVM, - HAX_VM_IOCTL_ADD_RAMBLOCK, - &ramblock, sizeof(ramblock), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - } else { - struct hax_alloc_ram_info info = { - .size = (uint32_t) size, - .pad = 0, - .va = va - }; - - ret = DeviceIoControl(hDeviceVM, - HAX_VM_IOCTL_ALLOC_RAM, - &info, sizeof(info), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - } - - if (!ret) { - fprintf(stderr, "Failed to register RAM block: va=0x%" PRIx64 - ", size=0x%" PRIx64 ", method=%s\n", va, size, - hax_global.supports_64bit_ramblock ? "new" : "legacy"); - return ret; - } - - return 0; -} - -int hax_set_ram(uint64_t start_pa, uint32_t size, uint64_t host_va, int flags) -{ - struct hax_set_ram_info info; - HANDLE hDeviceVM = hax_global.vm->fd; - DWORD dSize = 0; - int ret; - - info.pa_start = start_pa; - info.size = size; - info.va = host_va; - info.flags = (uint8_t) flags; - - ret = DeviceIoControl(hDeviceVM, HAX_VM_IOCTL_SET_RAM, - &info, sizeof(info), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_capability(struct hax_state *hax, struct hax_capabilityinfo *cap) -{ - int ret; - HANDLE hDevice = hax->fd; /* handle to hax module */ - DWORD dSize = 0; - DWORD err = 0; - - if (hax_invalid_fd(hDevice)) { - fprintf(stderr, "Invalid fd for hax device!\n"); - return -ENODEV; - } - - ret = DeviceIoControl(hDevice, HAX_IOCTL_CAPABILITY, NULL, 0, cap, - sizeof(*cap), &dSize, (LPOVERLAPPED) NULL); - - if (!ret) { - err = GetLastError(); - if (err == ERROR_INSUFFICIENT_BUFFER || err == ERROR_MORE_DATA) { - fprintf(stderr, "hax capability is too long to hold.\n"); - } - fprintf(stderr, "Failed to get Hax capability:%luu\n", err); - return -EFAULT; - } else { - return 0; - } -} - -int hax_mod_version(struct hax_state *hax, struct hax_module_version *version) -{ - int ret; - HANDLE hDevice = hax->fd; /* handle to hax module */ - DWORD dSize = 0; - DWORD err = 0; - - if (hax_invalid_fd(hDevice)) { - fprintf(stderr, "Invalid fd for hax device!\n"); - return -ENODEV; - } - - ret = DeviceIoControl(hDevice, - HAX_IOCTL_VERSION, - NULL, 0, - version, sizeof(*version), &dSize, - (LPOVERLAPPED) NULL); - - if (!ret) { - err = GetLastError(); - if (err == ERROR_INSUFFICIENT_BUFFER || err == ERROR_MORE_DATA) { - fprintf(stderr, "hax module verion is too long to hold.\n"); - } - fprintf(stderr, "Failed to get Hax module version:%lu\n", err); - return -EFAULT; - } else { - return 0; - } -} - -static char *hax_vm_devfs_string(int vm_id) -{ - return g_strdup_printf("\\\\.\\hax_vm%02d", vm_id); -} - -static char *hax_vcpu_devfs_string(int vm_id, int vcpu_id) -{ - return g_strdup_printf("\\\\.\\hax_vm%02d_vcpu%02d", vm_id, vcpu_id); -} - -int hax_host_create_vm(struct hax_state *hax, int *vmid) -{ - int ret; - int vm_id = 0; - DWORD dSize = 0; - - if (hax_invalid_fd(hax->fd)) { - return -EINVAL; - } - - if (hax->vm) { - return 0; - } - - ret = DeviceIoControl(hax->fd, - HAX_IOCTL_CREATE_VM, - NULL, 0, &vm_id, sizeof(vm_id), &dSize, - (LPOVERLAPPED) NULL); - if (!ret) { - fprintf(stderr, "Failed to create VM. Error code: %lu\n", - GetLastError()); - return -1; - } - *vmid = vm_id; - return 0; -} - -hax_fd hax_host_open_vm(struct hax_state *hax, int vm_id) -{ - char *vm_name = NULL; - hax_fd hDeviceVM; - - vm_name = hax_vm_devfs_string(vm_id); - if (!vm_name) { - fprintf(stderr, "Failed to open VM. VM name is null\n"); - return INVALID_HANDLE_VALUE; - } - - hDeviceVM = CreateFile(vm_name, - GENERIC_READ | GENERIC_WRITE, - 0, NULL, CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, NULL); - if (hDeviceVM == INVALID_HANDLE_VALUE) { - fprintf(stderr, "Open the vm device error:%s, ec:%lu\n", - vm_name, GetLastError()); - } - - g_free(vm_name); - return hDeviceVM; -} - -int hax_notify_qemu_version(hax_fd vm_fd, struct hax_qemu_version *qversion) -{ - int ret; - DWORD dSize = 0; - if (hax_invalid_fd(vm_fd)) { - return -EINVAL; - } - ret = DeviceIoControl(vm_fd, - HAX_VM_IOCTL_NOTIFY_QEMU_VERSION, - qversion, sizeof(struct hax_qemu_version), - NULL, 0, &dSize, (LPOVERLAPPED) NULL); - if (!ret) { - fprintf(stderr, "Failed to notify qemu API version\n"); - return -1; - } - return 0; -} - -int hax_host_create_vcpu(hax_fd vm_fd, int vcpuid) -{ - int ret; - DWORD dSize = 0; - - ret = DeviceIoControl(vm_fd, - HAX_VM_IOCTL_VCPU_CREATE, - &vcpuid, sizeof(vcpuid), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - if (!ret) { - fprintf(stderr, "Failed to create vcpu %x\n", vcpuid); - return -1; - } - - return 0; -} - -hax_fd hax_host_open_vcpu(int vmid, int vcpuid) -{ - char *devfs_path = NULL; - hax_fd hDeviceVCPU; - - devfs_path = hax_vcpu_devfs_string(vmid, vcpuid); - if (!devfs_path) { - fprintf(stderr, "Failed to get the devfs\n"); - return INVALID_HANDLE_VALUE; - } - - hDeviceVCPU = CreateFile(devfs_path, - GENERIC_READ | GENERIC_WRITE, - 0, NULL, CREATE_ALWAYS, FILE_ATTRIBUTE_NORMAL, - NULL); - - if (hDeviceVCPU == INVALID_HANDLE_VALUE) { - fprintf(stderr, "Failed to open the vcpu devfs\n"); - } - g_free(devfs_path); - return hDeviceVCPU; -} - -int hax_host_setup_vcpu_channel(AccelCPUState *vcpu) -{ - hax_fd hDeviceVCPU = vcpu->fd; - int ret; - struct hax_tunnel_info info; - DWORD dSize = 0; - - ret = DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_SETUP_TUNNEL, - NULL, 0, &info, sizeof(info), &dSize, - (LPOVERLAPPED) NULL); - if (!ret) { - fprintf(stderr, "Failed to setup the hax tunnel\n"); - return -1; - } - - if (!valid_hax_tunnel_size(info.size)) { - fprintf(stderr, "Invalid hax tunnel size %x\n", info.size); - ret = -EINVAL; - return ret; - } - vcpu->tunnel = (struct hax_tunnel *) (intptr_t) (info.va); - vcpu->iobuf = (unsigned char *) (intptr_t) (info.io_va); - return 0; -} - -int hax_vcpu_run(AccelCPUState *vcpu) -{ - int ret; - HANDLE hDeviceVCPU = vcpu->fd; - DWORD dSize = 0; - - ret = DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_RUN, - NULL, 0, NULL, 0, &dSize, (LPOVERLAPPED) NULL); - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_sync_fpu(CPUArchState *env, struct fx_layout *fl, int set) -{ - int ret; - hax_fd fd; - HANDLE hDeviceVCPU; - DWORD dSize = 0; - - fd = hax_vcpu_get_fd(env); - if (hax_invalid_fd(fd)) { - return -1; - } - - hDeviceVCPU = fd; - - if (set) { - ret = DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_SET_FPU, - fl, sizeof(*fl), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - } else { - ret = DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_GET_FPU, - NULL, 0, fl, sizeof(*fl), &dSize, - (LPOVERLAPPED) NULL); - } - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_sync_msr(CPUArchState *env, struct hax_msr_data *msrs, int set) -{ - int ret; - hax_fd fd; - HANDLE hDeviceVCPU; - DWORD dSize = 0; - - fd = hax_vcpu_get_fd(env); - if (hax_invalid_fd(fd)) { - return -1; - } - hDeviceVCPU = fd; - - if (set) { - ret = DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_SET_MSRS, - msrs, sizeof(*msrs), - msrs, sizeof(*msrs), &dSize, (LPOVERLAPPED) NULL); - } else { - ret = DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_GET_MSRS, - msrs, sizeof(*msrs), - msrs, sizeof(*msrs), &dSize, (LPOVERLAPPED) NULL); - } - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_sync_vcpu_state(CPUArchState *env, struct vcpu_state_t *state, int set) -{ - int ret; - hax_fd fd; - HANDLE hDeviceVCPU; - DWORD dSize; - - fd = hax_vcpu_get_fd(env); - if (hax_invalid_fd(fd)) { - return -1; - } - - hDeviceVCPU = fd; - - if (set) { - ret = DeviceIoControl(hDeviceVCPU, - HAX_VCPU_SET_REGS, - state, sizeof(*state), - NULL, 0, &dSize, (LPOVERLAPPED) NULL); - } else { - ret = DeviceIoControl(hDeviceVCPU, - HAX_VCPU_GET_REGS, - NULL, 0, - state, sizeof(*state), &dSize, - (LPOVERLAPPED) NULL); - } - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -int hax_inject_interrupt(CPUArchState *env, int vector) -{ - int ret; - hax_fd fd; - HANDLE hDeviceVCPU; - DWORD dSize; - - fd = hax_vcpu_get_fd(env); - if (hax_invalid_fd(fd)) { - return -1; - } - - hDeviceVCPU = fd; - - ret = DeviceIoControl(hDeviceVCPU, - HAX_VCPU_IOCTL_INTERRUPT, - &vector, sizeof(vector), NULL, 0, &dSize, - (LPOVERLAPPED) NULL); - if (!ret) { - return -EFAULT; - } else { - return 0; - } -} - -static void CALLBACK dummy_apc_func(ULONG_PTR unused) -{ -} - -void hax_kick_vcpu_thread(CPUState *cpu) -{ - /* - * FIXME: race condition with the exit_request check in - * hax_vcpu_hax_exec - */ - cpu->exit_request = 1; - if (!qemu_cpu_is_self(cpu)) { - if (!QueueUserAPC(dummy_apc_func, cpu->accel->hThread, 0)) { - fprintf(stderr, "%s: QueueUserAPC failed with error %lu\n", - __func__, GetLastError()); - exit(1); - } - } -} diff --git a/target/i386/hax/hax-windows.h b/target/i386/hax/hax-windows.h deleted file mode 100644 index b1f5d4f32f..0000000000 --- a/target/i386/hax/hax-windows.h +++ /dev/null @@ -1,88 +0,0 @@ -/* - * QEMU HAXM support - * - * Copyright IBM, Corp. 2008 - * - * Authors: - * Anthony Liguori <aliguori@us.ibm.com> - * - * Copyright (c) 2011 Intel Corporation - * Written by: - * Jiang Yunhong<yunhong.jiang@intel.com> - * Xin Xiaohui<xiaohui.xin@intel.com> - * Zhang Xiantao<xiantao.zhang@intel.com> - * - * This work is licensed under the terms of the GNU GPL, version 2 or later. - * See the COPYING file in the top-level directory. - * - */ - -#ifndef TARGET_I386_HAX_WINDOWS_H -#define TARGET_I386_HAX_WINDOWS_H - -#include <winioctl.h> -#include <windef.h> - -#include "hax-accel-ops.h" - -#define HAX_INVALID_FD INVALID_HANDLE_VALUE - -static inline void hax_mod_close(struct hax_state *hax) -{ - CloseHandle(hax->fd); -} - -static inline void hax_close_fd(hax_fd fd) -{ - CloseHandle(fd); -} - -static inline int hax_invalid_fd(hax_fd fd) -{ - return (fd == INVALID_HANDLE_VALUE); -} - -#define HAX_DEVICE_TYPE 0x4000 - -#define HAX_IOCTL_VERSION CTL_CODE(HAX_DEVICE_TYPE, 0x900, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_IOCTL_CREATE_VM CTL_CODE(HAX_DEVICE_TYPE, 0x901, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_IOCTL_CAPABILITY CTL_CODE(HAX_DEVICE_TYPE, 0x910, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) - -#define HAX_VM_IOCTL_VCPU_CREATE CTL_CODE(HAX_DEVICE_TYPE, 0x902, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VM_IOCTL_ALLOC_RAM CTL_CODE(HAX_DEVICE_TYPE, 0x903, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VM_IOCTL_SET_RAM CTL_CODE(HAX_DEVICE_TYPE, 0x904, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VM_IOCTL_VCPU_DESTROY CTL_CODE(HAX_DEVICE_TYPE, 0x905, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VM_IOCTL_ADD_RAMBLOCK CTL_CODE(HAX_DEVICE_TYPE, 0x913, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) - -#define HAX_VCPU_IOCTL_RUN CTL_CODE(HAX_DEVICE_TYPE, 0x906, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_IOCTL_SET_MSRS CTL_CODE(HAX_DEVICE_TYPE, 0x907, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_IOCTL_GET_MSRS CTL_CODE(HAX_DEVICE_TYPE, 0x908, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_IOCTL_SET_FPU CTL_CODE(HAX_DEVICE_TYPE, 0x909, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_IOCTL_GET_FPU CTL_CODE(HAX_DEVICE_TYPE, 0x90a, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) - -#define HAX_VCPU_IOCTL_SETUP_TUNNEL CTL_CODE(HAX_DEVICE_TYPE, 0x90b, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_IOCTL_INTERRUPT CTL_CODE(HAX_DEVICE_TYPE, 0x90c, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_SET_REGS CTL_CODE(HAX_DEVICE_TYPE, 0x90d, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) -#define HAX_VCPU_GET_REGS CTL_CODE(HAX_DEVICE_TYPE, 0x90e, \ - METHOD_BUFFERED, FILE_ANY_ACCESS) - -#define HAX_VM_IOCTL_NOTIFY_QEMU_VERSION CTL_CODE(HAX_DEVICE_TYPE, 0x910, \ - METHOD_BUFFERED, \ - FILE_ANY_ACCESS) -#endif /* TARGET_I386_HAX_WINDOWS_H */ diff --git a/target/i386/hax/meson.build b/target/i386/hax/meson.build deleted file mode 100644 index 6ac314aa35..0000000000 --- a/target/i386/hax/meson.build +++ /dev/null @@ -1,7 +0,0 @@ -i386_system_ss.add(when: 'CONFIG_HAX', if_true: files( - 'hax-all.c', - 'hax-mem.c', - 'hax-accel-ops.c', -)) -i386_system_ss.add(when: ['CONFIG_HAX', 'CONFIG_POSIX'], if_true: files('hax-posix.c')) -i386_system_ss.add(when: ['CONFIG_HAX', 'CONFIG_WIN32'], if_true: files('hax-windows.c')) diff --git a/target/i386/meson.build b/target/i386/meson.build index 1effe1ed9a..6f1036d469 100644 --- a/target/i386/meson.build +++ b/target/i386/meson.build @@ -25,7 +25,6 @@ i386_system_ss.add(when: 'CONFIG_SEV', if_true: files('sev.c'), if_false: files( i386_user_ss = ss.source_set() subdir('kvm') -subdir('hax') subdir('whpx') subdir('nvmm') subdir('hvf') diff --git a/target/i386/sev.h b/target/i386/sev.h index 7b1528248a..e7499c95b1 100644 --- a/target/i386/sev.h +++ b/target/i386/sev.h @@ -46,9 +46,9 @@ bool sev_es_enabled(void); #define sev_es_enabled() 0 #endif -extern uint32_t sev_get_cbit_position(void); -extern uint32_t sev_get_reduced_phys_bits(void); -extern bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **errp); +uint32_t sev_get_cbit_position(void); +uint32_t sev_get_reduced_phys_bits(void); +bool sev_add_kernel_loader_hashes(SevKernelLoaderContext *ctx, Error **errp); int sev_encrypt_flash(uint8_t *ptr, uint64_t len, Error **errp); int sev_inject_launch_secret(const char *hdr, const char *secret, diff --git a/target/i386/tcg/fpu_helper.c b/target/i386/tcg/fpu_helper.c index 6f3741b635..4430d3d380 100644 --- a/target/i386/tcg/fpu_helper.c +++ b/target/i386/tcg/fpu_helper.c @@ -21,6 +21,7 @@ #include <math.h> #include "cpu.h" #include "tcg-cpu.h" +#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "fpu/softfloat-macros.h" diff --git a/target/i386/tcg/sysemu/excp_helper.c b/target/i386/tcg/sysemu/excp_helper.c index b5f0abffa3..226689a4f2 100644 --- a/target/i386/tcg/sysemu/excp_helper.c +++ b/target/i386/tcg/sysemu/excp_helper.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "cpu.h" +#include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "tcg/helper-tcg.h" diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c index 27fc6e1f33..65f9320e34 100644 --- a/target/loongarch/cpu.c +++ b/target/loongarch/cpu.c @@ -11,6 +11,7 @@ #include "qapi/error.h" #include "qemu/module.h" #include "sysemu/qtest.h" +#include "exec/cpu_ldst.h" #include "exec/exec-all.h" #include "cpu.h" #include "internals.h" diff --git a/target/loongarch/iocsr_helper.c b/target/loongarch/iocsr_helper.c index dda9845d6c..6cd01d5f09 100644 --- a/target/loongarch/iocsr_helper.c +++ b/target/loongarch/iocsr_helper.c @@ -6,7 +6,6 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" diff --git a/target/loongarch/op_helper.c b/target/loongarch/op_helper.c index cf84f20aba..fe79c62fa4 100644 --- a/target/loongarch/op_helper.c +++ b/target/loongarch/op_helper.c @@ -7,7 +7,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "qemu/host-utils.h" #include "exec/helper-proto.h" diff --git a/target/m68k/translate.c b/target/m68k/translate.c index 15b3701b8f..9e224fe796 100644 --- a/target/m68k/translate.c +++ b/target/m68k/translate.c @@ -25,7 +25,6 @@ #include "tcg/tcg-op.h" #include "qemu/log.h" #include "qemu/qemu-print.h" -#include "exec/cpu_ldst.h" #include "exec/translator.h" #include "exec/helper-proto.h" diff --git a/target/microblaze/translate.c b/target/microblaze/translate.c index 7e7f837c63..d02c16296a 100644 --- a/target/microblaze/translate.c +++ b/target/microblaze/translate.c @@ -24,7 +24,6 @@ #include "exec/exec-all.h" #include "tcg/tcg-op.h" #include "exec/helper-proto.h" -#include "exec/cpu_ldst.h" #include "exec/helper-gen.h" #include "exec/translator.h" #include "qemu/qemu-print.h" diff --git a/target/mips/cpu-defs.c.inc b/target/mips/cpu-defs.c.inc index 03185d9aa0..c0c389c59a 100644 --- a/target/mips/cpu-defs.c.inc +++ b/target/mips/cpu-defs.c.inc @@ -1045,7 +1045,7 @@ static void mvp_init(CPUMIPSState *env) return; } - /* MVPConf1 implemented, TLB sharable, no gating storage support, + /* MVPConf1 implemented, TLB shareable, no gating storage support, programmable cache partitioning implemented, number of allocatable and shareable TLB entries, MVP has allocatable TCs, 2 VPEs implemented, 5 TCs implemented. */ diff --git a/target/mips/cpu.h b/target/mips/cpu.h index f81bd06f5e..6d6af1f2a8 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -1224,8 +1224,8 @@ void mips_cpu_list(void); #define cpu_list mips_cpu_list -extern void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); -extern uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); +void cpu_wrdsp(uint32_t rs, uint32_t mask_num, CPUMIPSState *env); +uint32_t cpu_rddsp(uint32_t mask_num, CPUMIPSState *env); /* * MMU modes definitions. We carefully match the indices with our diff --git a/target/mips/tcg/fpu_helper.c b/target/mips/tcg/fpu_helper.c index 8ce56ed7c8..45d593de48 100644 --- a/target/mips/tcg/fpu_helper.c +++ b/target/mips/tcg/fpu_helper.c @@ -25,7 +25,6 @@ #include "internal.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "fpu/softfloat.h" #include "fpu_helper.h" diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c index c1a8380e34..97056d00a2 100644 --- a/target/mips/tcg/ldst_helper.c +++ b/target/mips/tcg/ldst_helper.c @@ -24,6 +24,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/memop.h" #include "internal.h" diff --git a/target/mips/tcg/msa_helper.c b/target/mips/tcg/msa_helper.c index 29b31d70fe..c314a74397 100644 --- a/target/mips/tcg/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -22,6 +22,7 @@ #include "internal.h" #include "tcg/tcg.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/memop.h" #include "fpu/softfloat.h" @@ -802,9 +803,9 @@ void helper_msa_bset_d(CPUMIPSState *env, uint32_t wd, uint32_t ws, uint32_t wt) * | HADD_S.H | Vector Signed Horizontal Add (halfword) | * | HADD_S.W | Vector Signed Horizontal Add (word) | * | HADD_S.D | Vector Signed Horizontal Add (doubleword) | - * | HADD_U.H | Vector Unigned Horizontal Add (halfword) | - * | HADD_U.W | Vector Unigned Horizontal Add (word) | - * | HADD_U.D | Vector Unigned Horizontal Add (doubleword) | + * | HADD_U.H | Vector Unsigned Horizontal Add (halfword) | + * | HADD_U.W | Vector Unsigned Horizontal Add (word) | + * | HADD_U.D | Vector Unsigned Horizontal Add (doubleword) | * +---------------+----------------------------------------------------------+ */ @@ -3451,9 +3452,9 @@ void helper_msa_mulv_d(CPUMIPSState *env, * | HSUB_S.H | Vector Signed Horizontal Subtract (halfword) | * | HSUB_S.W | Vector Signed Horizontal Subtract (word) | * | HSUB_S.D | Vector Signed Horizontal Subtract (doubleword) | - * | HSUB_U.H | Vector Unigned Horizontal Subtract (halfword) | - * | HSUB_U.W | Vector Unigned Horizontal Subtract (word) | - * | HSUB_U.D | Vector Unigned Horizontal Subtract (doubleword) | + * | HSUB_U.H | Vector Unsigned Horizontal Subtract (halfword) | + * | HSUB_U.W | Vector Unsigned Horizontal Subtract (word) | + * | HSUB_U.D | Vector Unsigned Horizontal Subtract (doubleword) | * | SUBS_S.B | Vector Signed Saturated Subtract (of Signed) (byte) | * | SUBS_S.H | Vector Signed Saturated Subtract (of Signed) (halfword) | * | SUBS_S.W | Vector Signed Saturated Subtract (of Signed) (word) | diff --git a/target/mips/tcg/mxu_translate.c b/target/mips/tcg/mxu_translate.c index e662acd5df..cfcd8ac9bc 100644 --- a/target/mips/tcg/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c @@ -2977,14 +2977,14 @@ static void gen_mxu_Q8ADD(DisasContext *ctx) * to another one in XRc, with zero extending * to 16-bit and put results as packed 16-bit data * into XRa and XRd. - * aptn2 manages action add or subract of pairs of data. + * aptn2 manages action add or subtract of pairs of data. * * Q8ACCE XRa, XRb, XRc, XRd, aptn2 * Add/subtract quadruple of 8-bit packed in XRb * to another one in XRc, with zero extending * to 16-bit and accumulate results as packed 16-bit data * into XRa and XRd. - * aptn2 manages action add or subract of pairs of data. + * aptn2 manages action add or subtract of pairs of data. */ static void gen_mxu_q8adde(DisasContext *ctx, bool accumulate) { @@ -4056,7 +4056,7 @@ static void gen_mxu_s32sfl(DisasContext *ctx) /* * Q8SAD XRa, XRd, XRb, XRc - * Typical SAD opration for motion estimation. + * Typical SAD operation for motion estimation. */ static void gen_mxu_q8sad(DisasContext *ctx) { diff --git a/target/mips/tcg/sysemu/lcsr_helper.c b/target/mips/tcg/sysemu/lcsr_helper.c index 942143d209..25e03572fe 100644 --- a/target/mips/tcg/sysemu/lcsr_helper.c +++ b/target/mips/tcg/sysemu/lcsr_helper.c @@ -7,13 +7,8 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" -#include "internal.h" -#include "qemu/host-utils.h" #include "exec/helper-proto.h" -#include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #define GET_MEMTXATTRS(cas) \ ((MemTxAttrs){.requester_id = env_cpu(cas)->cpu_index}) diff --git a/target/nios2/op_helper.c b/target/nios2/op_helper.c index 0aaf33ffc2..5017457c5e 100644 --- a/target/nios2/op_helper.c +++ b/target/nios2/op_helper.c @@ -22,7 +22,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "qemu/main-loop.h" void helper_raise_exception(CPUNios2State *env, uint32_t index) { diff --git a/target/nios2/translate.c b/target/nios2/translate.c index 4264c7ec6b..dfc546d3bb 100644 --- a/target/nios2/translate.c +++ b/target/nios2/translate.c @@ -29,7 +29,6 @@ #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/log.h" -#include "exec/cpu_ldst.h" #include "exec/translator.h" #include "qemu/qemu-print.h" #include "semihosting/semihost.h" diff --git a/target/openrisc/translate.c b/target/openrisc/translate.c index 7c6f80daf1..d65758449f 100644 --- a/target/openrisc/translate.c +++ b/target/openrisc/translate.c @@ -26,7 +26,6 @@ #include "qemu/log.h" #include "qemu/bitops.h" #include "qemu/qemu-print.h" -#include "exec/cpu_ldst.h" #include "exec/translator.h" #include "exec/helper-proto.h" diff --git a/target/ppc/compat.c b/target/ppc/compat.c index 7949a24f5a..ebef2cccec 100644 --- a/target/ppc/compat.c +++ b/target/ppc/compat.c @@ -229,6 +229,25 @@ int ppc_set_compat_all(uint32_t compat_pvr, Error **errp) return 0; } +/* To be used when the machine is not running */ +int ppc_init_compat_all(uint32_t compat_pvr, Error **errp) +{ + CPUState *cs; + + CPU_FOREACH(cs) { + PowerPCCPU *cpu = POWERPC_CPU(cs); + int ret; + + ret = ppc_set_compat(cpu, compat_pvr, errp); + + if (ret < 0) { + return ret; + } + } + + return 0; +} + int ppc_compat_max_vthreads(PowerPCCPU *cpu) { const CompatInfo *compat = compat_by_pvr(cpu->compat_pvr); diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c index 424f2e1741..e3ad8e0c27 100644 --- a/target/ppc/cpu.c +++ b/target/ppc/cpu.c @@ -59,6 +59,7 @@ void ppc_store_vscr(CPUPPCState *env, uint32_t vscr) env->vscr_sat.u64[0] = vscr & (1u << VSCR_SAT); env->vscr_sat.u64[1] = 0; set_flush_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); + set_flush_inputs_to_zero((vscr >> VSCR_NJ) & 1, &env->vec_status); } uint32_t ppc_get_vscr(CPUPPCState *env) @@ -102,6 +103,92 @@ void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val) ppc_maybe_interrupt(env); } + +#if defined(TARGET_PPC64) +void ppc_update_ciabr(CPUPPCState *env) +{ + CPUState *cs = env_cpu(env); + target_ulong ciabr = env->spr[SPR_CIABR]; + target_ulong ciea, priv; + + ciea = ciabr & PPC_BITMASK(0, 61); + priv = ciabr & PPC_BITMASK(62, 63); + + if (env->ciabr_breakpoint) { + cpu_breakpoint_remove_by_ref(cs, env->ciabr_breakpoint); + env->ciabr_breakpoint = NULL; + } + + if (priv) { + cpu_breakpoint_insert(cs, ciea, BP_CPU, &env->ciabr_breakpoint); + } +} + +void ppc_store_ciabr(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_CIABR] = val; + ppc_update_ciabr(env); +} + +void ppc_update_daw0(CPUPPCState *env) +{ + CPUState *cs = env_cpu(env); + target_ulong deaw = env->spr[SPR_DAWR0] & PPC_BITMASK(0, 60); + uint32_t dawrx = env->spr[SPR_DAWRX0]; + int mrd = extract32(dawrx, PPC_BIT_NR(48), 54 - 48); + bool dw = extract32(dawrx, PPC_BIT_NR(57), 1); + bool dr = extract32(dawrx, PPC_BIT_NR(58), 1); + bool hv = extract32(dawrx, PPC_BIT_NR(61), 1); + bool sv = extract32(dawrx, PPC_BIT_NR(62), 1); + bool pr = extract32(dawrx, PPC_BIT_NR(62), 1); + vaddr len; + int flags; + + if (env->dawr0_watchpoint) { + cpu_watchpoint_remove_by_ref(cs, env->dawr0_watchpoint); + env->dawr0_watchpoint = NULL; + } + + if (!dr && !dw) { + return; + } + + if (!hv && !sv && !pr) { + return; + } + + len = (mrd + 1) * 8; + flags = BP_CPU | BP_STOP_BEFORE_ACCESS; + if (dr) { + flags |= BP_MEM_READ; + } + if (dw) { + flags |= BP_MEM_WRITE; + } + + cpu_watchpoint_insert(cs, deaw, len, flags, &env->dawr0_watchpoint); +} + +void ppc_store_dawr0(CPUPPCState *env, target_ulong val) +{ + env->spr[SPR_DAWR0] = val; + ppc_update_daw0(env); +} + +void ppc_store_dawrx0(CPUPPCState *env, uint32_t val) +{ + int hrammc = extract32(val, PPC_BIT_NR(56), 1); + + if (hrammc) { + /* This might be done with a second watchpoint at the xor of DEAW[0] */ + qemu_log_mask(LOG_UNIMP, "%s: DAWRX0[HRAMMC] is unimplemented\n", + __func__); + } + + env->spr[SPR_DAWRX0] = val; + ppc_update_daw0(env); +} +#endif #endif static inline void fpscr_set_rounding_mode(CPUPPCState *env) diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index 25fac9577a..173e4c351a 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -1121,7 +1121,9 @@ struct CPUArchState { target_ulong reserve_addr; /* Reservation address */ target_ulong reserve_length; /* Reservation larx op size (bytes) */ target_ulong reserve_val; /* Reservation value */ +#if defined(TARGET_PPC64) target_ulong reserve_val2; +#endif /* These are used in supervisor mode only */ target_ulong msr; /* machine state register */ @@ -1137,6 +1139,8 @@ struct CPUArchState { /* MMU context, only relevant for full system emulation */ #if defined(TARGET_PPC64) ppc_slb_t slb[MAX_SLB_ENTRIES]; /* PowerPC 64 SLB area */ + struct CPUBreakpoint *ciabr_breakpoint; + struct CPUWatchpoint *dawr0_watchpoint; #endif target_ulong sr[32]; /* segment registers */ uint32_t nb_BATs; /* number of BATs */ @@ -1403,6 +1407,11 @@ void ppc_translate_init(void); #if !defined(CONFIG_USER_ONLY) void ppc_store_sdr1(CPUPPCState *env, target_ulong value); void ppc_store_lpcr(PowerPCCPU *cpu, target_ulong val); +void ppc_update_ciabr(CPUPPCState *env); +void ppc_store_ciabr(CPUPPCState *env, target_ulong value); +void ppc_update_daw0(CPUPPCState *env); +void ppc_store_dawr0(CPUPPCState *env, target_ulong value); +void ppc_store_dawrx0(CPUPPCState *env, uint32_t value); #endif /* !defined(CONFIG_USER_ONLY) */ void ppc_store_msr(CPUPPCState *env, target_ulong value); @@ -1495,6 +1504,7 @@ int ppc_set_compat(PowerPCCPU *cpu, uint32_t compat_pvr, Error **errp); #if !defined(CONFIG_USER_ONLY) int ppc_set_compat_all(uint32_t compat_pvr, Error **errp); +int ppc_init_compat_all(uint32_t compat_pvr, Error **errp); #endif int ppc_compat_max_vthreads(PowerPCCPU *cpu); void ppc_compat_add_property(Object *obj, const char *name, @@ -1897,7 +1907,9 @@ void ppc_compat_add_property(Object *obj, const char *name, #define SPR_PSSCR (0x357) #define SPR_440_INV0 (0x370) #define SPR_440_INV1 (0x371) +#define SPR_TRIG1 (0x371) #define SPR_440_INV2 (0x372) +#define SPR_TRIG2 (0x372) #define SPR_440_INV3 (0x373) #define SPR_440_ITV0 (0x374) #define SPR_440_ITV1 (0x375) diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index 02b7aad9b0..7ab5ee92d9 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -5117,17 +5117,17 @@ static void register_book3s_207_dbg_sprs(CPUPPCState *env) spr_register_kvm_hv(env, SPR_DAWR0, "DAWR0", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_dawr0, KVM_REG_PPC_DAWR, 0x00000000); spr_register_kvm_hv(env, SPR_DAWRX0, "DAWRX0", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic32, + &spr_read_generic, &spr_write_dawrx0, KVM_REG_PPC_DAWRX, 0x00000000); spr_register_kvm_hv(env, SPR_CIABR, "CIABR", SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, SPR_NOACCESS, - &spr_read_generic, &spr_write_generic, + &spr_read_generic, &spr_write_ciabr, KVM_REG_PPC_CIABR, 0x00000000); } @@ -5660,6 +5660,16 @@ static void register_power_common_book4_sprs(CPUPPCState *env) SPR_NOACCESS, SPR_NOACCESS, &spr_read_tfmr, &spr_write_tfmr, 0x00000000); + spr_register_hv(env, SPR_TRIG1, "TRIG1", + SPR_NOACCESS, SPR_NOACCESS, + &spr_access_nop, &spr_write_generic, + &spr_access_nop, &spr_write_generic, + 0x00000000); + spr_register_hv(env, SPR_TRIG2, "TRIG2", + SPR_NOACCESS, SPR_NOACCESS, + &spr_access_nop, &spr_write_generic, + &spr_access_nop, &spr_write_generic, + 0x00000000); #endif } @@ -7149,6 +7159,8 @@ static void ppc_cpu_reset_hold(Object *obj) env->nip = env->hreset_vector | env->excp_prefix; if (tcg_enabled()) { + cpu_breakpoint_remove_all(s, BP_CPU); + cpu_watchpoint_remove_all(s, BP_CPU); if (env->mmu_model != POWERPC_MMU_REAL) { ppc_tlb_invalidate_all(env); } @@ -7336,6 +7348,9 @@ static const struct TCGCPUOps ppc_tcg_ops = { .cpu_exec_exit = ppc_cpu_exec_exit, .do_unaligned_access = ppc_cpu_do_unaligned_access, .do_transaction_failed = ppc_cpu_do_transaction_failed, + .debug_excp_handler = ppc_cpu_debug_excp_handler, + .debug_check_breakpoint = ppc_cpu_debug_check_breakpoint, + .debug_check_watchpoint = ppc_cpu_debug_check_watchpoint, #endif /* !CONFIG_USER_ONLY */ }; #endif /* CONFIG_TCG */ diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 9aa8e46566..72ec2be92e 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -843,6 +843,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp) PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); vhc->hypercall(cpu->vhyp, cpu); + powerpc_reset_excp_state(cpu); return; } @@ -1014,6 +1015,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp) PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); vhc->hypercall(cpu->vhyp, cpu); + powerpc_reset_excp_state(cpu); return; } @@ -1526,6 +1528,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) PPCVirtualHypervisorClass *vhc = PPC_VIRTUAL_HYPERVISOR_GET_CLASS(cpu->vhyp); vhc->hypercall(cpu->vhyp, cpu); + powerpc_reset_excp_state(cpu); return; } if (env->insns_flags2 & PPC2_ISA310) { @@ -1571,9 +1574,11 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp) } } break; + case POWERPC_EXCP_TRACE: /* Trace exception */ + msr |= env->error_code; + /* fall through */ case POWERPC_EXCP_DSEG: /* Data segment exception */ case POWERPC_EXCP_ISEG: /* Instruction segment exception */ - case POWERPC_EXCP_TRACE: /* Trace exception */ case POWERPC_EXCP_SDOOR: /* Doorbell interrupt */ case POWERPC_EXCP_PERFM: /* Performance monitor interrupt */ break; @@ -3168,6 +3173,18 @@ void helper_book3s_msgsndp(CPUPPCState *env, target_ulong rb) } #endif /* TARGET_PPC64 */ +/* Single-step tracing */ +void helper_book3s_trace(CPUPPCState *env, target_ulong prev_ip) +{ + uint32_t error_code = 0; + if (env->insns_flags2 & PPC2_ISA207S) { + /* Load/store reporting, SRR1[35, 36] and SDAR, are not implemented. */ + env->spr[SPR_POWER_SIAR] = prev_ip; + error_code = PPC_BIT(33); + } + raise_exception_err(env, POWERPC_EXCP_TRACE, error_code); +} + void ppc_cpu_do_unaligned_access(CPUState *cs, vaddr vaddr, MMUAccessType access_type, int mmu_idx, uintptr_t retaddr) @@ -3243,5 +3260,97 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, cs->exception_index = POWERPC_EXCP_MCHECK; cpu_loop_exit_restore(cs, retaddr); } + +void ppc_cpu_debug_excp_handler(CPUState *cs) +{ +#if defined(TARGET_PPC64) + CPUPPCState *env = cs->env_ptr; + + if (env->insns_flags2 & PPC2_ISA207S) { + if (cs->watchpoint_hit) { + if (cs->watchpoint_hit->flags & BP_CPU) { + env->spr[SPR_DAR] = cs->watchpoint_hit->hitaddr; + env->spr[SPR_DSISR] = PPC_BIT(41); + cs->watchpoint_hit = NULL; + raise_exception(env, POWERPC_EXCP_DSI); + } + cs->watchpoint_hit = NULL; + } else if (cpu_breakpoint_test(cs, env->nip, BP_CPU)) { + raise_exception_err(env, POWERPC_EXCP_TRACE, + PPC_BIT(33) | PPC_BIT(43)); + } + } +#endif +} + +bool ppc_cpu_debug_check_breakpoint(CPUState *cs) +{ +#if defined(TARGET_PPC64) + CPUPPCState *env = cs->env_ptr; + + if (env->insns_flags2 & PPC2_ISA207S) { + target_ulong priv; + + priv = env->spr[SPR_CIABR] & PPC_BITMASK(62, 63); + switch (priv) { + case 0x1: /* problem */ + return env->msr & ((target_ulong)1 << MSR_PR); + case 0x2: /* supervisor */ + return (!(env->msr & ((target_ulong)1 << MSR_PR)) && + !(env->msr & ((target_ulong)1 << MSR_HV))); + case 0x3: /* hypervisor */ + return (!(env->msr & ((target_ulong)1 << MSR_PR)) && + (env->msr & ((target_ulong)1 << MSR_HV))); + default: + g_assert_not_reached(); + } + } +#endif + + return false; +} + +bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp) +{ +#if defined(TARGET_PPC64) + CPUPPCState *env = cs->env_ptr; + + if (env->insns_flags2 & PPC2_ISA207S) { + if (wp == env->dawr0_watchpoint) { + uint32_t dawrx = env->spr[SPR_DAWRX0]; + bool wt = extract32(dawrx, PPC_BIT_NR(59), 1); + bool wti = extract32(dawrx, PPC_BIT_NR(60), 1); + bool hv = extract32(dawrx, PPC_BIT_NR(61), 1); + bool sv = extract32(dawrx, PPC_BIT_NR(62), 1); + bool pr = extract32(dawrx, PPC_BIT_NR(62), 1); + + if ((env->msr & ((target_ulong)1 << MSR_PR)) && !pr) { + return false; + } else if ((env->msr & ((target_ulong)1 << MSR_HV)) && !hv) { + return false; + } else if (!sv) { + return false; + } + + if (!wti) { + if (env->msr & ((target_ulong)1 << MSR_DR)) { + if (!wt) { + return false; + } + } else { + if (wt) { + return false; + } + } + } + + return true; + } + } +#endif + + return false; +} + #endif /* CONFIG_TCG */ #endif /* !CONFIG_USER_ONLY */ diff --git a/target/ppc/helper.h b/target/ppc/helper.h index abec6fe341..86f97ee1e7 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -25,6 +25,9 @@ DEF_HELPER_1(hrfid, void, env) DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) +DEF_HELPER_2(store_ciabr, void, env, tl) +DEF_HELPER_2(store_dawr0, void, env, tl) +DEF_HELPER_2(store_dawrx0, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) DEF_HELPER_2(store_mmcr1, void, env, tl) DEF_HELPER_3(store_pmc, void, env, i32, i64) @@ -32,6 +35,7 @@ DEF_HELPER_2(read_pmc, tl, env, i32) DEF_HELPER_2(insns_inc, void, env, i32) DEF_HELPER_1(handle_pmc5_overflow, void, env) #endif +DEF_HELPER_2(book3s_trace, void, env, tl) DEF_HELPER_1(check_tlb_flush_local, void, env) DEF_HELPER_1(check_tlb_flush_global, void, env) #endif diff --git a/target/ppc/int_helper.c b/target/ppc/int_helper.c index 834da80fe3..96cdb3c7e3 100644 --- a/target/ppc/int_helper.c +++ b/target/ppc/int_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "internal.h" #include "qemu/host-utils.h" -#include "qemu/main-loop.h" #include "qemu/log.h" #include "exec/helper-proto.h" #include "crypto/aes.h" diff --git a/target/ppc/internal.h b/target/ppc/internal.h index 57acb3212c..15803bc313 100644 --- a/target/ppc/internal.h +++ b/target/ppc/internal.h @@ -301,6 +301,9 @@ void ppc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, MMUAccessType access_type, int mmu_idx, MemTxAttrs attrs, MemTxResult response, uintptr_t retaddr); +void ppc_cpu_debug_excp_handler(CPUState *cs); +bool ppc_cpu_debug_check_breakpoint(CPUState *cs); +bool ppc_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp); #endif FIELD(GER_MSK, XMSK, 0, 4) diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c index 7698501743..51112bd367 100644 --- a/target/ppc/kvm.c +++ b/target/ppc/kvm.c @@ -1320,7 +1320,7 @@ int kvmppc_set_interrupt(PowerPCCPU *cpu, int irq, int level) return 0; } - if (!kvm_enabled() || !cap_interrupt_unset) { + if (!cap_interrupt_unset) { return 0; } diff --git a/target/ppc/machine.c b/target/ppc/machine.c index 134b16c625..68cbdffecd 100644 --- a/target/ppc/machine.c +++ b/target/ppc/machine.c @@ -7,9 +7,9 @@ #include "mmu-hash64.h" #include "migration/cpu.h" #include "qapi/error.h" -#include "qemu/main-loop.h" #include "kvm_ppc.h" #include "power8-pmu.h" +#include "sysemu/replay.h" static void post_load_update_msr(CPUPPCState *env) { @@ -209,6 +209,14 @@ static int cpu_pre_save(void *opaque) /* Used to retain migration compatibility for pre 6.0 for 601 machines. */ env->hflags_compat_nmsr = 0; + if (tcg_enabled()) { + /* + * TCG does not maintain the DECR spr (unlike KVM) so have to save + * it here. + */ + env->spr[SPR_DECR] = cpu_ppc_load_decr(env); + } + return 0; } @@ -314,6 +322,17 @@ static int cpu_post_load(void *opaque, int version_id) post_load_update_msr(env); if (tcg_enabled()) { + /* Re-set breaks based on regs */ +#if defined(TARGET_PPC64) + ppc_update_ciabr(env); + ppc_update_daw0(env); +#endif + /* + * TCG needs to re-start the decrementer timer and/or raise the + * interrupt. This works for level-triggered decrementer. Edge + * triggered types (including HDEC) would need to carry more state. + */ + cpu_ppc_store_decr(env, env->spr[SPR_DECR]); pmu_mmcr01_updated(env); } @@ -671,6 +690,27 @@ static const VMStateDescription vmstate_compat = { } }; +static bool reservation_needed(void *opaque) +{ + return (replay_mode != REPLAY_MODE_NONE); +} + +static const VMStateDescription vmstate_reservation = { + .name = "cpu/reservation", + .version_id = 1, + .minimum_version_id = 1, + .needed = reservation_needed, + .fields = (VMStateField[]) { + VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), + VMSTATE_UINTTL(env.reserve_length, PowerPCCPU), + VMSTATE_UINTTL(env.reserve_val, PowerPCCPU), +#if defined(TARGET_PPC64) + VMSTATE_UINTTL(env.reserve_val2, PowerPCCPU), +#endif + VMSTATE_END_OF_LIST() + } +}; + const VMStateDescription vmstate_ppc_cpu = { .name = "cpu", .version_id = 5, @@ -692,8 +732,7 @@ const VMStateDescription vmstate_ppc_cpu = { VMSTATE_UINTTL_ARRAY(env.spr, PowerPCCPU, 1024), VMSTATE_UINT64(env.spe_acc, PowerPCCPU), - /* Reservation */ - VMSTATE_UINTTL(env.reserve_addr, PowerPCCPU), + VMSTATE_UNUSED(sizeof(target_ulong)), /* was env.reserve_addr */ /* Supervisor mode architected state */ VMSTATE_UINTTL(env.msr, PowerPCCPU), @@ -722,6 +761,7 @@ const VMStateDescription vmstate_ppc_cpu = { &vmstate_tlbemb, &vmstate_tlbmas, &vmstate_compat, + &vmstate_reservation, NULL } }; diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c index 46eae65819..c7535481d6 100644 --- a/target/ppc/mem_helper.c +++ b/target/ppc/mem_helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "exec/exec-all.h" #include "qemu/host-utils.h" -#include "qemu/main-loop.h" #include "exec/helper-proto.h" #include "helper_regs.h" #include "exec/cpu_ldst.h" diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c index 692d058665..a05bdf78c9 100644 --- a/target/ppc/misc_helper.c +++ b/target/ppc/misc_helper.c @@ -199,6 +199,21 @@ void helper_store_pcr(CPUPPCState *env, target_ulong value) env->spr[SPR_PCR] = value & pcc->pcr_mask; } +void helper_store_ciabr(CPUPPCState *env, target_ulong value) +{ + ppc_store_ciabr(env, value); +} + +void helper_store_dawr0(CPUPPCState *env, target_ulong value) +{ + ppc_store_dawr0(env, value); +} + +void helper_store_dawrx0(CPUPPCState *env, target_ulong value) +{ + ppc_store_dawrx0(env, value); +} + /* * DPDES register is shared. Each bit reflects the state of the * doorbell interrupt of a thread of the same core. diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c index 920084bd8f..5823e039e6 100644 --- a/target/ppc/mmu-radix64.c +++ b/target/ppc/mmu-radix64.c @@ -219,27 +219,25 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type, return false; } -static void ppc_radix64_set_rc(PowerPCCPU *cpu, MMUAccessType access_type, - uint64_t pte, hwaddr pte_addr, int *prot) +static int ppc_radix64_check_rc(MMUAccessType access_type, uint64_t pte) { - CPUState *cs = CPU(cpu); - uint64_t npte; - - npte = pte | R_PTE_R; /* Always set reference bit */ + switch (access_type) { + case MMU_DATA_STORE: + if (!(pte & R_PTE_C)) { + break; + } + /* fall through */ + case MMU_INST_FETCH: + case MMU_DATA_LOAD: + if (!(pte & R_PTE_R)) { + break; + } - if (access_type == MMU_DATA_STORE) { /* Store/Write */ - npte |= R_PTE_C; /* Set change bit */ - } else { - /* - * Treat the page as read-only for now, so that a later write - * will pass through this function again to set the C bit. - */ - *prot &= ~PAGE_WRITE; + /* R/C bits are already set appropriately for this access */ + return 0; } - if (pte ^ npte) { /* If pte has changed then write it back */ - stq_phys(cs->as, pte_addr, npte); - } + return 1; } static bool ppc_radix64_is_valid_level(int level, int psize, uint64_t nls) @@ -380,7 +378,8 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, ppc_v3_pate_t pate, hwaddr *h_raddr, int *h_prot, int *h_page_size, bool pde_addr, - int mmu_idx, bool guest_visible) + int mmu_idx, uint64_t lpid, + bool guest_visible) { MMUAccessType access_type = orig_access_type; int fault_cause = 0; @@ -418,7 +417,24 @@ static int ppc_radix64_partition_scoped_xlate(PowerPCCPU *cpu, } if (guest_visible) { - ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, h_prot); + if (ppc_radix64_check_rc(access_type, pte)) { + /* + * Per ISA 3.1 Book III, 7.5.3 and 7.5.5, failure to set R/C during + * partition-scoped translation when effLPID = 0 results in normal + * (non-Hypervisor) Data and Instruction Storage Interrupts + * respectively. + * + * ISA 3.0 is ambiguous about this, but tests on POWER9 hardware + * seem to exhibit the same behavior. + */ + if (lpid > 0) { + ppc_radix64_raise_hsi(cpu, access_type, eaddr, g_raddr, + DSISR_ATOMIC_RC); + } else { + ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_ATOMIC_RC); + } + return 1; + } } return 0; @@ -447,7 +463,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, vaddr eaddr, uint64_t pid, ppc_v3_pate_t pate, hwaddr *g_raddr, int *g_prot, int *g_page_size, - int mmu_idx, bool guest_visible) + int mmu_idx, uint64_t lpid, + bool guest_visible) { CPUState *cs = CPU(cpu); CPUPPCState *env = &cpu->env; @@ -497,7 +514,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, ret = ppc_radix64_partition_scoped_xlate(cpu, access_type, eaddr, prtbe_addr, pate, &h_raddr, &h_prot, &h_page_size, true, - 5, guest_visible); + 5, lpid, guest_visible); if (ret) { return ret; } @@ -539,7 +556,8 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, ret = ppc_radix64_partition_scoped_xlate(cpu, access_type, eaddr, pte_addr, pate, &h_raddr, &h_prot, &h_page_size, - true, 5, guest_visible); + true, 5, lpid, + guest_visible); if (ret) { return ret; } @@ -580,7 +598,11 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu, } if (guest_visible) { - ppc_radix64_set_rc(cpu, access_type, pte, pte_addr, g_prot); + /* R/C bits not appropriately set for access */ + if (ppc_radix64_check_rc(access_type, pte)) { + ppc_radix64_raise_si(cpu, access_type, eaddr, DSISR_ATOMIC_RC); + return 1; + } } return 0; @@ -695,7 +717,8 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr, if (relocation) { int ret = ppc_radix64_process_scoped_xlate(cpu, access_type, eaddr, pid, pate, &g_raddr, &prot, - &psize, mmu_idx, guest_visible); + &psize, mmu_idx, lpid, + guest_visible); if (ret) { return false; } @@ -719,7 +742,8 @@ static bool ppc_radix64_xlate_impl(PowerPCCPU *cpu, vaddr eaddr, ret = ppc_radix64_partition_scoped_xlate(cpu, access_type, eaddr, g_raddr, pate, raddr, &prot, &psize, false, - mmu_idx, guest_visible); + mmu_idx, lpid, + guest_visible); if (ret) { return false; } diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c index 8c000e250d..6ca5d12207 100644 --- a/target/ppc/mmu_common.c +++ b/target/ppc/mmu_common.c @@ -28,7 +28,6 @@ #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qemu/qemu-print.h" #include "internal.h" #include "mmu-book3s-v3.h" diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c index d3ea7588f9..f87d35379a 100644 --- a/target/ppc/mmu_helper.c +++ b/target/ppc/mmu_helper.c @@ -28,7 +28,6 @@ #include "exec/log.h" #include "helper_regs.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" #include "qemu/qemu-print.h" #include "internal.h" #include "mmu-book3s-v3.h" diff --git a/target/ppc/power8-pmu.c b/target/ppc/power8-pmu.c index 7bb4bf81f7..cbc5889d91 100644 --- a/target/ppc/power8-pmu.c +++ b/target/ppc/power8-pmu.c @@ -16,7 +16,7 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "qemu/error-report.h" -#include "qemu/main-loop.h" +#include "qemu/timer.h" #include "hw/ppc/ppc.h" #include "power8-pmu.h" diff --git a/target/ppc/spr_common.h b/target/ppc/spr_common.h index 5995070eaf..8a9d6cd994 100644 --- a/target/ppc/spr_common.h +++ b/target/ppc/spr_common.h @@ -159,6 +159,9 @@ void spr_read_mas73(DisasContext *ctx, int gprn, int sprn); #ifdef TARGET_PPC64 void spr_read_cfar(DisasContext *ctx, int gprn, int sprn); void spr_write_cfar(DisasContext *ctx, int sprn, int gprn); +void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn); +void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn); +void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn); void spr_write_ureg(DisasContext *ctx, int sprn, int gprn); void spr_read_purr(DisasContext *ctx, int gprn, int sprn); void spr_write_purr(DisasContext *ctx, int sprn, int gprn); diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 74796ec7ba..6b242ae0a6 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -26,8 +26,6 @@ #include "tcg/tcg-op.h" #include "tcg/tcg-op-gvec.h" #include "qemu/host-utils.h" -#include "qemu/main-loop.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" @@ -77,7 +75,9 @@ static TCGv cpu_xer, cpu_so, cpu_ov, cpu_ca, cpu_ov32, cpu_ca32; static TCGv cpu_reserve; static TCGv cpu_reserve_length; static TCGv cpu_reserve_val; +#if defined(TARGET_PPC64) static TCGv cpu_reserve_val2; +#endif static TCGv cpu_fpscr; static TCGv_i32 cpu_access_type; @@ -151,9 +151,11 @@ void ppc_translate_init(void) cpu_reserve_val = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, reserve_val), "reserve_val"); +#if defined(TARGET_PPC64) cpu_reserve_val2 = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, reserve_val2), "reserve_val2"); +#endif cpu_fpscr = tcg_global_mem_new(cpu_env, offsetof(CPUPPCState, fpscr), "fpscr"); @@ -338,8 +340,9 @@ static void gen_ppc_maybe_interrupt(DisasContext *ctx) * The exception can be either POWERPC_EXCP_TRACE (on most PowerPCs) or * POWERPC_EXCP_DEBUG (on BookE). */ -static uint32_t gen_prep_dbgex(DisasContext *ctx) +static void gen_debug_exception(DisasContext *ctx, bool rfi_type) { +#if !defined(CONFIG_USER_ONLY) if (ctx->flags & POWERPC_FLAG_DE) { target_ulong dbsr = 0; if (ctx->singlestep_enabled & CPU_SINGLE_STEP) { @@ -352,16 +355,18 @@ static uint32_t gen_prep_dbgex(DisasContext *ctx) gen_load_spr(t0, SPR_BOOKE_DBSR); tcg_gen_ori_tl(t0, t0, dbsr); gen_store_spr(SPR_BOOKE_DBSR, t0); - return POWERPC_EXCP_DEBUG; + gen_helper_raise_exception(cpu_env, + tcg_constant_i32(POWERPC_EXCP_DEBUG)); + ctx->base.is_jmp = DISAS_NORETURN; } else { - return POWERPC_EXCP_TRACE; + if (!rfi_type) { /* BookS does not single step rfi type instructions */ + TCGv t0 = tcg_temp_new(); + tcg_gen_movi_tl(t0, ctx->cia); + gen_helper_book3s_trace(cpu_env, t0); + ctx->base.is_jmp = DISAS_NORETURN; + } } -} - -static void gen_debug_exception(DisasContext *ctx) -{ - gen_helper_raise_exception(cpu_env, tcg_constant_i32(gen_prep_dbgex(ctx))); - ctx->base.is_jmp = DISAS_NORETURN; +#endif } static inline void gen_inval_exception(DisasContext *ctx, uint32_t error) @@ -556,8 +561,9 @@ void spr_write_lr(DisasContext *ctx, int sprn, int gprn) tcg_gen_mov_tl(cpu_lr, cpu_gpr[gprn]); } -/* CFAR */ #if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +/* Debug facilities */ +/* CFAR */ void spr_read_cfar(DisasContext *ctx, int gprn, int sprn) { tcg_gen_mov_tl(cpu_gpr[gprn], cpu_cfar); @@ -567,6 +573,26 @@ void spr_write_cfar(DisasContext *ctx, int sprn, int gprn) { tcg_gen_mov_tl(cpu_cfar, cpu_gpr[gprn]); } + +/* Breakpoint */ +void spr_write_ciabr(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_ciabr(cpu_env, cpu_gpr[gprn]); +} + +/* Watchpoint */ +void spr_write_dawr0(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_dawr0(cpu_env, cpu_gpr[gprn]); +} + +void spr_write_dawrx0(DisasContext *ctx, int sprn, int gprn) +{ + translator_io_start(&ctx->base); + gen_helper_store_dawrx0(cpu_env, cpu_gpr[gprn]); +} #endif /* defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) */ /* CTR */ @@ -4184,7 +4210,7 @@ static inline bool use_goto_tb(DisasContext *ctx, target_ulong dest) static void gen_lookup_and_goto_ptr(DisasContext *ctx) { if (unlikely(ctx->singlestep_enabled)) { - gen_debug_exception(ctx); + gen_debug_exception(ctx, false); } else { /* * tcg_gen_lookup_and_goto_ptr will exit the TB if @@ -7410,8 +7436,9 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) } /* Honor single stepping. */ - if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP) - && (nip <= 0x100 || nip > 0xf00)) { + if (unlikely(ctx->singlestep_enabled & CPU_SINGLE_STEP)) { + bool rfi_type = false; + switch (is_jmp) { case DISAS_TOO_MANY: case DISAS_EXIT_UPDATE: @@ -7420,12 +7447,19 @@ static void ppc_tr_tb_stop(DisasContextBase *dcbase, CPUState *cs) break; case DISAS_EXIT: case DISAS_CHAIN: + /* + * This is a heuristic, to put it kindly. The rfi class of + * instructions are among the few outside branches that change + * NIP without taking an interrupt. Single step trace interrupts + * do not fire on completion of these instructions. + */ + rfi_type = true; break; default: g_assert_not_reached(); } - gen_debug_exception(ctx); + gen_debug_exception(ctx, rfi_type); return; } diff --git a/target/ppc/translate/fixedpoint-impl.c.inc b/target/ppc/translate/fixedpoint-impl.c.inc index 4ce02fd3a4..7ff7e1ec46 100644 --- a/target/ppc/translate/fixedpoint-impl.c.inc +++ b/target/ppc/translate/fixedpoint-impl.c.inc @@ -71,7 +71,7 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed) { #if defined(TARGET_PPC64) TCGv ea; - TCGv_i64 low_addr_gpr, high_addr_gpr; + TCGv_i64 lo, hi; TCGv_i128 t16; REQUIRE_INSNS_FLAGS(ctx, 64BX); @@ -94,21 +94,21 @@ static bool do_ldst_quad(DisasContext *ctx, arg_D *a, bool store, bool prefixed) gen_set_access_type(ctx, ACCESS_INT); ea = do_ea_calc(ctx, a->ra, tcg_constant_tl(a->si)); - if (prefixed || !ctx->le_mode) { - low_addr_gpr = cpu_gpr[a->rt]; - high_addr_gpr = cpu_gpr[a->rt + 1]; + if (ctx->le_mode && prefixed) { + lo = cpu_gpr[a->rt]; + hi = cpu_gpr[a->rt + 1]; } else { - low_addr_gpr = cpu_gpr[a->rt + 1]; - high_addr_gpr = cpu_gpr[a->rt]; + lo = cpu_gpr[a->rt + 1]; + hi = cpu_gpr[a->rt]; } t16 = tcg_temp_new_i128(); if (store) { - tcg_gen_concat_i64_i128(t16, low_addr_gpr, high_addr_gpr); + tcg_gen_concat_i64_i128(t16, lo, hi); tcg_gen_qemu_st_i128(t16, ea, ctx->mem_idx, DEF_MEMOP(MO_128)); } else { tcg_gen_qemu_ld_i128(t16, ea, ctx->mem_idx, DEF_MEMOP(MO_128)); - tcg_gen_extr_i128_i64(low_addr_gpr, high_addr_gpr, t16); + tcg_gen_extr_i128_i64(lo, hi, t16); } #else qemu_build_not_reached(); diff --git a/target/riscv/csr.c b/target/riscv/csr.c index ea7585329e..de31818daa 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "pmu.h" #include "time_helper.h" -#include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/tb-flush.h" #include "sysemu/cpu-timers.h" diff --git a/target/riscv/m128_helper.c b/target/riscv/m128_helper.c index e6a4f6120a..ec14aaa901 100644 --- a/target/riscv/m128_helper.c +++ b/target/riscv/m128_helper.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "cpu.h" -#include "qemu/main-loop.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 9cdb9cdd06..5355225d56 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -21,8 +21,8 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internals.h" -#include "qemu/main-loop.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" /* Exceptions processing helpers */ diff --git a/target/riscv/pmu.c b/target/riscv/pmu.c index db06b3882f..36f6307d28 100644 --- a/target/riscv/pmu.c +++ b/target/riscv/pmu.c @@ -17,6 +17,7 @@ */ #include "qemu/osdep.h" +#include "qemu/log.h" #include "cpu.h" #include "pmu.h" #include "sysemu/cpu-timers.h" diff --git a/target/riscv/pmu.h b/target/riscv/pmu.h index 0c819ca983..2bfb71ba87 100644 --- a/target/riscv/pmu.h +++ b/target/riscv/pmu.h @@ -16,10 +16,7 @@ * this program. If not, see <http://www.gnu.org/licenses/>. */ -#include "qemu/log.h" #include "cpu.h" -#include "qemu/main-loop.h" -#include "exec/exec-all.h" bool riscv_pmu_ctr_monitor_instructions(CPURISCVState *env, uint32_t target_ctr); diff --git a/target/riscv/vector_helper.c b/target/riscv/vector_helper.c index bf7e0029a1..bc9e151aa9 100644 --- a/target/riscv/vector_helper.c +++ b/target/riscv/vector_helper.c @@ -22,6 +22,7 @@ #include "cpu.h" #include "exec/memop.h" #include "exec/exec-all.h" +#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" #include "tcg/tcg-gvec-desc.h" diff --git a/target/s390x/cpu.h b/target/s390x/cpu.h index eb5b65b7d3..304029e57c 100644 --- a/target/s390x/cpu.h +++ b/target/s390x/cpu.h @@ -36,6 +36,8 @@ /* The z/Architecture has a strong memory model with some store-after-load re-ordering */ #define TCG_GUEST_DEFAULT_MO (TCG_MO_ALL & ~TCG_MO_ST_LD) +#define TARGET_HAS_PRECISE_SMC + #define TARGET_INSN_START_EXTRA_WORDS 2 #define MMU_USER_IDX 0 diff --git a/target/s390x/tcg/crypto_helper.c b/target/s390x/tcg/crypto_helper.c index 762b277884..93aabd236f 100644 --- a/target/s390x/tcg/crypto_helper.c +++ b/target/s390x/tcg/crypto_helper.c @@ -13,7 +13,6 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "s390x-internal.h" #include "tcg_s390x.h" diff --git a/target/s390x/tcg/excp_helper.c b/target/s390x/tcg/excp_helper.c index b7116d0577..b875bf14e5 100644 --- a/target/s390x/tcg/excp_helper.c +++ b/target/s390x/tcg/excp_helper.c @@ -23,7 +23,6 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "s390x-internal.h" #include "tcg_s390x.h" #ifndef CONFIG_USER_ONLY diff --git a/target/s390x/tcg/fpu_helper.c b/target/s390x/tcg/fpu_helper.c index c329b31261..d8bd5748fa 100644 --- a/target/s390x/tcg/fpu_helper.c +++ b/target/s390x/tcg/fpu_helper.c @@ -23,7 +23,6 @@ #include "s390x-internal.h" #include "tcg_s390x.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "fpu/softfloat.h" diff --git a/target/s390x/tcg/misc_helper.c b/target/s390x/tcg/misc_helper.c index 576157b1f3..e85658ce22 100644 --- a/target/s390x/tcg/misc_helper.c +++ b/target/s390x/tcg/misc_helper.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "s390x-internal.h" #include "qemu/host-utils.h" diff --git a/target/sh4/translate.c b/target/sh4/translate.c index 49c87d7a01..c1e590feb3 100644 --- a/target/sh4/translate.c +++ b/target/sh4/translate.c @@ -22,7 +22,6 @@ #include "disas/disas.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" #include "exec/helper-proto.h" #include "exec/helper-gen.h" #include "exec/translator.h" diff --git a/target/sparc/translate.c b/target/sparc/translate.c index fa80a91161..3bf0ab8135 100644 --- a/target/sparc/translate.c +++ b/target/sparc/translate.c @@ -25,7 +25,6 @@ #include "exec/helper-proto.h" #include "exec/exec-all.h" #include "tcg/tcg-op.h" -#include "exec/cpu_ldst.h" #include "exec/helper-gen.h" diff --git a/target/xtensa/dbg_helper.c b/target/xtensa/dbg_helper.c index ce2a820c60..3e0c9e8e8b 100644 --- a/target/xtensa/dbg_helper.c +++ b/target/xtensa/dbg_helper.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/target/xtensa/exc_helper.c b/target/xtensa/exc_helper.c index 43f6a862de..91354884f7 100644 --- a/target/xtensa/exc_helper.c +++ b/target/xtensa/exc_helper.c @@ -31,6 +31,7 @@ #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" +#include "qemu/atomic.h" #include "exec/exec-all.h" void HELPER(exception)(CPUXtensaState *env, uint32_t excp) diff --git a/target/xtensa/fpu_helper.c b/target/xtensa/fpu_helper.c index d2a10cc797..381e83ded8 100644 --- a/target/xtensa/fpu_helper.c +++ b/target/xtensa/fpu_helper.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/target/xtensa/mmu_helper.c b/target/xtensa/mmu_helper.c index fa66e8e867..12552a3347 100644 --- a/target/xtensa/mmu_helper.c +++ b/target/xtensa/mmu_helper.c @@ -27,14 +27,12 @@ #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "qemu/qemu-print.h" #include "qemu/units.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" #define XTENSA_MPU_SEGMENT_MASK 0x0000001f #define XTENSA_MPU_ACC_RIGHTS_MASK 0x00000f00 diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 1af7becc54..7bb8cd6726 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -26,12 +26,11 @@ */ #include "qemu/osdep.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" #include "exec/exec-all.h" -#include "exec/cpu_ldst.h" +#include "qemu/atomic.h" #include "qemu/timer.h" #ifndef CONFIG_USER_ONLY diff --git a/target/xtensa/win_helper.c b/target/xtensa/win_helper.c index 5a1555360a..ec9ff44db0 100644 --- a/target/xtensa/win_helper.c +++ b/target/xtensa/win_helper.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" -#include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" #include "qemu/host-utils.h" diff --git a/tcg/tcg-internal.h b/tcg/tcg-internal.h index fbe62b31b8..40a69e6e6e 100644 --- a/tcg/tcg-internal.h +++ b/tcg/tcg-internal.h @@ -64,8 +64,8 @@ static inline TCGv_i32 TCGV_HIGH(TCGv_i64 t) return temp_tcgv_i32(tcgv_i64_temp(t) + !HOST_BIG_ENDIAN); } #else -extern TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); -extern TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); +TCGv_i32 TCGV_LOW(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); +TCGv_i32 TCGV_HIGH(TCGv_i64) QEMU_ERROR("32-bit code path is reachable"); #endif static inline TCGv_i64 TCGV128_LOW(TCGv_i128 t) diff --git a/tests/avocado/machine_aspeed.py b/tests/avocado/machine_aspeed.py index 724ee72c02..90f1b7cb77 100644 --- a/tests/avocado/machine_aspeed.py +++ b/tests/avocado/machine_aspeed.py @@ -316,8 +316,8 @@ class AST2x00MachineSDK(QemuSystemTest, LinuxSSHMixIn): """ image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/' - 'download/v08.01/ast2500-default-obmc.tar.gz') - image_hash = ('5375f82b4c43a79427909342a1e18b4e48bd663e38466862145d27bb358796fd') + 'download/v08.06/ast2500-default-obmc.tar.gz') + image_hash = ('e1755f3cadff69190438c688d52dd0f0d399b70a1e14b1d3d5540fc4851d38ca') image_path = self.fetch_asset(image_url, asset_hash=image_hash, algorithm='sha256') archive.extract(image_path, self.workdir) @@ -334,8 +334,8 @@ class AST2x00MachineSDK(QemuSystemTest, LinuxSSHMixIn): """ image_url = ('https://github.com/AspeedTech-BMC/openbmc/releases/' - 'download/v08.01/ast2600-default-obmc.tar.gz') - image_hash = ('f12ef15e8c1f03a214df3b91c814515c5e2b2f56119021398c1dbdd626817d15') + 'download/v08.06/ast2600-a2-obmc.tar.gz') + image_hash = ('9083506135f622d5e7351fcf7d4e1c7125cee5ba16141220c0ba88931f3681a4') image_path = self.fetch_asset(image_url, asset_hash=image_hash, algorithm='sha256') archive.extract(image_path, self.workdir) @@ -345,8 +345,8 @@ class AST2x00MachineSDK(QemuSystemTest, LinuxSSHMixIn): self.vm.add_args('-device', 'ds1338,bus=aspeed.i2c.bus.5,address=0x32'); self.do_test_arm_aspeed_sdk_start( - self.workdir + '/ast2600-default/image-bmc') - self.wait_for_console_pattern('nodistro.0 ast2600-default ttyS4') + self.workdir + '/ast2600-a2/image-bmc') + self.wait_for_console_pattern('nodistro.0 ast2600-a2 ttyS4') self.ssh_connect('root', '0penBmc', False) self.ssh_command('dmesg -c > /dev/null') diff --git a/tests/avocado/replay_kernel.py b/tests/avocado/replay_kernel.py index 79c607b0e7..a18610542e 100644 --- a/tests/avocado/replay_kernel.py +++ b/tests/avocado/replay_kernel.py @@ -255,8 +255,7 @@ class ReplayKernelNormal(ReplayKernelBase): kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) kernel_command_line = self.KERNEL_COMMON_COMMAND_LINE + 'console=hvc0' - # icount is not good enough for PPC64 for complete boot yet - console_pattern = 'Kernel command line: %s' % kernel_command_line + console_pattern = 'VFS: Cannot open root device' self.run_rr(kernel_path, kernel_command_line, console_pattern) def test_ppc64_powernv(self): diff --git a/tests/avocado/reverse_debugging.py b/tests/avocado/reverse_debugging.py index 680c314cfc..fc47874eda 100644 --- a/tests/avocado/reverse_debugging.py +++ b/tests/avocado/reverse_debugging.py @@ -150,16 +150,33 @@ class ReverseDebugging(LinuxKernelTest): self.check_pc(g, addr) logger.info('found position %x' % addr) - logger.info('seeking to the end (icount %s)' % (last_icount - 1)) - vm.qmp('replay-break', icount=last_icount - 1) - # continue - will return after pausing - g.cmd(b'c', b'T02thread:01;') + # visit the recorded instruction in forward order + logger.info('stepping forward') + for addr in steps: + self.check_pc(g, addr) + self.gdb_step(g) + logger.info('found position %x' % addr) + # set breakpoints for the instructions just stepped over logger.info('setting breakpoints') for addr in steps: # hardware breakpoint at addr with len=1 g.cmd(b'Z1,%x,1' % addr, b'OK') + # this may hit a breakpoint if first instructions are executed + # again + logger.info('continuing execution') + vm.qmp('replay-break', icount=last_icount - 1) + # continue - will return after pausing + # This could stop at the end and get a T02 return, or by + # re-executing one of the breakpoints and get a T05 return. + g.cmd(b'c') + if self.vm_get_icount(vm) == last_icount - 1: + logger.info('reached the end (icount %s)' % (last_icount - 1)) + else: + logger.info('hit a breakpoint again at %x (icount %s)' % + (self.get_pc(g), self.vm_get_icount(vm))) + logger.info('running reverse continue to reach %x' % steps[-1]) # reverse continue - will return after stopping at the breakpoint g.cmd(b'bc', b'T05thread:01;') @@ -216,3 +233,32 @@ class ReverseDebugging_AArch64(ReverseDebugging): self.reverse_debugging( args=('-kernel', kernel_path)) + +class ReverseDebugging_ppc64(ReverseDebugging): + """ + :avocado: tags=accel:tcg + """ + + REG_PC = 0x40 + + # unidentified gitlab timeout problem + @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') + def test_ppc64_pseries(self): + """ + :avocado: tags=arch:ppc64 + :avocado: tags=machine:pseries + """ + # SLOF branches back to its entry point, which causes this test + # to take the 'hit a breakpoint again' path. That's not a problem, + # just slightly different than the other machines. + self.endian_is_le = False + self.reverse_debugging() + + @skipIf(os.getenv('GITLAB_CI'), 'Running on GitLab') + def test_ppc64_powernv(self): + """ + :avocado: tags=arch:ppc64 + :avocado: tags=machine:powernv + """ + self.endian_is_le = False + self.reverse_debugging() diff --git a/tests/qemu-iotests/131 b/tests/qemu-iotests/131 index a847692b4c..304bbb3f61 100755 --- a/tests/qemu-iotests/131 +++ b/tests/qemu-iotests/131 @@ -44,31 +44,35 @@ _supported_os Linux inuse_offset=$((0x2c)) size=$((64 * 1024 * 1024)) -CLUSTER_SIZE=64k IMGFMT=parallels _make_test_img $size +# get cluster size in sectors from "tracks" header field +CLUSTER_SIZE_OFFSET=28 +CLUSTER_SIZE=$(peek_file_le $TEST_IMG $CLUSTER_SIZE_OFFSET 4) +CLUSTER_SIZE=$((CLUSTER_SIZE * 512)) +CLUSTER_HALF_SIZE=$((CLUSTER_SIZE / 2)) +CLUSTER_DBL_SIZE=$((CLUSTER_SIZE * 2)) + echo == read empty image == -{ $QEMU_IO -c "read -P 0 32k 64k" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir +{ $QEMU_IO -c "read -P 0 $CLUSTER_HALF_SIZE $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir echo == write more than 1 block in a row == -{ $QEMU_IO -c "write -P 0x11 32k 128k" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir +{ $QEMU_IO -c "write -P 0x11 $CLUSTER_HALF_SIZE $CLUSTER_DBL_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir echo == read less than block == -{ $QEMU_IO -c "read -P 0x11 32k 32k" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir +{ $QEMU_IO -c "read -P 0x11 $CLUSTER_HALF_SIZE $CLUSTER_HALF_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir echo == read exactly 1 block == -{ $QEMU_IO -c "read -P 0x11 64k 64k" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir +{ $QEMU_IO -c "read -P 0x11 $CLUSTER_SIZE $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir echo == read more than 1 block == -{ $QEMU_IO -c "read -P 0x11 32k 128k" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir +{ $QEMU_IO -c "read -P 0x11 $CLUSTER_HALF_SIZE $CLUSTER_DBL_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir echo == check that there is no trash after written == -{ $QEMU_IO -c "read -P 0 160k 32k" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir +{ $QEMU_IO -c "read -P 0 $((CLUSTER_HALF_SIZE + CLUSTER_DBL_SIZE)) $CLUSTER_HALF_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir echo == check that there is no trash before written == -{ $QEMU_IO -c "read -P 0 0 32k" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir +{ $QEMU_IO -c "read -P 0 0 $CLUSTER_HALF_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir -echo "== Corrupt image ==" +echo "== corrupt image ==" poke_file "$TEST_IMG" "$inuse_offset" "\x59\x6e\x6f\x74" -{ $QEMU_IO -c "read -P 0x11 64k 64k" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir -_check_test_img -_check_test_img -r all -{ $QEMU_IO -c "read -P 0x11 64k 64k" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir +echo "== read corrupted image with repairing ==" +{ $QEMU_IO -c "read -P 0x11 $CLUSTER_SIZE $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir echo "== allocate with backing ==" # Verify that allocating clusters works fine even when there is a backing image. @@ -83,7 +87,7 @@ TEST_IMG="$TEST_IMG.base" _make_test_img $size # Write some data to the base image (which would trigger an assertion failure if # interpreted as a QEMUIOVector) -$QEMU_IO -c 'write -P 42 0 64k' "$TEST_IMG.base" | _filter_qemu_io +$QEMU_IO -c "write -P 42 0 $CLUSTER_SIZE" "$TEST_IMG.base" | _filter_qemu_io # Parallels does not seem to support storing a backing filename in the image # itself, so we need to build our backing chain on the command line @@ -99,8 +103,8 @@ QEMU_IO_OPTIONS=$QEMU_IO_OPTIONS_NO_FMT \ QEMU_IO_OPTIONS=$QEMU_IO_OPTIONS_NO_FMT \ $QEMU_IO --image-opts "$imgopts" \ -c 'read -P 1 0 64' \ - -c "read -P 42 64 $((64 * 1024 - 64))" \ - -c "read -P 0 64k $((size - 64 * 1024))" \ + -c "read -P 42 64 $((CLUSTER_SIZE - 64))" \ + -c "read -P 0 $CLUSTER_SIZE $((size - CLUSTER_SIZE))" \ | _filter_qemu_io # success, all done diff --git a/tests/qemu-iotests/131.out b/tests/qemu-iotests/131.out index de5ef7a8f5..d2904578df 100644 --- a/tests/qemu-iotests/131.out +++ b/tests/qemu-iotests/131.out @@ -1,53 +1,42 @@ QA output created by 131 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 == read empty image == -read 65536/65536 bytes at offset 32768 -64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 1048576/1048576 bytes at offset 524288 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) == write more than 1 block in a row == -wrote 131072/131072 bytes at offset 32768 -128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +wrote 2097152/2097152 bytes at offset 524288 +2 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) == read less than block == -read 32768/32768 bytes at offset 32768 -32 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 524288/524288 bytes at offset 524288 +512 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) == read exactly 1 block == -read 65536/65536 bytes at offset 65536 -64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 1048576/1048576 bytes at offset 1048576 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) == read more than 1 block == -read 131072/131072 bytes at offset 32768 -128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 2097152/2097152 bytes at offset 524288 +2 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) == check that there is no trash after written == -read 32768/32768 bytes at offset 163840 -32 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 524288/524288 bytes at offset 2621440 +512 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) == check that there is no trash before written == -read 32768/32768 bytes at offset 0 -32 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -== Corrupt image == -qemu-io: can't open device TEST_DIR/t.parallels: parallels: Image was not closed correctly; cannot be opened read/write -ERROR image was not closed correctly - -1 errors were found on the image. -Data may be corrupted, or further writes to the image may corrupt it. +read 524288/524288 bytes at offset 0 +512 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +== corrupt image == +== read corrupted image with repairing == Repairing image was not closed correctly -The following inconsistencies were found and repaired: - - 0 leaked clusters - 1 corruptions - -Double checking the fixed image now... -No errors were found on the image. -read 65536/65536 bytes at offset 65536 -64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 1048576/1048576 bytes at offset 1048576 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) == allocate with backing == Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 Formatting 'TEST_DIR/t.IMGFMT.base', fmt=IMGFMT size=67108864 -wrote 65536/65536 bytes at offset 0 -64 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +wrote 1048576/1048576 bytes at offset 0 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) wrote 64/64 bytes at offset 0 64 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) read 64/64 bytes at offset 0 64 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -read 65472/65472 bytes at offset 64 -63.938 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -read 67043328/67043328 bytes at offset 65536 -63.938 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 1048512/1048512 bytes at offset 64 +1023.938 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 66060288/66060288 bytes at offset 1048576 +63 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) *** done diff --git a/tests/qemu-iotests/tests/parallels-checks b/tests/qemu-iotests/tests/parallels-checks new file mode 100755 index 0000000000..a7a1b357b5 --- /dev/null +++ b/tests/qemu-iotests/tests/parallels-checks @@ -0,0 +1,145 @@ +#!/usr/bin/env bash +# group: rw quick +# +# Test qemu-img check for parallels format +# +# Copyright (C) 2022 Virtuozzo International GmbH +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +# creator +owner=alexander.ivanov@virtuozzo.com + +seq=`basename $0` +echo "QA output created by $seq" + +status=1 # failure is the default! + +_cleanup() +{ + _cleanup_test_img +} +trap "_cleanup; exit \$status" 0 1 2 3 15 + +# get standard environment, filters and checks +. ../common.rc +. ../common.filter + +_supported_fmt parallels +_supported_proto file +_supported_os Linux + +SIZE=$((4 * 1024 * 1024)) +IMGFMT=parallels +CLUSTER_SIZE_OFFSET=28 +DATA_OFF_OFFSET=48 +BAT_OFFSET=64 + +_make_test_img $SIZE + +CLUSTER_SIZE=$(peek_file_le $TEST_IMG $CLUSTER_SIZE_OFFSET 4) +CLUSTER_SIZE=$((CLUSTER_SIZE * 512)) +LAST_CLUSTER_OFF=$((SIZE - CLUSTER_SIZE)) +LAST_CLUSTER=$((LAST_CLUSTER_OFF/CLUSTER_SIZE)) + +echo "== TEST OUT OF IMAGE CHECK ==" + +echo "== write pattern ==" +{ $QEMU_IO -c "write -P 0x11 0 $SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +echo "== corrupt image ==" +cluster=$(($LAST_CLUSTER + 2)) +poke_file "$TEST_IMG" "$BAT_OFFSET" "\x$cluster\x00\x00\x00" + +echo "== read corrupted image with repairing ==" +{ $QEMU_IO -c "read -P 0x00 0 $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +# Clear image +_make_test_img $SIZE + +echo "== TEST LEAK CHECK ==" + +echo "== write pattern to last cluster ==" +echo "write -P 0x11 $LAST_CLUSTER_OFF $CLUSTER_SIZE" +{ $QEMU_IO -c "write -P 0x11 $LAST_CLUSTER_OFF $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +file_size=`stat --printf="%s" "$TEST_IMG"` +echo "file size: $file_size" + +echo "== extend image by 1 cluster ==" +fallocate -xl $((file_size + CLUSTER_SIZE)) "$TEST_IMG" + +file_size=`stat --printf="%s" "$TEST_IMG"` +echo "file size: $file_size" + +echo "== repair image ==" +_check_test_img -r all + +file_size=`stat --printf="%s" "$TEST_IMG"` +echo "file size: $file_size" + +echo "== check last cluster ==" +{ $QEMU_IO -c "read -P 0x11 $LAST_CLUSTER_OFF $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +# Clear image +_make_test_img $SIZE + +echo "== TEST DUPLICATION CHECK ==" + +echo "== write pattern to whole image ==" +{ $QEMU_IO -c "write -P 0x11 0 $SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +echo "== write another pattern to second cluster ==" +{ $QEMU_IO -c "write -P 0x55 $CLUSTER_SIZE $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +echo "== check second cluster ==" +{ $QEMU_IO -c "read -P 0x55 $CLUSTER_SIZE $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +echo "== corrupt image ==" +poke_file "$TEST_IMG" "$(($BAT_OFFSET + 4))" "\x01\x00\x00\x00" + +echo "== check second cluster ==" +{ $QEMU_IO -c "read -P 0x11 $CLUSTER_SIZE $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +echo "== repair image ==" +_check_test_img -r all + +echo "== check second cluster ==" +{ $QEMU_IO -c "read -P 0x11 $CLUSTER_SIZE $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +echo "== check first cluster on host ==" +printf "content: 0x%02x\n" `peek_file_le $TEST_IMG $(($CLUSTER_SIZE)) 1` + +echo "== check second cluster on host ==" +printf "content: 0x%02x\n" `peek_file_le $TEST_IMG $(($CLUSTER_SIZE)) 1` + +# Clear image +_make_test_img $SIZE + +echo "== TEST DATA_OFF CHECK ==" + +echo "== write pattern to first cluster ==" +{ $QEMU_IO -c "write -P 0x55 0 $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +echo "== spoil data_off field ==" +poke_file "$TEST_IMG" "$DATA_OFF_OFFSET" "\xff\xff\xff\xff" + +echo "== check first cluster ==" +{ $QEMU_IO -c "read -P 0x55 0 $CLUSTER_SIZE" "$TEST_IMG"; } 2>&1 | _filter_qemu_io | _filter_testdir + +# success, all done +echo "*** done" +rm -f $seq.full +status=0 diff --git a/tests/qemu-iotests/tests/parallels-checks.out b/tests/qemu-iotests/tests/parallels-checks.out new file mode 100644 index 0000000000..98a3a7f55e --- /dev/null +++ b/tests/qemu-iotests/tests/parallels-checks.out @@ -0,0 +1,75 @@ +QA output created by parallels-checks +Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=4194304 +== TEST OUT OF IMAGE CHECK == +== write pattern == +wrote 4194304/4194304 bytes at offset 0 +4 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +== corrupt image == +== read corrupted image with repairing == +Repairing cluster 0 is outside image +read 1048576/1048576 bytes at offset 0 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=4194304 +== TEST LEAK CHECK == +== write pattern to last cluster == +write -P 0x11 3145728 1048576 +wrote 1048576/1048576 bytes at offset 3145728 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +file size: 2097152 +== extend image by 1 cluster == +file size: 3145728 +== repair image == +Repairing space leaked at the end of the image 1048576 +The following inconsistencies were found and repaired: + + 1 leaked clusters + 0 corruptions + +Double checking the fixed image now... +No errors were found on the image. +file size: 2097152 +== check last cluster == +read 1048576/1048576 bytes at offset 3145728 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=4194304 +== TEST DUPLICATION CHECK == +== write pattern to whole image == +wrote 4194304/4194304 bytes at offset 0 +4 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +== write another pattern to second cluster == +wrote 1048576/1048576 bytes at offset 1048576 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +== check second cluster == +read 1048576/1048576 bytes at offset 1048576 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +== corrupt image == +== check second cluster == +read 1048576/1048576 bytes at offset 1048576 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +== repair image == +Repairing duplicate offset in BAT entry 1 +The following inconsistencies were found and repaired: + + 0 leaked clusters + 1 corruptions + +Double checking the fixed image now... +No errors were found on the image. +== check second cluster == +read 1048576/1048576 bytes at offset 1048576 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +== check first cluster on host == +content: 0x11 +== check second cluster on host == +content: 0x11 +Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=4194304 +== TEST DATA_OFF CHECK == +== write pattern to first cluster == +wrote 1048576/1048576 bytes at offset 0 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +== spoil data_off field == +== check first cluster == +Repairing data_off field has incorrect value +read 1048576/1048576 bytes at offset 0 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +*** done diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 47ba20b957..dd06e6300a 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -2138,7 +2138,9 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/core-count2", test_acpi_q35_tcg_core_count2); } - qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); + if (qtest_has_device("virtio-iommu-pci")) { + qtest_add_func("acpi/q35/viot", test_acpi_q35_viot); + } #ifdef CONFIG_POSIX qtest_add_func("acpi/q35/cxl", test_acpi_q35_cxl); #endif @@ -2173,7 +2175,9 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); qtest_add_func("acpi/virt/pxb", test_acpi_virt_tcg_pxb); qtest_add_func("acpi/virt/oem-fields", test_acpi_virt_oem_fields); - qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); + if (qtest_has_device("virtio-iommu-pci")) { + qtest_add_func("acpi/virt/viot", test_acpi_virt_viot); + } } } ret = g_test_run(); diff --git a/tests/qtest/libqos/ahci.c b/tests/qtest/libqos/ahci.c index f53f12aa99..a2c94c6e06 100644 --- a/tests/qtest/libqos/ahci.c +++ b/tests/qtest/libqos/ahci.c @@ -404,57 +404,110 @@ void ahci_port_clear(AHCIQState *ahci, uint8_t port) /** * Check a port for errors. */ -void ahci_port_check_error(AHCIQState *ahci, uint8_t port, - uint32_t imask, uint8_t emask) +void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd) { + uint8_t port = cmd->port; uint32_t reg; - /* The upper 9 bits of the IS register all indicate errors. */ - reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); - reg &= ~imask; - reg >>= 23; - g_assert_cmphex(reg, ==, 0); + /* If expecting TF error, ensure that TFES is set. */ + if (cmd->errors) { + reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); + ASSERT_BIT_SET(reg, AHCI_PX_IS_TFES); + } else { + /* The upper 9 bits of the IS register all indicate errors. */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); + reg &= ~cmd->interrupts; + reg >>= 23; + g_assert_cmphex(reg, ==, 0); + } - /* The Sata Error Register should be empty. */ + /* The Sata Error Register should be empty, even when expecting TF error. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_SERR); g_assert_cmphex(reg, ==, 0); + /* If expecting TF error, and TFES was set, perform error recovery + * (see AHCI 1.3 section 6.2.2.1) such that we can send new commands. */ + if (cmd->errors) { + /* This will clear PxCI. */ + ahci_px_clr(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST); + + /* The port has 500ms to disengage. */ + usleep(500000); + reg = ahci_px_rreg(ahci, port, AHCI_PX_CMD); + ASSERT_BIT_CLEAR(reg, AHCI_PX_CMD_CR); + + /* Clear PxIS. */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); + ahci_px_wreg(ahci, port, AHCI_PX_IS, reg); + + /* Check if we need to perform a COMRESET. + * Not implemented right now, as there is no reason why our QEMU model + * should need a COMRESET when expecting TF error. */ + reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); + ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_BSY | AHCI_PX_TFD_STS_DRQ); + + /* Enable issuing new commands. */ + ahci_px_set(ahci, port, AHCI_PX_CMD, AHCI_PX_CMD_ST); + } + /* The TFD also has two error sections. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); - if (!emask) { + if (!cmd->errors) { ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_STS_ERR); } else { ASSERT_BIT_SET(reg, AHCI_PX_TFD_STS_ERR); } - ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~emask << 8)); - ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (emask << 8)); + ASSERT_BIT_CLEAR(reg, AHCI_PX_TFD_ERR & (~cmd->errors << 8)); + ASSERT_BIT_SET(reg, AHCI_PX_TFD_ERR & (cmd->errors << 8)); } -void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, - uint32_t intr_mask) +void ahci_port_check_interrupts(AHCIQState *ahci, AHCICommand *cmd) { + uint8_t port = cmd->port; uint32_t reg; + /* If we expect errors, error handling in ahci_port_check_error() will + * already have cleared PxIS, so in that case this function cannot verify + * and clear expected interrupts. */ + if (cmd->errors) { + return; + } + /* Check for expected interrupts */ reg = ahci_px_rreg(ahci, port, AHCI_PX_IS); - ASSERT_BIT_SET(reg, intr_mask); + ASSERT_BIT_SET(reg, cmd->interrupts); /* Clear expected interrupts and assert all interrupts now cleared. */ - ahci_px_wreg(ahci, port, AHCI_PX_IS, intr_mask); + ahci_px_wreg(ahci, port, AHCI_PX_IS, cmd->interrupts); g_assert_cmphex(ahci_px_rreg(ahci, port, AHCI_PX_IS), ==, 0); } -void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot) +void ahci_port_check_nonbusy(AHCIQState *ahci, AHCICommand *cmd) { + uint8_t slot = cmd->slot; + uint8_t port = cmd->port; uint32_t reg; - /* Assert that the command slot is no longer busy (NCQ) */ + /* For NCQ command with error PxSACT bit should still be set. + * For NCQ command without error, PxSACT bit should be cleared. + * For non-NCQ command, PxSACT bit should always be cleared. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_SACT); - ASSERT_BIT_CLEAR(reg, (1 << slot)); + if (cmd->props->ncq && cmd->errors) { + ASSERT_BIT_SET(reg, (1 << slot)); + } else { + ASSERT_BIT_CLEAR(reg, (1 << slot)); + } - /* Non-NCQ */ + /* For non-NCQ command with error, PxCI bit should still be set. + * For non-NCQ command without error, PxCI bit should be cleared. + * For NCQ command without error, PxCI bit should be cleared. + * For NCQ command with error, PxCI bit may or may not be cleared. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_CI); - ASSERT_BIT_CLEAR(reg, (1 << slot)); + if (!cmd->props->ncq && cmd->errors) { + ASSERT_BIT_SET(reg, (1 << slot)); + } else if (!cmd->errors) { + ASSERT_BIT_CLEAR(reg, (1 << slot)); + } /* And assert that we are generally not busy. */ reg = ahci_px_rreg(ahci, port, AHCI_PX_TFD); @@ -1207,9 +1260,10 @@ void ahci_command_wait(AHCIQState *ahci, AHCICommand *cmd) #define RSET(REG, MASK) (BITSET(ahci_px_rreg(ahci, cmd->port, (REG)), (MASK))) - while (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) || - RSET(AHCI_PX_CI, 1 << cmd->slot) || - (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot))) { + while (!RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_ERR) && + (RSET(AHCI_PX_TFD, AHCI_PX_TFD_STS_BSY) || + RSET(AHCI_PX_CI, 1 << cmd->slot) || + (cmd->props->ncq && RSET(AHCI_PX_SACT, 1 << cmd->slot)))) { usleep(50); } @@ -1226,9 +1280,9 @@ void ahci_command_verify(AHCIQState *ahci, AHCICommand *cmd) uint8_t slot = cmd->slot; uint8_t port = cmd->port; - ahci_port_check_error(ahci, port, cmd->interrupts, cmd->errors); - ahci_port_check_interrupts(ahci, port, cmd->interrupts); - ahci_port_check_nonbusy(ahci, port, slot); + ahci_port_check_nonbusy(ahci, cmd); + ahci_port_check_error(ahci, cmd); + ahci_port_check_interrupts(ahci, cmd); ahci_port_check_cmd_sanity(ahci, cmd); if (cmd->interrupts & AHCI_PX_IS_DHRS) { ahci_port_check_d2h_sanity(ahci, port, slot); diff --git a/tests/qtest/libqos/ahci.h b/tests/qtest/libqos/ahci.h index 88835b6228..48017864bf 100644 --- a/tests/qtest/libqos/ahci.h +++ b/tests/qtest/libqos/ahci.h @@ -590,11 +590,9 @@ void ahci_set_command_header(AHCIQState *ahci, uint8_t port, void ahci_destroy_command(AHCIQState *ahci, uint8_t port, uint8_t slot); /* AHCI sanity check routines */ -void ahci_port_check_error(AHCIQState *ahci, uint8_t port, - uint32_t imask, uint8_t emask); -void ahci_port_check_interrupts(AHCIQState *ahci, uint8_t port, - uint32_t intr_mask); -void ahci_port_check_nonbusy(AHCIQState *ahci, uint8_t port, uint8_t slot); +void ahci_port_check_error(AHCIQState *ahci, AHCICommand *cmd); +void ahci_port_check_interrupts(AHCIQState *ahci, AHCICommand *cmd); +void ahci_port_check_nonbusy(AHCIQState *ahci, AHCICommand *cmd); void ahci_port_check_d2h_sanity(AHCIQState *ahci, uint8_t port, uint8_t slot); void ahci_port_check_pio_sanity(AHCIQState *ahci, AHCICommand *cmd); void ahci_port_check_cmd_sanity(AHCIQState *ahci, AHCICommand *cmd); diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 383bdfeda9..4a9b0267e5 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -155,8 +155,8 @@ qtests_ppc = \ qtests_filter + \ (config_all_devices.has_key('CONFIG_ISA_TESTDEV') ? ['endianness-test'] : []) + \ (config_all_devices.has_key('CONFIG_M48T59') ? ['m48t59-test'] : []) + \ - (config_all_devices.has_key('CONFIG_TCG') ? ['prom-env-test'] : []) + \ - (config_all_devices.has_key('CONFIG_TCG') ? ['boot-serial-test'] : []) + \ + (config_all.has_key('CONFIG_TCG') ? ['prom-env-test'] : []) + \ + (config_all.has_key('CONFIG_TCG') ? ['boot-serial-test'] : []) + \ ['boot-order-test'] qtests_ppc64 = \ diff --git a/tests/qtest/netdev-socket.c b/tests/qtest/netdev-socket.c index 097abc0230..8eed54801f 100644 --- a/tests/qtest/netdev-socket.c +++ b/tests/qtest/netdev-socket.c @@ -82,7 +82,7 @@ static int inet_get_free_port_socket_ipv6(int sock) static int inet_get_free_port_multiple(int nb, int *port, bool ipv6) { - int sock[nb]; + g_autofree int *sock = g_new(int, nb); int i; for (i = 0; i < nb; i++) { diff --git a/tests/qtest/usb-hcd-xhci-test.c b/tests/qtest/usb-hcd-xhci-test.c index 10ef9d2a91..80bc039446 100644 --- a/tests/qtest/usb-hcd-xhci-test.c +++ b/tests/qtest/usb-hcd-xhci-test.c @@ -56,8 +56,12 @@ int main(int argc, char **argv) qtest_add_func("/xhci/pci/init", test_xhci_init); qtest_add_func("/xhci/pci/hotplug", test_xhci_hotplug); - qtest_add_func("/xhci/pci/hotplug/usb-uas", test_usb_uas_hotplug); - qtest_add_func("/xhci/pci/hotplug/usb-ccid", test_usb_ccid_hotplug); + if (qtest_has_device("usb-uas")) { + qtest_add_func("/xhci/pci/hotplug/usb-uas", test_usb_uas_hotplug); + } + if (qtest_has_device("usb-ccid")) { + qtest_add_func("/xhci/pci/hotplug/usb-ccid", test_usb_ccid_hotplug); + } qtest_start("-device nec-usb-xhci,id=xhci" " -drive id=drive0,if=none,file=null-co://," diff --git a/tests/tcg/aarch64/bti-1.c b/tests/tcg/aarch64/bti-1.c index 61924f0d7a..99a879af23 100644 --- a/tests/tcg/aarch64/bti-1.c +++ b/tests/tcg/aarch64/bti-1.c @@ -2,7 +2,7 @@ * Branch target identification, basic notskip cases. */ -#include "bti-crt.inc.c" +#include "bti-crt.c.inc" static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) { diff --git a/tests/tcg/aarch64/bti-3.c b/tests/tcg/aarch64/bti-3.c index a852856d9a..8c534c09d7 100644 --- a/tests/tcg/aarch64/bti-3.c +++ b/tests/tcg/aarch64/bti-3.c @@ -2,7 +2,7 @@ * BTI vs PACIASP */ -#include "bti-crt.inc.c" +#include "bti-crt.c.inc" static void skip2_sigill(int sig, siginfo_t *info, ucontext_t *uc) { diff --git a/tests/tcg/aarch64/bti-crt.inc.c b/tests/tcg/aarch64/bti-crt.c.inc index 47805f4e35..47805f4e35 100644 --- a/tests/tcg/aarch64/bti-crt.inc.c +++ b/tests/tcg/aarch64/bti-crt.c.inc diff --git a/tests/tcg/s390x/Makefile.softmmu-target b/tests/tcg/s390x/Makefile.softmmu-target index 76345b6e64..1a1f088b28 100644 --- a/tests/tcg/s390x/Makefile.softmmu-target +++ b/tests/tcg/s390x/Makefile.softmmu-target @@ -25,6 +25,7 @@ ASM_TESTS = \ lpswe-early \ lra \ mc \ + precise-smc-softmmu \ ssm-early \ stosm-early \ stpq \ diff --git a/tests/tcg/s390x/Makefile.target b/tests/tcg/s390x/Makefile.target index 9c0e70c6ca..c650aefe5c 100644 --- a/tests/tcg/s390x/Makefile.target +++ b/tests/tcg/s390x/Makefile.target @@ -61,6 +61,7 @@ Z13_TESTS+=locfhr Z13_TESTS+=vcksm Z13_TESTS+=vstl Z13_TESTS+=vrep +Z13_TESTS+=precise-smc-user $(Z13_TESTS): CFLAGS+=-march=z13 -O2 TESTS+=$(Z13_TESTS) diff --git a/tests/tcg/s390x/precise-smc-softmmu.S b/tests/tcg/s390x/precise-smc-softmmu.S new file mode 100644 index 0000000000..f7fa57d899 --- /dev/null +++ b/tests/tcg/s390x/precise-smc-softmmu.S @@ -0,0 +1,63 @@ +/* + * Test s390x-softmmu precise self-modifying code handling. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + .org 0x8e +program_interruption_code: + .org 0x150 +program_old_psw: + .org 0x1D0 /* program new PSW */ + .quad 0x180000000,pgm /* 64-bit mode */ + .org 0x200 /* lowcore padding */ + .globl _start +_start: + lctlg %c0,%c0,c0 + lghi %r0,15 + + /* Test 1: replace sgr with agr. */ + lghi %r1,21 + vl %v0,patch1 + jg 1f /* start a new TB */ +0: + .org . + 6 /* pad patched code to 16 bytes */ +1: + vstl %v0,%r0,0b /* start writing before TB */ + sgr %r1,%r1 /* this becomes `agr %r1,%r1` */ + cgijne %r1,42,failure + + /* Test 2: replace agr with division by zero. */ + vl %v0,patch2 + jg 1f /* start a new TB */ +0: + .org . + 6 /* pad patched code to 16 bytes */ +1: + vstl %v0,%r0,0b /* start writing before TB */ + sgr %r1,%r1 /* this becomes `d %r0,zero` */ +failure: + lpswe failure_psw + +pgm: + chhsi program_interruption_code,0x9 /* divide exception? */ + jne failure + clc program_old_psw(16),expected_old_psw2 /* correct old PSW? */ + jne failure + lpswe success_psw + +patch1: + .fill 12 /* replaces padding and stpq */ + agr %r1,%r1 /* replaces sgr */ +patch2: + .fill 12 /* replaces padding and stpq */ + d %r0,zero /* replaces sgr */ +zero: + .long 0 +expected_old_psw2: + .quad 0x200180000000,failure /* cc is from addition */ + .align 8 +c0: + .quad 0x60000 /* AFP, VX */ +success_psw: + .quad 0x2000000000000,0xfff /* see is_special_wait_psw() */ +failure_psw: + .quad 0x2000000000000,0 /* disabled wait */ diff --git a/tests/tcg/s390x/precise-smc-user.c b/tests/tcg/s390x/precise-smc-user.c new file mode 100644 index 0000000000..33a5270865 --- /dev/null +++ b/tests/tcg/s390x/precise-smc-user.c @@ -0,0 +1,39 @@ +/* + * Test s390x-linux-user precise self-modifying code handling. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include <assert.h> +#include <sys/mman.h> +#include <stdint.h> +#include <stdlib.h> + +extern __uint128_t __attribute__((__aligned__(1))) smc; +extern __uint128_t __attribute__((__aligned__(1))) patch; + +int main(void) +{ + char *aligned_smc = (char *)((uintptr_t)&smc & ~0xFFFULL); + char *smc_end = (char *)&smc + sizeof(smc); + uint64_t value = 21; + int err; + + err = mprotect(aligned_smc, smc_end - aligned_smc, + PROT_READ | PROT_WRITE | PROT_EXEC); + assert(err == 0); + + asm("jg 0f\n" /* start a new TB */ + "patch: .byte 0,0,0,0,0,0\n" /* replaces padding */ + ".byte 0,0,0,0,0,0\n" /* replaces vstl */ + "agr %[value],%[value]\n" /* replaces sgr */ + "smc: .org . + 6\n" /* pad patched code to 16 bytes */ + "0: vstl %[patch],%[idx],%[smc]\n" /* start writing before TB */ + "sgr %[value],%[value]" /* this becomes `agr %r0,%r0` */ + : [smc] "=R" (smc) + , [value] "+r" (value) + : [patch] "v" (patch) + , [idx] "r" (sizeof(patch) - 1) + : "cc"); + + return value == 42 ? EXIT_SUCCESS : EXIT_FAILURE; +} diff --git a/ui/cocoa.m b/ui/cocoa.m index 0c2153d17c..4d8989c4eb 100644 --- a/ui/cocoa.m +++ b/ui/cocoa.m @@ -2045,7 +2045,7 @@ static void cocoa_display_init(DisplayState *ds, DisplayOptions *opts) /* * Create the menu entries which depend on QEMU state (for consoles - * and removeable devices). These make calls back into QEMU functions, + * and removable devices). These make calls back into QEMU functions, * which is OK because at this point we know that the second thread * holds the iothread lock and is synchronously waiting for us to * finish. diff --git a/ui/console.c b/ui/console.c index 8da2170a7e..e4d61794bb 100644 --- a/ui/console.c +++ b/ui/console.c @@ -27,9 +27,10 @@ #include "hw/qdev-core.h" #include "qapi/error.h" #include "qapi/qapi-commands-ui.h" +#include "qapi/visitor.h" #include "qemu/coroutine.h" -#include "qemu/error-report.h" #include "qemu/fifo8.h" +#include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/option.h" @@ -37,11 +38,7 @@ #include "chardev/char.h" #include "trace.h" #include "exec/memory.h" -#include "io/channel-file.h" #include "qom/object.h" -#ifdef CONFIG_PNG -#include <png.h> -#endif #define DEFAULT_BACKSCROLL 512 #define CONSOLE_CURSOR_PERIOD 500 @@ -56,6 +53,11 @@ typedef struct TextAttributes { uint8_t unvisible:1; } TextAttributes; +#define TEXT_ATTRIBUTES_DEFAULT ((TextAttributes) { \ + .fgcol = QEMU_COLOR_WHITE, \ + .bgcol = QEMU_COLOR_BLACK \ +}) + typedef struct TextCell { uint8_t ch; TextAttributes t_attrib; @@ -69,17 +71,10 @@ enum TTYState { TTY_STATE_CSI, }; -typedef enum { - GRAPHIC_CONSOLE, - TEXT_CONSOLE, - TEXT_CONSOLE_FIXED_SIZE -} console_type_t; - struct QemuConsole { Object parent; int index; - console_type_t console_type; DisplayState *ds; DisplaySurface *surface; DisplayScanout scanout; @@ -88,28 +83,41 @@ struct QemuConsole { int gl_block; QEMUTimer *gl_unblock_timer; int window_id; + QemuUIInfo ui_info; + QEMUTimer *ui_timer; + const GraphicHwOps *hw_ops; + void *hw; + CoQueue dump_queue; + + QTAILQ_ENTRY(QemuConsole) next; +}; + +OBJECT_DEFINE_ABSTRACT_TYPE(QemuConsole, qemu_console, QEMU_CONSOLE, OBJECT) + +typedef struct QemuGraphicConsole { + QemuConsole parent; - /* Graphic console state. */ Object *device; uint32_t head; - QemuUIInfo ui_info; - QEMUTimer *ui_timer; + QEMUCursor *cursor; int cursor_x, cursor_y, cursor_on; - const GraphicHwOps *hw_ops; - void *hw; +} QemuGraphicConsole; + +typedef QemuConsoleClass QemuGraphicConsoleClass; + +OBJECT_DEFINE_TYPE(QemuGraphicConsole, qemu_graphic_console, QEMU_GRAPHIC_CONSOLE, QEMU_CONSOLE) + +typedef struct QemuTextConsole { + QemuConsole parent; - /* Text console state */ int width; int height; int total_height; int backscroll_height; int x, y; - int x_saved, y_saved; int y_displayed; int y_base; - TextAttributes t_attrib_default; /* default text attributes */ - TextAttributes t_attrib; /* currently active text attributes */ TextCell *cells; int text_x[2], text_y[2], cursor_invalidate; int echo; @@ -119,25 +127,40 @@ struct QemuConsole { int update_x1; int update_y1; - enum TTYState state; - int esc_params[MAX_ESC_PARAMS]; - int nb_esc_params; - Chardev *chr; /* fifo for key pressed */ Fifo8 out_fifo; - CoQueue dump_queue; +} QemuTextConsole; - QTAILQ_ENTRY(QemuConsole) next; +typedef QemuConsoleClass QemuTextConsoleClass; + +OBJECT_DEFINE_TYPE(QemuTextConsole, qemu_text_console, QEMU_TEXT_CONSOLE, QEMU_CONSOLE) + +typedef struct QemuFixedTextConsole { + QemuTextConsole parent; +} QemuFixedTextConsole; + +typedef QemuTextConsoleClass QemuFixedTextConsoleClass; + +OBJECT_DEFINE_TYPE(QemuFixedTextConsole, qemu_fixed_text_console, QEMU_FIXED_TEXT_CONSOLE, QEMU_TEXT_CONSOLE) + +struct VCChardev { + Chardev parent; + QemuTextConsole *console; + + enum TTYState state; + int esc_params[MAX_ESC_PARAMS]; + int nb_esc_params; + TextAttributes t_attrib; /* currently active text attributes */ + int x_saved, y_saved; }; +typedef struct VCChardev VCChardev; struct DisplayState { QEMUTimer *gui_timer; uint64_t last_update; uint64_t update_interval; bool refreshing; - bool have_gfx; - bool have_text; QLIST_HEAD(, DisplayChangeListener) listeners; }; @@ -149,14 +172,14 @@ static QTAILQ_HEAD(, QemuConsole) consoles = static bool cursor_visible_phase; static QEMUTimer *cursor_timer; -static void text_console_do_init(Chardev *chr, DisplayState *ds); static void dpy_refresh(DisplayState *s); static DisplayState *get_alloc_displaystate(void); -static void text_console_update_cursor_timer(void); static void text_console_update_cursor(void *opaque); static bool displaychangelistener_has_dmabuf(DisplayChangeListener *dcl); static bool console_compatible_with(QemuConsole *con, DisplayChangeListener *dcl, Error **errp); +static QemuConsole *qemu_graphic_console_lookup_unused(void); +static void dpy_set_ui_info_timer(void *opaque); static void gui_update(void *opaque) { @@ -188,19 +211,11 @@ static void gui_setup_refresh(DisplayState *ds) { DisplayChangeListener *dcl; bool need_timer = false; - bool have_gfx = false; - bool have_text = false; QLIST_FOREACH(dcl, &ds->listeners, next) { if (dcl->ops->dpy_refresh != NULL) { need_timer = true; } - if (dcl->ops->dpy_gfx_update != NULL) { - have_gfx = true; - } - if (dcl->ops->dpy_text_update != NULL) { - have_text = true; - } } if (need_timer && ds->gui_timer == NULL) { @@ -211,9 +226,6 @@ static void gui_setup_refresh(DisplayState *ds) timer_free(ds->gui_timer); ds->gui_timer = NULL; } - - ds->have_gfx = have_gfx; - ds->have_text = have_text; } void graphic_hw_update_done(QemuConsole *con) @@ -239,6 +251,22 @@ void graphic_hw_update(QemuConsole *con) } } +static void graphic_hw_update_bh(void *con) +{ + graphic_hw_update(con); +} + +void qemu_console_co_wait_update(QemuConsole *con) +{ + if (qemu_co_queue_empty(&con->dump_queue)) { + /* Defer the update, it will restart the pending coroutines */ + aio_bh_schedule_oneshot(qemu_get_aio_context(), + graphic_hw_update_bh, con); + } + qemu_co_queue_wait(&con->dump_queue, NULL); + +} + static void graphic_hw_gl_unblock_timer(void *opaque) { warn_report("console: no gl-unblock within one second"); @@ -292,196 +320,6 @@ void graphic_hw_invalidate(QemuConsole *con) } } -#ifdef CONFIG_PNG -/** - * png_save: Take a screenshot as PNG - * - * Saves screendump as a PNG file - * - * Returns true for success or false for error. - * - * @fd: File descriptor for PNG file. - * @image: Image data in pixman format. - * @errp: Pointer to an error. - */ -static bool png_save(int fd, pixman_image_t *image, Error **errp) -{ - int width = pixman_image_get_width(image); - int height = pixman_image_get_height(image); - png_struct *png_ptr; - png_info *info_ptr; - g_autoptr(pixman_image_t) linebuf = - qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); - uint8_t *buf = (uint8_t *)pixman_image_get_data(linebuf); - FILE *f = fdopen(fd, "wb"); - int y; - if (!f) { - error_setg_errno(errp, errno, - "Failed to create file from file descriptor"); - return false; - } - - png_ptr = png_create_write_struct(PNG_LIBPNG_VER_STRING, NULL, - NULL, NULL); - if (!png_ptr) { - error_setg(errp, "PNG creation failed. Unable to write struct"); - fclose(f); - return false; - } - - info_ptr = png_create_info_struct(png_ptr); - - if (!info_ptr) { - error_setg(errp, "PNG creation failed. Unable to write info"); - fclose(f); - png_destroy_write_struct(&png_ptr, &info_ptr); - return false; - } - - png_init_io(png_ptr, f); - - png_set_IHDR(png_ptr, info_ptr, width, height, 8, - PNG_COLOR_TYPE_RGB, PNG_INTERLACE_NONE, - PNG_COMPRESSION_TYPE_BASE, PNG_FILTER_TYPE_BASE); - - png_write_info(png_ptr, info_ptr); - - for (y = 0; y < height; ++y) { - qemu_pixman_linebuf_fill(linebuf, image, width, 0, y); - png_write_row(png_ptr, buf); - } - - png_write_end(png_ptr, NULL); - - png_destroy_write_struct(&png_ptr, &info_ptr); - - if (fclose(f) != 0) { - error_setg_errno(errp, errno, - "PNG creation failed. Unable to close file"); - return false; - } - - return true; -} - -#else /* no png support */ - -static bool png_save(int fd, pixman_image_t *image, Error **errp) -{ - error_setg(errp, "Enable PNG support with libpng for screendump"); - return false; -} - -#endif /* CONFIG_PNG */ - -static bool ppm_save(int fd, pixman_image_t *image, Error **errp) -{ - int width = pixman_image_get_width(image); - int height = pixman_image_get_height(image); - g_autoptr(Object) ioc = OBJECT(qio_channel_file_new_fd(fd)); - g_autofree char *header = NULL; - g_autoptr(pixman_image_t) linebuf = NULL; - int y; - - trace_ppm_save(fd, image); - - header = g_strdup_printf("P6\n%d %d\n%d\n", width, height, 255); - if (qio_channel_write_all(QIO_CHANNEL(ioc), - header, strlen(header), errp) < 0) { - return false; - } - - linebuf = qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); - for (y = 0; y < height; y++) { - qemu_pixman_linebuf_fill(linebuf, image, width, 0, y); - if (qio_channel_write_all(QIO_CHANNEL(ioc), - (char *)pixman_image_get_data(linebuf), - pixman_image_get_stride(linebuf), errp) < 0) { - return false; - } - } - - return true; -} - -static void graphic_hw_update_bh(void *con) -{ - graphic_hw_update(con); -} - -/* Safety: coroutine-only, concurrent-coroutine safe, main thread only */ -void coroutine_fn -qmp_screendump(const char *filename, const char *device, - bool has_head, int64_t head, - bool has_format, ImageFormat format, Error **errp) -{ - g_autoptr(pixman_image_t) image = NULL; - QemuConsole *con; - DisplaySurface *surface; - int fd; - - if (device) { - con = qemu_console_lookup_by_device_name(device, has_head ? head : 0, - errp); - if (!con) { - return; - } - } else { - if (has_head) { - error_setg(errp, "'head' must be specified together with 'device'"); - return; - } - con = qemu_console_lookup_by_index(0); - if (!con) { - error_setg(errp, "There is no console to take a screendump from"); - return; - } - } - - if (qemu_co_queue_empty(&con->dump_queue)) { - /* Defer the update, it will restart the pending coroutines */ - aio_bh_schedule_oneshot(qemu_get_aio_context(), - graphic_hw_update_bh, con); - } - qemu_co_queue_wait(&con->dump_queue, NULL); - - /* - * All pending coroutines are woken up, while the BQL is held. No - * further graphic update are possible until it is released. Take - * an image ref before that. - */ - surface = qemu_console_surface(con); - if (!surface) { - error_setg(errp, "no surface"); - return; - } - image = pixman_image_ref(surface->image); - - fd = qemu_open_old(filename, O_WRONLY | O_CREAT | O_TRUNC | O_BINARY, 0666); - if (fd == -1) { - error_setg(errp, "failed to open file '%s': %s", filename, - strerror(errno)); - return; - } - - /* - * The image content could potentially be updated as the coroutine - * yields and releases the BQL. It could produce corrupted dump, but - * it should be otherwise safe. - */ - if (has_format && format == IMAGE_FORMAT_PNG) { - /* PNG format specified for screendump */ - if (!png_save(fd, image, errp)) { - qemu_unlink(filename); - } - } else { - /* PPM format specified/default for screendump */ - if (!ppm_save(fd, image, errp)) { - qemu_unlink(filename); - } - } -} - void graphic_hw_text_update(QemuConsole *con, console_ch_t *chardata) { if (!con) { @@ -492,25 +330,26 @@ void graphic_hw_text_update(QemuConsole *con, console_ch_t *chardata) } } -static void vga_fill_rect(QemuConsole *con, - int posx, int posy, int width, int height, - pixman_color_t color) +static void qemu_console_fill_rect(QemuConsole *con, int posx, int posy, + int width, int height, pixman_color_t color) { DisplaySurface *surface = qemu_console_surface(con); pixman_rectangle16_t rect = { .x = posx, .y = posy, .width = width, .height = height }; + assert(surface); pixman_image_fill_rectangles(PIXMAN_OP_SRC, surface->image, &color, 1, &rect); } /* copy from (xs, ys) to (xd, yd) a rectangle of size (w, h) */ -static void vga_bitblt(QemuConsole *con, - int xs, int ys, int xd, int yd, int w, int h) +static void qemu_console_bitblt(QemuConsole *con, + int xs, int ys, int xd, int yd, int w, int h) { DisplaySurface *surface = qemu_console_surface(con); + assert(surface); pixman_image_composite(PIXMAN_OP_SRC, surface->image, NULL, surface->image, xs, ys, 0, 0, xd, yd, w, h); @@ -524,29 +363,26 @@ static void vga_bitblt(QemuConsole *con, #include "vgafont.h" -#define QEMU_RGB(r, g, b) \ - { .red = r << 8, .green = g << 8, .blue = b << 8, .alpha = 0xffff } - static const pixman_color_t color_table_rgb[2][8] = { { /* dark */ - [QEMU_COLOR_BLACK] = QEMU_RGB(0x00, 0x00, 0x00), /* black */ - [QEMU_COLOR_BLUE] = QEMU_RGB(0x00, 0x00, 0xaa), /* blue */ - [QEMU_COLOR_GREEN] = QEMU_RGB(0x00, 0xaa, 0x00), /* green */ - [QEMU_COLOR_CYAN] = QEMU_RGB(0x00, 0xaa, 0xaa), /* cyan */ - [QEMU_COLOR_RED] = QEMU_RGB(0xaa, 0x00, 0x00), /* red */ - [QEMU_COLOR_MAGENTA] = QEMU_RGB(0xaa, 0x00, 0xaa), /* magenta */ - [QEMU_COLOR_YELLOW] = QEMU_RGB(0xaa, 0xaa, 0x00), /* yellow */ - [QEMU_COLOR_WHITE] = QEMU_RGB(0xaa, 0xaa, 0xaa), /* white */ + [QEMU_COLOR_BLACK] = QEMU_PIXMAN_COLOR_BLACK, + [QEMU_COLOR_BLUE] = QEMU_PIXMAN_COLOR(0x00, 0x00, 0xaa), /* blue */ + [QEMU_COLOR_GREEN] = QEMU_PIXMAN_COLOR(0x00, 0xaa, 0x00), /* green */ + [QEMU_COLOR_CYAN] = QEMU_PIXMAN_COLOR(0x00, 0xaa, 0xaa), /* cyan */ + [QEMU_COLOR_RED] = QEMU_PIXMAN_COLOR(0xaa, 0x00, 0x00), /* red */ + [QEMU_COLOR_MAGENTA] = QEMU_PIXMAN_COLOR(0xaa, 0x00, 0xaa), /* magenta */ + [QEMU_COLOR_YELLOW] = QEMU_PIXMAN_COLOR(0xaa, 0xaa, 0x00), /* yellow */ + [QEMU_COLOR_WHITE] = QEMU_PIXMAN_COLOR_GRAY, }, { /* bright */ - [QEMU_COLOR_BLACK] = QEMU_RGB(0x00, 0x00, 0x00), /* black */ - [QEMU_COLOR_BLUE] = QEMU_RGB(0x00, 0x00, 0xff), /* blue */ - [QEMU_COLOR_GREEN] = QEMU_RGB(0x00, 0xff, 0x00), /* green */ - [QEMU_COLOR_CYAN] = QEMU_RGB(0x00, 0xff, 0xff), /* cyan */ - [QEMU_COLOR_RED] = QEMU_RGB(0xff, 0x00, 0x00), /* red */ - [QEMU_COLOR_MAGENTA] = QEMU_RGB(0xff, 0x00, 0xff), /* magenta */ - [QEMU_COLOR_YELLOW] = QEMU_RGB(0xff, 0xff, 0x00), /* yellow */ - [QEMU_COLOR_WHITE] = QEMU_RGB(0xff, 0xff, 0xff), /* white */ + [QEMU_COLOR_BLACK] = QEMU_PIXMAN_COLOR_BLACK, + [QEMU_COLOR_BLUE] = QEMU_PIXMAN_COLOR(0x00, 0x00, 0xff), /* blue */ + [QEMU_COLOR_GREEN] = QEMU_PIXMAN_COLOR(0x00, 0xff, 0x00), /* green */ + [QEMU_COLOR_CYAN] = QEMU_PIXMAN_COLOR(0x00, 0xff, 0xff), /* cyan */ + [QEMU_COLOR_RED] = QEMU_PIXMAN_COLOR(0xff, 0x00, 0x00), /* red */ + [QEMU_COLOR_MAGENTA] = QEMU_PIXMAN_COLOR(0xff, 0x00, 0xff), /* magenta */ + [QEMU_COLOR_YELLOW] = QEMU_PIXMAN_COLOR(0xff, 0xff, 0x00), /* yellow */ + [QEMU_COLOR_WHITE] = QEMU_PIXMAN_COLOR(0xff, 0xff, 0xff), /* white */ } }; @@ -557,6 +393,7 @@ static void vga_putcharxy(QemuConsole *s, int x, int y, int ch, DisplaySurface *surface = qemu_console_surface(s); pixman_color_t fgcol, bgcol; + assert(surface); if (t_attrib->invers) { bgcol = color_table_rgb[t_attrib->bold][t_attrib->fgcol]; fgcol = color_table_rgb[t_attrib->bold][t_attrib->bgcol]; @@ -572,51 +409,48 @@ static void vga_putcharxy(QemuConsole *s, int x, int y, int ch, &fgcol, &bgcol, x, y, FONT_WIDTH, FONT_HEIGHT); } -static void text_console_resize(QemuConsole *s) +static void text_console_resize(QemuTextConsole *t) { + QemuConsole *s = QEMU_CONSOLE(t); TextCell *cells, *c, *c1; - int w1, x, y, last_width; + int w1, x, y, last_width, w, h; assert(s->scanout.kind == SCANOUT_SURFACE); - last_width = s->width; - s->width = surface_width(s->surface) / FONT_WIDTH; - s->height = surface_height(s->surface) / FONT_HEIGHT; + w = surface_width(s->surface) / FONT_WIDTH; + h = surface_height(s->surface) / FONT_HEIGHT; + if (w == t->width && h == t->height) { + return; + } + + last_width = t->width; + t->width = w; + t->height = h; - w1 = last_width; - if (s->width < w1) - w1 = s->width; + w1 = MIN(t->width, last_width); - cells = g_new(TextCell, s->width * s->total_height + 1); - for(y = 0; y < s->total_height; y++) { - c = &cells[y * s->width]; + cells = g_new(TextCell, t->width * t->total_height + 1); + for (y = 0; y < t->total_height; y++) { + c = &cells[y * t->width]; if (w1 > 0) { - c1 = &s->cells[y * last_width]; - for(x = 0; x < w1; x++) { + c1 = &t->cells[y * last_width]; + for (x = 0; x < w1; x++) { *c++ = *c1++; } } - for(x = w1; x < s->width; x++) { + for (x = w1; x < t->width; x++) { c->ch = ' '; - c->t_attrib = s->t_attrib_default; + c->t_attrib = TEXT_ATTRIBUTES_DEFAULT; c++; } } - g_free(s->cells); - s->cells = cells; -} - -static inline void text_update_xy(QemuConsole *s, int x, int y) -{ - s->text_x[0] = MIN(s->text_x[0], x); - s->text_x[1] = MAX(s->text_x[1], x); - s->text_y[0] = MIN(s->text_y[0], y); - s->text_y[1] = MAX(s->text_y[1], y); + g_free(t->cells); + t->cells = cells; } -static void invalidate_xy(QemuConsole *s, int x, int y) +static void invalidate_xy(QemuTextConsole *s, int x, int y) { - if (!qemu_console_is_visible(s)) { + if (!qemu_console_is_visible(QEMU_CONSOLE(s))) { return; } if (s->update_x0 > x * FONT_WIDTH) @@ -629,14 +463,16 @@ static void invalidate_xy(QemuConsole *s, int x, int y) s->update_y1 = (y + 1) * FONT_HEIGHT; } -static void update_xy(QemuConsole *s, int x, int y) +static void vc_update_xy(VCChardev *vc, int x, int y) { + QemuTextConsole *s = vc->console; TextCell *c; int y1, y2; - if (s->ds->have_text) { - text_update_xy(s, x, y); - } + s->text_x[0] = MIN(s->text_x[0], x); + s->text_x[1] = MAX(s->text_x[1], x); + s->text_y[0] = MIN(s->text_y[0], y); + s->text_y[1] = MAX(s->text_y[1], y); y1 = (s->y_base + y) % s->total_height; y2 = y1 - s->y_displayed; @@ -648,21 +484,19 @@ static void update_xy(QemuConsole *s, int x, int y) x = s->width - 1; } c = &s->cells[y1 * s->width + x]; - vga_putcharxy(s, x, y2, c->ch, + vga_putcharxy(QEMU_CONSOLE(s), x, y2, c->ch, &(c->t_attrib)); invalidate_xy(s, x, y2); } } -static void console_show_cursor(QemuConsole *s, int show) +static void console_show_cursor(QemuTextConsole *s, int show) { TextCell *c; int y, y1; int x = s->x; - if (s->ds->have_text) { - s->cursor_invalidate = 1; - } + s->cursor_invalidate = 1; if (x >= s->width) { x = s->width - 1; @@ -675,37 +509,36 @@ static void console_show_cursor(QemuConsole *s, int show) if (y < s->height) { c = &s->cells[y1 * s->width + x]; if (show && cursor_visible_phase) { - TextAttributes t_attrib = s->t_attrib_default; + TextAttributes t_attrib = TEXT_ATTRIBUTES_DEFAULT; t_attrib.invers = !(t_attrib.invers); /* invert fg and bg */ - vga_putcharxy(s, x, y, c->ch, &t_attrib); + vga_putcharxy(QEMU_CONSOLE(s), x, y, c->ch, &t_attrib); } else { - vga_putcharxy(s, x, y, c->ch, &(c->t_attrib)); + vga_putcharxy(QEMU_CONSOLE(s), x, y, c->ch, &(c->t_attrib)); } invalidate_xy(s, x, y); } } -static void console_refresh(QemuConsole *s) +static void console_refresh(QemuTextConsole *s) { - DisplaySurface *surface = qemu_console_surface(s); + DisplaySurface *surface = qemu_console_surface(QEMU_CONSOLE(s)); TextCell *c; int x, y, y1; - if (s->ds->have_text) { - s->text_x[0] = 0; - s->text_y[0] = 0; - s->text_x[1] = s->width - 1; - s->text_y[1] = s->height - 1; - s->cursor_invalidate = 1; - } + assert(surface); + s->text_x[0] = 0; + s->text_y[0] = 0; + s->text_x[1] = s->width - 1; + s->text_y[1] = s->height - 1; + s->cursor_invalidate = 1; - vga_fill_rect(s, 0, 0, surface_width(surface), surface_height(surface), - color_table_rgb[0][QEMU_COLOR_BLACK]); + qemu_console_fill_rect(QEMU_CONSOLE(s), 0, 0, surface_width(surface), surface_height(surface), + color_table_rgb[0][QEMU_COLOR_BLACK]); y1 = s->y_displayed; for (y = 0; y < s->height; y++) { c = s->cells + y1 * s->width; for (x = 0; x < s->width; x++) { - vga_putcharxy(s, x, y, c->ch, + vga_putcharxy(QEMU_CONSOLE(s), x, y, c->ch, &(c->t_attrib)); c++; } @@ -714,11 +547,11 @@ static void console_refresh(QemuConsole *s) } } console_show_cursor(s, 1); - dpy_gfx_update(s, 0, 0, + dpy_gfx_update(QEMU_CONSOLE(s), 0, 0, surface_width(surface), surface_height(surface)); } -static void console_scroll(QemuConsole *s, int ydelta) +static void console_scroll(QemuTextConsole *s, int ydelta) { int i, y1; @@ -747,8 +580,9 @@ static void console_scroll(QemuConsole *s, int ydelta) console_refresh(s); } -static void console_put_lf(QemuConsole *s) +static void vc_put_lf(VCChardev *vc) { + QemuTextConsole *s = vc->console; TextCell *c; int x, y1; @@ -768,23 +602,21 @@ static void console_put_lf(QemuConsole *s) c = &s->cells[y1 * s->width]; for(x = 0; x < s->width; x++) { c->ch = ' '; - c->t_attrib = s->t_attrib_default; + c->t_attrib = TEXT_ATTRIBUTES_DEFAULT; c++; } if (s->y_displayed == s->y_base) { - if (s->ds->have_text) { - s->text_x[0] = 0; - s->text_y[0] = 0; - s->text_x[1] = s->width - 1; - s->text_y[1] = s->height - 1; - } - - vga_bitblt(s, 0, FONT_HEIGHT, 0, 0, - s->width * FONT_WIDTH, - (s->height - 1) * FONT_HEIGHT); - vga_fill_rect(s, 0, (s->height - 1) * FONT_HEIGHT, - s->width * FONT_WIDTH, FONT_HEIGHT, - color_table_rgb[0][s->t_attrib_default.bgcol]); + s->text_x[0] = 0; + s->text_y[0] = 0; + s->text_x[1] = s->width - 1; + s->text_y[1] = s->height - 1; + + qemu_console_bitblt(QEMU_CONSOLE(s), 0, FONT_HEIGHT, 0, 0, + s->width * FONT_WIDTH, + (s->height - 1) * FONT_HEIGHT); + qemu_console_fill_rect(QEMU_CONSOLE(s), 0, (s->height - 1) * FONT_HEIGHT, + s->width * FONT_WIDTH, FONT_HEIGHT, + color_table_rgb[0][TEXT_ATTRIBUTES_DEFAULT.bgcol]); s->update_x0 = 0; s->update_y0 = 0; s->update_x1 = s->width * FONT_WIDTH; @@ -797,139 +629,143 @@ static void console_put_lf(QemuConsole *s) * NOTE: I know this code is not very efficient (checking every color for it * self) but it is more readable and better maintainable. */ -static void console_handle_escape(QemuConsole *s) +static void vc_handle_escape(VCChardev *vc) { int i; - for (i=0; i<s->nb_esc_params; i++) { - switch (s->esc_params[i]) { + for (i = 0; i < vc->nb_esc_params; i++) { + switch (vc->esc_params[i]) { case 0: /* reset all console attributes to default */ - s->t_attrib = s->t_attrib_default; + vc->t_attrib = TEXT_ATTRIBUTES_DEFAULT; break; case 1: - s->t_attrib.bold = 1; + vc->t_attrib.bold = 1; break; case 4: - s->t_attrib.uline = 1; + vc->t_attrib.uline = 1; break; case 5: - s->t_attrib.blink = 1; + vc->t_attrib.blink = 1; break; case 7: - s->t_attrib.invers = 1; + vc->t_attrib.invers = 1; break; case 8: - s->t_attrib.unvisible = 1; + vc->t_attrib.unvisible = 1; break; case 22: - s->t_attrib.bold = 0; + vc->t_attrib.bold = 0; break; case 24: - s->t_attrib.uline = 0; + vc->t_attrib.uline = 0; break; case 25: - s->t_attrib.blink = 0; + vc->t_attrib.blink = 0; break; case 27: - s->t_attrib.invers = 0; + vc->t_attrib.invers = 0; break; case 28: - s->t_attrib.unvisible = 0; + vc->t_attrib.unvisible = 0; break; /* set foreground color */ case 30: - s->t_attrib.fgcol = QEMU_COLOR_BLACK; + vc->t_attrib.fgcol = QEMU_COLOR_BLACK; break; case 31: - s->t_attrib.fgcol = QEMU_COLOR_RED; + vc->t_attrib.fgcol = QEMU_COLOR_RED; break; case 32: - s->t_attrib.fgcol = QEMU_COLOR_GREEN; + vc->t_attrib.fgcol = QEMU_COLOR_GREEN; break; case 33: - s->t_attrib.fgcol = QEMU_COLOR_YELLOW; + vc->t_attrib.fgcol = QEMU_COLOR_YELLOW; break; case 34: - s->t_attrib.fgcol = QEMU_COLOR_BLUE; + vc->t_attrib.fgcol = QEMU_COLOR_BLUE; break; case 35: - s->t_attrib.fgcol = QEMU_COLOR_MAGENTA; + vc->t_attrib.fgcol = QEMU_COLOR_MAGENTA; break; case 36: - s->t_attrib.fgcol = QEMU_COLOR_CYAN; + vc->t_attrib.fgcol = QEMU_COLOR_CYAN; break; case 37: - s->t_attrib.fgcol = QEMU_COLOR_WHITE; + vc->t_attrib.fgcol = QEMU_COLOR_WHITE; break; /* set background color */ case 40: - s->t_attrib.bgcol = QEMU_COLOR_BLACK; + vc->t_attrib.bgcol = QEMU_COLOR_BLACK; break; case 41: - s->t_attrib.bgcol = QEMU_COLOR_RED; + vc->t_attrib.bgcol = QEMU_COLOR_RED; break; case 42: - s->t_attrib.bgcol = QEMU_COLOR_GREEN; + vc->t_attrib.bgcol = QEMU_COLOR_GREEN; break; case 43: - s->t_attrib.bgcol = QEMU_COLOR_YELLOW; + vc->t_attrib.bgcol = QEMU_COLOR_YELLOW; break; case 44: - s->t_attrib.bgcol = QEMU_COLOR_BLUE; + vc->t_attrib.bgcol = QEMU_COLOR_BLUE; break; case 45: - s->t_attrib.bgcol = QEMU_COLOR_MAGENTA; + vc->t_attrib.bgcol = QEMU_COLOR_MAGENTA; break; case 46: - s->t_attrib.bgcol = QEMU_COLOR_CYAN; + vc->t_attrib.bgcol = QEMU_COLOR_CYAN; break; case 47: - s->t_attrib.bgcol = QEMU_COLOR_WHITE; + vc->t_attrib.bgcol = QEMU_COLOR_WHITE; break; } } } -static void console_clear_xy(QemuConsole *s, int x, int y) +static void vc_clear_xy(VCChardev *vc, int x, int y) { + QemuTextConsole *s = vc->console; int y1 = (s->y_base + y) % s->total_height; if (x >= s->width) { x = s->width - 1; } TextCell *c = &s->cells[y1 * s->width + x]; c->ch = ' '; - c->t_attrib = s->t_attrib_default; - update_xy(s, x, y); + c->t_attrib = TEXT_ATTRIBUTES_DEFAULT; + vc_update_xy(vc, x, y); } -static void console_put_one(QemuConsole *s, int ch) +static void vc_put_one(VCChardev *vc, int ch) { + QemuTextConsole *s = vc->console; TextCell *c; int y1; if (s->x >= s->width) { /* line wrap */ s->x = 0; - console_put_lf(s); + vc_put_lf(vc); } y1 = (s->y_base + s->y) % s->total_height; c = &s->cells[y1 * s->width + s->x]; c->ch = ch; - c->t_attrib = s->t_attrib; - update_xy(s, s->x, s->y); + c->t_attrib = vc->t_attrib; + vc_update_xy(vc, s->x, s->y); s->x++; } -static void console_respond_str(QemuConsole *s, const char *buf) +static void vc_respond_str(VCChardev *vc, const char *buf) { while (*buf) { - console_put_one(s, *buf); + vc_put_one(vc, *buf); buf++; } } /* set cursor, checking bounds */ -static void set_cursor(QemuConsole *s, int x, int y) +static void vc_set_cursor(VCChardev *vc, int x, int y) { + QemuTextConsole *s = vc->console; + if (x < 0) { x = 0; } @@ -947,20 +783,21 @@ static void set_cursor(QemuConsole *s, int x, int y) s->y = y; } -static void console_putchar(QemuConsole *s, int ch) +static void vc_putchar(VCChardev *vc, int ch) { + QemuTextConsole *s = vc->console; int i; int x, y; char response[40]; - switch(s->state) { + switch(vc->state) { case TTY_STATE_NORM: switch(ch) { case '\r': /* carriage return */ s->x = 0; break; case '\n': /* newline */ - console_put_lf(s); + vc_put_lf(vc); break; case '\b': /* backspace */ if (s->x > 0) @@ -969,7 +806,7 @@ static void console_putchar(QemuConsole *s, int ch) case '\t': /* tabspace */ if (s->x + (8 - (s->x % 8)) > s->width) { s->x = 0; - console_put_lf(s); + vc_put_lf(vc); } else { s->x = s->x + (8 - (s->x % 8)); } @@ -984,81 +821,81 @@ static void console_putchar(QemuConsole *s, int ch) /* SO (shift out), character set 1 (ignored) */ break; case 27: /* esc (introducing an escape sequence) */ - s->state = TTY_STATE_ESC; + vc->state = TTY_STATE_ESC; break; default: - console_put_one(s, ch); + vc_put_one(vc, ch); break; } break; case TTY_STATE_ESC: /* check if it is a terminal escape sequence */ if (ch == '[') { for(i=0;i<MAX_ESC_PARAMS;i++) - s->esc_params[i] = 0; - s->nb_esc_params = 0; - s->state = TTY_STATE_CSI; + vc->esc_params[i] = 0; + vc->nb_esc_params = 0; + vc->state = TTY_STATE_CSI; } else { - s->state = TTY_STATE_NORM; + vc->state = TTY_STATE_NORM; } break; case TTY_STATE_CSI: /* handle escape sequence parameters */ if (ch >= '0' && ch <= '9') { - if (s->nb_esc_params < MAX_ESC_PARAMS) { - int *param = &s->esc_params[s->nb_esc_params]; + if (vc->nb_esc_params < MAX_ESC_PARAMS) { + int *param = &vc->esc_params[vc->nb_esc_params]; int digit = (ch - '0'); *param = (*param <= (INT_MAX - digit) / 10) ? *param * 10 + digit : INT_MAX; } } else { - if (s->nb_esc_params < MAX_ESC_PARAMS) - s->nb_esc_params++; + if (vc->nb_esc_params < MAX_ESC_PARAMS) + vc->nb_esc_params++; if (ch == ';' || ch == '?') { break; } - trace_console_putchar_csi(s->esc_params[0], s->esc_params[1], - ch, s->nb_esc_params); - s->state = TTY_STATE_NORM; + trace_console_putchar_csi(vc->esc_params[0], vc->esc_params[1], + ch, vc->nb_esc_params); + vc->state = TTY_STATE_NORM; switch(ch) { case 'A': /* move cursor up */ - if (s->esc_params[0] == 0) { - s->esc_params[0] = 1; + if (vc->esc_params[0] == 0) { + vc->esc_params[0] = 1; } - set_cursor(s, s->x, s->y - s->esc_params[0]); + vc_set_cursor(vc, s->x, s->y - vc->esc_params[0]); break; case 'B': /* move cursor down */ - if (s->esc_params[0] == 0) { - s->esc_params[0] = 1; + if (vc->esc_params[0] == 0) { + vc->esc_params[0] = 1; } - set_cursor(s, s->x, s->y + s->esc_params[0]); + vc_set_cursor(vc, s->x, s->y + vc->esc_params[0]); break; case 'C': /* move cursor right */ - if (s->esc_params[0] == 0) { - s->esc_params[0] = 1; + if (vc->esc_params[0] == 0) { + vc->esc_params[0] = 1; } - set_cursor(s, s->x + s->esc_params[0], s->y); + vc_set_cursor(vc, s->x + vc->esc_params[0], s->y); break; case 'D': /* move cursor left */ - if (s->esc_params[0] == 0) { - s->esc_params[0] = 1; + if (vc->esc_params[0] == 0) { + vc->esc_params[0] = 1; } - set_cursor(s, s->x - s->esc_params[0], s->y); + vc_set_cursor(vc, s->x - vc->esc_params[0], s->y); break; case 'G': /* move cursor to column */ - set_cursor(s, s->esc_params[0] - 1, s->y); + vc_set_cursor(vc, vc->esc_params[0] - 1, s->y); break; case 'f': case 'H': /* move cursor to row, column */ - set_cursor(s, s->esc_params[1] - 1, s->esc_params[0] - 1); + vc_set_cursor(vc, vc->esc_params[1] - 1, vc->esc_params[0] - 1); break; case 'J': - switch (s->esc_params[0]) { + switch (vc->esc_params[0]) { case 0: /* clear to end of screen */ for (y = s->y; y < s->height; y++) { @@ -1066,7 +903,7 @@ static void console_putchar(QemuConsole *s, int ch) if (y == s->y && x < s->x) { continue; } - console_clear_xy(s, x, y); + vc_clear_xy(vc, x, y); } } break; @@ -1077,7 +914,7 @@ static void console_putchar(QemuConsole *s, int ch) if (y == s->y && x > s->x) { break; } - console_clear_xy(s, x, y); + vc_clear_xy(vc, x, y); } } break; @@ -1085,61 +922,61 @@ static void console_putchar(QemuConsole *s, int ch) /* clear entire screen */ for (y = 0; y <= s->height; y++) { for (x = 0; x < s->width; x++) { - console_clear_xy(s, x, y); + vc_clear_xy(vc, x, y); } } break; } break; case 'K': - switch (s->esc_params[0]) { + switch (vc->esc_params[0]) { case 0: /* clear to eol */ for(x = s->x; x < s->width; x++) { - console_clear_xy(s, x, s->y); + vc_clear_xy(vc, x, s->y); } break; case 1: /* clear from beginning of line */ for (x = 0; x <= s->x && x < s->width; x++) { - console_clear_xy(s, x, s->y); + vc_clear_xy(vc, x, s->y); } break; case 2: /* clear entire line */ for(x = 0; x < s->width; x++) { - console_clear_xy(s, x, s->y); + vc_clear_xy(vc, x, s->y); } break; } break; case 'm': - console_handle_escape(s); + vc_handle_escape(vc); break; case 'n': - switch (s->esc_params[0]) { + switch (vc->esc_params[0]) { case 5: /* report console status (always succeed)*/ - console_respond_str(s, "\033[0n"); + vc_respond_str(vc, "\033[0n"); break; case 6: /* report cursor position */ sprintf(response, "\033[%d;%dR", (s->y_base + s->y) % s->total_height + 1, s->x + 1); - console_respond_str(s, response); + vc_respond_str(vc, response); break; } break; case 's': /* save cursor position */ - s->x_saved = s->x; - s->y_saved = s->y; + vc->x_saved = s->x; + vc->y_saved = s->y; break; case 'u': /* restore cursor position */ - s->x = s->x_saved; - s->y = s->y_saved; + s->x = vc->x_saved; + s->y = vc->y_saved; break; default: trace_console_putchar_unhandled(ch); @@ -1239,27 +1076,20 @@ void console_select(unsigned int index) DisplayState *ds = s->ds; active_console = s; - if (ds->have_gfx) { - QLIST_FOREACH(dcl, &ds->listeners, next) { - if (dcl->con != NULL) { - continue; - } - displaychangelistener_display_console(dcl, s, NULL); + QLIST_FOREACH (dcl, &ds->listeners, next) { + if (dcl->con != NULL) { + continue; } + displaychangelistener_display_console(dcl, s, NULL); } - if (ds->have_text) { - dpy_text_resize(s, s->width, s->height); + + if (QEMU_IS_TEXT_CONSOLE(s)) { + dpy_text_resize(s, QEMU_TEXT_CONSOLE(s)->width, QEMU_TEXT_CONSOLE(s)->height); + text_console_update_cursor(NULL); } - text_console_update_cursor(NULL); } } -struct VCChardev { - Chardev parent; - QemuConsole *console; -}; -typedef struct VCChardev VCChardev; - #define TYPE_CHARDEV_VC "chardev-vc" DECLARE_INSTANCE_CHECKER(VCChardev, VC_CHARDEV, TYPE_CHARDEV_VC) @@ -1267,31 +1097,27 @@ DECLARE_INSTANCE_CHECKER(VCChardev, VC_CHARDEV, static int vc_chr_write(Chardev *chr, const uint8_t *buf, int len) { VCChardev *drv = VC_CHARDEV(chr); - QemuConsole *s = drv->console; + QemuTextConsole *s = drv->console; int i; - if (!s->ds) { - return 0; - } - s->update_x0 = s->width * FONT_WIDTH; s->update_y0 = s->height * FONT_HEIGHT; s->update_x1 = 0; s->update_y1 = 0; console_show_cursor(s, 0); for(i = 0; i < len; i++) { - console_putchar(s, buf[i]); + vc_putchar(drv, buf[i]); } console_show_cursor(s, 1); - if (s->ds->have_gfx && s->update_x0 < s->update_x1) { - dpy_gfx_update(s, s->update_x0, s->update_y0, + if (s->update_x0 < s->update_x1) { + dpy_gfx_update(QEMU_CONSOLE(s), s->update_x0, s->update_y0, s->update_x1 - s->update_x0, s->update_y1 - s->update_y0); } return len; } -static void kbd_send_chars(QemuConsole *s) +static void kbd_send_chars(QemuTextConsole *s) { uint32_t len, avail; @@ -1309,15 +1135,12 @@ static void kbd_send_chars(QemuConsole *s) } /* called when an ascii key is pressed */ -void kbd_put_keysym_console(QemuConsole *s, int keysym) +void kbd_put_keysym_console(QemuTextConsole *s, int keysym) { uint8_t buf[16], *q; int c; uint32_t num_free; - if (!s || (s->console_type == GRAPHIC_CONSOLE)) - return; - switch(keysym) { case QEMU_KEY_CTRL_UP: console_scroll(s, -1); @@ -1347,13 +1170,13 @@ void kbd_put_keysym_console(QemuConsole *s, int keysym) *q++ = '['; *q++ = keysym & 0xff; } else if (s->echo && (keysym == '\r' || keysym == '\n')) { - vc_chr_write(s->chr, (const uint8_t *) "\r", 1); + qemu_chr_write(s->chr, (uint8_t *)"\r", 1, true); *q++ = '\n'; } else { *q++ = keysym; } if (s->echo) { - vc_chr_write(s->chr, buf, q - buf); + qemu_chr_write(s->chr, buf, q - buf, true); } num_free = fifo8_num_free(&s->out_fifo); fifo8_push_all(&s->out_fifo, buf, MIN(num_free, q - buf)); @@ -1387,7 +1210,7 @@ static const int ctrl_qcode_to_keysym[Q_KEY_CODE__MAX] = { [Q_KEY_CODE_PGDN] = QEMU_KEY_CTRL_PAGEDOWN, }; -bool kbd_put_qcode_console(QemuConsole *s, int qcode, bool ctrl) +bool kbd_put_qcode_console(QemuTextConsole *s, int qcode, bool ctrl) { int keysym; @@ -1399,7 +1222,7 @@ bool kbd_put_qcode_console(QemuConsole *s, int qcode, bool ctrl) return true; } -void kbd_put_string_console(QemuConsole *s, const char *str, int len) +void kbd_put_string_console(QemuTextConsole *s, const char *str, int len) { int i; @@ -1410,22 +1233,24 @@ void kbd_put_string_console(QemuConsole *s, const char *str, int len) void kbd_put_keysym(int keysym) { - kbd_put_keysym_console(active_console, keysym); + if (QEMU_IS_TEXT_CONSOLE(active_console)) { + kbd_put_keysym_console(QEMU_TEXT_CONSOLE(active_console), keysym); + } } static void text_console_invalidate(void *opaque) { - QemuConsole *s = (QemuConsole *) opaque; + QemuTextConsole *s = QEMU_TEXT_CONSOLE(opaque); - if (s->ds->have_text && s->console_type == TEXT_CONSOLE) { - text_console_resize(s); + if (!QEMU_IS_FIXED_TEXT_CONSOLE(s)) { + text_console_resize(QEMU_TEXT_CONSOLE(s)); } console_refresh(s); } static void text_console_update(void *opaque, console_ch_t *chardata) { - QemuConsole *s = (QemuConsole *) opaque; + QemuTextConsole *s = QEMU_TEXT_CONSOLE(opaque); int i, j, src; if (s->text_x[0] <= s->text_x[1]) { @@ -1439,7 +1264,7 @@ static void text_console_update(void *opaque, console_ch_t *chardata) s->cells[src].t_attrib.bgcol, s->cells[src].t_attrib.bold)); } - dpy_text_update(s, s->text_x[0], s->text_y[0], + dpy_text_update(QEMU_CONSOLE(s), s->text_x[0], s->text_y[0], s->text_x[1] - s->text_x[0], i - s->text_y[0]); s->text_x[0] = s->width; s->text_y[0] = s->height; @@ -1447,44 +1272,28 @@ static void text_console_update(void *opaque, console_ch_t *chardata) s->text_y[1] = 0; } if (s->cursor_invalidate) { - dpy_text_cursor(s, s->x, s->y); + dpy_text_cursor(QEMU_CONSOLE(s), s->x, s->y); s->cursor_invalidate = 0; } } -static QemuConsole *new_console(DisplayState *ds, console_type_t console_type, - uint32_t head) +static void +qemu_console_register(QemuConsole *c) { - Object *obj; - QemuConsole *s; int i; - obj = object_new(TYPE_QEMU_CONSOLE); - s = QEMU_CONSOLE(obj); - qemu_co_queue_init(&s->dump_queue); - s->head = head; - object_property_add_link(obj, "device", TYPE_DEVICE, - (Object **)&s->device, - object_property_allow_set_link, - OBJ_PROP_LINK_STRONG); - object_property_add_uint32_ptr(obj, "head", &s->head, - OBJ_PROP_FLAG_READ); - - if (!active_console || ((active_console->console_type != GRAPHIC_CONSOLE) && - (console_type == GRAPHIC_CONSOLE))) { - active_console = s; + if (!active_console || (!QEMU_IS_GRAPHIC_CONSOLE(active_console) && + QEMU_IS_GRAPHIC_CONSOLE(c))) { + active_console = c; } - s->ds = ds; - s->console_type = console_type; - s->window_id = -1; if (QTAILQ_EMPTY(&consoles)) { - s->index = 0; - QTAILQ_INSERT_TAIL(&consoles, s, next); - } else if (console_type != GRAPHIC_CONSOLE || phase_check(PHASE_MACHINE_READY)) { + c->index = 0; + QTAILQ_INSERT_TAIL(&consoles, c, next); + } else if (!QEMU_IS_GRAPHIC_CONSOLE(c) || phase_check(PHASE_MACHINE_READY)) { QemuConsole *last = QTAILQ_LAST(&consoles); - s->index = last->index + 1; - QTAILQ_INSERT_TAIL(&consoles, s, next); + c->index = last->index + 1; + QTAILQ_INSERT_TAIL(&consoles, c, next); } else { /* * HACK: Put graphical consoles before text consoles. @@ -1492,26 +1301,133 @@ static QemuConsole *new_console(DisplayState *ds, console_type_t console_type, * Only do that for coldplugged devices. After initial device * initialization we will not renumber the consoles any more. */ - QemuConsole *c = QTAILQ_FIRST(&consoles); + QemuConsole *it = QTAILQ_FIRST(&consoles); - while (QTAILQ_NEXT(c, next) != NULL && - c->console_type == GRAPHIC_CONSOLE) { - c = QTAILQ_NEXT(c, next); + while (QTAILQ_NEXT(it, next) != NULL && QEMU_IS_GRAPHIC_CONSOLE(it)) { + it = QTAILQ_NEXT(it, next); } - if (c->console_type == GRAPHIC_CONSOLE) { + if (QEMU_IS_GRAPHIC_CONSOLE(it)) { /* have no text consoles */ - s->index = c->index + 1; - QTAILQ_INSERT_AFTER(&consoles, c, s, next); + c->index = it->index + 1; + QTAILQ_INSERT_AFTER(&consoles, it, c, next); } else { - s->index = c->index; - QTAILQ_INSERT_BEFORE(c, s, next); + c->index = it->index; + QTAILQ_INSERT_BEFORE(it, c, next); /* renumber text consoles */ - for (i = s->index + 1; c != NULL; c = QTAILQ_NEXT(c, next), i++) { - c->index = i; + for (i = c->index + 1; it != NULL; it = QTAILQ_NEXT(it, next), i++) { + it->index = i; } } } - return s; +} + +static void +qemu_console_finalize(Object *obj) +{ + QemuConsole *c = QEMU_CONSOLE(obj); + + /* TODO: check this code path, and unregister from consoles */ + g_clear_pointer(&c->surface, qemu_free_displaysurface); + g_clear_pointer(&c->gl_unblock_timer, timer_free); + g_clear_pointer(&c->ui_timer, timer_free); +} + +static void +qemu_console_class_init(ObjectClass *oc, void *data) +{ +} + +static void +qemu_console_init(Object *obj) +{ + QemuConsole *c = QEMU_CONSOLE(obj); + DisplayState *ds = get_alloc_displaystate(); + + qemu_co_queue_init(&c->dump_queue); + c->ds = ds; + c->window_id = -1; + c->ui_timer = timer_new_ms(QEMU_CLOCK_REALTIME, + dpy_set_ui_info_timer, c); + qemu_console_register(c); +} + +static void +qemu_graphic_console_finalize(Object *obj) +{ + QemuGraphicConsole *c = QEMU_GRAPHIC_CONSOLE(obj); + + g_clear_pointer(&c->device, object_unref); +} + +static void +qemu_graphic_console_prop_get_head(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + QemuGraphicConsole *c = QEMU_GRAPHIC_CONSOLE(obj); + + visit_type_uint32(v, name, &c->head, errp); +} + +static void +qemu_graphic_console_class_init(ObjectClass *oc, void *data) +{ + object_class_property_add_link(oc, "device", TYPE_DEVICE, + offsetof(QemuGraphicConsole, device), + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG); + object_class_property_add(oc, "head", "uint32", + qemu_graphic_console_prop_get_head, + NULL, NULL, NULL); +} + +static void +qemu_graphic_console_init(Object *obj) +{ +} + +static void +qemu_text_console_finalize(Object *obj) +{ +} + +static void +qemu_text_console_class_init(ObjectClass *oc, void *data) +{ + if (!cursor_timer) { + cursor_timer = timer_new_ms(QEMU_CLOCK_REALTIME, + text_console_update_cursor, NULL); + } +} + +static const GraphicHwOps text_console_ops = { + .invalidate = text_console_invalidate, + .text_update = text_console_update, +}; + +static void +qemu_text_console_init(Object *obj) +{ + QemuTextConsole *c = QEMU_TEXT_CONSOLE(obj); + + fifo8_create(&c->out_fifo, 16); + c->total_height = DEFAULT_BACKSCROLL; + QEMU_CONSOLE(c)->hw_ops = &text_console_ops; + QEMU_CONSOLE(c)->hw = c; +} + +static void +qemu_fixed_text_console_finalize(Object *obj) +{ +} + +static void +qemu_fixed_text_console_class_init(ObjectClass *oc, void *data) +{ +} + +static void +qemu_fixed_text_console_init(Object *obj) +{ } #ifdef WIN32 @@ -1605,8 +1521,8 @@ DisplaySurface *qemu_create_placeholder_surface(int w, int h, const char *msg) { DisplaySurface *surface = qemu_create_displaysurface(w, h); - pixman_color_t bg = color_table_rgb[0][QEMU_COLOR_BLACK]; - pixman_color_t fg = color_table_rgb[0][QEMU_COLOR_WHITE]; + pixman_color_t bg = QEMU_PIXMAN_COLOR_BLACK; + pixman_color_t fg = QEMU_PIXMAN_COLOR_GRAY; pixman_image_t *glyph; int len, x, y, i; @@ -1757,6 +1673,16 @@ void qemu_console_set_display_gl_ctx(QemuConsole *con, DisplayGLCtx *gl) con->gl = gl; } +static void +dcl_set_graphic_cursor(DisplayChangeListener *dcl, QemuGraphicConsole *con) +{ + if (con && con->cursor && dcl->ops->dpy_cursor_define) { + dcl->ops->dpy_cursor_define(dcl, con->cursor); + } + if (con && dcl->ops->dpy_mouse_set) { + dcl->ops->dpy_mouse_set(dcl, con->cursor_x, con->cursor_y, con->cursor_on); + } +} void register_displaychangelistener(DisplayChangeListener *dcl) { QemuConsole *con; @@ -1774,11 +1700,8 @@ void register_displaychangelistener(DisplayChangeListener *dcl) con = active_console; } displaychangelistener_display_console(dcl, con, dcl->con ? &error_fatal : NULL); - if (con && con->cursor && dcl->ops->dpy_cursor_define) { - dcl->ops->dpy_cursor_define(dcl, con->cursor); - } - if (con && dcl->ops->dpy_mouse_set) { - dcl->ops->dpy_mouse_set(dcl, con->cursor_x, con->cursor_y, con->cursor_on); + if (QEMU_IS_GRAPHIC_CONSOLE(con)) { + dcl_set_graphic_cursor(dcl, QEMU_GRAPHIC_CONSOLE(con)); } text_console_update_cursor(NULL); } @@ -1809,8 +1732,9 @@ void unregister_displaychangelistener(DisplayChangeListener *dcl) static void dpy_set_ui_info_timer(void *opaque) { QemuConsole *con = opaque; + uint32_t head = qemu_console_get_head(con); - con->hw_ops->ui_info(con->hw, con->head, &con->ui_info); + con->hw_ops->ui_info(con->hw, head, &con->ui_info); } bool dpy_ui_info_supported(QemuConsole *con) @@ -2020,19 +1944,20 @@ void dpy_text_resize(QemuConsole *con, int w, int h) } } -void dpy_mouse_set(QemuConsole *con, int x, int y, int on) +void dpy_mouse_set(QemuConsole *c, int x, int y, int on) { - DisplayState *s = con->ds; + QemuGraphicConsole *con = QEMU_GRAPHIC_CONSOLE(c); + DisplayState *s = c->ds; DisplayChangeListener *dcl; con->cursor_x = x; con->cursor_y = y; con->cursor_on = on; - if (!qemu_console_is_visible(con)) { + if (!qemu_console_is_visible(c)) { return; } QLIST_FOREACH(dcl, &s->listeners, next) { - if (con != (dcl->con ? dcl->con : active_console)) { + if (c != (dcl->con ? dcl->con : active_console)) { continue; } if (dcl->ops->dpy_mouse_set) { @@ -2041,18 +1966,19 @@ void dpy_mouse_set(QemuConsole *con, int x, int y, int on) } } -void dpy_cursor_define(QemuConsole *con, QEMUCursor *cursor) +void dpy_cursor_define(QemuConsole *c, QEMUCursor *cursor) { - DisplayState *s = con->ds; + QemuGraphicConsole *con = QEMU_GRAPHIC_CONSOLE(c); + DisplayState *s = c->ds; DisplayChangeListener *dcl; cursor_unref(con->cursor); con->cursor = cursor_ref(cursor); - if (!qemu_console_is_visible(con)) { + if (!qemu_console_is_visible(c)) { return; } QLIST_FOREACH(dcl, &s->listeners, next) { - if (con != (dcl->con ? dcl->con : active_console)) { + if (c != (dcl->con ? dcl->con : active_console)) { continue; } if (dcl->ops->dpy_cursor_define) { @@ -2237,8 +2163,6 @@ static DisplayState *get_alloc_displaystate(void) { if (!display_state) { display_state = g_new0(DisplayState, 1); - cursor_timer = timer_new_ms(QEMU_CLOCK_REALTIME, - text_console_update_cursor, NULL); } return display_state; } @@ -2252,14 +2176,8 @@ DisplayState *init_displaystate(void) gchar *name; QemuConsole *con; - get_alloc_displaystate(); QTAILQ_FOREACH(con, &consoles, next) { - if (con->console_type != GRAPHIC_CONSOLE && - con->ds == NULL) { - text_console_do_init(con->chr, display_state); - } - - /* Hook up into the qom tree here (not in new_console()), once + /* Hook up into the qom tree here (not in object_new()), once * all QemuConsoles are created and the order / numbering * doesn't change any more */ name = g_strdup_printf("console[%d]", con->index); @@ -2288,21 +2206,18 @@ QemuConsole *graphic_console_init(DeviceState *dev, uint32_t head, int width = 640; int height = 480; QemuConsole *s; - DisplayState *ds; DisplaySurface *surface; - ds = get_alloc_displaystate(); - s = qemu_console_lookup_unused(); + s = qemu_graphic_console_lookup_unused(); if (s) { trace_console_gfx_reuse(s->index); width = qemu_console_get_width(s, 0); height = qemu_console_get_height(s, 0); } else { trace_console_gfx_new(); - s = new_console(ds, GRAPHIC_CONSOLE, head); - s->ui_timer = timer_new_ms(QEMU_CLOCK_REALTIME, - dpy_set_ui_info_timer, s); + s = (QemuConsole *)object_new(TYPE_QEMU_GRAPHIC_CONSOLE); } + QEMU_GRAPHIC_CONSOLE(s)->head = head; graphic_console_set_hwops(s, hw_ops, opaque); if (dev) { object_property_set_link(OBJECT(s), "device", OBJECT(dev), @@ -2396,13 +2311,13 @@ QemuConsole *qemu_console_lookup_by_device_name(const char *device_id, return con; } -QemuConsole *qemu_console_lookup_unused(void) +static QemuConsole *qemu_graphic_console_lookup_unused(void) { QemuConsole *con; Object *obj; QTAILQ_FOREACH(con, &consoles, next) { - if (con->hw_ops != &unused_ops) { + if (!QEMU_IS_GRAPHIC_CONSOLE(con) || con->hw_ops != &unused_ops) { continue; } obj = object_property_get_link(OBJECT(con), @@ -2420,7 +2335,7 @@ QEMUCursor *qemu_console_get_cursor(QemuConsole *con) if (con == NULL) { con = active_console; } - return con ? con->cursor : NULL; + return QEMU_IS_GRAPHIC_CONSOLE(con) ? QEMU_GRAPHIC_CONSOLE(con)->cursor : NULL; } bool qemu_console_is_visible(QemuConsole *con) @@ -2433,7 +2348,7 @@ bool qemu_console_is_graphic(QemuConsole *con) if (con == NULL) { con = active_console; } - return con && (con->console_type == GRAPHIC_CONSOLE); + return con && QEMU_IS_GRAPHIC_CONSOLE(con); } bool qemu_console_is_fixedsize(QemuConsole *con) @@ -2441,7 +2356,7 @@ bool qemu_console_is_fixedsize(QemuConsole *con) if (con == NULL) { con = active_console; } - return con && (con->console_type != TEXT_CONSOLE); + return con && (QEMU_IS_GRAPHIC_CONSOLE(con) || QEMU_IS_FIXED_TEXT_CONSOLE(con)); } bool qemu_console_is_gl_blocked(QemuConsole *con) @@ -2477,31 +2392,34 @@ bool qemu_console_is_multihead(DeviceState *dev) char *qemu_console_get_label(QemuConsole *con) { - if (con->console_type == GRAPHIC_CONSOLE) { - if (con->device) { + if (QEMU_IS_GRAPHIC_CONSOLE(con)) { + QemuGraphicConsole *c = QEMU_GRAPHIC_CONSOLE(con); + if (c->device) { DeviceState *dev; bool multihead; - dev = DEVICE(con->device); + dev = DEVICE(c->device); multihead = qemu_console_is_multihead(dev); if (multihead) { return g_strdup_printf("%s.%d", dev->id ? dev->id : - object_get_typename(con->device), - con->head); + object_get_typename(c->device), + c->head); } else { return g_strdup_printf("%s", dev->id ? dev->id : - object_get_typename(con->device)); + object_get_typename(c->device)); } } return g_strdup("VGA"); - } else { - if (con->chr && con->chr->label) { - return g_strdup(con->chr->label); + } else if (QEMU_IS_TEXT_CONSOLE(con)) { + QemuTextConsole *c = QEMU_TEXT_CONSOLE(con); + if (c->chr && c->chr->label) { + return g_strdup(c->chr->label); } - return g_strdup_printf("vc%d", con->index); } + + return g_strdup_printf("vc%d", con->index); } int qemu_console_get_index(QemuConsole *con) @@ -2517,7 +2435,13 @@ uint32_t qemu_console_get_head(QemuConsole *con) if (con == NULL) { con = active_console; } - return con ? con->head : -1; + if (con == NULL) { + return -1; + } + if (QEMU_IS_GRAPHIC_CONSOLE(con)) { + return QEMU_GRAPHIC_CONSOLE(con)->head; + } + return 0; } int qemu_console_get_width(QemuConsole *con, int fallback) @@ -2563,32 +2487,22 @@ int qemu_console_get_height(QemuConsole *con, int fallback) static void vc_chr_accept_input(Chardev *chr) { VCChardev *drv = VC_CHARDEV(chr); - QemuConsole *s = drv->console; - kbd_send_chars(s); + kbd_send_chars(drv->console); } static void vc_chr_set_echo(Chardev *chr, bool echo) { VCChardev *drv = VC_CHARDEV(chr); - QemuConsole *s = drv->console; - s->echo = echo; + drv->console->echo = echo; } -static void text_console_update_cursor_timer(void) -{ - timer_mod(cursor_timer, qemu_clock_get_ms(QEMU_CLOCK_REALTIME) - + CONSOLE_CURSOR_PERIOD / 2); -} - -static void text_console_update_cursor(void *opaque) +int qemu_invalidate_text_consoles(void) { QemuConsole *s; int count = 0; - cursor_visible_phase = !cursor_visible_phase; - QTAILQ_FOREACH(s, &consoles, next) { if (qemu_console_is_graphic(s) || !qemu_console_is_visible(s)) { @@ -2598,66 +2512,17 @@ static void text_console_update_cursor(void *opaque) graphic_hw_invalidate(s); } - if (count) { - text_console_update_cursor_timer(); - } + return count; } -static const GraphicHwOps text_console_ops = { - .invalidate = text_console_invalidate, - .text_update = text_console_update, -}; - -static void text_console_do_init(Chardev *chr, DisplayState *ds) +static void text_console_update_cursor(void *opaque) { - VCChardev *drv = VC_CHARDEV(chr); - QemuConsole *s = drv->console; - int g_width = 80 * FONT_WIDTH; - int g_height = 24 * FONT_HEIGHT; - - fifo8_create(&s->out_fifo, 16); - s->ds = ds; - - s->y_displayed = 0; - s->y_base = 0; - s->total_height = DEFAULT_BACKSCROLL; - s->x = 0; - s->y = 0; - if (s->scanout.kind != SCANOUT_SURFACE) { - if (active_console && active_console->scanout.kind == SCANOUT_SURFACE) { - g_width = qemu_console_get_width(active_console, g_width); - g_height = qemu_console_get_height(active_console, g_height); - } - s->surface = qemu_create_displaysurface(g_width, g_height); - s->scanout.kind = SCANOUT_SURFACE; - } - - s->hw_ops = &text_console_ops; - s->hw = s; - - /* Set text attribute defaults */ - s->t_attrib_default.bold = 0; - s->t_attrib_default.uline = 0; - s->t_attrib_default.blink = 0; - s->t_attrib_default.invers = 0; - s->t_attrib_default.unvisible = 0; - s->t_attrib_default.fgcol = QEMU_COLOR_WHITE; - s->t_attrib_default.bgcol = QEMU_COLOR_BLACK; - /* set current text attributes to default */ - s->t_attrib = s->t_attrib_default; - text_console_resize(s); - - if (chr->label) { - char *msg; + cursor_visible_phase = !cursor_visible_phase; - s->t_attrib.bgcol = QEMU_COLOR_BLUE; - msg = g_strdup_printf("%s console\r\n", chr->label); - vc_chr_write(chr, (uint8_t *)msg, strlen(msg)); - g_free(msg); - s->t_attrib = s->t_attrib_default; + if (qemu_invalidate_text_consoles()) { + timer_mod(cursor_timer, + qemu_clock_get_ms(QEMU_CLOCK_REALTIME) + CONSOLE_CURSOR_PERIOD / 2); } - - qemu_chr_be_event(chr, CHR_EVENT_OPENED); } static void vc_chr_open(Chardev *chr, @@ -2667,7 +2532,7 @@ static void vc_chr_open(Chardev *chr, { ChardevVC *vc = backend->u.vc.data; VCChardev *drv = VC_CHARDEV(chr); - QemuConsole *s; + QemuTextConsole *s; unsigned width = 0; unsigned height = 0; @@ -2685,36 +2550,40 @@ static void vc_chr_open(Chardev *chr, trace_console_txt_new(width, height); if (width == 0 || height == 0) { - s = new_console(NULL, TEXT_CONSOLE, 0); + s = QEMU_TEXT_CONSOLE(object_new(TYPE_QEMU_TEXT_CONSOLE)); + width = qemu_console_get_width(NULL, 80 * FONT_WIDTH); + height = qemu_console_get_height(NULL, 24 * FONT_HEIGHT); } else { - s = new_console(NULL, TEXT_CONSOLE_FIXED_SIZE, 0); - s->scanout.kind = SCANOUT_SURFACE; - s->surface = qemu_create_displaysurface(width, height); + s = QEMU_TEXT_CONSOLE(object_new(TYPE_QEMU_FIXED_TEXT_CONSOLE)); } - if (!s) { - error_setg(errp, "cannot create text console"); - return; - } + dpy_gfx_replace_surface(QEMU_CONSOLE(s), qemu_create_displaysurface(width, height)); s->chr = chr; drv->console = s; - if (display_state) { - text_console_do_init(chr, display_state); + /* set current text attributes to default */ + drv->t_attrib = TEXT_ATTRIBUTES_DEFAULT; + text_console_resize(s); + + if (chr->label) { + char *msg; + + drv->t_attrib.bgcol = QEMU_COLOR_BLUE; + msg = g_strdup_printf("%s console\r\n", chr->label); + qemu_chr_write(chr, (uint8_t *)msg, strlen(msg), true); + g_free(msg); + drv->t_attrib = TEXT_ATTRIBUTES_DEFAULT; } - /* console/chardev init sometimes completes elsewhere in a 2nd - * stage, so defer OPENED events until they are fully initialized - */ - *be_opened = false; + *be_opened = true; } void qemu_console_resize(QemuConsole *s, int width, int height) { DisplaySurface *surface = qemu_console_surface(s); - assert(s->console_type == GRAPHIC_CONSOLE); + assert(QEMU_IS_GRAPHIC_CONSOLE(s)); if ((s->scanout.kind != SCANOUT_SURFACE || (surface && surface->flags & QEMU_ALLOCATED_FLAG)) && @@ -2837,7 +2706,7 @@ void qemu_display_help(void) } } -void qemu_chr_parse_vc(QemuOpts *opts, ChardevBackend *backend, Error **errp) +static void vc_chr_parse(QemuOpts *opts, ChardevBackend *backend, Error **errp) { int val; ChardevVC *vc; @@ -2871,18 +2740,11 @@ void qemu_chr_parse_vc(QemuOpts *opts, ChardevBackend *backend, Error **errp) } } -static const TypeInfo qemu_console_info = { - .name = TYPE_QEMU_CONSOLE, - .parent = TYPE_OBJECT, - .instance_size = sizeof(QemuConsole), - .class_size = sizeof(QemuConsoleClass), -}; - static void char_vc_class_init(ObjectClass *oc, void *data) { ChardevClass *cc = CHARDEV_CLASS(oc); - cc->parse = qemu_chr_parse_vc; + cc->parse = vc_chr_parse; cc->open = vc_chr_open; cc->chr_write = vc_chr_write; cc->chr_accept_input = vc_chr_accept_input; @@ -2903,10 +2765,3 @@ void qemu_console_early_init(void) type_register(&char_vc_type_info); } } - -static void register_types(void) -{ - type_register_static(&qemu_console_info); -} - -type_init(register_types); diff --git a/ui/dbus-console.c b/ui/dbus-console.c index e19774f985..36f7349585 100644 --- a/ui/dbus-console.c +++ b/ui/dbus-console.c @@ -150,6 +150,8 @@ dbus_display_console_dispose(GObject *object) DBusDisplayConsole *ddc = DBUS_DISPLAY_CONSOLE(object); unregister_displaychangelistener(&ddc->dcl); + g_clear_object(&ddc->iface_touch); + g_clear_object(&ddc->iface_mouse); g_clear_object(&ddc->iface_kbd); g_clear_object(&ddc->iface); g_clear_pointer(&ddc->listeners, g_hash_table_unref); diff --git a/ui/dbus-listener.c b/ui/dbus-listener.c index 30917271ab..36548a7f52 100644 --- a/ui/dbus-listener.c +++ b/ui/dbus-listener.c @@ -26,6 +26,9 @@ #include "qapi/error.h" #include "sysemu/sysemu.h" #include "dbus.h" +#ifdef CONFIG_OPENGL +#include <pixman.h> +#endif #ifdef G_OS_UNIX #include <gio/gunixfdlist.h> #endif @@ -59,12 +62,15 @@ struct _DBusDisplayListener { QemuDBusDisplay1Listener *proxy; +#ifdef CONFIG_OPENGL + /* Keep track of the damage region */ + pixman_region32_t gl_damage; +#endif + DisplayChangeListener dcl; DisplaySurface *ds; enum share_kind ds_share; - int gl_updates; - bool ds_mapped; bool can_share_map; @@ -539,11 +545,16 @@ static void dbus_gl_refresh(DisplayChangeListener *dcl) return; } - if (ddl->gl_updates) { - dbus_call_update_gl(dcl, 0, 0, - surface_width(ddl->ds), surface_height(ddl->ds)); - ddl->gl_updates = 0; + int n_rects = pixman_region32_n_rects(&ddl->gl_damage); + + for (int i = 0; i < n_rects; i++) { + pixman_box32_t *box; + box = pixman_region32_rectangles(&ddl->gl_damage, NULL) + i; + /* TODO: Add a UpdateList call to send multiple updates at once */ + dbus_call_update_gl(dcl, box->x1, box->y1, + box->x2 - box->x1, box->y2 - box->y1); } + pixman_region32_clear(&ddl->gl_damage); } #endif /* OPENGL */ @@ -558,7 +569,10 @@ static void dbus_gl_gfx_update(DisplayChangeListener *dcl, { DBusDisplayListener *ddl = container_of(dcl, DBusDisplayListener, dcl); - ddl->gl_updates++; + pixman_region32_t rect_region; + pixman_region32_init_rect(&rect_region, x, y, w, h); + pixman_region32_union(&ddl->gl_damage, &ddl->gl_damage, &rect_region); + pixman_region32_fini(&rect_region); } #endif @@ -738,6 +752,7 @@ dbus_display_listener_dispose(GObject *object) g_clear_object(&ddl->d3d11_proxy); g_clear_pointer(&ddl->peer_process, CloseHandle); #ifdef CONFIG_OPENGL + pixman_region32_fini(&ddl->gl_damage); egl_fb_destroy(&ddl->fb); #endif #endif @@ -772,6 +787,9 @@ dbus_display_listener_class_init(DBusDisplayListenerClass *klass) static void dbus_display_listener_init(DBusDisplayListener *ddl) { +#ifdef CONFIG_OPENGL + pixman_region32_init(&ddl->gl_damage); +#endif } const char * diff --git a/ui/gtk.c b/ui/gtk.c index 8ba41c8f13..a14d56168d 100644 --- a/ui/gtk.c +++ b/ui/gtk.c @@ -1187,7 +1187,7 @@ static gboolean gd_text_key_down(GtkWidget *widget, GdkEventKey *key, void *opaque) { VirtualConsole *vc = opaque; - QemuConsole *con = vc->gfx.dcl.con; + QemuTextConsole *con = QEMU_TEXT_CONSOLE(vc->gfx.dcl.con); if (key->keyval == GDK_KEY_Delete) { kbd_put_qcode_console(con, Q_KEY_CODE_DELETE, false); @@ -1860,7 +1860,6 @@ static void char_gd_vc_class_init(ObjectClass *oc, void *data) { ChardevClass *cc = CHARDEV_CLASS(oc); - cc->parse = qemu_chr_parse_vc; cc->open = gd_vc_open; cc->chr_write = gd_vc_chr_write; cc->chr_accept_input = gd_vc_chr_accept_input; @@ -2360,7 +2359,7 @@ static void gtk_display_init(DisplayState *ds, DisplayOptions *opts) { VirtualConsole *vc; - GtkDisplayState *s = g_malloc0(sizeof(*s)); + GtkDisplayState *s; GdkDisplay *window_display; GtkIconTheme *theme; char *dir; @@ -2370,6 +2369,7 @@ static void gtk_display_init(DisplayState *ds, DisplayOptions *opts) exit(1); } assert(opts->type == DISPLAY_TYPE_GTK); + s = g_malloc0(sizeof(*s)); s->opts = opts; theme = gtk_icon_theme_get_default(); diff --git a/ui/keymaps.h b/ui/keymaps.h index 6473405485..3d52c0882a 100644 --- a/ui/keymaps.h +++ b/ui/keymaps.h @@ -44,7 +44,7 @@ typedef struct { /* "up" flag */ #define SCANCODE_UP 0x80 -/* Additional modifiers to use if not catched another way. */ +/* Additional modifiers to use if not caught another way. */ #define SCANCODE_SHIFT 0x100 #define SCANCODE_CTRL 0x200 #define SCANCODE_ALT 0x400 diff --git a/ui/qemu-pixman.c b/ui/qemu-pixman.c index e4f024a85e..be00a96340 100644 --- a/ui/qemu-pixman.c +++ b/ui/qemu-pixman.c @@ -200,14 +200,6 @@ void qemu_pixman_linebuf_fill(pixman_image_t *linebuf, pixman_image_t *fb, x, y, 0, 0, 0, 0, width, 1); } -/* copy linebuf to framebuffer */ -void qemu_pixman_linebuf_copy(pixman_image_t *fb, int width, int x, int y, - pixman_image_t *linebuf) -{ - pixman_image_composite(PIXMAN_OP_SRC, linebuf, NULL, fb, - 0, 0, 0, 0, x, y, width, 1); -} - pixman_image_t *qemu_pixman_mirror_create(pixman_format_code_t format, pixman_image_t *image) { @@ -226,17 +218,6 @@ void qemu_pixman_image_unref(pixman_image_t *image) pixman_image_unref(image); } -pixman_color_t qemu_pixman_color(PixelFormat *pf, uint32_t color) -{ - pixman_color_t c; - - c.red = ((color & pf->rmask) >> pf->rshift) << (16 - pf->rbits); - c.green = ((color & pf->gmask) >> pf->gshift) << (16 - pf->gbits); - c.blue = ((color & pf->bmask) >> pf->bshift) << (16 - pf->bbits); - c.alpha = ((color & pf->amask) >> pf->ashift) << (16 - pf->abits); - return c; -} - pixman_image_t *qemu_pixman_glyph_from_vgafont(int height, const uint8_t *font, unsigned int ch) { diff --git a/ui/sdl2-2d.c b/ui/sdl2-2d.c index bfebbdeaea..06468cd493 100644 --- a/ui/sdl2-2d.c +++ b/ui/sdl2-2d.c @@ -150,7 +150,7 @@ bool sdl2_2d_check_format(DisplayChangeListener *dcl, { /* * We let SDL convert for us a few more formats than, - * the native ones. Thes are the ones I have tested. + * the native ones. These are the ones I have tested. */ return (format == PIXMAN_x8r8g8b8 || format == PIXMAN_a8r8g8b8 || diff --git a/ui/sdl2-input.c b/ui/sdl2-input.c index f068382209..a318cc5867 100644 --- a/ui/sdl2-input.c +++ b/ui/sdl2-input.c @@ -43,15 +43,16 @@ void sdl2_process_key(struct sdl2_console *scon, ev->type == SDL_KEYDOWN ? "down" : "up"); qkbd_state_key_event(scon->kbd, qcode, ev->type == SDL_KEYDOWN); - if (!qemu_console_is_graphic(con)) { + if (QEMU_IS_TEXT_CONSOLE(con)) { + QemuTextConsole *s = QEMU_TEXT_CONSOLE(con); bool ctrl = qkbd_state_modifier_get(scon->kbd, QKBD_MOD_CTRL); if (ev->type == SDL_KEYDOWN) { switch (qcode) { case Q_KEY_CODE_RET: - kbd_put_keysym_console(con, '\n'); + kbd_put_keysym_console(s, '\n'); break; default: - kbd_put_qcode_console(con, qcode, ctrl); + kbd_put_qcode_console(s, qcode, ctrl); break; } } diff --git a/ui/sdl2.c b/ui/sdl2.c index 0d91b555e3..dfa260a507 100644 --- a/ui/sdl2.c +++ b/ui/sdl2.c @@ -483,10 +483,9 @@ static void handle_textinput(SDL_Event *ev) return; } - if (qemu_console_is_graphic(con)) { - return; + if (QEMU_IS_TEXT_CONSOLE(con)) { + kbd_put_string_console(QEMU_TEXT_CONSOLE(con), ev->text.text, strlen(ev->text.text)); } - kbd_put_string_console(con, ev->text.text, strlen(ev->text.text)); } static void handle_mousemotion(SDL_Event *ev) @@ -860,7 +859,7 @@ static void sdl2_display_init(DisplayState *ds, DisplayOptions *o) SDL_SetHint(SDL_HINT_VIDEO_X11_NET_WM_BYPASS_COMPOSITOR, "0"); #endif #ifndef CONFIG_WIN32 - /* QEMU uses its own low level keyboard hook procecure on Windows */ + /* QEMU uses its own low level keyboard hook procedure on Windows */ SDL_SetHint(SDL_HINT_GRAB_KEYBOARD, "1"); #endif #ifdef SDL_HINT_ALLOW_ALT_TAB_WHILE_GRABBED diff --git a/ui/spice-app.c b/ui/spice-app.c index ad7f0551ad..405fb7f9f5 100644 --- a/ui/spice-app.c +++ b/ui/spice-app.c @@ -96,6 +96,11 @@ static void vc_chr_set_echo(Chardev *chr, bool echo) /* TODO: set echo for frontends QMP and qtest */ } +static void vc_chr_parse(QemuOpts *opts, ChardevBackend *backend, Error **errp) +{ + /* fqdn is dealt with in vc_chr_open() */ +} + static void char_vc_class_init(ObjectClass *oc, void *data) { VCChardevClass *vc = CHARDEV_VC_CLASS(oc); @@ -103,7 +108,7 @@ static void char_vc_class_init(ObjectClass *oc, void *data) vc->parent_open = cc->open; - cc->parse = qemu_chr_parse_vc; + cc->parse = vc_chr_parse; cc->open = vc_chr_open; cc->chr_set_echo = vc_chr_set_echo; } diff --git a/ui/spice-display.c b/ui/spice-display.c index 3f3f8013d8..0e2fbfb17c 100644 --- a/ui/spice-display.c +++ b/ui/spice-display.c @@ -189,7 +189,7 @@ static void qemu_spice_create_update(SimpleSpiceDisplay *ssd) { static const int blksize = 32; int blocks = DIV_ROUND_UP(surface_width(ssd->ds), blksize); - int dirty_top[blocks]; + g_autofree int *dirty_top = NULL; int y, yoff1, yoff2, x, xoff, blk, bw; int bpp = surface_bytes_per_pixel(ssd->ds); uint8_t *guest, *mirror; @@ -198,6 +198,7 @@ static void qemu_spice_create_update(SimpleSpiceDisplay *ssd) return; }; + dirty_top = g_new(int, blocks); for (blk = 0; blk < blocks; blk++) { dirty_top[blk] = -1; } diff --git a/ui/ui-qmp-cmds.c b/ui/ui-qmp-cmds.c index a37a7024f3..debc07d678 100644 --- a/ui/ui-qmp-cmds.c +++ b/ui/ui-qmp-cmds.c @@ -14,13 +14,20 @@ */ #include "qemu/osdep.h" + +#include "io/channel-file.h" #include "monitor/qmp-helpers.h" #include "qapi/qapi-commands-ui.h" #include "qapi/qmp/qerror.h" +#include "qemu/coroutine.h" #include "qemu/cutils.h" +#include "trace.h" #include "ui/console.h" #include "ui/dbus-display.h" #include "ui/qemu-spice.h" +#ifdef CONFIG_PNG +#include <png.h> +#endif void qmp_set_password(SetPasswordOptions *opts, Error **errp) { @@ -204,3 +211,183 @@ void qmp_client_migrate_info(const char *protocol, const char *hostname, error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "protocol", "'spice'"); } + +#ifdef CONFIG_PNG +/** + * png_save: Take a screenshot as PNG + * + * Saves screendump as a PNG file + * + * Returns true for success or false for error. + * + * @fd: File descriptor for PNG file. + * @image: Image data in pixman format. + * @errp: Pointer to an error. + */ +static bool png_save(int fd, pixman_image_t *image, Error **errp) +{ + int width = pixman_image_get_width(image); + int height = pixman_image_get_height(image); + png_struct *png_ptr; + png_info *info_ptr; + g_autoptr(pixman_image_t) linebuf = + qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); + uint8_t *buf = (uint8_t *)pixman_image_get_data(linebuf); + FILE *f = fdopen(fd, "wb"); + int y; + if (!f) { + error_setg_errno(errp, errno, + "Failed to create file from file descriptor"); + return false; + } + + png_ptr = png_create_write_struct(PNG_LIBPNG_VER_STRING, NULL, + NULL, NULL); + if (!png_ptr) { + error_setg(errp, "PNG creation failed. Unable to write struct"); + fclose(f); + return false; + } + + info_ptr = png_create_info_struct(png_ptr); + + if (!info_ptr) { + error_setg(errp, "PNG creation failed. Unable to write info"); + fclose(f); + png_destroy_write_struct(&png_ptr, &info_ptr); + return false; + } + + png_init_io(png_ptr, f); + + png_set_IHDR(png_ptr, info_ptr, width, height, 8, + PNG_COLOR_TYPE_RGB, PNG_INTERLACE_NONE, + PNG_COMPRESSION_TYPE_BASE, PNG_FILTER_TYPE_BASE); + + png_write_info(png_ptr, info_ptr); + + for (y = 0; y < height; ++y) { + qemu_pixman_linebuf_fill(linebuf, image, width, 0, y); + png_write_row(png_ptr, buf); + } + + png_write_end(png_ptr, NULL); + + png_destroy_write_struct(&png_ptr, &info_ptr); + + if (fclose(f) != 0) { + error_setg_errno(errp, errno, + "PNG creation failed. Unable to close file"); + return false; + } + + return true; +} + +#else /* no png support */ + +static bool png_save(int fd, pixman_image_t *image, Error **errp) +{ + error_setg(errp, "Enable PNG support with libpng for screendump"); + return false; +} + +#endif /* CONFIG_PNG */ + +static bool ppm_save(int fd, pixman_image_t *image, Error **errp) +{ + int width = pixman_image_get_width(image); + int height = pixman_image_get_height(image); + g_autoptr(Object) ioc = OBJECT(qio_channel_file_new_fd(fd)); + g_autofree char *header = NULL; + g_autoptr(pixman_image_t) linebuf = NULL; + int y; + + trace_ppm_save(fd, image); + + header = g_strdup_printf("P6\n%d %d\n%d\n", width, height, 255); + if (qio_channel_write_all(QIO_CHANNEL(ioc), + header, strlen(header), errp) < 0) { + return false; + } + + linebuf = qemu_pixman_linebuf_create(PIXMAN_BE_r8g8b8, width); + for (y = 0; y < height; y++) { + qemu_pixman_linebuf_fill(linebuf, image, width, 0, y); + if (qio_channel_write_all(QIO_CHANNEL(ioc), + (char *)pixman_image_get_data(linebuf), + pixman_image_get_stride(linebuf), errp) < 0) { + return false; + } + } + + return true; +} + +/* Safety: coroutine-only, concurrent-coroutine safe, main thread only */ +void coroutine_fn +qmp_screendump(const char *filename, const char *device, + bool has_head, int64_t head, + bool has_format, ImageFormat format, Error **errp) +{ + g_autoptr(pixman_image_t) image = NULL; + QemuConsole *con; + DisplaySurface *surface; + int fd; + + if (device) { + con = qemu_console_lookup_by_device_name(device, has_head ? head : 0, + errp); + if (!con) { + return; + } + } else { + if (has_head) { + error_setg(errp, "'head' must be specified together with 'device'"); + return; + } + con = qemu_console_lookup_by_index(0); + if (!con) { + error_setg(errp, "There is no console to take a screendump from"); + return; + } + } + + qemu_console_co_wait_update(con); + + /* + * All pending coroutines are woken up, while the BQL is held. No + * further graphic update are possible until it is released. Take + * an image ref before that. + */ + surface = qemu_console_surface(con); + if (!surface) { + error_setg(errp, "no surface"); + return; + } + image = pixman_image_ref(surface->image); + + fd = qemu_open_old(filename, O_WRONLY | O_CREAT | O_TRUNC | O_BINARY, 0666); + if (fd == -1) { + error_setg(errp, "failed to open file '%s': %s", filename, + strerror(errno)); + return; + } + + /* + * The image content could potentially be updated as the coroutine + * yields and releases the BQL. It could produce corrupted dump, but + * it should be otherwise safe. + */ + if (has_format && format == IMAGE_FORMAT_PNG) { + /* PNG format specified for screendump */ + if (!png_save(fd, image, errp)) { + qemu_unlink(filename); + } + } else { + /* PPM format specified/default for screendump */ + if (!ppm_save(fd, image, errp)) { + qemu_unlink(filename); + } + } +} diff --git a/ui/vdagent.c b/ui/vdagent.c index 8a651492f0..00d36a8677 100644 --- a/ui/vdagent.c +++ b/ui/vdagent.c @@ -870,8 +870,11 @@ static void vdagent_disconnect(VDAgentChardev *vd) static void vdagent_chr_set_fe_open(struct Chardev *chr, int fe_open) { + VDAgentChardev *vd = QEMU_VDAGENT_CHARDEV(chr); + if (!fe_open) { trace_vdagent_close(); + vdagent_disconnect(vd); /* To reset_serial, we CLOSED our side. Make sure the other end knows we * are ready again. */ qemu_chr_be_event(chr, CHR_EVENT_OPENED); @@ -923,6 +926,9 @@ static void vdagent_chr_fini(Object *obj) migrate_del_blocker(vd->migration_blocker); vdagent_disconnect(vd); + if (vd->mouse_hs) { + qemu_input_handler_unregister(vd->mouse_hs); + } buffer_free(&vd->outbuf); error_free(vd->migration_blocker); } diff --git a/ui/vnc-enc-hextile-template.h b/ui/vnc-enc-hextile-template.h index 0c56262aff..8ee92086ac 100644 --- a/ui/vnc-enc-hextile-template.h +++ b/ui/vnc-enc-hextile-template.h @@ -7,6 +7,8 @@ #define NAME BPP #endif +#define MAX_BYTES_PER_PIXEL 4 + static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, int x, int y, int w, int h, void *last_bg_, @@ -25,10 +27,13 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, int bg_count = 0; int fg_count = 0; int flags = 0; - uint8_t data[(vs->client_pf.bytes_per_pixel + 2) * 16 * 16]; + uint8_t data[(MAX_BYTES_PER_PIXEL + 2) * 16 * 16]; int n_data = 0; int n_subtiles = 0; + /* Enforced by set_pixel_format() */ + assert(vs->client_pf.bytes_per_pixel <= MAX_BYTES_PER_PIXEL); + for (j = 0; j < h; j++) { for (i = 0; i < w; i++) { switch (n_colors) { @@ -205,6 +210,7 @@ static void CONCAT(send_hextile_tile_, NAME)(VncState *vs, } } +#undef MAX_BYTES_PER_PIXEL #undef NAME #undef pixel_t #undef CONCAT_I diff --git a/ui/vnc-enc-tight.c b/ui/vnc-enc-tight.c index ee853dcfcb..41f559eb83 100644 --- a/ui/vnc-enc-tight.c +++ b/ui/vnc-enc-tight.c @@ -1097,13 +1097,13 @@ static int send_palette_rect(VncState *vs, int x, int y, switch (vs->client_pf.bytes_per_pixel) { case 4: { - size_t old_offset, offset; - uint32_t header[palette_size(palette)]; + size_t old_offset, offset, palette_sz = palette_size(palette); + g_autofree uint32_t *header = g_new(uint32_t, palette_sz); struct palette_cb_priv priv = { vs, (uint8_t *)header }; old_offset = vs->output.offset; palette_iter(palette, write_palette, &priv); - vnc_write(vs, header, sizeof(header)); + vnc_write(vs, header, palette_sz * sizeof(uint32_t)); if (vs->tight->pixel24) { tight_pack24(vs, vs->output.buffer + old_offset, colors, &offset); @@ -1115,11 +1115,12 @@ static int send_palette_rect(VncState *vs, int x, int y, } case 2: { - uint16_t header[palette_size(palette)]; + size_t palette_sz = palette_size(palette); + g_autofree uint16_t *header = g_new(uint16_t, palette_sz); struct palette_cb_priv priv = { vs, (uint8_t *)header }; palette_iter(palette, write_palette, &priv); - vnc_write(vs, header, sizeof(header)); + vnc_write(vs, header, palette_sz * sizeof(uint16_t)); tight_encode_indexed_rect16(vs->tight->tight.buffer, w * h, palette); break; } diff --git a/ui/vnc-enc-zrle.c.inc b/ui/vnc-enc-zrle.c.inc index c107d8affc..a8ca37d05e 100644 --- a/ui/vnc-enc-zrle.c.inc +++ b/ui/vnc-enc-zrle.c.inc @@ -110,7 +110,7 @@ static void ZRLE_ENCODE_TILE(VncState *vs, ZRLE_PIXEL *data, int w, int h, ZRLE_PIXEL *end = ptr + h * w; *end = ~*(end-1); /* one past the end is different so the while loop ends */ - /* Real limit is 127 but we wan't a way to know if there is more than 127 */ + /* Real limit is 127 but we want a way to know if there is more than 127 */ palette_init(palette, 256, ZRLE_BPP); while (ptr < end) { diff --git a/ui/vnc-enc-zywrle.h b/ui/vnc-enc-zywrle.h index e661ec117d..64fbc90ee7 100644 --- a/ui/vnc-enc-zywrle.h +++ b/ui/vnc-enc-zywrle.h @@ -485,7 +485,7 @@ static inline void wavelet(int *buf, int width, int height, int level) /* RGB <=> YUV conversion stuffs. - YUV coversion is explained as following formula in strict meaning: + YUV conversion is explained as following formula in strict meaning: Y = 0.299R + 0.587G + 0.114B ( 0<=Y<=255) U = -0.169R - 0.331G + 0.500B (-128<=U<=127) V = 0.500R - 0.419G - 0.081B (-128<=V<=127) @@ -539,7 +539,7 @@ static inline void wavelet(int *buf, int width, int height, int level) +------+------+ So, we must transfer each sub images individually in strict meaning. - But at least ZRLE meaning, following one decompositon image is same as + But at least ZRLE meaning, following one decomposition image is same as avobe individual sub image. I use this format. (Strictly saying, transfer order is reverse(Hxy->Hy->Hx->L) for simplified procedure for any wavelet level.) diff --git a/util/cpuinfo-aarch64.c b/util/cpuinfo-aarch64.c index ababc39550..7d39f47e3b 100644 --- a/util/cpuinfo-aarch64.c +++ b/util/cpuinfo-aarch64.c @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for AArch64. + * Host specific cpu identification for AArch64. */ #include "qemu/osdep.h" @@ -33,7 +33,7 @@ static bool sysctl_for_bool(const char *name) /* * We might in the future ask for properties not present in older kernels, * but we're only asking about static properties, all of which should be - * 'int'. So we shouln't see ENOMEM (val too small), or any of the other + * 'int'. So we shouldn't see ENOMEM (val too small), or any of the other * more exotic errors. */ assert(errno == ENOENT); diff --git a/util/cpuinfo-i386.c b/util/cpuinfo-i386.c index 3a7b7e0ad1..b2ed65bb10 100644 --- a/util/cpuinfo-i386.c +++ b/util/cpuinfo-i386.c @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for x86. + * Host specific cpu identification for x86. */ #include "qemu/osdep.h" @@ -74,7 +74,7 @@ unsigned __attribute__((constructor)) cpuinfo_init(void) * of their memory operands to be 16-byte aligned. * * AMD has provided an even stronger guarantee that processors - * with AVX provide 16-byte atomicity for all cachable, + * with AVX provide 16-byte atomicity for all cacheable, * naturally aligned single loads and stores, e.g. MOVDQU. * * See https://gcc.gnu.org/bugzilla/show_bug.cgi?id=104688 diff --git a/util/cpuinfo-ppc.c b/util/cpuinfo-ppc.c index 7212afa45d..1ea3db0ac8 100644 --- a/util/cpuinfo-ppc.c +++ b/util/cpuinfo-ppc.c @@ -1,6 +1,6 @@ /* * SPDX-License-Identifier: GPL-2.0-or-later - * Host specific cpu indentification for ppc. + * Host specific cpu identification for ppc. */ #include "qemu/osdep.h" diff --git a/util/main-loop.c b/util/main-loop.c index 014c795916..797b640c41 100644 --- a/util/main-loop.c +++ b/util/main-loop.c @@ -47,7 +47,7 @@ */ /* * Disable CFI checks. - * We are going to call a signal hander directly. Such handler may or may not + * We are going to call a signal handler directly. Such handler may or may not * have been defined in our binary, so there's no guarantee that the pointer * used to set the handler is a cfi-valid pointer. Since the handlers are * stored in kernel memory, changing the handler to an attacker-defined diff --git a/util/oslib-posix.c b/util/oslib-posix.c index 760390b31e..4d583da7ce 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -671,7 +671,7 @@ void qemu_free_stack(void *stack, size_t sz) /* * Disable CFI checks. - * We are going to call a signal hander directly. Such handler may or may not + * We are going to call a signal handler directly. Such handler may or may not * have been defined in our binary, so there's no guarantee that the pointer * used to set the handler is a cfi-valid pointer. Since the handlers are * stored in kernel memory, changing the handler to an attacker-defined diff --git a/util/qdist.c b/util/qdist.c index 5f75e24c29..ef3566b03a 100644 --- a/util/qdist.c +++ b/util/qdist.c @@ -210,7 +210,7 @@ void qdist_bin__internal(struct qdist *to, const struct qdist *from, size_t n) /* * To avoid double-counting we capture [left, right) ranges, except for - * the righmost bin, which captures a [left, right] range. + * the rightmost bin, which captures a [left, right] range. */ while (j < from->n && (from->entries[j].x < right || i == n - 1)) { struct qdist_entry *o = &from->entries[j]; diff --git a/util/qemu-sockets.c b/util/qemu-sockets.c index 892d33f5e6..83e84b1186 100644 --- a/util/qemu-sockets.c +++ b/util/qemu-sockets.c @@ -929,7 +929,7 @@ static int unix_listen_saddr(UnixSocketAddress *saddr, if (pathbuf != NULL) { /* - * This dummy fd usage silences the mktemp() unsecure warning. + * This dummy fd usage silences the mktemp() insecure warning. * Using mkstemp() doesn't make things more secure here * though. bind() complains about existing files, so we have * to unlink first and thus re-open the race window. The diff --git a/util/rcu.c b/util/rcu.c index 30a7e22026..e587bcc483 100644 --- a/util/rcu.c +++ b/util/rcu.c @@ -355,7 +355,7 @@ void drain_call_rcu(void) * * Note that since we have only one global queue of the RCU callbacks, * we also end up waiting for most of RCU callbacks that were registered - * on the other threads, but this is a side effect that shoudn't be + * on the other threads, but this is a side effect that shouldn't be * assumed. */ diff --git a/util/selfmap.c b/util/selfmap.c index 4db5b42651..483cb617e2 100644 --- a/util/selfmap.c +++ b/util/selfmap.c @@ -30,19 +30,21 @@ IntervalTreeRoot *read_self_maps(void) if (nfields > 4) { uint64_t start, end, offset, inode; + unsigned dev_maj, dev_min; int errors = 0; const char *p; errors |= qemu_strtou64(fields[0], &p, 16, &start); errors |= qemu_strtou64(p + 1, NULL, 16, &end); errors |= qemu_strtou64(fields[2], NULL, 16, &offset); + errors |= qemu_strtoui(fields[3], &p, 16, &dev_maj); + errors |= qemu_strtoui(p + 1, NULL, 16, &dev_min); errors |= qemu_strtou64(fields[4], NULL, 10, &inode); if (!errors) { - size_t dev_len, path_len; + size_t path_len; MapInfo *e; - dev_len = strlen(fields[3]) + 1; if (nfields == 6) { p = fields[5]; p += strspn(p, " "); @@ -52,11 +54,12 @@ IntervalTreeRoot *read_self_maps(void) path_len = 0; } - e = g_malloc0(sizeof(*e) + dev_len + path_len); + e = g_malloc0(sizeof(*e) + path_len); e->itree.start = start; e->itree.last = end - 1; e->offset = offset; + e->dev = makedev(dev_maj, dev_min); e->inode = inode; e->is_read = fields[1][0] == 'r'; @@ -64,9 +67,8 @@ IntervalTreeRoot *read_self_maps(void) e->is_exec = fields[1][2] == 'x'; e->is_priv = fields[1][3] == 'p'; - memcpy(e->dev, fields[3], dev_len); if (path_len) { - e->path = memcpy(e->dev + dev_len, p, path_len); + e->path = memcpy(e + 1, p, path_len); } interval_tree_insert(&e->itree, root); |