diff options
48 files changed, 469 insertions, 154 deletions
diff --git a/README.rst b/README.rst index ce39d89077..91aa1e314c 100644 --- a/README.rst +++ b/README.rst @@ -66,7 +66,9 @@ When submitting patches, one common approach is to use 'git format-patch' and/or 'git send-email' to format & send the mail to the qemu-devel@nongnu.org mailing list. All patches submitted must contain a 'Signed-off-by' line from the author. Patches should follow the -guidelines set out in the CODING_STYLE.rst file. +guidelines set out in the `style section +<https://www.qemu.org/docs/master/devel/style.html>` of +the Developers Guide. Additional information on submitting patches can be found online via the QEMU website diff --git a/docs/devel/index.rst b/docs/devel/index.rst index 22854e334d..ae664da00c 100644 --- a/docs/devel/index.rst +++ b/docs/devel/index.rst @@ -14,6 +14,7 @@ Contents: :maxdepth: 2 build-system + style kconfig testing fuzzing diff --git a/CODING_STYLE.rst b/docs/devel/style.rst index 7bf4e39d48..8b0bdb3570 100644 --- a/CODING_STYLE.rst +++ b/docs/devel/style.rst @@ -641,7 +641,7 @@ trace-events style In trace-events files, use a '0x' prefix to specify hex numbers, as in: -.. code-block:: +.. code-block:: c some_trace(unsigned x, uint64_t y) "x 0x%x y 0x" PRIx64 @@ -649,14 +649,14 @@ An exception is made for groups of numbers that are hexadecimal by convention and separated by the symbols '.', '/', ':', or ' ' (such as PCI bus id): -.. code-block:: +.. code-block:: c another_trace(int cssid, int ssid, int dev_num) "bus id: %x.%x.%04x" However, you can use '0x' for such groups if you want. Anyway, be sure that it is obvious that numbers are in hex, ex.: -.. code-block:: +.. code-block:: c data_dump(uint8_t c1, uint8_t c2, uint8_t c3) "bytes (in hex): %02x %02x %02x" diff --git a/docs/devel/testing.rst b/docs/devel/testing.rst index 00ce16de48..1434a50cc4 100644 --- a/docs/devel/testing.rst +++ b/docs/devel/testing.rst @@ -272,21 +272,28 @@ Note that the following group names have a special meaning: - disabled: Tests in this group are disabled and ignored by check. -.. _docker-ref: +.. _container-ref: -Docker based tests -================== +Container based tests +===================== Introduction ------------ -The Docker testing framework in QEMU utilizes public Docker images to build and -test QEMU in predefined and widely accessible Linux environments. This makes -it possible to expand the test coverage across distros, toolchain flavors and -library versions. +The container testing framework in QEMU utilizes public images to +build and test QEMU in predefined and widely accessible Linux +environments. This makes it possible to expand the test coverage +across distros, toolchain flavors and library versions. The support +was originally written for Docker although we also support Podman as +an alternative container runtime. Although the many of the target +names and scripts are prefixed with "docker" the system will +automatically run on whichever is configured. -Prerequisites -------------- +The container images are also used to augment the generation of tests +for testing TCG. See :ref:`checktcg-ref` for more details. + +Docker Prerequisites +-------------------- Install "docker" with the system package manager and start the Docker service on your development machine, then make sure you have the privilege to run @@ -316,26 +323,53 @@ Note that any one of above configurations makes it possible for the user to exploit the whole host with Docker bind mounting or other privileged operations. So only do it on development machines. +Podman Prerequisites +-------------------- + +Install "podman" with the system package manager. + +.. code:: + + $ sudo dnf install podman + $ podman ps + +The last command should print an empty table, to verify the system is ready. + Quickstart ---------- -From source tree, type ``make docker`` to see the help. Testing can be started -without configuring or building QEMU (``configure`` and ``make`` are done in -the container, with parameters defined by the make target): +From source tree, type ``make docker-help`` to see the help. Testing +can be started without configuring or building QEMU (``configure`` and +``make`` are done in the container, with parameters defined by the +make target): .. code:: - make docker-test-build@min-glib + make docker-test-build@centos8 -This will create a container instance using the ``min-glib`` image (the image +This will create a container instance using the ``centos8`` image (the image is downloaded and initialized automatically), in which the ``test-build`` job is executed. +Registry +-------- + +The QEMU project has a container registry hosted by GitLab at +``registry.gitlab.com/qemu-project/qemu`` which will automatically be +used to pull in pre-built layers. This avoids unnecessary strain on +the distro archives created by multiple developers running the same +container build steps over and over again. This can be overridden +locally by using the ``NOCACHE`` build option: + +.. code:: + + make docker-image-debian10 NOCACHE=1 + Images ------ -Along with many other images, the ``min-glib`` image is defined in a Dockerfile -in ``tests/docker/dockerfiles/``, called ``min-glib.docker``. ``make docker`` +Along with many other images, the ``centos8`` image is defined in a Dockerfile +in ``tests/docker/dockerfiles/``, called ``centos8.docker``. ``make docker-help`` command will list all the available images. To add a new image, simply create a new ``.docker`` file under the @@ -355,7 +389,7 @@ QEMU. Docker tests are the executables under ``tests/docker`` named library, ``tests/docker/common.rc``, which provides helpers to find the QEMU source and build it. -The full list of tests is printed in the ``make docker`` help. +The full list of tests is printed in the ``make docker-help`` help. Debugging a Docker test failure ------------------------------- @@ -980,6 +1014,8 @@ And remove any package you want with:: If you've used ``make check-acceptance``, the Python virtual environment where Avocado is installed will be cleaned up as part of ``make check-clean``. +.. _checktcg-ref: + Testing with "make check-tcg" ============================= @@ -1001,10 +1037,17 @@ for the architecture in question, for example:: There is also a ``--cross-cc-flags-ARCH`` flag in case additional compiler flags are needed to build for a given target. -If you have the ability to run containers as the user you can also -take advantage of the build systems "Docker" support. It will then use -containers to build any test case for an enabled guest where there is -no system compiler available. See :ref:`docker-ref` for details. +If you have the ability to run containers as the user the build system +will automatically use them where no system compiler is available. For +architectures where we also support building QEMU we will generally +use the same container to build tests. However there are a number of +additional containers defined that have a minimal cross-build +environment that is only suitable for building test cases. Sometimes +we may use a bleeding edge distribution for compiler features needed +for test cases that aren't yet in the LTS distros we support for QEMU +itself. + +See :ref:`container-ref` for more details. Running subset of tests ----------------------- diff --git a/hw/acpi/core.c b/hw/acpi/core.c index 7170bff657..1e004d0078 100644 --- a/hw/acpi/core.c +++ b/hw/acpi/core.c @@ -579,6 +579,10 @@ void acpi_pm1_cnt_update(ACPIREGS *ar, bool sci_enable, bool sci_disable) { /* ACPI specs 3.0, 4.7.2.5 */ + if (ar->pm1.cnt.acpi_only) { + return; + } + if (sci_enable) { ar->pm1.cnt.cnt |= ACPI_BITMASK_SCI_ENABLE; } else if (sci_disable) { @@ -608,11 +612,13 @@ static const MemoryRegionOps acpi_pm_cnt_ops = { }; void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent, - bool disable_s3, bool disable_s4, uint8_t s4_val) + bool disable_s3, bool disable_s4, uint8_t s4_val, + bool acpi_only) { FWCfgState *fw_cfg; ar->pm1.cnt.s4_val = s4_val; + ar->pm1.cnt.acpi_only = acpi_only; ar->wakeup.notify = acpi_notify_wakeup; qemu_register_wakeup_notifier(&ar->wakeup); @@ -638,6 +644,9 @@ void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent, void acpi_pm1_cnt_reset(ACPIREGS *ar) { ar->pm1.cnt.cnt = 0; + if (ar->pm1.cnt.acpi_only) { + ar->pm1.cnt.cnt |= ACPI_BITMASK_SCI_ENABLE; + } } /* ACPI GPE */ diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 5ff4e01c36..853447cf9d 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -282,7 +282,7 @@ void ich9_pm_init(PCIDevice *lpc_pci, ICH9LPCPMRegs *pm, acpi_pm_tmr_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_evt_init(&pm->acpi_regs, ich9_pm_update_sci_fn, &pm->io); acpi_pm1_cnt_init(&pm->acpi_regs, &pm->io, pm->disable_s3, pm->disable_s4, - pm->s4_val); + pm->s4_val, !pm->smm_compat && !smm_enabled); acpi_gpe_init(&pm->acpi_regs, ICH9_PMIO_GPE0_LEN); memory_region_init_io(&pm->io_gpe, OBJECT(lpc_pci), &ich9_gpe_ops, pm, diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 669be5bbf6..1efc0ded9f 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -74,6 +74,7 @@ struct PIIX4PMState { qemu_irq irq; qemu_irq smi_irq; int smm_enabled; + bool smm_compat; Notifier machine_ready; Notifier powerdown_notifier; @@ -496,7 +497,8 @@ static void piix4_pm_realize(PCIDevice *dev, Error **errp) acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); - acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val); + acpi_pm1_cnt_init(&s->ar, &s->io, s->disable_s3, s->disable_s4, s->s4_val, + !s->smm_compat && !s->smm_enabled); acpi_gpe_init(&s->ar, GPE_LEN); s->powerdown_notifier.notify = piix4_pm_powerdown_req; @@ -642,6 +644,7 @@ static Property piix4_pm_properties[] = { use_acpi_root_pci_hotplug, true), DEFINE_PROP_BOOL("memory-hotplug-support", PIIX4PMState, acpi_memory_hotplug.is_enabled, true), + DEFINE_PROP_BOOL("smm-compat", PIIX4PMState, smm_compat, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/core/machine.c b/hw/core/machine.c index 970046f438..4386f57b5c 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -36,7 +36,10 @@ #include "hw/virtio/virtio.h" #include "hw/virtio/virtio-pci.h" -GlobalProperty hw_compat_5_2[] = {}; +GlobalProperty hw_compat_5_2[] = { + { "ICH9-LPC", "smm-compat", "on"}, + { "PIIX4_PM", "smm-compat", "on"}, +}; const size_t hw_compat_5_2_len = G_N_ELEMENTS(hw_compat_5_2); GlobalProperty hw_compat_5_1[] = { diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index b9190b924a..31a5f6f4a5 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -139,6 +139,14 @@ const struct AcpiGenericAddress x86_nvdimm_acpi_dsmio = { static void init_common_fadt_data(MachineState *ms, Object *o, AcpiFadtData *data) { + X86MachineState *x86ms = X86_MACHINE(ms); + /* + * "ICH9-LPC" or "PIIX4_PM" has "smm-compat" property to keep the old + * behavior for compatibility irrelevant to smm_enabled, which doesn't + * comforms to ACPI spec. + */ + bool smm_enabled = object_property_get_bool(o, "smm-compat", NULL) ? + true : x86_machine_is_smm_enabled(x86ms); uint32_t io = object_property_get_uint(o, ACPI_PM_PROP_PM_IO_BASE, NULL); AmlAddressSpace as = AML_AS_SYSTEM_IO; AcpiFadtData fadt = { @@ -159,12 +167,16 @@ static void init_common_fadt_data(MachineState *ms, Object *o, .rtc_century = RTC_CENTURY, .plvl2_lat = 0xfff /* C2 state not supported */, .plvl3_lat = 0xfff /* C3 state not supported */, - .smi_cmd = ACPI_PORT_SMI_CMD, + .smi_cmd = smm_enabled ? ACPI_PORT_SMI_CMD : 0, .sci_int = object_property_get_uint(o, ACPI_PM_PROP_SCI_INT, NULL), .acpi_enable_cmd = - object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL), + smm_enabled ? + object_property_get_uint(o, ACPI_PM_PROP_ACPI_ENABLE_CMD, NULL) : + 0, .acpi_disable_cmd = - object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL), + smm_enabled ? + object_property_get_uint(o, ACPI_PM_PROP_ACPI_DISABLE_CMD, NULL) : + 0, .pm1a_evt = { .space_id = as, .bit_width = 4 * 8, .address = io }, .pm1a_cnt = { .space_id = as, .bit_width = 2 * 8, .address = io + 0x04 }, @@ -1060,6 +1072,46 @@ static void build_q35_pci0_int(Aml *table) aml_append(table, sb_scope); } +static Aml *build_q35_dram_controller(const AcpiMcfgInfo *mcfg) +{ + Aml *dev; + Aml *resource_template; + + /* DRAM controller */ + dev = aml_device("DRAC"); + aml_append(dev, aml_name_decl("_HID", aml_string("PNP0C01"))); + + resource_template = aml_resource_template(); + if (mcfg->base + mcfg->size - 1 >= (1ULL << 32)) { + aml_append(resource_template, + aml_qword_memory(AML_POS_DECODE, + AML_MIN_FIXED, + AML_MAX_FIXED, + AML_NON_CACHEABLE, + AML_READ_WRITE, + 0x0000000000000000, + mcfg->base, + mcfg->base + mcfg->size - 1, + 0x0000000000000000, + mcfg->size)); + } else { + aml_append(resource_template, + aml_dword_memory(AML_POS_DECODE, + AML_MIN_FIXED, + AML_MAX_FIXED, + AML_NON_CACHEABLE, + AML_READ_WRITE, + 0x0000000000000000, + mcfg->base, + mcfg->base + mcfg->size - 1, + 0x0000000000000000, + mcfg->size)); + } + aml_append(dev, aml_name_decl("_CRS", resource_template)); + + return dev; +} + static void build_q35_isa_bridge(Aml *table) { Aml *dev; @@ -1206,6 +1258,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(machine); X86MachineState *x86ms = X86_MACHINE(machine); AcpiMcfgInfo mcfg; + bool mcfg_valid = !!acpi_get_mcfg(&mcfg); uint32_t nr_mem = machine->ram_slots; int root_bus_limit = 0xFF; PCIBus *bus = NULL; @@ -1228,7 +1281,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(sb_scope, dev); aml_append(dsdt, sb_scope); - build_hpet_aml(dsdt); + if (misc->has_hpet) { + build_hpet_aml(dsdt); + } build_piix4_isa_bridge(dsdt); build_isa_devices_aml(dsdt); if (pm->pcihp_bridge_en || pm->pcihp_root_en) { @@ -1244,6 +1299,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_UID", aml_int(0))); aml_append(dev, build_q35_osc_method()); aml_append(sb_scope, dev); + if (mcfg_valid) { + aml_append(sb_scope, build_q35_dram_controller(&mcfg)); + } if (pm->smi_on_cpuhp) { /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ @@ -1272,7 +1330,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dsdt, sb_scope); - build_hpet_aml(dsdt); + if (misc->has_hpet) { + build_hpet_aml(dsdt); + } build_q35_isa_bridge(dsdt); build_isa_devices_aml(dsdt); build_q35_pci0_int(dsdt); @@ -1374,7 +1434,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, * the PCI0._CRS. Add mmconfig to the set so it will be excluded * too. */ - if (acpi_get_mcfg(&mcfg)) { + if (mcfg_valid) { crs_range_insert(crs_range_set.mem_ranges, mcfg.base, mcfg.base + mcfg.size - 1); } diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index d3145bf014..3963b73520 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -775,6 +775,7 @@ static const VMStateDescription vmstate_ich9_lpc = { static Property ich9_lpc_properties[] = { DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), + DEFINE_PROP_BOOL("smm-compat", ICH9LPCState, pm.smm_compat, false), DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, ICH9_LPC_SMI_F_BROADCAST_BIT, true), DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features, diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 5db9b1706c..05d084f698 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -190,7 +190,7 @@ static void via_pm_realize(PCIDevice *dev, Error **errp) acpi_pm_tmr_init(&s->ar, pm_tmr_timer, &s->io); acpi_pm1_evt_init(&s->ar, pm_tmr_timer, &s->io); - acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2); + acpi_pm1_cnt_init(&s->ar, &s->io, false, false, 2, false); } typedef struct via_pm_init_info { diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 5150f295e8..439f823b19 100644 --- a/hw/net/virtio-net.c +++ b/hw/net/virtio-net.c @@ -855,19 +855,19 @@ static void failover_add_primary(VirtIONet *n, Error **errp) id = failover_find_primary_device_id(n); if (!id) { + error_setg(errp, "Primary device not found"); + error_append_hint(errp, "Virtio-net failover will not work. Make " + "sure primary device has parameter" + " failover_pair_id=%s\n", n->netclient_name); return; } opts = qemu_opts_find(qemu_find_opts("device"), id); - if (opts) { - dev = qdev_device_add(opts, &err); - if (err) { - qemu_opts_del(opts); - } + g_assert(opts); /* cannot be NULL because id was found using opts list */ + dev = qdev_device_add(opts, &err); + if (err) { + qemu_opts_del(opts); } else { - error_setg(errp, "Primary device not found"); - error_append_hint(errp, "Virtio-net failover will not work. Make " - "sure primary device has parameter" - " failover_pair_id=<virtio-net-id>\n"); + object_unref(OBJECT(dev)); } error_propagate(errp, err); } diff --git a/hw/pci-host/gpex-acpi.c b/hw/pci-host/gpex-acpi.c index 446912d771..0f01f13a6e 100644 --- a/hw/pci-host/gpex-acpi.c +++ b/hw/pci-host/gpex-acpi.c @@ -175,6 +175,7 @@ void acpi_dsdt_add_gpex(Aml *scope, struct GPEXConfig *cfg) aml_append(dev, aml_name_decl("_BBN", aml_int(bus_num))); aml_append(dev, aml_name_decl("_UID", aml_int(bus_num))); aml_append(dev, aml_name_decl("_STR", aml_unicode("pxb Device"))); + aml_append(dev, aml_name_decl("_CCA", aml_int(1))); if (numa_node != NUMA_NODE_UNASSIGNED) { aml_append(dev, aml_name_decl("_PXM", aml_int(numa_node))); } diff --git a/hw/pci/pci.c b/hw/pci/pci.c index a9ebef8a35..fa97a671d1 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2127,10 +2127,8 @@ static void pci_qdev_realize(DeviceState *qdev, Error **errp) pci_qdev_unrealize(DEVICE(pci_dev)); return; } - if (!(pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) - && (PCI_FUNC(pci_dev->devfn) == 0)) { - qdev->allow_unplug_during_migration = true; - } else { + if ((pci_dev->cap_present & QEMU_PCI_CAP_MULTIFUNCTION) + || (PCI_FUNC(pci_dev->devfn) != 0)) { error_setg(errp, "failover: primary device must be in its own " "PCI slot"); pci_qdev_unrealize(DEVICE(pci_dev)); diff --git a/hw/pci/pcie.c b/hw/pci/pcie.c index d4010cf8f3..a733e2fb87 100644 --- a/hw/pci/pcie.c +++ b/hw/pci/pcie.c @@ -75,11 +75,6 @@ pcie_cap_v1_fill(PCIDevice *dev, uint8_t port, uint8_t type, uint8_t version) QEMU_PCI_EXP_LNKSTA_NLW(QEMU_PCI_EXP_LNK_X1) | QEMU_PCI_EXP_LNKSTA_CLS(QEMU_PCI_EXP_LNK_2_5GT)); - if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { - pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, - PCI_EXP_LNKSTA_DLLLA); - } - /* We changed link status bits over time, and changing them across * migrations is generally fine as hardware changes them too. * Let's not bother checking. @@ -125,8 +120,7 @@ static void pcie_cap_fill_slot_lnk(PCIDevice *dev) */ pci_long_test_and_set_mask(exp_cap + PCI_EXP_LNKCAP, PCI_EXP_LNKCAP_DLLLARC); - pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, - PCI_EXP_LNKSTA_DLLLA); + /* the PCI_EXP_LNKSTA_DLLLA will be set in the hotplug function */ /* * Target Link Speed defaults to the highest link speed supported by @@ -427,6 +421,7 @@ void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, PCIDevice *hotplug_pdev = PCI_DEVICE(hotplug_dev); uint8_t *exp_cap = hotplug_pdev->config + hotplug_pdev->exp.exp_cap; PCIDevice *pci_dev = PCI_DEVICE(dev); + uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); /* Don't send event when device is enabled during qemu machine creation: * it is present on boot, no hotplug event is necessary. We do send an @@ -434,7 +429,8 @@ void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, if (!dev->hotplugged) { pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_PDS); - if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { + if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || + (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, PCI_EXP_LNKSTA_DLLLA); } @@ -448,7 +444,8 @@ void pcie_cap_slot_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, if (pci_get_function_0(pci_dev)) { pci_word_test_and_set_mask(exp_cap + PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_PDS); - if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { + if (pci_dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || + (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { pci_word_test_and_set_mask(exp_cap + PCI_EXP_LNKSTA, PCI_EXP_LNKSTA_DLLLA); } @@ -640,6 +637,7 @@ void pcie_cap_slot_write_config(PCIDevice *dev, uint32_t pos = dev->exp.exp_cap; uint8_t *exp_cap = dev->config + pos; uint16_t sltsta = pci_get_word(exp_cap + PCI_EXP_SLTSTA); + uint32_t lnkcap = pci_get_long(exp_cap + PCI_EXP_LNKCAP); if (ranges_overlap(addr, len, pos + PCI_EXP_SLTSTA, 2)) { /* @@ -695,7 +693,8 @@ void pcie_cap_slot_write_config(PCIDevice *dev, pci_word_test_and_clear_mask(exp_cap + PCI_EXP_SLTSTA, PCI_EXP_SLTSTA_PDS); - if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA) { + if (dev->cap_present & QEMU_PCIE_LNKSTA_DLLLA || + (lnkcap & PCI_EXP_LNKCAP_DLLLARC)) { pci_word_test_and_clear_mask(exp_cap + PCI_EXP_LNKSTA, PCI_EXP_LNKSTA_DLLLA); } diff --git a/include/hw/acpi/acpi.h b/include/hw/acpi/acpi.h index 22b0b65bb2..9e8a76f2e2 100644 --- a/include/hw/acpi/acpi.h +++ b/include/hw/acpi/acpi.h @@ -128,6 +128,7 @@ struct ACPIPM1CNT { MemoryRegion io; uint16_t cnt; uint8_t s4_val; + bool acpi_only; }; struct ACPIGPE { @@ -163,7 +164,8 @@ void acpi_pm1_evt_init(ACPIREGS *ar, acpi_update_sci_fn update_sci, /* PM1a_CNT: piix and ich9 don't implement PM1b CNT. */ void acpi_pm1_cnt_init(ACPIREGS *ar, MemoryRegion *parent, - bool disable_s3, bool disable_s4, uint8_t s4_val); + bool disable_s3, bool disable_s4, uint8_t s4_val, + bool acpi_only); void acpi_pm1_cnt_update(ACPIREGS *ar, bool sci_enable, bool sci_disable); void acpi_pm1_cnt_reset(ACPIREGS *ar); diff --git a/include/hw/acpi/ich9.h b/include/hw/acpi/ich9.h index 54571c77e0..df519e40b5 100644 --- a/include/hw/acpi/ich9.h +++ b/include/hw/acpi/ich9.h @@ -59,6 +59,7 @@ typedef struct ICH9LPCPMRegs { uint8_t disable_s4; uint8_t s4_val; uint8_t smm_enabled; + bool smm_compat; bool enable_tco; TCOIORegs tco_regs; } ICH9LPCPMRegs; diff --git a/meson.build b/meson.build index d38620d3be..07bc23129a 100644 --- a/meson.build +++ b/meson.build @@ -2517,6 +2517,24 @@ endif summary_info += {'strip binaries': get_option('strip')} summary_info += {'sparse': sparse.found() ? sparse.full_path() : false} summary_info += {'mingw32 support': targetos == 'windows'} + +# snarf the cross-compilation information for tests +foreach target: target_dirs + tcg_mak = meson.current_build_dir() / 'tests/tcg' / 'config-' + target + '.mak' + if fs.exists(tcg_mak) + config_cross_tcg = keyval.load(tcg_mak) + target = config_cross_tcg['TARGET_NAME'] + compiler = '' + if 'DOCKER_CROSS_CC_GUEST' in config_cross_tcg + summary_info += {target + ' tests': config_cross_tcg['DOCKER_CROSS_CC_GUEST'] + + ' via ' + config_cross_tcg['DOCKER_IMAGE']} + elif 'CROSS_CC_GUEST' in config_cross_tcg + summary_info += {target + ' tests' + : config_cross_tcg['CROSS_CC_GUEST'] } + endif + endif +endforeach + summary(summary_info, bool_yn: true, section: 'Compilation') # Targets and accelerators diff --git a/scripts/checkpatch.pl b/scripts/checkpatch.pl index 7f194c842b..8f7053ec9b 100755 --- a/scripts/checkpatch.pl +++ b/scripts/checkpatch.pl @@ -1530,7 +1530,9 @@ sub process { ($line =~ /^(?:new|deleted) file mode\s*\d+\s*$/ || $line =~ /^rename (?:from|to) [\w\/\.\-]+\s*$/ || ($line =~ /\{\s*([\w\/\.\-]*)\s*\=\>\s*([\w\/\.\-]*)\s*\}/ && - (defined($1) || defined($2))))) { + (defined($1) || defined($2)))) && + !(($realfile ne '') && + ($realfile eq $acpi_testexpected))) { $reported_maintainer_file = 1; WARN("added, moved or deleted file(s), does MAINTAINERS need updating?\n" . $herecurr); } diff --git a/scripts/fix-multiline-comments.sh b/scripts/fix-multiline-comments.sh index 93f9b10669..c15a041272 100755 --- a/scripts/fix-multiline-comments.sh +++ b/scripts/fix-multiline-comments.sh @@ -1,6 +1,6 @@ #! /bin/sh # -# Fix multiline comments to match CODING_STYLE +# Fix multiline comments to match docs/devel/style.rst # # Copyright (C) 2018 Red Hat, Inc. # diff --git a/target/cris/helper.c b/target/cris/helper.c index 7e3bb58fe1..911867f3b4 100644 --- a/target/cris/helper.c +++ b/target/cris/helper.c @@ -275,10 +275,10 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) struct cris_mmu_result res; int miss; - miss = cris_mmu_translate(&res, &cpu->env, addr, 0, 0, 1); + miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_DATA_LOAD, 0, 1); /* If D TLB misses, try I TLB. */ if (miss) { - miss = cris_mmu_translate(&res, &cpu->env, addr, 2, 0, 1); + miss = cris_mmu_translate(&res, &cpu->env, addr, MMU_INST_FETCH, 0, 1); } if (!miss) { diff --git a/target/cris/mmu.c b/target/cris/mmu.c index a279b7f1b6..b574ec6e5b 100644 --- a/target/cris/mmu.c +++ b/target/cris/mmu.c @@ -129,10 +129,10 @@ static void dump_tlb(CPUCRISState *env, int mmu) } #endif -/* rw 0 = read, 1 = write, 2 = exec. */ static int cris_mmu_translate_page(struct cris_mmu_result *res, - CPUCRISState *env, uint32_t vaddr, - int rw, int usermode, int debug) + CPUCRISState *env, uint32_t vaddr, + MMUAccessType access_type, + int usermode, int debug) { unsigned int vpage; unsigned int idx; @@ -151,16 +151,16 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, r_cfg = env->sregs[SFR_RW_MM_CFG]; pid = env->pregs[PR_PID] & 0xff; - switch (rw) { - case 2: + switch (access_type) { + case MMU_INST_FETCH: rwcause = CRIS_MMU_ERR_EXEC; mmu = 0; break; - case 1: + case MMU_DATA_STORE: rwcause = CRIS_MMU_ERR_WRITE; break; default: - case 0: + case MMU_DATA_LOAD: rwcause = CRIS_MMU_ERR_READ; break; } @@ -219,13 +219,13 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, vaddr, lo, env->pc)); match = 0; res->bf_vec = vect_base + 2; - } else if (rw == 1 && cfg_w && !tlb_w) { + } else if (access_type == MMU_DATA_STORE && cfg_w && !tlb_w) { D(printf("tlb: write protected %x lo=%x pc=%x\n", vaddr, lo, env->pc)); match = 0; /* write accesses never go through the I mmu. */ res->bf_vec = vect_base + 3; - } else if (rw == 2 && cfg_x && !tlb_x) { + } else if (access_type == MMU_INST_FETCH && cfg_x && !tlb_x) { D(printf("tlb: exec protected %x lo=%x pc=%x\n", vaddr, lo, env->pc)); match = 0; @@ -272,9 +272,9 @@ static int cris_mmu_translate_page(struct cris_mmu_result *res, D(printf("refill vaddr=%x pc=%x\n", vaddr, env->pc)); } - D(printf("%s rw=%d mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x" + D(printf("%s access=%u mtch=%d pc=%x va=%x vpn=%x tlbvpn=%x pfn=%x pid=%x" " %x cause=%x sel=%x sp=%x %x %x\n", - __func__, rw, match, env->pc, + __func__, access_type, match, env->pc, vaddr, vpage, tlb_vpn, tlb_pfn, tlb_pid, pid, @@ -319,8 +319,8 @@ void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid) } int cris_mmu_translate(struct cris_mmu_result *res, - CPUCRISState *env, uint32_t vaddr, - int rw, int mmu_idx, int debug) + CPUCRISState *env, uint32_t vaddr, + MMUAccessType access_type, int mmu_idx, int debug) { int seg; int miss = 0; @@ -329,8 +329,7 @@ int cris_mmu_translate(struct cris_mmu_result *res, old_srs = env->pregs[PR_SRS]; - /* rw == 2 means exec, map the access to the insn mmu. */ - env->pregs[PR_SRS] = rw == 2 ? 1 : 2; + env->pregs[PR_SRS] = access_type == MMU_INST_FETCH ? 1 : 2; if (!cris_mmu_enabled(env->sregs[SFR_RW_GC_CFG])) { res->phy = vaddr; @@ -347,7 +346,7 @@ int cris_mmu_translate(struct cris_mmu_result *res, res->phy = base | (0x0fffffff & vaddr); res->prot = PAGE_BITS; } else { - miss = cris_mmu_translate_page(res, env, vaddr, rw, + miss = cris_mmu_translate_page(res, env, vaddr, access_type, is_user, debug); } done: diff --git a/target/cris/mmu.h b/target/cris/mmu.h index 9ab1642b96..d57386ec6c 100644 --- a/target/cris/mmu.h +++ b/target/cris/mmu.h @@ -17,6 +17,6 @@ void cris_mmu_init(CPUCRISState *env); void cris_mmu_flush_pid(CPUCRISState *env, uint32_t pid); int cris_mmu_translate(struct cris_mmu_result *res, CPUCRISState *env, uint32_t vaddr, - int rw, int mmu_idx, int debug); + MMUAccessType access_type, int mmu_idx, int debug); #endif diff --git a/target/cris/translate.c b/target/cris/translate.c index 65c168c0c7..6dd5a267a6 100644 --- a/target/cris/translate.c +++ b/target/cris/translate.c @@ -172,14 +172,20 @@ static int preg_sizes[] = { tcg_gen_ld_tl(tn, cpu_env, offsetof(CPUCRISState, member)) #define t_gen_mov_env_TN(member, tn) \ tcg_gen_st_tl(tn, cpu_env, offsetof(CPUCRISState, member)) +#define t_gen_movi_env_TN(member, c) \ + do { \ + TCGv tc = tcg_const_tl(c); \ + t_gen_mov_env_TN(member, tc); \ + tcg_temp_free(tc); \ + } while (0) static inline void t_gen_mov_TN_preg(TCGv tn, int r) { assert(r >= 0 && r <= 15); if (r == PR_BZ || r == PR_WZ || r == PR_DZ) { - tcg_gen_mov_tl(tn, tcg_const_tl(0)); + tcg_gen_movi_tl(tn, 0); } else if (r == PR_VR) { - tcg_gen_mov_tl(tn, tcg_const_tl(32)); + tcg_gen_movi_tl(tn, 32); } else { tcg_gen_mov_tl(tn, cpu_PR[r]); } @@ -256,7 +262,7 @@ static int cris_fetch(CPUCRISState *env, DisasContext *dc, uint32_t addr, static void cris_lock_irq(DisasContext *dc) { dc->clear_locked_irq = 0; - t_gen_mov_env_TN(locked_irq, tcg_const_tl(1)); + t_gen_movi_env_TN(locked_irq, 1); } static inline void t_gen_raise_exception(uint32_t index) @@ -885,8 +891,7 @@ static void gen_tst_cc (DisasContext *dc, TCGv cc, int cond) case CC_EQ: if ((arith_opt || move_opt) && dc->cc_x_uptodate != (2 | X_FLAG)) { - tcg_gen_setcond_tl(TCG_COND_EQ, cc, - cc_result, tcg_const_tl(0)); + tcg_gen_setcondi_tl(TCG_COND_EQ, cc, cc_result, 0); } else { cris_evaluate_flags(dc); tcg_gen_andi_tl(cc, @@ -1330,14 +1335,17 @@ static int dec_addoq(CPUCRISState *env, DisasContext *dc) } static int dec_addq(CPUCRISState *env, DisasContext *dc) { + TCGv c; LOG_DIS("addq %u, $r%u\n", dc->op1, dc->op2); dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(dc->op1); cris_alu(dc, CC_OP_ADD, - cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4); + cpu_R[dc->op2], cpu_R[dc->op2], c, 4); + tcg_temp_free(c); return 2; } static int dec_moveq(CPUCRISState *env, DisasContext *dc) @@ -1353,62 +1361,77 @@ static int dec_moveq(CPUCRISState *env, DisasContext *dc) } static int dec_subq(CPUCRISState *env, DisasContext *dc) { + TCGv c; dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); LOG_DIS("subq %u, $r%u\n", dc->op1, dc->op2); cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(dc->op1); cris_alu(dc, CC_OP_SUB, - cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(dc->op1), 4); + cpu_R[dc->op2], cpu_R[dc->op2], c, 4); + tcg_temp_free(c); return 2; } static int dec_cmpq(CPUCRISState *env, DisasContext *dc) { uint32_t imm; + TCGv c; dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); imm = sign_extend(dc->op1, 5); LOG_DIS("cmpq %d, $r%d\n", imm, dc->op2); cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(imm); cris_alu(dc, CC_OP_CMP, - cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); + cpu_R[dc->op2], cpu_R[dc->op2], c, 4); + tcg_temp_free(c); return 2; } static int dec_andq(CPUCRISState *env, DisasContext *dc) { uint32_t imm; + TCGv c; dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); imm = sign_extend(dc->op1, 5); LOG_DIS("andq %d, $r%d\n", imm, dc->op2); cris_cc_mask(dc, CC_MASK_NZ); + c = tcg_const_tl(imm); cris_alu(dc, CC_OP_AND, - cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); + cpu_R[dc->op2], cpu_R[dc->op2], c, 4); + tcg_temp_free(c); return 2; } static int dec_orq(CPUCRISState *env, DisasContext *dc) { uint32_t imm; + TCGv c; dc->op1 = EXTRACT_FIELD(dc->ir, 0, 5); imm = sign_extend(dc->op1, 5); LOG_DIS("orq %d, $r%d\n", imm, dc->op2); cris_cc_mask(dc, CC_MASK_NZ); + c = tcg_const_tl(imm); cris_alu(dc, CC_OP_OR, - cpu_R[dc->op2], cpu_R[dc->op2], tcg_const_tl(imm), 4); + cpu_R[dc->op2], cpu_R[dc->op2], c, 4); + tcg_temp_free(c); return 2; } static int dec_btstq(CPUCRISState *env, DisasContext *dc) { + TCGv c; dc->op1 = EXTRACT_FIELD(dc->ir, 0, 4); LOG_DIS("btstq %u, $r%d\n", dc->op1, dc->op2); cris_cc_mask(dc, CC_MASK_NZ); + c = tcg_const_tl(dc->op1); cris_evaluate_flags(dc); - gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], - tcg_const_tl(dc->op1), cpu_PR[PR_CCS]); + gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->op2], + c, cpu_PR[PR_CCS]); + tcg_temp_free(c); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->op2], cpu_R[dc->op2], cpu_R[dc->op2], 4); cris_update_cc_op(dc, CC_OP_FLAGS, 4); @@ -1558,7 +1581,7 @@ static int dec_lsl_r(CPUCRISState *env, DisasContext *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); tcg_gen_andi_tl(t[1], t[1], 63); cris_alu(dc, CC_OP_LSL, cpu_R[dc->op2], t[0], t[1], size); - cris_alu_alloc_temps(dc, size, t); + cris_alu_free_temps(dc, size, t); return 2; } @@ -1624,7 +1647,7 @@ static int dec_mulu_r(CPUCRISState *env, DisasContext *dc) dec_prep_alu_r(dc, dc->op1, dc->op2, size, 0, t[0], t[1]); cris_alu(dc, CC_OP_MULU, cpu_R[dc->op2], t[0], t[1], 4); - cris_alu_alloc_temps(dc, size, t); + cris_alu_free_temps(dc, size, t); return 2; } @@ -1806,7 +1829,7 @@ static int dec_addi_r(CPUCRISState *env, DisasContext *dc) memsize_char(memsize_zz(dc)), dc->op2, dc->op1); cris_cc_mask(dc, 0); t0 = tcg_temp_new(); - tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); + tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize); tcg_gen_add_tl(cpu_R[dc->op1], cpu_R[dc->op1], t0); tcg_temp_free(t0); return 2; @@ -1819,7 +1842,7 @@ static int dec_addi_acr(CPUCRISState *env, DisasContext *dc) memsize_char(memsize_zz(dc)), dc->op2, dc->op1); cris_cc_mask(dc, 0); t0 = tcg_temp_new(); - tcg_gen_shl_tl(t0, cpu_R[dc->op2], tcg_const_tl(dc->zzsize)); + tcg_gen_shli_tl(t0, cpu_R[dc->op2], dc->zzsize); tcg_gen_add_tl(cpu_R[R_ACR], cpu_R[dc->op1], t0); tcg_temp_free(t0); return 2; @@ -2051,18 +2074,26 @@ static int dec_setclrf(CPUCRISState *env, DisasContext *dc) static int dec_move_rs(CPUCRISState *env, DisasContext *dc) { + TCGv c2, c1; LOG_DIS("move $r%u, $s%u\n", dc->op1, dc->op2); + c1 = tcg_const_tl(dc->op1); + c2 = tcg_const_tl(dc->op2); cris_cc_mask(dc, 0); - gen_helper_movl_sreg_reg(cpu_env, tcg_const_tl(dc->op2), - tcg_const_tl(dc->op1)); + gen_helper_movl_sreg_reg(cpu_env, c2, c1); + tcg_temp_free(c1); + tcg_temp_free(c2); return 2; } static int dec_move_sr(CPUCRISState *env, DisasContext *dc) { + TCGv c2, c1; LOG_DIS("move $s%u, $r%u\n", dc->op2, dc->op1); + c1 = tcg_const_tl(dc->op1); + c2 = tcg_const_tl(dc->op2); cris_cc_mask(dc, 0); - gen_helper_movl_reg_sreg(cpu_env, tcg_const_tl(dc->op1), - tcg_const_tl(dc->op2)); + gen_helper_movl_reg_sreg(cpu_env, c1, c2); + tcg_temp_free(c1); + tcg_temp_free(c2); return 2; } @@ -2345,7 +2376,7 @@ static int dec_cmp_m(CPUCRISState *env, DisasContext *dc) static int dec_test_m(CPUCRISState *env, DisasContext *dc) { - TCGv t[2]; + TCGv t[2], c; int memsize = memsize_zz(dc); int insn_len; LOG_DIS("test.%c [$r%u%s] op2=%x\n", @@ -2360,8 +2391,10 @@ static int dec_test_m(CPUCRISState *env, DisasContext *dc) cris_cc_mask(dc, CC_MASK_NZ); tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); + c = tcg_const_tl(0); cris_alu(dc, CC_OP_CMP, - cpu_R[dc->op2], t[1], tcg_const_tl(0), memsize_zz(dc)); + cpu_R[dc->op2], t[1], c, memsize_zz(dc)); + tcg_temp_free(c); do_postinc(dc, memsize); cris_alu_m_free_temps(t); return insn_len; @@ -2713,6 +2746,7 @@ static int dec_jump_p(CPUCRISState *env, DisasContext *dc) /* Jump and save. */ static int dec_jas_r(CPUCRISState *env, DisasContext *dc) { + TCGv c; LOG_DIS("jas $r%u, $p%u\n", dc->op1, dc->op2); cris_cc_mask(dc, 0); /* Store the return address in Pd. */ @@ -2720,7 +2754,9 @@ static int dec_jas_r(CPUCRISState *env, DisasContext *dc) if (dc->op2 > 15) { abort(); } - t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4)); + c = tcg_const_tl(dc->pc + 4); + t_gen_mov_preg_TN(dc, dc->op2, c); + tcg_temp_free(c); cris_prepare_jmp(dc, JMP_INDIRECT); return 2; @@ -2729,13 +2765,16 @@ static int dec_jas_r(CPUCRISState *env, DisasContext *dc) static int dec_jas_im(CPUCRISState *env, DisasContext *dc) { uint32_t imm; + TCGv c; imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); LOG_DIS("jas 0x%x\n", imm); cris_cc_mask(dc, 0); + c = tcg_const_tl(dc->pc + 8); /* Store the return address in Pd. */ - t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); + t_gen_mov_preg_TN(dc, dc->op2, c); + tcg_temp_free(c); dc->jmp_pc = imm; cris_prepare_jmp(dc, JMP_DIRECT); @@ -2745,13 +2784,16 @@ static int dec_jas_im(CPUCRISState *env, DisasContext *dc) static int dec_jasc_im(CPUCRISState *env, DisasContext *dc) { uint32_t imm; + TCGv c; imm = cris_fetch(env, dc, dc->pc + 2, 4, 0); LOG_DIS("jasc 0x%x\n", imm); cris_cc_mask(dc, 0); + c = tcg_const_tl(dc->pc + 8 + 4); /* Store the return address in Pd. */ - t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8 + 4)); + t_gen_mov_preg_TN(dc, dc->op2, c); + tcg_temp_free(c); dc->jmp_pc = imm; cris_prepare_jmp(dc, JMP_DIRECT); @@ -2760,11 +2802,14 @@ static int dec_jasc_im(CPUCRISState *env, DisasContext *dc) static int dec_jasc_r(CPUCRISState *env, DisasContext *dc) { + TCGv c; LOG_DIS("jasc_r $r%u, $p%u\n", dc->op1, dc->op2); cris_cc_mask(dc, 0); /* Store the return address in Pd. */ tcg_gen_mov_tl(env_btarget, cpu_R[dc->op1]); - t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 4 + 4)); + c = tcg_const_tl(dc->pc + 4 + 4); + t_gen_mov_preg_TN(dc, dc->op2, c); + tcg_temp_free(c); cris_prepare_jmp(dc, JMP_INDIRECT); return 2; } @@ -2789,13 +2834,16 @@ static int dec_bcc_im(CPUCRISState *env, DisasContext *dc) static int dec_bas_im(CPUCRISState *env, DisasContext *dc) { int32_t simm; + TCGv c; simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); LOG_DIS("bas 0x%x, $p%u\n", dc->pc + simm, dc->op2); cris_cc_mask(dc, 0); + c = tcg_const_tl(dc->pc + 8); /* Store the return address in Pd. */ - t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 8)); + t_gen_mov_preg_TN(dc, dc->op2, c); + tcg_temp_free(c); dc->jmp_pc = dc->pc + simm; cris_prepare_jmp(dc, JMP_DIRECT); @@ -2805,12 +2853,15 @@ static int dec_bas_im(CPUCRISState *env, DisasContext *dc) static int dec_basc_im(CPUCRISState *env, DisasContext *dc) { int32_t simm; + TCGv c; simm = cris_fetch(env, dc, dc->pc + 2, 4, 0); LOG_DIS("basc 0x%x, $p%u\n", dc->pc + simm, dc->op2); cris_cc_mask(dc, 0); + c = tcg_const_tl(dc->pc + 12); /* Store the return address in Pd. */ - t_gen_mov_preg_TN(dc, dc->op2, tcg_const_tl(dc->pc + 12)); + t_gen_mov_preg_TN(dc, dc->op2, c); + tcg_temp_free(c); dc->jmp_pc = dc->pc + simm; cris_prepare_jmp(dc, JMP_DIRECT); @@ -2851,8 +2902,7 @@ static int dec_rfe_etc(CPUCRISState *env, DisasContext *dc) tcg_gen_movi_tl(env_pc, dc->pc + 2); /* Breaks start at 16 in the exception vector. */ - t_gen_mov_env_TN(trap_vector, - tcg_const_tl(dc->op1 + 16)); + t_gen_movi_env_TN(trap_vector, dc->op1 + 16); t_gen_raise_exception(EXCP_BREAK); dc->is_jmp = DISAS_UPDATE; break; @@ -3026,7 +3076,7 @@ static unsigned int crisv32_decoder(CPUCRISState *env, DisasContext *dc) tcg_gen_brcondi_tl(TCG_COND_NE, cpu_PR[PR_SPC], dc->pc, l1); /* We treat SPC as a break with an odd trap vector. */ cris_evaluate_flags(dc); - t_gen_mov_env_TN(trap_vector, tcg_const_tl(3)); + t_gen_movi_env_TN(trap_vector, 3); tcg_gen_movi_tl(env_pc, dc->pc + insn_len); tcg_gen_movi_tl(cpu_PR[PR_SPC], dc->pc + insn_len); t_gen_raise_exception(EXCP_BREAK); @@ -3170,7 +3220,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) dc->delayed_branch--; if (dc->delayed_branch == 0) { if (tb->flags & 7) { - t_gen_mov_env_TN(dslot, tcg_const_tl(0)); + t_gen_movi_env_TN(dslot, 0); } if (dc->cpustate_changed || !dc->flagx_known || (dc->flags_x != (tb->flags & X_FLAG))) { @@ -3179,7 +3229,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) if (dc->clear_locked_irq) { dc->clear_locked_irq = 0; - t_gen_mov_env_TN(locked_irq, tcg_const_tl(0)); + t_gen_movi_env_TN(locked_irq, 0); } if (dc->jmp == JMP_DIRECT_CC) { @@ -3200,7 +3250,9 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) dc->is_jmp = DISAS_TB_JUMP; dc->jmp = JMP_NOJMP; } else { - t_gen_cc_jmp(env_btarget, tcg_const_tl(dc->pc)); + TCGv c = tcg_const_tl(dc->pc); + t_gen_cc_jmp(env_btarget, c); + tcg_temp_free(c); dc->is_jmp = DISAS_JUMP; } break; @@ -3219,7 +3271,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) && num_insns < max_insns); if (dc->clear_locked_irq) { - t_gen_mov_env_TN(locked_irq, tcg_const_tl(0)); + t_gen_movi_env_TN(locked_irq, 0); } npc = dc->pc; @@ -3234,7 +3286,7 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) /* Broken branch+delayslot sequence. */ if (dc->delayed_branch == 1) { /* Set env->dslot to the size of the branch insn. */ - t_gen_mov_env_TN(dslot, tcg_const_tl(dc->pc - dc->ppc)); + t_gen_movi_env_TN(dslot, dc->pc - dc->ppc); cris_store_direct_jmp(dc); } diff --git a/target/cris/translate_v10.c.inc b/target/cris/translate_v10.c.inc index 86d78a82aa..f7cd67be37 100644 --- a/target/cris/translate_v10.c.inc +++ b/target/cris/translate_v10.c.inc @@ -228,6 +228,7 @@ static unsigned int dec10_quick_imm(DisasContext *dc) { int32_t imm, simm; int op; + TCGv c; /* sign extend. */ imm = dc->ir & ((1 << 6) - 1); @@ -254,29 +255,37 @@ static unsigned int dec10_quick_imm(DisasContext *dc) LOG_DIS("moveq %d, $r%d\n", simm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(simm); cris_alu(dc, CC_OP_MOVE, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(simm), 4); + cpu_R[dc->dst], c, 4); + tcg_temp_free(c); break; case CRISV10_QIMM_CMPQ: LOG_DIS("cmpq %d, $r%d\n", simm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(simm); cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(simm), 4); + cpu_R[dc->dst], c, 4); + tcg_temp_free(c); break; case CRISV10_QIMM_ADDQ: LOG_DIS("addq %d, $r%d\n", imm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(imm); cris_alu(dc, CC_OP_ADD, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(imm), 4); + cpu_R[dc->dst], c, 4); + tcg_temp_free(c); break; case CRISV10_QIMM_ANDQ: LOG_DIS("andq %d, $r%d\n", simm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(simm); cris_alu(dc, CC_OP_AND, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(simm), 4); + cpu_R[dc->dst], c, 4); + tcg_temp_free(c); break; case CRISV10_QIMM_ASHQ: LOG_DIS("ashq %d, $r%d\n", simm, dc->dst); @@ -284,15 +293,17 @@ static unsigned int dec10_quick_imm(DisasContext *dc) cris_cc_mask(dc, CC_MASK_NZVC); op = imm & (1 << 5); imm &= 0x1f; + c = tcg_const_tl(imm); if (op) { cris_alu(dc, CC_OP_ASR, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(imm), 4); + cpu_R[dc->dst], c, 4); } else { /* BTST */ cris_update_cc_op(dc, CC_OP_FLAGS, 4); gen_helper_btst(cpu_PR[PR_CCS], cpu_env, cpu_R[dc->dst], - tcg_const_tl(imm), cpu_PR[PR_CCS]); + c, cpu_PR[PR_CCS]); } + tcg_temp_free(c); break; case CRISV10_QIMM_LSHQ: LOG_DIS("lshq %d, $r%d\n", simm, dc->dst); @@ -303,22 +314,28 @@ static unsigned int dec10_quick_imm(DisasContext *dc) } imm &= 0x1f; cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(imm); cris_alu(dc, op, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(imm), 4); + cpu_R[dc->dst], c, 4); + tcg_temp_free(c); break; case CRISV10_QIMM_SUBQ: LOG_DIS("subq %d, $r%d\n", imm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(imm); cris_alu(dc, CC_OP_SUB, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(imm), 4); + cpu_R[dc->dst], c, 4); + tcg_temp_free(c); break; case CRISV10_QIMM_ORQ: LOG_DIS("andq %d, $r%d\n", simm, dc->dst); cris_cc_mask(dc, CC_MASK_NZVC); + c = tcg_const_tl(simm); cris_alu(dc, CC_OP_OR, cpu_R[dc->dst], - cpu_R[dc->dst], tcg_const_tl(simm), 4); + cpu_R[dc->dst], c, 4); + tcg_temp_free(c); break; case CRISV10_QIMM_BCC_R0: @@ -760,7 +777,6 @@ static unsigned int dec10_ind_move_m_r(CPUCRISState *env, DisasContext *dc, tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch = 1; - return insn_len; } tcg_temp_free(t); @@ -777,6 +793,7 @@ static unsigned int dec10_ind_move_r_m(DisasContext *dc, unsigned int size) crisv10_prepare_memaddr(dc, addr, size); gen_store_v10(dc, addr, cpu_R[dc->dst], size); insn_len += crisv10_post_memaddr(dc, size); + tcg_temp_free(addr); return insn_len; } @@ -796,11 +813,10 @@ static unsigned int dec10_ind_move_m_pr(CPUCRISState *env, DisasContext *dc) tcg_gen_mov_tl(env_btarget, t); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch = 1; - return insn_len; + } else { + tcg_gen_mov_tl(cpu_PR[rd], t); + dc->cpustate_changed = 1; } - - tcg_gen_mov_tl(cpu_PR[rd], t); - dc->cpustate_changed = 1; tcg_temp_free(addr); tcg_temp_free(t); return insn_len; @@ -824,8 +840,8 @@ static unsigned int dec10_ind_move_pr_m(DisasContext *dc) } else { gen_store_v10(dc, addr, cpu_PR[dc->dst], size); } - t0 = tcg_temp_new(); insn_len += crisv10_post_memaddr(dc, size); + tcg_temp_free(addr); cris_lock_irq(dc); return insn_len; @@ -927,7 +943,6 @@ static int dec10_ind_bound(CPUCRISState *env, DisasContext *dc, tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch = 1; - return insn_len; } tcg_temp_free(t); @@ -953,7 +968,6 @@ static int dec10_alux_m(CPUCRISState *env, DisasContext *dc, int op) tcg_gen_mov_tl(env_btarget, cpu_R[dc->dst]); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch = 1; - return insn_len; } tcg_temp_free(t); @@ -1020,7 +1034,7 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) unsigned int size = dec10_size(dc->size); uint32_t imm; int32_t simm; - TCGv t[2]; + TCGv t[2], c; if (dc->size != 3) { switch (dc->opcode) { @@ -1041,8 +1055,10 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) cris_alu_m_alloc_temps(t); insn_len += dec10_prep_move_m(env, dc, 0, size, t[0]); tcg_gen_andi_tl(cpu_PR[PR_CCS], cpu_PR[PR_CCS], ~3); + c = tcg_const_tl(0); cris_alu(dc, CC_OP_CMP, cpu_R[dc->dst], - t[0], tcg_const_tl(0), size); + t[0], c, size); + tcg_temp_free(c); cris_alu_m_free_temps(t); break; case CRISV10_IND_ADD: @@ -1138,7 +1154,9 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) if (dc->mode == CRISV10_MODE_AUTOINC) insn_len += size; - t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); + c = tcg_const_tl(dc->pc + insn_len); + t_gen_mov_preg_TN(dc, dc->dst, c); + tcg_temp_free(c); dc->jmp_pc = imm; cris_prepare_jmp(dc, JMP_DIRECT); dc->delayed_branch--; /* v10 has no dslot here. */ @@ -1147,7 +1165,9 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) LOG_DIS("break %d\n", dc->src); cris_evaluate_flags(dc); tcg_gen_movi_tl(env_pc, dc->pc + 2); - t_gen_mov_env_TN(trap_vector, tcg_const_tl(dc->src + 2)); + c = tcg_const_tl(dc->src + 2); + t_gen_mov_env_TN(trap_vector, c); + tcg_temp_free(c); t_gen_raise_exception(EXCP_BREAK); dc->is_jmp = DISAS_UPDATE; return insn_len; @@ -1155,7 +1175,9 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) LOG_DIS("%d: jump.%d %d r%d r%d\n", __LINE__, size, dc->opcode, dc->src, dc->dst); t[0] = tcg_temp_new(); - t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); + c = tcg_const_tl(dc->pc + insn_len); + t_gen_mov_preg_TN(dc, dc->dst, c); + tcg_temp_free(c); crisv10_prepare_memaddr(dc, t[0], size); gen_load(dc, env_btarget, t[0], 4, 0); insn_len += crisv10_post_memaddr(dc, size); @@ -1178,7 +1200,9 @@ static unsigned int dec10_ind(CPUCRISState *env, DisasContext *dc) LOG_DIS("jmp pc=%x opcode=%d r%d r%d\n", dc->pc, dc->opcode, dc->dst, dc->src); tcg_gen_mov_tl(env_btarget, cpu_R[dc->src]); - t_gen_mov_preg_TN(dc, dc->dst, tcg_const_tl(dc->pc + insn_len)); + c = tcg_const_tl(dc->pc + insn_len); + t_gen_mov_preg_TN(dc, dc->dst, c); + tcg_temp_free(c); cris_prepare_jmp(dc, JMP_INDIRECT); dc->delayed_branch--; /* v10 has no dslot here. */ break; diff --git a/tests/acceptance/virtio-gpu.py b/tests/acceptance/virtio-gpu.py index ab1a4c1a71..ab18cddbb7 100644 --- a/tests/acceptance/virtio-gpu.py +++ b/tests/acceptance/virtio-gpu.py @@ -85,7 +85,12 @@ class VirtioGPUx86(Test): "-append", kernel_command_line, ) - self.vm.launch() + try: + self.vm.launch() + except: + # TODO: probably fails because we are missing the VirGL features + self.cancel("VirGL not enabled?") + self.wait_for_console_pattern("as init process") exec_command_and_wait_for_pattern( self, "/usr/sbin/modprobe virtio_gpu", "" diff --git a/tests/data/acpi/pc/DSDT.nohpet b/tests/data/acpi/pc/DSDT.nohpet new file mode 100644 index 0000000000..d7d21be070 --- /dev/null +++ b/tests/data/acpi/pc/DSDT.nohpet Binary files differdiff --git a/tests/data/acpi/pc/FACP.nosmm b/tests/data/acpi/pc/FACP.nosmm new file mode 100644 index 0000000000..7e19550748 --- /dev/null +++ b/tests/data/acpi/pc/FACP.nosmm Binary files differdiff --git a/tests/data/acpi/q35/DSDT b/tests/data/acpi/q35/DSDT index 008a3d7d0f..cccf92f046 100644 --- a/tests/data/acpi/q35/DSDT +++ b/tests/data/acpi/q35/DSDT Binary files differdiff --git a/tests/data/acpi/q35/DSDT.acpihmat b/tests/data/acpi/q35/DSDT.acpihmat index 2723b69008..b3c1dd6bc4 100644 --- a/tests/data/acpi/q35/DSDT.acpihmat +++ b/tests/data/acpi/q35/DSDT.acpihmat Binary files differdiff --git a/tests/data/acpi/q35/DSDT.bridge b/tests/data/acpi/q35/DSDT.bridge index 8671145557..eb5d27d95b 100644 --- a/tests/data/acpi/q35/DSDT.bridge +++ b/tests/data/acpi/q35/DSDT.bridge Binary files differdiff --git a/tests/data/acpi/q35/DSDT.cphp b/tests/data/acpi/q35/DSDT.cphp index 42b7819ea8..e55d12990c 100644 --- a/tests/data/acpi/q35/DSDT.cphp +++ b/tests/data/acpi/q35/DSDT.cphp Binary files differdiff --git a/tests/data/acpi/q35/DSDT.dimmpxm b/tests/data/acpi/q35/DSDT.dimmpxm index 7c3526d967..95901f94c0 100644 --- a/tests/data/acpi/q35/DSDT.dimmpxm +++ b/tests/data/acpi/q35/DSDT.dimmpxm Binary files differdiff --git a/tests/data/acpi/q35/DSDT.ipmibt b/tests/data/acpi/q35/DSDT.ipmibt index 8d3ccc3e75..ce07e9f152 100644 --- a/tests/data/acpi/q35/DSDT.ipmibt +++ b/tests/data/acpi/q35/DSDT.ipmibt Binary files differdiff --git a/tests/data/acpi/q35/DSDT.memhp b/tests/data/acpi/q35/DSDT.memhp index f1c545d94b..7acf6243f0 100644 --- a/tests/data/acpi/q35/DSDT.memhp +++ b/tests/data/acpi/q35/DSDT.memhp Binary files differdiff --git a/tests/data/acpi/q35/DSDT.mmio64 b/tests/data/acpi/q35/DSDT.mmio64 index 4fb285f2ef..77d46369e4 100644 --- a/tests/data/acpi/q35/DSDT.mmio64 +++ b/tests/data/acpi/q35/DSDT.mmio64 Binary files differdiff --git a/tests/data/acpi/q35/DSDT.nohpet b/tests/data/acpi/q35/DSDT.nohpet new file mode 100644 index 0000000000..0b10128e42 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.nohpet Binary files differdiff --git a/tests/data/acpi/q35/DSDT.numamem b/tests/data/acpi/q35/DSDT.numamem index dd9dc9d025..e4c4582e7f 100644 --- a/tests/data/acpi/q35/DSDT.numamem +++ b/tests/data/acpi/q35/DSDT.numamem Binary files differdiff --git a/tests/data/acpi/q35/DSDT.tis b/tests/data/acpi/q35/DSDT.tis index b8e3803402..15a26a14e4 100644 --- a/tests/data/acpi/q35/DSDT.tis +++ b/tests/data/acpi/q35/DSDT.tis Binary files differdiff --git a/tests/data/acpi/q35/FACP.nosmm b/tests/data/acpi/q35/FACP.nosmm new file mode 100644 index 0000000000..6a9aa5f370 --- /dev/null +++ b/tests/data/acpi/q35/FACP.nosmm Binary files differdiff --git a/tests/data/acpi/virt/DSDT.pxb b/tests/data/acpi/virt/DSDT.pxb index eaa507b4bb..46b9c4cad5 100644 --- a/tests/data/acpi/virt/DSDT.pxb +++ b/tests/data/acpi/virt/DSDT.pxb Binary files differdiff --git a/tests/docker/dockerfiles/fedora-cris-cross.docker b/tests/docker/dockerfiles/fedora-cris-cross.docker index 09e7e449f9..1dfff6e0b9 100644 --- a/tests/docker/dockerfiles/fedora-cris-cross.docker +++ b/tests/docker/dockerfiles/fedora-cris-cross.docker @@ -2,7 +2,7 @@ # Cross compiler for cris system tests # -FROM fedora:30 +FROM fedora:33 ENV PACKAGES gcc-cris-linux-gnu RUN dnf install -y $PACKAGES RUN rpm -q $PACKAGES | sort > /packages.txt diff --git a/tests/docker/dockerfiles/fedora-i386-cross.docker b/tests/docker/dockerfiles/fedora-i386-cross.docker index a6e411291b..966072c08e 100644 --- a/tests/docker/dockerfiles/fedora-i386-cross.docker +++ b/tests/docker/dockerfiles/fedora-i386-cross.docker @@ -1,4 +1,4 @@ -FROM fedora:31 +FROM fedora:33 ENV PACKAGES \ bzip2 \ diffutils \ diff --git a/tests/docker/dockerfiles/fedora-win32-cross.docker b/tests/docker/dockerfiles/fedora-win32-cross.docker index 087df598a0..81b5659e9c 100644 --- a/tests/docker/dockerfiles/fedora-win32-cross.docker +++ b/tests/docker/dockerfiles/fedora-win32-cross.docker @@ -1,4 +1,4 @@ -FROM fedora:32 +FROM fedora:33 # Please keep this list sorted alphabetically ENV PACKAGES \ diff --git a/tests/docker/dockerfiles/fedora-win64-cross.docker b/tests/docker/dockerfiles/fedora-win64-cross.docker index d5d2f5f00d..bcb428e724 100644 --- a/tests/docker/dockerfiles/fedora-win64-cross.docker +++ b/tests/docker/dockerfiles/fedora-win64-cross.docker @@ -1,4 +1,4 @@ -FROM fedora:32 +FROM fedora:33 # Please keep this list sorted alphabetically ENV PACKAGES \ diff --git a/tests/docker/dockerfiles/fedora.docker b/tests/docker/dockerfiles/fedora.docker index 0d7602abbe..915fdc1845 100644 --- a/tests/docker/dockerfiles/fedora.docker +++ b/tests/docker/dockerfiles/fedora.docker @@ -1,4 +1,4 @@ -FROM fedora:32 +FROM fedora:33 # Please keep this list sorted alphabetically ENV PACKAGES \ diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index 77053975aa..e020c83d2a 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -973,6 +973,50 @@ static void test_acpi_piix4_tcg_memhp(void) free_test_data(&data); } +static void test_acpi_piix4_tcg_nosmm(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".nosmm"; + test_acpi_one("-machine smm=off", &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_smm_compat(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".smm-compat"; + test_acpi_one("-global PIIX4_PM.smm-compat=on", &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_smm_compat_nosmm(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".smm-compat-nosmm"; + test_acpi_one("-global PIIX4_PM.smm-compat=on -machine smm=off", &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_nohpet(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".nohpet"; + test_acpi_one("-no-hpet", &data); + free_test_data(&data); +} + static void test_acpi_q35_tcg_numamem(void) { test_data data; @@ -985,6 +1029,50 @@ static void test_acpi_q35_tcg_numamem(void) free_test_data(&data); } +static void test_acpi_q35_tcg_nosmm(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".nosmm"; + test_acpi_one("-machine smm=off", &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_smm_compat(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".smm-compat"; + test_acpi_one("-global ICH9-LPC.smm-compat=on", &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_smm_compat_nosmm(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".smm-compat-nosmm"; + test_acpi_one("-global ICH9-LPC.smm-compat=on -machine smm=off", &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_nohpet(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".nohpet"; + test_acpi_one("-no-hpet", &data); + free_test_data(&data); +} + static void test_acpi_piix4_tcg_numamem(void) { test_data data; @@ -1445,6 +1533,18 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/memhp", test_acpi_q35_tcg_memhp); qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_tcg_numamem); qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem); + qtest_add_func("acpi/piix4/nosmm", test_acpi_piix4_tcg_nosmm); + qtest_add_func("acpi/piix4/smm-compat", + test_acpi_piix4_tcg_smm_compat); + qtest_add_func("acpi/piix4/smm-compat-nosmm", + test_acpi_piix4_tcg_smm_compat_nosmm); + qtest_add_func("acpi/piix4/nohpet", test_acpi_piix4_tcg_nohpet); + qtest_add_func("acpi/q35/nosmm", test_acpi_q35_tcg_nosmm); + qtest_add_func("acpi/q35/smm-compat", + test_acpi_q35_tcg_smm_compat); + qtest_add_func("acpi/q35/smm-compat-nosmm", + test_acpi_q35_tcg_smm_compat_nosmm); + qtest_add_func("acpi/q35/nohpet", test_acpi_q35_tcg_nohpet); qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm); qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm); qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat); diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh index 551c02f469..36b8a73a54 100755 --- a/tests/tcg/configure.sh +++ b/tests/tcg/configure.sh @@ -263,11 +263,3 @@ for target in $target_list; do echo "DOCKER_CROSS_CC_GUEST=$container_cross_cc" >> $config_target_mak fi done - -# report container support state -echo "cross containers $container" - -if test -n "$enabled_cross_compilers"; then - echo - echo "NOTE: guest cross-compilers enabled:$enabled_cross_compilers" -fi |