diff options
| -rw-r--r-- | target/ppc/cpu.h | 13 | ||||
| -rw-r--r-- | target/ppc/excp_helper.c | 31 | ||||
| -rw-r--r-- | target/ppc/helper.h | 1 | ||||
| -rw-r--r-- | target/ppc/insn32.decode | 5 | ||||
| -rw-r--r-- | target/ppc/translate.c | 2 | ||||
| -rw-r--r-- | target/ppc/translate/branch-impl.c.inc | 33 |
6 files changed, 85 insertions, 0 deletions
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h index b0473526ce..fc66c3561d 100644 --- a/target/ppc/cpu.h +++ b/target/ppc/cpu.h @@ -392,6 +392,19 @@ typedef enum { /* PMU uses CTRL_RUN to sample PM_RUN_INST_CMPL */ #define CTRL_RUN PPC_BIT(63) +/* EBB/BESCR bits */ +/* Global Enable */ +#define BESCR_GE PPC_BIT(0) +/* External Event-based Exception Enable */ +#define BESCR_EE PPC_BIT(30) +/* Performance Monitor Event-based Exception Enable */ +#define BESCR_PME PPC_BIT(31) +/* External Event-based Exception Occurred */ +#define BESCR_EEO PPC_BIT(62) +/* Performance Monitor Event-based Exception Occurred */ +#define BESCR_PMEO PPC_BIT(63) +#define BESCR_INVALID PPC_BITMASK(32, 33) + /* LPCR bits */ #define LPCR_VPM0 PPC_BIT(0) #define LPCR_VPM1 PPC_BIT(1) diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c index 6ba0840e99..f90e616aac 100644 --- a/target/ppc/excp_helper.c +++ b/target/ppc/excp_helper.c @@ -1228,6 +1228,37 @@ void helper_hrfid(CPUPPCState *env) } #endif +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) +void helper_rfebb(CPUPPCState *env, target_ulong s) +{ + target_ulong msr = env->msr; + + /* + * Handling of BESCR bits 32:33 according to PowerISA v3.1: + * + * "If BESCR 32:33 != 0b00 the instruction is treated as if + * the instruction form were invalid." + */ + if (env->spr[SPR_BESCR] & BESCR_INVALID) { + raise_exception_err(env, POWERPC_EXCP_PROGRAM, + POWERPC_EXCP_INVAL | POWERPC_EXCP_INVAL_INVAL); + } + + env->nip = env->spr[SPR_EBBRR]; + + /* Switching to 32-bit ? Crop the nip */ + if (!msr_is_64bit(env, msr)) { + env->nip = (uint32_t)env->spr[SPR_EBBRR]; + } + + if (s) { + env->spr[SPR_BESCR] |= BESCR_GE; + } else { + env->spr[SPR_BESCR] &= ~BESCR_GE; + } +} +#endif + /*****************************************************************************/ /* Embedded PowerPC specific helpers */ void helper_40x_rfci(CPUPPCState *env) diff --git a/target/ppc/helper.h b/target/ppc/helper.h index 13d8305a08..fb6cac38b4 100644 --- a/target/ppc/helper.h +++ b/target/ppc/helper.h @@ -18,6 +18,7 @@ DEF_HELPER_2(pminsn, void, env, i32) DEF_HELPER_1(rfid, void, env) DEF_HELPER_1(rfscv, void, env) DEF_HELPER_1(hrfid, void, env) +DEF_HELPER_2(rfebb, void, env, tl) DEF_HELPER_2(store_lpcr, void, env, tl) DEF_HELPER_2(store_pcr, void, env, tl) DEF_HELPER_2(store_mmcr0, void, env, tl) diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 8bdc059a4c..2a9c91a423 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -470,3 +470,8 @@ XSMINJDP 111100 ..... ..... ..... 10011000 ... @XX3 ## VSX Binary Floating-Point Convert Instructions XSCVQPDP 111111 ..... 10100 ..... 1101000100 . @X_tb_rc + +### rfebb +&XL_s s:uint8_t +@XL_s ......-------------- s:1 .......... - &XL_s +RFEBB 010011-------------- . 0010010010 - @XL_s diff --git a/target/ppc/translate.c b/target/ppc/translate.c index 68fbbf67ec..114456148c 100644 --- a/target/ppc/translate.c +++ b/target/ppc/translate.c @@ -7461,6 +7461,8 @@ static bool resolve_PLS_D(DisasContext *ctx, arg_D *d, arg_PLS_D *a) #include "translate/spe-impl.c.inc" +#include "translate/branch-impl.c.inc" + /* Handles lfdp, lxsd, lxssp */ static void gen_dform39(DisasContext *ctx) { diff --git a/target/ppc/translate/branch-impl.c.inc b/target/ppc/translate/branch-impl.c.inc new file mode 100644 index 0000000000..29cfa11854 --- /dev/null +++ b/target/ppc/translate/branch-impl.c.inc @@ -0,0 +1,33 @@ +/* + * Power ISA decode for branch instructions + * + * Copyright IBM Corp. 2021 + * + * Authors: + * Daniel Henrique Barboza <danielhb413@gmail.com> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#if defined(TARGET_PPC64) && !defined(CONFIG_USER_ONLY) + +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + REQUIRE_INSNS_FLAGS2(ctx, ISA207S); + + gen_icount_io_start(ctx); + gen_update_cfar(ctx, ctx->cia); + gen_helper_rfebb(cpu_env, cpu_gpr[arg->s]); + + ctx->base.is_jmp = DISAS_CHAIN; + + return true; +} +#else +static bool trans_RFEBB(DisasContext *ctx, arg_XL_s *arg) +{ + gen_invalid(ctx); + return true; +} +#endif |