diff options
| -rw-r--r-- | MAINTAINERS | 6 | ||||
| -rw-r--r-- | docs/system/deprecated.rst | 23 | ||||
| -rw-r--r-- | hw/mips/boston.c | 10 | ||||
| -rw-r--r-- | target/mips/cp0_helper.c | 27 | ||||
| -rw-r--r-- | target/mips/cpu.h | 1 |
5 files changed, 54 insertions, 13 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index f6da5990aa..3f4b6e29df 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -227,7 +227,7 @@ R: Aleksandar Rikalo <aleksandar.rikalo@syrmia.com> S: Odd Fixes F: target/mips/ F: default-configs/*mips* -F: disas/*mips* +F: disas/mips.c F: docs/system/cpu-models-mips.rst.inc F: hw/intc/mips_gic.c F: hw/mips/ @@ -240,6 +240,10 @@ F: include/hw/timer/mips_gictimer.h F: tests/tcg/mips/ K: ^Subject:.*(?i)mips +MIPS TCG CPUs (nanoMIPS ISA) +S: Orphan +F: disas/nanomips.* + Moxie TCG CPUs M: Anthony Green <green@moxielogic.com> S: Maintained diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index 8c1dc7645d..bbaae0d97c 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -310,6 +310,13 @@ to build binaries for it. ``Icelake-Client`` CPU Models are deprecated. Use ``Icelake-Server`` CPU Models instead. +MIPS ``I7200`` CPU Model (since 5.2) +'''''''''''''''''''''''''''''''''''' + +The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated +(the ISA has never been upstreamed to a compiler toolchain). Therefore +this CPU is also deprecated. + System emulator devices ----------------------- @@ -407,6 +414,13 @@ The ``ppc64abi32`` architecture has a number of issues which regularly trip up our CI testing and is suspected to be quite broken. For that reason the maintainers strongly suspect no one actually uses it. +MIPS ``I7200`` CPU (since 5.2) +'''''''''''''''''''''''''''''' + +The ``I7200`` guest CPU relies on the nanoMIPS ISA, which is deprecated +(the ISA has never been upstreamed to a compiler toolchain). Therefore +this CPU is also deprecated. + Related binaries ---------------- @@ -471,6 +485,15 @@ versions, aliases will point to newer CPU model versions depending on the machine type, so management software must resolve CPU model aliases before starting a virtual machine. +Guest Emulator ISAs +------------------- + +nanoMIPS ISA +'''''''''''' + +The ``nanoMIPS`` ISA has never been upstreamed to any compiler toolchain. +As it is hard to generate binaries for it, declare it deprecated. + Recently removed features ========================= diff --git a/hw/mips/boston.c b/hw/mips/boston.c index 3356d7a681..3d40867dc4 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -349,11 +349,9 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, MachineState *machine = s->mach; const char *cmdline; int err; - void *fdt; - size_t fdt_sz, ram_low_sz, ram_high_sz; - - fdt_sz = fdt_totalsize(fdt_orig) * 2; - fdt = g_malloc0(fdt_sz); + size_t ram_low_sz, ram_high_sz; + size_t fdt_sz = fdt_totalsize(fdt_orig) * 2; + g_autofree void *fdt = g_malloc0(fdt_sz); err = fdt_open_into(fdt_orig, fdt, fdt_sz); if (err) { @@ -380,7 +378,7 @@ static const void *boston_fdt_filter(void *opaque, const void *fdt_orig, s->fdt_base = *load_addr; - return fdt; + return g_steal_pointer(&fdt); } static const void *boston_kernel_filter(void *opaque, const void *kernel, diff --git a/target/mips/cp0_helper.c b/target/mips/cp0_helper.c index 709cc9a7e3..a1b5140cca 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/cp0_helper.c @@ -892,13 +892,28 @@ void helper_mtc0_memorymapid(CPUMIPSState *env, target_ulong arg1) void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask) { - uint64_t mask = arg1 >> (TARGET_PAGE_BITS + 1); - if (!(env->insn_flags & ISA_MIPS32R6) || (arg1 == ~0) || - (mask == 0x0000 || mask == 0x0003 || mask == 0x000F || - mask == 0x003F || mask == 0x00FF || mask == 0x03FF || - mask == 0x0FFF || mask == 0x3FFF || mask == 0xFFFF)) { - env->CP0_PageMask = arg1 & (0x1FFFFFFF & (TARGET_PAGE_MASK << 1)); + uint32_t mask; + int maskbits; + + /* Don't care MASKX as we don't support 1KB page */ + mask = extract32((uint32_t)arg1, CP0PM_MASK, 16); + maskbits = cto32(mask); + + /* Ensure no more set bit after first zero */ + if ((mask >> maskbits) != 0) { + goto invalid; } + /* We don't support VTLB entry smaller than target page */ + if ((maskbits + 12) < TARGET_PAGE_BITS) { + goto invalid; + } + env->CP0_PageMask = mask << CP0PM_MASK; + + return; + +invalid: + /* When invalid, set to default target page size. */ + env->CP0_PageMask = (~TARGET_PAGE_MASK >> 12) << CP0PM_MASK; } void helper_mtc0_pagemask(CPUMIPSState *env, target_ulong arg1) diff --git a/target/mips/cpu.h b/target/mips/cpu.h index d41579d44a..23f8c6f96c 100644 --- a/target/mips/cpu.h +++ b/target/mips/cpu.h @@ -619,6 +619,7 @@ struct CPUMIPSState { * CP0 Register 5 */ int32_t CP0_PageMask; +#define CP0PM_MASK 13 int32_t CP0_PageGrain_rw_bitmask; int32_t CP0_PageGrain; #define CP0PG_RIE 31 |