diff options
| -rw-r--r-- | target/i386/cpu.c | 47 | ||||
| -rw-r--r-- | target/i386/cpu.h | 1 |
2 files changed, 38 insertions, 10 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index 92d21ce64c..ca85603077 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -250,23 +250,17 @@ static const CPUCaches legacy_intel_cpuid2_cache_info; /* Encode cache info for CPUID[2] */ static void encode_cache_cpuid2(X86CPU *cpu, + const CPUCaches *caches, uint32_t *eax, uint32_t *ebx, uint32_t *ecx, uint32_t *edx) { CPUX86State *env = &cpu->env; - const CPUCaches *caches; int l1d, l1i, l2, l3; bool unmatched = false; *eax = 1; /* Number of CPUID[EAX=2] calls required */ *ebx = *ecx = *edx = 0; - if (env->enable_legacy_cpuid2_cache) { - caches = &legacy_intel_cpuid2_cache_info; - } else { - caches = &env->cache_info_cpuid4; - } - l1d = cpuid2_cache_descriptor(caches->l1d_cache, &unmatched); l1i = cpuid2_cache_descriptor(caches->l1i_cache, &unmatched); l2 = cpuid2_cache_descriptor(caches->l2_cache, &unmatched); @@ -7472,8 +7466,37 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *ebx |= threads_per_pkg << 16; } break; - case 2: - /* cache info: needed for Pentium Pro compatibility */ + case 2: { /* cache info: needed for Pentium Pro compatibility */ + const CPUCaches *caches; + + if (env->enable_legacy_cpuid2_cache) { + caches = &legacy_intel_cpuid2_cache_info; + } else if (env->enable_legacy_vendor_cache) { + caches = &legacy_intel_cache_info; + } else { + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * This condition covers the following cases (with + * enable_legacy_vendor_cache=false): + * - When CPU model has its own cache model and doesn't use legacy + * cache model (legacy_model=off). Then cache_info_amd and + * cache_info_cpuid4 are the same. + * + * - For v10.1 and newer machines, when CPU model uses legacy cache + * model. Non-AMD CPUs use cache_info_cpuid4 like before and AMD + * CPU will use cache_info_amd. But this doesn't matter for AMD + * CPU, because this leaf encodes all-0 for AMD whatever its cache + * model is. + */ + if (IS_AMD_CPU(env)) { + caches = &env->cache_info_amd; + } else { + caches = &env->cache_info_cpuid4; + } + } + if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, 0, eax, ebx, ecx, edx); break; @@ -7481,8 +7504,9 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, *eax = *ebx = *ecx = *edx = 0; break; } - encode_cache_cpuid2(cpu, eax, ebx, ecx, edx); + encode_cache_cpuid2(cpu, caches, eax, ebx, ecx, edx); break; + } case 4: /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { @@ -8988,6 +9012,9 @@ static void x86_cpu_realizefn(DeviceState *dev, Error **errp) env->enable_legacy_cpuid2_cache = true; } + if (!cpu->vendor_cpuid_only_v2) { + env->enable_legacy_vendor_cache = true; + } env->cache_info_cpuid4 = legacy_intel_cache_info; env->cache_info_amd = legacy_amd_cache_info; } diff --git a/target/i386/cpu.h b/target/i386/cpu.h index d88481ba8e..20499a82a5 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -2079,6 +2079,7 @@ typedef struct CPUArchState { */ CPUCaches cache_info_cpuid4, cache_info_amd; bool enable_legacy_cpuid2_cache; + bool enable_legacy_vendor_cache; /* MTRRs */ uint64_t mtrr_fixed[11]; |