diff options
| -rw-r--r-- | hw/arm/boot.c | 5 | ||||
| -rw-r--r-- | hw/ssi/xilinx_spi.c | 1 | ||||
| -rw-r--r-- | target/arm/gdbstub64.c | 7 | ||||
| -rw-r--r-- | target/arm/internals.h | 15 | ||||
| -rw-r--r-- | target/arm/tcg/pauth_helper.c | 18 | ||||
| -rw-r--r-- | target/arm/tcg/translate.c | 6 |
6 files changed, 27 insertions, 25 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index 50e5141116..54f6a3e0b3 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -689,7 +689,10 @@ int arm_load_dtb(hwaddr addr, const struct arm_boot_info *binfo, qemu_register_reset_nosnapshotload(qemu_fdt_randomize_seeds, rom_ptr_for_as(as, addr, size)); - g_free(fdt); + if (fdt != ms->fdt) { + g_free(ms->fdt); + ms->fdt = fdt; + } return size; diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 552927622f..d4de2e7aab 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -156,6 +156,7 @@ static void xlx_spi_do_reset(XilinxSPI *s) txfifo_reset(s); s->regs[R_SPISSR] = ~0; + s->regs[R_SPICR] = R_SPICR_MTI; xlx_spi_update_irq(s); xlx_spi_update_cs(s); } diff --git a/target/arm/gdbstub64.c b/target/arm/gdbstub64.c index ec1e07f139..c1f7e8c934 100644 --- a/target/arm/gdbstub64.c +++ b/target/arm/gdbstub64.c @@ -230,8 +230,11 @@ int aarch64_gdb_get_pauth_reg(CPUARMState *env, GByteArray *buf, int reg) { bool is_data = !(reg & 1); bool is_high = reg & 2; - uint64_t mask = pauth_ptr_mask(env, -is_high, is_data); - return gdb_get_reg64(buf, mask); + ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); + ARMVAParameters param; + + param = aa64_va_parameters(env, -is_high, mmu_idx, is_data); + return gdb_get_reg64(buf, pauth_ptr_mask(param)); } default: return 0; diff --git a/target/arm/internals.h b/target/arm/internals.h index 673519a24a..c2c70d5918 100644 --- a/target/arm/internals.h +++ b/target/arm/internals.h @@ -1391,13 +1391,18 @@ bool arm_generate_debug_exceptions(CPUARMState *env); /** * pauth_ptr_mask: - * @env: cpu context - * @ptr: selects between TTBR0 and TTBR1 - * @data: selects between TBI and TBID + * @param: parameters defining the MMU setup * - * Return a mask of the bits of @ptr that contain the authentication code. + * Return a mask of the address bits that contain the authentication code, + * given the MMU config defined by @param. */ -uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data); +static inline uint64_t pauth_ptr_mask(ARMVAParameters param) +{ + int bot_pac_bit = 64 - param.tsz; + int top_pac_bit = 64 - 8 * param.tbi; + + return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); +} /* Add the cpreg definitions for debug related system registers */ void define_debug_regs(ARMCPU *cpu); diff --git a/target/arm/tcg/pauth_helper.c b/target/arm/tcg/pauth_helper.c index 20f347332d..de067fa716 100644 --- a/target/arm/tcg/pauth_helper.c +++ b/target/arm/tcg/pauth_helper.c @@ -339,17 +339,9 @@ static uint64_t pauth_addpac(CPUARMState *env, uint64_t ptr, uint64_t modifier, return pac | ext | ptr; } -static uint64_t pauth_ptr_mask_internal(ARMVAParameters param) -{ - int bot_pac_bit = 64 - param.tsz; - int top_pac_bit = 64 - 8 * param.tbi; - - return MAKE_64BIT_MASK(bot_pac_bit, top_pac_bit - bot_pac_bit); -} - static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) { - uint64_t mask = pauth_ptr_mask_internal(param); + uint64_t mask = pauth_ptr_mask(param); /* Note that bit 55 is used whether or not the regime has 2 ranges. */ if (extract64(ptr, 55, 1)) { @@ -359,14 +351,6 @@ static uint64_t pauth_original_ptr(uint64_t ptr, ARMVAParameters param) } } -uint64_t pauth_ptr_mask(CPUARMState *env, uint64_t ptr, bool data) -{ - ARMMMUIdx mmu_idx = arm_stage1_mmu_idx(env); - ARMVAParameters param = aa64_va_parameters(env, ptr, mmu_idx, data); - - return pauth_ptr_mask_internal(param); -} - static uint64_t pauth_auth(CPUARMState *env, uint64_t ptr, uint64_t modifier, ARMPACKey *key, bool data, int keynumber) { diff --git a/target/arm/tcg/translate.c b/target/arm/tcg/translate.c index 2cb9368b1b..3c8401e908 100644 --- a/target/arm/tcg/translate.c +++ b/target/arm/tcg/translate.c @@ -4623,6 +4623,12 @@ static void do_coproc_insn(DisasContext *s, int cpnum, int is64, tcg_gen_brcondi_i32(TCG_COND_EQ, t, 0, over.label); gen_exception_insn(s, 0, EXCP_UDEF, syndrome); + /* + * gen_exception_insn() will set is_jmp to DISAS_NORETURN, + * but since we're conditionally branching over it, we want + * to assume continue-to-next-instruction. + */ + s->base.is_jmp = DISAS_NEXT; set_disas_label(s, over); } } |