diff options
36 files changed, 302 insertions, 236 deletions
diff --git a/HACKING b/HACKING index 89a6b3ad44..6654d33249 100644 --- a/HACKING +++ b/HACKING @@ -123,3 +123,23 @@ gcc's printf attribute directive in the prototype. This makes it so gcc's -Wformat and -Wformat-security options can do their jobs and cross-check format strings with the number and types of arguments. + +6. C standard, implementation defined and undefined behaviors + +C code in QEMU should be written to the C99 language specification. A copy +of the final version of the C99 standard with corrigenda TC1, TC2, and TC3 +included, formatted as a draft, can be downloaded from: + http://www.open-std.org/jtc1/sc22/WG14/www/docs/n1256.pdf + +The C language specification defines regions of undefined behavior and +implementation defined behavior (to give compiler authors enough leeway to +produce better code). In general, code in QEMU should follow the language +specification and avoid both undefined and implementation defined +constructs. ("It works fine on the gcc I tested it with" is not a valid +argument...) However there are a few areas where we allow ourselves to +assume certain behaviors because in practice all the platforms we care about +behave in the same way and writing strictly conformant code would be +painful. These are: + * you may assume that integers are 2s complement representation + * you may assume that right shift of a signed integer duplicates + the sign bit (ie it is an arithmetic shift, not a logical shift) diff --git a/configure b/configure index 994f7310b8..44034d66b9 100755 --- a/configure +++ b/configure @@ -2118,7 +2118,7 @@ fi # pixman support probe if test "$pixman" = ""; then - if $pkg_config pixman-1 > /dev/null 2>&1; then + if $pkg_config --atleast-version=0.18.4 pixman-1 > /dev/null 2>&1; then pixman="system" else pixman="internal" @@ -2129,7 +2129,7 @@ if test "$pixman" = "system"; then pixman_libs=`$pkg_config --libs pixman-1 2>/dev/null` else if test ! -d ${source_path}/pixman/pixman; then - echo "ERROR: pixman not present. Your options:" + echo "ERROR: pixman not present (or older than 0.18.4). Your options:" echo " (1) Prefered: Install the pixman devel package (any recent" echo " distro should have packages as Xorg needs pixman too)." echo " (2) Fetch the pixman submodule, using:" diff --git a/exec-all.h b/exec-all.h index 21aacdab50..b18d4ca534 100644 --- a/exec-all.h +++ b/exec-all.h @@ -70,10 +70,6 @@ typedef struct TranslationBlock TranslationBlock; #define OPPARAM_BUF_SIZE (OPC_BUF_SIZE * MAX_OPC_PARAM) -extern target_ulong gen_opc_pc[OPC_BUF_SIZE]; -extern uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; -extern uint16_t gen_opc_icount[OPC_BUF_SIZE]; - #include "qemu-log.h" void gen_intermediate_code(CPUArchState *env, struct TranslationBlock *tb); diff --git a/exec.c b/exec.c index 8435de0bd2..0594b07057 100644 --- a/exec.c +++ b/exec.c @@ -607,6 +607,8 @@ static inline void code_gen_alloc(size_t tb_size) exit(1); } + qemu_madvise(code_gen_buffer, code_gen_buffer_size, QEMU_MADV_HUGEPAGE); + /* Steal room for the prologue at the end of the buffer. This ensures (via the MAX_CODE_GEN_BUFFER_SIZE limits above) that direct branches from TB's to the prologue are going to be in range. It also means diff --git a/hw/acpi_piix4.c b/hw/acpi_piix4.c index 519269a013..dbddde13ab 100644 --- a/hw/acpi_piix4.c +++ b/hw/acpi_piix4.c @@ -438,7 +438,7 @@ static int piix4_pm_initfn(PCIDevice *dev) pci_conf[0x3d] = 0x01; // interrupt pin 1 /* APM */ - apm_init(&s->apm, apm_ctrl_changed, s); + apm_init(dev, &s->apm, apm_ctrl_changed, s); register_ioport_write(ACPI_DBG_IO_ADDR, 4, 4, acpi_dbg_writel, s); diff --git a/hw/apm.c b/hw/apm.c index 2aead52a74..e988ad9939 100644 --- a/hw/apm.c +++ b/hw/apm.c @@ -22,6 +22,7 @@ #include "apm.h" #include "hw.h" +#include "pci.h" //#define DEBUG @@ -35,7 +36,8 @@ #define APM_CNT_IOPORT 0xb2 #define APM_STS_IOPORT 0xb3 -static void apm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) +static void apm_ioport_writeb(void *opaque, hwaddr addr, uint64_t val, + unsigned size) { APMState *apm = opaque; addr &= 1; @@ -51,7 +53,7 @@ static void apm_ioport_writeb(void *opaque, uint32_t addr, uint32_t val) } } -static uint32_t apm_ioport_readb(void *opaque, uint32_t addr) +static uint64_t apm_ioport_readb(void *opaque, hwaddr addr, unsigned size) { APMState *apm = opaque; uint32_t val; @@ -78,12 +80,23 @@ const VMStateDescription vmstate_apm = { } }; -void apm_init(APMState *apm, apm_ctrl_changed_t callback, void *arg) +static const MemoryRegionOps apm_ops = { + .read = apm_ioport_readb, + .write = apm_ioport_writeb, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +void apm_init(PCIDevice *dev, APMState *apm, apm_ctrl_changed_t callback, + void *arg) { apm->callback = callback; apm->arg = arg; /* ioport 0xb2, 0xb3 */ - register_ioport_write(APM_CNT_IOPORT, 2, 1, apm_ioport_writeb, apm); - register_ioport_read(APM_CNT_IOPORT, 2, 1, apm_ioport_readb, apm); + memory_region_init_io(&apm->io, &apm_ops, apm, "apm-io", 2); + memory_region_add_subregion(pci_address_space_io(dev), APM_CNT_IOPORT, + &apm->io); } diff --git a/hw/apm.h b/hw/apm.h index f7c741e327..5431b6d7c8 100644 --- a/hw/apm.h +++ b/hw/apm.h @@ -4,6 +4,7 @@ #include <stdint.h> #include "qemu-common.h" #include "hw.h" +#include "memory.h" typedef void (*apm_ctrl_changed_t)(uint32_t val, void *arg); @@ -13,9 +14,11 @@ typedef struct APMState { apm_ctrl_changed_t callback; void *arg; + MemoryRegion io; } APMState; -void apm_init(APMState *s, apm_ctrl_changed_t callback, void *arg); +void apm_init(PCIDevice *dev, APMState *s, apm_ctrl_changed_t callback, + void *arg); extern const VMStateDescription vmstate_apm; diff --git a/hw/cirrus_vga.c b/hw/cirrus_vga.c index 9bef96e6d7..40efa8a523 100644 --- a/hw/cirrus_vga.c +++ b/hw/cirrus_vga.c @@ -197,6 +197,7 @@ typedef void (*cirrus_fill_t)(struct CirrusVGAState *s, typedef struct CirrusVGAState { VGACommonState vga; + MemoryRegion cirrus_vga_io; MemoryRegion cirrus_linear_io; MemoryRegion cirrus_linear_bitblt_io; MemoryRegion cirrus_mmio_io; @@ -2432,13 +2433,15 @@ static void cirrus_update_memory_access(CirrusVGAState *s) /* I/O ports */ -static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr) +static uint64_t cirrus_vga_ioport_read(void *opaque, hwaddr addr, + unsigned size) { CirrusVGAState *c = opaque; VGACommonState *s = &c->vga; int val, index; qemu_flush_coalesced_mmio_buffer(); + addr += 0x3b0; if (vga_ioport_invalid(s, addr)) { val = 0xff; @@ -2527,13 +2530,15 @@ static uint32_t cirrus_vga_ioport_read(void *opaque, uint32_t addr) return val; } -static void cirrus_vga_ioport_write(void *opaque, uint32_t addr, uint32_t val) +static void cirrus_vga_ioport_write(void *opaque, hwaddr addr, uint64_t val, + unsigned size) { CirrusVGAState *c = opaque; VGACommonState *s = &c->vga; int index; qemu_flush_coalesced_mmio_buffer(); + addr += 0x3b0; /* check port range access depending on color/monochrome mode */ if (vga_ioport_invalid(s, addr)) { @@ -2646,7 +2651,7 @@ static uint64_t cirrus_mmio_read(void *opaque, hwaddr addr, if (addr >= 0x100) { return cirrus_mmio_blt_read(s, addr - 0x100); } else { - return cirrus_vga_ioport_read(s, addr + 0x3c0); + return cirrus_vga_ioport_read(s, addr + 0x10, size); } } @@ -2658,7 +2663,7 @@ static void cirrus_mmio_write(void *opaque, hwaddr addr, if (addr >= 0x100) { cirrus_mmio_blt_write(s, addr - 0x100, val); } else { - cirrus_vga_ioport_write(s, addr + 0x3c0, val); + cirrus_vga_ioport_write(s, addr + 0x10, val, size); } } @@ -2784,8 +2789,19 @@ static const MemoryRegionOps cirrus_linear_io_ops = { }, }; +static const MemoryRegionOps cirrus_vga_io_ops = { + .read = cirrus_vga_ioport_read, + .write = cirrus_vga_ioport_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci, - MemoryRegion *system_memory) + MemoryRegion *system_memory, + MemoryRegion *system_io) { int i; static int inited; @@ -2817,19 +2833,10 @@ static void cirrus_init_common(CirrusVGAState * s, int device_id, int is_pci, s->bustype = CIRRUS_BUSTYPE_ISA; } - register_ioport_write(0x3c0, 16, 1, cirrus_vga_ioport_write, s); - - register_ioport_write(0x3b4, 2, 1, cirrus_vga_ioport_write, s); - register_ioport_write(0x3d4, 2, 1, cirrus_vga_ioport_write, s); - register_ioport_write(0x3ba, 1, 1, cirrus_vga_ioport_write, s); - register_ioport_write(0x3da, 1, 1, cirrus_vga_ioport_write, s); - - register_ioport_read(0x3c0, 16, 1, cirrus_vga_ioport_read, s); - - register_ioport_read(0x3b4, 2, 1, cirrus_vga_ioport_read, s); - register_ioport_read(0x3d4, 2, 1, cirrus_vga_ioport_read, s); - register_ioport_read(0x3ba, 1, 1, cirrus_vga_ioport_read, s); - register_ioport_read(0x3da, 1, 1, cirrus_vga_ioport_read, s); + /* Register ioport 0x3b0 - 0x3df */ + memory_region_init_io(&s->cirrus_vga_io, &cirrus_vga_io_ops, s, + "cirrus-io", 0x30); + memory_region_add_subregion(system_io, 0x3b0, &s->cirrus_vga_io); memory_region_init(&s->low_mem_container, "cirrus-lowmem-container", @@ -2900,7 +2907,7 @@ static int vga_initfn(ISADevice *dev) vga_common_init(s); cirrus_init_common(&d->cirrus_vga, CIRRUS_ID_CLGD5430, 0, - isa_address_space(dev)); + isa_address_space(dev), isa_address_space_io(dev)); s->ds = graphic_console_init(s->update, s->invalidate, s->screen_dump, s->text_update, s); @@ -2948,7 +2955,8 @@ static int pci_cirrus_vga_initfn(PCIDevice *dev) /* setup VGA */ vga_common_init(&s->vga); - cirrus_init_common(s, device_id, 1, pci_address_space(dev)); + cirrus_init_common(s, device_id, 1, pci_address_space(dev), + pci_address_space_io(dev)); s->vga.ds = graphic_console_init(s->vga.update, s->vga.invalidate, s->vga.screen_dump, s->vga.text_update, &s->vga); diff --git a/hw/dma.c b/hw/dma.c index d6aeac2834..c2d7b21562 100644 --- a/hw/dma.c +++ b/hw/dma.c @@ -58,6 +58,8 @@ static struct dma_cont { int dshift; struct dma_regs regs[4]; qemu_irq *cpu_request_exit; + MemoryRegion channel_io; + MemoryRegion cont_io; } dma_controllers[2]; enum { @@ -149,7 +151,7 @@ static inline int getff (struct dma_cont *d) return ff; } -static uint32_t read_chan (void *opaque, uint32_t nport) +static uint64_t read_chan(void *opaque, hwaddr nport, unsigned size) { struct dma_cont *d = opaque; int ichan, nreg, iport, ff, val, dir; @@ -171,7 +173,8 @@ static uint32_t read_chan (void *opaque, uint32_t nport) return (val >> (d->dshift + (ff << 3))) & 0xff; } -static void write_chan (void *opaque, uint32_t nport, uint32_t data) +static void write_chan(void *opaque, hwaddr nport, uint64_t data, + unsigned size) { struct dma_cont *d = opaque; int iport, ichan, nreg; @@ -189,22 +192,23 @@ static void write_chan (void *opaque, uint32_t nport, uint32_t data) } } -static void write_cont (void *opaque, uint32_t nport, uint32_t data) +static void write_cont(void *opaque, hwaddr nport, uint64_t data, + unsigned size) { struct dma_cont *d = opaque; int iport, ichan = 0; iport = (nport >> d->dshift) & 0x0f; switch (iport) { - case 0x08: /* command */ + case 0x01: /* command */ if ((data != 0) && (data & CMD_NOT_SUPPORTED)) { - dolog ("command %#x not supported\n", data); + dolog("command %"PRIx64" not supported\n", data); return; } d->command = data; break; - case 0x09: + case 0x02: ichan = data & 3; if (data & 4) { d->status |= 1 << (ichan + 4); @@ -216,7 +220,7 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data) DMA_run(); break; - case 0x0a: /* single mask */ + case 0x03: /* single mask */ if (data & 4) d->mask |= 1 << (data & 3); else @@ -224,7 +228,7 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data) DMA_run(); break; - case 0x0b: /* mode */ + case 0x04: /* mode */ { ichan = data & 3; #ifdef DEBUG_DMA @@ -243,23 +247,23 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data) break; } - case 0x0c: /* clear flip flop */ + case 0x05: /* clear flip flop */ d->flip_flop = 0; break; - case 0x0d: /* reset */ + case 0x06: /* reset */ d->flip_flop = 0; d->mask = ~0; d->status = 0; d->command = 0; break; - case 0x0e: /* clear mask for all channels */ + case 0x07: /* clear mask for all channels */ d->mask = 0; DMA_run(); break; - case 0x0f: /* write mask for all channels */ + case 0x08: /* write mask for all channels */ d->mask = data; DMA_run(); break; @@ -277,7 +281,7 @@ static void write_cont (void *opaque, uint32_t nport, uint32_t data) #endif } -static uint32_t read_cont (void *opaque, uint32_t nport) +static uint64_t read_cont(void *opaque, hwaddr nport, unsigned size) { struct dma_cont *d = opaque; int iport, val; @@ -463,7 +467,7 @@ void DMA_schedule(int nchan) static void dma_reset(void *opaque) { struct dma_cont *d = opaque; - write_cont (d, (0x0d << d->dshift), 0); + write_cont(d, (0x06 << d->dshift), 0, 1); } static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) @@ -473,38 +477,68 @@ static int dma_phony_handler (void *opaque, int nchan, int dma_pos, int dma_len) return dma_pos; } + +static const MemoryRegionOps channel_io_ops = { + .read = read_chan, + .write = write_chan, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +/* IOport from page_base */ +static const MemoryRegionPortio page_portio_list[] = { + { 0x01, 3, 1, .write = write_page, .read = read_page, }, + { 0x07, 1, 1, .write = write_page, .read = read_page, }, + PORTIO_END_OF_LIST(), +}; + +/* IOport from pageh_base */ +static const MemoryRegionPortio pageh_portio_list[] = { + { 0x01, 3, 1, .write = write_pageh, .read = read_pageh, }, + { 0x07, 3, 1, .write = write_pageh, .read = read_pageh, }, + PORTIO_END_OF_LIST(), +}; + +static const MemoryRegionOps cont_io_ops = { + .read = read_cont, + .write = write_cont, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + /* dshift = 0: 8 bit DMA, 1 = 16 bit DMA */ static void dma_init2(struct dma_cont *d, int base, int dshift, int page_base, int pageh_base, qemu_irq *cpu_request_exit) { - static const int page_port_list[] = { 0x1, 0x2, 0x3, 0x7 }; int i; d->dshift = dshift; d->cpu_request_exit = cpu_request_exit; - for (i = 0; i < 8; i++) { - register_ioport_write (base + (i << dshift), 1, 1, write_chan, d); - register_ioport_read (base + (i << dshift), 1, 1, read_chan, d); - } - for (i = 0; i < ARRAY_SIZE (page_port_list); i++) { - register_ioport_write (page_base + page_port_list[i], 1, 1, - write_page, d); - register_ioport_read (page_base + page_port_list[i], 1, 1, - read_page, d); - if (pageh_base >= 0) { - register_ioport_write (pageh_base + page_port_list[i], 1, 1, - write_pageh, d); - register_ioport_read (pageh_base + page_port_list[i], 1, 1, - read_pageh, d); - } - } - for (i = 0; i < 8; i++) { - register_ioport_write (base + ((i + 8) << dshift), 1, 1, - write_cont, d); - register_ioport_read (base + ((i + 8) << dshift), 1, 1, - read_cont, d); + + memory_region_init_io(&d->channel_io, &channel_io_ops, d, + "dma-chan", 8 << d->dshift); + memory_region_add_subregion(isa_address_space_io(NULL), + base, &d->channel_io); + + isa_register_portio_list(NULL, page_base, page_portio_list, d, + "dma-page"); + if (pageh_base >= 0) { + isa_register_portio_list(NULL, pageh_base, pageh_portio_list, d, + "dma-pageh"); } + + memory_region_init_io(&d->cont_io, &cont_io_ops, d, "dma-cont", + 8 << d->dshift); + memory_region_add_subregion(isa_address_space_io(NULL), + base + (8 << d->dshift), &d->cont_io); + qemu_register_reset(dma_reset, d); dma_reset(d); for (i = 0; i < ARRAY_SIZE (d->regs); ++i) { diff --git a/hw/isa-bus.c b/hw/isa-bus.c index 685fdc0f82..144a88e272 100644 --- a/hw/isa-bus.c +++ b/hw/isa-bus.c @@ -264,4 +264,13 @@ MemoryRegion *isa_address_space(ISADevice *dev) return get_system_memory(); } +MemoryRegion *isa_address_space_io(ISADevice *dev) +{ + if (dev) { + return isa_bus_from_device(dev)->address_space_io; + } + + return isabus->address_space_io; +} + type_init(isabus_register_types) diff --git a/hw/isa.h b/hw/isa.h index f9382e8367..9d719fa3c8 100644 --- a/hw/isa.h +++ b/hw/isa.h @@ -43,6 +43,7 @@ void isa_bus_irqs(ISABus *bus, qemu_irq *irqs); qemu_irq isa_get_irq(ISADevice *dev, int isairq); void isa_init_irq(ISADevice *dev, qemu_irq *p, int isairq); MemoryRegion *isa_address_space(ISADevice *dev); +MemoryRegion *isa_address_space_io(ISADevice *dev); ISADevice *isa_create(ISABus *bus, const char *name); ISADevice *isa_try_create(ISABus *bus, const char *name); ISADevice *isa_create_simple(ISABus *bus, const char *name); diff --git a/hw/lpc_ich9.c b/hw/lpc_ich9.c index 2fc83a496f..7de5427a69 100644 --- a/hw/lpc_ich9.c +++ b/hw/lpc_ich9.c @@ -472,7 +472,7 @@ static int ich9_lpc_initfn(PCIDevice *d) lpc->isa_bus = isa_bus; ich9_cc_init(lpc); - apm_init(&lpc->apm, ich9_apm_ctrl_changed, lpc); + apm_init(d, &lpc->apm, ich9_apm_ctrl_changed, lpc); return 0; } diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c index a95a3c1f11..20b5f1a58c 100644 --- a/hw/mips_mipssim.c +++ b/hw/mips_mipssim.c @@ -217,7 +217,8 @@ mips_mipssim_init(QEMUMachineInitArgs *args) /* A single 16450 sits at offset 0x3f8. It is attached to MIPS CPU INT2, which is interrupt 4. */ if (serial_hds[0]) - serial_init(0x3f8, env->irq[4], 115200, serial_hds[0]); + serial_init(0x3f8, env->irq[4], 115200, serial_hds[0], + get_system_io()); if (nd_table[0].used) /* MIPSnet uses the MIPS CPU INT0, which is interrupt 2. */ diff --git a/hw/pc.c b/hw/pc.c index 2b5bbbfb30..b11e7c4adc 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -98,7 +98,8 @@ void gsi_handler(void *opaque, int n, int level) qemu_set_irq(s->ioapic_irq[n], level); } -static void ioport80_write(void *opaque, uint32_t addr, uint32_t data) +static void ioport80_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) { } @@ -116,7 +117,8 @@ void cpu_set_ferr(CPUX86State *s) qemu_irq_raise(ferr_irq); } -static void ioportF0_write(void *opaque, uint32_t addr, uint32_t data) +static void ioportF0_write(void *opaque, hwaddr addr, uint64_t data, + unsigned size) { qemu_irq_lower(ferr_irq); } @@ -567,6 +569,14 @@ int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) return index; } +static const MemoryRegionPortio bochs_bios_portio_list[] = { + { 0x500, 1, 1, .write = bochs_bios_write, }, /* 0x500 */ + { 0x501, 1, 1, .write = bochs_bios_write, }, /* 0x501 */ + { 0x501, 2, 2, .write = bochs_bios_write, }, /* 0x501 */ + { 0x8900, 1, 1, .write = bochs_bios_write, }, /* 0x8900 */ + PORTIO_END_OF_LIST(), +}; + static void *bochs_bios_init(void) { void *fw_cfg; @@ -574,12 +584,11 @@ static void *bochs_bios_init(void) size_t smbios_len; uint64_t *numa_fw_cfg; int i, j; + PortioList *bochs_bios_port_list = g_new(PortioList, 1); - register_ioport_write(0x8900, 1, 1, bochs_bios_write, NULL); - - register_ioport_write(0x501, 1, 1, bochs_bios_write, NULL); - register_ioport_write(0x501, 1, 2, bochs_bios_write, NULL); - register_ioport_write(0x502, 1, 2, bochs_bios_write, NULL); + portio_list_init(bochs_bios_port_list, bochs_bios_portio_list, + NULL, "bochs-bios"); + portio_list_add(bochs_bios_port_list, get_system_io(), 0x0); fw_cfg = fw_cfg_init(BIOS_CFG_IOPORT, BIOS_CFG_IOPORT + 1, 0, 0); @@ -967,6 +976,24 @@ static void cpu_request_exit(void *opaque, int irq, int level) } } +static const MemoryRegionOps ioport80_io_ops = { + .write = ioport80_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + +static const MemoryRegionOps ioportF0_io_ops = { + .write = ioportF0_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .impl = { + .min_access_size = 1, + .max_access_size = 1, + }, +}; + void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, ISADevice **rtc_state, ISADevice **floppy, @@ -981,10 +1008,14 @@ void pc_basic_device_init(ISABus *isa_bus, qemu_irq *gsi, qemu_irq *a20_line; ISADevice *i8042, *port92, *vmmouse, *pit = NULL; qemu_irq *cpu_exit_irq; + MemoryRegion *ioport80_io = g_new(MemoryRegion, 1); + MemoryRegion *ioportF0_io = g_new(MemoryRegion, 1); - register_ioport_write(0x80, 1, 1, ioport80_write, NULL); + memory_region_init_io(ioport80_io, &ioport80_io_ops, NULL, "ioport80", 1); + memory_region_add_subregion(isa_bus->address_space_io, 0x80, ioport80_io); - register_ioport_write(0xf0, 1, 1, ioportF0_write, NULL); + memory_region_init_io(ioportF0_io, &ioportF0_io_ops, NULL, "ioportF0", 1); + memory_region_add_subregion(isa_bus->address_space_io, 0xf0, ioportF0_io); /* * Check if an HPET shall be created. diff --git a/hw/serial.c b/hw/serial.c index 60283eab91..07a2a11931 100644 --- a/hw/serial.c +++ b/hw/serial.c @@ -718,7 +718,7 @@ const MemoryRegionOps serial_io_ops = { }; SerialState *serial_init(int base, qemu_irq irq, int baudbase, - CharDriverState *chr) + CharDriverState *chr, MemoryRegion *system_io) { SerialState *s; @@ -732,7 +732,7 @@ SerialState *serial_init(int base, qemu_irq irq, int baudbase, vmstate_register(NULL, base, &vmstate_serial, s); memory_region_init_io(&s->io, &serial_io_ops, s, "serial", 8); - memory_region_add_subregion(get_system_io(), base, &s->io); + memory_region_add_subregion(system_io, base, &s->io); return s; } diff --git a/hw/serial.h b/hw/serial.h index f1e3c4aaa7..ed1a5cd43e 100644 --- a/hw/serial.h +++ b/hw/serial.h @@ -89,7 +89,7 @@ void serial_set_frequency(SerialState *s, uint32_t frequency); /* legacy pre qom */ SerialState *serial_init(int base, qemu_irq irq, int baudbase, - CharDriverState *chr); + CharDriverState *chr, MemoryRegion *system_io); SerialState *serial_mm_init(MemoryRegion *address_space, hwaddr base, int it_shift, qemu_irq irq, int baudbase, diff --git a/hw/vt82c686.c b/hw/vt82c686.c index 5d7c00cf4b..7f11dbe782 100644 --- a/hw/vt82c686.c +++ b/hw/vt82c686.c @@ -427,7 +427,7 @@ static int vt82c686b_pm_initfn(PCIDevice *dev) register_ioport_write(s->smb_io_base, 0xf, 1, smb_ioport_writeb, &s->smb); register_ioport_read(s->smb_io_base, 0xf, 1, smb_ioport_readb, &s->smb); - apm_init(&s->apm, NULL, s); + apm_init(dev, &s->apm, NULL, s); acpi_pm_tmr_init(&s->ar, pm_tmr_timer); acpi_pm1_cnt_init(&s->ar); diff --git a/qemu-config.c b/qemu-config.c index 10d1ba4176..aa78fb9ea7 100644 --- a/qemu-config.c +++ b/qemu-config.c @@ -417,54 +417,6 @@ static QemuOptsList qemu_trace_opts = { }, }; -static QemuOptsList qemu_cpudef_opts = { - .name = "cpudef", - .head = QTAILQ_HEAD_INITIALIZER(qemu_cpudef_opts.head), - .desc = { - { - .name = "name", - .type = QEMU_OPT_STRING, - },{ - .name = "level", - .type = QEMU_OPT_NUMBER, - },{ - .name = "vendor", - .type = QEMU_OPT_STRING, - },{ - .name = "family", - .type = QEMU_OPT_NUMBER, - },{ - .name = "model", - .type = QEMU_OPT_NUMBER, - },{ - .name = "stepping", - .type = QEMU_OPT_NUMBER, - },{ - .name = "feature_edx", /* cpuid 0000_0001.edx */ - .type = QEMU_OPT_STRING, - },{ - .name = "feature_ecx", /* cpuid 0000_0001.ecx */ - .type = QEMU_OPT_STRING, - },{ - .name = "extfeature_edx", /* cpuid 8000_0001.edx */ - .type = QEMU_OPT_STRING, - },{ - .name = "extfeature_ecx", /* cpuid 8000_0001.ecx */ - .type = QEMU_OPT_STRING, - },{ - .name = "xlevel", - .type = QEMU_OPT_NUMBER, - },{ - .name = "model_id", - .type = QEMU_OPT_STRING, - },{ - .name = "vendor_override", - .type = QEMU_OPT_NUMBER, - }, - { /* end of list */ } - }, -}; - QemuOptsList qemu_spice_opts = { .name = "spice", .head = QTAILQ_HEAD_INITIALIZER(qemu_spice_opts.head), @@ -700,7 +652,6 @@ static QemuOptsList *vm_config_groups[32] = { &qemu_rtc_opts, &qemu_global_opts, &qemu_mon_opts, - &qemu_cpudef_opts, &qemu_trace_opts, &qemu_option_rom_opts, &qemu_machine_opts, diff --git a/target-alpha/translate.c b/target-alpha/translate.c index 4045f788ea..71fe1a1ab0 100644 --- a/target-alpha/translate.c +++ b/target-alpha/translate.c @@ -3410,11 +3410,11 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env, if (lj < j) { lj++; while (lj < j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = ctx.pc; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_pc[lj] = ctx.pc; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); @@ -3468,7 +3468,7 @@ static inline void gen_intermediate_code_internal(CPUAlphaState *env, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } else { tb->size = ctx.pc - pc_start; tb->icount = num_insns; @@ -3551,5 +3551,5 @@ CPUAlphaState * cpu_alpha_init (const char *cpu_model) void restore_state_to_opc(CPUAlphaState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-arm/translate.c b/target-arm/translate.c index c42110ab0d..3cf3604517 100644 --- a/target-arm/translate.c +++ b/target-arm/translate.c @@ -9838,12 +9838,12 @@ static inline void gen_intermediate_code_internal(CPUARMState *env, if (lj < j) { lj++; while (lj < j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_condexec_bits[lj] = (dc->condexec_cond << 4) | (dc->condexec_mask >> 1); - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) @@ -9977,7 +9977,7 @@ done_generating: j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } else { tb->size = dc->pc - pc_start; tb->icount = num_insns; @@ -10043,6 +10043,6 @@ void cpu_dump_state(CPUARMState *env, FILE *f, fprintf_function cpu_fprintf, void restore_state_to_opc(CPUARMState *env, TranslationBlock *tb, int pc_pos) { - env->regs[15] = gen_opc_pc[pc_pos]; + env->regs[15] = tcg_ctx.gen_opc_pc[pc_pos]; env->condexec_bits = gen_opc_condexec_bits[pc_pos]; } diff --git a/target-cris/translate.c b/target-cris/translate.c index 0b0e86dbd1..60bdc241ef 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3301,16 +3301,16 @@ gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb, if (lj < j) { lj++; while (lj < j) { - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } } if (dc->delayed_branch == 1) { - gen_opc_pc[lj] = dc->ppc | 1; + tcg_ctx.gen_opc_pc[lj] = dc->ppc | 1; } else { - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_pc[lj] = dc->pc; } - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } /* Pretty disas. */ @@ -3439,7 +3439,7 @@ gen_intermediate_code_internal(CPUCRISState *env, TranslationBlock *tb, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) { - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } } else { tb->size = dc->pc - pc_start; @@ -3621,5 +3621,5 @@ CRISCPU *cpu_cris_init(const char *cpu_model) void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-i386/translate.c b/target-i386/translate.c index 8e676ba1a8..f394ea69a5 100644 --- a/target-i386/translate.c +++ b/target-i386/translate.c @@ -7988,12 +7988,12 @@ static inline void gen_intermediate_code_internal(CPUX86State *env, if (lj < j) { lj++; while (lj < j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = pc_ptr; + tcg_ctx.gen_opc_pc[lj] = pc_ptr; gen_opc_cc_op[lj] = dc->cc_op; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); @@ -8037,7 +8037,7 @@ static inline void gen_intermediate_code_internal(CPUX86State *env, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } #ifdef DEBUG_DISAS @@ -8080,16 +8080,17 @@ void restore_state_to_opc(CPUX86State *env, TranslationBlock *tb, int pc_pos) int i; qemu_log("RESTORE:\n"); for(i = 0;i <= pc_pos; i++) { - if (gen_opc_instr_start[i]) { - qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, gen_opc_pc[i]); + if (tcg_ctx.gen_opc_instr_start[i]) { + qemu_log("0x%04x: " TARGET_FMT_lx "\n", i, + tcg_ctx.gen_opc_pc[i]); } } qemu_log("pc_pos=0x%x eip=" TARGET_FMT_lx " cs_base=%x\n", - pc_pos, gen_opc_pc[pc_pos] - tb->cs_base, + pc_pos, tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base, (uint32_t)tb->cs_base); } #endif - env->eip = gen_opc_pc[pc_pos] - tb->cs_base; + env->eip = tcg_ctx.gen_opc_pc[pc_pos] - tb->cs_base; cc_op = gen_opc_cc_op[pc_pos]; if (cc_op != CC_OP_DYNAMIC) env->cc_op = cc_op; diff --git a/target-lm32/translate.c b/target-lm32/translate.c index af986499f2..e131ad1b5f 100644 --- a/target-lm32/translate.c +++ b/target-lm32/translate.c @@ -1051,12 +1051,12 @@ static void gen_intermediate_code_internal(CPULM32State *env, if (lj < j) { lj++; while (lj < j) { - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } } - gen_opc_pc[lj] = dc->pc; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } /* Pretty disas. */ @@ -1110,7 +1110,7 @@ static void gen_intermediate_code_internal(CPULM32State *env, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) { - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } } else { tb->size = dc->pc - pc_start; @@ -1172,7 +1172,7 @@ void cpu_dump_state(CPULM32State *env, FILE *f, fprintf_function cpu_fprintf, void restore_state_to_opc(CPULM32State *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } void lm32_translate_init(void) diff --git a/target-m68k/translate.c b/target-m68k/translate.c index b13be4899e..11defc6e04 100644 --- a/target-m68k/translate.c +++ b/target-m68k/translate.c @@ -3019,11 +3019,11 @@ gen_intermediate_code_internal(CPUM68KState *env, TranslationBlock *tb, if (lj < j) { lj++; while (lj < j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = dc->pc; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); @@ -3078,7 +3078,7 @@ gen_intermediate_code_internal(CPUM68KState *env, TranslationBlock *tb, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } else { tb->size = dc->pc - pc_start; tb->icount = num_insns; @@ -3121,5 +3121,5 @@ void cpu_dump_state(CPUM68KState *env, FILE *f, fprintf_function cpu_fprintf, void restore_state_to_opc(CPUM68KState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index cce4494954..6ceff02a12 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1788,11 +1788,11 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, if (lj < j) { lj++; while (lj < j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = dc->pc; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } /* Pretty disas. */ @@ -1902,7 +1902,7 @@ gen_intermediate_code_internal(CPUMBState *env, TranslationBlock *tb, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } else { tb->size = dc->pc - pc_start; tb->icount = num_insns; @@ -2014,5 +2014,5 @@ MicroBlazeCPU *cpu_mb_init(const char *cpu_model) void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos) { - env->sregs[SR_PC] = gen_opc_pc[pc_pos]; + env->sregs[SR_PC] = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-mips/translate.c b/target-mips/translate.c index 71c55bcadb..65e6725cc9 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -15579,13 +15579,13 @@ gen_intermediate_code_internal (CPUMIPSState *env, TranslationBlock *tb, if (lj < j) { lj++; while (lj < j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = ctx.pc; + tcg_ctx.gen_opc_pc[lj] = ctx.pc; gen_opc_hflags[lj] = ctx.hflags & MIPS_HFLAG_BMASK; gen_opc_btarget[lj] = ctx.btarget; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); @@ -15662,7 +15662,7 @@ done_generating: j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } else { tb->size = ctx.pc - pc_start; tb->icount = num_insns; @@ -16002,7 +16002,7 @@ void cpu_state_reset(CPUMIPSState *env) void restore_state_to_opc(CPUMIPSState *env, TranslationBlock *tb, int pc_pos) { - env->active_tc.PC = gen_opc_pc[pc_pos]; + env->active_tc.PC = tcg_ctx.gen_opc_pc[pc_pos]; env->hflags &= ~MIPS_HFLAG_BMASK; env->hflags |= gen_opc_hflags[pc_pos]; switch (env->hflags & MIPS_HFLAG_BMASK_BASE) { diff --git a/target-openrisc/translate.c b/target-openrisc/translate.c index f14da7bd1a..9ac999a9c8 100644 --- a/target-openrisc/translate.c +++ b/target-openrisc/translate.c @@ -1707,12 +1707,12 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, if (k < j) { k++; while (k < j) { - gen_opc_instr_start[k++] = 0; + tcg_ctx.gen_opc_instr_start[k++] = 0; } } - gen_opc_pc[k] = dc->pc; - gen_opc_instr_start[k] = 1; - gen_opc_icount[k] = num_insns; + tcg_ctx.gen_opc_pc[k] = dc->pc; + tcg_ctx.gen_opc_instr_start[k] = 1; + tcg_ctx.gen_opc_icount[k] = num_insns; } if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { @@ -1787,7 +1787,7 @@ static inline void gen_intermediate_code_internal(OpenRISCCPU *cpu, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; k++; while (k <= j) { - gen_opc_instr_start[k++] = 0; + tcg_ctx.gen_opc_instr_start[k++] = 0; } } else { tb->size = dc->pc - pc_start; @@ -1832,5 +1832,5 @@ void cpu_dump_state(CPUOpenRISCState *env, FILE *f, void restore_state_to_opc(CPUOpenRISCState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-ppc/translate.c b/target-ppc/translate.c index 987b04eda5..653c2fdb1f 100644 --- a/target-ppc/translate.c +++ b/target-ppc/translate.c @@ -9680,11 +9680,11 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env, if (lj < j) { lj++; while (lj < j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } - gen_opc_pc[lj] = ctx.nip; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_pc[lj] = ctx.nip; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } LOG_DISAS("----------------\n"); LOG_DISAS("nip=" TARGET_FMT_lx " super=%d ir=%d\n", @@ -9781,7 +9781,7 @@ static inline void gen_intermediate_code_internal(CPUPPCState *env, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } else { tb->size = ctx.nip - pc_start; tb->icount = num_insns; @@ -9810,5 +9810,5 @@ void gen_intermediate_code_pc (CPUPPCState *env, struct TranslationBlock *tb) void restore_state_to_opc(CPUPPCState *env, TranslationBlock *tb, int pc_pos) { - env->nip = gen_opc_pc[pc_pos]; + env->nip = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-s390x/translate.c b/target-s390x/translate.c index 993f20752c..787e3c6963 100644 --- a/target-s390x/translate.c +++ b/target-s390x/translate.c @@ -5160,13 +5160,13 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env, if (lj < j) { lj++; while (lj < j) { - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } } - gen_opc_pc[lj] = dc.pc; + tcg_ctx.gen_opc_pc[lj] = dc.pc; gen_opc_cc_op[lj] = dc.cc_op; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { gen_io_start(); @@ -5212,7 +5212,7 @@ static inline void gen_intermediate_code_internal(CPUS390XState *env, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) { - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } } else { tb->size = dc.pc - pc_start; @@ -5240,7 +5240,7 @@ void gen_intermediate_code_pc (CPUS390XState *env, struct TranslationBlock *tb) void restore_state_to_opc(CPUS390XState *env, TranslationBlock *tb, int pc_pos) { int cc_op; - env->psw.addr = gen_opc_pc[pc_pos]; + env->psw.addr = tcg_ctx.gen_opc_pc[pc_pos]; cc_op = gen_opc_cc_op[pc_pos]; if ((cc_op != CC_OP_DYNAMIC) && (cc_op != CC_OP_STATIC)) { env->cc_op = cc_op; diff --git a/target-sh4/translate.c b/target-sh4/translate.c index 5497dede05..86493e1b03 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -2003,12 +2003,12 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb, if (ii < i) { ii++; while (ii < i) - gen_opc_instr_start[ii++] = 0; + tcg_ctx.gen_opc_instr_start[ii++] = 0; } - gen_opc_pc[ii] = ctx.pc; + tcg_ctx.gen_opc_pc[ii] = ctx.pc; gen_opc_hflags[ii] = ctx.flags; - gen_opc_instr_start[ii] = 1; - gen_opc_icount[ii] = num_insns; + tcg_ctx.gen_opc_instr_start[ii] = 1; + tcg_ctx.gen_opc_icount[ii] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) gen_io_start(); @@ -2061,7 +2061,7 @@ gen_intermediate_code_internal(CPUSH4State * env, TranslationBlock * tb, i = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; ii++; while (ii <= i) - gen_opc_instr_start[ii++] = 0; + tcg_ctx.gen_opc_instr_start[ii++] = 0; } else { tb->size = ctx.pc - pc_start; tb->icount = num_insns; @@ -2088,6 +2088,6 @@ void gen_intermediate_code_pc(CPUSH4State * env, struct TranslationBlock *tb) void restore_state_to_opc(CPUSH4State *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; env->flags = gen_opc_hflags[pc_pos]; } diff --git a/target-sparc/translate.c b/target-sparc/translate.c index 2ae803695b..5859f2e801 100644 --- a/target-sparc/translate.c +++ b/target-sparc/translate.c @@ -5283,11 +5283,11 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, if (lj < j) { lj++; while (lj < j) - gen_opc_instr_start[lj++] = 0; - gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_pc[lj] = dc->pc; gen_opc_npc[lj] = dc->npc; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) @@ -5339,7 +5339,7 @@ static inline void gen_intermediate_code_internal(TranslationBlock * tb, j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; #if 0 log_page_dump(); #endif @@ -5478,7 +5478,7 @@ void gen_intermediate_code_init(CPUSPARCState *env) void restore_state_to_opc(CPUSPARCState *env, TranslationBlock *tb, int pc_pos) { target_ulong npc; - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; npc = gen_opc_npc[pc_pos]; if (npc == 1) { /* dynamic NPC: already stored */ diff --git a/target-unicore32/translate.c b/target-unicore32/translate.c index 052bb45d70..3951758fc8 100644 --- a/target-unicore32/translate.c +++ b/target-unicore32/translate.c @@ -2003,12 +2003,12 @@ static inline void gen_intermediate_code_internal(CPUUniCore32State *env, if (lj < j) { lj++; while (lj < j) { - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } } - gen_opc_pc[lj] = dc->pc; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = num_insns; + tcg_ctx.gen_opc_pc[lj] = dc->pc; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = num_insns; } if (num_insns + 1 == max_insns && (tb->cflags & CF_LAST_IO)) { @@ -2117,7 +2117,7 @@ done_generating: j = tcg_ctx.gen_opc_ptr - tcg_ctx.gen_opc_buf; lj++; while (lj <= j) { - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } } else { tb->size = dc->pc - pc_start; @@ -2203,5 +2203,5 @@ void cpu_dump_state(CPUUniCore32State *env, FILE *f, void restore_state_to_opc(CPUUniCore32State *env, TranslationBlock *tb, int pc_pos) { - env->regs[31] = gen_opc_pc[pc_pos]; + env->regs[31] = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/target-xtensa/translate.c b/target-xtensa/translate.c index e5a3f49a75..828b9cabb5 100644 --- a/target-xtensa/translate.c +++ b/target-xtensa/translate.c @@ -2897,12 +2897,12 @@ static void gen_intermediate_code_internal( if (lj < j) { lj++; while (lj < j) { - gen_opc_instr_start[lj++] = 0; + tcg_ctx.gen_opc_instr_start[lj++] = 0; } } - gen_opc_pc[lj] = dc.pc; - gen_opc_instr_start[lj] = 1; - gen_opc_icount[lj] = insn_count; + tcg_ctx.gen_opc_pc[lj] = dc.pc; + tcg_ctx.gen_opc_instr_start[lj] = 1; + tcg_ctx.gen_opc_icount[lj] = insn_count; } if (unlikely(qemu_loglevel_mask(CPU_LOG_TB_OP | CPU_LOG_TB_OP_OPT))) { @@ -3028,5 +3028,5 @@ void cpu_dump_state(CPUXtensaState *env, FILE *f, fprintf_function cpu_fprintf, void restore_state_to_opc(CPUXtensaState *env, TranslationBlock *tb, int pc_pos) { - env->pc = gen_opc_pc[pc_pos]; + env->pc = tcg_ctx.gen_opc_pc[pc_pos]; } diff --git a/tcg/tcg.h b/tcg/tcg.h index 9481e35ab4..f6e255f775 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -455,6 +455,9 @@ struct TCGContext { uint16_t *gen_opc_ptr; TCGArg *gen_opparam_ptr; + target_ulong gen_opc_pc[OPC_BUF_SIZE]; + uint16_t gen_opc_icount[OPC_BUF_SIZE]; + uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; #if defined(CONFIG_QEMU_LDST_OPTIMIZATION) && defined(CONFIG_SOFTMMU) /* labels info for qemu_ld/st IRs diff --git a/translate-all.c b/translate-all.c index d9c2e57861..f22e3eedd2 100644 --- a/translate-all.c +++ b/translate-all.c @@ -33,10 +33,6 @@ /* code generation context */ TCGContext tcg_ctx; -target_ulong gen_opc_pc[OPC_BUF_SIZE]; -uint16_t gen_opc_icount[OPC_BUF_SIZE]; -uint8_t gen_opc_instr_start[OPC_BUF_SIZE]; - void cpu_gen_init(void) { tcg_context_init(&tcg_ctx); @@ -146,9 +142,10 @@ int cpu_restore_state(TranslationBlock *tb, if (j < 0) return -1; /* now find start of instruction before */ - while (gen_opc_instr_start[j] == 0) + while (s->gen_opc_instr_start[j] == 0) { j--; - env->icount_decr.u16.low -= gen_opc_icount[j]; + } + env->icount_decr.u16.low -= s->gen_opc_icount[j]; restore_state_to_opc(env, tb, j); diff --git a/ui/curses.c b/ui/curses.c index b40b22307d..5dc0b2c95f 100644 --- a/ui/curses.c +++ b/ui/curses.c @@ -28,10 +28,6 @@ #include <termios.h> #endif -#ifdef __OpenBSD__ -#define resize_term resizeterm -#endif - #include "qemu-common.h" #include "console.h" #include "sysemu.h" |