diff options
405 files changed, 73378 insertions, 681 deletions
diff --git a/Kconfig.host b/Kconfig.host index 4af19bf70e..a9a55a9c31 100644 --- a/Kconfig.host +++ b/Kconfig.host @@ -24,6 +24,10 @@ config VHOST_USER bool select VHOST +config VHOST_VDPA + bool + select VHOST + config VHOST_KERNEL bool select VHOST diff --git a/configure b/configure index e8e8e984f2..8ee15810c8 100755 --- a/configure +++ b/configure @@ -2494,9 +2494,10 @@ if test "$vhost_net_vdpa" = "yes" && test "$vhost_vdpa" = "no"; then error_exit "--enable-vhost-net-vdpa requires --enable-vhost-vdpa" fi -# OR the vhost-kernel and vhost-user values for simplicity +# OR the vhost-kernel, vhost-vdpa and vhost-user values for simplicity if test "$vhost_net" = ""; then test "$vhost_net_user" = "yes" && vhost_net=yes + test "$vhost_net_vdpa" = "yes" && vhost_net=yes test "$vhost_kernel" = "yes" && vhost_net=yes fi diff --git a/contrib/libvhost-user/libvhost-user.c b/contrib/libvhost-user/libvhost-user.c index 70055c98b7..9f1285b8a1 100644 --- a/contrib/libvhost-user/libvhost-user.c +++ b/contrib/libvhost-user/libvhost-user.c @@ -2416,7 +2416,7 @@ vu_queue_set_notification(VuDev *dev, VuVirtq *vq, int enable) } } -static void +static bool virtqueue_map_desc(VuDev *dev, unsigned int *p_num_sg, struct iovec *iov, unsigned int max_num_sg, bool is_write, @@ -2428,7 +2428,7 @@ virtqueue_map_desc(VuDev *dev, if (!sz) { vu_panic(dev, "virtio: zero sized buffers are not allowed"); - return; + return false; } while (sz) { @@ -2436,13 +2436,13 @@ virtqueue_map_desc(VuDev *dev, if (num_sg == max_num_sg) { vu_panic(dev, "virtio: too many descriptors in indirect table"); - return; + return false; } iov[num_sg].iov_base = vu_gpa_to_va(dev, &len, pa); if (iov[num_sg].iov_base == NULL) { vu_panic(dev, "virtio: invalid address for buffers"); - return; + return false; } iov[num_sg].iov_len = len; num_sg++; @@ -2451,6 +2451,7 @@ virtqueue_map_desc(VuDev *dev, } *p_num_sg = num_sg; + return true; } static void * @@ -2488,6 +2489,7 @@ vu_queue_map_desc(VuDev *dev, VuVirtq *vq, unsigned int idx, size_t sz) if (lduw_le_p(&desc[i].flags) & VRING_DESC_F_INDIRECT) { if (ldl_le_p(&desc[i].len) % sizeof(struct vring_desc)) { vu_panic(dev, "Invalid size for indirect buffer table"); + return NULL; } /* loop over the indirect descriptor table */ @@ -2515,22 +2517,29 @@ vu_queue_map_desc(VuDev *dev, VuVirtq *vq, unsigned int idx, size_t sz) /* Collect all the descriptors */ do { if (lduw_le_p(&desc[i].flags) & VRING_DESC_F_WRITE) { - virtqueue_map_desc(dev, &in_num, iov + out_num, + if (!virtqueue_map_desc(dev, &in_num, iov + out_num, VIRTQUEUE_MAX_SIZE - out_num, true, - ldq_le_p(&desc[i].addr), ldl_le_p(&desc[i].len)); + ldq_le_p(&desc[i].addr), + ldl_le_p(&desc[i].len))) { + return NULL; + } } else { if (in_num) { vu_panic(dev, "Incorrect order for descriptors"); return NULL; } - virtqueue_map_desc(dev, &out_num, iov, + if (!virtqueue_map_desc(dev, &out_num, iov, VIRTQUEUE_MAX_SIZE, false, - ldq_le_p(&desc[i].addr), ldl_le_p(&desc[i].len)); + ldq_le_p(&desc[i].addr), + ldl_le_p(&desc[i].len))) { + return NULL; + } } /* If we've got too many, that implies a descriptor loop. */ if ((in_num + out_num) > max) { vu_panic(dev, "Looped descriptor"); + return NULL; } rc = virtqueue_read_next_desc(dev, desc, i, max, &i); } while (rc == VIRTQUEUE_READ_DESC_MORE); @@ -2724,6 +2733,7 @@ vu_log_queue_fill(VuDev *dev, VuVirtq *vq, if (lduw_le_p(&desc[i].flags) & VRING_DESC_F_INDIRECT) { if (ldl_le_p(&desc[i].len) % sizeof(struct vring_desc)) { vu_panic(dev, "Invalid size for indirect buffer table"); + return; } /* loop over the indirect descriptor table */ diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index 17aa74531c..5326141cee 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -272,13 +272,6 @@ The ``query-cpus`` command is replaced by the ``query-cpus-fast`` command. The ``arch`` output member of the ``query-cpus-fast`` command is replaced by the ``target`` output member. -``cpu-add`` (since 4.0) -''''''''''''''''''''''' - -Use ``device_add`` for hotplugging vCPUs instead of ``cpu-add``. See -documentation of ``query-hotpluggable-cpus`` for additional -details. - ``query-events`` (since 4.0) '''''''''''''''''''''''''''' @@ -294,12 +287,6 @@ the 'wait' field, which is only applicable to sockets in server mode Human Monitor Protocol (HMP) commands ------------------------------------- -``cpu-add`` (since 4.0) -''''''''''''''''''''''' - -Use ``device_add`` for hotplugging vCPUs instead of ``cpu-add``. See -documentation of ``query-hotpluggable-cpus`` for additional details. - ``acl_show``, ``acl_reset``, ``acl_policy``, ``acl_add``, ``acl_remove`` (since 4.0.0) '''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' @@ -517,6 +504,12 @@ QEMU Machine Protocol (QMP) commands The "autoload" parameter has been ignored since 2.12.0. All bitmaps are automatically loaded from qcow2 images. +``cpu-add`` (removed in 5.2) +'''''''''''''''''''''''''''' + +Use ``device_add`` for hotplugging vCPUs instead of ``cpu-add``. See +documentation of ``query-hotpluggable-cpus`` for additional details. + Human Monitor Protocol (HMP) commands ------------------------------------- @@ -526,6 +519,12 @@ The ``hub_id`` parameter of ``hostfwd_add`` / ``hostfwd_remove`` (removed in 5.0 The ``[hub_id name]`` parameter tuple of the 'hostfwd_add' and 'hostfwd_remove' HMP commands has been replaced by ``netdev_id``. +``cpu-add`` (removed in 5.2) +'''''''''''''''''''''''''''' + +Use ``device_add`` for hotplugging vCPUs instead of ``cpu-add``. See +documentation of ``query-hotpluggable-cpus`` for additional details. + Guest Emulator ISAs ------------------- diff --git a/hmp-commands.hx b/hmp-commands.hx index 27c4bbe0f2..1088d64503 100644 --- a/hmp-commands.hx +++ b/hmp-commands.hx @@ -1762,21 +1762,6 @@ SRST ERST { - .name = "cpu-add", - .args_type = "id:i", - .params = "id", - .help = "add cpu (deprecated, use device_add instead)", - .cmd = hmp_cpu_add, - }, - -SRST -``cpu-add`` *id* - Add CPU with id *id*. This command is deprecated, please - +use ``device_add`` instead. For details, refer to - 'docs/cpu-hotplug.rst'. -ERST - - { .name = "qom-list", .args_type = "path:s?", .params = "path", diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index f6fbc9b95d..3792ba96ce 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -556,6 +556,15 @@ Aml *aml_or(Aml *arg1, Aml *arg2, Aml *dst) return build_opcode_2arg_dst(0x7D /* OrOp */, arg1, arg2, dst); } +/* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLAnd */ +Aml *aml_land(Aml *arg1, Aml *arg2) +{ + Aml *var = aml_opcode(0x90 /* LAndOp */); + aml_append(var, arg1); + aml_append(var, arg2); + return var; +} + /* ACPI 1.0b: 16.2.5.4 Type 2 Opcodes Encoding: DefLOr */ Aml *aml_lor(Aml *arg1, Aml *arg2) { @@ -629,6 +638,13 @@ Aml *aml_notify(Aml *arg1, Aml *arg2) return var; } +/* ACPI 1.0b: 16.2.5.3 Type 1 Opcodes Encoding: DefBreak */ +Aml *aml_break(void) +{ + Aml *var = aml_opcode(0xa5 /* BreakOp */); + return var; +} + /* helper to call method without argument */ Aml *aml_call0(const char *method) { diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index 3d6a500fb7..8dd4d8ebbf 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -14,6 +14,8 @@ #define ACPI_CPU_CMD_DATA_OFFSET_RW 8 #define ACPI_CPU_CMD_DATA2_OFFSET_R 0 +#define OVMF_CPUHP_SMI_CMD 4 + enum { CPHP_GET_NEXT_CPU_WITH_EVENT_CMD = 0, CPHP_OST_EVENT_CMD = 1, @@ -321,6 +323,7 @@ const VMStateDescription vmstate_cpu_hotplug = { #define CPU_NOTIFY_METHOD "CTFY" #define CPU_EJECT_METHOD "CEJ0" #define CPU_OST_METHOD "COST" +#define CPU_ADDED_LIST "CNEW" #define CPU_ENABLED "CPEN" #define CPU_SELECTOR "CSEL" @@ -465,42 +468,150 @@ void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, method = aml_method(CPU_SCAN_METHOD, 0, AML_SERIALIZED); { + const uint8_t max_cpus_per_pass = 255; Aml *else_ctx; - Aml *while_ctx; + Aml *while_ctx, *while_ctx2; Aml *has_event = aml_local(0); Aml *dev_chk = aml_int(1); Aml *eject_req = aml_int(3); Aml *next_cpu_cmd = aml_int(CPHP_GET_NEXT_CPU_WITH_EVENT_CMD); + Aml *num_added_cpus = aml_local(1); + Aml *cpu_idx = aml_local(2); + Aml *uid = aml_local(3); + Aml *has_job = aml_local(4); + Aml *new_cpus = aml_name(CPU_ADDED_LIST); aml_append(method, aml_acquire(ctrl_lock, 0xFFFF)); - aml_append(method, aml_store(one, has_event)); - while_ctx = aml_while(aml_equal(has_event, one)); + + /* + * Windows versions newer than XP (including Windows 10/Windows + * Server 2019), do support* VarPackageOp but, it is cripled to hold + * the same elements number as old PackageOp. + * For compatibility with Windows XP (so it won't crash) use ACPI1.0 + * PackageOp which can hold max 255 elements. + * + * use named package as old Windows don't support it in local var + */ + aml_append(method, aml_name_decl(CPU_ADDED_LIST, + aml_package(max_cpus_per_pass))); + + aml_append(method, aml_store(zero, uid)); + aml_append(method, aml_store(one, has_job)); + /* + * CPU_ADDED_LIST can hold limited number of elements, outer loop + * allows to process CPUs in batches which let us to handle more + * CPUs than CPU_ADDED_LIST can hold. + */ + while_ctx2 = aml_while(aml_equal(has_job, one)); { - /* clear loop exit condition, ins_evt/rm_evt checks - * will set it to 1 while next_cpu_cmd returns a CPU - * with events */ - aml_append(while_ctx, aml_store(zero, has_event)); - aml_append(while_ctx, aml_store(next_cpu_cmd, cpu_cmd)); - ifctx = aml_if(aml_equal(ins_evt, one)); - { - aml_append(ifctx, - aml_call2(CPU_NOTIFY_METHOD, cpu_data, dev_chk)); - aml_append(ifctx, aml_store(one, ins_evt)); - aml_append(ifctx, aml_store(one, has_event)); - } - aml_append(while_ctx, ifctx); - else_ctx = aml_else(); - ifctx = aml_if(aml_equal(rm_evt, one)); - { - aml_append(ifctx, - aml_call2(CPU_NOTIFY_METHOD, cpu_data, eject_req)); - aml_append(ifctx, aml_store(one, rm_evt)); - aml_append(ifctx, aml_store(one, has_event)); - } - aml_append(else_ctx, ifctx); - aml_append(while_ctx, else_ctx); + aml_append(while_ctx2, aml_store(zero, has_job)); + + aml_append(while_ctx2, aml_store(one, has_event)); + aml_append(while_ctx2, aml_store(zero, num_added_cpus)); + + /* + * Scan CPUs, till there are CPUs with events or + * CPU_ADDED_LIST capacity is exhausted + */ + while_ctx = aml_while(aml_land(aml_equal(has_event, one), + aml_lless(uid, aml_int(arch_ids->len)))); + { + /* + * clear loop exit condition, ins_evt/rm_evt checks will + * set it to 1 while next_cpu_cmd returns a CPU with events + */ + aml_append(while_ctx, aml_store(zero, has_event)); + + aml_append(while_ctx, aml_store(uid, cpu_selector)); + aml_append(while_ctx, aml_store(next_cpu_cmd, cpu_cmd)); + + /* + * wrap around case, scan is complete, exit loop. + * It happens since events are not cleared in scan loop, + * so next_cpu_cmd continues to find already processed CPUs + */ + ifctx = aml_if(aml_lless(cpu_data, uid)); + { + aml_append(ifctx, aml_break()); + } + aml_append(while_ctx, ifctx); + + /* + * if CPU_ADDED_LIST is full, exit inner loop and process + * collected CPUs + */ + ifctx = aml_if( + aml_equal(num_added_cpus, aml_int(max_cpus_per_pass))); + { + aml_append(ifctx, aml_store(one, has_job)); + aml_append(ifctx, aml_break()); + } + aml_append(while_ctx, ifctx); + + aml_append(while_ctx, aml_store(cpu_data, uid)); + ifctx = aml_if(aml_equal(ins_evt, one)); + { + /* cache added CPUs to Notify/Wakeup later */ + aml_append(ifctx, aml_store(uid, + aml_index(new_cpus, num_added_cpus))); + aml_append(ifctx, aml_increment(num_added_cpus)); + aml_append(ifctx, aml_store(one, has_event)); + } + aml_append(while_ctx, ifctx); + else_ctx = aml_else(); + ifctx = aml_if(aml_equal(rm_evt, one)); + { + aml_append(ifctx, + aml_call2(CPU_NOTIFY_METHOD, uid, eject_req)); + aml_append(ifctx, aml_store(one, rm_evt)); + aml_append(ifctx, aml_store(one, has_event)); + } + aml_append(else_ctx, ifctx); + aml_append(while_ctx, else_ctx); + aml_append(while_ctx, aml_increment(uid)); + } + aml_append(while_ctx2, while_ctx); + + /* + * in case FW negotiated ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, + * make upcall to FW, so it can pull in new CPUs before + * OS is notified and wakes them up + */ + if (opts.smi_path) { + ifctx = aml_if(aml_lgreater(num_added_cpus, zero)); + { + aml_append(ifctx, aml_store(aml_int(OVMF_CPUHP_SMI_CMD), + aml_name("%s", opts.smi_path))); + } + aml_append(while_ctx2, ifctx); + } + + /* Notify OSPM about new CPUs and clear insert events */ + aml_append(while_ctx2, aml_store(zero, cpu_idx)); + while_ctx = aml_while(aml_lless(cpu_idx, num_added_cpus)); + { + aml_append(while_ctx, + aml_store(aml_derefof(aml_index(new_cpus, cpu_idx)), + uid)); + aml_append(while_ctx, + aml_call2(CPU_NOTIFY_METHOD, uid, dev_chk)); + aml_append(while_ctx, aml_store(uid, aml_debug())); + aml_append(while_ctx, aml_store(uid, cpu_selector)); + aml_append(while_ctx, aml_store(one, ins_evt)); + aml_append(while_ctx, aml_increment(cpu_idx)); + } + aml_append(while_ctx2, while_ctx); + /* + * If another batch is needed, then it will resume scanning + * exactly at -- and not after -- the last CPU that's currently + * in CPU_ADDED_LIST. In other words, the last CPU in + * CPU_ADDED_LIST is going to be re-checked. That's OK: we've + * just cleared the insert event for *all* CPUs in + * CPU_ADDED_LIST, including the last one. So the scan will + * simply seek past it. + */ } - aml_append(method, while_ctx); + aml_append(method, while_ctx2); aml_append(method, aml_release(ctrl_lock)); } aml_append(cpus_dev, method); diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 6a19070cec..95cb0f935b 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -408,10 +408,20 @@ void ich9_pm_device_pre_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, ICH9LPCState *lpc = ICH9_LPC_DEVICE(hotplug_dev); if (object_dynamic_cast(OBJECT(dev), TYPE_PC_DIMM) && - !lpc->pm.acpi_memory_hotplug.is_enabled) + !lpc->pm.acpi_memory_hotplug.is_enabled) { error_setg(errp, "memory hotplug is not enabled: %s.memory-hotplug-support " "is not set", object_get_typename(OBJECT(lpc))); + } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU)) { + uint64_t negotiated = lpc->smi_negotiated_features; + + if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) && + !(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT))) { + error_setg(errp, "cpu hotplug with SMI wasn't enabled by firmware"); + error_append_hint(errp, "update machine type to newer than 5.1 " + "and firmware that suppors CPU hotplug with SMM"); + } + } } void ich9_pm_device_plug_cb(HotplugHandler *hotplug_dev, DeviceState *dev, @@ -450,6 +460,18 @@ void ich9_pm_device_unplug_request_cb(HotplugHandler *hotplug_dev, errp); } else if (object_dynamic_cast(OBJECT(dev), TYPE_CPU) && !lpc->pm.cpu_hotplug_legacy) { + uint64_t negotiated = lpc->smi_negotiated_features; + + if (negotiated & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT) && + !(negotiated & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT))) { + error_setg(errp, "cpu hot-unplug with SMI wasn't enabled " + "by firmware"); + error_append_hint(errp, "update machine type to a version having " + "x-smi-cpu-hotunplug=on and firmware that " + "supports CPU hot-unplug with SMM"); + return; + } + acpi_cpu_unplug_request_cb(hotplug_dev, &lpc->pm.cpuhp_state, dev, errp); } else { diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index 39b1f74442..32ae8b2c0a 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -147,6 +147,21 @@ static PCIBus *acpi_pcihp_find_hotplug_bus(AcpiPciHpState *s, int bsel) if (!bsel && !find.bus) { find.bus = s->root; } + + /* + * Check if find.bus is actually hotpluggable. If bsel is set to + * NULL for example on the root bus in order to make it + * non-hotpluggable, find.bus will match the root bus when bsel + * is 0. See acpi_pcihp_test_hotplug_bus() above. Since the + * bus is not hotpluggable however, we should not select the bus. + * Instead, we should set find.bus to NULL in that case. In the check + * below, we generalize this case for all buses, not just the root bus. + * The callers of this function check for a null return value and + * handle them appropriately. + */ + if (find.bus && !qbus_is_hotpluggable(BUS(find.bus))) { + find.bus = NULL; + } return find.bus; } diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 832f8fba82..894d357f8c 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -596,8 +596,10 @@ static void piix4_acpi_system_hot_add_init(MemoryRegion *parent, "acpi-gpe0", GPE_LEN); memory_region_add_subregion(parent, GPE_BASE, &s->io_gpe); - acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, - s->use_acpi_hotplug_bridge); + if (s->use_acpi_hotplug_bridge || s->use_acpi_root_pci_hotplug) { + acpi_pcihp_init(OBJECT(s), &s->acpi_pci_hotplug, bus, parent, + s->use_acpi_hotplug_bridge); + } s->cpu_hotplug_legacy = true; object_property_add_bool(OBJECT(s), "cpu-hotplug-legacy", diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 39aec42dae..a076b1e54d 100644 --- a/hw/block/vhost-user-blk.c +++ b/hw/block/vhost-user-blk.c @@ -150,6 +150,7 @@ static int vhost_user_blk_start(VirtIODevice *vdev) error_report("Error starting vhost: %d", -ret); goto err_guest_notifiers; } + s->started_vu = true; /* guest_notifier_mask/pending not used yet, so just unmask * everything here. virtio-pci will do the right thing by @@ -175,6 +176,11 @@ static void vhost_user_blk_stop(VirtIODevice *vdev) VirtioBusClass *k = VIRTIO_BUS_GET_CLASS(qbus); int ret; + if (!s->started_vu) { + return; + } + s->started_vu = false; + if (!k->set_guest_notifiers) { return; } @@ -341,9 +347,7 @@ static void vhost_user_blk_disconnect(DeviceState *dev) } s->connected = false; - if (s->dev.started) { - vhost_user_blk_stop(vdev); - } + vhost_user_blk_stop(vdev); vhost_dev_cleanup(&s->dev); } @@ -399,6 +403,15 @@ static void vhost_user_blk_event(void *opaque, QEMUChrEvent event) NULL, NULL, false); aio_bh_schedule_oneshot(ctx, vhost_user_blk_chr_closed_bh, opaque); } + + /* + * Move vhost device to the stopped state. The vhost-user device + * will be clean up and disconnected in BH. This can be useful in + * the vhost migration code. If disconnect was caught there is an + * option for the general vhost code to get the dev state without + * knowing its type (in this case vhost-user). + */ + s->dev.started = false; break; case CHR_EVENT_BREAK: case CHR_EVENT_MUX_IN: diff --git a/hw/core/machine-hmp-cmds.c b/hw/core/machine-hmp-cmds.c index 39999c47c5..f4092b98cc 100644 --- a/hw/core/machine-hmp-cmds.c +++ b/hw/core/machine-hmp-cmds.c @@ -46,18 +46,6 @@ void hmp_info_cpus(Monitor *mon, const QDict *qdict) qapi_free_CpuInfoFastList(cpu_list); } -void hmp_cpu_add(Monitor *mon, const QDict *qdict) -{ - int cpuid; - Error *err = NULL; - - error_report("cpu_add is deprecated, please use device_add instead"); - - cpuid = qdict_get_int(qdict, "id"); - qmp_cpu_add(cpuid, &err); - hmp_handle_error(mon, err); -} - void hmp_hotpluggable_cpus(Monitor *mon, const QDict *qdict) { Error *err = NULL; diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 21551221ad..5362c80a18 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -284,18 +284,6 @@ HotpluggableCPUList *qmp_query_hotpluggable_cpus(Error **errp) return machine_query_hotpluggable_cpus(ms); } -void qmp_cpu_add(int64_t id, Error **errp) -{ - MachineClass *mc; - - mc = MACHINE_GET_CLASS(current_machine); - if (mc->hot_add_cpu) { - mc->hot_add_cpu(current_machine, id, errp); - } else { - error_setg(errp, "Not supported"); - } -} - void qmp_set_numa_node(NumaOptions *cmd, Error **errp) { if (!runstate_check(RUN_STATE_PRECONFIG)) { diff --git a/hw/core/machine.c b/hw/core/machine.c index 9b02fb2f5e..d7f4a0d259 100644 --- a/hw/core/machine.c +++ b/hw/core/machine.c @@ -44,6 +44,7 @@ GlobalProperty hw_compat_5_0[] = { { "vmport", "x-signal-unsupported-cmd", "off" }, { "vmport", "x-report-vmx-type", "off" }, { "vmport", "x-cmds-v2", "off" }, + { "virtio-device", "x-disable-legacy-check", "true" }, }; const size_t hw_compat_5_0_len = G_N_ELEMENTS(hw_compat_5_0); diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index 0e0535d2e3..8d14e4667a 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -95,6 +95,8 @@ typedef struct AcpiPmInfo { bool s3_disabled; bool s4_disabled; bool pcihp_bridge_en; + bool smi_on_cpuhp; + bool pcihp_root_en; uint8_t s4_val; AcpiFadtData fadt; uint16_t cpu_hp_io_base; @@ -194,6 +196,7 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) pm->cpu_hp_io_base = 0; pm->pcihp_io_base = 0; pm->pcihp_io_len = 0; + pm->smi_on_cpuhp = false; assert(obj); init_common_fadt_data(machine, obj, &pm->fadt); @@ -207,12 +210,16 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) object_property_get_uint(obj, ACPI_PCIHP_IO_LEN_PROP, NULL); } if (lpc) { + uint64_t smi_features = object_property_get_uint(lpc, + ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, NULL); struct AcpiGenericAddress r = { .space_id = AML_AS_SYSTEM_IO, .bit_width = 8, .address = ICH9_RST_CNT_IOPORT }; pm->fadt.reset_reg = r; pm->fadt.reset_val = 0xf; pm->fadt.flags |= 1 << ACPI_FADT_F_RESET_REG_SUP; pm->cpu_hp_io_base = ICH9_CPU_HOTPLUG_IO_BASE; + pm->smi_on_cpuhp = + !!(smi_features & BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT)); } /* The above need not be conditional on machine type because the reset port @@ -245,6 +252,9 @@ static void acpi_get_pm_info(MachineState *machine, AcpiPmInfo *pm) pm->pcihp_bridge_en = object_property_get_bool(obj, "acpi-pci-hotplug-with-bridge-support", NULL); + pm->pcihp_root_en = + object_property_get_bool(obj, "acpi-root-pci-hotplug", + NULL); } static void acpi_get_misc_info(AcpiMiscInfo *info) @@ -359,6 +369,7 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, int slot = PCI_SLOT(i); bool hotplug_enabled_dev; bool bridge_in_acpi; + bool cold_plugged_bridge; if (!pdev) { if (bsel) { /* add hotplug slots for non present devices */ @@ -380,15 +391,14 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, pc = PCI_DEVICE_GET_CLASS(pdev); dc = DEVICE_GET_CLASS(pdev); - /* When hotplug for bridges is enabled, bridges are - * described in ACPI separately (see build_pci_bus_end). - * In this case they aren't themselves hot-pluggable. + /* + * Cold plugged bridges aren't themselves hot-pluggable. * Hotplugged bridges *are* hot-pluggable. */ - bridge_in_acpi = pc->is_bridge && pcihp_bridge_en && - !DEVICE(pdev)->hotplugged; + cold_plugged_bridge = pc->is_bridge && !DEVICE(pdev)->hotplugged; + bridge_in_acpi = cold_plugged_bridge && pcihp_bridge_en; - hotplug_enabled_dev = bsel && dc->hotpluggable && !bridge_in_acpi; + hotplug_enabled_dev = bsel && dc->hotpluggable && !cold_plugged_bridge; if (pc->class_id == PCI_CLASS_BRIDGE_ISA) { continue; @@ -450,10 +460,12 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, } /* Append PCNT method to notify about events on local and child buses. - * Add unconditionally for root since DSDT expects it. + * Add this method for root bus only when hotplug is enabled since DSDT + * expects it. */ - method = aml_method("PCNT", 0, AML_NOTSERIALIZED); - + if (bsel || pcihp_bridge_en) { + method = aml_method("PCNT", 0, AML_NOTSERIALIZED); + } /* If bus supports hotplug select it and notify about local events */ if (bsel) { uint64_t bsel_val = qnum_get_uint(qobject_to(QNum, bsel)); @@ -479,7 +491,10 @@ static void build_append_pci_bus_devices(Aml *parent_scope, PCIBus *bus, aml_append(method, aml_name("^S%.02X.PCNT", devfn)); } } - aml_append(parent_scope, method); + + if (bsel || pcihp_bridge_en) { + aml_append(parent_scope, method); + } qobject_unref(bsel); } @@ -1504,7 +1519,9 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_hpet_aml(dsdt); build_piix4_isa_bridge(dsdt); build_isa_devices_aml(dsdt); - build_piix4_pci_hotplug(dsdt); + if (pm->pcihp_bridge_en || pm->pcihp_root_en) { + build_piix4_pci_hotplug(dsdt); + } build_piix4_pci0_int(dsdt); } else { sb_scope = aml_scope("_SB"); @@ -1515,6 +1532,32 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, aml_append(dev, aml_name_decl("_UID", aml_int(0))); aml_append(dev, build_q35_osc_method()); aml_append(sb_scope, dev); + + if (pm->smi_on_cpuhp) { + /* reserve SMI block resources, IO ports 0xB2, 0xB3 */ + dev = aml_device("PCI0.SMI0"); + aml_append(dev, aml_name_decl("_HID", aml_eisaid("PNP0A06"))); + aml_append(dev, aml_name_decl("_UID", aml_string("SMI resources"))); + crs = aml_resource_template(); + aml_append(crs, + aml_io( + AML_DECODE16, + ACPI_PORT_SMI_CMD, + ACPI_PORT_SMI_CMD, + 1, + 2) + ); + aml_append(dev, aml_name_decl("_CRS", crs)); + aml_append(dev, aml_operation_region("SMIR", AML_SYSTEM_IO, + aml_int(ACPI_PORT_SMI_CMD), 2)); + field = aml_field("SMIR", AML_BYTE_ACC, AML_NOLOCK, + AML_WRITE_AS_ZEROS); + aml_append(field, aml_named_field("SMIC", 8)); + aml_append(field, aml_reserved_field(8)); + aml_append(dev, field); + aml_append(sb_scope, dev); + } + aml_append(dsdt, sb_scope); build_hpet_aml(dsdt); @@ -1530,7 +1573,8 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, build_legacy_cpu_hotplug_aml(dsdt, machine, pm->cpu_hp_io_base); } else { CPUHotplugFeatures opts = { - .acpi_1_compatible = true, .has_legacy_cphp = true + .acpi_1_compatible = true, .has_legacy_cphp = true, + .smi_path = pm->smi_on_cpuhp ? "\\_SB.PCI0.SMI0.SMIC" : NULL, }; build_cpus_aml(dsdt, machine, opts, pm->cpu_hp_io_base, "\\_SB.PCI0", "\\_GPE._E02"); @@ -1546,7 +1590,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, { aml_append(scope, aml_name_decl("_HID", aml_string("ACPI0006"))); - if (misc->is_piix4) { + if (misc->is_piix4 && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { method = aml_method("_E01", 0, AML_NOTSERIALIZED); aml_append(method, aml_acquire(aml_name("\\_SB.PCI0.BLCK"), 0xFFFF)); @@ -1698,7 +1742,7 @@ build_dsdt(GArray *table_data, BIOSLinker *linker, crs_range_set_free(&crs_range_set); /* reserve PCIHP resources */ - if (pm->pcihp_io_len) { + if (pm->pcihp_io_len && (pm->pcihp_bridge_en || pm->pcihp_root_en)) { dev = aml_device("PHPR"); aml_append(dev, aml_name_decl("_HID", aml_string("PNP0A06"))); aml_append(dev, diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 1e2ab5ebe7..2c6194e57f 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -97,7 +97,9 @@ #include "trace.h" #include CONFIG_DEVICES -GlobalProperty pc_compat_5_1[] = {}; +GlobalProperty pc_compat_5_1[] = { + { "ICH9-LPC", "x-smi-cpu-hotplug", "off" }, +}; const size_t pc_compat_5_1_len = G_N_ELEMENTS(pc_compat_5_1); GlobalProperty pc_compat_5_0[] = { @@ -769,32 +771,6 @@ void pc_smp_parse(MachineState *ms, QemuOpts *opts) } } -void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp) -{ - X86MachineState *x86ms = X86_MACHINE(ms); - int64_t apic_id = x86_cpu_apic_id_from_index(x86ms, id); - Error *local_err = NULL; - - if (id < 0) { - error_setg(errp, "Invalid CPU id: %" PRIi64, id); - return; - } - - if (apic_id >= ACPI_CPU_HOTPLUG_ID_LIMIT) { - error_setg(errp, "Unable to add CPU: %" PRIi64 - ", resulting APIC ID (%" PRIi64 ") is too large", - id, apic_id); - return; - } - - - x86_cpu_new(X86_MACHINE(ms), apic_id, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } -} - static void pc_machine_done(Notifier *notifier, void *data) { @@ -1691,7 +1667,6 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) mc->auto_enable_numa_with_memdev = true; mc->has_hotpluggable_cpus = true; mc->default_boot_order = "cad"; - mc->hot_add_cpu = pc_hot_add_cpu; mc->smp_parse = pc_smp_parse; mc->block_default_type = IF_IDE; mc->max_cpus = 255; diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 6f3e78bb60..2d8413a0ce 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -752,7 +752,6 @@ static void pc_i440fx_1_4_machine_options(MachineClass *m) { pc_i440fx_1_5_machine_options(m); m->hw_version = "1.4.0"; - m->hot_add_cpu = NULL; compat_props_add(m->compat_props, pc_compat_1_4, pc_compat_1_4_len); } diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 622d039717..e1c415f57d 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -382,7 +382,7 @@ static void pc_q35_5_0_machine_options(MachineClass *m) m->numa_mem_supported = true; compat_props_add(m->compat_props, hw_compat_5_0, hw_compat_5_0_len); compat_props_add(m->compat_props, pc_compat_5_0, pc_compat_5_0_len); - m->auto_enable_numa_with_memhp = false; + m->auto_enable_numa_with_memdev = false; } DEFINE_Q35_MACHINE(v5_0, "pc-q35-5.0", NULL, diff --git a/hw/i386/x86.c b/hw/i386/x86.c index c2ea989579..403c2b1dad 100644 --- a/hw/i386/x86.c +++ b/hw/i386/x86.c @@ -279,6 +279,17 @@ void x86_cpu_pre_plug(HotplugHandler *hotplug_dev, return; } + if (x86ms->acpi_dev) { + Error *local_err = NULL; + + hotplug_handler_pre_plug(HOTPLUG_HANDLER(x86ms->acpi_dev), dev, + &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + } + init_topo_info(&topo_info, x86ms); env->nr_dies = x86ms->smp_dies; diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 3303d2eab6..04e5323140 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -373,6 +373,15 @@ static void smi_features_ok_callback(void *opaque) /* guest requests invalid features, leave @features_ok at zero */ return; } + if (!(guest_features & BIT_ULL(ICH9_LPC_SMI_F_BROADCAST_BIT)) && + guest_features & (BIT_ULL(ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT) | + BIT_ULL(ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT))) { + /* + * cpu hot-[un]plug with SMI requires SMI broadcast, + * leave @features_ok at zero + */ + return; + } /* valid feature subset requested, lock it down, report success */ lpc->smi_negotiated_features = guest_features; @@ -638,6 +647,9 @@ static void ich9_lpc_initfn(Object *obj) &acpi_enable_cmd, OBJ_PROP_FLAG_READ); object_property_add_uint8_ptr(OBJECT(lpc), ACPI_PM_PROP_ACPI_DISABLE_CMD, &acpi_disable_cmd, OBJ_PROP_FLAG_READ); + object_property_add_uint64_ptr(obj, ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP, + &lpc->smi_negotiated_features, + OBJ_PROP_FLAG_READ); ich9_pm_add_properties(obj, &lpc->pm); } @@ -747,6 +759,10 @@ static Property ich9_lpc_properties[] = { DEFINE_PROP_BOOL("noreboot", ICH9LPCState, pin_strap.spkr_hi, true), DEFINE_PROP_BIT64("x-smi-broadcast", ICH9LPCState, smi_host_features, ICH9_LPC_SMI_F_BROADCAST_BIT, true), + DEFINE_PROP_BIT64("x-smi-cpu-hotplug", ICH9LPCState, smi_host_features, + ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT, true), + DEFINE_PROP_BIT64("x-smi-cpu-hotunplug", ICH9LPCState, smi_host_features, + ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 3106bbea33..28266a3a35 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -553,17 +553,6 @@ static HotplugHandler *s390_get_hotplug_handler(MachineState *machine, return NULL; } -static void s390_hot_add_cpu(MachineState *machine, - const int64_t id, Error **errp) -{ - ObjectClass *oc; - - g_assert(machine->possible_cpus->cpus[0].cpu); - oc = OBJECT_CLASS(CPU_GET_CLASS(machine->possible_cpus->cpus[0].cpu)); - - s390x_new_cpu(object_class_get_name(oc), id, errp); -} - static void s390_nmi(NMIState *n, int cpu_index, Error **errp) { CPUState *cs = qemu_get_cpu(cpu_index); @@ -604,7 +593,6 @@ static void ccw_machine_class_init(ObjectClass *oc, void *data) s390mc->hpage_1m_allowed = true; mc->init = ccw_init; mc->reset = s390_machine_reset; - mc->hot_add_cpu = s390_hot_add_cpu; mc->block_default_type = IF_VIRTIO; mc->no_cdrom = 1; mc->no_floppy = 1; diff --git a/hw/s390x/vhost-vsock-ccw.c b/hw/s390x/vhost-vsock-ccw.c index 0822ecca89..246416a8f9 100644 --- a/hw/s390x/vhost-vsock-ccw.c +++ b/hw/s390x/vhost-vsock-ccw.c @@ -40,9 +40,21 @@ static void vhost_vsock_ccw_class_init(ObjectClass *klass, void *data) static void vhost_vsock_ccw_instance_init(Object *obj) { VHostVSockCCWState *dev = VHOST_VSOCK_CCW(obj); + VirtioCcwDevice *ccw_dev = VIRTIO_CCW_DEVICE(obj); + VirtIODevice *virtio_dev; virtio_instance_init_common(obj, &dev->vdev, sizeof(dev->vdev), TYPE_VHOST_VSOCK); + + virtio_dev = VIRTIO_DEVICE(&dev->vdev); + + /* + * To avoid migration issues, we force virtio version 1 only when + * legacy check is enabled in the new machine types (>= 5.1). + */ + if (!virtio_legacy_check_disabled(virtio_dev)) { + ccw_dev->force_revision_1 = true; + } } static const TypeInfo vhost_vsock_ccw_info = { diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 8d140dc50f..4582e94ae7 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -1122,9 +1122,18 @@ static void virtio_ccw_device_plugged(DeviceState *d, Error **errp) } if (!virtio_ccw_rev_max(dev) && !virtio_legacy_allowed(vdev)) { - error_setg(errp, "Invalid value of property max_rev " - "(is %d expected >= 1)", virtio_ccw_rev_max(dev)); - return; + /* + * To avoid migration issues, we allow legacy mode when legacy + * check is disabled in the old machine types (< 5.1). + */ + if (virtio_legacy_check_disabled(vdev)) { + warn_report("device requires revision >= 1, but for backward " + "compatibility max_revision=0 is allowed"); + } else { + error_setg(errp, "Invalid value of property max_rev " + "(is %d expected >= 1)", virtio_ccw_rev_max(dev)); + return; + } } if (virtio_get_num_queues(vdev) > VIRTIO_QUEUE_MAX) { diff --git a/hw/smbios/smbios.c b/hw/smbios/smbios.c index 7cc950b41c..8b30906e50 100644 --- a/hw/smbios/smbios.c +++ b/hw/smbios/smbios.c @@ -110,7 +110,7 @@ static struct { static struct { size_t nvalues; - const char **values; + char **values; } type11; static struct { @@ -314,6 +314,11 @@ static const QemuOptDesc qemu_smbios_type11_opts[] = { .type = QEMU_OPT_STRING, .help = "OEM string data", }, + { + .name = "path", + .type = QEMU_OPT_STRING, + .help = "OEM string data from file", + }, }; static const QemuOptDesc qemu_smbios_type17_opts[] = { @@ -360,6 +365,13 @@ static void smbios_register_config(void) opts_init(smbios_register_config); +/* + * The SMBIOS 2.1 "structure table length" field in the + * entry point uses a 16-bit integer, so we're limited + * in total table size + */ +#define SMBIOS_21_MAX_TABLES_LEN 0xffff + static void smbios_validate_table(MachineState *ms) { uint32_t expect_t4_count = smbios_legacy ? @@ -370,6 +382,13 @@ static void smbios_validate_table(MachineState *ms) expect_t4_count, smbios_type4_count); exit(1); } + + if (smbios_ep_type == SMBIOS_ENTRY_POINT_21 && + smbios_tables_len > SMBIOS_21_MAX_TABLES_LEN) { + error_report("SMBIOS 2.1 table length %zu exceeds %d", + smbios_tables_len, SMBIOS_21_MAX_TABLES_LEN); + exit(1); + } } @@ -641,6 +660,8 @@ static void smbios_build_type_11_table(void) for (i = 0; i < type11.nvalues; i++) { SMBIOS_TABLE_SET_STR_LIST(11, type11.values[i]); + g_free(type11.values[i]); + type11.values[i] = NULL; } SMBIOS_BUILD_TABLE_POST; @@ -940,9 +961,8 @@ static void save_opt(const char **dest, QemuOpts *opts, const char *name) struct opt_list { - const char *name; size_t *ndest; - const char ***dest; + char ***dest; }; static int save_opt_one(void *opaque, @@ -951,23 +971,60 @@ static int save_opt_one(void *opaque, { struct opt_list *opt = opaque; - if (!g_str_equal(name, opt->name)) { - return 0; + if (g_str_equal(name, "path")) { + g_autoptr(GByteArray) data = g_byte_array_new(); + g_autofree char *buf = g_new(char, 4096); + ssize_t ret; + int fd = qemu_open(value, O_RDONLY, errp); + if (fd < 0) { + return -1; + } + + while (1) { + ret = read(fd, buf, 4096); + if (ret == 0) { + break; + } + if (ret < 0) { + error_setg(errp, "Unable to read from %s: %s", + value, strerror(errno)); + return -1; + } + if (memchr(buf, '\0', ret)) { + error_setg(errp, "NUL in OEM strings value in %s", value); + return -1; + } + g_byte_array_append(data, (guint8 *)buf, ret); + } + + close(fd); + + *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1); + (*opt->dest)[*opt->ndest] = (char *)g_byte_array_free(data, FALSE); + (*opt->ndest)++; + data = NULL; + } else if (g_str_equal(name, "value")) { + *opt->dest = g_renew(char *, *opt->dest, (*opt->ndest) + 1); + (*opt->dest)[*opt->ndest] = g_strdup(value); + (*opt->ndest)++; + } else if (!g_str_equal(name, "type")) { + error_setg(errp, "Unexpected option %s", name); + return -1; } - *opt->dest = g_renew(const char *, *opt->dest, (*opt->ndest) + 1); - (*opt->dest)[*opt->ndest] = value; - (*opt->ndest)++; return 0; } -static void save_opt_list(size_t *ndest, const char ***dest, - QemuOpts *opts, const char *name) +static bool save_opt_list(size_t *ndest, char ***dest, QemuOpts *opts, + Error **errp) { struct opt_list opt = { - name, ndest, dest, + ndest, dest, }; - qemu_opt_foreach(opts, save_opt_one, &opt, NULL); + if (!qemu_opt_foreach(opts, save_opt_one, &opt, errp)) { + return false; + } + return true; } void smbios_entry_add(QemuOpts *opts, Error **errp) @@ -1149,7 +1206,9 @@ void smbios_entry_add(QemuOpts *opts, Error **errp) if (!qemu_opts_validate(opts, qemu_smbios_type11_opts, errp)) { return; } - save_opt_list(&type11.nvalues, &type11.values, opts, "value"); + if (!save_opt_list(&type11.nvalues, &type11.values, opts, errp)) { + return; + } return; case 17: if (!qemu_opts_validate(opts, qemu_smbios_type17_opts, errp)) { diff --git a/hw/usb/Kconfig b/hw/usb/Kconfig index 3fc8fbe3c7..4dd2ba9630 100644 --- a/hw/usb/Kconfig +++ b/hw/usb/Kconfig @@ -36,12 +36,23 @@ config USB_XHCI depends on PCI select USB +config USB_XHCI_PCI + bool + default y if PCI_DEVICES + depends on PCI + select USB_XHCI + config USB_XHCI_NEC bool default y if PCI_DEVICES depends on PCI select USB_XHCI +config USB_XHCI_SYSBUS + bool + default y if USB_XHCI + select USB + config USB_MUSB bool select USB diff --git a/hw/usb/ccid-card-emulated.c b/hw/usb/ccid-card-emulated.c index 5e4649d367..2d566f7db1 100644 --- a/hw/usb/ccid-card-emulated.c +++ b/hw/usb/ccid-card-emulated.c @@ -30,6 +30,7 @@ #include <libcacard.h> #include "qemu/thread.h" +#include "qemu/lockable.h" #include "qemu/main-loop.h" #include "qemu/module.h" #include "ccid.h" @@ -244,34 +245,34 @@ static void *handle_apdu_thread(void* arg) card->quit_apdu_thread = 0; /* debugging */ break; } - qemu_mutex_lock(&card->vreader_mutex); - while (!QSIMPLEQ_EMPTY(&card->guest_apdu_list)) { - event = QSIMPLEQ_FIRST(&card->guest_apdu_list); - assert((unsigned long)event > 1000); - QSIMPLEQ_REMOVE_HEAD(&card->guest_apdu_list, entry); - if (event->p.data.type != EMUL_GUEST_APDU) { - DPRINTF(card, 1, "unexpected message in handle_apdu_thread\n"); - g_free(event); - continue; - } - if (card->reader == NULL) { - DPRINTF(card, 1, "reader is NULL\n"); + WITH_QEMU_LOCK_GUARD(&card->vreader_mutex) { + while (!QSIMPLEQ_EMPTY(&card->guest_apdu_list)) { + event = QSIMPLEQ_FIRST(&card->guest_apdu_list); + assert((unsigned long)event > 1000); + QSIMPLEQ_REMOVE_HEAD(&card->guest_apdu_list, entry); + if (event->p.data.type != EMUL_GUEST_APDU) { + DPRINTF(card, 1, "unexpected message in handle_apdu_thread\n"); + g_free(event); + continue; + } + if (card->reader == NULL) { + DPRINTF(card, 1, "reader is NULL\n"); + g_free(event); + continue; + } + recv_len = sizeof(recv_data); + reader_status = vreader_xfr_bytes(card->reader, + event->p.data.data, event->p.data.len, + recv_data, &recv_len); + DPRINTF(card, 2, "got back apdu of length %d\n", recv_len); + if (reader_status == VREADER_OK) { + emulated_push_response_apdu(card, recv_data, recv_len); + } else { + emulated_push_error(card, reader_status); + } g_free(event); - continue; } - recv_len = sizeof(recv_data); - reader_status = vreader_xfr_bytes(card->reader, - event->p.data.data, event->p.data.len, - recv_data, &recv_len); - DPRINTF(card, 2, "got back apdu of length %d\n", recv_len); - if (reader_status == VREADER_OK) { - emulated_push_response_apdu(card, recv_data, recv_len); - } else { - emulated_push_error(card, reader_status); - } - g_free(event); } - qemu_mutex_unlock(&card->vreader_mutex); } return NULL; } @@ -365,7 +366,7 @@ static void card_event_handler(EventNotifier *notifier) EmulEvent *event, *next; event_notifier_test_and_clear(&card->notifier); - qemu_mutex_lock(&card->event_list_mutex); + QEMU_LOCK_GUARD(&card->event_list_mutex); QSIMPLEQ_FOREACH_SAFE(event, &card->event_list, entry, next) { DPRINTF(card, 2, "event %s\n", emul_event_to_string(event->p.gen.type)); switch (event->p.gen.type) { @@ -398,7 +399,6 @@ static void card_event_handler(EventNotifier *notifier) g_free(event); } QSIMPLEQ_INIT(&card->event_list); - qemu_mutex_unlock(&card->event_list_mutex); } static int init_event_notifier(EmulatedState *card, Error **errp) diff --git a/hw/usb/hcd-xhci-nec.c b/hw/usb/hcd-xhci-nec.c index e6a5a22b6d..2efa6fa0f8 100644 --- a/hw/usb/hcd-xhci-nec.c +++ b/hw/usb/hcd-xhci-nec.c @@ -25,17 +25,17 @@ #include "hw/pci/pci.h" #include "hw/qdev-properties.h" -#include "hcd-xhci.h" +#include "hcd-xhci-pci.h" static Property nec_xhci_properties[] = { - DEFINE_PROP_ON_OFF_AUTO("msi", XHCIState, msi, ON_OFF_AUTO_AUTO), - DEFINE_PROP_ON_OFF_AUTO("msix", XHCIState, msix, ON_OFF_AUTO_AUTO), - DEFINE_PROP_BIT("superspeed-ports-first", - XHCIState, flags, XHCI_FLAG_SS_FIRST, true), - DEFINE_PROP_BIT("force-pcie-endcap", XHCIState, flags, + DEFINE_PROP_ON_OFF_AUTO("msi", XHCIPciState, msi, ON_OFF_AUTO_AUTO), + DEFINE_PROP_ON_OFF_AUTO("msix", XHCIPciState, msix, ON_OFF_AUTO_AUTO), + DEFINE_PROP_BIT("superspeed-ports-first", XHCIPciState, + xhci.flags, XHCI_FLAG_SS_FIRST, true), + DEFINE_PROP_BIT("force-pcie-endcap", XHCIPciState, xhci.flags, XHCI_FLAG_FORCE_PCIE_ENDCAP, false), - DEFINE_PROP_UINT32("intrs", XHCIState, numintrs, MAXINTRS), - DEFINE_PROP_UINT32("slots", XHCIState, numslots, MAXSLOTS), + DEFINE_PROP_UINT32("intrs", XHCIPciState, xhci.numintrs, MAXINTRS), + DEFINE_PROP_UINT32("slots", XHCIPciState, xhci.numslots, MAXSLOTS), DEFINE_PROP_END_OF_LIST(), }; @@ -52,7 +52,7 @@ static void nec_xhci_class_init(ObjectClass *klass, void *data) static const TypeInfo nec_xhci_info = { .name = TYPE_NEC_XHCI, - .parent = TYPE_XHCI, + .parent = TYPE_XHCI_PCI, .class_init = nec_xhci_class_init, }; diff --git a/hw/usb/hcd-xhci-pci.c b/hw/usb/hcd-xhci-pci.c new file mode 100644 index 0000000000..a6d746e1da --- /dev/null +++ b/hw/usb/hcd-xhci-pci.c @@ -0,0 +1,261 @@ +/* + * USB xHCI controller with PCI bus emulation + * + * SPDX-FileCopyrightText: 2011 Securiforest + * SPDX-FileContributor: Hector Martin <hector@marcansoft.com> + * SPDX-sourceInfo: Based on usb-ohci.c, emulates Renesas NEC USB 3.0 + * SPDX-FileCopyrightText: 2020 Xilinx + * SPDX-FileContributor: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> + * SPDX-sourceInfo: Moved the pci specific content for hcd-xhci.c to + * hcd-xhci-pci.c + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "qemu/osdep.h" +#include "hw/pci/pci.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "hw/pci/msi.h" +#include "hw/pci/msix.h" +#include "hcd-xhci-pci.h" +#include "trace.h" +#include "qapi/error.h" + +#define OFF_MSIX_TABLE 0x3000 +#define OFF_MSIX_PBA 0x3800 + +static void xhci_pci_intr_update(XHCIState *xhci, int n, bool enable) +{ + XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); + PCIDevice *pci_dev = PCI_DEVICE(s); + + if (!msix_enabled(pci_dev)) { + return; + } + if (enable == !!xhci->intr[n].msix_used) { + return; + } + if (enable) { + trace_usb_xhci_irq_msix_use(n); + msix_vector_use(pci_dev, n); + xhci->intr[n].msix_used = true; + } else { + trace_usb_xhci_irq_msix_unuse(n); + msix_vector_unuse(pci_dev, n); + xhci->intr[n].msix_used = false; + } +} + +static void xhci_pci_intr_raise(XHCIState *xhci, int n, bool level) +{ + XHCIPciState *s = container_of(xhci, XHCIPciState, xhci); + PCIDevice *pci_dev = PCI_DEVICE(s); + + if (n == 0 && + !(msix_enabled(pci_dev) || + msi_enabled(pci_dev))) { + pci_set_irq(pci_dev, level); + } + if (msix_enabled(pci_dev)) { + msix_notify(pci_dev, n); + return; + } + + if (msi_enabled(pci_dev)) { + msi_notify(pci_dev, n); + return; + } +} + +static void xhci_pci_reset(DeviceState *dev) +{ + XHCIPciState *s = XHCI_PCI(dev); + + device_legacy_reset(DEVICE(&s->xhci)); +} + +static int xhci_pci_vmstate_post_load(void *opaque, int version_id) +{ + XHCIPciState *s = XHCI_PCI(opaque); + PCIDevice *pci_dev = PCI_DEVICE(s); + int intr; + + for (intr = 0; intr < s->xhci.numintrs; intr++) { + if (s->xhci.intr[intr].msix_used) { + msix_vector_use(pci_dev, intr); + } else { + msix_vector_unuse(pci_dev, intr); + } + } + return 0; +} + +static void usb_xhci_pci_realize(struct PCIDevice *dev, Error **errp) +{ + int ret; + Error *err = NULL; + XHCIPciState *s = XHCI_PCI(dev); + + dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ + dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ + dev->config[PCI_CACHE_LINE_SIZE] = 0x10; + dev->config[0x60] = 0x30; /* release number */ + + object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL); + s->xhci.intr_update = xhci_pci_intr_update; + s->xhci.intr_raise = xhci_pci_intr_raise; + object_property_set_bool(OBJECT(&s->xhci), "realized", true, &err); + if (err) { + error_propagate(errp, err); + return; + } + if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) { + s->xhci.nec_quirks = true; + } + + if (s->msi != ON_OFF_AUTO_OFF) { + ret = msi_init(dev, 0x70, s->xhci.numintrs, true, false, &err); + /* + * Any error other than -ENOTSUP(board's MSI support is broken) + * is a programming error + */ + assert(!ret || ret == -ENOTSUP); + if (ret && s->msi == ON_OFF_AUTO_ON) { + /* Can't satisfy user's explicit msi=on request, fail */ + error_append_hint(&err, "You have to use msi=auto (default) or " + "msi=off with this machine type.\n"); + error_propagate(errp, err); + return; + } + assert(!err || s->msi == ON_OFF_AUTO_AUTO); + /* With msi=auto, we fall back to MSI off silently */ + error_free(err); + } + pci_register_bar(dev, 0, + PCI_BASE_ADDRESS_SPACE_MEMORY | + PCI_BASE_ADDRESS_MEM_TYPE_64, + &s->xhci.mem); + + if (pci_bus_is_express(pci_get_bus(dev)) || + xhci_get_flag(&s->xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { + ret = pcie_endpoint_cap_init(dev, 0xa0); + assert(ret > 0); + } + + if (s->msix != ON_OFF_AUTO_OFF) { + /* TODO check for errors, and should fail when msix=on */ + msix_init(dev, s->xhci.numintrs, + &s->xhci.mem, 0, OFF_MSIX_TABLE, + &s->xhci.mem, 0, OFF_MSIX_PBA, + 0x90, NULL); + } + s->xhci.as = pci_get_address_space(dev); +} + +static void usb_xhci_pci_exit(PCIDevice *dev) +{ + XHCIPciState *s = XHCI_PCI(dev); + /* destroy msix memory region */ + if (dev->msix_table && dev->msix_pba + && dev->msix_entry_used) { + msix_uninit(dev, &s->xhci.mem, &s->xhci.mem); + } +} + +static const VMStateDescription vmstate_xhci_pci = { + .name = "xhci", + .version_id = 1, + .post_load = xhci_pci_vmstate_post_load, + .fields = (VMStateField[]) { + VMSTATE_PCI_DEVICE(parent_obj, XHCIPciState), + VMSTATE_MSIX(parent_obj, XHCIPciState), + VMSTATE_STRUCT(xhci, XHCIPciState, 1, vmstate_xhci, XHCIState), + VMSTATE_END_OF_LIST() + } +}; + +static void xhci_instance_init(Object *obj) +{ + XHCIPciState *s = XHCI_PCI(obj); + /* + * QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command + * line, therefore, no need to wait to realize like other devices + */ + PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS; + object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI); + qdev_alias_all_properties(DEVICE(&s->xhci), obj); +} + +static void xhci_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = xhci_pci_reset; + dc->vmsd = &vmstate_xhci_pci; + set_bit(DEVICE_CATEGORY_USB, dc->categories); + k->realize = usb_xhci_pci_realize; + k->exit = usb_xhci_pci_exit; + k->class_id = PCI_CLASS_SERIAL_USB; +} + +static const TypeInfo xhci_pci_info = { + .name = TYPE_XHCI_PCI, + .parent = TYPE_PCI_DEVICE, + .instance_size = sizeof(XHCIPciState), + .class_init = xhci_class_init, + .instance_init = xhci_instance_init, + .abstract = true, + .interfaces = (InterfaceInfo[]) { + { INTERFACE_PCIE_DEVICE }, + { INTERFACE_CONVENTIONAL_PCI_DEVICE }, + { } + }, +}; + +static void qemu_xhci_class_init(ObjectClass *klass, void *data) +{ + PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + + k->vendor_id = PCI_VENDOR_ID_REDHAT; + k->device_id = PCI_DEVICE_ID_REDHAT_XHCI; + k->revision = 0x01; +} + +static void qemu_xhci_instance_init(Object *obj) +{ + XHCIPciState *s = XHCI_PCI(obj); + XHCIState *xhci = &s->xhci; + + s->msi = ON_OFF_AUTO_OFF; + s->msix = ON_OFF_AUTO_AUTO; + xhci->numintrs = MAXINTRS; + xhci->numslots = MAXSLOTS; + xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST); +} + +static const TypeInfo qemu_xhci_info = { + .name = TYPE_QEMU_XHCI, + .parent = TYPE_XHCI_PCI, + .class_init = qemu_xhci_class_init, + .instance_init = qemu_xhci_instance_init, +}; + +static void xhci_register_types(void) +{ + type_register_static(&xhci_pci_info); + type_register_static(&qemu_xhci_info); +} + +type_init(xhci_register_types) diff --git a/hw/usb/hcd-xhci-pci.h b/hw/usb/hcd-xhci-pci.h new file mode 100644 index 0000000000..aa2e890627 --- /dev/null +++ b/hw/usb/hcd-xhci-pci.h @@ -0,0 +1,44 @@ +/* + * USB xHCI controller emulation + * + * Copyright (c) 2011 Securiforest + * Date: 2011-05-11 ; Author: Hector Martin <hector@marcansoft.com> + * Based on usb-ohci.c, emulates Renesas NEC USB 3.0 + * Date: 2020-01-1; Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> + * PCI hooks are moved from XHCIState to XHCIPciState + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_USB_HCD_XHCI_PCI_H +#define HW_USB_HCD_XHCI_PCI_H + +#include "hw/usb.h" +#include "hcd-xhci.h" + +#define TYPE_XHCI_PCI "pci-xhci" +#define XHCI_PCI(obj) \ + OBJECT_CHECK(XHCIPciState, (obj), TYPE_XHCI_PCI) + + +typedef struct XHCIPciState { + /*< private >*/ + PCIDevice parent_obj; + /*< public >*/ + XHCIState xhci; + OnOffAuto msi; + OnOffAuto msix; +} XHCIPciState; + +#endif diff --git a/hw/usb/hcd-xhci-sysbus.c b/hw/usb/hcd-xhci-sysbus.c new file mode 100644 index 0000000000..852ca5103b --- /dev/null +++ b/hw/usb/hcd-xhci-sysbus.c @@ -0,0 +1,109 @@ +/* + * USB xHCI controller for system-bus interface + * Based on hcd-echi-sysbus.c + + * SPDX-FileCopyrightText: 2020 Xilinx + * SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ +#include "qemu/osdep.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "trace.h" +#include "qapi/error.h" +#include "hcd-xhci-sysbus.h" +#include "hw/irq.h" + +static void xhci_sysbus_intr_raise(XHCIState *xhci, int n, bool level) +{ + XHCISysbusState *s = container_of(xhci, XHCISysbusState, xhci); + + qemu_set_irq(s->irq[n], level); +} + +void xhci_sysbus_reset(DeviceState *dev) +{ + XHCISysbusState *s = XHCI_SYSBUS(dev); + + device_legacy_reset(DEVICE(&s->xhci)); +} + +static void xhci_sysbus_realize(DeviceState *dev, Error **errp) +{ + XHCISysbusState *s = XHCI_SYSBUS(dev); + Error *err = NULL; + + object_property_set_link(OBJECT(&s->xhci), "host", OBJECT(s), NULL); + object_property_set_bool(OBJECT(&s->xhci), "realized", true, &err); + if (err) { + error_propagate(errp, err); + return; + } + s->irq = g_new0(qemu_irq, s->xhci.numintrs); + qdev_init_gpio_out_named(dev, s->irq, SYSBUS_DEVICE_GPIO_IRQ, + s->xhci.numintrs); + if (s->xhci.dma_mr) { + s->xhci.as = g_malloc0(sizeof(AddressSpace)); + address_space_init(s->xhci.as, s->xhci.dma_mr, NULL); + } else { + s->xhci.as = &address_space_memory; + } + + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->xhci.mem); +} + +static void xhci_sysbus_instance_init(Object *obj) +{ + XHCISysbusState *s = XHCI_SYSBUS(obj); + + object_initialize_child(obj, "xhci-core", &s->xhci, TYPE_XHCI); + qdev_alias_all_properties(DEVICE(&s->xhci), obj); + + object_property_add_link(obj, "dma", TYPE_MEMORY_REGION, + (Object **)&s->xhci.dma_mr, + qdev_prop_allow_set_link_before_realize, + OBJ_PROP_LINK_STRONG); + s->xhci.intr_update = NULL; + s->xhci.intr_raise = xhci_sysbus_intr_raise; +} + +static Property xhci_sysbus_props[] = { + DEFINE_PROP_UINT32("intrs", XHCISysbusState, xhci.numintrs, MAXINTRS), + DEFINE_PROP_UINT32("slots", XHCISysbusState, xhci.numslots, MAXSLOTS), + DEFINE_PROP_END_OF_LIST(), +}; + +static const VMStateDescription vmstate_xhci_sysbus = { + .name = "xhci-sysbus", + .version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_STRUCT(xhci, XHCISysbusState, 1, vmstate_xhci, XHCIState), + VMSTATE_END_OF_LIST() + } +}; + +static void xhci_sysbus_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = xhci_sysbus_reset; + dc->realize = xhci_sysbus_realize; + dc->vmsd = &vmstate_xhci_sysbus; + device_class_set_props(dc, xhci_sysbus_props); +} + +static const TypeInfo xhci_sysbus_info = { + .name = TYPE_XHCI_SYSBUS, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(XHCISysbusState), + .class_init = xhci_sysbus_class_init, + .instance_init = xhci_sysbus_instance_init +}; + +static void xhci_sysbus_register_types(void) +{ + type_register_static(&xhci_sysbus_info); +} + +type_init(xhci_sysbus_register_types); diff --git a/hw/usb/hcd-xhci-sysbus.h b/hw/usb/hcd-xhci-sysbus.h new file mode 100644 index 0000000000..a308753ceb --- /dev/null +++ b/hw/usb/hcd-xhci-sysbus.h @@ -0,0 +1,32 @@ +/* + * USB xHCI controller for system-bus interface + * + * SPDX-FileCopyrightText: 2020 Xilinx + * SPDX-FileContributor: Author: Sai Pavan Boddu <sai.pavan.boddu@xilinx.com> + * SPDX-sourceInfo: Based on hcd-echi-sysbus + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef HW_USB_HCD_XHCI_SYSBUS_H +#define HW_USB_HCD_XHCI_SYSBUS_H + +#include "hw/usb.h" +#include "hcd-xhci.h" +#include "hw/sysbus.h" + +#define TYPE_XHCI_SYSBUS "sysbus-xhci" +#define XHCI_SYSBUS(obj) \ + OBJECT_CHECK(XHCISysbusState, (obj), TYPE_XHCI_SYSBUS) + + +typedef struct XHCISysbusState { + /*< private >*/ + SysBusDevice parent_obj; + /*< public >*/ + XHCIState xhci; + qemu_irq *irq; +} XHCISysbusState; + +void xhci_sysbus_reset(DeviceState *dev); +#endif diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 46a2186d91..5e8bed9ef9 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -23,12 +23,8 @@ #include "qemu/timer.h" #include "qemu/module.h" #include "qemu/queue.h" -#include "hw/usb.h" #include "migration/vmstate.h" -#include "hw/pci/pci.h" #include "hw/qdev-properties.h" -#include "hw/pci/msi.h" -#include "hw/pci/msix.h" #include "trace.h" #include "qapi/error.h" @@ -57,8 +53,6 @@ #define OFF_OPER LEN_CAP #define OFF_RUNTIME 0x1000 #define OFF_DOORBELL 0x2000 -#define OFF_MSIX_TABLE 0x3000 -#define OFF_MSIX_PBA 0x3800 /* must be power of 2 */ #define LEN_REGS 0x4000 @@ -429,12 +423,12 @@ static const char *ep_state_name(uint32_t state) ARRAY_SIZE(ep_state_names)); } -static bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) +bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit) { return xhci->flags & (1 << bit); } -static void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit) +void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit) { xhci->flags |= (1 << bit); } @@ -495,7 +489,7 @@ static inline void xhci_dma_read_u32s(XHCIState *xhci, dma_addr_t addr, assert((len % sizeof(uint32_t)) == 0); - pci_dma_read(PCI_DEVICE(xhci), addr, buf, len); + dma_memory_read(xhci->as, addr, buf, len); for (i = 0; i < (len / sizeof(uint32_t)); i++) { buf[i] = le32_to_cpu(buf[i]); @@ -515,7 +509,7 @@ static inline void xhci_dma_write_u32s(XHCIState *xhci, dma_addr_t addr, for (i = 0; i < n; i++) { tmp[i] = cpu_to_le32(buf[i]); } - pci_dma_write(PCI_DEVICE(xhci), addr, tmp, len); + dma_memory_write(xhci->as, addr, tmp, len); } static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) @@ -548,54 +542,28 @@ static XHCIPort *xhci_lookup_port(XHCIState *xhci, struct USBPort *uport) return &xhci->ports[index]; } -static void xhci_intx_update(XHCIState *xhci) +static void xhci_intr_update(XHCIState *xhci, int v) { - PCIDevice *pci_dev = PCI_DEVICE(xhci); int level = 0; - if (msix_enabled(pci_dev) || - msi_enabled(pci_dev)) { - return; - } - - if (xhci->intr[0].iman & IMAN_IP && - xhci->intr[0].iman & IMAN_IE && - xhci->usbcmd & USBCMD_INTE) { - level = 1; - } - - trace_usb_xhci_irq_intx(level); - pci_set_irq(pci_dev, level); -} - -static void xhci_msix_update(XHCIState *xhci, int v) -{ - PCIDevice *pci_dev = PCI_DEVICE(xhci); - bool enabled; - - if (!msix_enabled(pci_dev)) { - return; - } - - enabled = xhci->intr[v].iman & IMAN_IE; - if (enabled == xhci->intr[v].msix_used) { - return; + if (v == 0) { + if (xhci->intr[0].iman & IMAN_IP && + xhci->intr[0].iman & IMAN_IE && + xhci->usbcmd & USBCMD_INTE) { + level = 1; + } + if (xhci->intr_raise) { + xhci->intr_raise(xhci, 0, level); + } } - - if (enabled) { - trace_usb_xhci_irq_msix_use(v); - msix_vector_use(pci_dev, v); - xhci->intr[v].msix_used = true; - } else { - trace_usb_xhci_irq_msix_unuse(v); - msix_vector_unuse(pci_dev, v); - xhci->intr[v].msix_used = false; + if (xhci->intr_update) { + xhci->intr_update(xhci, v, + xhci->intr[v].iman & IMAN_IE); } } static void xhci_intr_raise(XHCIState *xhci, int v) { - PCIDevice *pci_dev = PCI_DEVICE(xhci); bool pending = (xhci->intr[v].erdp_low & ERDP_EHB); xhci->intr[v].erdp_low |= ERDP_EHB; @@ -612,22 +580,8 @@ static void xhci_intr_raise(XHCIState *xhci, int v) if (!(xhci->usbcmd & USBCMD_INTE)) { return; } - - if (msix_enabled(pci_dev)) { - trace_usb_xhci_irq_msix(v); - msix_notify(pci_dev, v); - return; - } - - if (msi_enabled(pci_dev)) { - trace_usb_xhci_irq_msi(v); - msi_notify(pci_dev, v); - return; - } - - if (v == 0) { - trace_usb_xhci_irq_intx(1); - pci_irq_assert(pci_dev); + if (xhci->intr_raise) { + xhci->intr_raise(xhci, v, true); } } @@ -644,7 +598,6 @@ static void xhci_die(XHCIState *xhci) static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) { - PCIDevice *pci_dev = PCI_DEVICE(xhci); XHCIInterrupter *intr = &xhci->intr[v]; XHCITRB ev_trb; dma_addr_t addr; @@ -663,7 +616,7 @@ static void xhci_write_event(XHCIState *xhci, XHCIEvent *event, int v) ev_trb.status, ev_trb.control); addr = intr->er_start + TRB_SIZE*intr->er_ep_idx; - pci_dma_write(pci_dev, addr, &ev_trb, TRB_SIZE); + dma_memory_write(xhci->as, addr, &ev_trb, TRB_SIZE); intr->er_ep_idx++; if (intr->er_ep_idx >= intr->er_size) { @@ -720,12 +673,11 @@ static void xhci_ring_init(XHCIState *xhci, XHCIRing *ring, static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, dma_addr_t *addr) { - PCIDevice *pci_dev = PCI_DEVICE(xhci); uint32_t link_cnt = 0; while (1) { TRBType type; - pci_dma_read(pci_dev, ring->dequeue, trb, TRB_SIZE); + dma_memory_read(xhci->as, ring->dequeue, trb, TRB_SIZE); trb->addr = ring->dequeue; trb->ccs = ring->ccs; le64_to_cpus(&trb->parameter); @@ -762,7 +714,6 @@ static TRBType xhci_ring_fetch(XHCIState *xhci, XHCIRing *ring, XHCITRB *trb, static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) { - PCIDevice *pci_dev = PCI_DEVICE(xhci); XHCITRB trb; int length = 0; dma_addr_t dequeue = ring->dequeue; @@ -773,7 +724,7 @@ static int xhci_ring_chain_length(XHCIState *xhci, const XHCIRing *ring) while (1) { TRBType type; - pci_dma_read(pci_dev, dequeue, &trb, TRB_SIZE); + dma_memory_read(xhci->as, dequeue, &trb, TRB_SIZE); le64_to_cpus(&trb.parameter); le32_to_cpus(&trb.status); le32_to_cpus(&trb.control); @@ -828,7 +779,7 @@ static void xhci_er_reset(XHCIState *xhci, int v) xhci_die(xhci); return; } - pci_dma_read(PCI_DEVICE(xhci), erstba, &seg, sizeof(seg)); + dma_memory_read(xhci->as, erstba, &seg, sizeof(seg)); le32_to_cpus(&seg.addr_low); le32_to_cpus(&seg.addr_high); le32_to_cpus(&seg.size); @@ -1440,7 +1391,7 @@ static int xhci_xfer_create_sgl(XHCITransfer *xfer, int in_xfer) int i; xfer->int_req = false; - pci_dma_sglist_init(&xfer->sgl, PCI_DEVICE(xhci), xfer->trb_count); + qemu_sglist_init(&xfer->sgl, DEVICE(xhci), xfer->trb_count, xhci->as); for (i = 0; i < xfer->trb_count; i++) { XHCITRB *trb = &xfer->trbs[i]; dma_addr_t addr; @@ -2104,7 +2055,7 @@ static TRBCCode xhci_address_slot(XHCIState *xhci, unsigned int slotid, assert(slotid >= 1 && slotid <= xhci->numslots); dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); - poctx = ldq_le_pci_dma(PCI_DEVICE(xhci), dcbaap + 8 * slotid); + poctx = ldq_le_dma(xhci->as, dcbaap + 8 * slotid); ictx = xhci_mask64(pictx); octx = xhci_mask64(poctx); @@ -2442,7 +2393,7 @@ static TRBCCode xhci_get_port_bandwidth(XHCIState *xhci, uint64_t pctx) /* TODO: actually implement real values here */ bw_ctx[0] = 0; memset(&bw_ctx[1], 80, xhci->numports); /* 80% */ - pci_dma_write(PCI_DEVICE(xhci), ctx, bw_ctx, sizeof(bw_ctx)); + dma_memory_write(xhci->as, ctx, bw_ctx, sizeof(bw_ctx)); return CC_SUCCESS; } @@ -2721,7 +2672,6 @@ static void xhci_reset(DeviceState *dev) xhci->intr[i].erstba_high = 0; xhci->intr[i].erdp_low = 0; xhci->intr[i].erdp_high = 0; - xhci->intr[i].msix_used = 0; xhci->intr[i].er_ep_idx = 0; xhci->intr[i].er_pcs = 1; @@ -2943,8 +2893,7 @@ static uint64_t xhci_oper_read(void *ptr, hwaddr reg, unsigned size) static void xhci_oper_write(void *ptr, hwaddr reg, uint64_t val, unsigned size) { - XHCIState *xhci = ptr; - DeviceState *d = DEVICE(ptr); + XHCIState *xhci = XHCI(ptr); trace_usb_xhci_oper_write(reg, val); @@ -2966,15 +2915,15 @@ static void xhci_oper_write(void *ptr, hwaddr reg, xhci->usbcmd = val & 0xc0f; xhci_mfwrap_update(xhci); if (val & USBCMD_HCRST) { - xhci_reset(d); + xhci_reset(DEVICE(xhci)); } - xhci_intx_update(xhci); + xhci_intr_update(xhci, 0); break; case 0x04: /* USBSTS */ /* these bits are write-1-to-clear */ xhci->usbsts &= ~(val & (USBSTS_HSE|USBSTS_EINT|USBSTS_PCD|USBSTS_SRE)); - xhci_intx_update(xhci); + xhci_intr_update(xhci, 0); break; case 0x14: /* DNCTRL */ @@ -3077,10 +3026,7 @@ static void xhci_runtime_write(void *ptr, hwaddr reg, } intr->iman &= ~IMAN_IE; intr->iman |= val & IMAN_IE; - if (v == 0) { - xhci_intx_update(xhci); - } - xhci_msix_update(xhci, v); + xhci_intr_update(xhci, v); break; case 0x04: /* IMOD */ intr->imod = val; @@ -3325,7 +3271,6 @@ static USBBusOps xhci_bus_ops = { static void usb_xhci_init(XHCIState *xhci) { - DeviceState *dev = DEVICE(xhci); XHCIPort *port; unsigned int i, usbports, speedmask; @@ -3340,7 +3285,7 @@ static void usb_xhci_init(XHCIState *xhci) usbports = MAX(xhci->numports_2, xhci->numports_3); xhci->numports = xhci->numports_2 + xhci->numports_3; - usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, dev); + usb_bus_new(&xhci->bus, sizeof(xhci->bus), &xhci_bus_ops, xhci->hostOpaque); for (i = 0; i < usbports; i++) { speedmask = 0; @@ -3380,21 +3325,12 @@ static void usb_xhci_init(XHCIState *xhci) } } -static void usb_xhci_realize(struct PCIDevice *dev, Error **errp) +static void usb_xhci_realize(DeviceState *dev, Error **errp) { - int i, ret; - Error *err = NULL; + int i; XHCIState *xhci = XHCI(dev); - dev->config[PCI_CLASS_PROG] = 0x30; /* xHCI */ - dev->config[PCI_INTERRUPT_PIN] = 0x01; /* interrupt pin 1 */ - dev->config[PCI_CACHE_LINE_SIZE] = 0x10; - dev->config[0x60] = 0x30; /* release number */ - - if (strcmp(object_get_typename(OBJECT(dev)), TYPE_NEC_XHCI) == 0) { - xhci->nec_quirks = true; - } if (xhci->numintrs > MAXINTRS) { xhci->numintrs = MAXINTRS; } @@ -3416,35 +3352,18 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp) xhci->max_pstreams_mask = 0; } - if (xhci->msi != ON_OFF_AUTO_OFF) { - ret = msi_init(dev, 0x70, xhci->numintrs, true, false, &err); - /* Any error other than -ENOTSUP(board's MSI support is broken) - * is a programming error */ - assert(!ret || ret == -ENOTSUP); - if (ret && xhci->msi == ON_OFF_AUTO_ON) { - /* Can't satisfy user's explicit msi=on request, fail */ - error_append_hint(&err, "You have to use msi=auto (default) or " - "msi=off with this machine type.\n"); - error_propagate(errp, err); - return; - } - assert(!err || xhci->msi == ON_OFF_AUTO_AUTO); - /* With msi=auto, we fall back to MSI off silently */ - error_free(err); - } - usb_xhci_init(xhci); xhci->mfwrap_timer = timer_new_ns(QEMU_CLOCK_VIRTUAL, xhci_mfwrap_timer, xhci); - memory_region_init(&xhci->mem, OBJECT(xhci), "xhci", LEN_REGS); - memory_region_init_io(&xhci->mem_cap, OBJECT(xhci), &xhci_cap_ops, xhci, + memory_region_init(&xhci->mem, OBJECT(dev), "xhci", LEN_REGS); + memory_region_init_io(&xhci->mem_cap, OBJECT(dev), &xhci_cap_ops, xhci, "capabilities", LEN_CAP); - memory_region_init_io(&xhci->mem_oper, OBJECT(xhci), &xhci_oper_ops, xhci, + memory_region_init_io(&xhci->mem_oper, OBJECT(dev), &xhci_oper_ops, xhci, "operational", 0x400); - memory_region_init_io(&xhci->mem_runtime, OBJECT(xhci), &xhci_runtime_ops, xhci, - "runtime", LEN_RUNTIME); - memory_region_init_io(&xhci->mem_doorbell, OBJECT(xhci), &xhci_doorbell_ops, xhci, - "doorbell", LEN_DOORBELL); + memory_region_init_io(&xhci->mem_runtime, OBJECT(dev), &xhci_runtime_ops, + xhci, "runtime", LEN_RUNTIME); + memory_region_init_io(&xhci->mem_doorbell, OBJECT(dev), &xhci_doorbell_ops, + xhci, "doorbell", LEN_DOORBELL); memory_region_add_subregion(&xhci->mem, 0, &xhci->mem_cap); memory_region_add_subregion(&xhci->mem, OFF_OPER, &xhci->mem_oper); @@ -3455,31 +3374,13 @@ static void usb_xhci_realize(struct PCIDevice *dev, Error **errp) XHCIPort *port = &xhci->ports[i]; uint32_t offset = OFF_OPER + 0x400 + 0x10 * i; port->xhci = xhci; - memory_region_init_io(&port->mem, OBJECT(xhci), &xhci_port_ops, port, + memory_region_init_io(&port->mem, OBJECT(dev), &xhci_port_ops, port, port->name, 0x10); memory_region_add_subregion(&xhci->mem, offset, &port->mem); } - - pci_register_bar(dev, 0, - PCI_BASE_ADDRESS_SPACE_MEMORY|PCI_BASE_ADDRESS_MEM_TYPE_64, - &xhci->mem); - - if (pci_bus_is_express(pci_get_bus(dev)) || - xhci_get_flag(xhci, XHCI_FLAG_FORCE_PCIE_ENDCAP)) { - ret = pcie_endpoint_cap_init(dev, 0xa0); - assert(ret > 0); - } - - if (xhci->msix != ON_OFF_AUTO_OFF) { - /* TODO check for errors, and should fail when msix=on */ - msix_init(dev, xhci->numintrs, - &xhci->mem, 0, OFF_MSIX_TABLE, - &xhci->mem, 0, OFF_MSIX_PBA, - 0x90, NULL); - } } -static void usb_xhci_exit(PCIDevice *dev) +static void usb_xhci_unrealize(DeviceState *dev) { int i; XHCIState *xhci = XHCI(dev); @@ -3506,25 +3407,18 @@ static void usb_xhci_exit(PCIDevice *dev) memory_region_del_subregion(&xhci->mem, &port->mem); } - /* destroy msix memory region */ - if (dev->msix_table && dev->msix_pba - && dev->msix_entry_used) { - msix_uninit(dev, &xhci->mem, &xhci->mem); - } - usb_bus_release(&xhci->bus); } static int usb_xhci_post_load(void *opaque, int version_id) { XHCIState *xhci = opaque; - PCIDevice *pci_dev = PCI_DEVICE(xhci); XHCISlot *slot; XHCIEPContext *epctx; dma_addr_t dcbaap, pctx; uint32_t slot_ctx[4]; uint32_t ep_ctx[5]; - int slotid, epid, state, intr; + int slotid, epid, state; dcbaap = xhci_addr64(xhci->dcbaap_low, xhci->dcbaap_high); @@ -3534,7 +3428,7 @@ static int usb_xhci_post_load(void *opaque, int version_id) continue; } slot->ctx = - xhci_mask64(ldq_le_pci_dma(pci_dev, dcbaap + 8 * slotid)); + xhci_mask64(ldq_le_dma(xhci->as, dcbaap + 8 * slotid)); xhci_dma_read_u32s(xhci, slot->ctx, slot_ctx, sizeof(slot_ctx)); slot->uport = xhci_lookup_uport(xhci, slot_ctx); if (!slot->uport) { @@ -3562,15 +3456,6 @@ static int usb_xhci_post_load(void *opaque, int version_id) } } } - - for (intr = 0; intr < xhci->numintrs; intr++) { - if (xhci->intr[intr].msix_used) { - msix_vector_use(pci_dev, intr); - } else { - msix_vector_unuse(pci_dev, intr); - } - } - return 0; } @@ -3655,14 +3540,11 @@ static const VMStateDescription vmstate_xhci_intr = { } }; -static const VMStateDescription vmstate_xhci = { - .name = "xhci", +const VMStateDescription vmstate_xhci = { + .name = "xhci-core", .version_id = 1, .post_load = usb_xhci_post_load, .fields = (VMStateField[]) { - VMSTATE_PCI_DEVICE(parent_obj, XHCIState), - VMSTATE_MSIX(parent_obj, XHCIState), - VMSTATE_STRUCT_VARRAY_UINT32(ports, XHCIState, numports, 1, vmstate_xhci_port, XHCIPort), VMSTATE_STRUCT_VARRAY_UINT32(slots, XHCIState, numslots, 1, @@ -3694,75 +3576,32 @@ static Property xhci_properties[] = { XHCI_FLAG_ENABLE_STREAMS, true), DEFINE_PROP_UINT32("p2", XHCIState, numports_2, 4), DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), + DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE, + DeviceState *), DEFINE_PROP_END_OF_LIST(), }; -static void xhci_instance_init(Object *obj) -{ - /* QEMU_PCI_CAP_EXPRESS initialization does not depend on QEMU command - * line, therefore, no need to wait to realize like other devices */ - PCI_DEVICE(obj)->cap_present |= QEMU_PCI_CAP_EXPRESS; -} - static void xhci_class_init(ObjectClass *klass, void *data) { - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); - dc->vmsd = &vmstate_xhci; - device_class_set_props(dc, xhci_properties); + dc->realize = usb_xhci_realize; + dc->unrealize = usb_xhci_unrealize; dc->reset = xhci_reset; - set_bit(DEVICE_CATEGORY_USB, dc->categories); - k->realize = usb_xhci_realize; - k->exit = usb_xhci_exit; - k->class_id = PCI_CLASS_SERIAL_USB; + device_class_set_props(dc, xhci_properties); + dc->user_creatable = false; } static const TypeInfo xhci_info = { .name = TYPE_XHCI, - .parent = TYPE_PCI_DEVICE, + .parent = TYPE_DEVICE, .instance_size = sizeof(XHCIState), .class_init = xhci_class_init, - .instance_init = xhci_instance_init, - .abstract = true, - .interfaces = (InterfaceInfo[]) { - { INTERFACE_PCIE_DEVICE }, - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { } - }, -}; - -static void qemu_xhci_class_init(ObjectClass *klass, void *data) -{ - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->vendor_id = PCI_VENDOR_ID_REDHAT; - k->device_id = PCI_DEVICE_ID_REDHAT_XHCI; - k->revision = 0x01; -} - -static void qemu_xhci_instance_init(Object *obj) -{ - XHCIState *xhci = XHCI(obj); - - xhci->msi = ON_OFF_AUTO_OFF; - xhci->msix = ON_OFF_AUTO_AUTO; - xhci->numintrs = MAXINTRS; - xhci->numslots = MAXSLOTS; - xhci_set_flag(xhci, XHCI_FLAG_SS_FIRST); -} - -static const TypeInfo qemu_xhci_info = { - .name = TYPE_QEMU_XHCI, - .parent = TYPE_XHCI, - .class_init = qemu_xhci_class_init, - .instance_init = qemu_xhci_instance_init, }; static void xhci_register_types(void) { type_register_static(&xhci_info); - type_register_static(&qemu_xhci_info); } type_init(xhci_register_types) diff --git a/hw/usb/hcd-xhci.h b/hw/usb/hcd-xhci.h index c3dfc14405..f859a17e73 100644 --- a/hw/usb/hcd-xhci.h +++ b/hw/usb/hcd-xhci.h @@ -23,6 +23,9 @@ #define HW_USB_HCD_XHCI_H #include "qom/object.h" +#include "hw/usb.h" +#include "sysemu/dma.h" + #define TYPE_XHCI "base-xhci" #define TYPE_NEC_XHCI "nec-usb-xhci" #define TYPE_QEMU_XHCI "qemu-xhci" @@ -181,13 +184,13 @@ typedef struct XHCIInterrupter { } XHCIInterrupter; -struct XHCIState { - /*< private >*/ - PCIDevice parent_obj; - /*< public >*/ +typedef struct XHCIState { + DeviceState parent; USBBus bus; MemoryRegion mem; + MemoryRegion *dma_mr; + AddressSpace *as; MemoryRegion mem_cap; MemoryRegion mem_oper; MemoryRegion mem_runtime; @@ -200,8 +203,9 @@ struct XHCIState { uint32_t numslots; uint32_t flags; uint32_t max_pstreams_mask; - OnOffAuto msi; - OnOffAuto msix; + void (*intr_update)(XHCIState *s, int n, bool enable); + void (*intr_raise)(XHCIState *s, int n, bool level); + DeviceState *hostOpaque; /* Operational Registers */ uint32_t usbcmd; @@ -226,6 +230,9 @@ struct XHCIState { XHCIRing cmd_ring; bool nec_quirks; -}; +} XHCIState; +extern const VMStateDescription vmstate_xhci; +bool xhci_get_flag(XHCIState *xhci, enum xhci_flags bit); +void xhci_set_flag(XHCIState *xhci, enum xhci_flags bit); #endif diff --git a/hw/usb/meson.build b/hw/usb/meson.build index b7c7ff23bf..934e4fa675 100644 --- a/hw/usb/meson.build +++ b/hw/usb/meson.build @@ -21,6 +21,8 @@ softmmu_ss.add(when: 'CONFIG_USB_EHCI', if_true: files('hcd-ehci.c')) softmmu_ss.add(when: 'CONFIG_USB_EHCI_PCI', if_true: files('hcd-ehci-pci.c')) softmmu_ss.add(when: 'CONFIG_USB_EHCI_SYSBUS', if_true: files('hcd-ehci.c', 'hcd-ehci-sysbus.c')) softmmu_ss.add(when: 'CONFIG_USB_XHCI', if_true: files('hcd-xhci.c')) +softmmu_ss.add(when: 'CONFIG_USB_XHCI_PCI', if_true: files('hcd-xhci-pci.c')) +softmmu_ss.add(when: 'CONFIG_USB_XHCI_SYSBUS', if_true: files('hcd-xhci-sysbus.c')) softmmu_ss.add(when: 'CONFIG_USB_XHCI_NEC', if_true: files('hcd-xhci-nec.c')) softmmu_ss.add(when: 'CONFIG_USB_MUSB', if_true: files('hcd-musb.c')) softmmu_ss.add(when: 'CONFIG_USB_DWC2', if_true: files('hcd-dwc2.c')) diff --git a/hw/virtio/trace-events b/hw/virtio/trace-events index 845200bf10..cf1e59de30 100644 --- a/hw/virtio/trace-events +++ b/hw/virtio/trace-events @@ -22,6 +22,37 @@ vhost_user_postcopy_waker(const char *rb, uint64_t rb_offset) "%s + 0x%"PRIx64 vhost_user_postcopy_waker_found(uint64_t client_addr) "0x%"PRIx64 vhost_user_postcopy_waker_nomatch(const char *rb, uint64_t rb_offset) "%s + 0x%"PRIx64 +# vhost-vdpa.c +vhost_vdpa_dma_map(void *vdpa, int fd, uint32_t msg_type, uint64_t iova, uint64_t size, uint64_t uaddr, uint8_t perm, uint8_t type) "vdpa:%p fd: %d msg_type: %"PRIu32" iova: 0x%"PRIx64" size: 0x%"PRIx64" uaddr: 0x%"PRIx64" perm: 0x%"PRIx8" type: %"PRIu8 +vhost_vdpa_dma_unmap(void *vdpa, int fd, uint32_t msg_type, uint64_t iova, uint64_t size, uint8_t type) "vdpa:%p fd: %d msg_type: %"PRIu32" iova: 0x%"PRIx64" size: 0x%"PRIx64" type: %"PRIu8 +vhost_vdpa_listener_region_add(void *vdpa, uint64_t iova, uint64_t llend, void *vaddr, bool readonly) "vdpa: %p iova 0x%"PRIx64" llend 0x%"PRIx64" vaddr: %p read-only: %d" +vhost_vdpa_listener_region_del(void *vdpa, uint64_t iova, uint64_t llend) "vdpa: %p iova 0x%"PRIx64" llend 0x%"PRIx64 +vhost_vdpa_add_status(void *dev, uint8_t status) "dev: %p status: 0x%"PRIx8 +vhost_vdpa_init(void *dev, void *vdpa) "dev: %p vdpa: %p" +vhost_vdpa_cleanup(void *dev, void *vdpa) "dev: %p vdpa: %p" +vhost_vdpa_memslots_limit(void *dev, int ret) "dev: %p = 0x%x" +vhost_vdpa_set_mem_table(void *dev, uint32_t nregions, uint32_t padding) "dev: %p nregions: %"PRIu32" padding: 0x%"PRIx32 +vhost_vdpa_dump_regions(void *dev, int i, uint64_t guest_phys_addr, uint64_t memory_size, uint64_t userspace_addr, uint64_t flags_padding) "dev: %p %d: guest_phys_addr: 0x%"PRIx64" memory_size: 0x%"PRIx64" userspace_addr: 0x%"PRIx64" flags_padding: 0x%"PRIx64 +vhost_vdpa_set_features(void *dev, uint64_t features) "dev: %p features: 0x%"PRIx64 +vhost_vdpa_get_device_id(void *dev, uint32_t device_id) "dev: %p device_id %"PRIu32 +vhost_vdpa_reset_device(void *dev, uint8_t status) "dev: %p status: 0x%"PRIx8 +vhost_vdpa_get_vq_index(void *dev, int idx, int vq_idx) "dev: %p idx: %d vq idx: %d" +vhost_vdpa_set_vring_ready(void *dev) "dev: %p" +vhost_vdpa_dump_config(void *dev, const char *line) "dev: %p %s" +vhost_vdpa_set_config(void *dev, uint32_t offset, uint32_t size, uint32_t flags) "dev: %p offset: %"PRIu32" size: %"PRIu32" flags: 0x%"PRIx32 +vhost_vdpa_get_config(void *dev, void *config, uint32_t config_len) "dev: %p config: %p config_len: %"PRIu32 +vhost_vdpa_dev_start(void *dev, bool started) "dev: %p started: %d" +vhost_vdpa_set_log_base(void *dev, uint64_t base, unsigned long long size, int refcnt, int fd, void *log) "dev: %p base: 0x%"PRIx64" size: %llu refcnt: %d fd: %d log: %p" +vhost_vdpa_set_vring_addr(void *dev, unsigned int index, unsigned int flags, uint64_t desc_user_addr, uint64_t used_user_addr, uint64_t avail_user_addr, uint64_t log_guest_addr) "dev: %p index: %u flags: 0x%x desc_user_addr: 0x%"PRIx64" used_user_addr: 0x%"PRIx64" avail_user_addr: 0x%"PRIx64" log_guest_addr: 0x%"PRIx64 +vhost_vdpa_set_vring_num(void *dev, unsigned int index, unsigned int num) "dev: %p index: %u num: %u" +vhost_vdpa_set_vring_base(void *dev, unsigned int index, unsigned int num) "dev: %p index: %u num: %u" +vhost_vdpa_get_vring_base(void *dev, unsigned int index, unsigned int num) "dev: %p index: %u num: %u" +vhost_vdpa_set_vring_kick(void *dev, unsigned int index, int fd) "dev: %p index: %u fd: %d" +vhost_vdpa_set_vring_call(void *dev, unsigned int index, int fd) "dev: %p index: %u fd: %d" +vhost_vdpa_get_features(void *dev, uint64_t features) "dev: %p features: 0x%"PRIx64 +vhost_vdpa_set_owner(void *dev) "dev: %p" +vhost_vdpa_vq_get_addr(void *dev, void *vq, uint64_t desc_user_addr, uint64_t avail_user_addr, uint64_t used_user_addr) "dev: %p vq: %p desc_user_addr: 0x%"PRIx64" avail_user_addr: 0x%"PRIx64" used_user_addr: 0x%"PRIx64 + # virtio.c virtqueue_alloc_element(void *elem, size_t sz, unsigned in_num, unsigned out_num) "elem %p size %zd in_num %u out_num %u" virtqueue_fill(void *vq, const void *elem, unsigned int len, unsigned int idx) "vq %p elem %p len %u idx %u" diff --git a/hw/virtio/vhost-backend.c b/hw/virtio/vhost-backend.c index 782b1d67d9..88c8ecc9e0 100644 --- a/hw/virtio/vhost-backend.c +++ b/hw/virtio/vhost-backend.c @@ -156,6 +156,28 @@ static int vhost_kernel_set_features(struct vhost_dev *dev, return vhost_kernel_call(dev, VHOST_SET_FEATURES, &features); } +static int vhost_kernel_set_backend_cap(struct vhost_dev *dev) +{ + uint64_t features; + uint64_t f = 0x1ULL << VHOST_BACKEND_F_IOTLB_MSG_V2; + int r; + + if (vhost_kernel_call(dev, VHOST_GET_BACKEND_FEATURES, &features)) { + return 0; + } + + features &= f; + r = vhost_kernel_call(dev, VHOST_SET_BACKEND_FEATURES, + &features); + if (r) { + return 0; + } + + dev->backend_cap = features; + + return 0; +} + static int vhost_kernel_get_features(struct vhost_dev *dev, uint64_t *features) { @@ -195,34 +217,65 @@ static int vhost_kernel_vsock_set_running(struct vhost_dev *dev, int start) static void vhost_kernel_iotlb_read(void *opaque) { struct vhost_dev *dev = opaque; - struct vhost_msg msg; ssize_t len; - while ((len = read((uintptr_t)dev->opaque, &msg, sizeof msg)) > 0) { - if (len < sizeof msg) { - error_report("Wrong vhost message len: %d", (int)len); - break; + if (dev->backend_cap & + (0x1ULL << VHOST_BACKEND_F_IOTLB_MSG_V2)) { + struct vhost_msg_v2 msg; + + while ((len = read((uintptr_t)dev->opaque, &msg, sizeof msg)) > 0) { + if (len < sizeof msg) { + error_report("Wrong vhost message len: %d", (int)len); + break; + } + if (msg.type != VHOST_IOTLB_MSG_V2) { + error_report("Unknown vhost iotlb message type"); + break; + } + + vhost_backend_handle_iotlb_msg(dev, &msg.iotlb); } - if (msg.type != VHOST_IOTLB_MSG) { - error_report("Unknown vhost iotlb message type"); - break; + } else { + struct vhost_msg msg; + + while ((len = read((uintptr_t)dev->opaque, &msg, sizeof msg)) > 0) { + if (len < sizeof msg) { + error_report("Wrong vhost message len: %d", (int)len); + break; + } + if (msg.type != VHOST_IOTLB_MSG) { + error_report("Unknown vhost iotlb message type"); + break; + } + + vhost_backend_handle_iotlb_msg(dev, &msg.iotlb); } - - vhost_backend_handle_iotlb_msg(dev, &msg.iotlb); } } static int vhost_kernel_send_device_iotlb_msg(struct vhost_dev *dev, struct vhost_iotlb_msg *imsg) { - struct vhost_msg msg; + if (dev->backend_cap & (1ULL << VHOST_BACKEND_F_IOTLB_MSG_V2)) { + struct vhost_msg_v2 msg; - msg.type = VHOST_IOTLB_MSG; - msg.iotlb = *imsg; + msg.type = VHOST_IOTLB_MSG_V2; + msg.iotlb = *imsg; - if (write((uintptr_t)dev->opaque, &msg, sizeof msg) != sizeof msg) { - error_report("Fail to update device iotlb"); - return -EFAULT; + if (write((uintptr_t)dev->opaque, &msg, sizeof msg) != sizeof msg) { + error_report("Fail to update device iotlb"); + return -EFAULT; + } + } else { + struct vhost_msg msg; + + msg.type = VHOST_IOTLB_MSG; + msg.iotlb = *imsg; + + if (write((uintptr_t)dev->opaque, &msg, sizeof msg) != sizeof msg) { + error_report("Fail to update device iotlb"); + return -EFAULT; + } } return 0; @@ -260,6 +313,7 @@ static const VhostOps kernel_ops = { vhost_kernel_set_vring_busyloop_timeout, .vhost_set_features = vhost_kernel_set_features, .vhost_get_features = vhost_kernel_get_features, + .vhost_set_backend_cap = vhost_kernel_set_backend_cap, .vhost_set_owner = vhost_kernel_set_owner, .vhost_reset_device = vhost_kernel_reset_device, .vhost_get_vq_index = vhost_kernel_get_vq_index, diff --git a/hw/virtio/vhost-user-vsock-pci.c b/hw/virtio/vhost-user-vsock-pci.c index 763f89984e..72a96199cd 100644 --- a/hw/virtio/vhost-user-vsock-pci.c +++ b/hw/virtio/vhost-user-vsock-pci.c @@ -41,6 +41,9 @@ static void vhost_user_vsock_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) VHostUserVSockPCI *dev = VHOST_USER_VSOCK_PCI(vpci_dev); DeviceState *vdev = DEVICE(&dev->vdev); + /* unlike vhost-vsock, we do not need to care about pre-5.1 compat */ + virtio_pci_force_virtio_1(vpci_dev); + qdev_realize(vdev, BUS(&vpci_dev->bus), errp); } @@ -69,7 +72,6 @@ static void vhost_user_vsock_pci_instance_init(Object *obj) static const VirtioPCIDeviceTypeInfo vhost_user_vsock_pci_info = { .base_name = TYPE_VHOST_USER_VSOCK_PCI, .generic_name = "vhost-user-vsock-pci", - .transitional_name = "vhost-user-vsock-pci-transitional", .non_transitional_name = "vhost-user-vsock-pci-non-transitional", .instance_size = sizeof(VHostUserVSockPCI), .instance_init = vhost_user_vsock_pci_instance_init, diff --git a/hw/virtio/vhost-vdpa.c b/hw/virtio/vhost-vdpa.c index aedc52c4d7..4f1039910a 100644 --- a/hw/virtio/vhost-vdpa.c +++ b/hw/virtio/vhost-vdpa.c @@ -20,6 +20,8 @@ #include "hw/virtio/vhost-vdpa.h" #include "qemu/main-loop.h" #include "cpu.h" +#include "trace.h" +#include "qemu-common.h" static bool vhost_vdpa_listener_skipped_section(MemoryRegionSection *section) { @@ -48,6 +50,9 @@ static int vhost_vdpa_dma_map(struct vhost_vdpa *v, hwaddr iova, hwaddr size, msg.iotlb.perm = readonly ? VHOST_ACCESS_RO : VHOST_ACCESS_RW; msg.iotlb.type = VHOST_IOTLB_UPDATE; + trace_vhost_vdpa_dma_map(v, fd, msg.type, msg.iotlb.iova, msg.iotlb.size, + msg.iotlb.uaddr, msg.iotlb.perm, msg.iotlb.type); + if (write(fd, &msg, sizeof(msg)) != sizeof(msg)) { error_report("failed to write, fd=%d, errno=%d (%s)", fd, errno, strerror(errno)); @@ -69,6 +74,9 @@ static int vhost_vdpa_dma_unmap(struct vhost_vdpa *v, hwaddr iova, msg.iotlb.size = size; msg.iotlb.type = VHOST_IOTLB_INVALIDATE; + trace_vhost_vdpa_dma_unmap(v, fd, msg.type, msg.iotlb.iova, + msg.iotlb.size, msg.iotlb.type); + if (write(fd, &msg, sizeof(msg)) != sizeof(msg)) { error_report("failed to write, fd=%d, errno=%d (%s)", fd, errno, strerror(errno)); @@ -78,6 +86,46 @@ static int vhost_vdpa_dma_unmap(struct vhost_vdpa *v, hwaddr iova, return ret; } +static void vhost_vdpa_listener_begin(MemoryListener *listener) +{ + struct vhost_vdpa *v = container_of(listener, struct vhost_vdpa, listener); + struct vhost_dev *dev = v->dev; + struct vhost_msg_v2 msg; + int fd = v->device_fd; + + if (!(dev->backend_cap & (0x1ULL << VHOST_BACKEND_F_IOTLB_BATCH))) { + return; + } + + msg.type = v->msg_type; + msg.iotlb.type = VHOST_IOTLB_BATCH_BEGIN; + + if (write(fd, &msg, sizeof(msg)) != sizeof(msg)) { + error_report("failed to write, fd=%d, errno=%d (%s)", + fd, errno, strerror(errno)); + } +} + +static void vhost_vdpa_listener_commit(MemoryListener *listener) +{ + struct vhost_vdpa *v = container_of(listener, struct vhost_vdpa, listener); + struct vhost_dev *dev = v->dev; + struct vhost_msg_v2 msg; + int fd = v->device_fd; + + if (!(dev->backend_cap & (0x1ULL << VHOST_BACKEND_F_IOTLB_BATCH))) { + return; + } + + msg.type = v->msg_type; + msg.iotlb.type = VHOST_IOTLB_BATCH_END; + + if (write(fd, &msg, sizeof(msg)) != sizeof(msg)) { + error_report("failed to write, fd=%d, errno=%d (%s)", + fd, errno, strerror(errno)); + } +} + static void vhost_vdpa_listener_region_add(MemoryListener *listener, MemoryRegionSection *section) { @@ -114,6 +162,9 @@ static void vhost_vdpa_listener_region_add(MemoryListener *listener, section->offset_within_region + (iova - section->offset_within_address_space); + trace_vhost_vdpa_listener_region_add(v, iova, int128_get64(llend), + vaddr, section->readonly); + llsize = int128_sub(llend, int128_make64(iova)); ret = vhost_vdpa_dma_map(v, iova, int128_get64(llsize), @@ -169,6 +220,8 @@ static void vhost_vdpa_listener_region_del(MemoryListener *listener, llend = int128_add(llend, section->size); llend = int128_and(llend, int128_exts64(TARGET_PAGE_MASK)); + trace_vhost_vdpa_listener_region_del(v, iova, int128_get64(llend)); + if (int128_ge(int128_make64(iova), llend)) { return; } @@ -188,6 +241,8 @@ static void vhost_vdpa_listener_region_del(MemoryListener *listener, * depends on the addnop(). */ static const MemoryListener vhost_vdpa_memory_listener = { + .begin = vhost_vdpa_listener_begin, + .commit = vhost_vdpa_listener_commit, .region_add = vhost_vdpa_listener_region_add, .region_del = vhost_vdpa_listener_region_del, }; @@ -207,6 +262,7 @@ static void vhost_vdpa_add_status(struct vhost_dev *dev, uint8_t status) { uint8_t s; + trace_vhost_vdpa_add_status(dev, status); if (vhost_vdpa_call(dev, VHOST_VDPA_GET_STATUS, &s)) { return; } @@ -221,8 +277,10 @@ static int vhost_vdpa_init(struct vhost_dev *dev, void *opaque) struct vhost_vdpa *v; uint64_t features; assert(dev->vhost_ops->backend_type == VHOST_BACKEND_TYPE_VDPA); + trace_vhost_vdpa_init(dev, opaque); v = opaque; + v->dev = dev; dev->opaque = opaque ; vhost_vdpa_call(dev, VHOST_GET_FEATURES, &features); dev->backend_features = features; @@ -240,6 +298,7 @@ static int vhost_vdpa_cleanup(struct vhost_dev *dev) struct vhost_vdpa *v; assert(dev->vhost_ops->backend_type == VHOST_BACKEND_TYPE_VDPA); v = dev->opaque; + trace_vhost_vdpa_cleanup(dev, v); memory_listener_unregister(&v->listener); dev->opaque = NULL; @@ -248,13 +307,25 @@ static int vhost_vdpa_cleanup(struct vhost_dev *dev) static int vhost_vdpa_memslots_limit(struct vhost_dev *dev) { + trace_vhost_vdpa_memslots_limit(dev, INT_MAX); return INT_MAX; } static int vhost_vdpa_set_mem_table(struct vhost_dev *dev, struct vhost_memory *mem) { - + trace_vhost_vdpa_set_mem_table(dev, mem->nregions, mem->padding); + if (trace_event_get_state_backends(TRACE_VHOST_VDPA_SET_MEM_TABLE) && + trace_event_get_state_backends(TRACE_VHOST_VDPA_DUMP_REGIONS)) { + int i; + for (i = 0; i < mem->nregions; i++) { + trace_vhost_vdpa_dump_regions(dev, i, + mem->regions[i].guest_phys_addr, + mem->regions[i].memory_size, + mem->regions[i].userspace_addr, + mem->regions[i].flags_padding); + } + } if (mem->padding) { return -1; } @@ -266,6 +337,7 @@ static int vhost_vdpa_set_features(struct vhost_dev *dev, uint64_t features) { int ret; + trace_vhost_vdpa_set_features(dev, features); ret = vhost_vdpa_call(dev, VHOST_SET_FEATURES, &features); uint8_t status = 0; if (ret) { @@ -277,29 +349,59 @@ static int vhost_vdpa_set_features(struct vhost_dev *dev, return !(status & VIRTIO_CONFIG_S_FEATURES_OK); } +static int vhost_vdpa_set_backend_cap(struct vhost_dev *dev) +{ + uint64_t features; + uint64_t f = 0x1ULL << VHOST_BACKEND_F_IOTLB_MSG_V2 | + 0x1ULL << VHOST_BACKEND_F_IOTLB_BATCH; + int r; + + if (vhost_vdpa_call(dev, VHOST_GET_BACKEND_FEATURES, &features)) { + return 0; + } + + features &= f; + r = vhost_vdpa_call(dev, VHOST_SET_BACKEND_FEATURES, &features); + if (r) { + return 0; + } + + dev->backend_cap = features; + + return 0; +} + int vhost_vdpa_get_device_id(struct vhost_dev *dev, uint32_t *device_id) { - return vhost_vdpa_call(dev, VHOST_VDPA_GET_DEVICE_ID, device_id); + int ret; + ret = vhost_vdpa_call(dev, VHOST_VDPA_GET_DEVICE_ID, device_id); + trace_vhost_vdpa_get_device_id(dev, *device_id); + return ret; } static int vhost_vdpa_reset_device(struct vhost_dev *dev) { + int ret; uint8_t status = 0; - return vhost_vdpa_call(dev, VHOST_VDPA_SET_STATUS, &status); + ret = vhost_vdpa_call(dev, VHOST_VDPA_SET_STATUS, &status); + trace_vhost_vdpa_reset_device(dev, status); + return ret; } static int vhost_vdpa_get_vq_index(struct vhost_dev *dev, int idx) { assert(idx >= dev->vq_index && idx < dev->vq_index + dev->nvqs); + trace_vhost_vdpa_get_vq_index(dev, idx, idx - dev->vq_index); return idx - dev->vq_index; } static int vhost_vdpa_set_vring_ready(struct vhost_dev *dev) { int i; + trace_vhost_vdpa_set_vring_ready(dev); for (i = 0; i < dev->nvqs; ++i) { struct vhost_vring_state state = { .index = dev->vq_index + i, @@ -310,6 +412,19 @@ static int vhost_vdpa_set_vring_ready(struct vhost_dev *dev) return 0; } +static void vhost_vdpa_dump_config(struct vhost_dev *dev, const uint8_t *config, + uint32_t config_len) +{ + int b, len; + char line[QEMU_HEXDUMP_LINE_LEN]; + + for (b = 0; b < config_len; b += 16) { + len = config_len - b; + qemu_hexdump_line(line, b, config, len, false); + trace_vhost_vdpa_dump_config(dev, line); + } +} + static int vhost_vdpa_set_config(struct vhost_dev *dev, const uint8_t *data, uint32_t offset, uint32_t size, uint32_t flags) @@ -318,10 +433,15 @@ static int vhost_vdpa_set_config(struct vhost_dev *dev, const uint8_t *data, int ret; unsigned long config_size = offsetof(struct vhost_vdpa_config, buf); + trace_vhost_vdpa_set_config(dev, offset, size, flags); config = g_malloc(size + config_size); config->off = offset; config->len = size; memcpy(config->buf, data, size); + if (trace_event_get_state_backends(TRACE_VHOST_VDPA_SET_CONFIG) && + trace_event_get_state_backends(TRACE_VHOST_VDPA_DUMP_CONFIG)) { + vhost_vdpa_dump_config(dev, data, size); + } ret = vhost_vdpa_call(dev, VHOST_VDPA_SET_CONFIG, config); g_free(config); return ret; @@ -334,18 +454,24 @@ static int vhost_vdpa_get_config(struct vhost_dev *dev, uint8_t *config, unsigned long config_size = offsetof(struct vhost_vdpa_config, buf); int ret; + trace_vhost_vdpa_get_config(dev, config, config_len); v_config = g_malloc(config_len + config_size); v_config->len = config_len; v_config->off = 0; ret = vhost_vdpa_call(dev, VHOST_VDPA_GET_CONFIG, v_config); memcpy(config, v_config->buf, config_len); g_free(v_config); + if (trace_event_get_state_backends(TRACE_VHOST_VDPA_GET_CONFIG) && + trace_event_get_state_backends(TRACE_VHOST_VDPA_DUMP_CONFIG)) { + vhost_vdpa_dump_config(dev, config, config_len); + } return ret; } static int vhost_vdpa_dev_start(struct vhost_dev *dev, bool started) { struct vhost_vdpa *v = dev->opaque; + trace_vhost_vdpa_dev_start(dev, started); if (started) { uint8_t status = 0; memory_listener_register(&v->listener, &address_space_memory); @@ -367,53 +493,72 @@ static int vhost_vdpa_dev_start(struct vhost_dev *dev, bool started) static int vhost_vdpa_set_log_base(struct vhost_dev *dev, uint64_t base, struct vhost_log *log) { + trace_vhost_vdpa_set_log_base(dev, base, log->size, log->refcnt, log->fd, + log->log); return vhost_vdpa_call(dev, VHOST_SET_LOG_BASE, &base); } static int vhost_vdpa_set_vring_addr(struct vhost_dev *dev, struct vhost_vring_addr *addr) { + trace_vhost_vdpa_set_vring_addr(dev, addr->index, addr->flags, + addr->desc_user_addr, addr->used_user_addr, + addr->avail_user_addr, + addr->log_guest_addr); return vhost_vdpa_call(dev, VHOST_SET_VRING_ADDR, addr); } static int vhost_vdpa_set_vring_num(struct vhost_dev *dev, struct vhost_vring_state *ring) { + trace_vhost_vdpa_set_vring_num(dev, ring->index, ring->num); return vhost_vdpa_call(dev, VHOST_SET_VRING_NUM, ring); } static int vhost_vdpa_set_vring_base(struct vhost_dev *dev, struct vhost_vring_state *ring) { + trace_vhost_vdpa_set_vring_base(dev, ring->index, ring->num); return vhost_vdpa_call(dev, VHOST_SET_VRING_BASE, ring); } static int vhost_vdpa_get_vring_base(struct vhost_dev *dev, struct vhost_vring_state *ring) { - return vhost_vdpa_call(dev, VHOST_GET_VRING_BASE, ring); + int ret; + + ret = vhost_vdpa_call(dev, VHOST_GET_VRING_BASE, ring); + trace_vhost_vdpa_get_vring_base(dev, ring->index, ring->num); + return ret; } static int vhost_vdpa_set_vring_kick(struct vhost_dev *dev, struct vhost_vring_file *file) { + trace_vhost_vdpa_set_vring_kick(dev, file->index, file->fd); return vhost_vdpa_call(dev, VHOST_SET_VRING_KICK, file); } static int vhost_vdpa_set_vring_call(struct vhost_dev *dev, struct vhost_vring_file *file) { + trace_vhost_vdpa_set_vring_call(dev, file->index, file->fd); return vhost_vdpa_call(dev, VHOST_SET_VRING_CALL, file); } static int vhost_vdpa_get_features(struct vhost_dev *dev, uint64_t *features) { - return vhost_vdpa_call(dev, VHOST_GET_FEATURES, features); + int ret; + + ret = vhost_vdpa_call(dev, VHOST_GET_FEATURES, features); + trace_vhost_vdpa_get_features(dev, *features); + return ret; } static int vhost_vdpa_set_owner(struct vhost_dev *dev) { + trace_vhost_vdpa_set_owner(dev); return vhost_vdpa_call(dev, VHOST_SET_OWNER, NULL); } @@ -424,6 +569,8 @@ static int vhost_vdpa_vq_get_addr(struct vhost_dev *dev, addr->desc_user_addr = (uint64_t)(unsigned long)vq->desc_phys; addr->avail_user_addr = (uint64_t)(unsigned long)vq->avail_phys; addr->used_user_addr = (uint64_t)(unsigned long)vq->used_phys; + trace_vhost_vdpa_vq_get_addr(dev, vq, addr->desc_user_addr, + addr->avail_user_addr, addr->used_user_addr); return 0; } @@ -444,6 +591,7 @@ const VhostOps vdpa_ops = { .vhost_set_vring_kick = vhost_vdpa_set_vring_kick, .vhost_set_vring_call = vhost_vdpa_set_vring_call, .vhost_get_features = vhost_vdpa_get_features, + .vhost_set_backend_cap = vhost_vdpa_set_backend_cap, .vhost_set_owner = vhost_vdpa_set_owner, .vhost_set_vring_endian = NULL, .vhost_backend_memslots_limit = vhost_vdpa_memslots_limit, diff --git a/hw/virtio/vhost-vsock-pci.c b/hw/virtio/vhost-vsock-pci.c index e56067b427..205da8d1f5 100644 --- a/hw/virtio/vhost-vsock-pci.c +++ b/hw/virtio/vhost-vsock-pci.c @@ -44,6 +44,15 @@ static void vhost_vsock_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VHostVSockPCI *dev = VHOST_VSOCK_PCI(vpci_dev); DeviceState *vdev = DEVICE(&dev->vdev); + VirtIODevice *virtio_dev = VIRTIO_DEVICE(vdev); + + /* + * To avoid migration issues, we force virtio version 1 only when + * legacy check is enabled in the new machine types (>= 5.1). + */ + if (!virtio_legacy_check_disabled(virtio_dev)) { + virtio_pci_force_virtio_1(vpci_dev); + } qdev_realize(vdev, BUS(&vpci_dev->bus), errp); } @@ -73,7 +82,6 @@ static void vhost_vsock_pci_instance_init(Object *obj) static const VirtioPCIDeviceTypeInfo vhost_vsock_pci_info = { .base_name = TYPE_VHOST_VSOCK_PCI, .generic_name = "vhost-vsock-pci", - .transitional_name = "vhost-vsock-pci-transitional", .non_transitional_name = "vhost-vsock-pci-non-transitional", .instance_size = sizeof(VHostVSockPCI), .instance_init = vhost_vsock_pci_instance_init, diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index 0119516254..68f0a75134 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -818,19 +818,41 @@ static int vhost_dev_set_features(struct vhost_dev *dev, r = dev->vhost_ops->vhost_set_features(dev, features); if (r < 0) { VHOST_OPS_DEBUG("vhost_set_features failed"); + goto out; + } + if (dev->vhost_ops->vhost_set_backend_cap) { + r = dev->vhost_ops->vhost_set_backend_cap(dev); + if (r < 0) { + VHOST_OPS_DEBUG("vhost_set_backend_cap failed"); + goto out; + } } + +out: return r < 0 ? -errno : 0; } static int vhost_dev_set_log(struct vhost_dev *dev, bool enable_log) { int r, i, idx; + hwaddr addr; + r = vhost_dev_set_features(dev, enable_log); if (r < 0) { goto err_features; } for (i = 0; i < dev->nvqs; ++i) { idx = dev->vhost_ops->vhost_get_vq_index(dev, dev->vq_index + i); + addr = virtio_queue_get_desc_addr(dev->vdev, idx); + if (!addr) { + /* + * The queue might not be ready for start. If this + * is the case there is no reason to continue the process. + * The similar logic is used by the vhost_virtqueue_start() + * routine. + */ + continue; + } r = vhost_virtqueue_set_addr(dev, dev->vqs + i, idx, enable_log); if (r < 0) { @@ -861,21 +883,42 @@ static int vhost_migration_log(MemoryListener *listener, bool enable) dev->log_enabled = enable; return 0; } + + r = 0; if (!enable) { r = vhost_dev_set_log(dev, false); if (r < 0) { - return r; + goto check_dev_state; } vhost_log_put(dev, false); } else { vhost_dev_log_resize(dev, vhost_get_log_size(dev)); r = vhost_dev_set_log(dev, true); if (r < 0) { - return r; + goto check_dev_state; } } + +check_dev_state: dev->log_enabled = enable; - return 0; + /* + * vhost-user-* devices could change their state during log + * initialization due to disconnect. So check dev state after + * vhost communication. + */ + if (!dev->started) { + /* + * Since device is in the stopped state, it is okay for + * migration. Return success. + */ + r = 0; + } + if (r) { + /* An error is occured. */ + dev->log_enabled = false; + } + + return r; } static void vhost_log_global_start(MemoryListener *listener) diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c index 76540e57b1..378f63b210 100644 --- a/hw/virtio/virtio-iommu-pci.c +++ b/hw/virtio/virtio-iommu-pci.c @@ -69,6 +69,7 @@ static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) object_property_set_link(OBJECT(dev), "primary-bus", OBJECT(pci_get_bus(&vpci_dev->pci_dev)), &error_abort); + virtio_pci_force_virtio_1(vpci_dev); qdev_realize(vdev, BUS(&vpci_dev->bus), errp); } @@ -98,7 +99,6 @@ static void virtio_iommu_pci_instance_init(Object *obj) static const VirtioPCIDeviceTypeInfo virtio_iommu_pci_info = { .base_name = TYPE_VIRTIO_IOMMU_PCI, .generic_name = "virtio-iommu-pci", - .transitional_name = "virtio-iommu-pci-transitional", .non_transitional_name = "virtio-iommu-pci-non-transitional", .instance_size = sizeof(VirtIOIOMMUPCI), .instance_init = virtio_iommu_pci_instance_init, diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 5d56865e56..21ec63b108 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -801,8 +801,12 @@ static void virtio_iommu_device_unrealize(DeviceState *dev) VirtIOIOMMU *s = VIRTIO_IOMMU(dev); g_hash_table_destroy(s->as_by_busptr); - g_tree_destroy(s->domains); - g_tree_destroy(s->endpoints); + if (s->domains) { + g_tree_destroy(s->domains); + } + if (s->endpoints) { + g_tree_destroy(s->endpoints); + } virtio_delete_queue(s->req_vq); virtio_delete_queue(s->event_vq); diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index 8fbec77ccc..7c8ca9f28b 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -318,6 +318,7 @@ static void virtio_mem_handle_request(VirtIODevice *vdev, VirtQueue *vq) if (iov_to_buf(elem->out_sg, elem->out_num, 0, &req, len) < len) { virtio_error(vdev, "virtio-mem protocol violation: invalid request" " size: %d", len); + virtqueue_detach_element(vq, elem, 0); g_free(elem); return; } @@ -327,6 +328,7 @@ static void virtio_mem_handle_request(VirtIODevice *vdev, VirtQueue *vq) virtio_error(vdev, "virtio-mem protocol violation: not enough space" " for response: %zu", iov_size(elem->in_sg, elem->in_num)); + virtqueue_detach_element(vq, elem, 0); g_free(elem); return; } @@ -348,6 +350,7 @@ static void virtio_mem_handle_request(VirtIODevice *vdev, VirtQueue *vq) default: virtio_error(vdev, "virtio-mem protocol violation: unknown request" " type: %d", type); + virtqueue_detach_element(vq, elem, 0); g_free(elem); return; } diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index 02790e3237..36524a5728 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -1597,8 +1597,18 @@ static void virtio_pci_device_plugged(DeviceState *d, Error **errp) if (legacy) { if (!virtio_legacy_allowed(vdev)) { - error_setg(errp, "device is modern-only, use disable-legacy=on"); - return; + /* + * To avoid migration issues, we allow legacy mode when legacy + * check is disabled in the old machine types (< 5.1). + */ + if (virtio_legacy_check_disabled(vdev)) { + warn_report("device is modern-only, but for backward " + "compatibility legacy is allowed"); + } else { + error_setg(errp, + "device is modern-only, use disable-legacy=on"); + return; + } } if (virtio_host_has_feature(vdev, VIRTIO_F_IOMMU_PLATFORM)) { error_setg(errp, "VIRTIO_F_IOMMU_PLATFORM was supported by" diff --git a/hw/virtio/virtio-pmem-pci.c b/hw/virtio/virtio-pmem-pci.c index 21a457d151..2b2a0b1eae 100644 --- a/hw/virtio/virtio-pmem-pci.c +++ b/hw/virtio/virtio-pmem-pci.c @@ -22,6 +22,7 @@ static void virtio_pmem_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) VirtIOPMEMPCI *pmem_pci = VIRTIO_PMEM_PCI(vpci_dev); DeviceState *vdev = DEVICE(&pmem_pci->vdev); + virtio_pci_force_virtio_1(vpci_dev); qdev_realize(vdev, BUS(&vpci_dev->bus), errp); } diff --git a/hw/virtio/virtio-pmem.c b/hw/virtio/virtio-pmem.c index 1e0c137497..ddb0125901 100644 --- a/hw/virtio/virtio-pmem.c +++ b/hw/virtio/virtio-pmem.c @@ -77,6 +77,7 @@ static void virtio_pmem_flush(VirtIODevice *vdev, VirtQueue *vq) if (req_data->elem.out_num < 1 || req_data->elem.in_num < 1) { virtio_error(vdev, "virtio-pmem request not proper"); + virtqueue_detach_element(vq, (VirtQueueElement *)req_data, 0); g_free(req_data); return; } diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 3a3d012d9f..6f8f865aff 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -2963,17 +2963,16 @@ int virtio_set_features(VirtIODevice *vdev, uint64_t val) return -EINVAL; } ret = virtio_set_features_nocheck(vdev, val); - if (!ret) { - if (virtio_vdev_has_feature(vdev, VIRTIO_RING_F_EVENT_IDX)) { - /* VIRTIO_RING_F_EVENT_IDX changes the size of the caches. */ - int i; - for (i = 0; i < VIRTIO_QUEUE_MAX; i++) { - if (vdev->vq[i].vring.num != 0) { - virtio_init_region_cache(vdev, i); - } + if (virtio_vdev_has_feature(vdev, VIRTIO_RING_F_EVENT_IDX)) { + /* VIRTIO_RING_F_EVENT_IDX changes the size of the caches. */ + int i; + for (i = 0; i < VIRTIO_QUEUE_MAX; i++) { + if (vdev->vq[i].vring.num != 0) { + virtio_init_region_cache(vdev, i); } } - + } + if (!ret) { if (!virtio_device_started(vdev, vdev->status) && !virtio_vdev_has_feature(vdev, VIRTIO_F_VERSION_1)) { vdev->start_on_kick = true; @@ -3304,6 +3303,11 @@ bool virtio_legacy_allowed(VirtIODevice *vdev) } } +bool virtio_legacy_check_disabled(VirtIODevice *vdev) +{ + return vdev->disable_legacy_check; +} + hwaddr virtio_queue_get_desc_addr(VirtIODevice *vdev, int n) { return vdev->vq[n].vring.desc; @@ -3713,6 +3717,8 @@ static Property virtio_properties[] = { DEFINE_VIRTIO_COMMON_FEATURES(VirtIODevice, host_features), DEFINE_PROP_BOOL("use-started", VirtIODevice, use_started, true), DEFINE_PROP_BOOL("use-disabled-flag", VirtIODevice, use_disabled_flag, true), + DEFINE_PROP_BOOL("x-disable-legacy-check", VirtIODevice, + disable_legacy_check, false), DEFINE_PROP_END_OF_LIST(), }; diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index d27da03d64..fe0055fffb 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -290,6 +290,7 @@ Aml *aml_to_buffer(Aml *src, Aml *dst); Aml *aml_store(Aml *val, Aml *target); Aml *aml_and(Aml *arg1, Aml *arg2, Aml *dst); Aml *aml_or(Aml *arg1, Aml *arg2, Aml *dst); +Aml *aml_land(Aml *arg1, Aml *arg2); Aml *aml_lor(Aml *arg1, Aml *arg2); Aml *aml_shiftleft(Aml *arg1, Aml *count); Aml *aml_shiftright(Aml *arg1, Aml *count, Aml *dst); @@ -300,6 +301,7 @@ Aml *aml_increment(Aml *arg); Aml *aml_decrement(Aml *arg); Aml *aml_index(Aml *arg1, Aml *idx); Aml *aml_notify(Aml *arg1, Aml *arg2); +Aml *aml_break(void); Aml *aml_call0(const char *method); Aml *aml_call1(const char *method, Aml *arg1); Aml *aml_call2(const char *method, Aml *arg1, Aml *arg2); diff --git a/include/hw/acpi/cpu.h b/include/hw/acpi/cpu.h index 62f0278ba2..0eeedaa491 100644 --- a/include/hw/acpi/cpu.h +++ b/include/hw/acpi/cpu.h @@ -50,6 +50,7 @@ void cpu_hotplug_hw_init(MemoryRegion *as, Object *owner, typedef struct CPUHotplugFeatures { bool acpi_1_compatible; bool has_legacy_cphp; + const char *smi_path; } CPUHotplugFeatures; void build_cpus_aml(Aml *table, MachineState *machine, CPUHotplugFeatures opts, diff --git a/include/hw/boards.h b/include/hw/boards.h index 56aa1ca335..482d2833f6 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -168,7 +168,6 @@ struct MachineClass { void (*init)(MachineState *state); void (*reset)(MachineState *state); void (*wakeup)(MachineState *state); - void (*hot_add_cpu)(MachineState *state, const int64_t id, Error **errp); int (*kvm_type)(MachineState *machine, const char *arg); void (*smp_parse)(MachineState *ms, QemuOpts *opts); diff --git a/include/hw/i386/ich9.h b/include/hw/i386/ich9.h index 48b442bc0b..294024be5f 100644 --- a/include/hw/i386/ich9.h +++ b/include/hw/i386/ich9.h @@ -245,7 +245,11 @@ struct ICH9LPCState { #define ICH9_SMB_HST_D1 0x06 #define ICH9_SMB_HOST_BLOCK_DB 0x07 +#define ICH9_LPC_SMI_NEGOTIATED_FEAT_PROP "x-smi-negotiated-features" + /* bit positions used in fw_cfg SMI feature negotiation */ #define ICH9_LPC_SMI_F_BROADCAST_BIT 0 +#define ICH9_LPC_SMI_F_CPU_HOTPLUG_BIT 1 +#define ICH9_LPC_SMI_F_CPU_HOT_UNPLUG_BIT 2 #endif /* HW_ICH9_H */ diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index b2da2c8d2b..c71b02cafd 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -132,7 +132,6 @@ extern int fd_bootchk; void pc_acpi_smi_interrupt(void *opaque, int irq, int level); -void pc_hot_add_cpu(MachineState *ms, const int64_t id, Error **errp); void pc_smp_parse(MachineState *ms, QemuOpts *opts); void pc_guest_info_init(PCMachineState *pcms); diff --git a/include/hw/virtio/vhost-backend.h b/include/hw/virtio/vhost-backend.h index 8825bd278f..8a6f8e2a7a 100644 --- a/include/hw/virtio/vhost-backend.h +++ b/include/hw/virtio/vhost-backend.h @@ -74,6 +74,7 @@ typedef int (*vhost_set_features_op)(struct vhost_dev *dev, uint64_t features); typedef int (*vhost_get_features_op)(struct vhost_dev *dev, uint64_t *features); +typedef int (*vhost_set_backend_cap_op)(struct vhost_dev *dev); typedef int (*vhost_set_owner_op)(struct vhost_dev *dev); typedef int (*vhost_reset_device_op)(struct vhost_dev *dev); typedef int (*vhost_get_vq_index_op)(struct vhost_dev *dev, int idx); @@ -146,6 +147,7 @@ typedef struct VhostOps { vhost_set_vring_busyloop_timeout_op vhost_set_vring_busyloop_timeout; vhost_set_features_op vhost_set_features; vhost_get_features_op vhost_get_features; + vhost_set_backend_cap_op vhost_set_backend_cap; vhost_set_owner_op vhost_set_owner; vhost_reset_device_op vhost_reset_device; vhost_get_vq_index_op vhost_get_vq_index; diff --git a/include/hw/virtio/vhost-user-blk.h b/include/hw/virtio/vhost-user-blk.h index f536576d20..7c91f15040 100644 --- a/include/hw/virtio/vhost-user-blk.h +++ b/include/hw/virtio/vhost-user-blk.h @@ -40,7 +40,17 @@ struct VHostUserBlk { VhostUserState vhost_user; struct vhost_virtqueue *vhost_vqs; VirtQueue **virtqs; + + /* + * There are at least two steps of initialization of the + * vhost-user device. The first is a "connect" step and + * second is a "start" step. Make a separation between + * those initialization phases by using two fields. + */ + /* vhost_user_blk_connect/vhost_user_blk_disconnect */ bool connected; + /* vhost_user_blk_start/vhost_user_blk_stop */ + bool started_vu; }; #endif diff --git a/include/hw/virtio/vhost-vdpa.h b/include/hw/virtio/vhost-vdpa.h index 6455663388..9b81a409da 100644 --- a/include/hw/virtio/vhost-vdpa.h +++ b/include/hw/virtio/vhost-vdpa.h @@ -18,6 +18,7 @@ typedef struct vhost_vdpa { int device_fd; uint32_t msg_type; MemoryListener listener; + struct vhost_dev *dev; } VhostVDPA; extern AddressSpace address_space_memory; diff --git a/include/hw/virtio/vhost.h b/include/hw/virtio/vhost.h index 767a95ec0b..94585067f7 100644 --- a/include/hw/virtio/vhost.h +++ b/include/hw/virtio/vhost.h @@ -79,6 +79,7 @@ struct vhost_dev { uint64_t backend_features; uint64_t protocol_features; uint64_t max_queues; + uint64_t backend_cap; bool started; bool log_enabled; uint64_t log_size; diff --git a/include/hw/virtio/virtio.h b/include/hw/virtio/virtio.h index 28cf3b9120..b7ece7a6a8 100644 --- a/include/hw/virtio/virtio.h +++ b/include/hw/virtio/virtio.h @@ -101,6 +101,7 @@ struct VirtIODevice bool use_started; bool started; bool start_on_kick; /* when virtio 1.0 feature has not been negotiated */ + bool disable_legacy_check; VMChangeStateEntry *vmstate; char *bus_name; uint8_t device_endian; @@ -394,5 +395,6 @@ static inline bool virtio_device_disabled(VirtIODevice *vdev) } bool virtio_legacy_allowed(VirtIODevice *vdev); +bool virtio_legacy_check_disabled(VirtIODevice *vdev); #endif diff --git a/include/monitor/hmp.h b/include/monitor/hmp.h index c986cfd28b..642e9e91f9 100644 --- a/include/monitor/hmp.h +++ b/include/monitor/hmp.h @@ -89,7 +89,6 @@ void hmp_chardev_add(Monitor *mon, const QDict *qdict); void hmp_chardev_change(Monitor *mon, const QDict *qdict); void hmp_chardev_remove(Monitor *mon, const QDict *qdict); void hmp_chardev_send_break(Monitor *mon, const QDict *qdict); -void hmp_cpu_add(Monitor *mon, const QDict *qdict); void hmp_object_add(Monitor *mon, const QDict *qdict); void hmp_object_del(Monitor *mon, const QDict *qdict); void hmp_info_memdev(Monitor *mon, const QDict *qdict); diff --git a/include/qemu-common.h b/include/qemu-common.h index 9cfd62669b..cc902b690d 100644 --- a/include/qemu-common.h +++ b/include/qemu-common.h @@ -135,6 +135,14 @@ char *os_find_datadir(void); int os_parse_cmd_args(int index, const char *optarg); /* + * Hexdump a line of a byte buffer into a hexadecimal/ASCII buffer + */ +#define QEMU_HEXDUMP_LINE_BYTES 16 /* Number of bytes to dump */ +#define QEMU_HEXDUMP_LINE_LEN 75 /* Number of characters in line */ +void qemu_hexdump_line(char *line, unsigned int b, const void *bufptr, + unsigned int len, bool ascii); + +/* * Hexdump a buffer to a file. An optional string prefix is added to every line */ diff --git a/include/standard-headers/drm/drm_fourcc.h b/include/standard-headers/drm/drm_fourcc.h index 909a66753c..0de1a552ca 100644 --- a/include/standard-headers/drm/drm_fourcc.h +++ b/include/standard-headers/drm/drm_fourcc.h @@ -235,6 +235,12 @@ extern "C" { #define DRM_FORMAT_NV61 fourcc_code('N', 'V', '6', '1') /* 2x1 subsampled Cb:Cr plane */ #define DRM_FORMAT_NV24 fourcc_code('N', 'V', '2', '4') /* non-subsampled Cr:Cb plane */ #define DRM_FORMAT_NV42 fourcc_code('N', 'V', '4', '2') /* non-subsampled Cb:Cr plane */ +/* + * 2 plane YCbCr + * index 0 = Y plane, [39:0] Y3:Y2:Y1:Y0 little endian + * index 1 = Cr:Cb plane, [39:0] Cr1:Cb1:Cr0:Cb0 little endian + */ +#define DRM_FORMAT_NV15 fourcc_code('N', 'V', '1', '5') /* 2x2 subsampled Cr:Cb plane */ /* * 2 plane YCbCr MSB aligned @@ -264,6 +270,22 @@ extern "C" { */ #define DRM_FORMAT_P016 fourcc_code('P', '0', '1', '6') /* 2x2 subsampled Cr:Cb plane 16 bits per channel */ +/* 3 plane non-subsampled (444) YCbCr + * 16 bits per component, but only 10 bits are used and 6 bits are padded + * index 0: Y plane, [15:0] Y:x [10:6] little endian + * index 1: Cb plane, [15:0] Cb:x [10:6] little endian + * index 2: Cr plane, [15:0] Cr:x [10:6] little endian + */ +#define DRM_FORMAT_Q410 fourcc_code('Q', '4', '1', '0') + +/* 3 plane non-subsampled (444) YCrCb + * 16 bits per component, but only 10 bits are used and 6 bits are padded + * index 0: Y plane, [15:0] Y:x [10:6] little endian + * index 1: Cr plane, [15:0] Cr:x [10:6] little endian + * index 2: Cb plane, [15:0] Cb:x [10:6] little endian + */ +#define DRM_FORMAT_Q401 fourcc_code('Q', '4', '0', '1') + /* * 3 plane YCbCr * index 0: Y plane, [7:0] Y @@ -308,6 +330,7 @@ extern "C" { #define DRM_FORMAT_MOD_VENDOR_BROADCOM 0x07 #define DRM_FORMAT_MOD_VENDOR_ARM 0x08 #define DRM_FORMAT_MOD_VENDOR_ALLWINNER 0x09 +#define DRM_FORMAT_MOD_VENDOR_AMLOGIC 0x0a /* add more to the end as needed */ @@ -322,8 +345,33 @@ extern "C" { * When adding a new token please document the layout with a code comment, * similar to the fourcc codes above. drm_fourcc.h is considered the * authoritative source for all of these. + * + * Generic modifier names: + * + * DRM_FORMAT_MOD_GENERIC_* definitions are used to provide vendor-neutral names + * for layouts which are common across multiple vendors. To preserve + * compatibility, in cases where a vendor-specific definition already exists and + * a generic name for it is desired, the common name is a purely symbolic alias + * and must use the same numerical value as the original definition. + * + * Note that generic names should only be used for modifiers which describe + * generic layouts (such as pixel re-ordering), which may have + * independently-developed support across multiple vendors. + * + * In future cases where a generic layout is identified before merging with a + * vendor-specific modifier, a new 'GENERIC' vendor or modifier using vendor + * 'NONE' could be considered. This should only be for obvious, exceptional + * cases to avoid polluting the 'GENERIC' namespace with modifiers which only + * apply to a single vendor. + * + * Generic names should not be used for cases where multiple hardware vendors + * have implementations of the same standardised compression scheme (such as + * AFBC). In those cases, all implementations should use the same format + * modifier(s), reflecting the vendor of the standard. */ +#define DRM_FORMAT_MOD_GENERIC_16_16_TILE DRM_FORMAT_MOD_SAMSUNG_16_16_TILE + /* * Invalid Modifier * @@ -891,6 +939,18 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) */ #define AFBC_FORMAT_MOD_BCH (1ULL << 11) +/* AFBC uncompressed storage mode + * + * Indicates that the buffer is using AFBC uncompressed storage mode. + * In this mode all superblock payloads in the buffer use the uncompressed + * storage mode, which is usually only used for data which cannot be compressed. + * The buffer layout is the same as for AFBC buffers without USM set, this only + * affects the storage mode of the individual superblocks. Note that even a + * buffer without USM set may use uncompressed storage mode for some or all + * superblocks, USM just guarantees it for all. + */ +#define AFBC_FORMAT_MOD_USM (1ULL << 12) + /* * Arm 16x16 Block U-Interleaved modifier * @@ -915,6 +975,86 @@ drm_fourcc_canonicalize_nvidia_format_mod(uint64_t modifier) */ #define DRM_FORMAT_MOD_ALLWINNER_TILED fourcc_mod_code(ALLWINNER, 1) +/* + * Amlogic Video Framebuffer Compression modifiers + * + * Amlogic uses a proprietary lossless image compression protocol and format + * for their hardware video codec accelerators, either video decoders or + * video input encoders. + * + * It considerably reduces memory bandwidth while writing and reading + * frames in memory. + * + * The underlying storage is considered to be 3 components, 8bit or 10-bit + * per component YCbCr 420, single plane : + * - DRM_FORMAT_YUV420_8BIT + * - DRM_FORMAT_YUV420_10BIT + * + * The first 8 bits of the mode defines the layout, then the following 8 bits + * defines the options changing the layout. + * + * Not all combinations are valid, and different SoCs may support different + * combinations of layout and options. + */ +#define __fourcc_mod_amlogic_layout_mask 0xf +#define __fourcc_mod_amlogic_options_shift 8 +#define __fourcc_mod_amlogic_options_mask 0xf + +#define DRM_FORMAT_MOD_AMLOGIC_FBC(__layout, __options) \ + fourcc_mod_code(AMLOGIC, \ + ((__layout) & __fourcc_mod_amlogic_layout_mask) | \ + (((__options) & __fourcc_mod_amlogic_options_mask) \ + << __fourcc_mod_amlogic_options_shift)) + +/* Amlogic FBC Layouts */ + +/* + * Amlogic FBC Basic Layout + * + * The basic layout is composed of: + * - a body content organized in 64x32 superblocks with 4096 bytes per + * superblock in default mode. + * - a 32 bytes per 128x64 header block + * + * This layout is transferrable between Amlogic SoCs supporting this modifier. + */ +#define AMLOGIC_FBC_LAYOUT_BASIC (1ULL) + +/* + * Amlogic FBC Scatter Memory layout + * + * Indicates the header contains IOMMU references to the compressed + * frames content to optimize memory access and layout. + * + * In this mode, only the header memory address is needed, thus the + * content memory organization is tied to the current producer + * execution and cannot be saved/dumped neither transferrable between + * Amlogic SoCs supporting this modifier. + * + * Due to the nature of the layout, these buffers are not expected to + * be accessible by the user-space clients, but only accessible by the + * hardware producers and consumers. + * + * The user-space clients should expect a failure while trying to mmap + * the DMA-BUF handle returned by the producer. + */ +#define AMLOGIC_FBC_LAYOUT_SCATTER (2ULL) + +/* Amlogic FBC Layout Options Bit Mask */ + +/* + * Amlogic FBC Memory Saving mode + * + * Indicates the storage is packed when pixel size is multiple of word + * boudaries, i.e. 8bit should be stored in this mode to save allocation + * memory. + * + * This mode reduces body layout to 3072 bytes per 64x32 superblock with + * the basic layout and 3200 bytes per 64x32 superblock combined with + * the scatter layout. + */ +#define AMLOGIC_FBC_OPTION_MEM_SAVING (1ULL << 0) + #if defined(__cplusplus) } #endif diff --git a/include/standard-headers/linux/ethtool.h b/include/standard-headers/linux/ethtool.h index fd8d2cccfe..e13eff4488 100644 --- a/include/standard-headers/linux/ethtool.h +++ b/include/standard-headers/linux/ethtool.h @@ -579,6 +579,76 @@ struct ethtool_pauseparam { uint32_t tx_pause; }; +/** + * enum ethtool_link_ext_state - link extended state + */ +enum ethtool_link_ext_state { + ETHTOOL_LINK_EXT_STATE_AUTONEG, + ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE, + ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH, + ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY, + ETHTOOL_LINK_EXT_STATE_NO_CABLE, + ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE, + ETHTOOL_LINK_EXT_STATE_EEPROM_ISSUE, + ETHTOOL_LINK_EXT_STATE_CALIBRATION_FAILURE, + ETHTOOL_LINK_EXT_STATE_POWER_BUDGET_EXCEEDED, + ETHTOOL_LINK_EXT_STATE_OVERHEAT, +}; + +/** + * enum ethtool_link_ext_substate_autoneg - more information in addition to + * ETHTOOL_LINK_EXT_STATE_AUTONEG. + */ +enum ethtool_link_ext_substate_autoneg { + ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED = 1, + ETHTOOL_LINK_EXT_SUBSTATE_AN_ACK_NOT_RECEIVED, + ETHTOOL_LINK_EXT_SUBSTATE_AN_NEXT_PAGE_EXCHANGE_FAILED, + ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_PARTNER_DETECTED_FORCE_MODE, + ETHTOOL_LINK_EXT_SUBSTATE_AN_FEC_MISMATCH_DURING_OVERRIDE, + ETHTOOL_LINK_EXT_SUBSTATE_AN_NO_HCD, +}; + +/** + * enum ethtool_link_ext_substate_link_training - more information in addition to + * ETHTOOL_LINK_EXT_STATE_LINK_TRAINING_FAILURE. + */ +enum ethtool_link_ext_substate_link_training { + ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_FRAME_LOCK_NOT_ACQUIRED = 1, + ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_INHIBIT_TIMEOUT, + ETHTOOL_LINK_EXT_SUBSTATE_LT_KR_LINK_PARTNER_DID_NOT_SET_RECEIVER_READY, + ETHTOOL_LINK_EXT_SUBSTATE_LT_REMOTE_FAULT, +}; + +/** + * enum ethtool_link_ext_substate_logical_mismatch - more information in addition + * to ETHTOOL_LINK_EXT_STATE_LINK_LOGICAL_MISMATCH. + */ +enum ethtool_link_ext_substate_link_logical_mismatch { + ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_BLOCK_LOCK = 1, + ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_ACQUIRE_AM_LOCK, + ETHTOOL_LINK_EXT_SUBSTATE_LLM_PCS_DID_NOT_GET_ALIGN_STATUS, + ETHTOOL_LINK_EXT_SUBSTATE_LLM_FC_FEC_IS_NOT_LOCKED, + ETHTOOL_LINK_EXT_SUBSTATE_LLM_RS_FEC_IS_NOT_LOCKED, +}; + +/** + * enum ethtool_link_ext_substate_bad_signal_integrity - more information in + * addition to ETHTOOL_LINK_EXT_STATE_BAD_SIGNAL_INTEGRITY. + */ +enum ethtool_link_ext_substate_bad_signal_integrity { + ETHTOOL_LINK_EXT_SUBSTATE_BSI_LARGE_NUMBER_OF_PHYSICAL_ERRORS = 1, + ETHTOOL_LINK_EXT_SUBSTATE_BSI_UNSUPPORTED_RATE, +}; + +/** + * enum ethtool_link_ext_substate_cable_issue - more information in + * addition to ETHTOOL_LINK_EXT_STATE_CABLE_ISSUE. + */ +enum ethtool_link_ext_substate_cable_issue { + ETHTOOL_LINK_EXT_SUBSTATE_CI_UNSUPPORTED_CABLE = 1, + ETHTOOL_LINK_EXT_SUBSTATE_CI_CABLE_TEST_FAILURE, +}; + #define ETH_GSTRING_LEN 32 /** @@ -599,6 +669,7 @@ struct ethtool_pauseparam { * @ETH_SS_SOF_TIMESTAMPING: SOF_TIMESTAMPING_* flags * @ETH_SS_TS_TX_TYPES: timestamping Tx types * @ETH_SS_TS_RX_FILTERS: timestamping Rx filters + * @ETH_SS_UDP_TUNNEL_TYPES: UDP tunnel types */ enum ethtool_stringset { ETH_SS_TEST = 0, @@ -616,6 +687,7 @@ enum ethtool_stringset { ETH_SS_SOF_TIMESTAMPING, ETH_SS_TS_TX_TYPES, ETH_SS_TS_RX_FILTERS, + ETH_SS_UDP_TUNNEL_TYPES, /* add new constants above here */ ETH_SS_COUNT @@ -1530,6 +1602,21 @@ enum ethtool_link_mode_bit_indices { ETHTOOL_LINK_MODE_400000baseDR8_Full_BIT = 72, ETHTOOL_LINK_MODE_400000baseCR8_Full_BIT = 73, ETHTOOL_LINK_MODE_FEC_LLRS_BIT = 74, + ETHTOOL_LINK_MODE_100000baseKR_Full_BIT = 75, + ETHTOOL_LINK_MODE_100000baseSR_Full_BIT = 76, + ETHTOOL_LINK_MODE_100000baseLR_ER_FR_Full_BIT = 77, + ETHTOOL_LINK_MODE_100000baseCR_Full_BIT = 78, + ETHTOOL_LINK_MODE_100000baseDR_Full_BIT = 79, + ETHTOOL_LINK_MODE_200000baseKR2_Full_BIT = 80, + ETHTOOL_LINK_MODE_200000baseSR2_Full_BIT = 81, + ETHTOOL_LINK_MODE_200000baseLR2_ER2_FR2_Full_BIT = 82, + ETHTOOL_LINK_MODE_200000baseDR2_Full_BIT = 83, + ETHTOOL_LINK_MODE_200000baseCR2_Full_BIT = 84, + ETHTOOL_LINK_MODE_400000baseKR4_Full_BIT = 85, + ETHTOOL_LINK_MODE_400000baseSR4_Full_BIT = 86, + ETHTOOL_LINK_MODE_400000baseLR4_ER4_FR4_Full_BIT = 87, + ETHTOOL_LINK_MODE_400000baseDR4_Full_BIT = 88, + ETHTOOL_LINK_MODE_400000baseCR4_Full_BIT = 89, /* must be last entry */ __ETHTOOL_LINK_MODE_MASK_NBITS }; diff --git a/include/standard-headers/linux/input-event-codes.h b/include/standard-headers/linux/input-event-codes.h index ebf72c1031..e740ad9f2e 100644 --- a/include/standard-headers/linux/input-event-codes.h +++ b/include/standard-headers/linux/input-event-codes.h @@ -888,7 +888,8 @@ #define SW_LINEIN_INSERT 0x0d /* set = inserted */ #define SW_MUTE_DEVICE 0x0e /* set = device disabled */ #define SW_PEN_INSERTED 0x0f /* set = pen inserted */ -#define SW_MAX_ 0x0f +#define SW_MACHINE_COVER 0x10 /* set = cover closed */ +#define SW_MAX_ 0x10 #define SW_CNT (SW_MAX_+1) /* diff --git a/include/standard-headers/linux/vhost_types.h b/include/standard-headers/linux/vhost_types.h index a678d8fbaa..486630b332 100644 --- a/include/standard-headers/linux/vhost_types.h +++ b/include/standard-headers/linux/vhost_types.h @@ -60,6 +60,17 @@ struct vhost_iotlb_msg { #define VHOST_IOTLB_UPDATE 2 #define VHOST_IOTLB_INVALIDATE 3 #define VHOST_IOTLB_ACCESS_FAIL 4 +/* + * VHOST_IOTLB_BATCH_BEGIN and VHOST_IOTLB_BATCH_END allow modifying + * multiple mappings in one go: beginning with + * VHOST_IOTLB_BATCH_BEGIN, followed by any number of + * VHOST_IOTLB_UPDATE messages, and ending with VHOST_IOTLB_BATCH_END. + * When one of these two values is used as the message type, the rest + * of the fields in the message are ignored. There's no guarantee that + * these changes take place automatically in the device. + */ +#define VHOST_IOTLB_BATCH_BEGIN 5 +#define VHOST_IOTLB_BATCH_END 6 uint8_t type; }; diff --git a/include/standard-headers/linux/virtio_9p.h b/include/standard-headers/linux/virtio_9p.h index e68f71dbe6..f5604fc5fb 100644 --- a/include/standard-headers/linux/virtio_9p.h +++ b/include/standard-headers/linux/virtio_9p.h @@ -25,7 +25,7 @@ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF * SUCH DAMAGE. */ -#include "standard-headers/linux/types.h" +#include "standard-headers/linux/virtio_types.h" #include "standard-headers/linux/virtio_ids.h" #include "standard-headers/linux/virtio_config.h" @@ -36,7 +36,7 @@ struct virtio_9p_config { /* length of the tag name */ - uint16_t tag_len; + __virtio16 tag_len; /* non-NULL terminated tag name */ uint8_t tag[0]; } QEMU_PACKED; diff --git a/include/standard-headers/linux/virtio_blk.h b/include/standard-headers/linux/virtio_blk.h index 0229b0fbe4..2dcc90826a 100644 --- a/include/standard-headers/linux/virtio_blk.h +++ b/include/standard-headers/linux/virtio_blk.h @@ -55,20 +55,20 @@ struct virtio_blk_config { /* The capacity (in 512-byte sectors). */ - uint64_t capacity; + __virtio64 capacity; /* The maximum segment size (if VIRTIO_BLK_F_SIZE_MAX) */ - uint32_t size_max; + __virtio32 size_max; /* The maximum number of segments (if VIRTIO_BLK_F_SEG_MAX) */ - uint32_t seg_max; + __virtio32 seg_max; /* geometry of the device (if VIRTIO_BLK_F_GEOMETRY) */ struct virtio_blk_geometry { - uint16_t cylinders; + __virtio16 cylinders; uint8_t heads; uint8_t sectors; } geometry; /* block size of device (if VIRTIO_BLK_F_BLK_SIZE) */ - uint32_t blk_size; + __virtio32 blk_size; /* the next 4 entries are guarded by VIRTIO_BLK_F_TOPOLOGY */ /* exponent for physical block per logical block. */ @@ -76,42 +76,42 @@ struct virtio_blk_config { /* alignment offset in logical blocks. */ uint8_t alignment_offset; /* minimum I/O size without performance penalty in logical blocks. */ - uint16_t min_io_size; + __virtio16 min_io_size; /* optimal sustained I/O size in logical blocks. */ - uint32_t opt_io_size; + __virtio32 opt_io_size; /* writeback mode (if VIRTIO_BLK_F_CONFIG_WCE) */ uint8_t wce; uint8_t unused; /* number of vqs, only available when VIRTIO_BLK_F_MQ is set */ - uint16_t num_queues; + __virtio16 num_queues; /* the next 3 entries are guarded by VIRTIO_BLK_F_DISCARD */ /* * The maximum discard sectors (in 512-byte sectors) for * one segment. */ - uint32_t max_discard_sectors; + __virtio32 max_discard_sectors; /* * The maximum number of discard segments in a * discard command. */ - uint32_t max_discard_seg; + __virtio32 max_discard_seg; /* Discard commands must be aligned to this number of sectors. */ - uint32_t discard_sector_alignment; + __virtio32 discard_sector_alignment; /* the next 3 entries are guarded by VIRTIO_BLK_F_WRITE_ZEROES */ /* * The maximum number of write zeroes sectors (in 512-byte sectors) in * one segment. */ - uint32_t max_write_zeroes_sectors; + __virtio32 max_write_zeroes_sectors; /* * The maximum number of segments in a write zeroes * command. */ - uint32_t max_write_zeroes_seg; + __virtio32 max_write_zeroes_seg; /* * Set if a VIRTIO_BLK_T_WRITE_ZEROES request may result in the * deallocation of one or more of the sectors. diff --git a/include/standard-headers/linux/virtio_config.h b/include/standard-headers/linux/virtio_config.h index 9a69d9e242..22e3a85f67 100644 --- a/include/standard-headers/linux/virtio_config.h +++ b/include/standard-headers/linux/virtio_config.h @@ -67,13 +67,15 @@ #define VIRTIO_F_VERSION_1 32 /* - * If clear - device has the IOMMU bypass quirk feature. - * If set - use platform tools to detect the IOMMU. + * If clear - device has the platform DMA (e.g. IOMMU) bypass quirk feature. + * If set - use platform DMA tools to access the memory. * * Note the reverse polarity (compared to most other features), * this is for compatibility with legacy systems. */ -#define VIRTIO_F_IOMMU_PLATFORM 33 +#define VIRTIO_F_ACCESS_PLATFORM 33 +/* Legacy name for VIRTIO_F_ACCESS_PLATFORM (for compatibility with old userspace) */ +#define VIRTIO_F_IOMMU_PLATFORM VIRTIO_F_ACCESS_PLATFORM /* This feature indicates support for the packed virtqueue layout. */ #define VIRTIO_F_RING_PACKED 34 diff --git a/include/standard-headers/linux/virtio_console.h b/include/standard-headers/linux/virtio_console.h index 0dedc9e6f5..71f5f648e3 100644 --- a/include/standard-headers/linux/virtio_console.h +++ b/include/standard-headers/linux/virtio_console.h @@ -45,13 +45,13 @@ struct virtio_console_config { /* colums of the screens */ - uint16_t cols; + __virtio16 cols; /* rows of the screens */ - uint16_t rows; + __virtio16 rows; /* max. number of ports this device can hold */ - uint32_t max_nr_ports; + __virtio32 max_nr_ports; /* emergency write register */ - uint32_t emerg_wr; + __virtio32 emerg_wr; } QEMU_PACKED; /* diff --git a/include/standard-headers/linux/virtio_net.h b/include/standard-headers/linux/virtio_net.h index a90f79e1b1..e0a070518f 100644 --- a/include/standard-headers/linux/virtio_net.h +++ b/include/standard-headers/linux/virtio_net.h @@ -87,14 +87,14 @@ struct virtio_net_config { /* The config defining mac address (if VIRTIO_NET_F_MAC) */ uint8_t mac[ETH_ALEN]; /* See VIRTIO_NET_F_STATUS and VIRTIO_NET_S_* above */ - uint16_t status; + __virtio16 status; /* Maximum number of each of transmit and receive queues; * see VIRTIO_NET_F_MQ and VIRTIO_NET_CTRL_MQ. * Legal values are between 1 and 0x8000 */ - uint16_t max_virtqueue_pairs; + __virtio16 max_virtqueue_pairs; /* Default maximum transmit unit advice */ - uint16_t mtu; + __virtio16 mtu; /* * speed, in units of 1Mb. All values 0 to INT_MAX are legal. * Any other value stands for unknown. diff --git a/include/standard-headers/linux/virtio_scsi.h b/include/standard-headers/linux/virtio_scsi.h index ab66166b6a..663f36cbb7 100644 --- a/include/standard-headers/linux/virtio_scsi.h +++ b/include/standard-headers/linux/virtio_scsi.h @@ -103,16 +103,16 @@ struct virtio_scsi_event { } QEMU_PACKED; struct virtio_scsi_config { - uint32_t num_queues; - uint32_t seg_max; - uint32_t max_sectors; - uint32_t cmd_per_lun; - uint32_t event_info_size; - uint32_t sense_size; - uint32_t cdb_size; - uint16_t max_channel; - uint16_t max_target; - uint32_t max_lun; + __virtio32 num_queues; + __virtio32 seg_max; + __virtio32 max_sectors; + __virtio32 cmd_per_lun; + __virtio32 event_info_size; + __virtio32 sense_size; + __virtio32 cdb_size; + __virtio16 max_channel; + __virtio16 max_target; + __virtio32 max_lun; } QEMU_PACKED; /* Feature Bits */ diff --git a/linux-headers/asm-generic/unistd.h b/linux-headers/asm-generic/unistd.h index f4a01305d9..995b36c2ea 100644 --- a/linux-headers/asm-generic/unistd.h +++ b/linux-headers/asm-generic/unistd.h @@ -606,9 +606,9 @@ __SYSCALL(__NR_sendto, sys_sendto) #define __NR_recvfrom 207 __SC_COMP(__NR_recvfrom, sys_recvfrom, compat_sys_recvfrom) #define __NR_setsockopt 208 -__SC_COMP(__NR_setsockopt, sys_setsockopt, compat_sys_setsockopt) +__SC_COMP(__NR_setsockopt, sys_setsockopt, sys_setsockopt) #define __NR_getsockopt 209 -__SC_COMP(__NR_getsockopt, sys_getsockopt, compat_sys_getsockopt) +__SC_COMP(__NR_getsockopt, sys_getsockopt, sys_getsockopt) #define __NR_shutdown 210 __SYSCALL(__NR_shutdown, sys_shutdown) #define __NR_sendmsg 211 @@ -850,6 +850,8 @@ __SYSCALL(__NR_pidfd_open, sys_pidfd_open) #define __NR_clone3 435 __SYSCALL(__NR_clone3, sys_clone3) #endif +#define __NR_close_range 436 +__SYSCALL(__NR_close_range, sys_close_range) #define __NR_openat2 437 __SYSCALL(__NR_openat2, sys_openat2) diff --git a/linux-headers/asm-mips/unistd_n32.h b/linux-headers/asm-mips/unistd_n32.h index 3b9eda7e7d..246fbb6a78 100644 --- a/linux-headers/asm-mips/unistd_n32.h +++ b/linux-headers/asm-mips/unistd_n32.h @@ -365,6 +365,7 @@ #define __NR_fspick (__NR_Linux + 433) #define __NR_pidfd_open (__NR_Linux + 434) #define __NR_clone3 (__NR_Linux + 435) +#define __NR_close_range (__NR_Linux + 436) #define __NR_openat2 (__NR_Linux + 437) #define __NR_pidfd_getfd (__NR_Linux + 438) #define __NR_faccessat2 (__NR_Linux + 439) diff --git a/linux-headers/asm-mips/unistd_n64.h b/linux-headers/asm-mips/unistd_n64.h index 9cdf9b6c60..194d777dfd 100644 --- a/linux-headers/asm-mips/unistd_n64.h +++ b/linux-headers/asm-mips/unistd_n64.h @@ -341,6 +341,7 @@ #define __NR_fspick (__NR_Linux + 433) #define __NR_pidfd_open (__NR_Linux + 434) #define __NR_clone3 (__NR_Linux + 435) +#define __NR_close_range (__NR_Linux + 436) #define __NR_openat2 (__NR_Linux + 437) #define __NR_pidfd_getfd (__NR_Linux + 438) #define __NR_faccessat2 (__NR_Linux + 439) diff --git a/linux-headers/asm-mips/unistd_o32.h b/linux-headers/asm-mips/unistd_o32.h index e3e5e238f0..3e093dd913 100644 --- a/linux-headers/asm-mips/unistd_o32.h +++ b/linux-headers/asm-mips/unistd_o32.h @@ -411,6 +411,7 @@ #define __NR_fspick (__NR_Linux + 433) #define __NR_pidfd_open (__NR_Linux + 434) #define __NR_clone3 (__NR_Linux + 435) +#define __NR_close_range (__NR_Linux + 436) #define __NR_openat2 (__NR_Linux + 437) #define __NR_pidfd_getfd (__NR_Linux + 438) #define __NR_faccessat2 (__NR_Linux + 439) diff --git a/linux-headers/asm-powerpc/kvm.h b/linux-headers/asm-powerpc/kvm.h index 264e266a85..c3af3f324c 100644 --- a/linux-headers/asm-powerpc/kvm.h +++ b/linux-headers/asm-powerpc/kvm.h @@ -640,6 +640,11 @@ struct kvm_ppc_cpu_char { #define KVM_REG_PPC_ONLINE (KVM_REG_PPC | KVM_REG_SIZE_U32 | 0xbf) #define KVM_REG_PPC_PTCR (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc0) +/* POWER10 registers */ +#define KVM_REG_PPC_MMCR3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc1) +#define KVM_REG_PPC_SIER2 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc2) +#define KVM_REG_PPC_SIER3 (KVM_REG_PPC | KVM_REG_SIZE_U64 | 0xc3) + /* Transactional Memory checkpointed state: * This is all GPRs, all VSX regs and a subset of SPRs */ diff --git a/linux-headers/asm-powerpc/unistd_32.h b/linux-headers/asm-powerpc/unistd_32.h index 862edb7448..0db9481d49 100644 --- a/linux-headers/asm-powerpc/unistd_32.h +++ b/linux-headers/asm-powerpc/unistd_32.h @@ -418,6 +418,7 @@ #define __NR_fspick 433 #define __NR_pidfd_open 434 #define __NR_clone3 435 +#define __NR_close_range 436 #define __NR_openat2 437 #define __NR_pidfd_getfd 438 #define __NR_faccessat2 439 diff --git a/linux-headers/asm-powerpc/unistd_64.h b/linux-headers/asm-powerpc/unistd_64.h index f553224ce4..9f74310988 100644 --- a/linux-headers/asm-powerpc/unistd_64.h +++ b/linux-headers/asm-powerpc/unistd_64.h @@ -390,6 +390,7 @@ #define __NR_fspick 433 #define __NR_pidfd_open 434 #define __NR_clone3 435 +#define __NR_close_range 436 #define __NR_openat2 437 #define __NR_pidfd_getfd 438 #define __NR_faccessat2 439 diff --git a/linux-headers/asm-s390/kvm.h b/linux-headers/asm-s390/kvm.h index 0138ccb0d8..f053b8304a 100644 --- a/linux-headers/asm-s390/kvm.h +++ b/linux-headers/asm-s390/kvm.h @@ -231,11 +231,13 @@ struct kvm_guest_debug_arch { #define KVM_SYNC_GSCB (1UL << 9) #define KVM_SYNC_BPBC (1UL << 10) #define KVM_SYNC_ETOKEN (1UL << 11) +#define KVM_SYNC_DIAG318 (1UL << 12) #define KVM_SYNC_S390_VALID_FIELDS \ (KVM_SYNC_PREFIX | KVM_SYNC_GPRS | KVM_SYNC_ACRS | KVM_SYNC_CRS | \ KVM_SYNC_ARCH0 | KVM_SYNC_PFAULT | KVM_SYNC_VRS | KVM_SYNC_RICCB | \ - KVM_SYNC_FPRS | KVM_SYNC_GSCB | KVM_SYNC_BPBC | KVM_SYNC_ETOKEN) + KVM_SYNC_FPRS | KVM_SYNC_GSCB | KVM_SYNC_BPBC | KVM_SYNC_ETOKEN | \ + KVM_SYNC_DIAG318) /* length and alignment of the sdnx as a power of two */ #define SDNXC 8 @@ -264,7 +266,8 @@ struct kvm_sync_regs { __u8 reserved2 : 7; __u8 padding1[51]; /* riccb needs to be 64byte aligned */ __u8 riccb[64]; /* runtime instrumentation controls block */ - __u8 padding2[192]; /* sdnx needs to be 256byte aligned */ + __u64 diag318; /* diagnose 0x318 info */ + __u8 padding2[184]; /* sdnx needs to be 256byte aligned */ union { __u8 sdnx[SDNXL]; /* state description annex */ struct { diff --git a/linux-headers/asm-s390/unistd_32.h b/linux-headers/asm-s390/unistd_32.h index e08233c0c3..1803cd0c3b 100644 --- a/linux-headers/asm-s390/unistd_32.h +++ b/linux-headers/asm-s390/unistd_32.h @@ -408,6 +408,7 @@ #define __NR_fspick 433 #define __NR_pidfd_open 434 #define __NR_clone3 435 +#define __NR_close_range 436 #define __NR_openat2 437 #define __NR_pidfd_getfd 438 #define __NR_faccessat2 439 diff --git a/linux-headers/asm-s390/unistd_64.h b/linux-headers/asm-s390/unistd_64.h index 560e19ae2b..228d5004e5 100644 --- a/linux-headers/asm-s390/unistd_64.h +++ b/linux-headers/asm-s390/unistd_64.h @@ -356,6 +356,7 @@ #define __NR_fspick 433 #define __NR_pidfd_open 434 #define __NR_clone3 435 +#define __NR_close_range 436 #define __NR_openat2 437 #define __NR_pidfd_getfd 438 #define __NR_faccessat2 439 diff --git a/linux-headers/asm-x86/unistd_32.h b/linux-headers/asm-x86/unistd_32.h index c727981d4a..356c12c2db 100644 --- a/linux-headers/asm-x86/unistd_32.h +++ b/linux-headers/asm-x86/unistd_32.h @@ -426,6 +426,7 @@ #define __NR_fspick 433 #define __NR_pidfd_open 434 #define __NR_clone3 435 +#define __NR_close_range 436 #define __NR_openat2 437 #define __NR_pidfd_getfd 438 #define __NR_faccessat2 439 diff --git a/linux-headers/asm-x86/unistd_64.h b/linux-headers/asm-x86/unistd_64.h index 843fa62745..ef70e1c7c9 100644 --- a/linux-headers/asm-x86/unistd_64.h +++ b/linux-headers/asm-x86/unistd_64.h @@ -348,6 +348,7 @@ #define __NR_fspick 433 #define __NR_pidfd_open 434 #define __NR_clone3 435 +#define __NR_close_range 436 #define __NR_openat2 437 #define __NR_pidfd_getfd 438 #define __NR_faccessat2 439 diff --git a/linux-headers/asm-x86/unistd_x32.h b/linux-headers/asm-x86/unistd_x32.h index 7d63d703ca..84ae8e9f5f 100644 --- a/linux-headers/asm-x86/unistd_x32.h +++ b/linux-headers/asm-x86/unistd_x32.h @@ -301,6 +301,7 @@ #define __NR_fspick (__X32_SYSCALL_BIT + 433) #define __NR_pidfd_open (__X32_SYSCALL_BIT + 434) #define __NR_clone3 (__X32_SYSCALL_BIT + 435) +#define __NR_close_range (__X32_SYSCALL_BIT + 436) #define __NR_openat2 (__X32_SYSCALL_BIT + 437) #define __NR_pidfd_getfd (__X32_SYSCALL_BIT + 438) #define __NR_faccessat2 (__X32_SYSCALL_BIT + 439) diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index a28c366737..6683e2e1b0 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -289,6 +289,7 @@ struct kvm_run { /* KVM_EXIT_FAIL_ENTRY */ struct { __u64 hardware_entry_failure_reason; + __u32 cpu; } fail_entry; /* KVM_EXIT_EXCEPTION */ struct { @@ -1031,6 +1032,9 @@ struct kvm_ppc_resize_hpt { #define KVM_CAP_PPC_SECURE_GUEST 181 #define KVM_CAP_HALT_POLL 182 #define KVM_CAP_ASYNC_PF_INT 183 +#define KVM_CAP_LAST_CPU 184 +#define KVM_CAP_SMALLER_MAXPHYADDR 185 +#define KVM_CAP_S390_DIAG318 186 #ifdef KVM_CAP_IRQ_ROUTING diff --git a/linux-headers/linux/vfio.h b/linux-headers/linux/vfio.h index f09df262c4..a90672494d 100644 --- a/linux-headers/linux/vfio.h +++ b/linux-headers/linux/vfio.h @@ -1030,7 +1030,7 @@ struct vfio_iommu_type1_info_cap_iova_range { * size in bytes that can be used by user applications when getting the dirty * bitmap. */ -#define VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION 1 +#define VFIO_IOMMU_TYPE1_INFO_CAP_MIGRATION 2 struct vfio_iommu_type1_info_cap_migration { struct vfio_info_cap_header header; diff --git a/linux-headers/linux/vhost.h b/linux-headers/linux/vhost.h index 0c2349612e..7523218532 100644 --- a/linux-headers/linux/vhost.h +++ b/linux-headers/linux/vhost.h @@ -91,6 +91,8 @@ /* Use message type V2 */ #define VHOST_BACKEND_F_IOTLB_MSG_V2 0x1 +/* IOTLB can accept batching hints */ +#define VHOST_BACKEND_F_IOTLB_BATCH 0x2 #define VHOST_SET_BACKEND_FEATURES _IOW(VHOST_VIRTIO, 0x25, __u64) #define VHOST_GET_BACKEND_FEATURES _IOR(VHOST_VIRTIO, 0x26, __u64) diff --git a/meson.build b/meson.build index b26c8bffc6..d36dd085b5 100644 --- a/meson.build +++ b/meson.build @@ -521,6 +521,7 @@ kconfig_external_symbols = [ 'CONFIG_OPENGL', 'CONFIG_X11', 'CONFIG_VHOST_USER', + 'CONFIG_VHOST_VDPA', 'CONFIG_VHOST_KERNEL', 'CONFIG_VIRTFS', 'CONFIG_LINUX', diff --git a/migration/migration.c b/migration/migration.c index 838ca79f57..aca7fdcd0b 100644 --- a/migration/migration.c +++ b/migration/migration.c @@ -238,15 +238,12 @@ void migration_incoming_state_destroy(void) mis->postcopy_remote_fds = NULL; } + qemu_event_reset(&mis->main_thread_load_event); + if (mis->socket_address_list) { qapi_free_SocketAddressList(mis->socket_address_list); mis->socket_address_list = NULL; } - - qemu_event_destroy(&mis->main_thread_load_event); - qemu_sem_destroy(&mis->postcopy_pause_sem_dst); - qemu_sem_destroy(&mis->postcopy_pause_sem_fault); - qemu_mutex_destroy(&mis->rp_mutex); } static void migrate_generate_event(int new_state) diff --git a/net/vhost-user.c b/net/vhost-user.c index 17532daaf3..ffbd94d944 100644 --- a/net/vhost-user.c +++ b/net/vhost-user.c @@ -226,7 +226,7 @@ static void chr_closed_bh(void *opaque) NetClientState *ncs[MAX_QUEUE_NUM]; NetVhostUserState *s; Error *err = NULL; - int queues; + int queues, i; queues = qemu_find_net_clients_except(name, ncs, NET_CLIENT_DRIVER_NIC, @@ -235,8 +235,12 @@ static void chr_closed_bh(void *opaque) s = DO_UPCAST(NetVhostUserState, nc, ncs[0]); - if (s->vhost_net) { - s->acked_features = vhost_net_get_acked_features(s->vhost_net); + for (i = queues -1; i >= 0; i--) { + s = DO_UPCAST(NetVhostUserState, nc, ncs[i]); + + if (s->vhost_net) { + s->acked_features = vhost_net_get_acked_features(s->vhost_net); + } } qmp_set_link(name, false, &err); diff --git a/qapi/machine.json b/qapi/machine.json index 0ac1880e4a..d8ed096e9a 100644 --- a/qapi/machine.json +++ b/qapi/machine.json @@ -308,30 +308,6 @@ { 'command': 'query-cpus-fast', 'returns': [ 'CpuInfoFast' ] } ## -# @cpu-add: -# -# Adds CPU with specified ID. -# -# @id: ID of CPU to be created, valid values [0..max_cpus) -# -# Features: -# @deprecated: This command is deprecated. Use `device_add` instead. -# See the `query-hotpluggable-cpus` command for details. -# -# Returns: Nothing on success -# -# Since: 1.5 -# -# Example: -# -# -> { "execute": "cpu-add", "arguments": { "id": 2 } } -# <- { "return": {} } -# -## -{ 'command': 'cpu-add', 'data': {'id': 'int'}, - 'features': [ 'deprecated' ] } - -## # @MachineInfo: # # Information describing a machine. diff --git a/qemu-options.hx b/qemu-options.hx index 47f64be0c0..3564c2303f 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -2296,6 +2296,8 @@ DEF("smbios", HAS_ARG, QEMU_OPTION_smbios, "-smbios type=4[,sock_pfx=str][,manufacturer=str][,version=str][,serial=str]\n" " [,asset=str][,part=str][,max-speed=%d][,current-speed=%d]\n" " specify SMBIOS type 4 fields\n" + "-smbios type=11[,value=str][,path=filename]\n" + " specify SMBIOS type 11 fields\n" "-smbios type=17[,loc_pfx=str][,bank=str][,manufacturer=str][,serial=str]\n" " [,asset=str][,part=str][,speed=%d]\n" " specify SMBIOS type 17 fields\n", @@ -2319,6 +2321,45 @@ SRST ``-smbios type=4[,sock_pfx=str][,manufacturer=str][,version=str][,serial=str][,asset=str][,part=str]`` Specify SMBIOS type 4 fields +``-smbios type=11[,value=str][,path=filename]`` + Specify SMBIOS type 11 fields + + This argument can be repeated multiple times, and values are added in the order they are parsed. + Applications intending to use OEM strings data are encouraged to use their application name as + a prefix for the value string. This facilitates passing information for multiple applications + concurrently. + + The ``value=str`` syntax provides the string data inline, while the ``path=filename`` syntax + loads data from a file on disk. Note that the file is not permitted to contain any NUL bytes. + + Both the ``value`` and ``path`` options can be repeated multiple times and will be added to + the SMBIOS table in the order in which they appear. + + Note that on the x86 architecture, the total size of all SMBIOS tables is limited to 65535 + bytes. Thus the OEM strings data is not suitable for passing large amounts of data into the + guest. Instead it should be used as a indicator to inform the guest where to locate the real + data set, for example, by specifying the serial ID of a block device. + + An example passing three strings is + + .. parsed-literal:: + + -smbios type=11,value=cloud-init:ds=nocloud-net;s=http://10.10.0.1:8000/,\\ + value=anaconda:method=http://dl.fedoraproject.org/pub/fedora/linux/releases/25/x86_64/os,\\ + path=/some/file/with/oemstringsdata.txt + + In the guest OS this is visible with the ``dmidecode`` command + + .. parsed-literal:: + + $ dmidecode -t 11 + Handle 0x0E00, DMI type 11, 5 bytes + OEM Strings + String 1: cloud-init:ds=nocloud-net;s=http://10.10.0.1:8000/ + String 2: anaconda:method=http://dl.fedoraproject.org/pub/fedora/linux/releases/25/x86_64/os + String 3: myapp:some extra data + + ``-smbios type=17[,loc_pfx=str][,bank=str][,manufacturer=str][,serial=str][,asset=str][,part=str][,speed=%d]`` Specify SMBIOS type 17 fields ERST diff --git a/tests/.vhost-user-test.c.swo b/tests/.vhost-user-test.c.swo new file mode 100644 index 0000000000..5545d2bef3 --- /dev/null +++ b/tests/.vhost-user-test.c.swo Binary files differdiff --git a/tests/Makefile.include.orig b/tests/Makefile.include.orig new file mode 100644 index 0000000000..ba82235bd4 --- /dev/null +++ b/tests/Makefile.include.orig @@ -0,0 +1,1012 @@ + +.PHONY: check-help +check-help: + @echo "Regression testing targets:" + @echo + @echo " $(MAKE) check Run all tests" + @echo " $(MAKE) check-qtest-TARGET Run qtest tests for given target" + @echo " $(MAKE) check-qtest Run qtest tests" + @echo " $(MAKE) check-unit Run qobject tests" + @echo " $(MAKE) check-speed Run qobject speed tests" + @echo " $(MAKE) check-qapi-schema Run QAPI schema tests" + @echo " $(MAKE) check-block Run block tests" + @echo " $(MAKE) check-tcg Run TCG tests" + @echo " $(MAKE) check-acceptance Run all acceptance (functional) tests" + @echo " $(MAKE) check-report.html Generates an HTML test report" + @echo " $(MAKE) check-venv Creates a Python venv for tests" + @echo " $(MAKE) check-clean Clean the tests" + @echo + @echo "Please note that HTML reports do not regenerate if the unit tests" + @echo "has not changed." + @echo + @echo "The variable SPEED can be set to control the gtester speed setting." + @echo "Default options are -k and (for $(MAKE) V=1) --verbose; they can be" + @echo "changed with variable GTESTER_OPTIONS." + +ifneq ($(wildcard config-host.mak),) +export SRC_PATH + +# TODO don't duplicate $(SRC_PATH)/Makefile's qapi-py here +qapi-py = $(SRC_PATH)/scripts/qapi/commands.py \ +$(SRC_PATH)/scripts/qapi/events.py \ +$(SRC_PATH)/scripts/qapi/introspect.py \ +$(SRC_PATH)/scripts/qapi/types.py \ +$(SRC_PATH)/scripts/qapi/visit.py \ +$(SRC_PATH)/scripts/qapi/common.py \ +$(SRC_PATH)/scripts/qapi/doc.py \ +$(SRC_PATH)/scripts/qapi-gen.py + +# Get the list of all supported sysemu targets +SYSEMU_TARGET_LIST := $(subst -softmmu.mak,,$(notdir \ + $(wildcard $(SRC_PATH)/default-configs/*-softmmu.mak))) + +check-unit-y += tests/check-qdict$(EXESUF) +check-unit-y += tests/check-block-qdict$(EXESUF) +check-unit-y += tests/test-char$(EXESUF) +check-unit-y += tests/check-qnum$(EXESUF) +check-unit-y += tests/check-qstring$(EXESUF) +check-unit-y += tests/check-qlist$(EXESUF) +check-unit-y += tests/check-qnull$(EXESUF) +check-unit-y += tests/check-qobject$(EXESUF) +check-unit-y += tests/check-qjson$(EXESUF) +check-unit-y += tests/check-qlit$(EXESUF) +check-unit-y += tests/test-qobject-output-visitor$(EXESUF) +check-unit-y += tests/test-clone-visitor$(EXESUF) +check-unit-y += tests/test-qobject-input-visitor$(EXESUF) +check-unit-y += tests/test-qmp-cmds$(EXESUF) +check-unit-y += tests/test-string-input-visitor$(EXESUF) +check-unit-y += tests/test-string-output-visitor$(EXESUF) +check-unit-y += tests/test-qmp-event$(EXESUF) +check-unit-y += tests/test-opts-visitor$(EXESUF) +check-unit-y += tests/test-coroutine$(EXESUF) +check-unit-y += tests/test-visitor-serialization$(EXESUF) +check-unit-y += tests/test-iov$(EXESUF) +check-unit-y += tests/test-aio$(EXESUF) +check-unit-y += tests/test-aio-multithread$(EXESUF) +check-unit-y += tests/test-throttle$(EXESUF) +check-unit-y += tests/test-thread-pool$(EXESUF) +check-unit-y += tests/test-hbitmap$(EXESUF) +check-unit-y += tests/test-bdrv-drain$(EXESUF) +check-unit-y += tests/test-blockjob$(EXESUF) +check-unit-y += tests/test-blockjob-txn$(EXESUF) +check-unit-y += tests/test-block-backend$(EXESUF) +check-unit-y += tests/test-image-locking$(EXESUF) +check-unit-y += tests/test-x86-cpuid$(EXESUF) +# all code tested by test-x86-cpuid is inside topology.h +ifeq ($(CONFIG_SOFTMMU),y) +check-unit-y += tests/test-xbzrle$(EXESUF) +check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF) +endif +check-unit-y += tests/test-cutils$(EXESUF) +check-unit-y += tests/test-shift128$(EXESUF) +check-unit-y += tests/test-mul64$(EXESUF) +check-unit-y += tests/test-int128$(EXESUF) +# all code tested by test-int128 is inside int128.h +check-unit-y += tests/rcutorture$(EXESUF) +check-unit-y += tests/test-rcu-list$(EXESUF) +check-unit-y += tests/test-rcu-simpleq$(EXESUF) +check-unit-y += tests/test-rcu-tailq$(EXESUF) +check-unit-y += tests/test-qdist$(EXESUF) +check-unit-y += tests/test-qht$(EXESUF) +# FIXME: {test-qht-par + gprof} often break on Travis CI +check-unit-$(call lnot,$(CONFIG_GPROF)) += tests/test-qht-par$(EXESUF) +check-unit-y += tests/test-bitops$(EXESUF) +check-unit-y += tests/test-bitcnt$(EXESUF) +check-unit-y += tests/test-qdev-global-props$(EXESUF) +check-unit-y += tests/check-qom-interface$(EXESUF) +check-unit-y += tests/check-qom-proplist$(EXESUF) +check-unit-y += tests/test-qemu-opts$(EXESUF) +check-unit-y += tests/test-keyval$(EXESUF) +check-unit-y += tests/test-write-threshold$(EXESUF) +check-unit-y += tests/test-crypto-hash$(EXESUF) +check-speed-y += tests/benchmark-crypto-hash$(EXESUF) +check-unit-y += tests/test-crypto-hmac$(EXESUF) +check-speed-y += tests/benchmark-crypto-hmac$(EXESUF) +check-unit-y += tests/test-crypto-cipher$(EXESUF) +check-speed-y += tests/benchmark-crypto-cipher$(EXESUF) +check-unit-y += tests/test-crypto-secret$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlscredsx509$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlssession$(EXESUF) +ifneq (,$(findstring qemu-ga,$(TOOLS))) +check-unit-$(CONFIG_LINUX) += tests/test-qga$(EXESUF) +endif +check-unit-y += tests/test-timed-average$(EXESUF) +check-unit-y += tests/test-util-sockets$(EXESUF) +check-unit-y += tests/test-io-task$(EXESUF) +check-unit-y += tests/test-io-channel-socket$(EXESUF) +check-unit-y += tests/test-io-channel-file$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-io-channel-tls$(EXESUF) +check-unit-y += tests/test-io-channel-command$(EXESUF) +check-unit-y += tests/test-io-channel-buffer$(EXESUF) +check-unit-y += tests/test-base64$(EXESUF) +check-unit-$(if $(CONFIG_NETTLE),y,$(CONFIG_GCRYPT)) += tests/test-crypto-pbkdf$(EXESUF) +check-unit-y += tests/test-crypto-ivgen$(EXESUF) +check-unit-y += tests/test-crypto-afsplit$(EXESUF) +check-unit-y += tests/test-crypto-xts$(EXESUF) +check-unit-y += tests/test-crypto-block$(EXESUF) +check-unit-y += tests/test-logging$(EXESUF) +check-unit-$(CONFIG_REPLICATION) += tests/test-replication$(EXESUF) +check-unit-y += tests/test-bufferiszero$(EXESUF) +check-unit-y += tests/test-uuid$(EXESUF) +check-unit-y += tests/ptimer-test$(EXESUF) +check-unit-y += tests/test-qapi-util$(EXESUF) + +check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh + +# All QTests for now are POSIX-only, but the dependencies are +# really in libqtest, not in the testcases themselves. + +check-qtest-generic-y += tests/qmp-test$(EXESUF) +check-qtest-generic-y += tests/qmp-cmd-test$(EXESUF) + +check-qtest-generic-y += tests/device-introspect-test$(EXESUF) +check-qtest-generic-y += tests/cdrom-test$(EXESUF) + +check-qtest-ipack-y += tests/ipoctal232-test$(EXESUF) + +check-qtest-virtioserial-y += tests/virtio-console-test$(EXESUF) + +check-qtest-virtio-y += tests/virtio-net-test$(EXESUF) +check-qtest-virtio-$(CONFIG_VIRTIO_BALLOON) += tests/virtio-balloon-test$(EXESUF) +check-qtest-virtio-y += tests/virtio-blk-test$(EXESUF) +check-qtest-virtio-$(CONFIG_VIRTIO_RNG) += tests/virtio-rng-test$(EXESUF) +check-qtest-virtio-$(CONFIG_VIRTIO_SCSI) += tests/virtio-scsi-test$(EXESUF) +ifeq ($(CONFIG_VIRTIO)$(CONFIG_VIRTFS)$(CONFIG_PCI),yyy) +check-qtest-virtio-$(CONFIG_VIRTIO_9P) += tests/virtio-9p-test$(EXESUF) +endif +check-qtest-virtio-y += tests/virtio-serial-test$(EXESUF) +check-qtest-virtio-y += $(check-qtest-virtioserial-y) + +check-qtest-pci-y += tests/e1000-test$(EXESUF) +check-qtest-pci-y += tests/e1000e-test$(EXESUF) +check-qtest-pci-$(CONFIG_RTL8139_PCI) += tests/rtl8139-test$(EXESUF) +check-qtest-pci-$(CONFIG_PCNET_PCI) += tests/pcnet-test$(EXESUF) +check-qtest-pci-$(CONFIG_EEPRO100_PCI) += tests/eepro100-test$(EXESUF) +check-qtest-pci-$(CONFIG_NE2000_PCI) += tests/ne2000-test$(EXESUF) +check-qtest-pci-$(CONFIG_NVME_PCI) += tests/nvme-test$(EXESUF) +check-qtest-pci-$(CONFIG_AC97) += tests/ac97-test$(EXESUF) +check-qtest-pci-$(CONFIG_ES1370) += tests/es1370-test$(EXESUF) +check-qtest-pci-y += $(check-qtest-virtio-y) +check-qtest-pci-$(CONFIG_IPACK) += tests/tpci200-test$(EXESUF) +check-qtest-pci-$(CONFIG_IPACK) += $(check-qtest-ipack-y) +check-qtest-pci-y += tests/display-vga-test$(EXESUF) +check-qtest-pci-$(CONFIG_HDA) += tests/intel-hda-test$(EXESUF) +check-qtest-pci-$(CONFIG_IVSHMEM_DEVICE) += tests/ivshmem-test$(EXESUF) +check-qtest-pci-y += tests/megasas-test$(EXESUF) + +check-qtest-i386-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-i386-y += tests/fdc-test$(EXESUF) +check-qtest-i386-y += tests/ide-test$(EXESUF) +check-qtest-i386-y += tests/ahci-test$(EXESUF) +check-qtest-i386-y += tests/hd-geo-test$(EXESUF) +check-qtest-i386-y += tests/boot-order-test$(EXESUF) +check-qtest-i386-y += tests/bios-tables-test$(EXESUF) +check-qtest-i386-$(CONFIG_SGA) += tests/boot-serial-test$(EXESUF) +check-qtest-i386-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF) +check-qtest-i386-y += tests/rtc-test$(EXESUF) +check-qtest-i386-y += tests/ipmi-kcs-test$(EXESUF) +check-qtest-i386-y += tests/ipmi-bt-test$(EXESUF) +check-qtest-i386-y += tests/i440fx-test$(EXESUF) +check-qtest-i386-y += tests/fw_cfg-test$(EXESUF) +check-qtest-i386-y += tests/drive_del-test$(EXESUF) +check-qtest-i386-$(CONFIG_WDT_IB700) += tests/wdt_ib700-test$(EXESUF) +check-qtest-i386-y += tests/tco-test$(EXESUF) +check-qtest-i386-y += $(check-qtest-pci-y) +check-qtest-i386-$(CONFIG_VMXNET3_PCI) += tests/vmxnet3-test$(EXESUF) +check-qtest-i386-$(CONFIG_PVPANIC) += tests/pvpanic-test$(EXESUF) +check-qtest-i386-$(CONFIG_I82801B11) += tests/i82801b11-test$(EXESUF) +check-qtest-i386-$(CONFIG_IOH3420) += tests/ioh3420-test$(EXESUF) +check-qtest-i386-$(CONFIG_USB_OHCI) += tests/usb-hcd-ohci-test$(EXESUF) +check-qtest-i386-$(CONFIG_USB_UHCI) += tests/usb-hcd-uhci-test$(EXESUF) +ifeq ($(CONFIG_USB_ECHI)$(CONFIG_USB_UHCI),yy) +check-qtest-i386-y += tests/usb-hcd-ehci-test$(EXESUF) +endif +check-qtest-i386-$(CONFIG_USB_XHCI_NEC) += tests/usb-hcd-xhci-test$(EXESUF) +check-qtest-i386-y += tests/cpu-plug-test$(EXESUF) +check-qtest-i386-y += tests/q35-test$(EXESUF) +check-qtest-i386-y += tests/vmgenid-test$(EXESUF) +check-qtest-i386-$(CONFIG_VHOST_USER_NET_TEST_i386) += tests/vhost-user-test$(EXESUF) +ifeq ($(CONFIG_VHOST_USER_NET_TEST_i386),) +check-qtest-x86_64-$(CONFIG_VHOST_USER_NET_TEST_x86_64) += tests/vhost-user-test$(EXESUF) +endif +check-qtest-i386-$(CONFIG_TPM_CRB) += tests/tpm-crb-swtpm-test$(EXESUF) +check-qtest-i386-$(CONFIG_TPM_CRB) += tests/tpm-crb-test$(EXESUF) +check-qtest-i386-$(CONFIG_TPM_TIS) += tests/tpm-tis-swtpm-test$(EXESUF) +check-qtest-i386-$(CONFIG_TPM_TIS) += tests/tpm-tis-test$(EXESUF) +check-qtest-i386-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF) +check-qtest-i386-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF) +check-qtest-i386-$(CONFIG_RTL8139_PCI) += tests/test-filter-redirector$(EXESUF) +check-qtest-i386-y += tests/migration-test$(EXESUF) +check-qtest-i386-y += tests/test-x86-cpuid-compat$(EXESUF) +check-qtest-i386-y += tests/numa-test$(EXESUF) +check-qtest-x86_64-y += $(check-qtest-i386-y) +check-qtest-x86_64-$(CONFIG_SDHCI) += tests/sdhci-test$(EXESUF) + +check-qtest-alpha-y += tests/boot-serial-test$(EXESUF) +check-qtest-alpha-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-hppa-y += tests/boot-serial-test$(EXESUF) +check-qtest-hppa-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-m68k-y = tests/boot-serial-test$(EXESUF) + +check-qtest-microblaze-y += tests/boot-serial-test$(EXESUF) + +check-qtest-mips-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-mips-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-mips64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-mips64-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-mips64el-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-mips64el-$(CONFIG_VGA) += tests/display-vga-test$(EXESUF) + +check-qtest-moxie-y += tests/boot-serial-test$(EXESUF) + +check-qtest-ppc-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-ppc-y += tests/boot-order-test$(EXESUF) +check-qtest-ppc-y += tests/prom-env-test$(EXESUF) +check-qtest-ppc-y += tests/drive_del-test$(EXESUF) +check-qtest-ppc-y += tests/boot-serial-test$(EXESUF) +check-qtest-ppc-y += tests/m48t59-test$(EXESUF) + +check-qtest-ppc64-y += $(check-qtest-ppc-y) +check-qtest-ppc64-y += tests/spapr-phb-test$(EXESUF) +check-qtest-ppc64-y += tests/pnv-xscom-test$(EXESUF) +check-qtest-ppc64-y += tests/migration-test$(EXESUF) +check-qtest-ppc64-y += tests/rtas-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_USB_OHCI) += tests/usb-hcd-ohci-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_USB_UHCI) += tests/usb-hcd-uhci-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_USB_XHCI_NEC) += tests/usb-hcd-xhci-test$(EXESUF) +check-qtest-ppc64-y += $(check-qtest-virtio-y) +check-qtest-ppc64-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF) +check-qtest-ppc64-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF) +check-qtest-ppc64-$(CONFIG_RTL8139_PCI) += tests/test-filter-redirector$(EXESUF) +check-qtest-ppc64-y += tests/display-vga-test$(EXESUF) +check-qtest-ppc64-y += tests/numa-test$(EXESUF) +check-qtest-ppc64-$(CONFIG_IVSHMEM_DEVICE) += tests/ivshmem-test$(EXESUF) +check-qtest-ppc64-y += tests/cpu-plug-test$(EXESUF) + +check-qtest-sh4-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) + +check-qtest-sh4eb-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) + +check-qtest-sparc-y += tests/prom-env-test$(EXESUF) +check-qtest-sparc-y += tests/m48t59-test$(EXESUF) +check-qtest-sparc-y += tests/boot-serial-test$(EXESUF) + +check-qtest-sparc64-$(CONFIG_ISA_TESTDEV) = tests/endianness-test$(EXESUF) +check-qtest-sparc64-y += tests/prom-env-test$(EXESUF) +check-qtest-sparc64-y += tests/boot-serial-test$(EXESUF) + +check-qtest-arm-y += tests/tmp105-test$(EXESUF) +check-qtest-arm-y += tests/pca9552-test$(EXESUF) +check-qtest-arm-y += tests/ds1338-test$(EXESUF) +check-qtest-arm-y += tests/microbit-test$(EXESUF) +check-qtest-arm-y += tests/m25p80-test$(EXESUF) +check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) +check-qtest-arm-y += tests/test-arm-mptimer$(EXESUF) +check-qtest-arm-y += tests/boot-serial-test$(EXESUF) +check-qtest-arm-$(CONFIG_SDHCI) += tests/sdhci-test$(EXESUF) +check-qtest-arm-y += tests/hexloader-test$(EXESUF) + +check-qtest-aarch64-y = tests/numa-test$(EXESUF) +check-qtest-aarch64-$(CONFIG_SDHCI) += tests/sdhci-test$(EXESUF) +check-qtest-aarch64-y += tests/boot-serial-test$(EXESUF) +check-qtest-aarch64-y += tests/migration-test$(EXESUF) + +check-qtest-microblazeel-y += $(check-qtest-microblaze-y) + +check-qtest-xtensaeb-y += $(check-qtest-xtensa-y) + +check-qtest-s390x-y = tests/boot-serial-test$(EXESUF) +check-qtest-s390x-$(CONFIG_SLIRP) += tests/pxe-test$(EXESUF) +check-qtest-s390x-$(CONFIG_SLIRP) += tests/test-netfilter$(EXESUF) +check-qtest-s390x-$(CONFIG_POSIX) += tests/test-filter-mirror$(EXESUF) +check-qtest-s390x-$(CONFIG_POSIX) += tests/test-filter-redirector$(EXESUF) +check-qtest-s390x-y += tests/drive_del-test$(EXESUF) +check-qtest-s390x-y += tests/virtio-ccw-test$(EXESUF) +check-qtest-s390x-y += tests/cpu-plug-test$(EXESUF) +check-qtest-s390x-y += tests/migration-test$(EXESUF) + +check-qtest-generic-y += tests/machine-none-test$(EXESUF) +check-qtest-generic-y += tests/qom-test$(EXESUF) +check-qtest-generic-y += tests/test-hmp$(EXESUF) + +qapi-schema += alternate-any.json +qapi-schema += alternate-array.json +qapi-schema += alternate-base.json +qapi-schema += alternate-clash.json +qapi-schema += alternate-conflict-dict.json +qapi-schema += alternate-conflict-enum-bool.json +qapi-schema += alternate-conflict-enum-int.json +qapi-schema += alternate-conflict-string.json +qapi-schema += alternate-conflict-bool-string.json +qapi-schema += alternate-conflict-num-string.json +qapi-schema += alternate-empty.json +qapi-schema += alternate-invalid-dict.json +qapi-schema += alternate-nested.json +qapi-schema += alternate-unknown.json +qapi-schema += args-alternate.json +qapi-schema += args-any.json +qapi-schema += args-array-empty.json +qapi-schema += args-array-unknown.json +qapi-schema += args-bad-boxed.json +qapi-schema += args-boxed-anon.json +qapi-schema += args-boxed-empty.json +qapi-schema += args-boxed-string.json +qapi-schema += args-int.json +qapi-schema += args-invalid.json +qapi-schema += args-member-array-bad.json +qapi-schema += args-member-case.json +qapi-schema += args-member-unknown.json +qapi-schema += args-name-clash.json +qapi-schema += args-union.json +qapi-schema += args-unknown.json +qapi-schema += bad-base.json +qapi-schema += bad-data.json +qapi-schema += bad-ident.json +qapi-schema += bad-if.json +qapi-schema += bad-if-empty.json +qapi-schema += bad-if-empty-list.json +qapi-schema += bad-if-list.json +qapi-schema += bad-type-bool.json +qapi-schema += bad-type-dict.json +qapi-schema += bad-type-int.json +qapi-schema += base-cycle-direct.json +qapi-schema += base-cycle-indirect.json +qapi-schema += command-int.json +qapi-schema += comments.json +qapi-schema += doc-bad-alternate-member.json +qapi-schema += doc-bad-command-arg.json +qapi-schema += doc-bad-section.json +qapi-schema += doc-bad-symbol.json +qapi-schema += doc-bad-union-member.json +qapi-schema += doc-before-include.json +qapi-schema += doc-before-pragma.json +qapi-schema += doc-duplicated-arg.json +qapi-schema += doc-duplicated-return.json +qapi-schema += doc-duplicated-since.json +qapi-schema += doc-empty-arg.json +qapi-schema += doc-empty-section.json +qapi-schema += doc-empty-symbol.json +qapi-schema += doc-good.json +qapi-schema += doc-interleaved-section.json +qapi-schema += doc-invalid-end.json +qapi-schema += doc-invalid-end2.json +qapi-schema += doc-invalid-return.json +qapi-schema += doc-invalid-section.json +qapi-schema += doc-invalid-start.json +qapi-schema += doc-missing-colon.json +qapi-schema += doc-missing-expr.json +qapi-schema += doc-missing-space.json +qapi-schema += doc-missing.json +qapi-schema += doc-no-symbol.json +qapi-schema += double-data.json +qapi-schema += double-type.json +qapi-schema += duplicate-key.json +qapi-schema += empty.json +qapi-schema += enum-bad-member.json +qapi-schema += enum-bad-name.json +qapi-schema += enum-bad-prefix.json +qapi-schema += enum-clash-member.json +qapi-schema += enum-dict-member-unknown.json +qapi-schema += enum-if-invalid.json +qapi-schema += enum-int-member.json +qapi-schema += enum-member-case.json +qapi-schema += enum-missing-data.json +qapi-schema += enum-wrong-data.json +qapi-schema += escape-outside-string.json +qapi-schema += escape-too-big.json +qapi-schema += escape-too-short.json +qapi-schema += event-boxed-empty.json +qapi-schema += event-case.json +qapi-schema += event-member-invalid-dict.json +qapi-schema += event-nest-struct.json +qapi-schema += flat-union-array-branch.json +qapi-schema += flat-union-bad-base.json +qapi-schema += flat-union-bad-discriminator.json +qapi-schema += flat-union-base-any.json +qapi-schema += flat-union-base-union.json +qapi-schema += flat-union-clash-member.json +qapi-schema += flat-union-empty.json +qapi-schema += flat-union-inline.json +qapi-schema += flat-union-inline-invalid-dict.json +qapi-schema += flat-union-int-branch.json +qapi-schema += flat-union-invalid-branch-key.json +qapi-schema += flat-union-invalid-discriminator.json +qapi-schema += flat-union-invalid-if-discriminator.json +qapi-schema += flat-union-no-base.json +qapi-schema += flat-union-optional-discriminator.json +qapi-schema += flat-union-string-discriminator.json +qapi-schema += funny-char.json +qapi-schema += ident-with-escape.json +qapi-schema += include-before-err.json +qapi-schema += include-cycle.json +qapi-schema += include-extra-junk.json +qapi-schema += include-format-err.json +qapi-schema += include-nested-err.json +qapi-schema += include-no-file.json +qapi-schema += include-non-file.json +qapi-schema += include-relpath.json +qapi-schema += include-repetition.json +qapi-schema += include-self-cycle.json +qapi-schema += include-simple.json +qapi-schema += indented-expr.json +qapi-schema += leading-comma-list.json +qapi-schema += leading-comma-object.json +qapi-schema += missing-colon.json +qapi-schema += missing-comma-list.json +qapi-schema += missing-comma-object.json +qapi-schema += missing-type.json +qapi-schema += nested-struct-data.json +qapi-schema += nested-struct-data-invalid-dict.json +qapi-schema += non-objects.json +qapi-schema += oob-test.json +qapi-schema += allow-preconfig-test.json +qapi-schema += pragma-doc-required-crap.json +qapi-schema += pragma-extra-junk.json +qapi-schema += pragma-name-case-whitelist-crap.json +qapi-schema += pragma-non-dict.json +qapi-schema += pragma-returns-whitelist-crap.json +qapi-schema += qapi-schema-test.json +qapi-schema += quoted-structural-chars.json +qapi-schema += redefined-builtin.json +qapi-schema += redefined-command.json +qapi-schema += redefined-event.json +qapi-schema += redefined-type.json +qapi-schema += reserved-command-q.json +qapi-schema += reserved-enum-q.json +qapi-schema += reserved-member-has.json +qapi-schema += reserved-member-q.json +qapi-schema += reserved-member-u.json +qapi-schema += reserved-member-underscore.json +qapi-schema += reserved-type-kind.json +qapi-schema += reserved-type-list.json +qapi-schema += returns-alternate.json +qapi-schema += returns-array-bad.json +qapi-schema += returns-dict.json +qapi-schema += returns-unknown.json +qapi-schema += returns-whitelist.json +qapi-schema += struct-base-clash-deep.json +qapi-schema += struct-base-clash.json +qapi-schema += struct-data-invalid.json +qapi-schema += struct-member-invalid-dict.json +qapi-schema += struct-member-invalid.json +qapi-schema += trailing-comma-list.json +qapi-schema += trailing-comma-object.json +qapi-schema += type-bypass-bad-gen.json +qapi-schema += unclosed-list.json +qapi-schema += unclosed-object.json +qapi-schema += unclosed-string.json +qapi-schema += unicode-str.json +qapi-schema += union-base-empty.json +qapi-schema += union-base-no-discriminator.json +qapi-schema += union-branch-case.json +qapi-schema += union-branch-invalid-dict.json +qapi-schema += union-clash-branches.json +qapi-schema += union-empty.json +qapi-schema += union-invalid-base.json +qapi-schema += union-optional-branch.json +qapi-schema += union-unknown.json +qapi-schema += unknown-escape.json +qapi-schema += unknown-expr-key.json + + +check-qapi-schema-y := $(addprefix tests/qapi-schema/, $(qapi-schema)) + +GENERATED_FILES += tests/test-qapi-types.h tests/test-qapi-visit.h \ + tests/test-qapi-commands.h tests/test-qapi-events.h \ + tests/test-qapi-introspect.h + +test-obj-y = tests/check-qnum.o tests/check-qstring.o tests/check-qdict.o \ + tests/check-qlist.o tests/check-qnull.o tests/check-qobject.o \ + tests/check-qjson.o tests/check-qlit.o \ + tests/check-block-qtest.o \ + tests/test-coroutine.o tests/test-string-output-visitor.o \ + tests/test-string-input-visitor.o tests/test-qobject-output-visitor.o \ + tests/test-clone-visitor.o \ + tests/test-qobject-input-visitor.o \ + tests/test-qmp-cmds.o tests/test-visitor-serialization.o \ + tests/test-x86-cpuid.o tests/test-mul64.o tests/test-int128.o \ + tests/test-opts-visitor.o tests/test-qmp-event.o \ + tests/rcutorture.o tests/test-rcu-list.o \ + tests/test-rcu-simpleq.o \ + tests/test-rcu-tailq.o \ + tests/test-qdist.o tests/test-shift128.o \ + tests/test-qht.o tests/qht-bench.o tests/test-qht-par.o \ + tests/atomic_add-bench.o tests/atomic64-bench.o + +$(test-obj-y): QEMU_INCLUDES += -Itests +QEMU_CFLAGS += -I$(SRC_PATH)/tests + + +# Deps that are common to various different sets of tests below +test-util-obj-y = libqemuutil.a +test-qom-obj-y = $(qom-obj-y) $(test-util-obj-y) +test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o \ + tests/test-qapi-events.o tests/test-qapi-introspect.o \ + $(test-qom-obj-y) +benchmark-crypto-obj-y = $(crypto-obj-y) $(test-qom-obj-y) +test-crypto-obj-y = $(crypto-obj-y) $(test-qom-obj-y) +test-io-obj-y = $(io-obj-y) $(test-crypto-obj-y) +test-block-obj-y = $(block-obj-y) $(test-io-obj-y) tests/iothread.o + +tests/check-qnum$(EXESUF): tests/check-qnum.o $(test-util-obj-y) +tests/check-qstring$(EXESUF): tests/check-qstring.o $(test-util-obj-y) +tests/check-qdict$(EXESUF): tests/check-qdict.o $(test-util-obj-y) +tests/check-block-qdict$(EXESUF): tests/check-block-qdict.o $(test-util-obj-y) +tests/check-qlist$(EXESUF): tests/check-qlist.o $(test-util-obj-y) +tests/check-qnull$(EXESUF): tests/check-qnull.o $(test-util-obj-y) +tests/check-qobject$(EXESUF): tests/check-qobject.o $(test-util-obj-y) +tests/check-qjson$(EXESUF): tests/check-qjson.o $(test-util-obj-y) +tests/check-qlit$(EXESUF): tests/check-qlit.o $(test-util-obj-y) +tests/check-qom-interface$(EXESUF): tests/check-qom-interface.o $(test-qom-obj-y) +tests/check-qom-proplist$(EXESUF): tests/check-qom-proplist.o $(test-qom-obj-y) + +tests/test-char$(EXESUF): tests/test-char.o $(test-util-obj-y) $(qtest-obj-y) $(test-io-obj-y) $(chardev-obj-y) +tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(test-block-obj-y) +tests/test-aio$(EXESUF): tests/test-aio.o $(test-block-obj-y) +tests/test-aio-multithread$(EXESUF): tests/test-aio-multithread.o $(test-block-obj-y) +tests/test-throttle$(EXESUF): tests/test-throttle.o $(test-block-obj-y) +tests/test-bdrv-drain$(EXESUF): tests/test-bdrv-drain.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-blockjob$(EXESUF): tests/test-blockjob.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-blockjob-txn$(EXESUF): tests/test-blockjob-txn.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-block-backend$(EXESUF): tests/test-block-backend.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-image-locking$(EXESUF): tests/test-image-locking.o $(test-block-obj-y) $(test-util-obj-y) +tests/test-thread-pool$(EXESUF): tests/test-thread-pool.o $(test-block-obj-y) +tests/test-iov$(EXESUF): tests/test-iov.o $(test-util-obj-y) +tests/test-hbitmap$(EXESUF): tests/test-hbitmap.o $(test-util-obj-y) $(test-crypto-obj-y) +tests/test-x86-cpuid$(EXESUF): tests/test-x86-cpuid.o +tests/test-xbzrle$(EXESUF): tests/test-xbzrle.o migration/xbzrle.o migration/page_cache.o $(test-util-obj-y) +tests/test-cutils$(EXESUF): tests/test-cutils.o util/cutils.o $(test-util-obj-y) +tests/test-int128$(EXESUF): tests/test-int128.o +tests/rcutorture$(EXESUF): tests/rcutorture.o $(test-util-obj-y) +tests/test-rcu-list$(EXESUF): tests/test-rcu-list.o $(test-util-obj-y) +tests/test-rcu-simpleq$(EXESUF): tests/test-rcu-simpleq.o $(test-util-obj-y) +tests/test-rcu-tailq$(EXESUF): tests/test-rcu-tailq.o $(test-util-obj-y) +tests/test-qdist$(EXESUF): tests/test-qdist.o $(test-util-obj-y) +tests/test-qht$(EXESUF): tests/test-qht.o $(test-util-obj-y) +tests/test-qht-par$(EXESUF): tests/test-qht-par.o tests/qht-bench$(EXESUF) $(test-util-obj-y) +tests/qht-bench$(EXESUF): tests/qht-bench.o $(test-util-obj-y) +tests/test-bufferiszero$(EXESUF): tests/test-bufferiszero.o $(test-util-obj-y) +tests/atomic_add-bench$(EXESUF): tests/atomic_add-bench.o $(test-util-obj-y) +tests/atomic64-bench$(EXESUF): tests/atomic64-bench.o $(test-util-obj-y) + +tests/fp/%: + $(MAKE) -C $(dir $@) $(notdir $@) + +tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ + hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ + hw/core/bus.o \ + hw/core/irq.o \ + hw/core/fw-path-provider.o \ + hw/core/reset.o \ + $(test-qapi-obj-y) +tests/test-vmstate$(EXESUF): tests/test-vmstate.o \ + migration/vmstate.o migration/vmstate-types.o migration/qemu-file.o \ + migration/qemu-file-channel.o migration/qjson.o \ + $(test-io-obj-y) +tests/test-timed-average$(EXESUF): tests/test-timed-average.o $(test-util-obj-y) +tests/test-base64$(EXESUF): tests/test-base64.o $(test-util-obj-y) +tests/ptimer-test$(EXESUF): tests/ptimer-test.o tests/ptimer-test-stubs.o hw/core/ptimer.o + +tests/test-logging$(EXESUF): tests/test-logging.o $(test-util-obj-y) + +tests/test-replication$(EXESUF): tests/test-replication.o $(test-util-obj-y) \ + $(test-block-obj-y) + +tests/test-qapi-types.c tests/test-qapi-types.h \ +tests/test-qapi-visit.c tests/test-qapi-visit.h \ +tests/test-qapi-commands.h tests/test-qapi-commands.c \ +tests/test-qapi-events.c tests/test-qapi-events.h \ +tests/test-qapi-introspect.c tests/test-qapi-introspect.h: \ +tests/test-qapi-gen-timestamp ; +tests/test-qapi-gen-timestamp: $(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \ + -o tests -p "test-" $<, \ + "GEN","$(@:%-timestamp=%)") + @>$@ + +tests/qapi-schema/doc-good.test.texi: $(SRC_PATH)/tests/qapi-schema/doc-good.json $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-gen.py \ + -o tests/qapi-schema -p "doc-good-" $<, \ + "GEN","$@") + @mv tests/qapi-schema/doc-good-qapi-doc.texi $@ + @rm -f tests/qapi-schema/doc-good-qapi-*.[ch] tests/qapi-schema/doc-good-qmp-*.[ch] + +tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) +tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y) +tests/test-qmp-event$(EXESUF): tests/test-qmp-event.o $(test-qapi-obj-y) +tests/test-qobject-output-visitor$(EXESUF): tests/test-qobject-output-visitor.o $(test-qapi-obj-y) +tests/test-clone-visitor$(EXESUF): tests/test-clone-visitor.o $(test-qapi-obj-y) +tests/test-qobject-input-visitor$(EXESUF): tests/test-qobject-input-visitor.o $(test-qapi-obj-y) +tests/test-qmp-cmds$(EXESUF): tests/test-qmp-cmds.o tests/test-qapi-commands.o $(test-qapi-obj-y) +tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(test-qapi-obj-y) +tests/test-opts-visitor$(EXESUF): tests/test-opts-visitor.o $(test-qapi-obj-y) + +tests/test-shift128$(EXESUF): tests/test-shift128.o $(test-util-obj-y) +tests/test-mul64$(EXESUF): tests/test-mul64.o $(test-util-obj-y) +tests/test-bitops$(EXESUF): tests/test-bitops.o $(test-util-obj-y) +tests/test-bitcnt$(EXESUF): tests/test-bitcnt.o $(test-util-obj-y) +tests/test-crypto-hash$(EXESUF): tests/test-crypto-hash.o $(test-crypto-obj-y) +tests/benchmark-crypto-hash$(EXESUF): tests/benchmark-crypto-hash.o $(test-crypto-obj-y) +tests/test-crypto-hmac$(EXESUF): tests/test-crypto-hmac.o $(test-crypto-obj-y) +tests/benchmark-crypto-hmac$(EXESUF): tests/benchmark-crypto-hmac.o $(test-crypto-obj-y) +tests/test-crypto-cipher$(EXESUF): tests/test-crypto-cipher.o $(test-crypto-obj-y) +tests/benchmark-crypto-cipher$(EXESUF): tests/benchmark-crypto-cipher.o $(test-crypto-obj-y) +tests/test-crypto-secret$(EXESUF): tests/test-crypto-secret.o $(test-crypto-obj-y) +tests/test-crypto-xts$(EXESUF): tests/test-crypto-xts.o $(test-crypto-obj-y) + +tests/crypto-tls-x509-helpers.o-cflags := $(TASN1_CFLAGS) +tests/crypto-tls-x509-helpers.o-libs := $(TASN1_LIBS) +tests/pkix_asn1_tab.o-cflags := $(TASN1_CFLAGS) + +tests/test-crypto-tlscredsx509.o-cflags := $(TASN1_CFLAGS) +tests/test-crypto-tlscredsx509$(EXESUF): tests/test-crypto-tlscredsx509.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o $(test-crypto-obj-y) + +tests/test-crypto-tlssession.o-cflags := $(TASN1_CFLAGS) +tests/test-crypto-tlssession$(EXESUF): tests/test-crypto-tlssession.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o \ + tests/crypto-tls-psk-helpers.o \ + $(test-crypto-obj-y) +tests/test-util-sockets$(EXESUF): tests/test-util-sockets.o \ + tests/socket-helpers.o $(test-util-obj-y) +tests/test-io-task$(EXESUF): tests/test-io-task.o $(test-io-obj-y) +tests/test-io-channel-socket$(EXESUF): tests/test-io-channel-socket.o \ + tests/io-channel-helpers.o tests/socket-helpers.o $(test-io-obj-y) +tests/tpm-crb-swtpm-test$(EXESUF): tests/tpm-crb-swtpm-test.o tests/tpm-emu.o \ + tests/tpm-util.o tests/tpm-tests.o $(test-io-obj-y) +tests/tpm-crb-test$(EXESUF): tests/tpm-crb-test.o tests/tpm-emu.o $(test-io-obj-y) +tests/tpm-tis-swtpm-test$(EXESUF): tests/tpm-tis-swtpm-test.o tests/tpm-emu.o \ + tests/tpm-util.o tests/tpm-tests.o $(test-io-obj-y) +tests/tpm-tis-test$(EXESUF): tests/tpm-tis-test.o tests/tpm-emu.o $(test-io-obj-y) +tests/test-io-channel-file$(EXESUF): tests/test-io-channel-file.o \ + tests/io-channel-helpers.o $(test-io-obj-y) +tests/test-io-channel-tls$(EXESUF): tests/test-io-channel-tls.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o \ + tests/io-channel-helpers.o $(test-io-obj-y) +tests/test-io-channel-command$(EXESUF): tests/test-io-channel-command.o \ + tests/io-channel-helpers.o $(test-io-obj-y) +tests/test-io-channel-buffer$(EXESUF): tests/test-io-channel-buffer.o \ + tests/io-channel-helpers.o $(test-io-obj-y) +tests/test-crypto-pbkdf$(EXESUF): tests/test-crypto-pbkdf.o $(test-crypto-obj-y) +tests/test-crypto-ivgen$(EXESUF): tests/test-crypto-ivgen.o $(test-crypto-obj-y) +tests/test-crypto-afsplit$(EXESUF): tests/test-crypto-afsplit.o $(test-crypto-obj-y) +tests/test-crypto-block$(EXESUF): tests/test-crypto-block.o $(test-crypto-obj-y) + +libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o tests/libqos/malloc.o +libqos-obj-y += tests/libqos/i2c.o tests/libqos/libqos.o +libqos-spapr-obj-y = $(libqos-obj-y) tests/libqos/malloc-spapr.o +libqos-spapr-obj-y += tests/libqos/libqos-spapr.o +libqos-spapr-obj-y += tests/libqos/rtas.o +libqos-spapr-obj-y += tests/libqos/pci-spapr.o +libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o +libqos-pc-obj-y += tests/libqos/malloc-pc.o tests/libqos/libqos-pc.o +libqos-pc-obj-y += tests/libqos/ahci.o +libqos-omap-obj-y = $(libqos-obj-y) tests/libqos/i2c-omap.o +libqos-imx-obj-y = $(libqos-obj-y) tests/libqos/i2c-imx.o +libqos-usb-obj-y = $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/libqos/usb.o +libqos-virtio-obj-y = $(libqos-spapr-obj-y) $(libqos-pc-obj-y) tests/libqos/virtio.o tests/libqos/virtio-pci.o tests/libqos/virtio-mmio.o tests/libqos/malloc-generic.o + +tests/qmp-test$(EXESUF): tests/qmp-test.o +tests/qmp-cmd-test$(EXESUF): tests/qmp-cmd-test.o +tests/device-introspect-test$(EXESUF): tests/device-introspect-test.o +tests/rtc-test$(EXESUF): tests/rtc-test.o +tests/m48t59-test$(EXESUF): tests/m48t59-test.o +tests/hexloader-test$(EXESUF): tests/hexloader-test.o +tests/endianness-test$(EXESUF): tests/endianness-test.o +tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y) +tests/prom-env-test$(EXESUF): tests/prom-env-test.o $(libqos-obj-y) +tests/rtas-test$(EXESUF): tests/rtas-test.o $(libqos-spapr-obj-y) +tests/fdc-test$(EXESUF): tests/fdc-test.o +tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y) +tests/ahci-test$(EXESUF): tests/ahci-test.o $(libqos-pc-obj-y) +tests/ipmi-kcs-test$(EXESUF): tests/ipmi-kcs-test.o +tests/ipmi-bt-test$(EXESUF): tests/ipmi-bt-test.o +tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o +tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y) +tests/boot-serial-test$(EXESUF): tests/boot-serial-test.o $(libqos-obj-y) +tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o \ + tests/boot-sector.o tests/acpi-utils.o $(libqos-obj-y) +tests/pxe-test$(EXESUF): tests/pxe-test.o tests/boot-sector.o $(libqos-obj-y) +tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) +tests/pca9552-test$(EXESUF): tests/pca9552-test.o $(libqos-omap-obj-y) +tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/microbit-test$(EXESUF): tests/microbit-test.o +tests/m25p80-test$(EXESUF): tests/m25p80-test.o +tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) +tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) +tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y) +tests/e1000-test$(EXESUF): tests/e1000-test.o +tests/e1000e-test$(EXESUF): tests/e1000e-test.o $(libqos-pc-obj-y) +tests/rtl8139-test$(EXESUF): tests/rtl8139-test.o $(libqos-pc-obj-y) +tests/pcnet-test$(EXESUF): tests/pcnet-test.o +tests/pnv-xscom-test$(EXESUF): tests/pnv-xscom-test.o +tests/eepro100-test$(EXESUF): tests/eepro100-test.o +tests/vmxnet3-test$(EXESUF): tests/vmxnet3-test.o +tests/ne2000-test$(EXESUF): tests/ne2000-test.o +tests/wdt_ib700-test$(EXESUF): tests/wdt_ib700-test.o +tests/tco-test$(EXESUF): tests/tco-test.o $(libqos-pc-obj-y) +tests/virtio-balloon-test$(EXESUF): tests/virtio-balloon-test.o $(libqos-virtio-obj-y) +tests/virtio-blk-test$(EXESUF): tests/virtio-blk-test.o $(libqos-virtio-obj-y) +tests/virtio-ccw-test$(EXESUF): tests/virtio-ccw-test.o +tests/virtio-net-test$(EXESUF): tests/virtio-net-test.o $(libqos-pc-obj-y) $(libqos-virtio-obj-y) +tests/virtio-rng-test$(EXESUF): tests/virtio-rng-test.o $(libqos-pc-obj-y) +tests/virtio-scsi-test$(EXESUF): tests/virtio-scsi-test.o $(libqos-virtio-obj-y) +tests/virtio-9p-test$(EXESUF): tests/virtio-9p-test.o $(libqos-virtio-obj-y) +tests/virtio-serial-test$(EXESUF): tests/virtio-serial-test.o $(libqos-virtio-obj-y) +tests/virtio-console-test$(EXESUF): tests/virtio-console-test.o $(libqos-virtio-obj-y) +tests/tpci200-test$(EXESUF): tests/tpci200-test.o +tests/display-vga-test$(EXESUF): tests/display-vga-test.o +tests/ipoctal232-test$(EXESUF): tests/ipoctal232-test.o +tests/qom-test$(EXESUF): tests/qom-test.o +tests/test-hmp$(EXESUF): tests/test-hmp.o +tests/machine-none-test$(EXESUF): tests/machine-none-test.o +tests/drive_del-test$(EXESUF): tests/drive_del-test.o $(libqos-virtio-obj-y) +tests/qdev-monitor-test$(EXESUF): tests/qdev-monitor-test.o $(libqos-pc-obj-y) +tests/nvme-test$(EXESUF): tests/nvme-test.o $(libqos-pc-obj-y) +tests/pvpanic-test$(EXESUF): tests/pvpanic-test.o +tests/i82801b11-test$(EXESUF): tests/i82801b11-test.o +tests/ac97-test$(EXESUF): tests/ac97-test.o +tests/es1370-test$(EXESUF): tests/es1370-test.o +tests/intel-hda-test$(EXESUF): tests/intel-hda-test.o +tests/ioh3420-test$(EXESUF): tests/ioh3420-test.o +tests/usb-hcd-ohci-test$(EXESUF): tests/usb-hcd-ohci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-uhci-test$(EXESUF): tests/usb-hcd-uhci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-ehci-test$(EXESUF): tests/usb-hcd-ehci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-xhci-test$(EXESUF): tests/usb-hcd-xhci-test.o $(libqos-usb-obj-y) +tests/cpu-plug-test$(EXESUF): tests/cpu-plug-test.o +tests/migration-test$(EXESUF): tests/migration-test.o +tests/vhost-user-test$(EXESUF): tests/vhost-user-test.o $(test-util-obj-y) \ + $(qtest-obj-y) $(test-io-obj-y) $(libqos-virtio-obj-y) $(libqos-pc-obj-y) \ + $(chardev-obj-y) +tests/qemu-iotests/socket_scm_helper$(EXESUF): tests/qemu-iotests/socket_scm_helper.o +tests/test-qemu-opts$(EXESUF): tests/test-qemu-opts.o $(test-util-obj-y) +tests/test-keyval$(EXESUF): tests/test-keyval.o $(test-util-obj-y) $(test-qapi-obj-y) +tests/test-write-threshold$(EXESUF): tests/test-write-threshold.o $(test-block-obj-y) +tests/test-netfilter$(EXESUF): tests/test-netfilter.o $(qtest-obj-y) +tests/test-filter-mirror$(EXESUF): tests/test-filter-mirror.o $(qtest-obj-y) +tests/test-filter-redirector$(EXESUF): tests/test-filter-redirector.o $(qtest-obj-y) +tests/test-x86-cpuid-compat$(EXESUF): tests/test-x86-cpuid-compat.o $(qtest-obj-y) +tests/ivshmem-test$(EXESUF): tests/ivshmem-test.o contrib/ivshmem-server/ivshmem-server.o $(libqos-pc-obj-y) $(libqos-spapr-obj-y) +tests/megasas-test$(EXESUF): tests/megasas-test.o $(libqos-spapr-obj-y) $(libqos-pc-obj-y) +tests/vhost-user-bridge$(EXESUF): tests/vhost-user-bridge.o $(test-util-obj-y) libvhost-user.a +tests/test-uuid$(EXESUF): tests/test-uuid.o $(test-util-obj-y) +tests/test-arm-mptimer$(EXESUF): tests/test-arm-mptimer.o +tests/test-qapi-util$(EXESUF): tests/test-qapi-util.o $(test-util-obj-y) +tests/numa-test$(EXESUF): tests/numa-test.o +tests/vmgenid-test$(EXESUF): tests/vmgenid-test.o tests/boot-sector.o tests/acpi-utils.o +tests/sdhci-test$(EXESUF): tests/sdhci-test.o $(libqos-pc-obj-y) +tests/cdrom-test$(EXESUF): tests/cdrom-test.o tests/boot-sector.o $(libqos-obj-y) + +tests/migration/stress$(EXESUF): tests/migration/stress.o + $(call quiet-command, $(LINKPROG) -static -O3 $(PTHREAD_LIB) -o $@ $< ,"LINK","$(TARGET_DIR)$@") + +INITRD_WORK_DIR=tests/migration/initrd + +tests/migration/initrd-stress.img: tests/migration/stress$(EXESUF) + mkdir -p $(INITRD_WORK_DIR) + cp $< $(INITRD_WORK_DIR)/init + (cd $(INITRD_WORK_DIR) && (find | cpio --quiet -o -H newc | gzip -9)) > $@ + rm $(INITRD_WORK_DIR)/init + rmdir $(INITRD_WORK_DIR) + +ifeq ($(CONFIG_POSIX),y) +LIBS += -lutil +endif + +# QTest rules + +TARGETS=$(patsubst %-softmmu,%, $(filter %-softmmu,$(TARGET_DIRS))) +ifeq ($(CONFIG_POSIX),y) +QTEST_TARGETS = $(TARGETS) +check-qtest-y=$(foreach TARGET,$(TARGETS), $(check-qtest-$(TARGET)-y)) +check-qtest-y += $(check-qtest-generic-y) +else +QTEST_TARGETS = +endif + +qtest-obj-y = tests/libqtest.o $(test-util-obj-y) +$(check-qtest-y): $(qtest-obj-y) + +tests/test-qga$(EXESUF): qemu-ga$(EXESUF) +tests/test-qga$(EXESUF): tests/test-qga.o $(qtest-obj-y) + +SPEED = quick + +# gtester tests, possibly with verbose output +# do_test_tap runs all tests, even if some of them fail, while do_test_human +# stops at the first failure unless -k is given on the command line + +define do_test_human_k + $(quiet-@)rc=0; $(foreach COMMAND, $1, \ + $(call quiet-command-run, \ + export MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} $2; \ + $(COMMAND) -m=$(SPEED) -k --tap < /dev/null \ + | ./scripts/tap-driver.pl --test-name="$(notdir $(COMMAND))" $(if $(V),, --show-failures-only) \ + || rc=$$?;, "TEST", "$@: $(COMMAND)")) exit $$rc +endef +define do_test_human_no_k + $(foreach COMMAND, $1, \ + $(call quiet-command, \ + MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} $2 \ + $(COMMAND) -m=$(SPEED) -k --tap < /dev/null \ + | ./scripts/tap-driver.pl --test-name="$(notdir $(COMMAND))" $(if $(V),, --show-failures-only), \ + "TEST", "$@: $(COMMAND)") +) +endef +do_test_human = \ + $(if $(findstring k, $(MAKEFLAGS)), $(do_test_human_k), $(do_test_human_no_k)) + +define do_test_tap + $(call quiet-command, \ + { export MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$(( $${RANDOM:-0} % 255 + 1))} $2; \ + $(foreach COMMAND, $1, \ + $(COMMAND) -m=$(SPEED) -k --tap < /dev/null \ + | sed "s/^[a-z][a-z]* [0-9]* /&$(notdir $(COMMAND)) /" || true; ) } \ + | ./scripts/tap-merge.pl | tee "$@" \ + | ./scripts/tap-driver.pl $(if $(V),, --show-failures-only), \ + "TAP","$@") +endef + +.PHONY: $(patsubst %, check-qtest-%, $(QTEST_TARGETS)) +$(patsubst %, check-qtest-%, $(QTEST_TARGETS)): check-qtest-%: subdir-%-softmmu $(check-qtest-y) + $(call do_test_human,$(check-qtest-$*-y) $(check-qtest-generic-y), \ + QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ + QTEST_QEMU_IMG=qemu-img$(EXESUF)) + +check-unit: $(check-unit-y) + $(call do_test_human, $^) + +check-speed: $(check-speed-y) + $(call do_test_human, $^) + +# gtester tests with TAP output + +$(patsubst %, check-report-qtest-%.tap, $(QTEST_TARGETS)): check-report-qtest-%.tap: $(check-qtest-y) + $(call do_test_tap, $(check-qtest-$*-y) $(check-qtest-generic-y), \ + QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ + QTEST_QEMU_IMG=qemu-img$(EXESUF)) + +check-report-unit.tap: $(check-unit-y) + $(call do_test_tap,$^) + +# Reports and overall runs + +check-report.tap: $(patsubst %,check-report-qtest-%.tap, $(QTEST_TARGETS)) check-report-unit.tap + $(call quiet-command,./scripts/tap-merge.py $^ > $@,"GEN","$@") + +# Per guest TCG tests + +LINUX_USER_TARGETS=$(filter %-linux-user,$(TARGET_DIRS)) +BUILD_TCG_TARGET_RULES=$(patsubst %,build-tcg-tests-%, $(LINUX_USER_TARGETS)) +CLEAN_TCG_TARGET_RULES=$(patsubst %,clean-tcg-tests-%, $(LINUX_USER_TARGETS)) +RUN_TCG_TARGET_RULES=$(patsubst %,run-tcg-tests-%, $(LINUX_USER_TARGETS)) + +ifeq ($(HAVE_USER_DOCKER),y) +# Probe for the Docker Builds needed for each build +$(foreach PROBE_TARGET,$(TARGET_DIRS), \ + $(eval -include $(SRC_PATH)/tests/tcg/Makefile.probe) \ + $(if $(DOCKER_PREREQ), \ + $(eval build-tcg-tests-$(PROBE_TARGET): $(DOCKER_PREREQ)))) +endif + +build-tcg-tests-%: + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \ + SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" guest-tests, \ + "BUILD", "TCG tests for $*") + +run-tcg-tests-%: % build-tcg-tests-% + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \ + SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" run-guest-tests, \ + "RUN", "TCG tests for $*") + +clean-tcg-tests-%: + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" TARGET_DIR="$*/" clean-guest-tests,) + +.PHONY: build-tcg +build-tcg: $(BUILD_TCG_TARGET_RULES) + +.PHONY: check-tcg +check-tcg: $(RUN_TCG_TARGET_RULES) + +.PHONY: clean-tcg +clean-tcg: $(CLEAN_TCG_TARGET_RULES) + +# Other tests + +QEMU_IOTESTS_HELPERS-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_LINUX)) = tests/qemu-iotests/socket_scm_helper$(EXESUF) + +.PHONY: check-tests/qemu-iotests-quick.sh +check-tests/qemu-iotests-quick.sh: tests/qemu-iotests-quick.sh qemu-img$(EXESUF) qemu-io$(EXESUF) $(QEMU_IOTESTS_HELPERS-y) + $< + +.PHONY: $(patsubst %, check-%, $(check-qapi-schema-y)) +$(patsubst %, check-%, $(check-qapi-schema-y)): check-%.json: $(SRC_PATH)/%.json + $(call quiet-command, PYTHONPATH=$(SRC_PATH)/scripts \ + $(PYTHON) $(SRC_PATH)/tests/qapi-schema/test-qapi.py \ + $^ >$*.test.out 2>$*.test.err; \ + echo $$? >$*.test.exit, \ + "TEST","$*.out") + @# Sanitize error messages (make them independent of build directory) + @perl -p -e 's|\Q$(SRC_PATH)\E/||g' $*.test.err | diff -u $(SRC_PATH)/$*.err - + @diff -u $(SRC_PATH)/$*.out $*.test.out + @diff -u $(SRC_PATH)/$*.exit $*.test.exit + +.PHONY: check-tests/qapi-schema/doc-good.texi +check-tests/qapi-schema/doc-good.texi: tests/qapi-schema/doc-good.test.texi + @diff -u $(SRC_PATH)/tests/qapi-schema/doc-good.texi $< + +.PHONY: check-decodetree +check-decodetree: + $(call quiet-command, \ + cd $(SRC_PATH)/tests/decode && \ + ./check.sh "$(PYTHON)" "$(SRC_PATH)/scripts/decodetree.py", \ + TEST, decodetree.py) + +# Python venv for running tests + +.PHONY: check-venv check-acceptance + +TESTS_VENV_DIR=$(BUILD_DIR)/tests/venv +TESTS_VENV_REQ=$(SRC_PATH)/tests/requirements.txt +TESTS_RESULTS_DIR=$(BUILD_DIR)/tests/results +# Controls the output generated by Avocado when running tests. +# Any number of command separated loggers are accepted. For more +# information please refer to "avocado --help". +AVOCADO_SHOW=none + +PYTHON3 = $(shell $(PYTHON) -c 'import sys; print(1 if sys.version_info >= (3, 0) else 0)') +ifeq ($(PYTHON3), 1) +$(TESTS_VENV_DIR): $(TESTS_VENV_REQ) + $(call quiet-command, \ + $(PYTHON) -m venv --system-site-packages $@, \ + VENV, $@) + $(call quiet-command, \ + $(TESTS_VENV_DIR)/bin/python -m pip -q install -r $(TESTS_VENV_REQ), \ + PIP, $(TESTS_VENV_REQ)) + $(call quiet-command, touch $@) +else +$(TESTS_VENV_DIR): + $(error "venv directory for tests requires Python 3") +endif + +$(TESTS_RESULTS_DIR): + $(call quiet-command, mkdir -p $@, \ + MKDIR, $@) + +check-venv: $(TESTS_VENV_DIR) + +check-acceptance: check-venv $(TESTS_RESULTS_DIR) + $(call quiet-command, \ + $(TESTS_VENV_DIR)/bin/python -m avocado \ + --show=$(AVOCADO_SHOW) run --job-results-dir=$(TESTS_RESULTS_DIR) \ + --failfast=on $(SRC_PATH)/tests/acceptance, \ + "AVOCADO", "tests/acceptance") + +# Consolidated targets + +.PHONY: check-qapi-schema check-qtest check-unit check check-clean +check-qapi-schema: $(patsubst %,check-%, $(check-qapi-schema-y)) check-tests/qapi-schema/doc-good.texi +check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS)) +check-block: $(patsubst %,check-%, $(check-block-y)) +check: check-qapi-schema check-unit check-qtest check-decodetree +check-clean: + rm -rf $(check-unit-y) tests/*.o $(QEMU_IOTESTS_HELPERS-y) + rm -rf $(sort $(foreach target,$(SYSEMU_TARGET_LIST), $(check-qtest-$(target)-y)) $(check-qtest-generic-y)) + rm -f tests/test-qapi-gen-timestamp + rm -rf $(TESTS_VENV_DIR) $(TESTS_RESULTS_DIR) + +clean: check-clean + +# Build the help program automatically + +all: $(QEMU_IOTESTS_HELPERS-y) + +-include $(wildcard tests/*.d) +-include $(wildcard tests/libqos/*.d) + +endif diff --git a/tests/Makefile.orig b/tests/Makefile.orig new file mode 100644 index 0000000000..e6474ba31b --- /dev/null +++ b/tests/Makefile.orig @@ -0,0 +1,569 @@ +export SRC_PATH + +qapi-py = $(SRC_PATH)/scripts/qapi.py $(SRC_PATH)/scripts/ordereddict.py + +# Get the list of all supported sysemu targets +SYSEMU_TARGET_LIST := $(subst -softmmu.mak,,$(notdir \ + $(wildcard $(SRC_PATH)/default-configs/*-softmmu.mak))) + +check-unit-y = tests/check-qdict$(EXESUF) +gcov-files-check-qdict-y = qobject/qdict.c +check-unit-y += tests/check-qfloat$(EXESUF) +gcov-files-check-qfloat-y = qobject/qfloat.c +check-unit-y += tests/check-qint$(EXESUF) +gcov-files-check-qint-y = qobject/qint.c +check-unit-y += tests/check-qstring$(EXESUF) +gcov-files-check-qstring-y = qobject/qstring.c +check-unit-y += tests/check-qlist$(EXESUF) +gcov-files-check-qlist-y = qobject/qlist.c +check-unit-y += tests/check-qjson$(EXESUF) +gcov-files-check-qjson-y = qobject/qjson.c +check-unit-y += tests/test-qmp-output-visitor$(EXESUF) +gcov-files-test-qmp-output-visitor-y = qapi/qmp-output-visitor.c +check-unit-y += tests/test-qmp-input-visitor$(EXESUF) +gcov-files-test-qmp-input-visitor-y = qapi/qmp-input-visitor.c +check-unit-y += tests/test-qmp-input-strict$(EXESUF) +check-unit-y += tests/test-qmp-commands$(EXESUF) +gcov-files-test-qmp-commands-y = qapi/qmp-dispatch.c +check-unit-y += tests/test-string-input-visitor$(EXESUF) +gcov-files-test-string-input-visitor-y = qapi/string-input-visitor.c +check-unit-y += tests/test-string-output-visitor$(EXESUF) +gcov-files-test-string-output-visitor-y = qapi/string-output-visitor.c +check-unit-y += tests/test-qmp-event$(EXESUF) +gcov-files-test-qmp-event-y += qapi/qmp-event.c +check-unit-y += tests/test-opts-visitor$(EXESUF) +gcov-files-test-opts-visitor-y = qapi/opts-visitor.c +check-unit-y += tests/test-coroutine$(EXESUF) +gcov-files-test-coroutine-y = coroutine-$(CONFIG_COROUTINE_BACKEND).c +check-unit-y += tests/test-visitor-serialization$(EXESUF) +check-unit-y += tests/test-iov$(EXESUF) +gcov-files-test-iov-y = util/iov.c +check-unit-y += tests/test-aio$(EXESUF) +check-unit-$(CONFIG_POSIX) += tests/test-rfifolock$(EXESUF) +check-unit-y += tests/test-throttle$(EXESUF) +gcov-files-test-aio-$(CONFIG_WIN32) = aio-win32.c +gcov-files-test-aio-$(CONFIG_POSIX) = aio-posix.c +check-unit-y += tests/test-thread-pool$(EXESUF) +gcov-files-test-thread-pool-y = thread-pool.c +gcov-files-test-hbitmap-y = util/hbitmap.c +check-unit-y += tests/test-hbitmap$(EXESUF) +check-unit-y += tests/test-x86-cpuid$(EXESUF) +# all code tested by test-x86-cpuid is inside topology.h +gcov-files-test-x86-cpuid-y = +ifeq ($(CONFIG_SOFTMMU),y) +check-unit-y += tests/test-xbzrle$(EXESUF) +gcov-files-test-xbzrle-y = migration/xbzrle.c +check-unit-$(CONFIG_POSIX) += tests/test-vmstate$(EXESUF) +endif +check-unit-y += tests/test-cutils$(EXESUF) +gcov-files-test-cutils-y += util/cutils.c +check-unit-y += tests/test-mul64$(EXESUF) +gcov-files-test-mul64-y = util/host-utils.c +check-unit-y += tests/test-int128$(EXESUF) +# all code tested by test-int128 is inside int128.h +gcov-files-test-int128-y = +check-unit-y += tests/rcutorture$(EXESUF) +gcov-files-rcutorture-y = util/rcu.c +check-unit-y += tests/test-rcu-list$(EXESUF) +gcov-files-test-rcu-list-y = util/rcu.c +check-unit-y += tests/test-bitops$(EXESUF) +check-unit-$(CONFIG_HAS_GLIB_SUBPROCESS_TESTS) += tests/test-qdev-global-props$(EXESUF) +check-unit-y += tests/check-qom-interface$(EXESUF) +gcov-files-check-qom-interface-y = qom/object.c +check-unit-y += tests/check-qom-proplist$(EXESUF) +gcov-files-check-qom-proplist-y = qom/object.c +check-unit-y += tests/test-qemu-opts$(EXESUF) +gcov-files-test-qemu-opts-y = qom/test-qemu-opts.c +check-unit-y += tests/test-write-threshold$(EXESUF) +gcov-files-test-write-threshold-y = block/write-threshold.c +check-unit-$(CONFIG_GNUTLS_HASH) += tests/test-crypto-hash$(EXESUF) +check-unit-y += tests/test-crypto-cipher$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlscredsx509$(EXESUF) +check-unit-$(CONFIG_GNUTLS) += tests/test-crypto-tlssession$(EXESUF) + +check-block-$(CONFIG_POSIX) += tests/qemu-iotests-quick.sh + +# All QTests for now are POSIX-only, but the dependencies are +# really in libqtest, not in the testcases themselves. + +gcov-files-ipack-y += hw/ipack/ipack.c +check-qtest-ipack-y += tests/ipoctal232-test$(EXESUF) +gcov-files-ipack-y += hw/char/ipoctal232.c + +check-qtest-virtioserial-y += tests/virtio-console-test$(EXESUF) +gcov-files-virtioserial-y += hw/char/virtio-console.c + +gcov-files-virtio-y += i386-softmmu/hw/virtio/virtio.c +check-qtest-virtio-y += tests/virtio-net-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/net/virtio-net.c +check-qtest-virtio-y += tests/virtio-balloon-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/virtio/virtio-balloon.c +check-qtest-virtio-y += tests/virtio-blk-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/block/virtio-blk.c +check-qtest-virtio-y += tests/virtio-rng-test$(EXESUF) +gcov-files-virtio-y += hw/virtio/virtio-rng.c +check-qtest-virtio-y += tests/virtio-scsi-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/scsi/virtio-scsi.c +ifeq ($(CONFIG_VIRTIO)$(CONFIG_VIRTFS)$(CONFIG_PCI),yyy) +check-qtest-virtio-y += tests/virtio-9p-test$(EXESUF) +gcov-files-virtio-y += hw/9pfs/virtio-9p.c +gcov-files-virtio-y += i386-softmmu/hw/9pfs/virtio-9p-device.c +endif +check-qtest-virtio-y += tests/virtio-serial-test$(EXESUF) +gcov-files-virtio-y += i386-softmmu/hw/char/virtio-serial-bus.c +check-qtest-virtio-y += $(check-qtest-virtioserial-y) +gcov-files-virtio-y += $(gcov-files-virtioserial-y) + +check-qtest-pci-y += tests/e1000-test$(EXESUF) +gcov-files-pci-y += hw/net/e1000.c +check-qtest-pci-y += tests/rtl8139-test$(EXESUF) +gcov-files-pci-y += hw/net/rtl8139.c +check-qtest-pci-y += tests/pcnet-test$(EXESUF) +gcov-files-pci-y += hw/net/pcnet.c +gcov-files-pci-y += hw/net/pcnet-pci.c +check-qtest-pci-y += tests/eepro100-test$(EXESUF) +gcov-files-pci-y += hw/net/eepro100.c +check-qtest-pci-y += tests/ne2000-test$(EXESUF) +gcov-files-pci-y += hw/net/ne2000.c +check-qtest-pci-y += tests/nvme-test$(EXESUF) +gcov-files-pci-y += hw/block/nvme.c +check-qtest-pci-y += tests/ac97-test$(EXESUF) +gcov-files-pci-y += hw/audio/ac97.c +check-qtest-pci-y += tests/es1370-test$(EXESUF) +gcov-files-pci-y += hw/audio/es1370.c +check-qtest-pci-y += $(check-qtest-virtio-y) +gcov-files-pci-y += $(gcov-files-virtio-y) hw/virtio/virtio-pci.c +check-qtest-pci-y += tests/tpci200-test$(EXESUF) +gcov-files-pci-y += hw/ipack/tpci200.c +check-qtest-pci-y += $(check-qtest-ipack-y) +gcov-files-pci-y += $(gcov-files-ipack-y) +check-qtest-pci-y += tests/display-vga-test$(EXESUF) +gcov-files-pci-y += hw/display/vga.c +gcov-files-pci-y += hw/display/cirrus_vga.c +gcov-files-pci-y += hw/display/vga-pci.c +gcov-files-pci-y += hw/display/virtio-gpu.c +gcov-files-pci-y += hw/display/virtio-gpu-pci.c +gcov-files-pci-$(CONFIG_VIRTIO_VGA) += hw/display/virtio-vga.c +check-qtest-pci-y += tests/intel-hda-test$(EXESUF) +gcov-files-pci-y += hw/audio/intel-hda.c hw/audio/hda-codec.c + +check-qtest-i386-y = tests/endianness-test$(EXESUF) +check-qtest-i386-y += tests/fdc-test$(EXESUF) +gcov-files-i386-y = hw/block/fdc.c +check-qtest-i386-y += tests/ide-test$(EXESUF) +check-qtest-i386-y += tests/ahci-test$(EXESUF) +check-qtest-i386-y += tests/hd-geo-test$(EXESUF) +gcov-files-i386-y += hw/block/hd-geometry.c +check-qtest-i386-y += tests/boot-order-test$(EXESUF) +check-qtest-i386-y += tests/bios-tables-test$(EXESUF) +check-qtest-i386-y += tests/rtc-test$(EXESUF) +check-qtest-i386-y += tests/i440fx-test$(EXESUF) +check-qtest-i386-y += tests/fw_cfg-test$(EXESUF) +check-qtest-i386-y += tests/drive_del-test$(EXESUF) +check-qtest-i386-y += tests/wdt_ib700-test$(EXESUF) +check-qtest-i386-y += tests/tco-test$(EXESUF) +gcov-files-i386-y += hw/watchdog/watchdog.c hw/watchdog/wdt_ib700.c +check-qtest-i386-y += $(check-qtest-pci-y) +gcov-files-i386-y += $(gcov-files-pci-y) +check-qtest-i386-y += tests/vmxnet3-test$(EXESUF) +gcov-files-i386-y += hw/net/vmxnet3.c +gcov-files-i386-y += hw/net/vmxnet_rx_pkt.c +gcov-files-i386-y += hw/net/vmxnet_tx_pkt.c +check-qtest-i386-y += tests/pvpanic-test$(EXESUF) +gcov-files-i386-y += i386-softmmu/hw/misc/pvpanic.c +check-qtest-i386-y += tests/i82801b11-test$(EXESUF) +gcov-files-i386-y += hw/pci-bridge/i82801b11.c +check-qtest-i386-y += tests/ioh3420-test$(EXESUF) +gcov-files-i386-y += hw/pci-bridge/ioh3420.c +check-qtest-i386-y += tests/usb-hcd-ohci-test$(EXESUF) +gcov-files-i386-y += hw/usb/hcd-ohci.c +check-qtest-i386-y += tests/usb-hcd-uhci-test$(EXESUF) +gcov-files-i386-y += hw/usb/hcd-uhci.c +check-qtest-i386-y += tests/usb-hcd-ehci-test$(EXESUF) +gcov-files-i386-y += hw/usb/hcd-ehci.c +gcov-files-i386-y += hw/usb/dev-hid.c +gcov-files-i386-y += hw/usb/dev-storage.c +check-qtest-i386-y += tests/usb-hcd-xhci-test$(EXESUF) +gcov-files-i386-y += hw/usb/hcd-xhci.c +check-qtest-i386-y += tests/pc-cpu-test$(EXESUF) +check-qtest-i386-y += tests/q35-test$(EXESUF) +gcov-files-i386-y += hw/pci-host/q35.c +ifeq ($(CONFIG_VHOST_NET),y) +check-qtest-i386-$(CONFIG_LINUX) += tests/vhost-user-test$(EXESUF) +endif +check-qtest-x86_64-y = $(check-qtest-i386-y) +gcov-files-i386-y += i386-softmmu/hw/timer/mc146818rtc.c +gcov-files-x86_64-y = $(subst i386-softmmu/,x86_64-softmmu/,$(gcov-files-i386-y)) +check-qtest-mips-y = tests/endianness-test$(EXESUF) +check-qtest-mips64-y = tests/endianness-test$(EXESUF) +check-qtest-mips64el-y = tests/endianness-test$(EXESUF) +check-qtest-ppc-y = tests/endianness-test$(EXESUF) +check-qtest-ppc64-y = tests/endianness-test$(EXESUF) +check-qtest-sh4-y = tests/endianness-test$(EXESUF) +check-qtest-sh4eb-y = tests/endianness-test$(EXESUF) +check-qtest-sparc64-y = tests/endianness-test$(EXESUF) +#check-qtest-sparc-y = tests/m48t59-test$(EXESUF) +#check-qtest-sparc64-y += tests/m48t59-test$(EXESUF) +gcov-files-sparc-y += hw/timer/m48t59.c +gcov-files-sparc64-y += hw/timer/m48t59.c +check-qtest-arm-y = tests/tmp105-test$(EXESUF) +check-qtest-arm-y = tests/ds1338-test$(EXESUF) +gcov-files-arm-y += hw/misc/tmp105.c +check-qtest-arm-y += tests/virtio-blk-test$(EXESUF) +gcov-files-arm-y += arm-softmmu/hw/block/virtio-blk.c +check-qtest-ppc-y += tests/boot-order-test$(EXESUF) +check-qtest-ppc64-y += tests/boot-order-test$(EXESUF) +check-qtest-ppc64-y += tests/spapr-phb-test$(EXESUF) +gcov-files-ppc64-y += ppc64-softmmu/hw/ppc/spapr_pci.c +check-qtest-microblazeel-y = $(check-qtest-microblaze-y) +check-qtest-xtensaeb-y = $(check-qtest-xtensa-y) + +# qom-test works for all sysemu architectures: +$(foreach target,$(SYSEMU_TARGET_LIST), \ + $(if $(findstring tests/qom-test$(EXESUF), $(check-qtest-$(target)-y)),, \ + $(eval check-qtest-$(target)-y += tests/qom-test$(EXESUF)))) + +check-qapi-schema-y := $(addprefix tests/qapi-schema/, \ + comments.json empty.json enum-empty.json enum-missing-data.json \ + enum-wrong-data.json enum-int-member.json enum-dict-member.json \ + enum-clash-member.json enum-max-member.json enum-union-clash.json \ + enum-bad-name.json enum-bad-prefix.json \ + funny-char.json indented-expr.json \ + missing-type.json bad-ident.json ident-with-escape.json \ + escape-outside-string.json unknown-escape.json \ + escape-too-short.json escape-too-big.json unicode-str.json \ + double-type.json bad-base.json bad-type-bool.json bad-type-int.json \ + bad-type-dict.json double-data.json unknown-expr-key.json \ + redefined-type.json redefined-command.json redefined-builtin.json \ + redefined-event.json command-int.json bad-data.json event-max.json \ + type-bypass-bad-gen.json \ + args-invalid.json \ + args-array-empty.json args-array-unknown.json args-int.json \ + args-unknown.json args-member-unknown.json args-member-array.json \ + args-member-array-bad.json args-alternate.json args-union.json \ + args-any.json \ + returns-array-bad.json returns-int.json returns-dict.json \ + returns-unknown.json returns-alternate.json returns-whitelist.json \ + missing-colon.json missing-comma-list.json missing-comma-object.json \ + struct-data-invalid.json struct-member-invalid.json \ + nested-struct-data.json non-objects.json \ + qapi-schema-test.json quoted-structural-chars.json \ + leading-comma-list.json leading-comma-object.json \ + trailing-comma-list.json trailing-comma-object.json \ + unclosed-list.json unclosed-object.json unclosed-string.json \ + duplicate-key.json union-invalid-base.json union-bad-branch.json \ + union-optional-branch.json union-unknown.json union-max.json \ + flat-union-optional-discriminator.json flat-union-no-base.json \ + flat-union-invalid-discriminator.json flat-union-inline.json \ + flat-union-invalid-branch-key.json flat-union-reverse-define.json \ + flat-union-string-discriminator.json union-base-no-discriminator.json \ + flat-union-bad-discriminator.json flat-union-bad-base.json \ + flat-union-base-any.json \ + flat-union-array-branch.json flat-union-int-branch.json \ + flat-union-base-union.json flat-union-branch-clash.json \ + alternate-nested.json alternate-unknown.json alternate-clash.json \ + alternate-good.json alternate-base.json alternate-array.json \ + alternate-conflict-string.json alternate-conflict-dict.json \ + include-simple.json include-relpath.json include-format-err.json \ + include-non-file.json include-no-file.json include-before-err.json \ + include-nested-err.json include-self-cycle.json include-cycle.json \ + include-repetition.json event-nest-struct.json event-case.json \ + struct-base-clash.json struct-base-clash-deep.json ) + +GENERATED_HEADERS += tests/test-qapi-types.h tests/test-qapi-visit.h \ + tests/test-qmp-commands.h tests/test-qapi-event.h \ + tests/test-qmp-introspect.h + +test-obj-y = tests/check-qint.o tests/check-qstring.o tests/check-qdict.o \ + tests/check-qlist.o tests/check-qfloat.o tests/check-qjson.o \ + tests/test-coroutine.o tests/test-string-output-visitor.o \ + tests/test-string-input-visitor.o tests/test-qmp-output-visitor.o \ + tests/test-qmp-input-visitor.o tests/test-qmp-input-strict.o \ + tests/test-qmp-commands.o tests/test-visitor-serialization.o \ + tests/test-x86-cpuid.o tests/test-mul64.o tests/test-int128.o \ + tests/test-opts-visitor.o tests/test-qmp-event.o \ + tests/rcutorture.o tests/test-rcu-list.o + +$(test-obj-y): QEMU_INCLUDES += -Itests +QEMU_CFLAGS += -I$(SRC_PATH)/tests + + +# Deps that are common to various different sets of tests below +test-util-obj-y = libqemuutil.a libqemustub.a +test-qom-obj-y = $(qom-obj-y) $(test-util-obj-y) +test-qapi-obj-y = tests/test-qapi-visit.o tests/test-qapi-types.o \ + tests/test-qapi-event.o tests/test-qmp-introspect.o \ + $(test-qom-obj-y) +test-crypto-obj-y = $(crypto-obj-y) $(test-qom-obj-y) +test-block-obj-y = $(block-obj-y) $(test-crypto-obj-y) + +tests/check-qint$(EXESUF): tests/check-qint.o $(test-util-obj-y) +tests/check-qstring$(EXESUF): tests/check-qstring.o $(test-util-obj-y) +tests/check-qdict$(EXESUF): tests/check-qdict.o $(test-util-obj-y) +tests/check-qlist$(EXESUF): tests/check-qlist.o $(test-util-obj-y) +tests/check-qfloat$(EXESUF): tests/check-qfloat.o $(test-util-obj-y) +tests/check-qjson$(EXESUF): tests/check-qjson.o $(test-util-obj-y) +tests/check-qom-interface$(EXESUF): tests/check-qom-interface.o $(test-qom-obj-y) +tests/check-qom-proplist$(EXESUF): tests/check-qom-proplist.o $(test-qom-obj-y) +tests/test-coroutine$(EXESUF): tests/test-coroutine.o $(test-block-obj-y) +tests/test-aio$(EXESUF): tests/test-aio.o $(test-block-obj-y) +tests/test-rfifolock$(EXESUF): tests/test-rfifolock.o $(test-util-obj-y) +tests/test-throttle$(EXESUF): tests/test-throttle.o $(test-block-obj-y) +tests/test-thread-pool$(EXESUF): tests/test-thread-pool.o $(test-block-obj-y) +tests/test-iov$(EXESUF): tests/test-iov.o $(test-util-obj-y) +tests/test-hbitmap$(EXESUF): tests/test-hbitmap.o $(test-util-obj-y) +tests/test-x86-cpuid$(EXESUF): tests/test-x86-cpuid.o +tests/test-xbzrle$(EXESUF): tests/test-xbzrle.o migration/xbzrle.o page_cache.o $(test-util-obj-y) +tests/test-cutils$(EXESUF): tests/test-cutils.o util/cutils.o +tests/test-int128$(EXESUF): tests/test-int128.o +tests/rcutorture$(EXESUF): tests/rcutorture.o $(test-util-obj-y) +tests/test-rcu-list$(EXESUF): tests/test-rcu-list.o $(test-util-obj-y) + +tests/test-qdev-global-props$(EXESUF): tests/test-qdev-global-props.o \ + hw/core/qdev.o hw/core/qdev-properties.o hw/core/hotplug.o\ + hw/core/irq.o \ + hw/core/fw-path-provider.o \ + $(test-qapi-obj-y) +tests/test-vmstate$(EXESUF): tests/test-vmstate.o \ + migration/vmstate.o migration/qemu-file.o migration/qemu-file-buf.o \ + migration/qemu-file-unix.o qjson.o \ + $(test-qom-obj-y) + +tests/test-qapi-types.c tests/test-qapi-types.h :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-types.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-types.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") +tests/test-qapi-visit.c tests/test-qapi-visit.h :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-visit.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-visit.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") +tests/test-qmp-commands.h tests/test-qmp-marshal.c :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-commands.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-commands.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") +tests/test-qapi-event.c tests/test-qapi-event.h :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-event.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-event.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") +tests/test-qmp-introspect.c tests/test-qmp-introspect.h :\ +$(SRC_PATH)/tests/qapi-schema/qapi-schema-test.json $(SRC_PATH)/scripts/qapi-introspect.py $(qapi-py) + $(call quiet-command,$(PYTHON) $(SRC_PATH)/scripts/qapi-introspect.py \ + $(gen-out-type) -o tests -p "test-" $<, \ + " GEN $@") + +tests/test-string-output-visitor$(EXESUF): tests/test-string-output-visitor.o $(test-qapi-obj-y) +tests/test-string-input-visitor$(EXESUF): tests/test-string-input-visitor.o $(test-qapi-obj-y) +tests/test-qmp-event$(EXESUF): tests/test-qmp-event.o $(test-qapi-obj-y) +tests/test-qmp-output-visitor$(EXESUF): tests/test-qmp-output-visitor.o $(test-qapi-obj-y) +tests/test-qmp-input-visitor$(EXESUF): tests/test-qmp-input-visitor.o $(test-qapi-obj-y) +tests/test-qmp-input-strict$(EXESUF): tests/test-qmp-input-strict.o $(test-qapi-obj-y) +tests/test-qmp-commands$(EXESUF): tests/test-qmp-commands.o tests/test-qmp-marshal.o $(test-qapi-obj-y) +tests/test-visitor-serialization$(EXESUF): tests/test-visitor-serialization.o $(test-qapi-obj-y) +tests/test-opts-visitor$(EXESUF): tests/test-opts-visitor.o $(test-qapi-obj-y) + +tests/test-mul64$(EXESUF): tests/test-mul64.o $(test-util-obj-y) +tests/test-bitops$(EXESUF): tests/test-bitops.o $(test-util-obj-y) +tests/test-crypto-hash$(EXESUF): tests/test-crypto-hash.o $(test-crypto-obj-y) +tests/test-crypto-cipher$(EXESUF): tests/test-crypto-cipher.o $(test-crypto-obj-y) +tests/test-crypto-tlscredsx509$(EXESUF): tests/test-crypto-tlscredsx509.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o $(test-crypto-obj-y) +tests/test-crypto-tlssession$(EXESUF): tests/test-crypto-tlssession.o \ + tests/crypto-tls-x509-helpers.o tests/pkix_asn1_tab.o $(test-crypto-obj-y) + +libqos-obj-y = tests/libqos/pci.o tests/libqos/fw_cfg.o tests/libqos/malloc.o +libqos-obj-y += tests/libqos/i2c.o tests/libqos/libqos.o +libqos-pc-obj-y = $(libqos-obj-y) tests/libqos/pci-pc.o +libqos-pc-obj-y += tests/libqos/malloc-pc.o tests/libqos/libqos-pc.o +libqos-pc-obj-y += tests/libqos/ahci.o +libqos-omap-obj-y = $(libqos-obj-y) tests/libqos/i2c-omap.o +libqos-imx-obj-y = $(libqos-obj-y) tests/libqos/i2c-imx.o +libqos-usb-obj-y = $(libqos-pc-obj-y) tests/libqos/usb.o +libqos-virtio-obj-y = $(libqos-pc-obj-y) tests/libqos/virtio.o tests/libqos/virtio-pci.o tests/libqos/virtio-mmio.o tests/libqos/malloc-generic.o + +tests/rtc-test$(EXESUF): tests/rtc-test.o +tests/m48t59-test$(EXESUF): tests/m48t59-test.o +tests/endianness-test$(EXESUF): tests/endianness-test.o +tests/spapr-phb-test$(EXESUF): tests/spapr-phb-test.o $(libqos-obj-y) +tests/fdc-test$(EXESUF): tests/fdc-test.o +tests/ide-test$(EXESUF): tests/ide-test.o $(libqos-pc-obj-y) +tests/ahci-test$(EXESUF): tests/ahci-test.o $(libqos-pc-obj-y) +tests/hd-geo-test$(EXESUF): tests/hd-geo-test.o +tests/boot-order-test$(EXESUF): tests/boot-order-test.o $(libqos-obj-y) +tests/bios-tables-test$(EXESUF): tests/bios-tables-test.o $(libqos-obj-y) +tests/tmp105-test$(EXESUF): tests/tmp105-test.o $(libqos-omap-obj-y) +tests/ds1338-test$(EXESUF): tests/ds1338-test.o $(libqos-imx-obj-y) +tests/i440fx-test$(EXESUF): tests/i440fx-test.o $(libqos-pc-obj-y) +tests/q35-test$(EXESUF): tests/q35-test.o $(libqos-pc-obj-y) +tests/fw_cfg-test$(EXESUF): tests/fw_cfg-test.o $(libqos-pc-obj-y) +tests/e1000-test$(EXESUF): tests/e1000-test.o +tests/rtl8139-test$(EXESUF): tests/rtl8139-test.o $(libqos-pc-obj-y) +tests/pcnet-test$(EXESUF): tests/pcnet-test.o +tests/eepro100-test$(EXESUF): tests/eepro100-test.o +tests/vmxnet3-test$(EXESUF): tests/vmxnet3-test.o +tests/ne2000-test$(EXESUF): tests/ne2000-test.o +tests/wdt_ib700-test$(EXESUF): tests/wdt_ib700-test.o +tests/tco-test$(EXESUF): tests/tco-test.o $(libqos-pc-obj-y) +tests/virtio-balloon-test$(EXESUF): tests/virtio-balloon-test.o +tests/virtio-blk-test$(EXESUF): tests/virtio-blk-test.o $(libqos-virtio-obj-y) +tests/virtio-net-test$(EXESUF): tests/virtio-net-test.o $(libqos-pc-obj-y) $(libqos-virtio-obj-y) +tests/virtio-rng-test$(EXESUF): tests/virtio-rng-test.o $(libqos-pc-obj-y) +tests/virtio-scsi-test$(EXESUF): tests/virtio-scsi-test.o $(libqos-virtio-obj-y) +tests/virtio-9p-test$(EXESUF): tests/virtio-9p-test.o +tests/virtio-serial-test$(EXESUF): tests/virtio-serial-test.o +tests/virtio-console-test$(EXESUF): tests/virtio-console-test.o +tests/tpci200-test$(EXESUF): tests/tpci200-test.o +tests/display-vga-test$(EXESUF): tests/display-vga-test.o +tests/ipoctal232-test$(EXESUF): tests/ipoctal232-test.o +tests/qom-test$(EXESUF): tests/qom-test.o +tests/drive_del-test$(EXESUF): tests/drive_del-test.o $(libqos-pc-obj-y) +tests/qdev-monitor-test$(EXESUF): tests/qdev-monitor-test.o $(libqos-pc-obj-y) +tests/nvme-test$(EXESUF): tests/nvme-test.o +tests/pvpanic-test$(EXESUF): tests/pvpanic-test.o +tests/i82801b11-test$(EXESUF): tests/i82801b11-test.o +tests/ac97-test$(EXESUF): tests/ac97-test.o +tests/es1370-test$(EXESUF): tests/es1370-test.o +tests/intel-hda-test$(EXESUF): tests/intel-hda-test.o +tests/ioh3420-test$(EXESUF): tests/ioh3420-test.o +tests/usb-hcd-ohci-test$(EXESUF): tests/usb-hcd-ohci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-uhci-test$(EXESUF): tests/usb-hcd-uhci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-ehci-test$(EXESUF): tests/usb-hcd-ehci-test.o $(libqos-usb-obj-y) +tests/usb-hcd-xhci-test$(EXESUF): tests/usb-hcd-xhci-test.o $(libqos-usb-obj-y) +tests/pc-cpu-test$(EXESUF): tests/pc-cpu-test.o +tests/vhost-user-test$(EXESUF): tests/vhost-user-test.o qemu-char.o qemu-timer.o $(qtest-obj-y) +tests/qemu-iotests/socket_scm_helper$(EXESUF): tests/qemu-iotests/socket_scm_helper.o +tests/test-qemu-opts$(EXESUF): tests/test-qemu-opts.o $(test-util-obj-y) +tests/test-write-threshold$(EXESUF): tests/test-write-threshold.o $(test-block-obj-y) + +ifeq ($(CONFIG_POSIX),y) +LIBS += -lutil +endif +LIBS += $(TEST_LIBS) +CFLAGS += $(TEST_CFLAGS) + +# QTest rules + +TARGETS=$(patsubst %-softmmu,%, $(filter %-softmmu,$(TARGET_DIRS))) +ifeq ($(CONFIG_POSIX),y) +QTEST_TARGETS=$(foreach TARGET,$(TARGETS), $(if $(check-qtest-$(TARGET)-y), $(TARGET),)) +check-qtest-y=$(foreach TARGET,$(TARGETS), $(check-qtest-$(TARGET)-y)) +endif + +qtest-obj-y = tests/libqtest.o $(test-util-obj-y) +$(check-qtest-y): $(qtest-obj-y) + +.PHONY: check-help +check-help: + @echo "Regression testing targets:" + @echo + @echo " make check Run all tests" + @echo " make check-qtest-TARGET Run qtest tests for given target" + @echo " make check-qtest Run qtest tests" + @echo " make check-unit Run qobject tests" + @echo " make check-qapi-schema Run QAPI schema tests" + @echo " make check-block Run block tests" + @echo " make check-report.html Generates an HTML test report" + @echo " make check-clean Clean the tests" + @echo + @echo "Please note that HTML reports do not regenerate if the unit tests" + @echo "has not changed." + @echo + @echo "The variable SPEED can be set to control the gtester speed setting." + @echo "Default options are -k and (for make V=1) --verbose; they can be" + @echo "changed with variable GTESTER_OPTIONS." + +SPEED = quick +GTESTER_OPTIONS = -k $(if $(V),--verbose,-q) +GCOV_OPTIONS = -n $(if $(V),-f,) + +# gtester tests, possibly with verbose output + +.PHONY: $(patsubst %, check-qtest-%, $(QTEST_TARGETS)) +$(patsubst %, check-qtest-%, $(QTEST_TARGETS)): check-qtest-%: $(check-qtest-y) + $(if $(CONFIG_GCOV),@rm -f *.gcda */*.gcda */*/*.gcda */*/*/*.gcda,) + $(call quiet-command,QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ + QTEST_QEMU_IMG=qemu-img$(EXESUF) \ + MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$((RANDOM % 255 + 1))} \ + gtester $(GTESTER_OPTIONS) -m=$(SPEED) $(check-qtest-$*-y),"GTESTER $@") + $(if $(CONFIG_GCOV),@for f in $(gcov-files-$*-y); do \ + echo Gcov report for $$f:;\ + $(GCOV) $(GCOV_OPTIONS) $$f -o `dirname $$f`; \ + done,) + +.PHONY: $(patsubst %, check-%, $(check-unit-y)) +$(patsubst %, check-%, $(check-unit-y)): check-%: % + $(if $(CONFIG_GCOV),@rm -f *.gcda */*.gcda */*/*.gcda */*/*/*.gcda,) + $(call quiet-command, \ + MALLOC_PERTURB_=$${MALLOC_PERTURB_:-$$((RANDOM % 255 + 1))} \ + gtester $(GTESTER_OPTIONS) -m=$(SPEED) $*,"GTESTER $*") + $(if $(CONFIG_GCOV),@for f in $(gcov-files-$(subst tests/,,$*)-y); do \ + echo Gcov report for $$f:;\ + $(GCOV) $(GCOV_OPTIONS) $$f -o `dirname $$f`; \ + done,) + +# gtester tests with XML output + +$(patsubst %, check-report-qtest-%.xml, $(QTEST_TARGETS)): check-report-qtest-%.xml: $(check-qtest-y) + $(call quiet-command,QTEST_QEMU_BINARY=$*-softmmu/qemu-system-$* \ + QTEST_QEMU_IMG=qemu-img$(EXESUF) \ + gtester -q $(GTESTER_OPTIONS) -o $@ -m=$(SPEED) $(check-qtest-$*-y),"GTESTER $@") + +check-report-unit.xml: $(check-unit-y) + $(call quiet-command,gtester -q $(GTESTER_OPTIONS) -o $@ -m=$(SPEED) $^, "GTESTER $@") + +# Reports and overall runs + +check-report.xml: $(patsubst %,check-report-qtest-%.xml, $(QTEST_TARGETS)) check-report-unit.xml + $(call quiet-command,$(SRC_PATH)/scripts/gtester-cat $^ > $@, " GEN $@") + +check-report.html: check-report.xml + $(call quiet-command,gtester-report $< > $@, " GEN $@") + + +# Other tests + +QEMU_IOTESTS_HELPERS-$(CONFIG_LINUX) = tests/qemu-iotests/socket_scm_helper$(EXESUF) + +.PHONY: check-tests/qemu-iotests-quick.sh +check-tests/qemu-iotests-quick.sh: tests/qemu-iotests-quick.sh qemu-img$(EXESUF) qemu-io$(EXESUF) $(QEMU_IOTESTS_HELPERS-y) + $< + +.PHONY: check-tests/test-qapi.py +check-tests/test-qapi.py: tests/test-qapi.py + +.PHONY: $(patsubst %, check-%, $(check-qapi-schema-y)) +$(patsubst %, check-%, $(check-qapi-schema-y)): check-%.json: $(SRC_PATH)/%.json + $(call quiet-command, PYTHONPATH=$(SRC_PATH)/scripts \ + $(PYTHON) $(SRC_PATH)/tests/qapi-schema/test-qapi.py \ + $^ >$*.test.out 2>$*.test.err; \ + echo $$? >$*.test.exit, \ + " TEST $*.out") + @diff -q $(SRC_PATH)/$*.out $*.test.out + @# Sanitize error messages (make them independent of build directory) + @perl -p -e 's|\Q$(SRC_PATH)\E/||g' $*.test.err | diff -q $(SRC_PATH)/$*.err - + @diff -q $(SRC_PATH)/$*.exit $*.test.exit + +# Consolidated targets + +.PHONY: check-qapi-schema check-qtest check-unit check check-clean +check-qapi-schema: $(patsubst %,check-%, $(check-qapi-schema-y)) +check-qtest: $(patsubst %,check-qtest-%, $(QTEST_TARGETS)) +check-unit: $(patsubst %,check-%, $(check-unit-y)) +check-block: $(patsubst %,check-%, $(check-block-y)) +check: check-qapi-schema check-unit check-qtest +check-clean: + $(MAKE) -C tests/tcg clean + rm -rf $(check-unit-y) tests/*.o $(QEMU_IOTESTS_HELPERS-y) + rm -rf $(sort $(foreach target,$(SYSEMU_TARGET_LIST), $(check-qtest-$(target)-y))) + +clean: check-clean + +# Build the help program automatically + +all: $(QEMU_IOTESTS_HELPERS-y) + +-include $(wildcard tests/*.d) +-include $(wildcard tests/libqos/*.d) diff --git a/tests/bios-tables-test.c.orig b/tests/bios-tables-test.c.orig new file mode 100644 index 0000000000..d455b2abfc --- /dev/null +++ b/tests/bios-tables-test.c.orig @@ -0,0 +1,925 @@ +/* + * Boot order test cases. + * + * Copyright (c) 2013 Red Hat Inc. + * + * Authors: + * Michael S. Tsirkin <mst@redhat.com>, + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" +#include <glib/gstdio.h> +#include "qemu-common.h" +#include "hw/firmware/smbios.h" +#include "qemu/bitmap.h" +#include "acpi-utils.h" +#include "boot-sector.h" + +#define MACHINE_PC "pc" +#define MACHINE_Q35 "q35" + +#define ACPI_REBUILD_EXPECTED_AML "TEST_ACPI_REBUILD_AML" + +typedef struct { + const char *machine; + const char *variant; + uint32_t rsdp_addr; + uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */]; + AcpiRsdtDescriptorRev1 rsdt_table; + uint32_t dsdt_addr; + uint32_t facs_addr; + AcpiFacsDescriptorRev1 facs_table; + uint32_t *rsdt_tables_addr; + int rsdt_tables_nr; + GArray *tables; + uint32_t smbios_ep_addr; + struct smbios_21_entry_point smbios_ep_table; + uint8_t *required_struct_types; + int required_struct_types_len; + QTestState *qts; +} test_data; + +static char disk[] = "tests/acpi-test-disk-XXXXXX"; +static const char *data_dir = "tests/data/acpi"; +#ifdef CONFIG_IASL +static const char *iasl = stringify(CONFIG_IASL); +#else +static const char *iasl; +#endif + +static void free_test_data(test_data *data) +{ + AcpiSdtTable *temp; + int i; + + g_free(data->rsdt_tables_addr); + + for (i = 0; i < data->tables->len; ++i) { + temp = &g_array_index(data->tables, AcpiSdtTable, i); + g_free(temp->aml); + if (temp->aml_file && + !temp->tmp_files_retain && + g_strstr_len(temp->aml_file, -1, "aml-")) { + unlink(temp->aml_file); + } + g_free(temp->aml_file); + g_free(temp->asl); + if (temp->asl_file && + !temp->tmp_files_retain) { + unlink(temp->asl_file); + } + g_free(temp->asl_file); + } + + g_array_free(data->tables, true); +} + +static void test_acpi_rsdp_address(test_data *data) +{ + uint32_t off = acpi_find_rsdp_address(data->qts); + g_assert_cmphex(off, <, 0x100000); + data->rsdp_addr = off; +} + +static void test_acpi_rsdp_table(test_data *data) +{ + uint8_t *rsdp_table = data->rsdp_table, revision; + uint32_t addr = data->rsdp_addr; + + acpi_parse_rsdp_table(data->qts, addr, rsdp_table); + revision = rsdp_table[15 /* Revision offset */]; + + switch (revision) { + case 0: /* ACPI 1.0 RSDP */ + /* With rev 1, checksum is only for the first 20 bytes */ + g_assert(!acpi_calc_checksum(rsdp_table, 20)); + break; + case 2: /* ACPI 2.0+ RSDP */ + /* With revision 2, we have 2 checksums */ + g_assert(!acpi_calc_checksum(rsdp_table, 20)); + g_assert(!acpi_calc_checksum(rsdp_table, 36)); + break; + default: + g_assert_not_reached(); + } +} + +static void test_acpi_rsdt_table(test_data *data) +{ + AcpiRsdtDescriptorRev1 *rsdt_table = &data->rsdt_table; + uint32_t addr = acpi_get_rsdt_address(data->rsdp_table); + uint32_t *tables; + int tables_nr; + uint8_t checksum; + uint32_t rsdt_table_length; + + /* read the header */ + ACPI_READ_TABLE_HEADER(data->qts, rsdt_table, addr); + ACPI_ASSERT_CMP(rsdt_table->signature, "RSDT"); + + rsdt_table_length = le32_to_cpu(rsdt_table->length); + + /* compute the table entries in rsdt */ + tables_nr = (rsdt_table_length - sizeof(AcpiRsdtDescriptorRev1)) / + sizeof(uint32_t); + g_assert(tables_nr > 0); + + /* get the addresses of the tables pointed by rsdt */ + tables = g_new0(uint32_t, tables_nr); + ACPI_READ_ARRAY_PTR(data->qts, tables, tables_nr, addr); + + checksum = acpi_calc_checksum((uint8_t *)rsdt_table, rsdt_table_length) + + acpi_calc_checksum((uint8_t *)tables, + tables_nr * sizeof(uint32_t)); + g_assert(!checksum); + + /* SSDT tables after FADT */ + data->rsdt_tables_addr = tables; + data->rsdt_tables_nr = tables_nr; +} + +static void fadt_fetch_facs_and_dsdt_ptrs(test_data *data) +{ + uint32_t addr; + AcpiTableHeader hdr; + + /* FADT table comes first */ + addr = le32_to_cpu(data->rsdt_tables_addr[0]); + ACPI_READ_TABLE_HEADER(data->qts, &hdr, addr); + ACPI_ASSERT_CMP(hdr.signature, "FACP"); + + ACPI_READ_FIELD(data->qts, data->facs_addr, addr); + ACPI_READ_FIELD(data->qts, data->dsdt_addr, addr); +} + +static void sanitize_fadt_ptrs(test_data *data) +{ + /* fixup pointers in FADT */ + int i; + + for (i = 0; i < data->tables->len; i++) { + AcpiSdtTable *sdt = &g_array_index(data->tables, AcpiSdtTable, i); + + if (memcmp(&sdt->header.signature, "FACP", 4)) { + continue; + } + + /* check original FADT checksum before sanitizing table */ + g_assert(!(uint8_t)( + acpi_calc_checksum((uint8_t *)sdt, sizeof(AcpiTableHeader)) + + acpi_calc_checksum((uint8_t *)sdt->aml, sdt->aml_len) + )); + + /* sdt->aml field offset := spec offset - header size */ + memset(sdt->aml + 0, 0, 4); /* sanitize FIRMWARE_CTRL(36) ptr */ + memset(sdt->aml + 4, 0, 4); /* sanitize DSDT(40) ptr */ + if (sdt->header.revision >= 3) { + memset(sdt->aml + 96, 0, 8); /* sanitize X_FIRMWARE_CTRL(132) ptr */ + memset(sdt->aml + 104, 0, 8); /* sanitize X_DSDT(140) ptr */ + } + + /* update checksum */ + sdt->header.checksum = 0; + sdt->header.checksum -= + acpi_calc_checksum((uint8_t *)sdt, sizeof(AcpiTableHeader)) + + acpi_calc_checksum((uint8_t *)sdt->aml, sdt->aml_len); + break; + } +} + +static void test_acpi_facs_table(test_data *data) +{ + AcpiFacsDescriptorRev1 *facs_table = &data->facs_table; + uint32_t addr = le32_to_cpu(data->facs_addr); + + ACPI_READ_FIELD(data->qts, facs_table->signature, addr); + ACPI_READ_FIELD(data->qts, facs_table->length, addr); + ACPI_READ_FIELD(data->qts, facs_table->hardware_signature, addr); + ACPI_READ_FIELD(data->qts, facs_table->firmware_waking_vector, addr); + ACPI_READ_FIELD(data->qts, facs_table->global_lock, addr); + ACPI_READ_FIELD(data->qts, facs_table->flags, addr); + ACPI_READ_ARRAY(data->qts, facs_table->resverved3, addr); + + ACPI_ASSERT_CMP(facs_table->signature, "FACS"); +} + +/** fetch_table + * load ACPI table at @addr into table descriptor @sdt_table + * and check that header checksum matches actual one. + */ +static void fetch_table(QTestState *qts, AcpiSdtTable *sdt_table, uint32_t addr) +{ + uint8_t checksum; + + memset(sdt_table, 0, sizeof(*sdt_table)); + ACPI_READ_TABLE_HEADER(qts, &sdt_table->header, addr); + + sdt_table->aml_len = le32_to_cpu(sdt_table->header.length) + - sizeof(AcpiTableHeader); + sdt_table->aml = g_malloc0(sdt_table->aml_len); + ACPI_READ_ARRAY_PTR(qts, sdt_table->aml, sdt_table->aml_len, addr); + + checksum = acpi_calc_checksum((uint8_t *)sdt_table, + sizeof(AcpiTableHeader)) + + acpi_calc_checksum((uint8_t *)sdt_table->aml, + sdt_table->aml_len); + g_assert(!checksum); +} + +static void test_acpi_dsdt_table(test_data *data) +{ + AcpiSdtTable dsdt_table; + uint32_t addr = le32_to_cpu(data->dsdt_addr); + + fetch_table(data->qts, &dsdt_table, addr); + ACPI_ASSERT_CMP(dsdt_table.header.signature, "DSDT"); + + /* Since DSDT isn't in RSDT, add DSDT to ASL test tables list manually */ + g_array_append_val(data->tables, dsdt_table); +} + +/* Load all tables and add to test list directly RSDT referenced tables */ +static void fetch_rsdt_referenced_tables(test_data *data) +{ + int tables_nr = data->rsdt_tables_nr; + int i; + + for (i = 0; i < tables_nr; i++) { + AcpiSdtTable ssdt_table; + uint32_t addr; + + addr = le32_to_cpu(data->rsdt_tables_addr[i]); + fetch_table(data->qts, &ssdt_table, addr); + + /* Add table to ASL test tables list */ + g_array_append_val(data->tables, ssdt_table); + } +} + +static void dump_aml_files(test_data *data, bool rebuild) +{ + AcpiSdtTable *sdt; + GError *error = NULL; + gchar *aml_file = NULL; + gint fd; + ssize_t ret; + int i; + + for (i = 0; i < data->tables->len; ++i) { + const char *ext = data->variant ? data->variant : ""; + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + g_assert(sdt->aml); + + if (rebuild) { + aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine, + (gchar *)&sdt->header.signature, ext); + fd = g_open(aml_file, O_WRONLY|O_TRUNC|O_CREAT, + S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); + } else { + fd = g_file_open_tmp("aml-XXXXXX", &sdt->aml_file, &error); + g_assert_no_error(error); + } + g_assert(fd >= 0); + + ret = qemu_write_full(fd, sdt, sizeof(AcpiTableHeader)); + g_assert(ret == sizeof(AcpiTableHeader)); + ret = qemu_write_full(fd, sdt->aml, sdt->aml_len); + g_assert(ret == sdt->aml_len); + + close(fd); + + g_free(aml_file); + } +} + +static bool compare_signature(AcpiSdtTable *sdt, const char *signature) +{ + return !memcmp(&sdt->header.signature, signature, 4); +} + +static bool load_asl(GArray *sdts, AcpiSdtTable *sdt) +{ + AcpiSdtTable *temp; + GError *error = NULL; + GString *command_line = g_string_new(iasl); + gint fd; + gchar *out, *out_err; + gboolean ret; + int i; + + fd = g_file_open_tmp("asl-XXXXXX.dsl", &sdt->asl_file, &error); + g_assert_no_error(error); + close(fd); + + /* build command line */ + g_string_append_printf(command_line, " -p %s ", sdt->asl_file); + if (compare_signature(sdt, "DSDT") || + compare_signature(sdt, "SSDT")) { + for (i = 0; i < sdts->len; ++i) { + temp = &g_array_index(sdts, AcpiSdtTable, i); + if (compare_signature(temp, "DSDT") || + compare_signature(temp, "SSDT")) { + g_string_append_printf(command_line, "-e %s ", temp->aml_file); + } + } + } + g_string_append_printf(command_line, "-d %s", sdt->aml_file); + + /* pass 'out' and 'out_err' in order to be redirected */ + ret = g_spawn_command_line_sync(command_line->str, &out, &out_err, NULL, &error); + g_assert_no_error(error); + if (ret) { + ret = g_file_get_contents(sdt->asl_file, &sdt->asl, + &sdt->asl_len, &error); + g_assert(ret); + g_assert_no_error(error); + ret = (sdt->asl_len > 0); + } + + g_free(out); + g_free(out_err); + g_string_free(command_line, true); + + return !ret; +} + +#define COMMENT_END "*/" +#define DEF_BLOCK "DefinitionBlock (" +#define BLOCK_NAME_END "," + +static GString *normalize_asl(gchar *asl_code) +{ + GString *asl = g_string_new(asl_code); + gchar *comment, *block_name; + + /* strip comments (different generation days) */ + comment = g_strstr_len(asl->str, asl->len, COMMENT_END); + if (comment) { + comment += strlen(COMMENT_END); + while (*comment == '\n') { + comment++; + } + asl = g_string_erase(asl, 0, comment - asl->str); + } + + /* strip def block name (it has file path in it) */ + if (g_str_has_prefix(asl->str, DEF_BLOCK)) { + block_name = g_strstr_len(asl->str, asl->len, BLOCK_NAME_END); + g_assert(block_name); + asl = g_string_erase(asl, 0, + block_name + sizeof(BLOCK_NAME_END) - asl->str); + } + + return asl; +} + +static GArray *load_expected_aml(test_data *data) +{ + int i; + AcpiSdtTable *sdt; + GError *error = NULL; + gboolean ret; + + GArray *exp_tables = g_array_new(false, true, sizeof(AcpiSdtTable)); + if (getenv("V")) { + fputc('\n', stderr); + } + for (i = 0; i < data->tables->len; ++i) { + AcpiSdtTable exp_sdt; + gchar *aml_file = NULL; + const char *ext = data->variant ? data->variant : ""; + + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + + memset(&exp_sdt, 0, sizeof(exp_sdt)); + exp_sdt.header.signature = sdt->header.signature; + +try_again: + aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine, + (gchar *)&sdt->header.signature, ext); + if (getenv("V")) { + fprintf(stderr, "Looking for expected file '%s'\n", aml_file); + } + if (g_file_test(aml_file, G_FILE_TEST_EXISTS)) { + exp_sdt.aml_file = aml_file; + } else if (*ext != '\0') { + /* try fallback to generic (extension less) expected file */ + ext = ""; + g_free(aml_file); + goto try_again; + } + g_assert(exp_sdt.aml_file); + if (getenv("V")) { + fprintf(stderr, "Using expected file '%s'\n", aml_file); + } + ret = g_file_get_contents(aml_file, &exp_sdt.aml, + &exp_sdt.aml_len, &error); + g_assert(ret); + g_assert_no_error(error); + g_assert(exp_sdt.aml); + g_assert(exp_sdt.aml_len); + + g_array_append_val(exp_tables, exp_sdt); + } + + return exp_tables; +} + +/* test the list of tables in @data->tables against reference tables */ +static void test_acpi_asl(test_data *data) +{ + int i; + AcpiSdtTable *sdt, *exp_sdt; + test_data exp_data; + gboolean exp_err, err; + + memset(&exp_data, 0, sizeof(exp_data)); + exp_data.tables = load_expected_aml(data); + dump_aml_files(data, false); + for (i = 0; i < data->tables->len; ++i) { + GString *asl, *exp_asl; + + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + exp_sdt = &g_array_index(exp_data.tables, AcpiSdtTable, i); + + err = load_asl(data->tables, sdt); + asl = normalize_asl(sdt->asl); + + exp_err = load_asl(exp_data.tables, exp_sdt); + exp_asl = normalize_asl(exp_sdt->asl); + + /* TODO: check for warnings */ + g_assert(!err || exp_err); + + if (g_strcmp0(asl->str, exp_asl->str)) { + if (exp_err) { + fprintf(stderr, + "Warning! iasl couldn't parse the expected aml\n"); + } else { + uint32_t signature = cpu_to_le32(exp_sdt->header.signature); + sdt->tmp_files_retain = true; + exp_sdt->tmp_files_retain = true; + fprintf(stderr, + "acpi-test: Warning! %.4s mismatch. " + "Actual [asl:%s, aml:%s], Expected [asl:%s, aml:%s].\n", + (gchar *)&signature, + sdt->asl_file, sdt->aml_file, + exp_sdt->asl_file, exp_sdt->aml_file); + if (getenv("V")) { + const char *diff_cmd = getenv("DIFF"); + if (diff_cmd) { + int ret G_GNUC_UNUSED; + char *diff = g_strdup_printf("%s %s %s", diff_cmd, + exp_sdt->asl_file, sdt->asl_file); + ret = system(diff) ; + g_free(diff); + } else { + fprintf(stderr, "acpi-test: Warning. not showing " + "difference since no diff utility is specified. " + "Set 'DIFF' environment variable to a preferred " + "diff utility and run 'make V=1 check' again to " + "see ASL difference."); + } + } + } + } + g_string_free(asl, true); + g_string_free(exp_asl, true); + } + + free_test_data(&exp_data); +} + +static bool smbios_ep_table_ok(test_data *data) +{ + struct smbios_21_entry_point *ep_table = &data->smbios_ep_table; + uint32_t addr = data->smbios_ep_addr; + + ACPI_READ_ARRAY(data->qts, ep_table->anchor_string, addr); + if (memcmp(ep_table->anchor_string, "_SM_", 4)) { + return false; + } + ACPI_READ_FIELD(data->qts, ep_table->checksum, addr); + ACPI_READ_FIELD(data->qts, ep_table->length, addr); + ACPI_READ_FIELD(data->qts, ep_table->smbios_major_version, addr); + ACPI_READ_FIELD(data->qts, ep_table->smbios_minor_version, addr); + ACPI_READ_FIELD(data->qts, ep_table->max_structure_size, addr); + ACPI_READ_FIELD(data->qts, ep_table->entry_point_revision, addr); + ACPI_READ_ARRAY(data->qts, ep_table->formatted_area, addr); + ACPI_READ_ARRAY(data->qts, ep_table->intermediate_anchor_string, addr); + if (memcmp(ep_table->intermediate_anchor_string, "_DMI_", 5)) { + return false; + } + ACPI_READ_FIELD(data->qts, ep_table->intermediate_checksum, addr); + ACPI_READ_FIELD(data->qts, ep_table->structure_table_length, addr); + if (ep_table->structure_table_length == 0) { + return false; + } + ACPI_READ_FIELD(data->qts, ep_table->structure_table_address, addr); + ACPI_READ_FIELD(data->qts, ep_table->number_of_structures, addr); + if (ep_table->number_of_structures == 0) { + return false; + } + ACPI_READ_FIELD(data->qts, ep_table->smbios_bcd_revision, addr); + if (acpi_calc_checksum((uint8_t *)ep_table, sizeof *ep_table) || + acpi_calc_checksum((uint8_t *)ep_table + 0x10, + sizeof *ep_table - 0x10)) { + return false; + } + return true; +} + +static void test_smbios_entry_point(test_data *data) +{ + uint32_t off; + + /* find smbios entry point structure */ + for (off = 0xf0000; off < 0x100000; off += 0x10) { + uint8_t sig[] = "_SM_"; + int i; + + for (i = 0; i < sizeof sig - 1; ++i) { + sig[i] = qtest_readb(data->qts, off + i); + } + + if (!memcmp(sig, "_SM_", sizeof sig)) { + /* signature match, but is this a valid entry point? */ + data->smbios_ep_addr = off; + if (smbios_ep_table_ok(data)) { + break; + } + } + } + + g_assert_cmphex(off, <, 0x100000); +} + +static inline bool smbios_single_instance(uint8_t type) +{ + switch (type) { + case 0: + case 1: + case 2: + case 3: + case 16: + case 32: + case 127: + return true; + default: + return false; + } +} + +static void test_smbios_structs(test_data *data) +{ + DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 }; + struct smbios_21_entry_point *ep_table = &data->smbios_ep_table; + uint32_t addr = le32_to_cpu(ep_table->structure_table_address); + int i, len, max_len = 0; + uint8_t type, prv, crt; + + /* walk the smbios tables */ + for (i = 0; i < le16_to_cpu(ep_table->number_of_structures); i++) { + + /* grab type and formatted area length from struct header */ + type = qtest_readb(data->qts, addr); + g_assert_cmpuint(type, <=, SMBIOS_MAX_TYPE); + len = qtest_readb(data->qts, addr + 1); + + /* single-instance structs must not have been encountered before */ + if (smbios_single_instance(type)) { + g_assert(!test_bit(type, struct_bitmap)); + } + set_bit(type, struct_bitmap); + + /* seek to end of unformatted string area of this struct ("\0\0") */ + prv = crt = 1; + while (prv || crt) { + prv = crt; + crt = qtest_readb(data->qts, addr + len); + len++; + } + + /* keep track of max. struct size */ + if (max_len < len) { + max_len = len; + g_assert_cmpuint(max_len, <=, ep_table->max_structure_size); + } + + /* start of next structure */ + addr += len; + } + + /* total table length and max struct size must match entry point values */ + g_assert_cmpuint(le16_to_cpu(ep_table->structure_table_length), ==, + addr - le32_to_cpu(ep_table->structure_table_address)); + g_assert_cmpuint(le16_to_cpu(ep_table->max_structure_size), ==, max_len); + + /* required struct types must all be present */ + for (i = 0; i < data->required_struct_types_len; i++) { + g_assert(test_bit(data->required_struct_types[i], struct_bitmap)); + } +} + +static void test_acpi_one(const char *params, test_data *data) +{ + char *args; + + /* Disable kernel irqchip to be able to override apic irq0. */ + args = g_strdup_printf("-machine %s,accel=%s,kernel-irqchip=off " + "-net none -display none %s " + "-drive id=hd0,if=none,file=%s,format=raw " + "-device ide-hd,drive=hd0 ", + data->machine, "kvm:tcg", + params ? params : "", disk); + + data->qts = qtest_init(args); + + boot_sector_test(data->qts); + + data->tables = g_array_new(false, true, sizeof(AcpiSdtTable)); + test_acpi_rsdp_address(data); + test_acpi_rsdp_table(data); + test_acpi_rsdt_table(data); + fadt_fetch_facs_and_dsdt_ptrs(data); + test_acpi_facs_table(data); + test_acpi_dsdt_table(data); + fetch_rsdt_referenced_tables(data); + + sanitize_fadt_ptrs(data); + + if (iasl) { + if (getenv(ACPI_REBUILD_EXPECTED_AML)) { + dump_aml_files(data, true); + } else { + test_acpi_asl(data); + } + } + + test_smbios_entry_point(data); + test_smbios_structs(data); + + assert(!global_qtest); + qtest_quit(data->qts); + g_free(args); +} + +static uint8_t base_required_struct_types[] = { + 0, 1, 3, 4, 16, 17, 19, 32, 127 +}; + +static void test_acpi_piix4_tcg(void) +{ + test_data data; + + /* Supplying -machine accel argument overrides the default (qtest). + * This is to make guest actually run. + */ + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one(NULL, &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_bridge(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".bridge"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-device pci-bridge,chassis_nr=1", &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one(NULL, &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_bridge(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".bridge"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-device pci-bridge,chassis_nr=1", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_mmio64(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".mmio64", + .required_struct_types = base_required_struct_types, + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types) + }; + + test_acpi_one("-m 128M,slots=1,maxmem=2G " + "-device pci-testdev,membar=2G", + &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_cphp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".cphp"; + test_acpi_one("-smp 2,cores=3,sockets=2,maxcpus=6" + " -numa node -numa node" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_cphp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".cphp"; + test_acpi_one(" -smp 2,cores=3,sockets=2,maxcpus=6" + " -numa node -numa node" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static uint8_t ipmi_required_struct_types[] = { + 0, 1, 3, 4, 16, 17, 19, 32, 38, 127 +}; + +static void test_acpi_q35_tcg_ipmi(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".ipmibt"; + data.required_struct_types = ipmi_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types); + test_acpi_one("-device ipmi-bmc-sim,id=bmc0" + " -device isa-ipmi-bt,bmc=bmc0", + &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_ipmi(void) +{ + test_data data; + + /* Supplying -machine accel argument overrides the default (qtest). + * This is to make guest actually run. + */ + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".ipmikcs"; + data.required_struct_types = ipmi_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types); + test_acpi_one("-device ipmi-bmc-sim,id=bmc0" + " -device isa-ipmi-kcs,irq=0,bmc=bmc0", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_memhp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".memhp"; + test_acpi_one(" -m 128,slots=3,maxmem=1G" + " -numa node -numa node" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_memhp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".memhp"; + test_acpi_one(" -m 128,slots=3,maxmem=1G" + " -numa node -numa node" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_numamem(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".numamem"; + test_acpi_one(" -numa node -numa node,mem=128", &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_numamem(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".numamem"; + test_acpi_one(" -numa node -numa node,mem=128", &data); + free_test_data(&data); +} + +static void test_acpi_tcg_dimm_pxm(const char *machine) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = machine; + data.variant = ".dimmpxm"; + test_acpi_one(" -machine nvdimm=on,nvdimm-persistence=cpu" + " -smp 4,sockets=4" + " -m 128M,slots=3,maxmem=1G" + " -numa node,mem=32M,nodeid=0" + " -numa node,mem=32M,nodeid=1" + " -numa node,mem=32M,nodeid=2" + " -numa node,mem=32M,nodeid=3" + " -numa cpu,node-id=0,socket-id=0" + " -numa cpu,node-id=1,socket-id=1" + " -numa cpu,node-id=2,socket-id=2" + " -numa cpu,node-id=3,socket-id=3" + " -object memory-backend-ram,id=ram0,size=128M" + " -object memory-backend-ram,id=nvm0,size=128M" + " -device pc-dimm,id=dimm0,memdev=ram0,node=1" + " -device nvdimm,id=dimm1,memdev=nvm0,node=2", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_dimm_pxm(void) +{ + test_acpi_tcg_dimm_pxm(MACHINE_Q35); +} + +static void test_acpi_piix4_tcg_dimm_pxm(void) +{ + test_acpi_tcg_dimm_pxm(MACHINE_PC); +} + +int main(int argc, char *argv[]) +{ + const char *arch = qtest_get_arch(); + int ret; + + ret = boot_sector_init(disk); + if(ret) + return ret; + + g_test_init(&argc, &argv, NULL); + + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { + qtest_add_func("acpi/piix4", test_acpi_piix4_tcg); + qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge); + qtest_add_func("acpi/q35", test_acpi_q35_tcg); + qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge); + qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64); + qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi); + qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi); + qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp); + qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_tcg_cphp); + qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_tcg_memhp); + qtest_add_func("acpi/q35/memhp", test_acpi_q35_tcg_memhp); + qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_tcg_numamem); + qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem); + qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm); + qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm); + } + ret = g_test_run(); + boot_sector_cleanup(disk); + return ret; +} diff --git a/tests/data/acpi/diff-aml.sh b/tests/data/acpi/diff-aml.sh new file mode 100644 index 0000000000..e69de29bb2 --- /dev/null +++ b/tests/data/acpi/diff-aml.sh diff --git a/tests/data/acpi/disassemle-aml.py b/tests/data/acpi/disassemle-aml.py new file mode 100644 index 0000000000..0398fada63 --- /dev/null +++ b/tests/data/acpi/disassemle-aml.py @@ -0,0 +1,21 @@ +#!/usr/bin/python + +import os, re +root = "tests/data/acpi" +for machine in os.listdir(root): + machine_root = os.path.join(root, machine) + if not os.path.isdir(machine_root): + continue + files = os.listdir(machine_root): + for file in files: + if file.endswith(".dsl"): + continue + extension_prefix = "^[^.]*\." + if re.match(extension_prefix, file): + variant = re.sub(extension_prefix, "", file) + + +for dirpath, dirnames, filenames in os.walk("tests/data/acpi"): + for file in files: + if file.endswith(".txt"): + print(os.path.join(root, file)) diff --git a/tests/data/acpi/microvm/APIC.dsl b/tests/data/acpi/microvm/APIC.dsl new file mode 100644 index 0000000000..02f56dce43 --- /dev/null +++ b/tests/data/acpi/microvm/APIC.dsl @@ -0,0 +1,56 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/microvm/APIC, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000046 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : D7 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 04 [Local APIC NMI] +[041h 0065 1] Length : 06 +[042h 0066 1] Processor ID : FF +[043h 0067 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[045h 0069 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 70 (0x46) + + 0000: 41 50 49 43 46 00 00 00 01 D7 42 4F 43 48 53 20 // APICF.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 04 06 FF 00 00 01 // ...... diff --git a/tests/data/acpi/microvm/DSDT.dsl b/tests/data/acpi/microvm/DSDT.dsl new file mode 100644 index 0000000000..fd53f08128 --- /dev/null +++ b/tests/data/acpi/microvm/DSDT.dsl @@ -0,0 +1,121 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/microvm/DSDT, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000016D (365) + * Revision 0x02 + * Checksum 0x62 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (_SB) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000009, + } + }) + OperationRegion (EREG, SystemMemory, 0xFEA00000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xFEB00E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000017, + } + }) + } + } + + Scope (\) + { + Name (_S5, Package (0x04) // _S5_: S5 System State + { + 0x05, + Zero, + Zero, + Zero + }) + } +} + diff --git a/tests/data/acpi/microvm/FACP.dsl b/tests/data/acpi/microvm/FACP.dsl new file mode 100644 index 0000000000..4cf780caec --- /dev/null +++ b/tests/data/acpi/microvm/FACP.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/microvm/FACP, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : 7E +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100400 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 00000000FEA00202 + +[080h 0128 1] Value to cause reset : 42 +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 08 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 00000000FEA00200 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 08 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 00000000FEA00201 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 7E 42 4F 43 48 53 20 // FACP.....~BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 04 10 00 00 08 00 00 02 02 A0 FE 00 00 00 00 // ................ + 0080: 42 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // B............... + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 08 00 00 00 02 A0 FE 00 00 00 00 // ................ + 0100: 00 08 00 00 01 02 A0 FE 00 00 00 00 // ............ diff --git a/tests/data/acpi/pc/APIC.acpihmat.dsl b/tests/data/acpi/pc/APIC.acpihmat.dsl new file mode 100644 index 0000000000..15155cac55 --- /dev/null +++ b/tests/data/acpi/pc/APIC.acpihmat.dsl @@ -0,0 +1,112 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000080 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : DA +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 01 [I/O APIC] +[03Dh 0061 1] Length : 0C +[03Eh 0062 1] I/O Apic ID : 00 +[03Fh 0063 1] Reserved : 00 +[040h 0064 4] Address : FEC00000 +[044h 0068 4] Interrupt : 00000000 + +[048h 0072 1] Subtable Type : 02 [Interrupt Source Override] +[049h 0073 1] Length : 0A +[04Ah 0074 1] Bus : 00 +[04Bh 0075 1] Source : 00 +[04Ch 0076 4] Interrupt : 00000002 +[050h 0080 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[052h 0082 1] Subtable Type : 02 [Interrupt Source Override] +[053h 0083 1] Length : 0A +[054h 0084 1] Bus : 00 +[055h 0085 1] Source : 05 +[056h 0086 4] Interrupt : 00000005 +[05Ah 0090 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Ch 0092 1] Subtable Type : 02 [Interrupt Source Override] +[05Dh 0093 1] Length : 0A +[05Eh 0094 1] Bus : 00 +[05Fh 0095 1] Source : 09 +[060h 0096 4] Interrupt : 00000009 +[064h 0100 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[066h 0102 1] Subtable Type : 02 [Interrupt Source Override] +[067h 0103 1] Length : 0A +[068h 0104 1] Bus : 00 +[069h 0105 1] Source : 0A +[06Ah 0106 4] Interrupt : 0000000A +[06Eh 0110 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[070h 0112 1] Subtable Type : 02 [Interrupt Source Override] +[071h 0113 1] Length : 0A +[072h 0114 1] Bus : 00 +[073h 0115 1] Source : 0B +[074h 0116 4] Interrupt : 0000000B +[078h 0120 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[07Ah 0122 1] Subtable Type : 04 [Local APIC NMI] +[07Bh 0123 1] Length : 06 +[07Ch 0124 1] Processor ID : FF +[07Dh 0125 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[07Fh 0127 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 128 (0x80) + + 0000: 41 50 49 43 80 00 00 00 01 DA 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 01 0C 00 00 // ................ + 0040: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0050: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0060: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0070: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/pc/APIC.bridge b/tests/data/acpi/pc/APIC.bridge new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/pc/APIC.bridge Binary files differdiff --git a/tests/data/acpi/pc/APIC.bridge.dsl b/tests/data/acpi/pc/APIC.bridge.dsl new file mode 100644 index 0000000000..2828370063 --- /dev/null +++ b/tests/data/acpi/pc/APIC.bridge.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.cphp.dsl b/tests/data/acpi/pc/APIC.cphp.dsl new file mode 100644 index 0000000000..b4b043229a --- /dev/null +++ b/tests/data/acpi/pc/APIC.cphp.dsl @@ -0,0 +1,146 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 7B +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC] +[03Dh 0061 1] Length : 08 +[03Eh 0062 1] Processor ID : 02 +[03Fh 0063 1] Local Apic ID : 02 +[040h 0064 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[044h 0068 1] Subtable Type : 00 [Processor Local APIC] +[045h 0069 1] Length : 08 +[046h 0070 1] Processor ID : 03 +[047h 0071 1] Local Apic ID : 04 +[048h 0072 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[04Ch 0076 1] Subtable Type : 00 [Processor Local APIC] +[04Dh 0077 1] Length : 08 +[04Eh 0078 1] Processor ID : 04 +[04Fh 0079 1] Local Apic ID : 05 +[050h 0080 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[054h 0084 1] Subtable Type : 00 [Processor Local APIC] +[055h 0085 1] Length : 08 +[056h 0086 1] Processor ID : 05 +[057h 0087 1] Local Apic ID : 06 +[058h 0088 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[05Ch 0092 1] Subtable Type : 01 [I/O APIC] +[05Dh 0093 1] Length : 0C +[05Eh 0094 1] I/O Apic ID : 00 +[05Fh 0095 1] Reserved : 00 +[060h 0096 4] Address : FEC00000 +[064h 0100 4] Interrupt : 00000000 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 00 +[06Ch 0108 4] Interrupt : 00000002 +[070h 0112 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[072h 0114 1] Subtable Type : 02 [Interrupt Source Override] +[073h 0115 1] Length : 0A +[074h 0116 1] Bus : 00 +[075h 0117 1] Source : 05 +[076h 0118 4] Interrupt : 00000005 +[07Ah 0122 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[07Ch 0124 1] Subtable Type : 02 [Interrupt Source Override] +[07Dh 0125 1] Length : 0A +[07Eh 0126 1] Bus : 00 +[07Fh 0127 1] Source : 09 +[080h 0128 4] Interrupt : 00000009 +[084h 0132 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[086h 0134 1] Subtable Type : 02 [Interrupt Source Override] +[087h 0135 1] Length : 0A +[088h 0136 1] Bus : 00 +[089h 0137 1] Source : 0A +[08Ah 0138 4] Interrupt : 0000000A +[08Eh 0142 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[090h 0144 1] Subtable Type : 02 [Interrupt Source Override] +[091h 0145 1] Length : 0A +[092h 0146 1] Bus : 00 +[093h 0147 1] Source : 0B +[094h 0148 4] Interrupt : 0000000B +[098h 0152 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[09Ah 0154 1] Subtable Type : 04 [Local APIC NMI] +[09Bh 0155 1] Length : 06 +[09Ch 0156 1] Processor ID : FF +[09Dh 0157 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[09Fh 0159 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 160 (0xA0) + + 0000: 41 50 49 43 A0 00 00 00 01 7B 42 4F 43 48 53 20 // APIC.....{BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................ + 0040: 00 00 00 00 00 08 03 04 00 00 00 00 00 08 04 05 // ................ + 0050: 00 00 00 00 00 08 05 06 00 00 00 00 01 0C 00 00 // ................ + 0060: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0070: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0080: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0090: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/pc/APIC.dimmpxm.dsl b/tests/data/acpi/pc/APIC.dimmpxm.dsl new file mode 100644 index 0000000000..adabdcc603 --- /dev/null +++ b/tests/data/acpi/pc/APIC.dimmpxm.dsl @@ -0,0 +1,129 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000090 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : AE +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC] +[03Dh 0061 1] Length : 08 +[03Eh 0062 1] Processor ID : 02 +[03Fh 0063 1] Local Apic ID : 02 +[040h 0064 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[044h 0068 1] Subtable Type : 00 [Processor Local APIC] +[045h 0069 1] Length : 08 +[046h 0070 1] Processor ID : 03 +[047h 0071 1] Local Apic ID : 03 +[048h 0072 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[04Ch 0076 1] Subtable Type : 01 [I/O APIC] +[04Dh 0077 1] Length : 0C +[04Eh 0078 1] I/O Apic ID : 00 +[04Fh 0079 1] Reserved : 00 +[050h 0080 4] Address : FEC00000 +[054h 0084 4] Interrupt : 00000000 + +[058h 0088 1] Subtable Type : 02 [Interrupt Source Override] +[059h 0089 1] Length : 0A +[05Ah 0090 1] Bus : 00 +[05Bh 0091 1] Source : 00 +[05Ch 0092 4] Interrupt : 00000002 +[060h 0096 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[062h 0098 1] Subtable Type : 02 [Interrupt Source Override] +[063h 0099 1] Length : 0A +[064h 0100 1] Bus : 00 +[065h 0101 1] Source : 05 +[066h 0102 4] Interrupt : 00000005 +[06Ah 0106 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[06Ch 0108 1] Subtable Type : 02 [Interrupt Source Override] +[06Dh 0109 1] Length : 0A +[06Eh 0110 1] Bus : 00 +[06Fh 0111 1] Source : 09 +[070h 0112 4] Interrupt : 00000009 +[074h 0116 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[076h 0118 1] Subtable Type : 02 [Interrupt Source Override] +[077h 0119 1] Length : 0A +[078h 0120 1] Bus : 00 +[079h 0121 1] Source : 0A +[07Ah 0122 4] Interrupt : 0000000A +[07Eh 0126 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[080h 0128 1] Subtable Type : 02 [Interrupt Source Override] +[081h 0129 1] Length : 0A +[082h 0130 1] Bus : 00 +[083h 0131 1] Source : 0B +[084h 0132 4] Interrupt : 0000000B +[088h 0136 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[08Ah 0138 1] Subtable Type : 04 [Local APIC NMI] +[08Bh 0139 1] Length : 06 +[08Ch 0140 1] Processor ID : FF +[08Dh 0141 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[08Fh 0143 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 144 (0x90) + + 0000: 41 50 49 43 90 00 00 00 01 AE 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................ + 0040: 01 00 00 00 00 08 03 03 01 00 00 00 01 0C 00 00 // ................ + 0050: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0060: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0070: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0080: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/pc/APIC.dsl b/tests/data/acpi/pc/APIC.dsl new file mode 100644 index 0000000000..d9516fc1f2 --- /dev/null +++ b/tests/data/acpi/pc/APIC.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.roothp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.hpbridge b/tests/data/acpi/pc/APIC.hpbridge new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/pc/APIC.hpbridge Binary files differdiff --git a/tests/data/acpi/pc/APIC.ipmikcs b/tests/data/acpi/pc/APIC.ipmikcs new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/pc/APIC.ipmikcs Binary files differdiff --git a/tests/data/acpi/pc/APIC.ipmikcs.dsl b/tests/data/acpi/pc/APIC.ipmikcs.dsl new file mode 100644 index 0000000000..28198bed68 --- /dev/null +++ b/tests/data/acpi/pc/APIC.ipmikcs.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.ipmikcs, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.memhp b/tests/data/acpi/pc/APIC.memhp new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/pc/APIC.memhp Binary files differdiff --git a/tests/data/acpi/pc/APIC.memhp.dsl b/tests/data/acpi/pc/APIC.memhp.dsl new file mode 100644 index 0000000000..b8449c0bde --- /dev/null +++ b/tests/data/acpi/pc/APIC.memhp.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.numamem b/tests/data/acpi/pc/APIC.numamem new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/pc/APIC.numamem Binary files differdiff --git a/tests/data/acpi/pc/APIC.numamem.dsl b/tests/data/acpi/pc/APIC.numamem.dsl new file mode 100644 index 0000000000..d75e4283d1 --- /dev/null +++ b/tests/data/acpi/pc/APIC.numamem.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/APIC.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/pc/APIC.roothp b/tests/data/acpi/pc/APIC.roothp new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/pc/APIC.roothp Binary files differdiff --git a/tests/data/acpi/pc/DSDT b/tests/data/acpi/pc/DSDT index b121bb5bc1..4ca46e5a2b 100644 --- a/tests/data/acpi/pc/DSDT +++ b/tests/data/acpi/pc/DSDT Binary files differdiff --git a/tests/data/acpi/pc/DSDT.acpihmat b/tests/data/acpi/pc/DSDT.acpihmat index b0dbb943f4..35a74bce8c 100644 --- a/tests/data/acpi/pc/DSDT.acpihmat +++ b/tests/data/acpi/pc/DSDT.acpihmat Binary files differdiff --git a/tests/data/acpi/pc/DSDT.acpihmat.dsl b/tests/data/acpi/pc/DSDT.acpihmat.dsl new file mode 100644 index 0000000000..b2a4b1bd7f --- /dev/null +++ b/tests/data/acpi/pc/DSDT.acpihmat.dsl @@ -0,0 +1,1619 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.acpihmat, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001872 (6258) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x8E + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x02) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x00000001C0000000, // Range Minimum + 0x000000023FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.bridge b/tests/data/acpi/pc/DSDT.bridge index 7b6c7a4787..803d7a8e83 100644 --- a/tests/data/acpi/pc/DSDT.bridge +++ b/tests/data/acpi/pc/DSDT.bridge Binary files differdiff --git a/tests/data/acpi/pc/DSDT.bridge.dsl b/tests/data/acpi/pc/DSDT.bridge.dsl new file mode 100644 index 0000000000..3311b57ecb --- /dev/null +++ b/tests/data/acpi/pc/DSDT.bridge.dsl @@ -0,0 +1,1800 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.bridge, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001A89 (6793) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x09 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_ADR, 0x00030000) // _ADR: Address + Name (BSEL, One) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S08) + { + Name (_SUN, One) // _SUN: Slot User Number + Name (_ADR, 0x00010000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S10) + { + Name (_SUN, 0x02) // _SUN: Slot User Number + Name (_ADR, 0x00020000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } + + If ((Arg0 & 0x02)) + { + Notify (S08, Arg1) + } + + If ((Arg0 & 0x04)) + { + Notify (S10, Arg1) + } + + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = One + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + ^S18.PCNT () + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.cphp b/tests/data/acpi/pc/DSDT.cphp index c0e8aa5b32..8bab2f5064 100644 --- a/tests/data/acpi/pc/DSDT.cphp +++ b/tests/data/acpi/pc/DSDT.cphp Binary files differdiff --git a/tests/data/acpi/pc/DSDT.cphp.dsl b/tests/data/acpi/pc/DSDT.cphp.dsl new file mode 100644 index 0000000000..22ed37d7dc --- /dev/null +++ b/tests/data/acpi/pc/DSDT.cphp.dsl @@ -0,0 +1,1466 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.cphp, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001515 (5397) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x39 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (C002, Arg1) + } + + If ((Arg0 == 0x03)) + { + Notify (C003, Arg1) + } + + If ((Arg0 == 0x04)) + { + Notify (C004, Arg1) + } + + If ((Arg0 == 0x05)) + { + Notify (C005, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C002, 0x02, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x02)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x02) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x02, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C003, 0x03, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x03)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x03, 0x04, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x03) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x03, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C004, 0x04, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x04)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x04, 0x05, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x04) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x04, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C005, 0x05, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x05)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x05, 0x06, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x05) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x05, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.dimmpxm b/tests/data/acpi/pc/DSDT.dimmpxm index 1649953b6c..e015b4594c 100644 --- a/tests/data/acpi/pc/DSDT.dimmpxm +++ b/tests/data/acpi/pc/DSDT.dimmpxm Binary files differdiff --git a/tests/data/acpi/pc/DSDT.dimmpxm.dsl b/tests/data/acpi/pc/DSDT.dimmpxm.dsl new file mode 100644 index 0000000000..798056147b --- /dev/null +++ b/tests/data/acpi/pc/DSDT.dimmpxm.dsl @@ -0,0 +1,1719 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000019BB (6587) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x21 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + External (_SB_.NVDR, UnknownObj) + + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (C002, Arg1) + } + + If ((Arg0 == 0x03)) + { + Notify (C003, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C002, 0x02, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x02)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x02) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x02, Arg0, Arg1, Arg2) + } + + Name (_PXM, 0x02) // _PXM: Device Proximity + } + + Processor (C003, 0x03, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x03)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x03) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x03, Arg0, Arg1, Arg2) + } + + Name (_PXM, 0x03) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + + Method (_E04, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.NVDR, 0x80) // Status Change + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x000000027FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.dsl b/tests/data/acpi/pc/DSDT.dsl new file mode 100644 index 0000000000..da2b413efc --- /dev/null +++ b/tests/data/acpi/pc/DSDT.dsl @@ -0,0 +1,1407 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.roothp, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001488 (5256) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xF2 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Name (CNEW, Package (0xFF){}) + Local3 = Zero + Local4 = One + While ((Local4 == One)) + { + Local4 = Zero + Local0 = One + Local1 = Zero + While (((Local0 == One) && (Local3 < One))) + { + Local0 = Zero + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CDAT < Local3)) + { + Break + } + + If ((Local1 == 0xFF)) + { + Local4 = One + Break + } + + Local3 = \_SB.PCI0.PRES.CDAT + If ((\_SB.PCI0.PRES.CINS == One)) + { + CNEW [Local1] = Local3 + Local1++ + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (Local3, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + + Local3++ + } + + Local2 = Zero + While ((Local2 < Local1)) + { + Local3 = DerefOf (CNEW [Local2]) + CTFY (Local3, One) + Debug = Local3 + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CINS = One + Local2++ + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_ADR, 0x00030000) // _ADR: Address + Name (BSEL, Zero) + Device (S00) + { + Name (_SUN, Zero) // _SUN: Slot User Number + Name (_ADR, Zero) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S08) + { + Name (_SUN, One) // _SUN: Slot User Number + Name (_ADR, 0x00010000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S10) + { + Name (_SUN, 0x02) // _SUN: Slot User Number + Name (_ADR, 0x00020000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & One)) + { + Notify (S00, Arg1) + } + + If ((Arg0 & 0x02)) + { + Notify (S08, Arg1) + } + + If ((Arg0 & 0x04)) + { + Notify (S10, Arg1) + } + + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + + Method (PCNT, 0, NotSerialized) + { + ^S18.PCNT () + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.hpbridge b/tests/data/acpi/pc/DSDT.hpbridge new file mode 100644 index 0000000000..56032bcf1b --- /dev/null +++ b/tests/data/acpi/pc/DSDT.hpbridge Binary files differdiff --git a/tests/data/acpi/pc/DSDT.ipmikcs b/tests/data/acpi/pc/DSDT.ipmikcs index 92748d49dc..ca6630e39f 100644 --- a/tests/data/acpi/pc/DSDT.ipmikcs +++ b/tests/data/acpi/pc/DSDT.ipmikcs Binary files differdiff --git a/tests/data/acpi/pc/DSDT.ipmikcs.dsl b/tests/data/acpi/pc/DSDT.ipmikcs.dsl new file mode 100644 index 0000000000..2e4b524ab8 --- /dev/null +++ b/tests/data/acpi/pc/DSDT.ipmikcs.dsl @@ -0,0 +1,1337 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.ipmikcs, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000138E (5006) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x54 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (MI1) + { + Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID + Name (_STR, "ipmi_kcs") // _STR: Description String + Name (_UID, One) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CA2, // Range Minimum + 0x0CA3, // Range Maximum + 0x01, // Alignment + 0x02, // Length + ) + }) + Name (_IFT, One) // _IFT: IPMI Interface Type + Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision + } + + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.memhp b/tests/data/acpi/pc/DSDT.memhp index 4026772906..43f4e114e2 100644 --- a/tests/data/acpi/pc/DSDT.memhp +++ b/tests/data/acpi/pc/DSDT.memhp Binary files differdiff --git a/tests/data/acpi/pc/DSDT.memhp.dsl b/tests/data/acpi/pc/DSDT.memhp.dsl new file mode 100644 index 0000000000..299315051e --- /dev/null +++ b/tests/data/acpi/pc/DSDT.memhp.dsl @@ -0,0 +1,1625 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.memhp, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001895 (6293) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xB2 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x000000027FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.numamem b/tests/data/acpi/pc/DSDT.numamem index 4d9ba337a8..ba8f7e6c33 100644 --- a/tests/data/acpi/pc/DSDT.numamem +++ b/tests/data/acpi/pc/DSDT.numamem Binary files differdiff --git a/tests/data/acpi/pc/DSDT.numamem.dsl b/tests/data/acpi/pc/DSDT.numamem.dsl new file mode 100644 index 0000000000..3d08447f1e --- /dev/null +++ b/tests/data/acpi/pc/DSDT.numamem.dsl @@ -0,0 +1,1321 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/DSDT.numamem, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000134C (4940) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x6A + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A03") /* PCI Bus */) // _HID: Hardware ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x00010000) // _ADR: Address + OperationRegion (P40C, PCI_Config, 0x60, 0x04) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (FDC0) + { + Name (_HID, EisaId ("PNP0700")) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F2, // Range Minimum + 0x03F2, // Range Maximum + 0x00, // Alignment + 0x04, // Length + ) + IO (Decode16, + 0x03F7, // Range Minimum + 0x03F7, // Range Maximum + 0x00, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {6} + DMA (Compatibility, NotBusMaster, Transfer8, ) + {2} + }) + Device (FLPA) + { + Name (_ADR, Zero) // _ADR: Address + Name (_FDI, Package (0x10) // _FDI: Floppy Drive Information + { + Zero, + 0x05, + 0x4F, + 0x30, + One, + 0xAF, + 0x02, + 0x25, + 0x02, + 0x12, + 0x1B, + 0xFF, + 0x6C, + 0xF6, + 0x0F, + 0x08 + }) + } + + Name (_FDE, Buffer (0x14) // _FDE: Floppy Disk Enumerate + { + /* 0000 */ 0x01, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0008 */ 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, // ........ + /* 0010 */ 0x02, 0x00, 0x00, 0x00 // .... + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Scope (_SB.PCI0) + { + OperationRegion (PCST, SystemIO, 0xAE00, 0x08) + Field (PCST, DWordAcc, NoLock, WriteAsZeros) + { + PCIU, 32, + PCID, 32 + } + + OperationRegion (SEJ, SystemIO, 0xAE08, 0x04) + Field (SEJ, DWordAcc, NoLock, WriteAsZeros) + { + B0EJ, 32 + } + + OperationRegion (BNMR, SystemIO, 0xAE10, 0x04) + Field (BNMR, DWordAcc, NoLock, WriteAsZeros) + { + BNUM, 32 + } + + Mutex (BLCK, 0x00) + Method (PCEJ, 2, NotSerialized) + { + Acquire (BLCK, 0xFFFF) + BNUM = Arg0 + B0EJ = (One << Arg1) + Release (BLCK) + Return (Zero) + } + } + + Scope (_SB) + { + Scope (PCI0) + { + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + Local0 = Package (0x80){} + Local1 = Zero + While ((Local1 < 0x80)) + { + Local2 = (Local1 >> 0x02) + Local3 = ((Local1 + Local2) & 0x03) + If ((Local3 == Zero)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKD, + Zero + } + } + + If ((Local3 == One)) + { + If ((Local1 == 0x04)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKS, + Zero + } + } + Else + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKA, + Zero + } + } + } + + If ((Local3 == 0x02)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKB, + Zero + } + } + + If ((Local3 == 0x03)) + { + Local4 = Package (0x04) + { + Zero, + Zero, + LNKC, + Zero + } + } + + Local4 [Zero] = ((Local2 << 0x10) | 0xFFFF) + Local4 [One] = (Local1 & 0x03) + Local0 [Local1] = Local4 + Local1++ + } + + Return (Local0) + } + } + + Field (PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) + { + PRQ0, 8, + PRQ1, 8, + PRQ2, 8, + PRQ3, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + If ((Arg0 < 0x80)) + { + PRRI = Arg0 + } + + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ0)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ0 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ0)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ0 = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ1)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ1 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ1)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ1 = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ2)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ2 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ2)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ2 = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQ3)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQ3 |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQ3)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQ3 = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKS) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000009, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (0x0B) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (_PRS) /* \_SB_.LNKS._PRS */ + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAF00, // Range Minimum + 0xAF00, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0xAF00, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E01, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Acquire (\_SB.PCI0.BLCK, 0xFFFF) + \_SB.PCI0.PCNT () + Release (\_SB.PCI0.BLCK) + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xF6C00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x000000017FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000080000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAFE0, // Range Minimum + 0xAFE0, // Range Maximum + 0x01, // Alignment + 0x04, // Length + ) + }) + } + + Device (PHPR) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "PCI Hotplug resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0xAE00, // Range Minimum + 0xAE00, // Range Maximum + 0x01, // Alignment + 0x14, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Name (BSEL, Zero) + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S18) + { + Name (_SUN, 0x03) // _SUN: Slot User Number + Name (_ADR, 0x00030000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S20) + { + Name (_SUN, 0x04) // _SUN: Slot User Number + Name (_ADR, 0x00040000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S28) + { + Name (_SUN, 0x05) // _SUN: Slot User Number + Name (_ADR, 0x00050000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S30) + { + Name (_SUN, 0x06) // _SUN: Slot User Number + Name (_ADR, 0x00060000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S38) + { + Name (_SUN, 0x07) // _SUN: Slot User Number + Name (_ADR, 0x00070000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S40) + { + Name (_SUN, 0x08) // _SUN: Slot User Number + Name (_ADR, 0x00080000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S48) + { + Name (_SUN, 0x09) // _SUN: Slot User Number + Name (_ADR, 0x00090000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S50) + { + Name (_SUN, 0x0A) // _SUN: Slot User Number + Name (_ADR, 0x000A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S58) + { + Name (_SUN, 0x0B) // _SUN: Slot User Number + Name (_ADR, 0x000B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S60) + { + Name (_SUN, 0x0C) // _SUN: Slot User Number + Name (_ADR, 0x000C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S68) + { + Name (_SUN, 0x0D) // _SUN: Slot User Number + Name (_ADR, 0x000D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S70) + { + Name (_SUN, 0x0E) // _SUN: Slot User Number + Name (_ADR, 0x000E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S78) + { + Name (_SUN, 0x0F) // _SUN: Slot User Number + Name (_ADR, 0x000F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S80) + { + Name (_SUN, 0x10) // _SUN: Slot User Number + Name (_ADR, 0x00100000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S88) + { + Name (_SUN, 0x11) // _SUN: Slot User Number + Name (_ADR, 0x00110000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S90) + { + Name (_SUN, 0x12) // _SUN: Slot User Number + Name (_ADR, 0x00120000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (S98) + { + Name (_SUN, 0x13) // _SUN: Slot User Number + Name (_ADR, 0x00130000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA0) + { + Name (_SUN, 0x14) // _SUN: Slot User Number + Name (_ADR, 0x00140000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SA8) + { + Name (_SUN, 0x15) // _SUN: Slot User Number + Name (_ADR, 0x00150000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB0) + { + Name (_SUN, 0x16) // _SUN: Slot User Number + Name (_ADR, 0x00160000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SB8) + { + Name (_SUN, 0x17) // _SUN: Slot User Number + Name (_ADR, 0x00170000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC0) + { + Name (_SUN, 0x18) // _SUN: Slot User Number + Name (_ADR, 0x00180000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SC8) + { + Name (_SUN, 0x19) // _SUN: Slot User Number + Name (_ADR, 0x00190000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD0) + { + Name (_SUN, 0x1A) // _SUN: Slot User Number + Name (_ADR, 0x001A0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SD8) + { + Name (_SUN, 0x1B) // _SUN: Slot User Number + Name (_ADR, 0x001B0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE0) + { + Name (_SUN, 0x1C) // _SUN: Slot User Number + Name (_ADR, 0x001C0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SE8) + { + Name (_SUN, 0x1D) // _SUN: Slot User Number + Name (_ADR, 0x001D0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF0) + { + Name (_SUN, 0x1E) // _SUN: Slot User Number + Name (_ADR, 0x001E0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Device (SF8) + { + Name (_SUN, 0x1F) // _SUN: Slot User Number + Name (_ADR, 0x001F0000) // _ADR: Address + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + PCEJ (BSEL, _SUN) + } + } + + Method (DVNT, 2, NotSerialized) + { + If ((Arg0 & 0x08)) + { + Notify (S18, Arg1) + } + + If ((Arg0 & 0x10)) + { + Notify (S20, Arg1) + } + + If ((Arg0 & 0x20)) + { + Notify (S28, Arg1) + } + + If ((Arg0 & 0x40)) + { + Notify (S30, Arg1) + } + + If ((Arg0 & 0x80)) + { + Notify (S38, Arg1) + } + + If ((Arg0 & 0x0100)) + { + Notify (S40, Arg1) + } + + If ((Arg0 & 0x0200)) + { + Notify (S48, Arg1) + } + + If ((Arg0 & 0x0400)) + { + Notify (S50, Arg1) + } + + If ((Arg0 & 0x0800)) + { + Notify (S58, Arg1) + } + + If ((Arg0 & 0x1000)) + { + Notify (S60, Arg1) + } + + If ((Arg0 & 0x2000)) + { + Notify (S68, Arg1) + } + + If ((Arg0 & 0x4000)) + { + Notify (S70, Arg1) + } + + If ((Arg0 & 0x8000)) + { + Notify (S78, Arg1) + } + + If ((Arg0 & 0x00010000)) + { + Notify (S80, Arg1) + } + + If ((Arg0 & 0x00020000)) + { + Notify (S88, Arg1) + } + + If ((Arg0 & 0x00040000)) + { + Notify (S90, Arg1) + } + + If ((Arg0 & 0x00080000)) + { + Notify (S98, Arg1) + } + + If ((Arg0 & 0x00100000)) + { + Notify (SA0, Arg1) + } + + If ((Arg0 & 0x00200000)) + { + Notify (SA8, Arg1) + } + + If ((Arg0 & 0x00400000)) + { + Notify (SB0, Arg1) + } + + If ((Arg0 & 0x00800000)) + { + Notify (SB8, Arg1) + } + + If ((Arg0 & 0x01000000)) + { + Notify (SC0, Arg1) + } + + If ((Arg0 & 0x02000000)) + { + Notify (SC8, Arg1) + } + + If ((Arg0 & 0x04000000)) + { + Notify (SD0, Arg1) + } + + If ((Arg0 & 0x08000000)) + { + Notify (SD8, Arg1) + } + + If ((Arg0 & 0x10000000)) + { + Notify (SE0, Arg1) + } + + If ((Arg0 & 0x20000000)) + { + Notify (SE8, Arg1) + } + + If ((Arg0 & 0x40000000)) + { + Notify (SF0, Arg1) + } + + If ((Arg0 & 0x80000000)) + { + Notify (SF8, Arg1) + } + } + + Method (PCNT, 0, NotSerialized) + { + BNUM = Zero + DVNT (PCIU, One) + DVNT (PCID, 0x03) + } + } + } +} + diff --git a/tests/data/acpi/pc/DSDT.roothp b/tests/data/acpi/pc/DSDT.roothp new file mode 100644 index 0000000000..18caa0765f --- /dev/null +++ b/tests/data/acpi/pc/DSDT.roothp Binary files differdiff --git a/tests/data/acpi/pc/FACP.acpihmat b/tests/data/acpi/pc/FACP.acpihmat new file mode 100644 index 0000000000..261ebdc5d1 --- /dev/null +++ b/tests/data/acpi/pc/FACP.acpihmat Binary files differdiff --git a/tests/data/acpi/pc/FACP.acpihmat.dsl b/tests/data/acpi/pc/FACP.acpihmat.dsl new file mode 100644 index 0000000000..226fd58ec9 --- /dev/null +++ b/tests/data/acpi/pc/FACP.acpihmat.dsl @@ -0,0 +1,99 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACP.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000074 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : F1 +[035h 0053 1] ACPI Disable Value : F0 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 0000AFE0 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 04 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000080A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +Raw Table Data: Length 116 (0x74) + + 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................ + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 80 00 00 // .... diff --git a/tests/data/acpi/pc/FACP.bridge b/tests/data/acpi/pc/FACP.bridge new file mode 100644 index 0000000000..261ebdc5d1 --- /dev/null +++ b/tests/data/acpi/pc/FACP.bridge Binary files differdiff --git a/tests/data/acpi/pc/FACP.bridge.dsl b/tests/data/acpi/pc/FACP.bridge.dsl new file mode 100644 index 0000000000..11b371812d --- /dev/null +++ b/tests/data/acpi/pc/FACP.bridge.dsl @@ -0,0 +1,99 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACP.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000074 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : F1 +[035h 0053 1] ACPI Disable Value : F0 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 0000AFE0 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 04 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000080A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +Raw Table Data: Length 116 (0x74) + + 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................ + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 80 00 00 // .... diff --git a/tests/data/acpi/pc/FACP.cphp b/tests/data/acpi/pc/FACP.cphp new file mode 100644 index 0000000000..261ebdc5d1 --- /dev/null +++ b/tests/data/acpi/pc/FACP.cphp Binary files differdiff --git a/tests/data/acpi/pc/FACP.cphp.dsl b/tests/data/acpi/pc/FACP.cphp.dsl new file mode 100644 index 0000000000..affffe9b64 --- /dev/null +++ b/tests/data/acpi/pc/FACP.cphp.dsl @@ -0,0 +1,99 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACP.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000074 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : F1 +[035h 0053 1] ACPI Disable Value : F0 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 0000AFE0 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 04 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000080A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +Raw Table Data: Length 116 (0x74) + + 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................ + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 80 00 00 // .... diff --git a/tests/data/acpi/pc/FACP.dimmpxm b/tests/data/acpi/pc/FACP.dimmpxm new file mode 100644 index 0000000000..261ebdc5d1 --- /dev/null +++ b/tests/data/acpi/pc/FACP.dimmpxm Binary files differdiff --git a/tests/data/acpi/pc/FACP.dimmpxm.dsl b/tests/data/acpi/pc/FACP.dimmpxm.dsl new file mode 100644 index 0000000000..fd5a5ef375 --- /dev/null +++ b/tests/data/acpi/pc/FACP.dimmpxm.dsl @@ -0,0 +1,99 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACP.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000074 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : F1 +[035h 0053 1] ACPI Disable Value : F0 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 0000AFE0 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 04 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000080A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +Raw Table Data: Length 116 (0x74) + + 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................ + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 80 00 00 // .... diff --git a/tests/data/acpi/pc/FACP.dsl b/tests/data/acpi/pc/FACP.dsl new file mode 100644 index 0000000000..c5e3718772 --- /dev/null +++ b/tests/data/acpi/pc/FACP.dsl @@ -0,0 +1,99 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACP.roothp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000074 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : F1 +[035h 0053 1] ACPI Disable Value : F0 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 0000AFE0 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 04 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000080A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +Raw Table Data: Length 116 (0x74) + + 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................ + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 80 00 00 // .... diff --git a/tests/data/acpi/pc/FACP.hpbridge b/tests/data/acpi/pc/FACP.hpbridge new file mode 100644 index 0000000000..261ebdc5d1 --- /dev/null +++ b/tests/data/acpi/pc/FACP.hpbridge Binary files differdiff --git a/tests/data/acpi/pc/FACP.ipmikcs b/tests/data/acpi/pc/FACP.ipmikcs new file mode 100644 index 0000000000..261ebdc5d1 --- /dev/null +++ b/tests/data/acpi/pc/FACP.ipmikcs Binary files differdiff --git a/tests/data/acpi/pc/FACP.ipmikcs.dsl b/tests/data/acpi/pc/FACP.ipmikcs.dsl new file mode 100644 index 0000000000..3f1dd018da --- /dev/null +++ b/tests/data/acpi/pc/FACP.ipmikcs.dsl @@ -0,0 +1,99 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACP.ipmikcs, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000074 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : F1 +[035h 0053 1] ACPI Disable Value : F0 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 0000AFE0 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 04 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000080A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +Raw Table Data: Length 116 (0x74) + + 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................ + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 80 00 00 // .... diff --git a/tests/data/acpi/pc/FACP.memhp b/tests/data/acpi/pc/FACP.memhp new file mode 100644 index 0000000000..261ebdc5d1 --- /dev/null +++ b/tests/data/acpi/pc/FACP.memhp Binary files differdiff --git a/tests/data/acpi/pc/FACP.memhp.dsl b/tests/data/acpi/pc/FACP.memhp.dsl new file mode 100644 index 0000000000..b2c466e989 --- /dev/null +++ b/tests/data/acpi/pc/FACP.memhp.dsl @@ -0,0 +1,99 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACP.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000074 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : F1 +[035h 0053 1] ACPI Disable Value : F0 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 0000AFE0 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 04 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000080A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +Raw Table Data: Length 116 (0x74) + + 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................ + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 80 00 00 // .... diff --git a/tests/data/acpi/pc/FACP.numamem b/tests/data/acpi/pc/FACP.numamem new file mode 100644 index 0000000000..261ebdc5d1 --- /dev/null +++ b/tests/data/acpi/pc/FACP.numamem Binary files differdiff --git a/tests/data/acpi/pc/FACP.numamem.dsl b/tests/data/acpi/pc/FACP.numamem.dsl new file mode 100644 index 0000000000..34ed95d536 --- /dev/null +++ b/tests/data/acpi/pc/FACP.numamem.dsl @@ -0,0 +1,99 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACP.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 00000074 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : F1 +[035h 0053 1] ACPI Disable Value : F0 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 0000AFE0 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 04 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000080A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +Raw Table Data: Length 116 (0x74) + + 0000: 46 41 43 50 74 00 00 00 01 A1 42 4F 43 48 53 20 // FACPt.....BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 F1 F0 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: E0 AF 00 00 00 00 00 00 04 02 00 04 04 00 00 00 // ................ + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 80 00 00 // .... diff --git a/tests/data/acpi/pc/FACP.roothp b/tests/data/acpi/pc/FACP.roothp new file mode 100644 index 0000000000..261ebdc5d1 --- /dev/null +++ b/tests/data/acpi/pc/FACP.roothp Binary files differdiff --git a/tests/data/acpi/pc/FACS.acpihmat b/tests/data/acpi/pc/FACS.acpihmat new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/pc/FACS.acpihmat Binary files differdiff --git a/tests/data/acpi/pc/FACS.acpihmat.dsl b/tests/data/acpi/pc/FACS.acpihmat.dsl new file mode 100644 index 0000000000..bff165ba4e --- /dev/null +++ b/tests/data/acpi/pc/FACS.acpihmat.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACS.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/FACS.bridge b/tests/data/acpi/pc/FACS.bridge new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/pc/FACS.bridge Binary files differdiff --git a/tests/data/acpi/pc/FACS.bridge.dsl b/tests/data/acpi/pc/FACS.bridge.dsl new file mode 100644 index 0000000000..981354f0f3 --- /dev/null +++ b/tests/data/acpi/pc/FACS.bridge.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACS.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/FACS.cphp b/tests/data/acpi/pc/FACS.cphp new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/pc/FACS.cphp Binary files differdiff --git a/tests/data/acpi/pc/FACS.cphp.dsl b/tests/data/acpi/pc/FACS.cphp.dsl new file mode 100644 index 0000000000..bb44e525b9 --- /dev/null +++ b/tests/data/acpi/pc/FACS.cphp.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACS.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/FACS.dimmpxm b/tests/data/acpi/pc/FACS.dimmpxm new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/pc/FACS.dimmpxm Binary files differdiff --git a/tests/data/acpi/pc/FACS.dimmpxm.dsl b/tests/data/acpi/pc/FACS.dimmpxm.dsl new file mode 100644 index 0000000000..e7586d3236 --- /dev/null +++ b/tests/data/acpi/pc/FACS.dimmpxm.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACS.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/FACS.dsl b/tests/data/acpi/pc/FACS.dsl new file mode 100644 index 0000000000..11d622cdf7 --- /dev/null +++ b/tests/data/acpi/pc/FACS.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACS.roothp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/FACS.hpbridge b/tests/data/acpi/pc/FACS.hpbridge new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/pc/FACS.hpbridge Binary files differdiff --git a/tests/data/acpi/pc/FACS.ipmikcs b/tests/data/acpi/pc/FACS.ipmikcs new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/pc/FACS.ipmikcs Binary files differdiff --git a/tests/data/acpi/pc/FACS.ipmikcs.dsl b/tests/data/acpi/pc/FACS.ipmikcs.dsl new file mode 100644 index 0000000000..f4b7c9718c --- /dev/null +++ b/tests/data/acpi/pc/FACS.ipmikcs.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACS.ipmikcs, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/FACS.memhp b/tests/data/acpi/pc/FACS.memhp new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/pc/FACS.memhp Binary files differdiff --git a/tests/data/acpi/pc/FACS.memhp.dsl b/tests/data/acpi/pc/FACS.memhp.dsl new file mode 100644 index 0000000000..da2e230a62 --- /dev/null +++ b/tests/data/acpi/pc/FACS.memhp.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACS.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/FACS.numamem b/tests/data/acpi/pc/FACS.numamem new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/pc/FACS.numamem Binary files differdiff --git a/tests/data/acpi/pc/FACS.numamem.dsl b/tests/data/acpi/pc/FACS.numamem.dsl new file mode 100644 index 0000000000..c856f8b230 --- /dev/null +++ b/tests/data/acpi/pc/FACS.numamem.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/FACS.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/FACS.roothp b/tests/data/acpi/pc/FACS.roothp new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/pc/FACS.roothp Binary files differdiff --git a/tests/data/acpi/pc/HMAT.acpihmat.dsl b/tests/data/acpi/pc/HMAT.acpihmat.dsl new file mode 100644 index 0000000000..b55564d383 --- /dev/null +++ b/tests/data/acpi/pc/HMAT.acpihmat.dsl @@ -0,0 +1,132 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HMAT.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HMAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table] +[004h 0004 4] Table Length : 00000118 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 98 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHMAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[02Ah 0042 2] Reserved : 0000 +[02Ch 0044 4] Length : 00000028 +[030h 0048 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[032h 0050 2] Reserved1 : 0000 +[034h 0052 4] Processor Proximity Domain : 00000000 +[038h 0056 4] Memory Proximity Domain : 00000000 +[03Ch 0060 4] Reserved2 : 00000000 +[040h 0064 8] Reserved3 : 0000000000000000 +[048h 0072 8] Reserved4 : 0000000000000000 + +[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[052h 0082 2] Reserved : 0000 +[054h 0084 4] Length : 00000028 +[058h 0088 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[05Ah 0090 2] Reserved1 : 0000 +[05Ch 0092 4] Processor Proximity Domain : 00000000 +[060h 0096 4] Memory Proximity Domain : 00000001 +[064h 0100 4] Reserved2 : 00000000 +[068h 0104 8] Reserved3 : 0000000000000000 +[070h 0112 8] Reserved4 : 0000000000000000 + +[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[07Ah 0122 2] Reserved : 0000 +[07Ch 0124 4] Length : 00000030 +[080h 0128 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[081h 0129 1] Data Type : 00 +[082h 0130 2] Reserved1 : 0000 +[084h 0132 4] Initiator Proximity Domains # : 00000001 +[088h 0136 4] Target Proximity Domains # : 00000002 +[08Ch 0140 4] Reserved2 : 00000000 +[090h 0144 8] Entry Base Unit : 00000000000003E8 +[098h 0152 4] Initiator Proximity Domain List : 00000000 +[09Ch 0156 4] Target Proximity Domain List : 00000000 +[0A0h 0160 4] Target Proximity Domain List : 00000001 +[0A4h 0164 2] Entry : 0001 +[0A6h 0166 2] Entry : FFFE + +[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[0AAh 0170 2] Reserved : 0000 +[0ACh 0172 4] Length : 00000030 +[0B0h 0176 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[0B1h 0177 1] Data Type : 03 +[0B2h 0178 2] Reserved1 : 0000 +[0B4h 0180 4] Initiator Proximity Domains # : 00000001 +[0B8h 0184 4] Target Proximity Domains # : 00000002 +[0BCh 0188 4] Reserved2 : 00000000 +[0C0h 0192 8] Entry Base Unit : 0000000000000001 +[0C8h 0200 4] Initiator Proximity Domain List : 00000000 +[0CCh 0204 4] Target Proximity Domain List : 00000000 +[0D0h 0208 4] Target Proximity Domain List : 00000001 +[0D4h 0212 2] Entry : FFFE +[0D6h 0214 2] Entry : 7FFF + +[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information] +[0DAh 0218 2] Reserved : 0000 +[0DCh 0220 4] Length : 00000020 +[0E0h 0224 4] Memory Proximity Domain : 00000000 +[0E4h 0228 4] Reserved1 : 00000000 +[0E8h 0232 8] Memory Side Cache Size : 0000000000002800 +[0F0h 0240 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[0F4h 0244 2] Reserved2 : 0000 +[0F6h 0246 2] SMBIOS Handle # : 0000 + +[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information] +[0FAh 0250 2] Reserved : 0000 +[0FCh 0252 4] Length : 00000020 +[100h 0256 4] Memory Proximity Domain : 00000001 +[104h 0260 4] Reserved1 : 00000000 +[108h 0264 8] Memory Side Cache Size : 0000000000002800 +[110h 0272 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[114h 0276 2] Reserved2 : 0000 +[116h 0278 2] SMBIOS Handle # : 0000 + +Raw Table Data: Length 280 (0x118) + + 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS + 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... + 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(........... + 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0... + 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0... + 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ... + 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ... + 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 0110: 11 11 08 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HMAT.dsl b/tests/data/acpi/pc/HMAT.dsl new file mode 100644 index 0000000000..8031f62433 --- /dev/null +++ b/tests/data/acpi/pc/HMAT.dsl @@ -0,0 +1,132 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HMAT.acpihmat, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [HMAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table] +[004h 0004 4] Table Length : 00000118 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 98 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHMAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[02Ah 0042 2] Reserved : 0000 +[02Ch 0044 4] Length : 00000028 +[030h 0048 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[032h 0050 2] Reserved1 : 0000 +[034h 0052 4] Processor Proximity Domain : 00000000 +[038h 0056 4] Memory Proximity Domain : 00000000 +[03Ch 0060 4] Reserved2 : 00000000 +[040h 0064 8] Reserved3 : 0000000000000000 +[048h 0072 8] Reserved4 : 0000000000000000 + +[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[052h 0082 2] Reserved : 0000 +[054h 0084 4] Length : 00000028 +[058h 0088 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[05Ah 0090 2] Reserved1 : 0000 +[05Ch 0092 4] Processor Proximity Domain : 00000000 +[060h 0096 4] Memory Proximity Domain : 00000001 +[064h 0100 4] Reserved2 : 00000000 +[068h 0104 8] Reserved3 : 0000000000000000 +[070h 0112 8] Reserved4 : 0000000000000000 + +[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[07Ah 0122 2] Reserved : 0000 +[07Ch 0124 4] Length : 00000030 +[080h 0128 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[081h 0129 1] Data Type : 00 +[082h 0130 2] Reserved1 : 0000 +[084h 0132 4] Initiator Proximity Domains # : 00000001 +[088h 0136 4] Target Proximity Domains # : 00000002 +[08Ch 0140 4] Reserved2 : 00000000 +[090h 0144 8] Entry Base Unit : 00000000000003E8 +[098h 0152 4] Initiator Proximity Domain List : 00000000 +[09Ch 0156 4] Target Proximity Domain List : 00000000 +[0A0h 0160 4] Target Proximity Domain List : 00000001 +[0A4h 0164 2] Entry : 0001 +[0A6h 0166 2] Entry : FFFE + +[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[0AAh 0170 2] Reserved : 0000 +[0ACh 0172 4] Length : 00000030 +[0B0h 0176 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[0B1h 0177 1] Data Type : 03 +[0B2h 0178 2] Reserved1 : 0000 +[0B4h 0180 4] Initiator Proximity Domains # : 00000001 +[0B8h 0184 4] Target Proximity Domains # : 00000002 +[0BCh 0188 4] Reserved2 : 00000000 +[0C0h 0192 8] Entry Base Unit : 0000000000000001 +[0C8h 0200 4] Initiator Proximity Domain List : 00000000 +[0CCh 0204 4] Target Proximity Domain List : 00000000 +[0D0h 0208 4] Target Proximity Domain List : 00000001 +[0D4h 0212 2] Entry : FFFE +[0D6h 0214 2] Entry : 7FFF + +[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information] +[0DAh 0218 2] Reserved : 0000 +[0DCh 0220 4] Length : 00000020 +[0E0h 0224 4] Memory Proximity Domain : 00000000 +[0E4h 0228 4] Reserved1 : 00000000 +[0E8h 0232 8] Memory Side Cache Size : 0000000000002800 +[0F0h 0240 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[0F4h 0244 2] Reserved2 : 0000 +[0F6h 0246 2] SMBIOS Handle # : 0000 + +[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information] +[0FAh 0250 2] Reserved : 0000 +[0FCh 0252 4] Length : 00000020 +[100h 0256 4] Memory Proximity Domain : 00000001 +[104h 0260 4] Reserved1 : 00000000 +[108h 0264 8] Memory Side Cache Size : 0000000000002800 +[110h 0272 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[114h 0276 2] Reserved2 : 0000 +[116h 0278 2] SMBIOS Handle # : 0000 + +Raw Table Data: Length 280 (0x118) + + 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS + 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... + 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(........... + 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0... + 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0... + 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ... + 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ... + 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 0110: 11 11 08 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HPET.acpihmat b/tests/data/acpi/pc/HPET.acpihmat new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/pc/HPET.acpihmat Binary files differdiff --git a/tests/data/acpi/pc/HPET.acpihmat.dsl b/tests/data/acpi/pc/HPET.acpihmat.dsl new file mode 100644 index 0000000000..9029afb2a2 --- /dev/null +++ b/tests/data/acpi/pc/HPET.acpihmat.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HPET.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HPET.bridge b/tests/data/acpi/pc/HPET.bridge new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/pc/HPET.bridge Binary files differdiff --git a/tests/data/acpi/pc/HPET.bridge.dsl b/tests/data/acpi/pc/HPET.bridge.dsl new file mode 100644 index 0000000000..936616faa8 --- /dev/null +++ b/tests/data/acpi/pc/HPET.bridge.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HPET.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HPET.cphp b/tests/data/acpi/pc/HPET.cphp new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/pc/HPET.cphp Binary files differdiff --git a/tests/data/acpi/pc/HPET.cphp.dsl b/tests/data/acpi/pc/HPET.cphp.dsl new file mode 100644 index 0000000000..e095a43ee7 --- /dev/null +++ b/tests/data/acpi/pc/HPET.cphp.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HPET.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HPET.dimmpxm b/tests/data/acpi/pc/HPET.dimmpxm new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/pc/HPET.dimmpxm Binary files differdiff --git a/tests/data/acpi/pc/HPET.dimmpxm.dsl b/tests/data/acpi/pc/HPET.dimmpxm.dsl new file mode 100644 index 0000000000..84ce218492 --- /dev/null +++ b/tests/data/acpi/pc/HPET.dimmpxm.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HPET.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HPET.dsl b/tests/data/acpi/pc/HPET.dsl new file mode 100644 index 0000000000..b392de5c95 --- /dev/null +++ b/tests/data/acpi/pc/HPET.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HPET.roothp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HPET.hpbridge b/tests/data/acpi/pc/HPET.hpbridge new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/pc/HPET.hpbridge Binary files differdiff --git a/tests/data/acpi/pc/HPET.ipmikcs b/tests/data/acpi/pc/HPET.ipmikcs new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/pc/HPET.ipmikcs Binary files differdiff --git a/tests/data/acpi/pc/HPET.ipmikcs.dsl b/tests/data/acpi/pc/HPET.ipmikcs.dsl new file mode 100644 index 0000000000..34d10927dc --- /dev/null +++ b/tests/data/acpi/pc/HPET.ipmikcs.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HPET.ipmikcs, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HPET.memhp b/tests/data/acpi/pc/HPET.memhp new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/pc/HPET.memhp Binary files differdiff --git a/tests/data/acpi/pc/HPET.memhp.dsl b/tests/data/acpi/pc/HPET.memhp.dsl new file mode 100644 index 0000000000..f9f62dd9c8 --- /dev/null +++ b/tests/data/acpi/pc/HPET.memhp.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HPET.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HPET.numamem b/tests/data/acpi/pc/HPET.numamem new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/pc/HPET.numamem Binary files differdiff --git a/tests/data/acpi/pc/HPET.numamem.dsl b/tests/data/acpi/pc/HPET.numamem.dsl new file mode 100644 index 0000000000..1f51efad19 --- /dev/null +++ b/tests/data/acpi/pc/HPET.numamem.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/HPET.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/HPET.roothp b/tests/data/acpi/pc/HPET.roothp new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/pc/HPET.roothp Binary files differdiff --git a/tests/data/acpi/pc/NFIT.dimmpxm.dsl b/tests/data/acpi/pc/NFIT.dimmpxm.dsl new file mode 100644 index 0000000000..33212b0a17 --- /dev/null +++ b/tests/data/acpi/pc/NFIT.dimmpxm.dsl @@ -0,0 +1,115 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/NFIT.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000F0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 24 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000002 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000108000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities] +[0E2h 0226 2] Length : 0010 + +[0E4h 0228 1] Highest Capability : 01 +[0E5h 0229 3] Reserved : 000000 +[0E8h 0232 4] Capabilities (decoded below) : 00000003 + Cache Flush to NVDIMM : 1 + Memory Flush to NVDIMM : 1 + Memory Mirroring : 0 +[0ECh 0236 4] Reserved : 00000000 + +Raw Table Data: Length 240 (0xF0) + + 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/NFIT.dsl b/tests/data/acpi/pc/NFIT.dsl new file mode 100644 index 0000000000..f4a8034f87 --- /dev/null +++ b/tests/data/acpi/pc/NFIT.dsl @@ -0,0 +1,115 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/NFIT.dimmpxm, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000F0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 24 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000002 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000108000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities] +[0E2h 0226 2] Length : 0010 + +[0E4h 0228 1] Highest Capability : 01 +[0E5h 0229 3] Reserved : 000000 +[0E8h 0232 4] Capabilities (decoded below) : 00000003 + Cache Flush to NVDIMM : 1 + Memory Flush to NVDIMM : 1 + Memory Mirroring : 0 +[0ECh 0236 4] Reserved : 00000000 + +Raw Table Data: Length 240 (0xF0) + + 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/SLIT.cphp.dsl b/tests/data/acpi/pc/SLIT.cphp.dsl new file mode 100644 index 0000000000..20289608db --- /dev/null +++ b/tests/data/acpi/pc/SLIT.cphp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/SLIT.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/pc/SLIT.dsl b/tests/data/acpi/pc/SLIT.dsl new file mode 100644 index 0000000000..8b923249af --- /dev/null +++ b/tests/data/acpi/pc/SLIT.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/SLIT.memhp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/pc/SLIT.memhp.dsl b/tests/data/acpi/pc/SLIT.memhp.dsl new file mode 100644 index 0000000000..b3a0170144 --- /dev/null +++ b/tests/data/acpi/pc/SLIT.memhp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/SLIT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/pc/SRAT.acpihmat.dsl b/tests/data/acpi/pc/SRAT.acpihmat.dsl new file mode 100644 index 0000000000..e3c788672f --- /dev/null +++ b/tests/data/acpi/pc/SRAT.acpihmat.dsl @@ -0,0 +1,137 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/SRAT.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000118 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : C0 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[041h 0065 1] Length : 10 + +[042h 0066 1] Proximity Domain Low(8) : 00 +[043h 0067 1] Apic ID : 01 +[044h 0068 4] Flags (decoded below) : 00000001 + Enabled : 1 +[048h 0072 1] Local Sapic EID : 00 +[049h 0073 3] Proximity Domain High(24) : 000000 +[04Ch 0076 4] Clock Domain : 00000000 + +[050h 0080 1] Subtable Type : 01 [Memory Affinity] +[051h 0081 1] Length : 28 + +[052h 0082 4] Proximity Domain : 00000000 +[056h 0086 2] Reserved1 : 0000 +[058h 0088 8] Base Address : 0000000000000000 +[060h 0096 8] Address Length : 00000000000A0000 +[068h 0104 4] Reserved2 : 00000000 +[06Ch 0108 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[070h 0112 8] Reserved3 : 0000000000000000 + +[078h 0120 1] Subtable Type : 01 [Memory Affinity] +[079h 0121 1] Length : 28 + +[07Ah 0122 4] Proximity Domain : 00000000 +[07Eh 0126 2] Reserved1 : 0000 +[080h 0128 8] Base Address : 0000000000100000 +[088h 0136 8] Address Length : 0000000003F00000 +[090h 0144 4] Reserved2 : 00000000 +[094h 0148 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[098h 0152 8] Reserved3 : 0000000000000000 + +[0A0h 0160 1] Subtable Type : 01 [Memory Affinity] +[0A1h 0161 1] Length : 28 + +[0A2h 0162 4] Proximity Domain : 00000001 +[0A6h 0166 2] Reserved1 : 0000 +[0A8h 0168 8] Base Address : 0000000004000000 +[0B0h 0176 8] Address Length : 0000000004000000 +[0B8h 0184 4] Reserved2 : 00000000 +[0BCh 0188 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0C0h 0192 8] Reserved3 : 0000000000000000 + +[0C8h 0200 1] Subtable Type : 01 [Memory Affinity] +[0C9h 0201 1] Length : 28 + +[0CAh 0202 4] Proximity Domain : 00000000 +[0CEh 0206 2] Reserved1 : 0000 +[0D0h 0208 8] Base Address : 0000000000000000 +[0D8h 0216 8] Address Length : 0000000000000000 +[0E0h 0224 4] Reserved2 : 00000000 +[0E4h 0228 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0E8h 0232 8] Reserved3 : 0000000000000000 + +[0F0h 0240 1] Subtable Type : 01 [Memory Affinity] +[0F1h 0241 1] Length : 28 + +[0F2h 0242 4] Proximity Domain : 00000001 +[0F6h 0246 2] Reserved1 : 0000 +[0F8h 0248 8] Base Address : 0000000100000000 +[100h 0256 8] Address Length : 00000000B8000000 +[108h 0264 4] Reserved2 : 00000000 +[10Ch 0268 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[110h 0272 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 280 (0x118) + + 0000: 53 52 41 54 18 01 00 00 01 C0 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0060: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0070: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0080: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................ + 0090: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(.............. + 00B0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(.............. + 0100: 00 00 00 B8 00 00 00 00 00 00 00 00 03 00 00 00 // ................ + 0110: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/SRAT.cphp.dsl b/tests/data/acpi/pc/SRAT.cphp.dsl new file mode 100644 index 0000000000..20c38ee3cc --- /dev/null +++ b/tests/data/acpi/pc/SRAT.cphp.dsl @@ -0,0 +1,168 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/SRAT.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000130 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 36 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[041h 0065 1] Length : 10 + +[042h 0066 1] Proximity Domain Low(8) : 00 +[043h 0067 1] Apic ID : 01 +[044h 0068 4] Flags (decoded below) : 00000001 + Enabled : 1 +[048h 0072 1] Local Sapic EID : 00 +[049h 0073 3] Proximity Domain High(24) : 000000 +[04Ch 0076 4] Clock Domain : 00000000 + +[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[051h 0081 1] Length : 10 + +[052h 0082 1] Proximity Domain Low(8) : 00 +[053h 0083 1] Apic ID : 02 +[054h 0084 4] Flags (decoded below) : 00000001 + Enabled : 1 +[058h 0088 1] Local Sapic EID : 00 +[059h 0089 3] Proximity Domain High(24) : 000000 +[05Ch 0092 4] Clock Domain : 00000000 + +[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[061h 0097 1] Length : 10 + +[062h 0098 1] Proximity Domain Low(8) : 01 +[063h 0099 1] Apic ID : 04 +[064h 0100 4] Flags (decoded below) : 00000001 + Enabled : 1 +[068h 0104 1] Local Sapic EID : 00 +[069h 0105 3] Proximity Domain High(24) : 000000 +[06Ch 0108 4] Clock Domain : 00000000 + +[070h 0112 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[071h 0113 1] Length : 10 + +[072h 0114 1] Proximity Domain Low(8) : 01 +[073h 0115 1] Apic ID : 05 +[074h 0116 4] Flags (decoded below) : 00000001 + Enabled : 1 +[078h 0120 1] Local Sapic EID : 00 +[079h 0121 3] Proximity Domain High(24) : 000000 +[07Ch 0124 4] Clock Domain : 00000000 + +[080h 0128 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[081h 0129 1] Length : 10 + +[082h 0130 1] Proximity Domain Low(8) : 01 +[083h 0131 1] Apic ID : 06 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 +[088h 0136 1] Local Sapic EID : 00 +[089h 0137 3] Proximity Domain High(24) : 000000 +[08Ch 0140 4] Clock Domain : 00000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 00000000000A0000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000100000 +[0C8h 0200 8] Address Length : 0000000003F00000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +[0E0h 0224 1] Subtable Type : 01 [Memory Affinity] +[0E1h 0225 1] Length : 28 + +[0E2h 0226 4] Proximity Domain : 00000001 +[0E6h 0230 2] Reserved1 : 0000 +[0E8h 0232 8] Base Address : 0000000004000000 +[0F0h 0240 8] Address Length : 0000000004000000 +[0F8h 0248 4] Reserved2 : 00000000 +[0FCh 0252 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[100h 0256 8] Reserved3 : 0000000000000000 + +[108h 0264 1] Subtable Type : 01 [Memory Affinity] +[109h 0265 1] Length : 28 + +[10Ah 0266 4] Proximity Domain : 00000000 +[10Eh 0270 2] Reserved1 : 0000 +[110h 0272 8] Base Address : 0000000000000000 +[118h 0280 8] Address Length : 0000000000000000 +[120h 0288 4] Reserved2 : 00000000 +[124h 0292 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[128h 0296 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 304 (0x130) + + 0000: 53 52 41 54 30 01 00 00 01 36 42 4F 43 48 53 20 // SRAT0....6BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 10 00 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 10 01 04 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 10 01 05 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 10 01 06 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................ + 00D0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(.............. + 00F0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/SRAT.dimmpxm.dsl b/tests/data/acpi/pc/SRAT.dimmpxm.dsl new file mode 100644 index 0000000000..888fef1b5c --- /dev/null +++ b/tests/data/acpi/pc/SRAT.dimmpxm.dsl @@ -0,0 +1,194 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/SRAT.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000188 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 68 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[041h 0065 1] Length : 10 + +[042h 0066 1] Proximity Domain Low(8) : 01 +[043h 0067 1] Apic ID : 01 +[044h 0068 4] Flags (decoded below) : 00000001 + Enabled : 1 +[048h 0072 1] Local Sapic EID : 00 +[049h 0073 3] Proximity Domain High(24) : 000000 +[04Ch 0076 4] Clock Domain : 00000000 + +[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[051h 0081 1] Length : 10 + +[052h 0082 1] Proximity Domain Low(8) : 02 +[053h 0083 1] Apic ID : 02 +[054h 0084 4] Flags (decoded below) : 00000001 + Enabled : 1 +[058h 0088 1] Local Sapic EID : 00 +[059h 0089 3] Proximity Domain High(24) : 000000 +[05Ch 0092 4] Clock Domain : 00000000 + +[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[061h 0097 1] Length : 10 + +[062h 0098 1] Proximity Domain Low(8) : 03 +[063h 0099 1] Apic ID : 03 +[064h 0100 4] Flags (decoded below) : 00000001 + Enabled : 1 +[068h 0104 1] Local Sapic EID : 00 +[069h 0105 3] Proximity Domain High(24) : 000000 +[06Ch 0108 4] Clock Domain : 00000000 + +[070h 0112 1] Subtable Type : 01 [Memory Affinity] +[071h 0113 1] Length : 28 + +[072h 0114 4] Proximity Domain : 00000000 +[076h 0118 2] Reserved1 : 0000 +[078h 0120 8] Base Address : 0000000000000000 +[080h 0128 8] Address Length : 00000000000A0000 +[088h 0136 4] Reserved2 : 00000000 +[08Ch 0140 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[090h 0144 8] Reserved3 : 0000000000000000 + +[098h 0152 1] Subtable Type : 01 [Memory Affinity] +[099h 0153 1] Length : 28 + +[09Ah 0154 4] Proximity Domain : 00000000 +[09Eh 0158 2] Reserved1 : 0000 +[0A0h 0160 8] Base Address : 0000000000100000 +[0A8h 0168 8] Address Length : 0000000001F00000 +[0B0h 0176 4] Reserved2 : 00000000 +[0B4h 0180 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B8h 0184 8] Reserved3 : 0000000000000000 + +[0C0h 0192 1] Subtable Type : 01 [Memory Affinity] +[0C1h 0193 1] Length : 28 + +[0C2h 0194 4] Proximity Domain : 00000001 +[0C6h 0198 2] Reserved1 : 0000 +[0C8h 0200 8] Base Address : 0000000002000000 +[0D0h 0208 8] Address Length : 0000000002000000 +[0D8h 0216 4] Reserved2 : 00000000 +[0DCh 0220 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0E0h 0224 8] Reserved3 : 0000000000000000 + +[0E8h 0232 1] Subtable Type : 01 [Memory Affinity] +[0E9h 0233 1] Length : 28 + +[0EAh 0234 4] Proximity Domain : 00000002 +[0EEh 0238 2] Reserved1 : 0000 +[0F0h 0240 8] Base Address : 0000000004000000 +[0F8h 0248 8] Address Length : 0000000002000000 +[100h 0256 4] Reserved2 : 00000000 +[104h 0260 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[108h 0264 8] Reserved3 : 0000000000000000 + +[110h 0272 1] Subtable Type : 01 [Memory Affinity] +[111h 0273 1] Length : 28 + +[112h 0274 4] Proximity Domain : 00000003 +[116h 0278 2] Reserved1 : 0000 +[118h 0280 8] Base Address : 0000000006000000 +[120h 0288 8] Address Length : 0000000002000000 +[128h 0296 4] Reserved2 : 00000000 +[12Ch 0300 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[130h 0304 8] Reserved3 : 0000000000000000 + +[138h 0312 1] Subtable Type : 01 [Memory Affinity] +[139h 0313 1] Length : 28 + +[13Ah 0314 4] Proximity Domain : 00000002 +[13Eh 0318 2] Reserved1 : 0000 +[140h 0320 8] Base Address : 0000000108000000 +[148h 0328 8] Address Length : 0000000008000000 +[150h 0336 4] Reserved2 : 00000000 +[154h 0340 4] Flags (decoded below) : 00000005 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 1 +[158h 0344 8] Reserved3 : 0000000000000000 + +[160h 0352 1] Subtable Type : 01 [Memory Affinity] +[161h 0353 1] Length : 28 + +[162h 0354 4] Proximity Domain : 00000003 +[166h 0358 2] Reserved1 : 0000 +[168h 0360 8] Base Address : 0000000100000000 +[170h 0368 8] Address Length : 00000000F8000000 +[178h 0376 4] Reserved2 : 00000000 +[17Ch 0380 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[180h 0384 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 392 (0x188) + + 0000: 53 52 41 54 88 01 00 00 01 68 42 4F 43 48 53 20 // SRAT.....hBOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 10 01 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 10 02 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 10 03 03 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0080: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00A0: 00 00 10 00 00 00 00 00 00 00 F0 01 00 00 00 00 // ................ + 00B0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 01 28 01 00 00 00 00 00 00 00 00 02 00 00 00 00 // .(.............. + 00D0: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(...... + 00F0: 00 00 00 04 00 00 00 00 00 00 00 02 00 00 00 00 // ................ + 0100: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0110: 01 28 03 00 00 00 00 00 00 00 00 06 00 00 00 00 // .(.............. + 0120: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0130: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(...... + 0140: 00 00 00 08 01 00 00 00 00 00 00 08 00 00 00 00 // ................ + 0150: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0160: 01 28 03 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(.............. + 0170: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................ + 0180: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/SRAT.dsl b/tests/data/acpi/pc/SRAT.dsl new file mode 100644 index 0000000000..77bbfebc81 --- /dev/null +++ b/tests/data/acpi/pc/SRAT.dsl @@ -0,0 +1,108 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/SRAT.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : F5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000001 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000001 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000007F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 0000000000000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000000000 +[0C8h 0200 8] Address Length : 0000000000000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/SRAT.memhp.dsl b/tests/data/acpi/pc/SRAT.memhp.dsl new file mode 100644 index 0000000000..803f9c8f1a --- /dev/null +++ b/tests/data/acpi/pc/SRAT.memhp.dsl @@ -0,0 +1,125 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/SRAT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000108 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A2 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000000 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000000 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000003F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000001 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000004000000 +[0A0h 0160 8] Address Length : 0000000004000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000000000 +[0C8h 0200 8] Address Length : 0000000000000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +[0E0h 0224 1] Subtable Type : 01 [Memory Affinity] +[0E1h 0225 1] Length : 28 + +[0E2h 0226 4] Proximity Domain : 00000001 +[0E6h 0230 2] Reserved1 : 0000 +[0E8h 0232 8] Base Address : 0000000100000000 +[0F0h 0240 8] Address Length : 00000000F8000000 +[0F8h 0248 4] Reserved2 : 00000000 +[0FCh 0252 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[100h 0256 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 264 (0x108) + + 0000: 53 52 41 54 08 01 00 00 01 A2 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(.............. + 00A0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(.............. + 00F0: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/pc/SRAT.numamem.dsl b/tests/data/acpi/pc/SRAT.numamem.dsl new file mode 100644 index 0000000000..74f4382dd1 --- /dev/null +++ b/tests/data/acpi/pc/SRAT.numamem.dsl @@ -0,0 +1,108 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/SRAT.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : F5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000001 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000001 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000007F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 0000000000000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000000000 +[0C8h 0200 8] Address Length : 0000000000000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/pc/SSDT.dsl b/tests/data/acpi/pc/SSDT.dsl new file mode 100644 index 0000000000..abd64f6133 --- /dev/null +++ b/tests/data/acpi/pc/SSDT.dsl @@ -0,0 +1,205 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/pc/SSDT.dimmpxm, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "SSDT" + * Length 0x000002DE (734) + * Revision 0x01 + * Checksum 0x56 + * OEM ID "BOCHS " + * OEM Table ID "NVDIMM" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) +{ + Scope (\_SB) + { + Device (NVDR) + { + Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID + Method (NCAL, 5, Serialized) + { + Local6 = MEMA /* \MEMA */ + OperationRegion (NPIO, SystemIO, 0x0A18, 0x04) + OperationRegion (NRAM, SystemMemory, Local6, 0x1000) + Field (NPIO, DWordAcc, NoLock, Preserve) + { + NTFI, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + REVS, 32, + FUNC, 32, + FARG, 32672 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + ODAT, 32736 + } + + If ((Arg4 == Zero)) + { + Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba") + } + ElseIf ((Arg4 == 0x00010000)) + { + Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62") + } + Else + { + Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66") + } + + If (((Local6 == Zero) | (Arg0 != Local0))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x00 // . + }) + } + + Return (Buffer (One) + { + 0x01 // . + }) + } + + HDLE = Arg4 + REVS = Arg1 + FUNC = Arg2 + If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) + { + Local2 = Arg3 [Zero] + Local3 = DerefOf (Local2) + FARG = Local3 + } + + NTFI = Local6 + Local1 = (RLEN - 0x04) + If ((Local1 < 0x08)) + { + Local2 = Zero + Name (TBUF, Buffer (One) + { + 0x00 // . + }) + Local7 = Buffer (Zero){} + While ((Local2 < Local1)) + { + TBUF [Zero] = DerefOf (ODAT [Local2]) + Concatenate (Local7, TBUF, Local7) + Local2++ + } + + Return (Local7) + } + + Local1 = (Local1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Return (OBUF) /* \_SB_.NVDR.NCAL.OBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, Zero)) + } + + Name (RSTA, Zero) + Method (RFIT, 1, Serialized) + { + Name (OFST, Zero) + OFST = Arg0 + Local0 = NCAL (ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62"), One, One, Package (0x01) + { + OFST + }, 0x00010000) + CreateDWordField (Local0, Zero, STAU) + RSTA = STAU /* \_SB_.NVDR.RFIT.STAU */ + If ((Zero != STAU)) + { + Return (Buffer (Zero){}) + } + + Local1 = SizeOf (Local0) + Local1 -= 0x04 + If ((Local1 == Zero)) + { + Return (Buffer (Zero){}) + } + + CreateField (Local0, 0x20, (Local1 << 0x03), BUFF) + Return (BUFF) /* \_SB_.NVDR.RFIT.BUFF */ + } + + Method (_FIT, 0, Serialized) // _FIT: Firmware Interface Table + { + Local2 = Buffer (Zero){} + Local3 = Zero + While (One) + { + Local0 = RFIT (Local3) + Local1 = SizeOf (Local0) + If ((RSTA == 0x0100)) + { + Local2 = Buffer (Zero){} + Local3 = Zero + } + Else + { + If ((Local1 == Zero)) + { + Return (Local2) + } + + Local3 += Local1 + Concatenate (Local2, Local0, Local2) + } + } + } + + Device (NV00) + { + Name (_ADR, One) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, One)) + } + } + + Device (NV01) + { + Name (_ADR, 0x02) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02)) + } + } + + Device (NV02) + { + Name (_ADR, 0x03) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03)) + } + } + } + } + + Name (MEMA, 0x07FFE000) +} + diff --git a/tests/data/acpi/pc/WAET.acpihmat b/tests/data/acpi/pc/WAET.acpihmat new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/pc/WAET.acpihmat Binary files differdiff --git a/tests/data/acpi/pc/WAET.acpihmat.dsl b/tests/data/acpi/pc/WAET.acpihmat.dsl new file mode 100644 index 0000000000..991c8773b8 --- /dev/null +++ b/tests/data/acpi/pc/WAET.acpihmat.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/WAET.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/pc/WAET.bridge b/tests/data/acpi/pc/WAET.bridge new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/pc/WAET.bridge Binary files differdiff --git a/tests/data/acpi/pc/WAET.bridge.dsl b/tests/data/acpi/pc/WAET.bridge.dsl new file mode 100644 index 0000000000..f47dbb17a7 --- /dev/null +++ b/tests/data/acpi/pc/WAET.bridge.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/WAET.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/pc/WAET.cphp b/tests/data/acpi/pc/WAET.cphp new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/pc/WAET.cphp Binary files differdiff --git a/tests/data/acpi/pc/WAET.cphp.dsl b/tests/data/acpi/pc/WAET.cphp.dsl new file mode 100644 index 0000000000..ff077a14eb --- /dev/null +++ b/tests/data/acpi/pc/WAET.cphp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/WAET.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/pc/WAET.dimmpxm b/tests/data/acpi/pc/WAET.dimmpxm new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/pc/WAET.dimmpxm Binary files differdiff --git a/tests/data/acpi/pc/WAET.dimmpxm.dsl b/tests/data/acpi/pc/WAET.dimmpxm.dsl new file mode 100644 index 0000000000..b8192c8601 --- /dev/null +++ b/tests/data/acpi/pc/WAET.dimmpxm.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/WAET.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/pc/WAET.dsl b/tests/data/acpi/pc/WAET.dsl new file mode 100644 index 0000000000..53b6c1dc42 --- /dev/null +++ b/tests/data/acpi/pc/WAET.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/WAET.roothp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/pc/WAET.hpbridge b/tests/data/acpi/pc/WAET.hpbridge new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/pc/WAET.hpbridge Binary files differdiff --git a/tests/data/acpi/pc/WAET.ipmikcs b/tests/data/acpi/pc/WAET.ipmikcs new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/pc/WAET.ipmikcs Binary files differdiff --git a/tests/data/acpi/pc/WAET.ipmikcs.dsl b/tests/data/acpi/pc/WAET.ipmikcs.dsl new file mode 100644 index 0000000000..5144bada0f --- /dev/null +++ b/tests/data/acpi/pc/WAET.ipmikcs.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/WAET.ipmikcs, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/pc/WAET.memhp b/tests/data/acpi/pc/WAET.memhp new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/pc/WAET.memhp Binary files differdiff --git a/tests/data/acpi/pc/WAET.memhp.dsl b/tests/data/acpi/pc/WAET.memhp.dsl new file mode 100644 index 0000000000..bfe3a036d7 --- /dev/null +++ b/tests/data/acpi/pc/WAET.memhp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/WAET.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/pc/WAET.numamem b/tests/data/acpi/pc/WAET.numamem new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/pc/WAET.numamem Binary files differdiff --git a/tests/data/acpi/pc/WAET.numamem.dsl b/tests/data/acpi/pc/WAET.numamem.dsl new file mode 100644 index 0000000000..e4c6cf4bf8 --- /dev/null +++ b/tests/data/acpi/pc/WAET.numamem.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/pc/WAET.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/pc/WAET.roothp b/tests/data/acpi/pc/WAET.roothp new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/pc/WAET.roothp Binary files differdiff --git a/tests/data/acpi/q35/APIC.acpihmat.dsl b/tests/data/acpi/q35/APIC.acpihmat.dsl new file mode 100644 index 0000000000..5fe9fb4669 --- /dev/null +++ b/tests/data/acpi/q35/APIC.acpihmat.dsl @@ -0,0 +1,112 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000080 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : DA +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 01 [I/O APIC] +[03Dh 0061 1] Length : 0C +[03Eh 0062 1] I/O Apic ID : 00 +[03Fh 0063 1] Reserved : 00 +[040h 0064 4] Address : FEC00000 +[044h 0068 4] Interrupt : 00000000 + +[048h 0072 1] Subtable Type : 02 [Interrupt Source Override] +[049h 0073 1] Length : 0A +[04Ah 0074 1] Bus : 00 +[04Bh 0075 1] Source : 00 +[04Ch 0076 4] Interrupt : 00000002 +[050h 0080 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[052h 0082 1] Subtable Type : 02 [Interrupt Source Override] +[053h 0083 1] Length : 0A +[054h 0084 1] Bus : 00 +[055h 0085 1] Source : 05 +[056h 0086 4] Interrupt : 00000005 +[05Ah 0090 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Ch 0092 1] Subtable Type : 02 [Interrupt Source Override] +[05Dh 0093 1] Length : 0A +[05Eh 0094 1] Bus : 00 +[05Fh 0095 1] Source : 09 +[060h 0096 4] Interrupt : 00000009 +[064h 0100 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[066h 0102 1] Subtable Type : 02 [Interrupt Source Override] +[067h 0103 1] Length : 0A +[068h 0104 1] Bus : 00 +[069h 0105 1] Source : 0A +[06Ah 0106 4] Interrupt : 0000000A +[06Eh 0110 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[070h 0112 1] Subtable Type : 02 [Interrupt Source Override] +[071h 0113 1] Length : 0A +[072h 0114 1] Bus : 00 +[073h 0115 1] Source : 0B +[074h 0116 4] Interrupt : 0000000B +[078h 0120 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[07Ah 0122 1] Subtable Type : 04 [Local APIC NMI] +[07Bh 0123 1] Length : 06 +[07Ch 0124 1] Processor ID : FF +[07Dh 0125 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[07Fh 0127 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 128 (0x80) + + 0000: 41 50 49 43 80 00 00 00 01 DA 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 01 0C 00 00 // ................ + 0040: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0050: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0060: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0070: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/q35/APIC.bridge b/tests/data/acpi/q35/APIC.bridge new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/q35/APIC.bridge Binary files differdiff --git a/tests/data/acpi/q35/APIC.bridge.dsl b/tests/data/acpi/q35/APIC.bridge.dsl new file mode 100644 index 0000000000..2489067401 --- /dev/null +++ b/tests/data/acpi/q35/APIC.bridge.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.cphp.dsl b/tests/data/acpi/q35/APIC.cphp.dsl new file mode 100644 index 0000000000..be8daf5f80 --- /dev/null +++ b/tests/data/acpi/q35/APIC.cphp.dsl @@ -0,0 +1,146 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 7B +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC] +[03Dh 0061 1] Length : 08 +[03Eh 0062 1] Processor ID : 02 +[03Fh 0063 1] Local Apic ID : 02 +[040h 0064 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[044h 0068 1] Subtable Type : 00 [Processor Local APIC] +[045h 0069 1] Length : 08 +[046h 0070 1] Processor ID : 03 +[047h 0071 1] Local Apic ID : 04 +[048h 0072 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[04Ch 0076 1] Subtable Type : 00 [Processor Local APIC] +[04Dh 0077 1] Length : 08 +[04Eh 0078 1] Processor ID : 04 +[04Fh 0079 1] Local Apic ID : 05 +[050h 0080 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[054h 0084 1] Subtable Type : 00 [Processor Local APIC] +[055h 0085 1] Length : 08 +[056h 0086 1] Processor ID : 05 +[057h 0087 1] Local Apic ID : 06 +[058h 0088 4] Flags (decoded below) : 00000000 + Processor Enabled : 0 + Runtime Online Capable : 0 + +[05Ch 0092 1] Subtable Type : 01 [I/O APIC] +[05Dh 0093 1] Length : 0C +[05Eh 0094 1] I/O Apic ID : 00 +[05Fh 0095 1] Reserved : 00 +[060h 0096 4] Address : FEC00000 +[064h 0100 4] Interrupt : 00000000 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 00 +[06Ch 0108 4] Interrupt : 00000002 +[070h 0112 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[072h 0114 1] Subtable Type : 02 [Interrupt Source Override] +[073h 0115 1] Length : 0A +[074h 0116 1] Bus : 00 +[075h 0117 1] Source : 05 +[076h 0118 4] Interrupt : 00000005 +[07Ah 0122 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[07Ch 0124 1] Subtable Type : 02 [Interrupt Source Override] +[07Dh 0125 1] Length : 0A +[07Eh 0126 1] Bus : 00 +[07Fh 0127 1] Source : 09 +[080h 0128 4] Interrupt : 00000009 +[084h 0132 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[086h 0134 1] Subtable Type : 02 [Interrupt Source Override] +[087h 0135 1] Length : 0A +[088h 0136 1] Bus : 00 +[089h 0137 1] Source : 0A +[08Ah 0138 4] Interrupt : 0000000A +[08Eh 0142 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[090h 0144 1] Subtable Type : 02 [Interrupt Source Override] +[091h 0145 1] Length : 0A +[092h 0146 1] Bus : 00 +[093h 0147 1] Source : 0B +[094h 0148 4] Interrupt : 0000000B +[098h 0152 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[09Ah 0154 1] Subtable Type : 04 [Local APIC NMI] +[09Bh 0155 1] Length : 06 +[09Ch 0156 1] Processor ID : FF +[09Dh 0157 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[09Fh 0159 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 160 (0xA0) + + 0000: 41 50 49 43 A0 00 00 00 01 7B 42 4F 43 48 53 20 // APIC.....{BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................ + 0040: 00 00 00 00 00 08 03 04 00 00 00 00 00 08 04 05 // ................ + 0050: 00 00 00 00 00 08 05 06 00 00 00 00 01 0C 00 00 // ................ + 0060: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0070: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0080: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0090: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/q35/APIC.dimmpxm.dsl b/tests/data/acpi/q35/APIC.dimmpxm.dsl new file mode 100644 index 0000000000..798ab91bed --- /dev/null +++ b/tests/data/acpi/q35/APIC.dimmpxm.dsl @@ -0,0 +1,129 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000090 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : AE +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 00 [Processor Local APIC] +[035h 0053 1] Length : 08 +[036h 0054 1] Processor ID : 01 +[037h 0055 1] Local Apic ID : 01 +[038h 0056 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[03Ch 0060 1] Subtable Type : 00 [Processor Local APIC] +[03Dh 0061 1] Length : 08 +[03Eh 0062 1] Processor ID : 02 +[03Fh 0063 1] Local Apic ID : 02 +[040h 0064 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[044h 0068 1] Subtable Type : 00 [Processor Local APIC] +[045h 0069 1] Length : 08 +[046h 0070 1] Processor ID : 03 +[047h 0071 1] Local Apic ID : 03 +[048h 0072 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[04Ch 0076 1] Subtable Type : 01 [I/O APIC] +[04Dh 0077 1] Length : 0C +[04Eh 0078 1] I/O Apic ID : 00 +[04Fh 0079 1] Reserved : 00 +[050h 0080 4] Address : FEC00000 +[054h 0084 4] Interrupt : 00000000 + +[058h 0088 1] Subtable Type : 02 [Interrupt Source Override] +[059h 0089 1] Length : 0A +[05Ah 0090 1] Bus : 00 +[05Bh 0091 1] Source : 00 +[05Ch 0092 4] Interrupt : 00000002 +[060h 0096 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[062h 0098 1] Subtable Type : 02 [Interrupt Source Override] +[063h 0099 1] Length : 0A +[064h 0100 1] Bus : 00 +[065h 0101 1] Source : 05 +[066h 0102 4] Interrupt : 00000005 +[06Ah 0106 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[06Ch 0108 1] Subtable Type : 02 [Interrupt Source Override] +[06Dh 0109 1] Length : 0A +[06Eh 0110 1] Bus : 00 +[06Fh 0111 1] Source : 09 +[070h 0112 4] Interrupt : 00000009 +[074h 0116 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[076h 0118 1] Subtable Type : 02 [Interrupt Source Override] +[077h 0119 1] Length : 0A +[078h 0120 1] Bus : 00 +[079h 0121 1] Source : 0A +[07Ah 0122 4] Interrupt : 0000000A +[07Eh 0126 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[080h 0128 1] Subtable Type : 02 [Interrupt Source Override] +[081h 0129 1] Length : 0A +[082h 0130 1] Bus : 00 +[083h 0131 1] Source : 0B +[084h 0132 4] Interrupt : 0000000B +[088h 0136 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[08Ah 0138 1] Subtable Type : 04 [Local APIC NMI] +[08Bh 0139 1] Length : 06 +[08Ch 0140 1] Processor ID : FF +[08Dh 0141 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[08Fh 0143 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 144 (0x90) + + 0000: 41 50 49 43 90 00 00 00 01 AE 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 00 08 01 01 01 00 00 00 00 08 02 02 // ................ + 0040: 01 00 00 00 00 08 03 03 01 00 00 00 01 0C 00 00 // ................ + 0050: 00 00 C0 FE 00 00 00 00 02 0A 00 00 02 00 00 00 // ................ + 0060: 00 00 02 0A 00 05 05 00 00 00 0D 00 02 0A 00 09 // ................ + 0070: 09 00 00 00 0D 00 02 0A 00 0A 0A 00 00 00 0D 00 // ................ + 0080: 02 0A 00 0B 0B 00 00 00 0D 00 04 06 FF 00 00 01 // ................ diff --git a/tests/data/acpi/q35/APIC.dsl b/tests/data/acpi/q35/APIC.dsl new file mode 100644 index 0000000000..77d2d2c0a5 --- /dev/null +++ b/tests/data/acpi/q35/APIC.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.ipmibt b/tests/data/acpi/q35/APIC.ipmibt new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/q35/APIC.ipmibt Binary files differdiff --git a/tests/data/acpi/q35/APIC.ipmibt.dsl b/tests/data/acpi/q35/APIC.ipmibt.dsl new file mode 100644 index 0000000000..127e21e2fe --- /dev/null +++ b/tests/data/acpi/q35/APIC.ipmibt.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.memhp b/tests/data/acpi/q35/APIC.memhp new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/q35/APIC.memhp Binary files differdiff --git a/tests/data/acpi/q35/APIC.memhp.dsl b/tests/data/acpi/q35/APIC.memhp.dsl new file mode 100644 index 0000000000..1c0cb1dad1 --- /dev/null +++ b/tests/data/acpi/q35/APIC.memhp.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.mmio64 b/tests/data/acpi/q35/APIC.mmio64 new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/q35/APIC.mmio64 Binary files differdiff --git a/tests/data/acpi/q35/APIC.mmio64.dsl b/tests/data/acpi/q35/APIC.mmio64.dsl new file mode 100644 index 0000000000..9a3df90766 --- /dev/null +++ b/tests/data/acpi/q35/APIC.mmio64.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.numamem b/tests/data/acpi/q35/APIC.numamem new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/q35/APIC.numamem Binary files differdiff --git a/tests/data/acpi/q35/APIC.numamem.dsl b/tests/data/acpi/q35/APIC.numamem.dsl new file mode 100644 index 0000000000..f4c5480fd6 --- /dev/null +++ b/tests/data/acpi/q35/APIC.numamem.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/APIC.tis b/tests/data/acpi/q35/APIC.tis new file mode 100644 index 0000000000..84509e0ae4 --- /dev/null +++ b/tests/data/acpi/q35/APIC.tis Binary files differdiff --git a/tests/data/acpi/q35/APIC.tis.dsl b/tests/data/acpi/q35/APIC.tis.dsl new file mode 100644 index 0000000000..ca2373818e --- /dev/null +++ b/tests/data/acpi/q35/APIC.tis.dsl @@ -0,0 +1,104 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/APIC.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 00000078 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : ED +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : FEE00000 +[028h 0040 4] Flags (decoded below) : 00000001 + PC-AT Compatibility : 1 + +[02Ch 0044 1] Subtable Type : 00 [Processor Local APIC] +[02Dh 0045 1] Length : 08 +[02Eh 0046 1] Processor ID : 00 +[02Fh 0047 1] Local Apic ID : 00 +[030h 0048 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Runtime Online Capable : 0 + +[034h 0052 1] Subtable Type : 01 [I/O APIC] +[035h 0053 1] Length : 0C +[036h 0054 1] I/O Apic ID : 00 +[037h 0055 1] Reserved : 00 +[038h 0056 4] Address : FEC00000 +[03Ch 0060 4] Interrupt : 00000000 + +[040h 0064 1] Subtable Type : 02 [Interrupt Source Override] +[041h 0065 1] Length : 0A +[042h 0066 1] Bus : 00 +[043h 0067 1] Source : 00 +[044h 0068 4] Interrupt : 00000002 +[048h 0072 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 + +[04Ah 0074 1] Subtable Type : 02 [Interrupt Source Override] +[04Bh 0075 1] Length : 0A +[04Ch 0076 1] Bus : 00 +[04Dh 0077 1] Source : 05 +[04Eh 0078 4] Interrupt : 00000005 +[052h 0082 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[054h 0084 1] Subtable Type : 02 [Interrupt Source Override] +[055h 0085 1] Length : 0A +[056h 0086 1] Bus : 00 +[057h 0087 1] Source : 09 +[058h 0088 4] Interrupt : 00000009 +[05Ch 0092 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[05Eh 0094 1] Subtable Type : 02 [Interrupt Source Override] +[05Fh 0095 1] Length : 0A +[060h 0096 1] Bus : 00 +[061h 0097 1] Source : 0A +[062h 0098 4] Interrupt : 0000000A +[066h 0102 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[068h 0104 1] Subtable Type : 02 [Interrupt Source Override] +[069h 0105 1] Length : 0A +[06Ah 0106 1] Bus : 00 +[06Bh 0107 1] Source : 0B +[06Ch 0108 4] Interrupt : 0000000B +[070h 0112 2] Flags (decoded below) : 000D + Polarity : 1 + Trigger Mode : 3 + +[072h 0114 1] Subtable Type : 04 [Local APIC NMI] +[073h 0115 1] Length : 06 +[074h 0116 1] Processor ID : FF +[075h 0117 2] Flags (decoded below) : 0000 + Polarity : 0 + Trigger Mode : 0 +[077h 0119 1] Interrupt Input LINT : 01 + +Raw Table Data: Length 120 (0x78) + + 0000: 41 50 49 43 78 00 00 00 01 ED 42 4F 43 48 53 20 // APICx.....BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 E0 FE 01 00 00 00 00 08 00 00 // ................ + 0030: 01 00 00 00 01 0C 00 00 00 00 C0 FE 00 00 00 00 // ................ + 0040: 02 0A 00 00 02 00 00 00 00 00 02 0A 00 05 05 00 // ................ + 0050: 00 00 0D 00 02 0A 00 09 09 00 00 00 0D 00 02 0A // ................ + 0060: 00 0A 0A 00 00 00 0D 00 02 0A 00 0B 0B 00 00 00 // ................ + 0070: 0D 00 04 06 FF 00 00 01 // ........ diff --git a/tests/data/acpi/q35/DSDT b/tests/data/acpi/q35/DSDT index bba8884073..e7414e7856 100644 --- a/tests/data/acpi/q35/DSDT +++ b/tests/data/acpi/q35/DSDT Binary files differdiff --git a/tests/data/acpi/q35/DSDT.acpihmat b/tests/data/acpi/q35/DSDT.acpihmat index 9cac92418b..88434da261 100644 --- a/tests/data/acpi/q35/DSDT.acpihmat +++ b/tests/data/acpi/q35/DSDT.acpihmat Binary files differdiff --git a/tests/data/acpi/q35/DSDT.acpihmat.dsl b/tests/data/acpi/q35/DSDT.acpihmat.dsl new file mode 100644 index 0000000000..a9e0d4144e --- /dev/null +++ b/tests/data/acpi/q35/DSDT.acpihmat.dsl @@ -0,0 +1,3436 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.acpihmat, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000232A (9002) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x79 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x02) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x00000001C0000000, // Range Minimum + 0x00000009BFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.bridge b/tests/data/acpi/q35/DSDT.bridge index f08b7245f5..118476ff61 100644 --- a/tests/data/acpi/q35/DSDT.bridge +++ b/tests/data/acpi/q35/DSDT.bridge Binary files differdiff --git a/tests/data/acpi/q35/DSDT.bridge.dsl b/tests/data/acpi/q35/DSDT.bridge.dsl new file mode 100644 index 0000000000..51fbeb729d --- /dev/null +++ b/tests/data/acpi/q35/DSDT.bridge.dsl @@ -0,0 +1,3141 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.bridge, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001E0F (7695) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x4B + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.cphp b/tests/data/acpi/q35/DSDT.cphp index 57d859cef9..69c5edf620 100644 --- a/tests/data/acpi/q35/DSDT.cphp +++ b/tests/data/acpi/q35/DSDT.cphp Binary files differdiff --git a/tests/data/acpi/q35/DSDT.cphp.dsl b/tests/data/acpi/q35/DSDT.cphp.dsl new file mode 100644 index 0000000000..d3677e802c --- /dev/null +++ b/tests/data/acpi/q35/DSDT.cphp.dsl @@ -0,0 +1,3283 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.cphp, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001FCD (8141) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x25 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (C002, Arg1) + } + + If ((Arg0 == 0x03)) + { + Notify (C003, Arg1) + } + + If ((Arg0 == 0x04)) + { + Notify (C004, Arg1) + } + + If ((Arg0 == 0x05)) + { + Notify (C005, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C002, 0x02, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x02)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x02) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x02, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C003, 0x03, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x03)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x03, 0x04, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x03) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x03, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C004, 0x04, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x04)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x04, 0x05, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x04) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x04, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C005, 0x05, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x05)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x05, 0x06, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x05) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x05, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.dimmpxm b/tests/data/acpi/q35/DSDT.dimmpxm index 9d5bd5744e..af41acba6e 100644 --- a/tests/data/acpi/q35/DSDT.dimmpxm +++ b/tests/data/acpi/q35/DSDT.dimmpxm Binary files differdiff --git a/tests/data/acpi/q35/DSDT.dimmpxm.dsl b/tests/data/acpi/q35/DSDT.dimmpxm.dsl new file mode 100644 index 0000000000..9cab76729e --- /dev/null +++ b/tests/data/acpi/q35/DSDT.dimmpxm.dsl @@ -0,0 +1,3535 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00002473 (9331) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xEE + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + External (_SB_.NVDR, UnknownObj) + + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + + If ((Arg0 == One)) + { + Notify (C001, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (C002, Arg1) + } + + If ((Arg0 == 0x03)) + { + Notify (C003, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + + Processor (C001, 0x01, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (One)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x01, 0x01, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (One) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (One, Arg0, Arg1, Arg2) + } + + Name (_PXM, One) // _PXM: Device Proximity + } + + Processor (C002, 0x02, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x02)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x02, 0x02, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x02) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x02, Arg0, Arg1, Arg2) + } + + Name (_PXM, 0x02) // _PXM: Device Proximity + } + + Processor (C003, 0x03, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (0x03)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x03, 0x03, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + CEJ0 (0x03) + } + + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (0x03, Arg0, Arg1, Arg2) + } + + Name (_PXM, 0x03) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + Method (_E04, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + Notify (\_SB.NVDR, 0x80) // Status Change + } + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x00000009FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.dsl b/tests/data/acpi/q35/DSDT.dsl new file mode 100644 index 0000000000..5adfe001c7 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.dsl @@ -0,0 +1,3351 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.tis, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000020D2 (8402) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xF4 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Name (CNEW, Package (0xFF){}) + Local3 = Zero + Local4 = One + While ((Local4 == One)) + { + Local4 = Zero + Local0 = One + Local1 = Zero + While (((Local0 == One) && (Local3 < One))) + { + Local0 = Zero + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CDAT < Local3)) + { + Break + } + + If ((Local1 == 0xFF)) + { + Local4 = One + Break + } + + Local3 = \_SB.PCI0.PRES.CDAT + If ((\_SB.PCI0.PRES.CINS == One)) + { + CNEW [Local1] = Local3 + Local1++ + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (Local3, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + + Local3++ + } + + Local2 = Zero + While ((Local2 < Local1)) + { + Local3 = DerefOf (CNEW [Local2]) + CTFY (Local3, One) + Debug = Local3 + \_SB.PCI0.PRES.CSEL = Local3 + \_SB.PCI0.PRES.CINS = One + Local2++ + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (TPM) + { + Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + OperationRegion (TPP2, SystemMemory, 0xFED45100, 0x5A) + Field (TPP2, AnyAcc, NoLock, Preserve) + { + PPIN, 8, + PPIP, 32, + PPRP, 32, + PPRQ, 32, + PPRM, 32, + LPPR, 32 + } + + OperationRegion (TPP3, SystemMemory, 0xFED4515A, One) + Field (TPP3, ByteAcc, NoLock, Preserve) + { + MOVV, 8 + } + + Method (TPFN, 1, Serialized) + { + If ((Arg0 >= 0x0100)) + { + Return (Zero) + } + + OperationRegion (TPP1, SystemMemory, (0xFED45000 + Arg0), One) + Field (TPP1, ByteAcc, NoLock, Preserve) + { + TPPF, 8 + } + + Return (TPPF) /* \_SB_.PCI0.TPM_.TPFN.TPPF */ + } + + Name (TPM2, Package (0x02) + { + Zero, + Zero + }) + Name (TPM3, Package (0x03) + { + Zero, + Zero, + Zero + }) + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + + If ((Arg2 == One)) + { + Return ("1.3") + } + + If ((Arg2 == 0x02)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + If (((Local1 & 0x07) == Zero)) + { + Return (One) + } + + PPRQ = Local0 + PPRM = Zero + Return (Zero) + } + + If ((Arg2 == 0x03)) + { + If ((Arg1 == One)) + { + TPM2 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */ + Return (TPM2) /* \_SB_.PCI0.TPM_.TPM2 */ + } + + If ((Arg1 == 0x02)) + { + TPM3 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */ + TPM3 [0x02] = PPRM /* \_SB_.PCI0.TPM_.PPRM */ + Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */ + } + } + + If ((Arg2 == 0x04)) + { + Return (0x02) + } + + If ((Arg2 == 0x05)) + { + TPM3 [One] = LPPR /* \_SB_.PCI0.TPM_.LPPR */ + TPM3 [0x02] = PPRP /* \_SB_.PCI0.TPM_.PPRP */ + Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */ + } + + If ((Arg2 == 0x06)) + { + Return (0x03) + } + + If ((Arg2 == 0x07)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + If (((Local1 & 0x07) == Zero)) + { + Return (One) + } + + If (((Local1 & 0x07) == 0x02)) + { + Return (0x03) + } + + If ((Arg1 == One)) + { + PPRQ = Local0 + PPRM = Zero + } + + If ((Arg1 == 0x02)) + { + PPRQ = Local0 + PPRM = DerefOf (Arg3 [One]) + } + + Return (Zero) + } + + If ((Arg2 == 0x08)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + Return ((Local1 & 0x07)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + If ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + + If ((Arg2 == One)) + { + Local0 = DerefOf (Arg3 [Zero]) + MOVV = Local0 + Return (Zero) + } + } + } + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.ipmibt b/tests/data/acpi/q35/DSDT.ipmibt index 5cd11de6a8..a650c3041a 100644 --- a/tests/data/acpi/q35/DSDT.ipmibt +++ b/tests/data/acpi/q35/DSDT.ipmibt Binary files differdiff --git a/tests/data/acpi/q35/DSDT.ipmibt.dsl b/tests/data/acpi/q35/DSDT.ipmibt.dsl new file mode 100644 index 0000000000..63c1140a61 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.ipmibt.dsl @@ -0,0 +1,3156 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.ipmibt, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001E49 (7753) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0xDF + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (MI1) + { + Name (_HID, EisaId ("IPI0001")) // _HID: Hardware ID + Name (_STR, "ipmi_bt") // _STR: Description String + Name (_UID, One) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x00E4, // Range Minimum + 0x00E6, // Range Maximum + 0x01, // Alignment + 0x03, // Length + ) + IRQNoFlags () + {5} + }) + Name (_IFT, 0x03) // _IFT: IPMI Interface Type + Name (_SRV, 0x0200) // _SRV: IPMI Spec Revision + } + + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.memhp b/tests/data/acpi/q35/DSDT.memhp index 05a7a73ec4..85598ca3f6 100644 --- a/tests/data/acpi/q35/DSDT.memhp +++ b/tests/data/acpi/q35/DSDT.memhp Binary files differdiff --git a/tests/data/acpi/q35/DSDT.memhp.dsl b/tests/data/acpi/q35/DSDT.memhp.dsl new file mode 100644 index 0000000000..18cea090e6 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.memhp.dsl @@ -0,0 +1,3442 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.memhp, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000234D (9037) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x9D + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x00000009FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.mmio64 b/tests/data/acpi/q35/DSDT.mmio64 index efd3f1188f..092fdc3262 100644 --- a/tests/data/acpi/q35/DSDT.mmio64 +++ b/tests/data/acpi/q35/DSDT.mmio64 Binary files differdiff --git a/tests/data/acpi/q35/DSDT.mmio64.dsl b/tests/data/acpi/q35/DSDT.mmio64.dsl new file mode 100644 index 0000000000..a724c886e8 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.mmio64.dsl @@ -0,0 +1,3377 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.mmio64, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00002268 (8808) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x59 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Device (\_SB.PCI0.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0A00, // Range Minimum + 0x0A00, // Range Maximum + 0x00, // Alignment + 0x18, // Length + ) + }) + OperationRegion (HPMR, SystemIO, 0x0A00, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, One) + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.PCI0.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.PCI0.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y01._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y02, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y02._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + } + } + + Method (\_GPE._E03, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.MHPC.MSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000200000000, // Range Minimum + 0x00000009FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Device (S10) + { + Name (_ADR, 0x00020000) // _ADR: Address + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.numamem b/tests/data/acpi/q35/DSDT.numamem index 1978b55f12..899946255b 100644 --- a/tests/data/acpi/q35/DSDT.numamem +++ b/tests/data/acpi/q35/DSDT.numamem Binary files differdiff --git a/tests/data/acpi/q35/DSDT.numamem.dsl b/tests/data/acpi/q35/DSDT.numamem.dsl new file mode 100644 index 0000000000..e76de462f0 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.numamem.dsl @@ -0,0 +1,3138 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.numamem, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001E04 (7684) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x55 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + + Name (_PXM, Zero) // _PXM: Device Proximity + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + } + } +} + diff --git a/tests/data/acpi/q35/DSDT.tis b/tests/data/acpi/q35/DSDT.tis index 638de38726..08802fbd12 100644 --- a/tests/data/acpi/q35/DSDT.tis +++ b/tests/data/acpi/q35/DSDT.tis Binary files differdiff --git a/tests/data/acpi/q35/DSDT.tis.dsl b/tests/data/acpi/q35/DSDT.tis.dsl new file mode 100644 index 0000000000..a43e36bfe3 --- /dev/null +++ b/tests/data/acpi/q35/DSDT.tis.dsl @@ -0,0 +1,3321 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/DSDT.tis, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x0000205B (8283) + * Revision 0x01 **** 32-bit table (V1), no 64-bit math support + * Checksum 0x84 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 1, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\) + { + OperationRegion (DBG, SystemIO, 0x0402, One) + Field (DBG, ByteAcc, NoLock, Preserve) + { + DBGB, 8 + } + + Method (DBUG, 1, NotSerialized) + { + ToHexString (Arg0, Local0) + ToBuffer (Local0, Local0) + Local1 = (SizeOf (Local0) - One) + Local2 = Zero + While ((Local2 < Local1)) + { + DBGB = DerefOf (Local0 [Local2]) + Local2++ + } + + DBGB = 0x0A + } + } + + Scope (_SB) + { + Device (PCI0) + { + Name (_HID, EisaId ("PNP0A08") /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A03") /* PCI Bus */) // _CID: Compatible ID + Name (_ADR, Zero) // _ADR: Address + Name (_UID, Zero) // _UID: Unique ID + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + Local0 = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + Local0 &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != Local0)) + { + CDW1 |= 0x10 + } + + CDW3 = Local0 + } + Else + { + CDW1 |= 0x04 + } + + Return (Arg3) + } + } + } + + Scope (_SB) + { + Device (HPET) + { + Name (_HID, EisaId ("PNP0103") /* HPET System Timer */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + OperationRegion (HPTM, SystemMemory, 0xFED00000, 0x0400) + Field (HPTM, DWordAcc, Lock, Preserve) + { + VEND, 32, + PRD, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Local0 = VEND /* \_SB_.HPET.VEND */ + Local1 = PRD /* \_SB_.HPET.PRD_ */ + Local0 >>= 0x10 + If (((Local0 == Zero) || (Local0 == 0xFFFF))) + { + Return (Zero) + } + + If (((Local1 == Zero) || (Local1 > 0x05F5E100))) + { + Return (Zero) + } + + Return (0x0F) + } + + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadOnly, + 0xFED00000, // Address Base + 0x00000400, // Address Length + ) + }) + } + } + + Scope (_SB.PCI0) + { + Device (ISA) + { + Name (_ADR, 0x001F0000) // _ADR: Address + OperationRegion (PIRQ, PCI_Config, 0x60, 0x0C) + } + } + + Scope (_SB.PCI0.ISA) + { + Device (KBD) + { + Name (_HID, EisaId ("PNP0303") /* IBM Enhanced Keyboard (101/102-key, PS/2 Mouse) */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0060, // Range Minimum + 0x0060, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IO (Decode16, + 0x0064, // Range Minimum + 0x0064, // Range Maximum + 0x01, // Alignment + 0x01, // Length + ) + IRQNoFlags () + {1} + }) + } + + Device (MOU) + { + Name (_HID, EisaId ("PNP0F13") /* PS/2 Mouse */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IRQNoFlags () + {12} + }) + } + + Device (LPT1) + { + Name (_HID, EisaId ("PNP0400") /* Standard LPT Parallel Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0378, // Range Minimum + 0x0378, // Range Maximum + 0x08, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {7} + }) + } + + Device (COM1) + { + Name (_HID, EisaId ("PNP0501") /* 16550A-compatible COM Serial Port */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x03F8, // Range Minimum + 0x03F8, // Range Maximum + 0x00, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {4} + }) + } + + Device (RTC) + { + Name (_HID, EisaId ("PNP0B00") /* AT Real-Time Clock */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0070, // Range Minimum + 0x0070, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + IRQNoFlags () + {8} + }) + } + } + + Name (PICF, Zero) + Method (_PIC, 1, NotSerialized) // _PIC: Interrupt Model + { + PICF = Arg0 + } + + Scope (_SB) + { + Scope (PCI0) + { + Name (PRTP, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + LNKD, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + LNKE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + LNKF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + LNKG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + LNKH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + LNKA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + LNKB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + LNKC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + LNKD, + Zero + } + }) + Name (PRTA, Package (0x80) + { + Package (0x04) + { + 0xFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSID, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSIE, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSIF, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSIG, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSIH, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSIA, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSIB, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSIC, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSID, + Zero + } + }) + Method (_PRT, 0, NotSerialized) // _PRT: PCI Routing Table + { + If ((PICF == Zero)) + { + Return (PRTP) /* \_SB_.PCI0.PRTP */ + } + Else + { + Return (PRTA) /* \_SB_.PCI0.PRTA */ + } + } + } + + Field (PCI0.ISA.PIRQ, ByteAcc, NoLock, Preserve) + { + PRQA, 8, + PRQB, 8, + PRQC, 8, + PRQD, 8, + Offset (0x08), + PRQE, 8, + PRQF, 8, + PRQG, 8, + PRQH, 8 + } + + Method (IQST, 1, NotSerialized) + { + If ((0x80 & Arg0)) + { + Return (0x09) + } + + Return (0x0B) + } + + Method (IQCR, 1, Serialized) + { + Name (PRR0, ResourceTemplate () + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, _Y00) + { + 0x00000000, + } + }) + CreateDWordField (PRR0, \_SB.IQCR._Y00._INT, PRRI) // _INT: Interrupts + PRRI = (Arg0 & 0x0F) + Return (PRR0) /* \_SB_.IQCR.PRR0 */ + } + + Device (LNKA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQA)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQA |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQA)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQA = PRRI /* \_SB_.LNKA._SRS.PRRI */ + } + } + + Device (LNKB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQB)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQB |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQB)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQB = PRRI /* \_SB_.LNKB._SRS.PRRI */ + } + } + + Device (LNKC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQC)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQC |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQC)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQC = PRRI /* \_SB_.LNKC._SRS.PRRI */ + } + } + + Device (LNKD) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQD)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQD |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQD)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQD = PRRI /* \_SB_.LNKD._SRS.PRRI */ + } + } + + Device (LNKE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQE)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQE |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQE)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQE = PRRI /* \_SB_.LNKE._SRS.PRRI */ + } + } + + Device (LNKF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQF)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQF |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQF)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQF = PRRI /* \_SB_.LNKF._SRS.PRRI */ + } + } + + Device (LNKG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQG)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQG |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQG)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQG = PRRI /* \_SB_.LNKG._SRS.PRRI */ + } + } + + Device (LNKH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000005, + 0x0000000A, + 0x0000000B, + } + }) + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (IQST (PRQH)) + } + + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + PRQH |= 0x80 + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (IQCR (PRQH)) + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + CreateDWordField (Arg0, 0x05, PRRI) + PRQH = PRRI /* \_SB_.LNKH._SRS.PRRI */ + } + } + + Device (GSIA) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000010, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIB) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000011, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIC) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000012, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSID) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000013, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIE) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000014, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIF) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000015, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIG) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000016, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSIH) + { + Name (_HID, EisaId ("PNP0C0F") /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Shared, ,, ) + { + 0x00000017, + } + }) + Method (_DIS, 0, NotSerialized) // _DIS: Disable Device + { + } + + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + } + + Scope (_SB.PCI0) + { + Device (SMB0) + { + Name (_ADR, 0x001F0003) // _ADR: Address + } + } + + Scope (_SB) + { + Device (\_SB.PCI0.PRES) + { + Name (_HID, EisaId ("PNP0A06") /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "CPU Hotplug resources") // _UID: Unique ID + Mutex (CPLK, 0x00) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0CD8, // Range Minimum + 0x0CD8, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + OperationRegion (PRST, SystemIO, 0x0CD8, 0x0C) + Field (PRST, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x04), + CPEN, 1, + CINS, 1, + CRMV, 1, + CEJ0, 1, + Offset (0x05), + CCMD, 8 + } + + Field (PRST, DWordAcc, NoLock, Preserve) + { + CSEL, 32, + Offset (0x08), + CDAT, 32 + } + + Method (_INI, 0, Serialized) // _INI: Initialize + { + CSEL = Zero + } + } + + Device (\_SB.CPUS) + { + Name (_HID, "ACPI0010" /* Processor Container Device */) // _HID: Hardware ID + Name (_CID, EisaId ("PNP0A05") /* Generic Container Device */) // _CID: Compatible ID + Method (CTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (C000, Arg1) + } + } + + Method (CSTA, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + Local0 = Zero + If ((\_SB.PCI0.PRES.CPEN == One)) + { + Local0 = 0x0F + } + + Release (\_SB.PCI0.PRES.CPLK) + Return (Local0) + } + + Method (CEJ0, 1, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CEJ0 = One + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (CSCN, 0, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + Local0 = One + While ((Local0 == One)) + { + Local0 = Zero + \_SB.PCI0.PRES.CCMD = Zero + If ((\_SB.PCI0.PRES.CINS == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, One) + \_SB.PCI0.PRES.CINS = One + Local0 = One + } + ElseIf ((\_SB.PCI0.PRES.CRMV == One)) + { + CTFY (\_SB.PCI0.PRES.CDAT, 0x03) + \_SB.PCI0.PRES.CRMV = One + Local0 = One + } + } + + Release (\_SB.PCI0.PRES.CPLK) + } + + Method (COST, 4, Serialized) + { + Acquire (\_SB.PCI0.PRES.CPLK, 0xFFFF) + \_SB.PCI0.PRES.CSEL = Arg0 + \_SB.PCI0.PRES.CCMD = One + \_SB.PCI0.PRES.CDAT = Arg1 + \_SB.PCI0.PRES.CCMD = 0x02 + \_SB.PCI0.PRES.CDAT = Arg2 + Release (\_SB.PCI0.PRES.CPLK) + } + + Processor (C000, 0x00, 0x00000000, 0x00) + { + Method (_STA, 0, Serialized) // _STA: Status + { + Return (CSTA (Zero)) + } + + Name (_MAT, Buffer (0x08) // _MAT: Multiple APIC Table Entry + { + 0x00, 0x08, 0x00, 0x00, 0x01, 0x00, 0x00, 0x00 // ........ + }) + Method (_OST, 3, Serialized) // _OST: OSPM Status Indication + { + COST (Zero, Arg0, Arg1, Arg2) + } + } + } + } + + Method (\_GPE._E02, 0, NotSerialized) // _Exx: Edge-Triggered GPE, xx=0x00-0xFF + { + \_SB.CPUS.CSCN () + } + + Scope (_GPE) + { + Name (_HID, "ACPI0006" /* GPE Block Device */) // _HID: Hardware ID + } + + Scope (\_SB.PCI0) + { + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + IO (Decode16, + 0x0CF8, // Range Minimum + 0x0CF8, // Range Maximum + 0x01, // Alignment + 0x08, // Length + ) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x0CF7, // Range Maximum + 0x0000, // Translation Offset + 0x0CF8, // Length + ,, , TypeStatic, DenseTranslation) + WordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, // Granularity + 0x0D00, // Range Minimum + 0xFFFF, // Range Maximum + 0x0000, // Translation Offset + 0xF300, // Length + ,, , TypeStatic, DenseTranslation) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x000A0000, // Range Minimum + 0x000BFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x00020000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x08000000, // Range Minimum + 0xAFFFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0xA8000000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0xC0000000, // Range Minimum + 0xFEBFFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x3EC00000, // Length + ,, , AddressRangeMemory, TypeStatic) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000100000000, // Range Minimum + 0x00000008FFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000800000000, // Length + ,, , AddressRangeMemory, TypeStatic) + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + Device (GPE0) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "GPE0 resources") // _UID: Unique ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0620, // Range Minimum + 0x0620, // Range Maximum + 0x01, // Alignment + 0x10, // Length + ) + }) + } + } + + Scope (\) + { + Name (_S3, Package (0x04) // _S3_: S3 System State + { + One, + One, + Zero, + Zero + }) + Name (_S4, Package (0x04) // _S4_: S4 System State + { + 0x02, + 0x02, + Zero, + Zero + }) + Name (_S5, Package (0x04) // _S5_: S5 System State + { + Zero, + Zero, + Zero, + Zero + }) + } + + Scope (\_SB.PCI0) + { + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + IO (Decode16, + 0x0510, // Range Minimum + 0x0510, // Range Maximum + 0x01, // Alignment + 0x0C, // Length + ) + }) + } + } + + Scope (\_SB) + { + Scope (PCI0) + { + Device (S00) + { + Name (_ADR, Zero) // _ADR: Address + } + + Device (S08) + { + Name (_ADR, 0x00010000) // _ADR: Address + Method (_S1D, 0, NotSerialized) // _S1D: S1 Device State + { + Return (Zero) + } + + Method (_S2D, 0, NotSerialized) // _S2D: S2 Device State + { + Return (Zero) + } + + Method (_S3D, 0, NotSerialized) // _S3D: S3 Device State + { + Return (Zero) + } + } + + Method (PCNT, 0, NotSerialized) + { + } + + Device (TPM) + { + Name (_HID, "MSFT0101" /* TPM 2.0 Security Device */) // _HID: Hardware ID + Name (_STA, 0x0F) // _STA: Status + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0xFED40000, // Address Base + 0x00005000, // Address Length + ) + }) + OperationRegion (TPP2, SystemMemory, 0xFED45100, 0x5A) + Field (TPP2, AnyAcc, NoLock, Preserve) + { + PPIN, 8, + PPIP, 32, + PPRP, 32, + PPRQ, 32, + PPRM, 32, + LPPR, 32 + } + + OperationRegion (TPP3, SystemMemory, 0xFED4515A, One) + Field (TPP3, ByteAcc, NoLock, Preserve) + { + MOVV, 8 + } + + Method (TPFN, 1, Serialized) + { + If ((Arg0 >= 0x0100)) + { + Return (Zero) + } + + OperationRegion (TPP1, SystemMemory, (0xFED45000 + Arg0), One) + Field (TPP1, ByteAcc, NoLock, Preserve) + { + TPPF, 8 + } + + Return (TPPF) /* \_SB_.PCI0.TPM_.TPFN.TPPF */ + } + + Name (TPM2, Package (0x02) + { + Zero, + Zero + }) + Name (TPM3, Package (0x03) + { + Zero, + Zero, + Zero + }) + Method (_DSM, 4, Serialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("3dddfaa6-361b-4eb4-a424-8d10089d1653") /* Physical Presence Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (0x02) + { + 0xFF, 0x01 // .. + }) + } + + If ((Arg2 == One)) + { + Return ("1.3") + } + + If ((Arg2 == 0x02)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + If (((Local1 & 0x07) == Zero)) + { + Return (One) + } + + PPRQ = Local0 + PPRM = Zero + Return (Zero) + } + + If ((Arg2 == 0x03)) + { + If ((Arg1 == One)) + { + TPM2 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */ + Return (TPM2) /* \_SB_.PCI0.TPM_.TPM2 */ + } + + If ((Arg1 == 0x02)) + { + TPM3 [One] = PPRQ /* \_SB_.PCI0.TPM_.PPRQ */ + TPM3 [0x02] = PPRM /* \_SB_.PCI0.TPM_.PPRM */ + Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */ + } + } + + If ((Arg2 == 0x04)) + { + Return (0x02) + } + + If ((Arg2 == 0x05)) + { + TPM3 [One] = LPPR /* \_SB_.PCI0.TPM_.LPPR */ + TPM3 [0x02] = PPRP /* \_SB_.PCI0.TPM_.PPRP */ + Return (TPM3) /* \_SB_.PCI0.TPM_.TPM3 */ + } + + If ((Arg2 == 0x06)) + { + Return (0x03) + } + + If ((Arg2 == 0x07)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + If (((Local1 & 0x07) == Zero)) + { + Return (One) + } + + If (((Local1 & 0x07) == 0x02)) + { + Return (0x03) + } + + If ((Arg1 == One)) + { + PPRQ = Local0 + PPRM = Zero + } + + If ((Arg1 == 0x02)) + { + PPRQ = Local0 + PPRM = DerefOf (Arg3 [One]) + } + + Return (Zero) + } + + If ((Arg2 == 0x08)) + { + Local0 = DerefOf (Arg3 [Zero]) + Local1 = TPFN (Local0) + Return ((Local1 & 0x07)) + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + If ((Arg0 == ToUUID ("376054ed-cc13-4675-901c-4756d7f2d45d"))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x03 // . + }) + } + + If ((Arg2 == One)) + { + Local0 = DerefOf (Arg3 [Zero]) + MOVV = Local0 + Return (Zero) + } + } + } + } + } + } +} + diff --git a/tests/data/acpi/q35/FACP.acpihmat b/tests/data/acpi/q35/FACP.acpihmat new file mode 100644 index 0000000000..72c9d97902 --- /dev/null +++ b/tests/data/acpi/q35/FACP.acpihmat Binary files differdiff --git a/tests/data/acpi/q35/FACP.acpihmat.dsl b/tests/data/acpi/q35/FACP.acpihmat.dsl new file mode 100644 index 0000000000..29466227a1 --- /dev/null +++ b/tests/data/acpi/q35/FACP.acpihmat.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.bridge b/tests/data/acpi/q35/FACP.bridge new file mode 100644 index 0000000000..72c9d97902 --- /dev/null +++ b/tests/data/acpi/q35/FACP.bridge Binary files differdiff --git a/tests/data/acpi/q35/FACP.bridge.dsl b/tests/data/acpi/q35/FACP.bridge.dsl new file mode 100644 index 0000000000..2416f4391a --- /dev/null +++ b/tests/data/acpi/q35/FACP.bridge.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.cphp b/tests/data/acpi/q35/FACP.cphp new file mode 100644 index 0000000000..72c9d97902 --- /dev/null +++ b/tests/data/acpi/q35/FACP.cphp Binary files differdiff --git a/tests/data/acpi/q35/FACP.cphp.dsl b/tests/data/acpi/q35/FACP.cphp.dsl new file mode 100644 index 0000000000..96ee322b53 --- /dev/null +++ b/tests/data/acpi/q35/FACP.cphp.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.dimmpxm b/tests/data/acpi/q35/FACP.dimmpxm new file mode 100644 index 0000000000..72c9d97902 --- /dev/null +++ b/tests/data/acpi/q35/FACP.dimmpxm Binary files differdiff --git a/tests/data/acpi/q35/FACP.dimmpxm.dsl b/tests/data/acpi/q35/FACP.dimmpxm.dsl new file mode 100644 index 0000000000..14f7c181b8 --- /dev/null +++ b/tests/data/acpi/q35/FACP.dimmpxm.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.dsl b/tests/data/acpi/q35/FACP.dsl new file mode 100644 index 0000000000..1a8893b320 --- /dev/null +++ b/tests/data/acpi/q35/FACP.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.ipmibt b/tests/data/acpi/q35/FACP.ipmibt new file mode 100644 index 0000000000..72c9d97902 --- /dev/null +++ b/tests/data/acpi/q35/FACP.ipmibt Binary files differdiff --git a/tests/data/acpi/q35/FACP.ipmibt.dsl b/tests/data/acpi/q35/FACP.ipmibt.dsl new file mode 100644 index 0000000000..b6e56c5af2 --- /dev/null +++ b/tests/data/acpi/q35/FACP.ipmibt.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.memhp b/tests/data/acpi/q35/FACP.memhp new file mode 100644 index 0000000000..72c9d97902 --- /dev/null +++ b/tests/data/acpi/q35/FACP.memhp Binary files differdiff --git a/tests/data/acpi/q35/FACP.memhp.dsl b/tests/data/acpi/q35/FACP.memhp.dsl new file mode 100644 index 0000000000..2405fcdca8 --- /dev/null +++ b/tests/data/acpi/q35/FACP.memhp.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.mmio64 b/tests/data/acpi/q35/FACP.mmio64 new file mode 100644 index 0000000000..72c9d97902 --- /dev/null +++ b/tests/data/acpi/q35/FACP.mmio64 Binary files differdiff --git a/tests/data/acpi/q35/FACP.mmio64.dsl b/tests/data/acpi/q35/FACP.mmio64.dsl new file mode 100644 index 0000000000..9f51c42156 --- /dev/null +++ b/tests/data/acpi/q35/FACP.mmio64.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.numamem b/tests/data/acpi/q35/FACP.numamem new file mode 100644 index 0000000000..72c9d97902 --- /dev/null +++ b/tests/data/acpi/q35/FACP.numamem Binary files differdiff --git a/tests/data/acpi/q35/FACP.numamem.dsl b/tests/data/acpi/q35/FACP.numamem.dsl new file mode 100644 index 0000000000..a5854c1a69 --- /dev/null +++ b/tests/data/acpi/q35/FACP.numamem.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACP.tis b/tests/data/acpi/q35/FACP.tis new file mode 100644 index 0000000000..72c9d97902 --- /dev/null +++ b/tests/data/acpi/q35/FACP.tis Binary files differdiff --git a/tests/data/acpi/q35/FACP.tis.dsl b/tests/data/acpi/q35/FACP.tis.dsl new file mode 100644 index 0000000000..22f6a34466 --- /dev/null +++ b/tests/data/acpi/q35/FACP.tis.dsl @@ -0,0 +1,179 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACP.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 000000F4 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 1F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 01 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0009 +[030h 0048 4] SMI Command Port : 000000B2 +[034h 0052 1] ACPI Enable Value : 02 +[035h 0053 1] ACPI Disable Value : 03 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000600 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000604 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000608 +[050h 0080 4] GPE0 Block Address : 00000620 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 04 +[059h 0089 1] PM1 Control Block Length : 02 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 04 +[05Ch 0092 1] GPE0 Block Length : 10 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0FFF +[062h 0098 2] C3 Latency : 0FFF +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 32 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 000084A5 + WBINVD instruction is operational (V1) : 1 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 1 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 1 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 1 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 1 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 1 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 0 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 01 [SystemIO] +[075h 0117 1] Bit Width : 08 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000CF9 + +[080h 0128 1] Value to cause reset : 0F +[081h 0129 2] ARM Flags (decoded below) : 0000 + PSCI Compliant : 0 + Must use HVC for PSCI : 0 + +[083h 0131 1] FADT Minor Revision : 00 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 01 [SystemIO] +[095h 0149 1] Bit Width : 20 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000600 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 01 [SystemIO] +[0ADh 0173 1] Bit Width : 10 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000604 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 01 [SystemIO] +[0D1h 0209 1] Bit Width : 20 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000608 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 01 [SystemIO] +[0DDh 0221 1] Bit Width : 80 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000620 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +Raw Table Data: Length 244 (0xF4) + + 0000: 46 41 43 50 F4 00 00 00 03 1F 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 01 00 09 00 // ................ + 0030: B2 00 00 00 02 03 00 00 00 06 00 00 00 00 00 00 // ................ + 0040: 04 06 00 00 00 00 00 00 00 00 00 00 08 06 00 00 // ................ + 0050: 20 06 00 00 00 00 00 00 04 02 00 04 10 00 00 00 // ............... + 0060: FF 0F FF 0F 00 00 00 00 00 00 00 00 32 00 00 00 // ............2... + 0070: A5 84 00 00 01 08 00 00 F9 0C 00 00 00 00 00 00 // ................ + 0080: 0F 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 01 20 00 00 00 06 00 00 00 00 00 00 // ..... .......... + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 01 10 00 00 // ................ + 00B0: 04 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 20 00 00 08 06 00 00 00 00 00 00 01 80 00 00 // . .............. + 00E0: 20 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ............... + 00F0: 00 00 00 00 // .... diff --git a/tests/data/acpi/q35/FACS.acpihmat b/tests/data/acpi/q35/FACS.acpihmat new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/q35/FACS.acpihmat Binary files differdiff --git a/tests/data/acpi/q35/FACS.acpihmat.dsl b/tests/data/acpi/q35/FACS.acpihmat.dsl new file mode 100644 index 0000000000..0bd98653ce --- /dev/null +++ b/tests/data/acpi/q35/FACS.acpihmat.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.bridge b/tests/data/acpi/q35/FACS.bridge new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/q35/FACS.bridge Binary files differdiff --git a/tests/data/acpi/q35/FACS.bridge.dsl b/tests/data/acpi/q35/FACS.bridge.dsl new file mode 100644 index 0000000000..116dce1f2d --- /dev/null +++ b/tests/data/acpi/q35/FACS.bridge.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.cphp b/tests/data/acpi/q35/FACS.cphp new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/q35/FACS.cphp Binary files differdiff --git a/tests/data/acpi/q35/FACS.cphp.dsl b/tests/data/acpi/q35/FACS.cphp.dsl new file mode 100644 index 0000000000..580d502491 --- /dev/null +++ b/tests/data/acpi/q35/FACS.cphp.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.dimmpxm b/tests/data/acpi/q35/FACS.dimmpxm new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/q35/FACS.dimmpxm Binary files differdiff --git a/tests/data/acpi/q35/FACS.dimmpxm.dsl b/tests/data/acpi/q35/FACS.dimmpxm.dsl new file mode 100644 index 0000000000..4106387866 --- /dev/null +++ b/tests/data/acpi/q35/FACS.dimmpxm.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.dsl b/tests/data/acpi/q35/FACS.dsl new file mode 100644 index 0000000000..0595b4ddb9 --- /dev/null +++ b/tests/data/acpi/q35/FACS.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.ipmibt b/tests/data/acpi/q35/FACS.ipmibt new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/q35/FACS.ipmibt Binary files differdiff --git a/tests/data/acpi/q35/FACS.ipmibt.dsl b/tests/data/acpi/q35/FACS.ipmibt.dsl new file mode 100644 index 0000000000..8c019f3475 --- /dev/null +++ b/tests/data/acpi/q35/FACS.ipmibt.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.memhp b/tests/data/acpi/q35/FACS.memhp new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/q35/FACS.memhp Binary files differdiff --git a/tests/data/acpi/q35/FACS.memhp.dsl b/tests/data/acpi/q35/FACS.memhp.dsl new file mode 100644 index 0000000000..fb6d84c152 --- /dev/null +++ b/tests/data/acpi/q35/FACS.memhp.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.mmio64 b/tests/data/acpi/q35/FACS.mmio64 new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/q35/FACS.mmio64 Binary files differdiff --git a/tests/data/acpi/q35/FACS.mmio64.dsl b/tests/data/acpi/q35/FACS.mmio64.dsl new file mode 100644 index 0000000000..1a20060749 --- /dev/null +++ b/tests/data/acpi/q35/FACS.mmio64.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.numamem b/tests/data/acpi/q35/FACS.numamem new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/q35/FACS.numamem Binary files differdiff --git a/tests/data/acpi/q35/FACS.numamem.dsl b/tests/data/acpi/q35/FACS.numamem.dsl new file mode 100644 index 0000000000..740e0bca9a --- /dev/null +++ b/tests/data/acpi/q35/FACS.numamem.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/FACS.tis b/tests/data/acpi/q35/FACS.tis new file mode 100644 index 0000000000..fc67ecc407 --- /dev/null +++ b/tests/data/acpi/q35/FACS.tis Binary files differdiff --git a/tests/data/acpi/q35/FACS.tis.dsl b/tests/data/acpi/q35/FACS.tis.dsl new file mode 100644 index 0000000000..cb35bde06c --- /dev/null +++ b/tests/data/acpi/q35/FACS.tis.dsl @@ -0,0 +1,32 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/FACS.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACS] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACS" +[004h 0004 4] Length : 00000040 +[008h 0008 4] Hardware Signature : 00000000 +[00Ch 0012 4] 32 Firmware Waking Vector : 00000000 +[010h 0016 4] Global Lock : 00000000 +[014h 0020 4] Flags (decoded below) : 00000000 + S4BIOS Support Present : 0 + 64-bit Wake Supported (V2) : 0 +[018h 0024 8] 64 Firmware Waking Vector : 0000000000000000 +[020h 0032 1] Version : 00 +[021h 0033 3] Reserved : 000000 +[024h 0036 4] OspmFlags (decoded below) : 00000000 + 64-bit Wake Env Required (V2) : 0 + +Raw Table Data: Length 64 (0x40) + + 0000: 46 41 43 53 40 00 00 00 00 00 00 00 00 00 00 00 // FACS@........... + 0010: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0020: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/HMAT.acpihmat.dsl b/tests/data/acpi/q35/HMAT.acpihmat.dsl new file mode 100644 index 0000000000..4abaa94f78 --- /dev/null +++ b/tests/data/acpi/q35/HMAT.acpihmat.dsl @@ -0,0 +1,132 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HMAT.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HMAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table] +[004h 0004 4] Table Length : 00000118 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 98 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHMAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[02Ah 0042 2] Reserved : 0000 +[02Ch 0044 4] Length : 00000028 +[030h 0048 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[032h 0050 2] Reserved1 : 0000 +[034h 0052 4] Processor Proximity Domain : 00000000 +[038h 0056 4] Memory Proximity Domain : 00000000 +[03Ch 0060 4] Reserved2 : 00000000 +[040h 0064 8] Reserved3 : 0000000000000000 +[048h 0072 8] Reserved4 : 0000000000000000 + +[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[052h 0082 2] Reserved : 0000 +[054h 0084 4] Length : 00000028 +[058h 0088 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[05Ah 0090 2] Reserved1 : 0000 +[05Ch 0092 4] Processor Proximity Domain : 00000000 +[060h 0096 4] Memory Proximity Domain : 00000001 +[064h 0100 4] Reserved2 : 00000000 +[068h 0104 8] Reserved3 : 0000000000000000 +[070h 0112 8] Reserved4 : 0000000000000000 + +[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[07Ah 0122 2] Reserved : 0000 +[07Ch 0124 4] Length : 00000030 +[080h 0128 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[081h 0129 1] Data Type : 00 +[082h 0130 2] Reserved1 : 0000 +[084h 0132 4] Initiator Proximity Domains # : 00000001 +[088h 0136 4] Target Proximity Domains # : 00000002 +[08Ch 0140 4] Reserved2 : 00000000 +[090h 0144 8] Entry Base Unit : 00000000000003E8 +[098h 0152 4] Initiator Proximity Domain List : 00000000 +[09Ch 0156 4] Target Proximity Domain List : 00000000 +[0A0h 0160 4] Target Proximity Domain List : 00000001 +[0A4h 0164 2] Entry : 0001 +[0A6h 0166 2] Entry : FFFE + +[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[0AAh 0170 2] Reserved : 0000 +[0ACh 0172 4] Length : 00000030 +[0B0h 0176 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[0B1h 0177 1] Data Type : 03 +[0B2h 0178 2] Reserved1 : 0000 +[0B4h 0180 4] Initiator Proximity Domains # : 00000001 +[0B8h 0184 4] Target Proximity Domains # : 00000002 +[0BCh 0188 4] Reserved2 : 00000000 +[0C0h 0192 8] Entry Base Unit : 0000000000000001 +[0C8h 0200 4] Initiator Proximity Domain List : 00000000 +[0CCh 0204 4] Target Proximity Domain List : 00000000 +[0D0h 0208 4] Target Proximity Domain List : 00000001 +[0D4h 0212 2] Entry : FFFE +[0D6h 0214 2] Entry : 7FFF + +[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information] +[0DAh 0218 2] Reserved : 0000 +[0DCh 0220 4] Length : 00000020 +[0E0h 0224 4] Memory Proximity Domain : 00000000 +[0E4h 0228 4] Reserved1 : 00000000 +[0E8h 0232 8] Memory Side Cache Size : 0000000000002800 +[0F0h 0240 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[0F4h 0244 2] Reserved2 : 0000 +[0F6h 0246 2] SMBIOS Handle # : 0000 + +[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information] +[0FAh 0250 2] Reserved : 0000 +[0FCh 0252 4] Length : 00000020 +[100h 0256 4] Memory Proximity Domain : 00000001 +[104h 0260 4] Reserved1 : 00000000 +[108h 0264 8] Memory Side Cache Size : 0000000000002800 +[110h 0272 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[114h 0276 2] Reserved2 : 0000 +[116h 0278 2] SMBIOS Handle # : 0000 + +Raw Table Data: Length 280 (0x118) + + 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS + 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... + 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(........... + 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0... + 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0... + 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ... + 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ... + 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 0110: 11 11 08 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HMAT.dsl b/tests/data/acpi/q35/HMAT.dsl new file mode 100644 index 0000000000..43bc9adc98 --- /dev/null +++ b/tests/data/acpi/q35/HMAT.dsl @@ -0,0 +1,132 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HMAT.acpihmat, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [HMAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HMAT" [Heterogeneous Memory Attributes Table] +[004h 0004 4] Table Length : 00000118 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 98 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHMAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[02Ah 0042 2] Reserved : 0000 +[02Ch 0044 4] Length : 00000028 +[030h 0048 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[032h 0050 2] Reserved1 : 0000 +[034h 0052 4] Processor Proximity Domain : 00000000 +[038h 0056 4] Memory Proximity Domain : 00000000 +[03Ch 0060 4] Reserved2 : 00000000 +[040h 0064 8] Reserved3 : 0000000000000000 +[048h 0072 8] Reserved4 : 0000000000000000 + +[050h 0080 2] Structure Type : 0000 [Memory Proximity Domain Attributes] +[052h 0082 2] Reserved : 0000 +[054h 0084 4] Length : 00000028 +[058h 0088 2] Flags (decoded below) : 0001 + Processor Proximity Domain Valid : 1 +[05Ah 0090 2] Reserved1 : 0000 +[05Ch 0092 4] Processor Proximity Domain : 00000000 +[060h 0096 4] Memory Proximity Domain : 00000001 +[064h 0100 4] Reserved2 : 00000000 +[068h 0104 8] Reserved3 : 0000000000000000 +[070h 0112 8] Reserved4 : 0000000000000000 + +[078h 0120 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[07Ah 0122 2] Reserved : 0000 +[07Ch 0124 4] Length : 00000030 +[080h 0128 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[081h 0129 1] Data Type : 00 +[082h 0130 2] Reserved1 : 0000 +[084h 0132 4] Initiator Proximity Domains # : 00000001 +[088h 0136 4] Target Proximity Domains # : 00000002 +[08Ch 0140 4] Reserved2 : 00000000 +[090h 0144 8] Entry Base Unit : 00000000000003E8 +[098h 0152 4] Initiator Proximity Domain List : 00000000 +[09Ch 0156 4] Target Proximity Domain List : 00000000 +[0A0h 0160 4] Target Proximity Domain List : 00000001 +[0A4h 0164 2] Entry : 0001 +[0A6h 0166 2] Entry : FFFE + +[0A8h 0168 2] Structure Type : 0001 [System Locality Latency and Bandwidth Information] +[0AAh 0170 2] Reserved : 0000 +[0ACh 0172 4] Length : 00000030 +[0B0h 0176 1] Flags (decoded below) : 00 + Memory Hierarchy : 0 +[0B1h 0177 1] Data Type : 03 +[0B2h 0178 2] Reserved1 : 0000 +[0B4h 0180 4] Initiator Proximity Domains # : 00000001 +[0B8h 0184 4] Target Proximity Domains # : 00000002 +[0BCh 0188 4] Reserved2 : 00000000 +[0C0h 0192 8] Entry Base Unit : 0000000000000001 +[0C8h 0200 4] Initiator Proximity Domain List : 00000000 +[0CCh 0204 4] Target Proximity Domain List : 00000000 +[0D0h 0208 4] Target Proximity Domain List : 00000001 +[0D4h 0212 2] Entry : FFFE +[0D6h 0214 2] Entry : 7FFF + +[0D8h 0216 2] Structure Type : 0002 [Memory Side Cache Information] +[0DAh 0218 2] Reserved : 0000 +[0DCh 0220 4] Length : 00000020 +[0E0h 0224 4] Memory Proximity Domain : 00000000 +[0E4h 0228 4] Reserved1 : 00000000 +[0E8h 0232 8] Memory Side Cache Size : 0000000000002800 +[0F0h 0240 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[0F4h 0244 2] Reserved2 : 0000 +[0F6h 0246 2] SMBIOS Handle # : 0000 + +[0F8h 0248 2] Structure Type : 0002 [Memory Side Cache Information] +[0FAh 0250 2] Reserved : 0000 +[0FCh 0252 4] Length : 00000020 +[100h 0256 4] Memory Proximity Domain : 00000001 +[104h 0260 4] Reserved1 : 00000000 +[108h 0264 8] Memory Side Cache Size : 0000000000002800 +[110h 0272 4] Cache Attributes (decoded below) : 00081111 + Total Cache Levels : 1 + Cache Level : 1 + Cache Associativity : 1 + Write Policy : 1 + Cache Line Size : 0008 +[114h 0276 2] Reserved2 : 0000 +[116h 0278 2] SMBIOS Handle # : 0000 + +Raw Table Data: Length 280 (0x118) + + 0000: 48 4D 41 54 18 01 00 00 02 98 42 4F 43 48 53 20 // HMAT......BOCHS + 0010: 42 58 50 43 48 4D 41 54 01 00 00 00 42 58 50 43 // BXPCHMAT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 28 00 00 00 // ............(... + 0030: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 28 00 00 00 01 00 00 00 00 00 00 00 // ....(........... + 0060: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 00 00 00 00 00 00 01 00 00 00 30 00 00 00 // ............0... + 0080: 00 00 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 0090: E8 03 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 01 00 00 00 01 00 FE FF 01 00 00 00 30 00 00 00 // ............0... + 00B0: 00 03 00 00 01 00 00 00 02 00 00 00 00 00 00 00 // ................ + 00C0: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 01 00 00 00 FE FF FF 7F 02 00 00 00 20 00 00 00 // ............ ... + 00E0: 00 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 00F0: 11 11 08 00 00 00 00 00 02 00 00 00 20 00 00 00 // ............ ... + 0100: 01 00 00 00 00 00 00 00 00 28 00 00 00 00 00 00 // .........(...... + 0110: 11 11 08 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.acpihmat b/tests/data/acpi/q35/HPET.acpihmat new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/q35/HPET.acpihmat Binary files differdiff --git a/tests/data/acpi/q35/HPET.acpihmat.dsl b/tests/data/acpi/q35/HPET.acpihmat.dsl new file mode 100644 index 0000000000..9806b81069 --- /dev/null +++ b/tests/data/acpi/q35/HPET.acpihmat.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.bridge b/tests/data/acpi/q35/HPET.bridge new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/q35/HPET.bridge Binary files differdiff --git a/tests/data/acpi/q35/HPET.bridge.dsl b/tests/data/acpi/q35/HPET.bridge.dsl new file mode 100644 index 0000000000..817040df23 --- /dev/null +++ b/tests/data/acpi/q35/HPET.bridge.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.cphp b/tests/data/acpi/q35/HPET.cphp new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/q35/HPET.cphp Binary files differdiff --git a/tests/data/acpi/q35/HPET.cphp.dsl b/tests/data/acpi/q35/HPET.cphp.dsl new file mode 100644 index 0000000000..4134b96873 --- /dev/null +++ b/tests/data/acpi/q35/HPET.cphp.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.dimmpxm b/tests/data/acpi/q35/HPET.dimmpxm new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/q35/HPET.dimmpxm Binary files differdiff --git a/tests/data/acpi/q35/HPET.dimmpxm.dsl b/tests/data/acpi/q35/HPET.dimmpxm.dsl new file mode 100644 index 0000000000..42a7cc5fd6 --- /dev/null +++ b/tests/data/acpi/q35/HPET.dimmpxm.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.dsl b/tests/data/acpi/q35/HPET.dsl new file mode 100644 index 0000000000..42c40fd653 --- /dev/null +++ b/tests/data/acpi/q35/HPET.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.ipmibt b/tests/data/acpi/q35/HPET.ipmibt new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/q35/HPET.ipmibt Binary files differdiff --git a/tests/data/acpi/q35/HPET.ipmibt.dsl b/tests/data/acpi/q35/HPET.ipmibt.dsl new file mode 100644 index 0000000000..9637f4cf81 --- /dev/null +++ b/tests/data/acpi/q35/HPET.ipmibt.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.memhp b/tests/data/acpi/q35/HPET.memhp new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/q35/HPET.memhp Binary files differdiff --git a/tests/data/acpi/q35/HPET.memhp.dsl b/tests/data/acpi/q35/HPET.memhp.dsl new file mode 100644 index 0000000000..2efab15846 --- /dev/null +++ b/tests/data/acpi/q35/HPET.memhp.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.mmio64 b/tests/data/acpi/q35/HPET.mmio64 new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/q35/HPET.mmio64 Binary files differdiff --git a/tests/data/acpi/q35/HPET.mmio64.dsl b/tests/data/acpi/q35/HPET.mmio64.dsl new file mode 100644 index 0000000000..dba0368678 --- /dev/null +++ b/tests/data/acpi/q35/HPET.mmio64.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.numamem b/tests/data/acpi/q35/HPET.numamem new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/q35/HPET.numamem Binary files differdiff --git a/tests/data/acpi/q35/HPET.numamem.dsl b/tests/data/acpi/q35/HPET.numamem.dsl new file mode 100644 index 0000000000..e9d18a59fd --- /dev/null +++ b/tests/data/acpi/q35/HPET.numamem.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/HPET.tis b/tests/data/acpi/q35/HPET.tis new file mode 100644 index 0000000000..df689b8f99 --- /dev/null +++ b/tests/data/acpi/q35/HPET.tis Binary files differdiff --git a/tests/data/acpi/q35/HPET.tis.dsl b/tests/data/acpi/q35/HPET.tis.dsl new file mode 100644 index 0000000000..471cb5b940 --- /dev/null +++ b/tests/data/acpi/q35/HPET.tis.dsl @@ -0,0 +1,43 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/HPET.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [HPET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "HPET" [High Precision Event Timer table] +[004h 0004 4] Table Length : 00000038 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 03 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCHPET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Hardware Block ID : 8086A201 + +[028h 0040 12] Timer Block Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 00 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 00 [Undefined/Legacy] +[02Ch 0044 8] Address : 00000000FED00000 + +[034h 0052 1] Sequence Number : 00 +[035h 0053 2] Minimum Clock Ticks : 0000 +[037h 0055 1] Flags (decoded below) : 00 + 4K Page Protect : 0 + 64K Page Protect : 0 + +Raw Table Data: Length 56 (0x38) + + 0000: 48 50 45 54 38 00 00 00 01 03 42 4F 43 48 53 20 // HPET8.....BOCHS + 0010: 42 58 50 43 48 50 45 54 01 00 00 00 42 58 50 43 // BXPCHPET....BXPC + 0020: 01 00 00 00 01 A2 86 80 00 00 00 00 00 00 D0 FE // ................ + 0030: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/MCFG.acpihmat b/tests/data/acpi/q35/MCFG.acpihmat new file mode 100644 index 0000000000..79ceb27a03 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.acpihmat Binary files differdiff --git a/tests/data/acpi/q35/MCFG.acpihmat.dsl b/tests/data/acpi/q35/MCFG.acpihmat.dsl new file mode 100644 index 0000000000..8d07f64e9d --- /dev/null +++ b/tests/data/acpi/q35/MCFG.acpihmat.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.bridge b/tests/data/acpi/q35/MCFG.bridge new file mode 100644 index 0000000000..79ceb27a03 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.bridge Binary files differdiff --git a/tests/data/acpi/q35/MCFG.bridge.dsl b/tests/data/acpi/q35/MCFG.bridge.dsl new file mode 100644 index 0000000000..6ce54d7228 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.bridge.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.cphp b/tests/data/acpi/q35/MCFG.cphp new file mode 100644 index 0000000000..79ceb27a03 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.cphp Binary files differdiff --git a/tests/data/acpi/q35/MCFG.cphp.dsl b/tests/data/acpi/q35/MCFG.cphp.dsl new file mode 100644 index 0000000000..7ffd7f30db --- /dev/null +++ b/tests/data/acpi/q35/MCFG.cphp.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.dimmpxm b/tests/data/acpi/q35/MCFG.dimmpxm new file mode 100644 index 0000000000..79ceb27a03 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.dimmpxm Binary files differdiff --git a/tests/data/acpi/q35/MCFG.dimmpxm.dsl b/tests/data/acpi/q35/MCFG.dimmpxm.dsl new file mode 100644 index 0000000000..dd7373b692 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.dimmpxm.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.dsl b/tests/data/acpi/q35/MCFG.dsl new file mode 100644 index 0000000000..5179d6d707 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.ipmibt b/tests/data/acpi/q35/MCFG.ipmibt new file mode 100644 index 0000000000..79ceb27a03 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.ipmibt Binary files differdiff --git a/tests/data/acpi/q35/MCFG.ipmibt.dsl b/tests/data/acpi/q35/MCFG.ipmibt.dsl new file mode 100644 index 0000000000..80c372162c --- /dev/null +++ b/tests/data/acpi/q35/MCFG.ipmibt.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.memhp b/tests/data/acpi/q35/MCFG.memhp new file mode 100644 index 0000000000..79ceb27a03 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.memhp Binary files differdiff --git a/tests/data/acpi/q35/MCFG.memhp.dsl b/tests/data/acpi/q35/MCFG.memhp.dsl new file mode 100644 index 0000000000..1b1f666833 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.memhp.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.mmio64 b/tests/data/acpi/q35/MCFG.mmio64 new file mode 100644 index 0000000000..79ceb27a03 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.mmio64 Binary files differdiff --git a/tests/data/acpi/q35/MCFG.mmio64.dsl b/tests/data/acpi/q35/MCFG.mmio64.dsl new file mode 100644 index 0000000000..79be440f72 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.mmio64.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.numamem b/tests/data/acpi/q35/MCFG.numamem new file mode 100644 index 0000000000..79ceb27a03 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.numamem Binary files differdiff --git a/tests/data/acpi/q35/MCFG.numamem.dsl b/tests/data/acpi/q35/MCFG.numamem.dsl new file mode 100644 index 0000000000..30b37074d3 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.numamem.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/MCFG.tis b/tests/data/acpi/q35/MCFG.tis new file mode 100644 index 0000000000..79ceb27a03 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.tis Binary files differdiff --git a/tests/data/acpi/q35/MCFG.tis.dsl b/tests/data/acpi/q35/MCFG.tis.dsl new file mode 100644 index 0000000000..0a92d698e9 --- /dev/null +++ b/tests/data/acpi/q35/MCFG.tis.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/MCFG.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : EF +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 00000000B0000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 EF 42 4F 43 48 53 20 // MCFG<.....BOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 B0 // ................ + 0030: 00 00 00 00 00 00 00 FF 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/NFIT.dimmpxm.dsl b/tests/data/acpi/q35/NFIT.dimmpxm.dsl new file mode 100644 index 0000000000..e29b770dca --- /dev/null +++ b/tests/data/acpi/q35/NFIT.dimmpxm.dsl @@ -0,0 +1,115 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/NFIT.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000F0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 24 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000002 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000108000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities] +[0E2h 0226 2] Length : 0010 + +[0E4h 0228 1] Highest Capability : 01 +[0E5h 0229 3] Reserved : 000000 +[0E8h 0232 4] Capabilities (decoded below) : 00000003 + Cache Flush to NVDIMM : 1 + Memory Flush to NVDIMM : 1 + Memory Mirroring : 0 +[0ECh 0236 4] Reserved : 00000000 + +Raw Table Data: Length 240 (0xF0) + + 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/NFIT.dsl b/tests/data/acpi/q35/NFIT.dsl new file mode 100644 index 0000000000..8da7718431 --- /dev/null +++ b/tests/data/acpi/q35/NFIT.dsl @@ -0,0 +1,115 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/NFIT.dimmpxm, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000F0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 24 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000002 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000108000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +[0E0h 0224 2] Subtable Type : 0007 [Platform Capabilities] +[0E2h 0226 2] Length : 0010 + +[0E4h 0228 1] Highest Capability : 01 +[0E5h 0229 3] Reserved : 000000 +[0E8h 0232 4] Capabilities (decoded below) : 00000003 + Cache Flush to NVDIMM : 1 + Memory Flush to NVDIMM : 1 + Memory Mirroring : 0 +[0ECh 0236 4] Reserved : 00000000 + +Raw Table Data: Length 240 (0xF0) + + 0000: 4E 46 49 54 F0 00 00 00 01 24 42 4F 43 48 53 20 // NFIT.....$BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 02 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 08 01 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 07 00 10 00 01 00 00 00 03 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SLIT.cphp.dsl b/tests/data/acpi/q35/SLIT.cphp.dsl new file mode 100644 index 0000000000..cb7347fbd4 --- /dev/null +++ b/tests/data/acpi/q35/SLIT.cphp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SLIT.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/q35/SLIT.dsl b/tests/data/acpi/q35/SLIT.dsl new file mode 100644 index 0000000000..89c381bdd0 --- /dev/null +++ b/tests/data/acpi/q35/SLIT.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SLIT.memhp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/q35/SLIT.memhp.dsl b/tests/data/acpi/q35/SLIT.memhp.dsl new file mode 100644 index 0000000000..70b233c0e6 --- /dev/null +++ b/tests/data/acpi/q35/SLIT.memhp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SLIT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/q35/SRAT.acpihmat.dsl b/tests/data/acpi/q35/SRAT.acpihmat.dsl new file mode 100644 index 0000000000..8a1b47e6b0 --- /dev/null +++ b/tests/data/acpi/q35/SRAT.acpihmat.dsl @@ -0,0 +1,137 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000118 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : C0 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[041h 0065 1] Length : 10 + +[042h 0066 1] Proximity Domain Low(8) : 00 +[043h 0067 1] Apic ID : 01 +[044h 0068 4] Flags (decoded below) : 00000001 + Enabled : 1 +[048h 0072 1] Local Sapic EID : 00 +[049h 0073 3] Proximity Domain High(24) : 000000 +[04Ch 0076 4] Clock Domain : 00000000 + +[050h 0080 1] Subtable Type : 01 [Memory Affinity] +[051h 0081 1] Length : 28 + +[052h 0082 4] Proximity Domain : 00000000 +[056h 0086 2] Reserved1 : 0000 +[058h 0088 8] Base Address : 0000000000000000 +[060h 0096 8] Address Length : 00000000000A0000 +[068h 0104 4] Reserved2 : 00000000 +[06Ch 0108 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[070h 0112 8] Reserved3 : 0000000000000000 + +[078h 0120 1] Subtable Type : 01 [Memory Affinity] +[079h 0121 1] Length : 28 + +[07Ah 0122 4] Proximity Domain : 00000000 +[07Eh 0126 2] Reserved1 : 0000 +[080h 0128 8] Base Address : 0000000000100000 +[088h 0136 8] Address Length : 0000000003F00000 +[090h 0144 4] Reserved2 : 00000000 +[094h 0148 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[098h 0152 8] Reserved3 : 0000000000000000 + +[0A0h 0160 1] Subtable Type : 01 [Memory Affinity] +[0A1h 0161 1] Length : 28 + +[0A2h 0162 4] Proximity Domain : 00000001 +[0A6h 0166 2] Reserved1 : 0000 +[0A8h 0168 8] Base Address : 0000000004000000 +[0B0h 0176 8] Address Length : 0000000004000000 +[0B8h 0184 4] Reserved2 : 00000000 +[0BCh 0188 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0C0h 0192 8] Reserved3 : 0000000000000000 + +[0C8h 0200 1] Subtable Type : 01 [Memory Affinity] +[0C9h 0201 1] Length : 28 + +[0CAh 0202 4] Proximity Domain : 00000000 +[0CEh 0206 2] Reserved1 : 0000 +[0D0h 0208 8] Base Address : 0000000000000000 +[0D8h 0216 8] Address Length : 0000000000000000 +[0E0h 0224 4] Reserved2 : 00000000 +[0E4h 0228 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0E8h 0232 8] Reserved3 : 0000000000000000 + +[0F0h 0240 1] Subtable Type : 01 [Memory Affinity] +[0F1h 0241 1] Length : 28 + +[0F2h 0242 4] Proximity Domain : 00000001 +[0F6h 0246 2] Reserved1 : 0000 +[0F8h 0248 8] Base Address : 0000000100000000 +[100h 0256 8] Address Length : 00000000B8000000 +[108h 0264 4] Reserved2 : 00000000 +[10Ch 0268 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[110h 0272 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 280 (0x118) + + 0000: 53 52 41 54 18 01 00 00 01 C0 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0060: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0070: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0080: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................ + 0090: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(.............. + 00B0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(.............. + 0100: 00 00 00 B8 00 00 00 00 00 00 00 00 03 00 00 00 // ................ + 0110: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/SRAT.cphp.dsl b/tests/data/acpi/q35/SRAT.cphp.dsl new file mode 100644 index 0000000000..f0023db38d --- /dev/null +++ b/tests/data/acpi/q35/SRAT.cphp.dsl @@ -0,0 +1,168 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000130 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 36 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[041h 0065 1] Length : 10 + +[042h 0066 1] Proximity Domain Low(8) : 00 +[043h 0067 1] Apic ID : 01 +[044h 0068 4] Flags (decoded below) : 00000001 + Enabled : 1 +[048h 0072 1] Local Sapic EID : 00 +[049h 0073 3] Proximity Domain High(24) : 000000 +[04Ch 0076 4] Clock Domain : 00000000 + +[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[051h 0081 1] Length : 10 + +[052h 0082 1] Proximity Domain Low(8) : 00 +[053h 0083 1] Apic ID : 02 +[054h 0084 4] Flags (decoded below) : 00000001 + Enabled : 1 +[058h 0088 1] Local Sapic EID : 00 +[059h 0089 3] Proximity Domain High(24) : 000000 +[05Ch 0092 4] Clock Domain : 00000000 + +[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[061h 0097 1] Length : 10 + +[062h 0098 1] Proximity Domain Low(8) : 01 +[063h 0099 1] Apic ID : 04 +[064h 0100 4] Flags (decoded below) : 00000001 + Enabled : 1 +[068h 0104 1] Local Sapic EID : 00 +[069h 0105 3] Proximity Domain High(24) : 000000 +[06Ch 0108 4] Clock Domain : 00000000 + +[070h 0112 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[071h 0113 1] Length : 10 + +[072h 0114 1] Proximity Domain Low(8) : 01 +[073h 0115 1] Apic ID : 05 +[074h 0116 4] Flags (decoded below) : 00000001 + Enabled : 1 +[078h 0120 1] Local Sapic EID : 00 +[079h 0121 3] Proximity Domain High(24) : 000000 +[07Ch 0124 4] Clock Domain : 00000000 + +[080h 0128 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[081h 0129 1] Length : 10 + +[082h 0130 1] Proximity Domain Low(8) : 01 +[083h 0131 1] Apic ID : 06 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 +[088h 0136 1] Local Sapic EID : 00 +[089h 0137 3] Proximity Domain High(24) : 000000 +[08Ch 0140 4] Clock Domain : 00000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 00000000000A0000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000100000 +[0C8h 0200 8] Address Length : 0000000003F00000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +[0E0h 0224 1] Subtable Type : 01 [Memory Affinity] +[0E1h 0225 1] Length : 28 + +[0E2h 0226 4] Proximity Domain : 00000001 +[0E6h 0230 2] Reserved1 : 0000 +[0E8h 0232 8] Base Address : 0000000004000000 +[0F0h 0240 8] Address Length : 0000000004000000 +[0F8h 0248 4] Reserved2 : 00000000 +[0FCh 0252 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[100h 0256 8] Reserved3 : 0000000000000000 + +[108h 0264 1] Subtable Type : 01 [Memory Affinity] +[109h 0265 1] Length : 28 + +[10Ah 0266 4] Proximity Domain : 00000000 +[10Eh 0270 2] Reserved1 : 0000 +[110h 0272 8] Base Address : 0000000000000000 +[118h 0280 8] Address Length : 0000000000000000 +[120h 0288 4] Reserved2 : 00000000 +[124h 0292 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[128h 0296 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 304 (0x130) + + 0000: 53 52 41 54 30 01 00 00 01 36 42 4F 43 48 53 20 // SRAT0....6BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 10 00 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 10 00 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 10 01 04 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 10 01 05 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 10 01 06 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................ + 00D0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(.............. + 00F0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0110: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0120: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SRAT.dimmpxm.dsl b/tests/data/acpi/q35/SRAT.dimmpxm.dsl new file mode 100644 index 0000000000..2cfe6994f5 --- /dev/null +++ b/tests/data/acpi/q35/SRAT.dimmpxm.dsl @@ -0,0 +1,194 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000188 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 68 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[041h 0065 1] Length : 10 + +[042h 0066 1] Proximity Domain Low(8) : 01 +[043h 0067 1] Apic ID : 01 +[044h 0068 4] Flags (decoded below) : 00000001 + Enabled : 1 +[048h 0072 1] Local Sapic EID : 00 +[049h 0073 3] Proximity Domain High(24) : 000000 +[04Ch 0076 4] Clock Domain : 00000000 + +[050h 0080 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[051h 0081 1] Length : 10 + +[052h 0082 1] Proximity Domain Low(8) : 02 +[053h 0083 1] Apic ID : 02 +[054h 0084 4] Flags (decoded below) : 00000001 + Enabled : 1 +[058h 0088 1] Local Sapic EID : 00 +[059h 0089 3] Proximity Domain High(24) : 000000 +[05Ch 0092 4] Clock Domain : 00000000 + +[060h 0096 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[061h 0097 1] Length : 10 + +[062h 0098 1] Proximity Domain Low(8) : 03 +[063h 0099 1] Apic ID : 03 +[064h 0100 4] Flags (decoded below) : 00000001 + Enabled : 1 +[068h 0104 1] Local Sapic EID : 00 +[069h 0105 3] Proximity Domain High(24) : 000000 +[06Ch 0108 4] Clock Domain : 00000000 + +[070h 0112 1] Subtable Type : 01 [Memory Affinity] +[071h 0113 1] Length : 28 + +[072h 0114 4] Proximity Domain : 00000000 +[076h 0118 2] Reserved1 : 0000 +[078h 0120 8] Base Address : 0000000000000000 +[080h 0128 8] Address Length : 00000000000A0000 +[088h 0136 4] Reserved2 : 00000000 +[08Ch 0140 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[090h 0144 8] Reserved3 : 0000000000000000 + +[098h 0152 1] Subtable Type : 01 [Memory Affinity] +[099h 0153 1] Length : 28 + +[09Ah 0154 4] Proximity Domain : 00000000 +[09Eh 0158 2] Reserved1 : 0000 +[0A0h 0160 8] Base Address : 0000000000100000 +[0A8h 0168 8] Address Length : 0000000001F00000 +[0B0h 0176 4] Reserved2 : 00000000 +[0B4h 0180 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B8h 0184 8] Reserved3 : 0000000000000000 + +[0C0h 0192 1] Subtable Type : 01 [Memory Affinity] +[0C1h 0193 1] Length : 28 + +[0C2h 0194 4] Proximity Domain : 00000001 +[0C6h 0198 2] Reserved1 : 0000 +[0C8h 0200 8] Base Address : 0000000002000000 +[0D0h 0208 8] Address Length : 0000000002000000 +[0D8h 0216 4] Reserved2 : 00000000 +[0DCh 0220 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0E0h 0224 8] Reserved3 : 0000000000000000 + +[0E8h 0232 1] Subtable Type : 01 [Memory Affinity] +[0E9h 0233 1] Length : 28 + +[0EAh 0234 4] Proximity Domain : 00000002 +[0EEh 0238 2] Reserved1 : 0000 +[0F0h 0240 8] Base Address : 0000000004000000 +[0F8h 0248 8] Address Length : 0000000002000000 +[100h 0256 4] Reserved2 : 00000000 +[104h 0260 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[108h 0264 8] Reserved3 : 0000000000000000 + +[110h 0272 1] Subtable Type : 01 [Memory Affinity] +[111h 0273 1] Length : 28 + +[112h 0274 4] Proximity Domain : 00000003 +[116h 0278 2] Reserved1 : 0000 +[118h 0280 8] Base Address : 0000000006000000 +[120h 0288 8] Address Length : 0000000002000000 +[128h 0296 4] Reserved2 : 00000000 +[12Ch 0300 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[130h 0304 8] Reserved3 : 0000000000000000 + +[138h 0312 1] Subtable Type : 01 [Memory Affinity] +[139h 0313 1] Length : 28 + +[13Ah 0314 4] Proximity Domain : 00000002 +[13Eh 0318 2] Reserved1 : 0000 +[140h 0320 8] Base Address : 0000000108000000 +[148h 0328 8] Address Length : 0000000008000000 +[150h 0336 4] Reserved2 : 00000000 +[154h 0340 4] Flags (decoded below) : 00000005 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 1 +[158h 0344 8] Reserved3 : 0000000000000000 + +[160h 0352 1] Subtable Type : 01 [Memory Affinity] +[161h 0353 1] Length : 28 + +[162h 0354 4] Proximity Domain : 00000003 +[166h 0358 2] Reserved1 : 0000 +[168h 0360 8] Base Address : 0000000100000000 +[170h 0368 8] Address Length : 00000000F8000000 +[178h 0376 4] Reserved2 : 00000000 +[17Ch 0380 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[180h 0384 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 392 (0x188) + + 0000: 53 52 41 54 88 01 00 00 01 68 42 4F 43 48 53 20 // SRAT.....hBOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 10 01 01 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 10 02 02 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 10 03 03 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0080: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00A0: 00 00 10 00 00 00 00 00 00 00 F0 01 00 00 00 00 // ................ + 00B0: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 01 28 01 00 00 00 00 00 00 00 00 02 00 00 00 00 // .(.............. + 00D0: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(...... + 00F0: 00 00 00 04 00 00 00 00 00 00 00 02 00 00 00 00 // ................ + 0100: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0110: 01 28 03 00 00 00 00 00 00 00 00 06 00 00 00 00 // .(.............. + 0120: 00 00 00 02 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0130: 00 00 00 00 00 00 00 00 01 28 02 00 00 00 00 00 // .........(...... + 0140: 00 00 00 08 01 00 00 00 00 00 00 08 00 00 00 00 // ................ + 0150: 00 00 00 00 05 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0160: 01 28 03 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(.............. + 0170: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................ + 0180: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/SRAT.dsl b/tests/data/acpi/q35/SRAT.dsl new file mode 100644 index 0000000000..5f4278994e --- /dev/null +++ b/tests/data/acpi/q35/SRAT.dsl @@ -0,0 +1,108 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : F5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000001 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000001 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000007F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 0000000000000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000000000 +[0C8h 0200 8] Address Length : 0000000000000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SRAT.memhp.dsl b/tests/data/acpi/q35/SRAT.memhp.dsl new file mode 100644 index 0000000000..a5f27214eb --- /dev/null +++ b/tests/data/acpi/q35/SRAT.memhp.dsl @@ -0,0 +1,125 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 00000108 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : A2 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000000 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000000 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000003F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000001 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000004000000 +[0A0h 0160 8] Address Length : 0000000004000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000000000 +[0C8h 0200 8] Address Length : 0000000000000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +[0E0h 0224 1] Subtable Type : 01 [Memory Affinity] +[0E1h 0225 1] Length : 28 + +[0E2h 0226 4] Proximity Domain : 00000001 +[0E6h 0230 2] Reserved1 : 0000 +[0E8h 0232 8] Base Address : 0000000100000000 +[0F0h 0240 8] Address Length : 00000000F8000000 +[0F8h 0248 4] Reserved2 : 00000000 +[0FCh 0252 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[100h 0256 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 264 (0x108) + + 0000: 53 52 41 54 08 01 00 00 01 A2 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 03 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 01 00 00 00 00 00 00 00 00 04 00 00 00 00 // .(.............. + 00A0: 00 00 00 04 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 01 28 01 00 00 00 00 00 00 00 00 00 01 00 00 00 // .(.............. + 00F0: 00 00 00 F8 00 00 00 00 00 00 00 00 03 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 // ........ diff --git a/tests/data/acpi/q35/SRAT.mmio64.dsl b/tests/data/acpi/q35/SRAT.mmio64.dsl new file mode 100644 index 0000000000..0065c21de4 --- /dev/null +++ b/tests/data/acpi/q35/SRAT.mmio64.dsl @@ -0,0 +1,108 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 3B +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000000 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000000 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000007F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 0000000000000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000100000000 +[0C8h 0200 8] Address Length : 00000000B8000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 53 52 41 54 E0 00 00 00 01 3B 42 4F 43 48 53 20 // SRAT.....;BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 01 00 00 00 00 00 00 B8 00 00 00 00 // ................ + 00D0: 00 00 00 00 03 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SRAT.numamem.dsl b/tests/data/acpi/q35/SRAT.numamem.dsl new file mode 100644 index 0000000000..e8de953ae2 --- /dev/null +++ b/tests/data/acpi/q35/SRAT.numamem.dsl @@ -0,0 +1,108 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/SRAT.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : F5 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 00 [Processor Local APIC/SAPIC Affinity] +[031h 0049 1] Length : 10 + +[032h 0050 1] Proximity Domain Low(8) : 00 +[033h 0051 1] Apic ID : 00 +[034h 0052 4] Flags (decoded below) : 00000001 + Enabled : 1 +[038h 0056 1] Local Sapic EID : 00 +[039h 0057 3] Proximity Domain High(24) : 000000 +[03Ch 0060 4] Clock Domain : 00000000 + +[040h 0064 1] Subtable Type : 01 [Memory Affinity] +[041h 0065 1] Length : 28 + +[042h 0066 4] Proximity Domain : 00000001 +[046h 0070 2] Reserved1 : 0000 +[048h 0072 8] Base Address : 0000000000000000 +[050h 0080 8] Address Length : 00000000000A0000 +[058h 0088 4] Reserved2 : 00000000 +[05Ch 0092 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[060h 0096 8] Reserved3 : 0000000000000000 + +[068h 0104 1] Subtable Type : 01 [Memory Affinity] +[069h 0105 1] Length : 28 + +[06Ah 0106 4] Proximity Domain : 00000001 +[06Eh 0110 2] Reserved1 : 0000 +[070h 0112 8] Base Address : 0000000000100000 +[078h 0120 8] Address Length : 0000000007F00000 +[080h 0128 4] Reserved2 : 00000000 +[084h 0132 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[088h 0136 8] Reserved3 : 0000000000000000 + +[090h 0144 1] Subtable Type : 01 [Memory Affinity] +[091h 0145 1] Length : 28 + +[092h 0146 4] Proximity Domain : 00000000 +[096h 0150 2] Reserved1 : 0000 +[098h 0152 8] Base Address : 0000000000000000 +[0A0h 0160 8] Address Length : 0000000000000000 +[0A8h 0168 4] Reserved2 : 00000000 +[0ACh 0172 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0B0h 0176 8] Reserved3 : 0000000000000000 + +[0B8h 0184 1] Subtable Type : 01 [Memory Affinity] +[0B9h 0185 1] Length : 28 + +[0BAh 0186 4] Proximity Domain : 00000000 +[0BEh 0190 2] Reserved1 : 0000 +[0C0h 0192 8] Base Address : 0000000000000000 +[0C8h 0200 8] Address Length : 0000000000000000 +[0D0h 0208 4] Reserved2 : 00000000 +[0D4h 0212 4] Flags (decoded below) : 00000000 + Enabled : 0 + Hot Pluggable : 0 + Non-Volatile : 0 +[0D8h 0216 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 53 52 41 54 E0 00 00 00 01 F5 42 4F 43 48 53 20 // SRAT......BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 10 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 01 28 01 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 0050: 00 00 0A 00 00 00 00 00 00 00 00 00 01 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 01 28 01 00 00 00 00 00 // .........(...... + 0070: 00 00 10 00 00 00 00 00 00 00 F0 07 00 00 00 00 // ................ + 0080: 00 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 01 28 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // .(.............. + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 01 28 00 00 00 00 00 00 // .........(...... + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/q35/SSDT.dsl b/tests/data/acpi/q35/SSDT.dsl new file mode 100644 index 0000000000..49df22f93d --- /dev/null +++ b/tests/data/acpi/q35/SSDT.dsl @@ -0,0 +1,205 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/q35/SSDT.dimmpxm, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "SSDT" + * Length 0x000002DE (734) + * Revision 0x01 + * Checksum 0x46 + * OEM ID "BOCHS " + * OEM Table ID "NVDIMM" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) +{ + Scope (\_SB) + { + Device (NVDR) + { + Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID + Method (NCAL, 5, Serialized) + { + Local6 = MEMA /* \MEMA */ + OperationRegion (NPIO, SystemIO, 0x0A18, 0x04) + OperationRegion (NRAM, SystemMemory, Local6, 0x1000) + Field (NPIO, DWordAcc, NoLock, Preserve) + { + NTFI, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + REVS, 32, + FUNC, 32, + FARG, 32672 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + ODAT, 32736 + } + + If ((Arg4 == Zero)) + { + Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba") + } + ElseIf ((Arg4 == 0x00010000)) + { + Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62") + } + Else + { + Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66") + } + + If (((Local6 == Zero) | (Arg0 != Local0))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x00 // . + }) + } + + Return (Buffer (One) + { + 0x01 // . + }) + } + + HDLE = Arg4 + REVS = Arg1 + FUNC = Arg2 + If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) + { + Local2 = Arg3 [Zero] + Local3 = DerefOf (Local2) + FARG = Local3 + } + + NTFI = Local6 + Local1 = (RLEN - 0x04) + If ((Local1 < 0x08)) + { + Local2 = Zero + Name (TBUF, Buffer (One) + { + 0x00 // . + }) + Local7 = Buffer (Zero){} + While ((Local2 < Local1)) + { + TBUF [Zero] = DerefOf (ODAT [Local2]) + Concatenate (Local7, TBUF, Local7) + Local2++ + } + + Return (Local7) + } + + Local1 = (Local1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Return (OBUF) /* \_SB_.NVDR.NCAL.OBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, Zero)) + } + + Name (RSTA, Zero) + Method (RFIT, 1, Serialized) + { + Name (OFST, Zero) + OFST = Arg0 + Local0 = NCAL (ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62"), One, One, Package (0x01) + { + OFST + }, 0x00010000) + CreateDWordField (Local0, Zero, STAU) + RSTA = STAU /* \_SB_.NVDR.RFIT.STAU */ + If ((Zero != STAU)) + { + Return (Buffer (Zero){}) + } + + Local1 = SizeOf (Local0) + Local1 -= 0x04 + If ((Local1 == Zero)) + { + Return (Buffer (Zero){}) + } + + CreateField (Local0, 0x20, (Local1 << 0x03), BUFF) + Return (BUFF) /* \_SB_.NVDR.RFIT.BUFF */ + } + + Method (_FIT, 0, Serialized) // _FIT: Firmware Interface Table + { + Local2 = Buffer (Zero){} + Local3 = Zero + While (One) + { + Local0 = RFIT (Local3) + Local1 = SizeOf (Local0) + If ((RSTA == 0x0100)) + { + Local2 = Buffer (Zero){} + Local3 = Zero + } + Else + { + If ((Local1 == Zero)) + { + Return (Local2) + } + + Local3 += Local1 + Concatenate (Local2, Local0, Local2) + } + } + } + + Device (NV00) + { + Name (_ADR, One) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, One)) + } + } + + Device (NV01) + { + Name (_ADR, 0x02) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02)) + } + } + + Device (NV02) + { + Name (_ADR, 0x03) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03)) + } + } + } + } + + Name (MEMA, 0x07FFF000) +} + diff --git a/tests/data/acpi/q35/TPM2.dsl b/tests/data/acpi/q35/TPM2.dsl new file mode 100644 index 0000000000..8568152ccf --- /dev/null +++ b/tests/data/acpi/q35/TPM2.dsl @@ -0,0 +1,38 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/TPM2.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [TPM2] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[004h 0004 4] Table Length : 0000004C +[008h 0008 1] Revision : 04 +[009h 0009 1] Checksum : 72 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCTPM2" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 2] Platform Class : 0000 +[026h 0038 2] Reserved : 0000 +[028h 0040 8] Control Address : 0000000000000000 +[030h 0048 4] Start Method : 06 [Memory Mapped I/O] + +[034h 0052 12] Method Parameters : 00 00 00 00 00 00 00 00 00 00 00 00 +[040h 0064 4] Minimum Log Length : 00010000 +[044h 0068 8] Log Address : 0000000007FF0000 + +Raw Table Data: Length 76 (0x4C) + + 0000: 54 50 4D 32 4C 00 00 00 04 72 42 4F 43 48 53 20 // TPM2L....rBOCHS + 0010: 42 58 50 43 54 50 4D 32 01 00 00 00 42 58 50 43 // BXPCTPM2....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 01 00 00 00 FF 07 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/TPM2.tis.dsl b/tests/data/acpi/q35/TPM2.tis.dsl new file mode 100644 index 0000000000..420643ab2b --- /dev/null +++ b/tests/data/acpi/q35/TPM2.tis.dsl @@ -0,0 +1,38 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/TPM2.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [TPM2] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "TPM2" [Trusted Platform Module hardware interface table] +[004h 0004 4] Table Length : 0000004C +[008h 0008 1] Revision : 04 +[009h 0009 1] Checksum : 72 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCTPM2" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 2] Platform Class : 0000 +[026h 0038 2] Reserved : 0000 +[028h 0040 8] Control Address : 0000000000000000 +[030h 0048 4] Start Method : 06 [Memory Mapped I/O] + +[034h 0052 12] Method Parameters : 00 00 00 00 00 00 00 00 00 00 00 00 +[040h 0064 4] Minimum Log Length : 00010000 +[044h 0068 8] Log Address : 0000000007FF0000 + +Raw Table Data: Length 76 (0x4C) + + 0000: 54 50 4D 32 4C 00 00 00 04 72 42 4F 43 48 53 20 // TPM2L....rBOCHS + 0010: 42 58 50 43 54 50 4D 32 01 00 00 00 42 58 50 43 // BXPCTPM2....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 06 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 01 00 00 00 FF 07 00 00 00 00 // ............ diff --git a/tests/data/acpi/q35/WAET.acpihmat b/tests/data/acpi/q35/WAET.acpihmat new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/q35/WAET.acpihmat Binary files differdiff --git a/tests/data/acpi/q35/WAET.acpihmat.dsl b/tests/data/acpi/q35/WAET.acpihmat.dsl new file mode 100644 index 0000000000..12a4fced5c --- /dev/null +++ b/tests/data/acpi/q35/WAET.acpihmat.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.acpihmat, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.bridge b/tests/data/acpi/q35/WAET.bridge new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/q35/WAET.bridge Binary files differdiff --git a/tests/data/acpi/q35/WAET.bridge.dsl b/tests/data/acpi/q35/WAET.bridge.dsl new file mode 100644 index 0000000000..48effe4c6e --- /dev/null +++ b/tests/data/acpi/q35/WAET.bridge.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.bridge, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.cphp b/tests/data/acpi/q35/WAET.cphp new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/q35/WAET.cphp Binary files differdiff --git a/tests/data/acpi/q35/WAET.cphp.dsl b/tests/data/acpi/q35/WAET.cphp.dsl new file mode 100644 index 0000000000..aadebd53e8 --- /dev/null +++ b/tests/data/acpi/q35/WAET.cphp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.cphp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.dimmpxm b/tests/data/acpi/q35/WAET.dimmpxm new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/q35/WAET.dimmpxm Binary files differdiff --git a/tests/data/acpi/q35/WAET.dimmpxm.dsl b/tests/data/acpi/q35/WAET.dimmpxm.dsl new file mode 100644 index 0000000000..7ad316b118 --- /dev/null +++ b/tests/data/acpi/q35/WAET.dimmpxm.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.dimmpxm, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.dsl b/tests/data/acpi/q35/WAET.dsl new file mode 100644 index 0000000000..b48db4efca --- /dev/null +++ b/tests/data/acpi/q35/WAET.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.tis, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.ipmibt b/tests/data/acpi/q35/WAET.ipmibt new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/q35/WAET.ipmibt Binary files differdiff --git a/tests/data/acpi/q35/WAET.ipmibt.dsl b/tests/data/acpi/q35/WAET.ipmibt.dsl new file mode 100644 index 0000000000..40cb1d5649 --- /dev/null +++ b/tests/data/acpi/q35/WAET.ipmibt.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.ipmibt, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.memhp b/tests/data/acpi/q35/WAET.memhp new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/q35/WAET.memhp Binary files differdiff --git a/tests/data/acpi/q35/WAET.memhp.dsl b/tests/data/acpi/q35/WAET.memhp.dsl new file mode 100644 index 0000000000..e27f54d4dd --- /dev/null +++ b/tests/data/acpi/q35/WAET.memhp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.mmio64 b/tests/data/acpi/q35/WAET.mmio64 new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/q35/WAET.mmio64 Binary files differdiff --git a/tests/data/acpi/q35/WAET.mmio64.dsl b/tests/data/acpi/q35/WAET.mmio64.dsl new file mode 100644 index 0000000000..98f3aaf569 --- /dev/null +++ b/tests/data/acpi/q35/WAET.mmio64.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.mmio64, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.numamem b/tests/data/acpi/q35/WAET.numamem new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/q35/WAET.numamem Binary files differdiff --git a/tests/data/acpi/q35/WAET.numamem.dsl b/tests/data/acpi/q35/WAET.numamem.dsl new file mode 100644 index 0000000000..738c75ca6c --- /dev/null +++ b/tests/data/acpi/q35/WAET.numamem.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/q35/WAET.tis b/tests/data/acpi/q35/WAET.tis new file mode 100644 index 0000000000..c2240f58df --- /dev/null +++ b/tests/data/acpi/q35/WAET.tis Binary files differdiff --git a/tests/data/acpi/q35/WAET.tis.dsl b/tests/data/acpi/q35/WAET.tis.dsl new file mode 100644 index 0000000000..869ebe2b4a --- /dev/null +++ b/tests/data/acpi/q35/WAET.tis.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/q35/WAET.tis, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [WAET] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "WAET" [Windows ACPI Emulated Devices Table] +[004h 0004 4] Table Length : 00000028 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 88 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCWAET" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Flags (decoded below) : 00000002 + RTC needs no INT ack : 0 + PM timer, one read only : 1 + +Raw Table Data: Length 40 (0x28) + + 0000: 57 41 45 54 28 00 00 00 01 88 42 4F 43 48 53 20 // WAET(.....BOCHS + 0010: 42 58 50 43 57 41 45 54 01 00 00 00 42 58 50 43 // BXPCWAET....BXPC + 0020: 01 00 00 00 02 00 00 00 // ........ diff --git a/tests/data/acpi/virt/APIC.dsl b/tests/data/acpi/virt/APIC.dsl new file mode 100644 index 0000000000..d334cef533 --- /dev/null +++ b/tests/data/acpi/virt/APIC.dsl @@ -0,0 +1,78 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/APIC.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A8 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 02 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 4C +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000008010000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +/**** ACPI subtable terminates early - may be older version (dump table) */ + +[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] +[091h 0145 1] Length : 18 +[092h 0146 2] Reserved : 0000 +[094h 0148 4] MSI Frame ID : 00000000 +[098h 0152 8] Base Address : 0000000008020000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + Select SPI : 1 +[0A4h 0164 2] SPI Count : 0040 +[0A6h 0166 2] SPI Base : 0050 + +Raw Table Data: Length 168 (0xA8) + + 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ + 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ + 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L.......... + 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................ + 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................ + 00A0: 01 00 00 00 40 00 50 00 // ....@.P. diff --git a/tests/data/acpi/virt/APIC.memhp.dsl b/tests/data/acpi/virt/APIC.memhp.dsl new file mode 100644 index 0000000000..9b86f7b984 --- /dev/null +++ b/tests/data/acpi/virt/APIC.memhp.dsl @@ -0,0 +1,78 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/APIC.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A8 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 02 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 4C +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000008010000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +/**** ACPI subtable terminates early - may be older version (dump table) */ + +[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] +[091h 0145 1] Length : 18 +[092h 0146 2] Reserved : 0000 +[094h 0148 4] MSI Frame ID : 00000000 +[098h 0152 8] Base Address : 0000000008020000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + Select SPI : 1 +[0A4h 0164 2] SPI Count : 0040 +[0A6h 0166 2] SPI Base : 0050 + +Raw Table Data: Length 168 (0xA8) + + 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ + 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ + 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L.......... + 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................ + 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................ + 00A0: 01 00 00 00 40 00 50 00 // ....@.P. diff --git a/tests/data/acpi/virt/APIC.numamem.dsl b/tests/data/acpi/virt/APIC.numamem.dsl new file mode 100644 index 0000000000..2d43338766 --- /dev/null +++ b/tests/data/acpi/virt/APIC.numamem.dsl @@ -0,0 +1,78 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/APIC.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [APIC] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "APIC" [Multiple APIC Description Table (MADT)] +[004h 0004 4] Table Length : 000000A8 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : B3 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCAPIC" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Local Apic Address : 00000000 +[028h 0040 4] Flags (decoded below) : 00000000 + PC-AT Compatibility : 0 + +[02Ch 0044 1] Subtable Type : 0C [Generic Interrupt Distributor] +[02Dh 0045 1] Length : 18 +[02Eh 0046 2] Reserved : 0000 +[030h 0048 4] Local GIC Hardware ID : 00000000 +[034h 0052 8] Base Address : 0000000008000000 +[03Ch 0060 4] Interrupt Base : 00000000 +[040h 0064 1] Version : 02 +[041h 0065 3] Reserved : 000000 + +[044h 0068 1] Subtable Type : 0B [Generic Interrupt Controller] +[045h 0069 1] Length : 4C +[046h 0070 2] Reserved : 0000 +[048h 0072 4] CPU Interface Number : 00000000 +[04Ch 0076 4] Processor UID : 00000000 +[050h 0080 4] Flags (decoded below) : 00000001 + Processor Enabled : 1 + Performance Interrupt Trigger Mode : 0 + Virtual GIC Interrupt Trigger Mode : 0 +[054h 0084 4] Parking Protocol Version : 00000000 +[058h 0088 4] Performance Interrupt : 00000017 +[05Ch 0092 8] Parked Address : 0000000000000000 +[064h 0100 8] Base Address : 0000000008010000 +[06Ch 0108 8] Virtual GIC Base Address : 0000000008040000 +[074h 0116 8] Hypervisor GIC Base Address : 0000000008030000 +[07Ch 0124 4] Virtual GIC Interrupt : 00000000 +[080h 0128 8] Redistributor Base Address : 0000000000000000 +[088h 0136 8] ARM MPIDR : 0000000000000000 +/**** ACPI subtable terminates early - may be older version (dump table) */ + +[090h 0144 1] Subtable Type : 0D [Generic MSI Frame] +[091h 0145 1] Length : 18 +[092h 0146 2] Reserved : 0000 +[094h 0148 4] MSI Frame ID : 00000000 +[098h 0152 8] Base Address : 0000000008020000 +[0A0h 0160 4] Flags (decoded below) : 00000001 + Select SPI : 1 +[0A4h 0164 2] SPI Count : 0040 +[0A6h 0166 2] SPI Base : 0050 + +Raw Table Data: Length 168 (0xA8) + + 0000: 41 50 49 43 A8 00 00 00 03 B3 42 4F 43 48 53 20 // APIC......BOCHS + 0010: 42 58 50 43 41 50 49 43 01 00 00 00 42 58 50 43 // BXPCAPIC....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 0C 18 00 00 // ................ + 0030: 00 00 00 00 00 00 00 08 00 00 00 00 00 00 00 00 // ................ + 0040: 02 00 00 00 0B 4C 00 00 00 00 00 00 00 00 00 00 // .....L.......... + 0050: 01 00 00 00 00 00 00 00 17 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 01 08 00 00 00 00 00 00 04 08 // ................ + 0070: 00 00 00 00 00 00 03 08 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 0D 18 00 00 00 00 00 00 00 00 02 08 00 00 00 00 // ................ + 00A0: 01 00 00 00 40 00 50 00 // ....@.P. diff --git a/tests/data/acpi/virt/DSDT.dsl b/tests/data/acpi/virt/DSDT.dsl new file mode 100644 index 0000000000..58368ff44c --- /dev/null +++ b/tests/data/acpi/virt/DSDT.dsl @@ -0,0 +1,1906 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/DSDT.numamem, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001450 (5200) + * Revision 0x02 + * Checksum 0xFA + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09000000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000021, + } + }) + } + + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09020000, // Address Base + 0x00000018, // Address Length + ) + }) + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000030, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000031, + } + }) + } + + Device (VR02) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000032, + } + }) + } + + Device (VR03) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000033, + } + }) + } + + Device (VR04) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000034, + } + }) + } + + Device (VR05) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000035, + } + }) + } + + Device (VR06) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000036, + } + }) + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000037, + } + }) + } + + Device (VR08) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x08) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000038, + } + }) + } + + Device (VR09) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x09) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000039, + } + }) + } + + Device (VR10) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003A, + } + }) + } + + Device (VR11) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003B, + } + }) + } + + Device (VR12) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003C, + } + }) + } + + Device (VR13) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003D, + } + }) + } + + Device (VR14) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003E, + } + }) + } + + Device (VR15) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003F, + } + }) + } + + Device (VR16) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000040, + } + }) + } + + Device (VR17) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + } + + Device (VR18) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000042, + } + }) + } + + Device (VR19) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000043, + } + }) + } + + Device (VR20) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000044, + } + }) + } + + Device (VR21) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000045, + } + }) + } + + Device (VR22) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000046, + } + }) + } + + Device (VR23) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000047, + } + }) + } + + Device (VR24) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x18) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000048, + } + }) + } + + Device (VR25) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x19) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000049, + } + }) + } + + Device (VR26) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004A, + } + }) + } + + Device (VR27) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004B, + } + }) + } + + Device (VR28) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004C, + } + }) + } + + Device (VR29) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004D, + } + }) + } + + Device (VR30) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004E, + } + }) + } + + Device (VR31) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004F, + } + }) + } + + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, Zero) // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + } + + Device (\_SB.GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000029, + } + }) + OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + } +} + diff --git a/tests/data/acpi/virt/DSDT.memhp.dsl b/tests/data/acpi/virt/DSDT.memhp.dsl new file mode 100644 index 0000000000..84f3c51867 --- /dev/null +++ b/tests/data/acpi/virt/DSDT.memhp.dsl @@ -0,0 +1,2215 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/DSDT.memhp, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x000019A6 (6566) + * Revision 0x02 + * Checksum 0x02 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + External (_SB_.NVDR, UnknownObj) + + Scope (\_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09000000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000021, + } + }) + } + + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09020000, // Address Base + 0x00000018, // Address Length + ) + }) + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000030, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000031, + } + }) + } + + Device (VR02) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000032, + } + }) + } + + Device (VR03) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000033, + } + }) + } + + Device (VR04) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000034, + } + }) + } + + Device (VR05) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000035, + } + }) + } + + Device (VR06) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000036, + } + }) + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000037, + } + }) + } + + Device (VR08) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x08) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000038, + } + }) + } + + Device (VR09) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x09) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000039, + } + }) + } + + Device (VR10) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003A, + } + }) + } + + Device (VR11) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003B, + } + }) + } + + Device (VR12) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003C, + } + }) + } + + Device (VR13) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003D, + } + }) + } + + Device (VR14) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003E, + } + }) + } + + Device (VR15) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003F, + } + }) + } + + Device (VR16) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000040, + } + }) + } + + Device (VR17) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + } + + Device (VR18) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000042, + } + }) + } + + Device (VR19) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000043, + } + }) + } + + Device (VR20) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000044, + } + }) + } + + Device (VR21) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000045, + } + }) + } + + Device (VR22) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000046, + } + }) + } + + Device (VR23) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000047, + } + }) + } + + Device (VR24) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x18) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000048, + } + }) + } + + Device (VR25) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x19) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000049, + } + }) + } + + Device (VR26) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004A, + } + }) + } + + Device (VR27) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004B, + } + }) + } + + Device (VR28) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004C, + } + }) + } + + Device (VR29) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004D, + } + }) + } + + Device (VR30) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004E, + } + }) + } + + Device (VR31) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004F, + } + }) + } + + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, "PCI0") // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + } + + Device (\_SB.GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000029, + } + }) + OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & One) == One)) + { + \_SB.MHPC.MSCN () + } + + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + + If (((Local0 & 0x04) == 0x04)) + { + Notify (\_SB.NVDR, 0x80) // Status Change + } + } + } + + Device (\_SB.MHPD) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "Memory hotplug resources") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09070000, // Address Base + 0x00000018, // Address Length + ) + }) + OperationRegion (HPMR, SystemMemory, 0x09070000, 0x18) + } + + Device (\_SB.MHPC) + { + Name (_HID, "PNP0A06" /* Generic Container Device */) // _HID: Hardware ID + Name (_UID, "DIMM devices") // _UID: Unique ID + Name (MDNR, 0x03) + Field (\_SB.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MRBL, 32, + MRBH, 32, + MRLL, 32, + MRLH, 32, + MPX, 32 + } + + Field (\_SB.MHPD.HPMR, ByteAcc, NoLock, WriteAsZeros) + { + Offset (0x14), + MES, 1, + MINS, 1, + MRMV, 1, + MEJ, 1 + } + + Field (\_SB.MHPD.HPMR, DWordAcc, NoLock, Preserve) + { + MSEL, 32, + MOEV, 32, + MOSC, 32 + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Return (0x0B) + } + + Mutex (MLCK, 0x00) + Method (MSCN, 0, NotSerialized) + { + If ((MDNR == Zero)) + { + Return (Zero) + } + + Local0 = Zero + Acquire (MLCK, 0xFFFF) + While ((Local0 < MDNR)) + { + MSEL = Local0 + If ((MINS == One)) + { + MTFY (Local0, One) + MINS = One + } + ElseIf ((MRMV == One)) + { + MTFY (Local0, 0x03) + MRMV = One + } + + Local0 += One + } + + Release (MLCK) + Return (One) + } + + Method (MRST, 1, NotSerialized) + { + Local0 = Zero + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + If ((MES == One)) + { + Local0 = 0x0F + } + + Release (MLCK) + Return (Local0) + } + + Method (MCRS, 1, Serialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Name (MR64, ResourceTemplate () + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000000000000000, // Range Minimum + 0xFFFFFFFFFFFFFFFE, // Range Maximum + 0x0000000000000000, // Translation Offset + 0xFFFFFFFFFFFFFFFF, // Length + ,, _Y00, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._MIN, MINL) // _MIN: Minimum Base Address + CreateDWordField (MR64, 0x12, MINH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._LEN, LENL) // _LEN: Length + CreateDWordField (MR64, 0x2A, LENH) + CreateDWordField (MR64, \_SB.MHPC.MCRS._Y00._MAX, MAXL) // _MAX: Maximum Base Address + CreateDWordField (MR64, 0x1A, MAXH) + MINH = MRBH /* \_SB_.MHPC.MRBH */ + MINL = MRBL /* \_SB_.MHPC.MRBL */ + LENH = MRLH /* \_SB_.MHPC.MRLH */ + LENL = MRLL /* \_SB_.MHPC.MRLL */ + MAXL = (MINL + LENL) /* \_SB_.MHPC.MCRS.LENL */ + MAXH = (MINH + LENH) /* \_SB_.MHPC.MCRS.LENH */ + If ((MAXL < MINL)) + { + MAXH += One + } + + If ((MAXL < One)) + { + MAXH -= One + } + + MAXL -= One + If ((MAXH == Zero)) + { + Name (MR32, ResourceTemplate () + { + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, Cacheable, ReadWrite, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0xFFFFFFFE, // Range Maximum + 0x00000000, // Translation Offset + 0xFFFFFFFF, // Length + ,, _Y01, AddressRangeMemory, TypeStatic) + }) + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._MIN, MIN) // _MIN: Minimum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._MAX, MAX) // _MAX: Maximum Base Address + CreateDWordField (MR32, \_SB.MHPC.MCRS._Y01._LEN, LEN) // _LEN: Length + MIN = MINL /* \_SB_.MHPC.MCRS.MINL */ + MAX = MAXL /* \_SB_.MHPC.MCRS.MAXL */ + LEN = LENL /* \_SB_.MHPC.MCRS.LENL */ + Release (MLCK) + Return (MR32) /* \_SB_.MHPC.MCRS.MR32 */ + } + + Release (MLCK) + Return (MR64) /* \_SB_.MHPC.MCRS.MR64 */ + } + + Method (MPXM, 1, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + Local0 = MPX /* \_SB_.MHPC.MPX_ */ + Release (MLCK) + Return (Local0) + } + + Method (MOST, 4, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MOEV = Arg1 + MOSC = Arg2 + Release (MLCK) + } + + Method (MEJ0, 2, NotSerialized) + { + Acquire (MLCK, 0xFFFF) + MSEL = ToInteger (Arg0) + MEJ = One + Release (MLCK) + } + + Device (MP00) + { + Name (_UID, "0x00") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP01) + { + Name (_UID, "0x01") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Device (MP02) + { + Name (_UID, "0x02") // _UID: Unique ID + Name (_HID, EisaId ("PNP0C80") /* Memory Device */) // _HID: Hardware ID + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (MCRS (_UID)) + } + + Method (_STA, 0, NotSerialized) // _STA: Status + { + Return (MRST (_UID)) + } + + Method (_PXM, 0, NotSerialized) // _PXM: Device Proximity + { + Return (MPXM (_UID)) + } + + Method (_OST, 3, NotSerialized) // _OST: OSPM Status Indication + { + MOST (_UID, Arg0, Arg1, Arg2) + } + + Method (_EJ0, 1, NotSerialized) // _EJx: Eject Device, x=0-9 + { + MEJ0 (_UID, Arg0) + } + } + + Method (MTFY, 2, NotSerialized) + { + If ((Arg0 == Zero)) + { + Notify (MP00, Arg1) + } + + If ((Arg0 == One)) + { + Notify (MP01, Arg1) + } + + If ((Arg0 == 0x02)) + { + Notify (MP02, Arg1) + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + } +} + diff --git a/tests/data/acpi/virt/DSDT.numamem.dsl b/tests/data/acpi/virt/DSDT.numamem.dsl new file mode 100644 index 0000000000..6603d31a01 --- /dev/null +++ b/tests/data/acpi/virt/DSDT.numamem.dsl @@ -0,0 +1,1906 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/DSDT.numamem, Tue Aug 4 11:14:15 2020 + * + * Original Table Header: + * Signature "DSDT" + * Length 0x00001455 (5205) + * Revision 0x02 + * Checksum 0xE1 + * OEM ID "BOCHS " + * OEM Table ID "BXPCDSDT" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "DSDT", 2, "BOCHS ", "BXPCDSDT", 0x00000001) +{ + Scope (\_SB) + { + Device (C000) + { + Name (_HID, "ACPI0007" /* Processor Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + + Device (COM0) + { + Name (_HID, "ARMH0011") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09000000, // Address Base + 0x00001000, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000021, + } + }) + } + + Device (FWCF) + { + Name (_HID, "QEMU0002") // _HID: Hardware ID + Name (_STA, 0x0B) // _STA: Status + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x09020000, // Address Base + 0x00000018, // Address Length + ) + }) + } + + Device (VR00) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000030, + } + }) + } + + Device (VR01) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000031, + } + }) + } + + Device (VR02) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000032, + } + }) + } + + Device (VR03) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000033, + } + }) + } + + Device (VR04) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x04) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000034, + } + }) + } + + Device (VR05) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x05) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000035, + } + }) + } + + Device (VR06) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x06) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000036, + } + }) + } + + Device (VR07) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x07) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A000E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000037, + } + }) + } + + Device (VR08) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x08) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000038, + } + }) + } + + Device (VR09) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x09) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000039, + } + }) + } + + Device (VR10) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003A, + } + }) + } + + Device (VR11) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003B, + } + }) + } + + Device (VR12) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003C, + } + }) + } + + Device (VR13) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003D, + } + }) + } + + Device (VR14) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003E, + } + }) + } + + Device (VR15) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x0F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A001E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000003F, + } + }) + } + + Device (VR16) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x10) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000040, + } + }) + } + + Device (VR17) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x11) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000041, + } + }) + } + + Device (VR18) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x12) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000042, + } + }) + } + + Device (VR19) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x13) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000043, + } + }) + } + + Device (VR20) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x14) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000044, + } + }) + } + + Device (VR21) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x15) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000045, + } + }) + } + + Device (VR22) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x16) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000046, + } + }) + } + + Device (VR23) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x17) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A002E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000047, + } + }) + } + + Device (VR24) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x18) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003000, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000048, + } + }) + } + + Device (VR25) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x19) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003200, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000049, + } + }) + } + + Device (VR26) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1A) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003400, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004A, + } + }) + } + + Device (VR27) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1B) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003600, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004B, + } + }) + } + + Device (VR28) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1C) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003800, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004C, + } + }) + } + + Device (VR29) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1D) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003A00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004D, + } + }) + } + + Device (VR30) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1E) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003C00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004E, + } + }) + } + + Device (VR31) + { + Name (_HID, "LNRO0005") // _HID: Hardware ID + Name (_UID, 0x1F) // _UID: Unique ID + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Memory32Fixed (ReadWrite, + 0x0A003E00, // Address Base + 0x00000200, // Address Length + ) + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x0000004F, + } + }) + } + + Device (PCI0) + { + Name (_HID, "PNP0A08" /* PCI Express Bus */) // _HID: Hardware ID + Name (_CID, "PNP0A03" /* PCI Bus */) // _CID: Compatible ID + Name (_SEG, Zero) // _SEG: PCI Segment + Name (_BBN, Zero) // _BBN: BIOS Bus Number + Name (_UID, "PCI0") // _UID: Unique ID + Name (_STR, Unicode ("PCIe 0 Device")) // _STR: Description String + Name (_CCA, One) // _CCA: Cache Coherency Attribute + Name (_PRT, Package (0x80) // _PRT: PCI Routing Table + { + Package (0x04) + { + 0xFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0xFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0xFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0001FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0002FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0003FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0004FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0005FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0006FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0007FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0008FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0009FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x000FFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0010FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0011FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0012FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0013FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0014FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0015FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0016FFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0017FFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0018FFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x0019FFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001AFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001BFFFF, + 0x03, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + Zero, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + One, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x02, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001CFFFF, + 0x03, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + Zero, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + One, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x02, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001DFFFF, + 0x03, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + Zero, + GSI2, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + One, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x02, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001EFFFF, + 0x03, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + Zero, + GSI3, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + One, + GSI0, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x02, + GSI1, + Zero + }, + + Package (0x04) + { + 0x001FFFFF, + 0x03, + GSI2, + Zero + } + }) + Device (GSI0) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000023, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI1) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, One) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000024, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI2) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x02) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000025, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Device (GSI3) + { + Name (_HID, "PNP0C0F" /* PCI Interrupt Link Device */) // _HID: Hardware ID + Name (_UID, 0x03) // _UID: Unique ID + Name (_PRS, ResourceTemplate () // _PRS: Possible Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Level, ActiveHigh, Exclusive, ,, ) + { + 0x00000026, + } + }) + Method (_SRS, 1, NotSerialized) // _SRS: Set Resource Settings + { + } + } + + Method (_CBA, 0, NotSerialized) // _CBA: Configuration Base Address + { + Return (0x0000004010000000) + } + + Method (_CRS, 0, NotSerialized) // _CRS: Current Resource Settings + { + Return (ResourceTemplate () + { + WordBusNumber (ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, // Granularity + 0x0000, // Range Minimum + 0x00FF, // Range Maximum + 0x0000, // Translation Offset + 0x0100, // Length + ,, ) + DWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x00000000, // Granularity + 0x10000000, // Range Minimum + 0x3EFEFFFF, // Range Maximum + 0x00000000, // Translation Offset + 0x2EFF0000, // Length + ,, , AddressRangeMemory, TypeStatic) + DWordIO (ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x00000000, // Granularity + 0x00000000, // Range Minimum + 0x0000FFFF, // Range Maximum + 0x3EFF0000, // Translation Offset + 0x00010000, // Length + ,, , TypeStatic, DenseTranslation) + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000008000000000, // Range Minimum + 0x000000FFFFFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000008000000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + + Name (SUPP, Zero) + Name (CTRL, Zero) + Method (_OSC, 4, NotSerialized) // _OSC: Operating System Capabilities + { + CreateDWordField (Arg3, Zero, CDW1) + If ((Arg0 == ToUUID ("33db4d5b-1ff7-401c-9657-7441c03dd766") /* PCI Host Bridge Device */)) + { + CreateDWordField (Arg3, 0x04, CDW2) + CreateDWordField (Arg3, 0x08, CDW3) + SUPP = CDW2 /* \_SB_.PCI0._OSC.CDW2 */ + CTRL = CDW3 /* \_SB_.PCI0._OSC.CDW3 */ + CTRL &= 0x1F + If ((Arg1 != One)) + { + CDW1 |= 0x08 + } + + If ((CDW3 != CTRL)) + { + CDW1 |= 0x10 + } + + CDW3 = CTRL /* \_SB_.PCI0.CTRL */ + Return (Arg3) + } + Else + { + CDW1 |= 0x04 + Return (Arg3) + } + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + If ((Arg0 == ToUUID ("e5c937d0-3553-4d7a-9117-ea4d19c3434d") /* Device Labeling Interface */)) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x01 // . + }) + } + } + + Return (Buffer (One) + { + 0x00 // . + }) + } + + Device (RES0) + { + Name (_HID, "PNP0C02" /* PNP Motherboard Resources */) // _HID: Hardware ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + QWordMemory (ResourceProducer, PosDecode, MinFixed, MaxFixed, NonCacheable, ReadWrite, + 0x0000000000000000, // Granularity + 0x0000004010000000, // Range Minimum + 0x000000401FFFFFFF, // Range Maximum + 0x0000000000000000, // Translation Offset + 0x0000000010000000, // Length + ,, , AddressRangeMemory, TypeStatic) + }) + } + } + + Device (\_SB.GED) + { + Name (_HID, "ACPI0013" /* Generic Event Device */) // _HID: Hardware ID + Name (_UID, "GED") // _UID: Unique ID + Name (_CRS, ResourceTemplate () // _CRS: Current Resource Settings + { + Interrupt (ResourceConsumer, Edge, ActiveHigh, Exclusive, ,, ) + { + 0x00000029, + } + }) + OperationRegion (EREG, SystemMemory, 0x09080000, 0x04) + Field (EREG, DWordAcc, NoLock, WriteAsZeros) + { + ESEL, 32 + } + + Method (_EVT, 1, Serialized) // _EVT: Event + { + Local0 = ESEL /* \_SB_.GED_.ESEL */ + If (((Local0 & 0x02) == 0x02)) + { + Notify (PWRB, 0x80) // Status Change + } + } + } + + Device (PWRB) + { + Name (_HID, "PNP0C0C" /* Power Button Device */) // _HID: Hardware ID + Name (_UID, Zero) // _UID: Unique ID + } + } +} + diff --git a/tests/data/acpi/virt/FACP.dsl b/tests/data/acpi/virt/FACP.dsl new file mode 100644 index 0000000000..2c73796f89 --- /dev/null +++ b/tests/data/acpi/virt/FACP.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/FACP.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : BB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000000 + +[080h 0128 1] Value to cause reset : 00 +[081h 0129 2] ARM Flags (decoded below) : 0003 + PSCI Compliant : 1 + Must use HVC for PSCI : 1 + +[083h 0131 1] FADT Minor Revision : 01 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ diff --git a/tests/data/acpi/virt/FACP.memhp.dsl b/tests/data/acpi/virt/FACP.memhp.dsl new file mode 100644 index 0000000000..0083b95ef7 --- /dev/null +++ b/tests/data/acpi/virt/FACP.memhp.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/FACP.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : BB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000000 + +[080h 0128 1] Value to cause reset : 00 +[081h 0129 2] ARM Flags (decoded below) : 0003 + PSCI Compliant : 1 + Must use HVC for PSCI : 1 + +[083h 0131 1] FADT Minor Revision : 01 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ diff --git a/tests/data/acpi/virt/FACP.numamem.dsl b/tests/data/acpi/virt/FACP.numamem.dsl new file mode 100644 index 0000000000..aee15bd4c2 --- /dev/null +++ b/tests/data/acpi/virt/FACP.numamem.dsl @@ -0,0 +1,196 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/FACP.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [FACP] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "FACP" [Fixed ACPI Description Table (FADT)] +[004h 0004 4] Table Length : 0000010C +[008h 0008 1] Revision : 05 +[009h 0009 1] Checksum : BB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCFACP" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] FACS Address : 00000000 +[028h 0040 4] DSDT Address : 00000000 +[02Ch 0044 1] Model : 00 +[02Dh 0045 1] PM Profile : 00 [Unspecified] +[02Eh 0046 2] SCI Interrupt : 0000 +[030h 0048 4] SMI Command Port : 00000000 +[034h 0052 1] ACPI Enable Value : 00 +[035h 0053 1] ACPI Disable Value : 00 +[036h 0054 1] S4BIOS Command : 00 +[037h 0055 1] P-State Control : 00 +[038h 0056 4] PM1A Event Block Address : 00000000 +[03Ch 0060 4] PM1B Event Block Address : 00000000 +[040h 0064 4] PM1A Control Block Address : 00000000 +[044h 0068 4] PM1B Control Block Address : 00000000 +[048h 0072 4] PM2 Control Block Address : 00000000 +[04Ch 0076 4] PM Timer Block Address : 00000000 +[050h 0080 4] GPE0 Block Address : 00000000 +[054h 0084 4] GPE1 Block Address : 00000000 +[058h 0088 1] PM1 Event Block Length : 00 +[059h 0089 1] PM1 Control Block Length : 00 +[05Ah 0090 1] PM2 Control Block Length : 00 +[05Bh 0091 1] PM Timer Block Length : 00 +[05Ch 0092 1] GPE0 Block Length : 00 +[05Dh 0093 1] GPE1 Block Length : 00 +[05Eh 0094 1] GPE1 Base Offset : 00 +[05Fh 0095 1] _CST Support : 00 +[060h 0096 2] C2 Latency : 0000 +[062h 0098 2] C3 Latency : 0000 +[064h 0100 2] CPU Cache Size : 0000 +[066h 0102 2] Cache Flush Stride : 0000 +[068h 0104 1] Duty Cycle Offset : 00 +[069h 0105 1] Duty Cycle Width : 00 +[06Ah 0106 1] RTC Day Alarm Index : 00 +[06Bh 0107 1] RTC Month Alarm Index : 00 +[06Ch 0108 1] RTC Century Index : 00 +[06Dh 0109 2] Boot Flags (decoded below) : 0000 + Legacy Devices Supported (V2) : 0 + 8042 Present on ports 60/64 (V2) : 0 + VGA Not Present (V4) : 0 + MSI Not Supported (V4) : 0 + PCIe ASPM Not Supported (V4) : 0 + CMOS RTC Not Present (V5) : 0 +[06Fh 0111 1] Reserved : 00 +[070h 0112 4] Flags (decoded below) : 00100000 + WBINVD instruction is operational (V1) : 0 + WBINVD flushes all caches (V1) : 0 + All CPUs support C1 (V1) : 0 + C2 works on MP system (V1) : 0 + Control Method Power Button (V1) : 0 + Control Method Sleep Button (V1) : 0 + RTC wake not in fixed reg space (V1) : 0 + RTC can wake system from S4 (V1) : 0 + 32-bit PM Timer (V1) : 0 + Docking Supported (V1) : 0 + Reset Register Supported (V2) : 0 + Sealed Case (V3) : 0 + Headless - No Video (V3) : 0 + Use native instr after SLP_TYPx (V3) : 0 + PCIEXP_WAK Bits Supported (V4) : 0 + Use Platform Timer (V4) : 0 + RTC_STS valid on S4 wake (V4) : 0 + Remote Power-on capable (V4) : 0 + Use APIC Cluster Model (V4) : 0 + Use APIC Physical Destination Mode (V4) : 0 + Hardware Reduced (V5) : 1 + Low Power S0 Idle (V5) : 0 + +[074h 0116 12] Reset Register : [Generic Address Structure] +[074h 0116 1] Space ID : 00 [SystemMemory] +[075h 0117 1] Bit Width : 00 +[076h 0118 1] Bit Offset : 00 +[077h 0119 1] Encoded Access Width : 00 [Undefined/Legacy] +[078h 0120 8] Address : 0000000000000000 + +[080h 0128 1] Value to cause reset : 00 +[081h 0129 2] ARM Flags (decoded below) : 0003 + PSCI Compliant : 1 + Must use HVC for PSCI : 1 + +[083h 0131 1] FADT Minor Revision : 01 +[084h 0132 8] FACS Address : 0000000000000000 +[08Ch 0140 8] DSDT Address : 0000000000000000 +[094h 0148 12] PM1A Event Block : [Generic Address Structure] +[094h 0148 1] Space ID : 00 [SystemMemory] +[095h 0149 1] Bit Width : 00 +[096h 0150 1] Bit Offset : 00 +[097h 0151 1] Encoded Access Width : 00 [Undefined/Legacy] +[098h 0152 8] Address : 0000000000000000 + +[0A0h 0160 12] PM1B Event Block : [Generic Address Structure] +[0A0h 0160 1] Space ID : 00 [SystemMemory] +[0A1h 0161 1] Bit Width : 00 +[0A2h 0162 1] Bit Offset : 00 +[0A3h 0163 1] Encoded Access Width : 00 [Undefined/Legacy] +[0A4h 0164 8] Address : 0000000000000000 + +[0ACh 0172 12] PM1A Control Block : [Generic Address Structure] +[0ACh 0172 1] Space ID : 00 [SystemMemory] +[0ADh 0173 1] Bit Width : 00 +[0AEh 0174 1] Bit Offset : 00 +[0AFh 0175 1] Encoded Access Width : 00 [Undefined/Legacy] +[0B0h 0176 8] Address : 0000000000000000 + +[0B8h 0184 12] PM1B Control Block : [Generic Address Structure] +[0B8h 0184 1] Space ID : 00 [SystemMemory] +[0B9h 0185 1] Bit Width : 00 +[0BAh 0186 1] Bit Offset : 00 +[0BBh 0187 1] Encoded Access Width : 00 [Undefined/Legacy] +[0BCh 0188 8] Address : 0000000000000000 + +[0C4h 0196 12] PM2 Control Block : [Generic Address Structure] +[0C4h 0196 1] Space ID : 00 [SystemMemory] +[0C5h 0197 1] Bit Width : 00 +[0C6h 0198 1] Bit Offset : 00 +[0C7h 0199 1] Encoded Access Width : 00 [Undefined/Legacy] +[0C8h 0200 8] Address : 0000000000000000 + +[0D0h 0208 12] PM Timer Block : [Generic Address Structure] +[0D0h 0208 1] Space ID : 00 [SystemMemory] +[0D1h 0209 1] Bit Width : 00 +[0D2h 0210 1] Bit Offset : 00 +[0D3h 0211 1] Encoded Access Width : 00 [Undefined/Legacy] +[0D4h 0212 8] Address : 0000000000000000 + +[0DCh 0220 12] GPE0 Block : [Generic Address Structure] +[0DCh 0220 1] Space ID : 00 [SystemMemory] +[0DDh 0221 1] Bit Width : 00 +[0DEh 0222 1] Bit Offset : 00 +[0DFh 0223 1] Encoded Access Width : 00 [Undefined/Legacy] +[0E0h 0224 8] Address : 0000000000000000 + +[0E8h 0232 12] GPE1 Block : [Generic Address Structure] +[0E8h 0232 1] Space ID : 00 [SystemMemory] +[0E9h 0233 1] Bit Width : 00 +[0EAh 0234 1] Bit Offset : 00 +[0EBh 0235 1] Encoded Access Width : 00 [Undefined/Legacy] +[0ECh 0236 8] Address : 0000000000000000 + + +[0F4h 0244 12] Sleep Control Register : [Generic Address Structure] +[0F4h 0244 1] Space ID : 00 [SystemMemory] +[0F5h 0245 1] Bit Width : 00 +[0F6h 0246 1] Bit Offset : 00 +[0F7h 0247 1] Encoded Access Width : 00 [Undefined/Legacy] +[0F8h 0248 8] Address : 0000000000000000 + +[100h 0256 12] Sleep Status Register : [Generic Address Structure] +[100h 0256 1] Space ID : 00 [SystemMemory] +[101h 0257 1] Bit Width : 00 +[102h 0258 1] Bit Offset : 00 +[103h 0259 1] Encoded Access Width : 00 [Undefined/Legacy] +[104h 0260 8] Address : 0000000000000000 + +/**** ACPI table terminates in the middle of a data structure! (dump table) */ + +Raw Table Data: Length 268 (0x10C) + + 0000: 46 41 43 50 0C 01 00 00 05 BB 42 4F 43 48 53 20 // FACP......BOCHS + 0010: 42 58 50 43 46 41 43 50 01 00 00 00 42 58 50 43 // BXPCFACP....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0040: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0070: 00 00 10 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 03 00 01 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00A0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00F0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0100: 00 00 00 00 00 00 00 00 00 00 00 00 // ............ diff --git a/tests/data/acpi/virt/GTDT.dsl b/tests/data/acpi/virt/GTDT.dsl new file mode 100644 index 0000000000..1ab06dd3c2 --- /dev/null +++ b/tests/data/acpi/virt/GTDT.dsl @@ -0,0 +1,61 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/GTDT.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [GTDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 00000060 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : D9 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCGTDT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Counter Block Address : 0000000000000000 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 0000001D +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004 + Trigger Mode : 0 + Polarity : 0 + Always On : 1 + +[040h 0064 4] Virtual Timer Interrupt : 0000001B +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : 0000000000000000 + +[058h 0088 4] Platform Timer Count : 00000000 +[05Ch 0092 4] Platform Timer Offset : 00000000 + +Raw Table Data: Length 96 (0x60) + + 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ + 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/GTDT.memhp.dsl b/tests/data/acpi/virt/GTDT.memhp.dsl new file mode 100644 index 0000000000..d78bb092c5 --- /dev/null +++ b/tests/data/acpi/virt/GTDT.memhp.dsl @@ -0,0 +1,61 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/GTDT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [GTDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 00000060 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : D9 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCGTDT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Counter Block Address : 0000000000000000 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 0000001D +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004 + Trigger Mode : 0 + Polarity : 0 + Always On : 1 + +[040h 0064 4] Virtual Timer Interrupt : 0000001B +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : 0000000000000000 + +[058h 0088 4] Platform Timer Count : 00000000 +[05Ch 0092 4] Platform Timer Offset : 00000000 + +Raw Table Data: Length 96 (0x60) + + 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ + 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/GTDT.numamem.dsl b/tests/data/acpi/virt/GTDT.numamem.dsl new file mode 100644 index 0000000000..5c3c2a83db --- /dev/null +++ b/tests/data/acpi/virt/GTDT.numamem.dsl @@ -0,0 +1,61 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/GTDT.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [GTDT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "GTDT" [Generic Timer Description Table] +[004h 0004 4] Table Length : 00000060 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : D9 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCGTDT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Counter Block Address : 0000000000000000 +[02Ch 0044 4] Reserved : 00000000 + +[030h 0048 4] Secure EL1 Interrupt : 0000001D +[034h 0052 4] EL1 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[038h 0056 4] Non-Secure EL1 Interrupt : 0000001E +[03Ch 0060 4] NEL1 Flags (decoded below) : 00000004 + Trigger Mode : 0 + Polarity : 0 + Always On : 1 + +[040h 0064 4] Virtual Timer Interrupt : 0000001B +[044h 0068 4] VT Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 + +[048h 0072 4] Non-Secure EL2 Interrupt : 0000001A +[04Ch 0076 4] NEL2 Flags (decoded below) : 00000000 + Trigger Mode : 0 + Polarity : 0 + Always On : 0 +[050h 0080 8] Counter Read Block Address : 0000000000000000 + +[058h 0088 4] Platform Timer Count : 00000000 +[05Ch 0092 4] Platform Timer Offset : 00000000 + +Raw Table Data: Length 96 (0x60) + + 0000: 47 54 44 54 60 00 00 00 02 D9 42 4F 43 48 53 20 // GTDT`.....BOCHS + 0010: 42 58 50 43 47 54 44 54 01 00 00 00 42 58 50 43 // BXPCGTDT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 1D 00 00 00 00 00 00 00 1E 00 00 00 04 00 00 00 // ................ + 0040: 1B 00 00 00 00 00 00 00 1A 00 00 00 00 00 00 00 // ................ + 0050: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/MCFG.dsl b/tests/data/acpi/virt/MCFG.dsl new file mode 100644 index 0000000000..f09c86f487 --- /dev/null +++ b/tests/data/acpi/virt/MCFG.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/MCFG.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 4F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 0000004010000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................ + 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @........... diff --git a/tests/data/acpi/virt/MCFG.memhp.dsl b/tests/data/acpi/virt/MCFG.memhp.dsl new file mode 100644 index 0000000000..b03a6384e8 --- /dev/null +++ b/tests/data/acpi/virt/MCFG.memhp.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/MCFG.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 4F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 0000004010000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................ + 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @........... diff --git a/tests/data/acpi/virt/MCFG.numamem.dsl b/tests/data/acpi/virt/MCFG.numamem.dsl new file mode 100644 index 0000000000..303df803f5 --- /dev/null +++ b/tests/data/acpi/virt/MCFG.numamem.dsl @@ -0,0 +1,36 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/MCFG.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [MCFG] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "MCFG" [Memory Mapped Configuration table] +[004h 0004 4] Table Length : 0000003C +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 4F +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCMCFG" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Reserved : 0000000000000000 + +[02Ch 0044 8] Base Address : 0000004010000000 +[034h 0052 2] Segment Group Number : 0000 +[036h 0054 1] Start Bus Number : 00 +[037h 0055 1] End Bus Number : FF +[038h 0056 4] Reserved : 00000000 + +Raw Table Data: Length 60 (0x3C) + + 0000: 4D 43 46 47 3C 00 00 00 01 4F 42 4F 43 48 53 20 // MCFG<....OBOCHS + 0010: 42 58 50 43 4D 43 46 47 01 00 00 00 42 58 50 43 // BXPCMCFG....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 00 00 00 00 00 10 // ................ + 0030: 40 00 00 00 00 00 00 FF 00 00 00 00 // @........... diff --git a/tests/data/acpi/virt/NFIT.dsl b/tests/data/acpi/virt/NFIT.dsl new file mode 100644 index 0000000000..947ba0f6a4 --- /dev/null +++ b/tests/data/acpi/virt/NFIT.dsl @@ -0,0 +1,103 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/NFIT.memhp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : D1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000001 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000088000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 4E 46 49 54 E0 00 00 00 01 D1 42 4F 43 48 53 20 // NFIT......BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 01 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 88 00 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/NFIT.memhp.dsl b/tests/data/acpi/virt/NFIT.memhp.dsl new file mode 100644 index 0000000000..84511bff96 --- /dev/null +++ b/tests/data/acpi/virt/NFIT.memhp.dsl @@ -0,0 +1,103 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/NFIT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [NFIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "NFIT" [NVDIMM Firmware Interface Table] +[004h 0004 4] Table Length : 000000E0 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : D1 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCNFIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Reserved : 00000000 + +[028h 0040 2] Subtable Type : 0000 [System Physical Address Range] +[02Ah 0042 2] Length : 0038 + +[02Ch 0044 2] Range Index : 0004 +[02Eh 0046 2] Flags (decoded below) : 0003 + Add/Online Operation Only : 1 + Proximity Domain Valid : 1 +[030h 0048 4] Reserved : 00000000 +[034h 0052 4] Proximity Domain : 00000001 +[038h 0056 16] Region Type GUID : 66F0D379-B4F3-4074-AC43-0D3318B78CDB +[048h 0072 8] Address Range Base : 0000000088000000 +[050h 0080 8] Address Range Length : 0000000008000000 +[058h 0088 8] Memory Map Attribute : 0000000000008008 + +[060h 0096 2] Subtable Type : 0001 [Memory Range Map] +[062h 0098 2] Length : 0030 + +[064h 0100 4] Device Handle : 00000002 +[068h 0104 2] Physical Id : 0000 +[06Ah 0106 2] Region Id : 0000 +[06Ch 0108 2] Range Index : 0004 +[06Eh 0110 2] Control Region Index : 0005 +[070h 0112 8] Region Size : 0000000008000000 +[078h 0120 8] Region Offset : 0000000000000000 +[080h 0128 8] Address Region Base : 0000000000000000 +[088h 0136 2] Interleave Index : 0000 +[08Ah 0138 2] Interleave Ways : 0001 +[08Ch 0140 2] Flags : 0000 + Save to device failed : 0 + Restore from device failed : 0 + Platform flush failed : 0 + Device not armed : 0 + Health events observed : 0 + Health events enabled : 0 + Mapping failed : 0 +[08Eh 0142 2] Reserved : 0000 + +[090h 0144 2] Subtable Type : 0004 [NVDIMM Control Region] +[092h 0146 2] Length : 0050 + +[094h 0148 2] Region Index : 0005 +[096h 0150 2] Vendor Id : 8086 +[098h 0152 2] Device Id : 0001 +[09Ah 0154 2] Revision Id : 0001 +[09Ch 0156 2] Subsystem Vendor Id : 0000 +[09Eh 0158 2] Subsystem Device Id : 0000 +[0A0h 0160 2] Subsystem Revision Id : 0000 +[0A2h 0162 1] Valid Fields : 00 +[0A3h 0163 1] Manufacturing Location : 00 +[0A4h 0164 2] Manufacturing Date : 0000 +[0A6h 0166 2] Reserved : 0000 +[0A8h 0168 4] Serial Number : 00123457 +[0ACh 0172 2] Code : 0301 +[0AEh 0174 2] Window Count : 0000 +[0B0h 0176 8] Window Size : 0000000000000000 +[0B8h 0184 8] Command Offset : 0000000000000000 +[0C0h 0192 8] Command Size : 0000000000000000 +[0C8h 0200 8] Status Offset : 0000000000000000 +[0D0h 0208 8] Status Size : 0000000000000000 +[0D8h 0216 2] Flags : 0000 + Windows buffered : 0 +[0DAh 0218 6] Reserved1 : 000000000000 + +Raw Table Data: Length 224 (0xE0) + + 0000: 4E 46 49 54 E0 00 00 00 01 D1 42 4F 43 48 53 20 // NFIT......BOCHS + 0010: 42 58 50 43 4E 46 49 54 01 00 00 00 42 58 50 43 // BXPCNFIT....BXPC + 0020: 01 00 00 00 00 00 00 00 00 00 38 00 04 00 03 00 // ..........8..... + 0030: 00 00 00 00 01 00 00 00 79 D3 F0 66 F3 B4 74 40 // ........y..f..t@ + 0040: AC 43 0D 33 18 B7 8C DB 00 00 00 88 00 00 00 00 // .C.3............ + 0050: 00 00 00 08 00 00 00 00 08 80 00 00 00 00 00 00 // ................ + 0060: 01 00 30 00 02 00 00 00 00 00 00 00 04 00 05 00 // ..0............. + 0070: 00 00 00 08 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0080: 00 00 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0090: 04 00 50 00 05 00 86 80 01 00 01 00 00 00 00 00 // ..P............. + 00A0: 00 00 00 00 00 00 00 00 57 34 12 00 01 03 00 00 // ........W4...... + 00B0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00C0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ + 00D0: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SLIT.dsl b/tests/data/acpi/virt/SLIT.dsl new file mode 100644 index 0000000000..34276fca96 --- /dev/null +++ b/tests/data/acpi/virt/SLIT.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SLIT.memhp, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/virt/SLIT.memhp.dsl b/tests/data/acpi/virt/SLIT.memhp.dsl new file mode 100644 index 0000000000..a17f948af2 --- /dev/null +++ b/tests/data/acpi/virt/SLIT.memhp.dsl @@ -0,0 +1,31 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SLIT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SLIT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SLIT" [System Locality Information Table] +[004h 0004 4] Table Length : 00000030 +[008h 0008 1] Revision : 01 +[009h 0009 1] Checksum : 2C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSLIT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 8] Localities : 0000000000000002 +[02Ch 0044 2] Locality 0 : 0A 15 +[02Eh 0046 2] Locality 1 : 15 0A + +Raw Table Data: Length 48 (0x30) + + 0000: 53 4C 49 54 30 00 00 00 01 2C 42 4F 43 48 53 20 // SLIT0....,BOCHS + 0010: 42 58 50 43 53 4C 49 54 01 00 00 00 42 58 50 43 // BXPCSLIT....BXPC + 0020: 01 00 00 00 02 00 00 00 00 00 00 00 0A 15 15 0A // ................ diff --git a/tests/data/acpi/virt/SPCR.dsl b/tests/data/acpi/virt/SPCR.dsl new file mode 100644 index 0000000000..3c271412cf --- /dev/null +++ b/tests/data/acpi/virt/SPCR.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SPCR.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SPCR] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] +[004h 0004 4] Table Length : 00000050 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 13 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSPCR" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 1] Interface Type : 03 +[025h 0037 3] Reserved : 000000 + +[028h 0040 12] Serial Port Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 08 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Ch 0044 8] Address : 0000000009000000 + +[034h 0052 1] Interrupt Type : 08 +[035h 0053 1] PCAT-compatible IRQ : 00 +[036h 0054 4] Interrupt : 00000021 +[03Ah 0058 1] Baud Rate : 03 +[03Bh 0059 1] Parity : 00 +[03Ch 0060 1] Stop Bits : 01 +[03Dh 0061 1] Flow Control : 02 +[03Eh 0062 1] Terminal Type : 00 +[04Ch 0076 1] Reserved : 00 +[040h 0064 2] PCI Device ID : FFFF +[042h 0066 2] PCI Vendor ID : FFFF +[044h 0068 1] PCI Bus : 00 +[045h 0069 1] PCI Device : 00 +[046h 0070 1] PCI Function : 00 +[047h 0071 4] PCI Flags : 00000000 +[04Bh 0075 1] PCI Segment : 00 +[04Ch 0076 4] Reserved : 00000000 + +Raw Table Data: Length 80 (0x50) + + 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC + 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... + 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SPCR.memhp.dsl b/tests/data/acpi/virt/SPCR.memhp.dsl new file mode 100644 index 0000000000..81e00457cc --- /dev/null +++ b/tests/data/acpi/virt/SPCR.memhp.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SPCR.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SPCR] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] +[004h 0004 4] Table Length : 00000050 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 13 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSPCR" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 1] Interface Type : 03 +[025h 0037 3] Reserved : 000000 + +[028h 0040 12] Serial Port Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 08 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Ch 0044 8] Address : 0000000009000000 + +[034h 0052 1] Interrupt Type : 08 +[035h 0053 1] PCAT-compatible IRQ : 00 +[036h 0054 4] Interrupt : 00000021 +[03Ah 0058 1] Baud Rate : 03 +[03Bh 0059 1] Parity : 00 +[03Ch 0060 1] Stop Bits : 01 +[03Dh 0061 1] Flow Control : 02 +[03Eh 0062 1] Terminal Type : 00 +[04Ch 0076 1] Reserved : 00 +[040h 0064 2] PCI Device ID : FFFF +[042h 0066 2] PCI Vendor ID : FFFF +[044h 0068 1] PCI Bus : 00 +[045h 0069 1] PCI Device : 00 +[046h 0070 1] PCI Function : 00 +[047h 0071 4] PCI Flags : 00000000 +[04Bh 0075 1] PCI Segment : 00 +[04Ch 0076 4] Reserved : 00000000 + +Raw Table Data: Length 80 (0x50) + + 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC + 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... + 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SPCR.numamem.dsl b/tests/data/acpi/virt/SPCR.numamem.dsl new file mode 100644 index 0000000000..faf6729797 --- /dev/null +++ b/tests/data/acpi/virt/SPCR.numamem.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SPCR.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SPCR] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SPCR" [Serial Port Console Redirection table] +[004h 0004 4] Table Length : 00000050 +[008h 0008 1] Revision : 02 +[009h 0009 1] Checksum : 13 +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSPCR" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 1] Interface Type : 03 +[025h 0037 3] Reserved : 000000 + +[028h 0040 12] Serial Port Register : [Generic Address Structure] +[028h 0040 1] Space ID : 00 [SystemMemory] +[029h 0041 1] Bit Width : 08 +[02Ah 0042 1] Bit Offset : 00 +[02Bh 0043 1] Encoded Access Width : 01 [Byte Access:8] +[02Ch 0044 8] Address : 0000000009000000 + +[034h 0052 1] Interrupt Type : 08 +[035h 0053 1] PCAT-compatible IRQ : 00 +[036h 0054 4] Interrupt : 00000021 +[03Ah 0058 1] Baud Rate : 03 +[03Bh 0059 1] Parity : 00 +[03Ch 0060 1] Stop Bits : 01 +[03Dh 0061 1] Flow Control : 02 +[03Eh 0062 1] Terminal Type : 00 +[04Ch 0076 1] Reserved : 00 +[040h 0064 2] PCI Device ID : FFFF +[042h 0066 2] PCI Vendor ID : FFFF +[044h 0068 1] PCI Bus : 00 +[045h 0069 1] PCI Device : 00 +[046h 0070 1] PCI Function : 00 +[047h 0071 4] PCI Flags : 00000000 +[04Bh 0075 1] PCI Segment : 00 +[04Ch 0076 4] Reserved : 00000000 + +Raw Table Data: Length 80 (0x50) + + 0000: 53 50 43 52 50 00 00 00 02 13 42 4F 43 48 53 20 // SPCRP.....BOCHS + 0010: 42 58 50 43 53 50 43 52 01 00 00 00 42 58 50 43 // BXPCSPCR....BXPC + 0020: 01 00 00 00 03 00 00 00 00 08 00 01 00 00 00 09 // ................ + 0030: 00 00 00 00 08 00 21 00 00 00 03 00 01 02 00 00 // ......!......... + 0040: FF FF FF FF 00 00 00 00 00 00 00 00 00 00 00 00 // ................ diff --git a/tests/data/acpi/virt/SRAT.dsl b/tests/data/acpi/virt/SRAT.dsl new file mode 100644 index 0000000000..f267aabc67 --- /dev/null +++ b/tests/data/acpi/virt/SRAT.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SRAT.numamem, Mon Sep 28 17:24:38 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 0000006A +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : AB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 03 [GICC Affinity] +[031h 0049 1] Length : 12 + +[032h 0050 4] Proximity Domain : 00000000 +[036h 0054 4] Acpi Processor UID : 00000000 +[03Ah 0058 4] Flags (decoded below) : 00000001 + Enabled : 1 +[03Eh 0062 4] Clock Domain : 00000000 + +[042h 0066 1] Subtable Type : 01 [Memory Affinity] +[043h 0067 1] Length : 28 + +[044h 0068 4] Proximity Domain : 00000000 +[048h 0072 2] Reserved1 : 0000 +[04Ah 0074 8] Base Address : 0000000040000000 +[052h 0082 8] Address Length : 0000000008000000 +[05Ah 0090 4] Reserved2 : 00000000 +[05Eh 0094 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[062h 0098 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 106 (0x6A) + + 0000: 53 52 41 54 6A 00 00 00 03 AB 42 4F 43 48 53 20 // SRATj.....BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@.. + 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 // .......... diff --git a/tests/data/acpi/virt/SRAT.memhp.dsl b/tests/data/acpi/virt/SRAT.memhp.dsl new file mode 100644 index 0000000000..3f311e6be0 --- /dev/null +++ b/tests/data/acpi/virt/SRAT.memhp.dsl @@ -0,0 +1,107 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SRAT.memhp, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 000000E2 +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : 5C +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 03 [GICC Affinity] +[031h 0049 1] Length : 12 + +[032h 0050 4] Proximity Domain : 00000000 +[036h 0054 4] Acpi Processor UID : 00000000 +[03Ah 0058 4] Flags (decoded below) : 00000001 + Enabled : 1 +[03Eh 0062 4] Clock Domain : 00000000 + +[042h 0066 1] Subtable Type : 01 [Memory Affinity] +[043h 0067 1] Length : 28 + +[044h 0068 4] Proximity Domain : 00000000 +[048h 0072 2] Reserved1 : 0000 +[04Ah 0074 8] Base Address : 0000000040000000 +[052h 0082 8] Address Length : 0000000008000000 +[05Ah 0090 4] Reserved2 : 00000000 +[05Eh 0094 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[062h 0098 8] Reserved3 : 0000000000000000 + +[06Ah 0106 1] Subtable Type : 01 [Memory Affinity] +[06Bh 0107 1] Length : 28 + +[06Ch 0108 4] Proximity Domain : 00000001 +[070h 0112 2] Reserved1 : 0000 +[072h 0114 8] Base Address : 0000000048000000 +[07Ah 0122 8] Address Length : 0000000008000000 +[082h 0130 4] Reserved2 : 00000000 +[086h 0134 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[08Ah 0138 8] Reserved3 : 0000000000000000 + +[092h 0146 1] Subtable Type : 01 [Memory Affinity] +[093h 0147 1] Length : 28 + +[094h 0148 4] Proximity Domain : 00000001 +[098h 0152 2] Reserved1 : 0000 +[09Ah 0154 8] Base Address : 0000000088000000 +[0A2h 0162 8] Address Length : 0000000008000000 +[0AAh 0170 4] Reserved2 : 00000000 +[0AEh 0174 4] Flags (decoded below) : 00000005 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 1 +[0B2h 0178 8] Reserved3 : 0000000000000000 + +[0BAh 0186 1] Subtable Type : 01 [Memory Affinity] +[0BBh 0187 1] Length : 28 + +[0BCh 0188 4] Proximity Domain : 00000001 +[0C0h 0192 2] Reserved1 : 0000 +[0C2h 0194 8] Base Address : 0000000080000000 +[0CAh 0202 8] Address Length : 00000000F0000000 +[0D2h 0210 4] Reserved2 : 00000000 +[0D6h 0214 4] Flags (decoded below) : 00000003 + Enabled : 1 + Hot Pluggable : 1 + Non-Volatile : 0 +[0DAh 0218 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 226 (0xE2) + + 0000: 53 52 41 54 E2 00 00 00 03 5C 42 4F 43 48 53 20 // SRAT.....\BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@.. + 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 01 28 01 00 00 00 // ...........(.... + 0070: 00 00 00 00 00 48 00 00 00 00 00 00 00 08 00 00 // .....H.......... + 0080: 00 00 00 00 00 00 01 00 00 00 00 00 00 00 00 00 // ................ + 0090: 00 00 01 28 01 00 00 00 00 00 00 00 00 88 00 00 // ...(............ + 00A0: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 05 00 // ................ + 00B0: 00 00 00 00 00 00 00 00 00 00 01 28 01 00 00 00 // ...........(.... + 00C0: 00 00 00 00 00 80 00 00 00 00 00 00 00 F0 00 00 // ................ + 00D0: 00 00 00 00 00 00 03 00 00 00 00 00 00 00 00 00 // ................ + 00E0: 00 00 // .. diff --git a/tests/data/acpi/virt/SRAT.numamem.dsl b/tests/data/acpi/virt/SRAT.numamem.dsl new file mode 100644 index 0000000000..b6e59b1af0 --- /dev/null +++ b/tests/data/acpi/virt/SRAT.numamem.dsl @@ -0,0 +1,57 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembly of tests/data/acpi/virt/SRAT.numamem, Tue Aug 4 11:14:15 2020 + * + * ACPI Data Table [SRAT] + * + * Format: [HexOffset DecimalOffset ByteLength] FieldName : FieldValue + */ + +[000h 0000 4] Signature : "SRAT" [System Resource Affinity Table] +[004h 0004 4] Table Length : 0000006A +[008h 0008 1] Revision : 03 +[009h 0009 1] Checksum : AB +[00Ah 0010 6] Oem ID : "BOCHS " +[010h 0016 8] Oem Table ID : "BXPCSRAT" +[018h 0024 4] Oem Revision : 00000001 +[01Ch 0028 4] Asl Compiler ID : "BXPC" +[020h 0032 4] Asl Compiler Revision : 00000001 + +[024h 0036 4] Table Revision : 00000001 +[028h 0040 8] Reserved : 0000000000000000 + +[030h 0048 1] Subtable Type : 03 [GICC Affinity] +[031h 0049 1] Length : 12 + +[032h 0050 4] Proximity Domain : 00000000 +[036h 0054 4] Acpi Processor UID : 00000000 +[03Ah 0058 4] Flags (decoded below) : 00000001 + Enabled : 1 +[03Eh 0062 4] Clock Domain : 00000000 + +[042h 0066 1] Subtable Type : 01 [Memory Affinity] +[043h 0067 1] Length : 28 + +[044h 0068 4] Proximity Domain : 00000000 +[048h 0072 2] Reserved1 : 0000 +[04Ah 0074 8] Base Address : 0000000040000000 +[052h 0082 8] Address Length : 0000000008000000 +[05Ah 0090 4] Reserved2 : 00000000 +[05Eh 0094 4] Flags (decoded below) : 00000001 + Enabled : 1 + Hot Pluggable : 0 + Non-Volatile : 0 +[062h 0098 8] Reserved3 : 0000000000000000 + +Raw Table Data: Length 106 (0x6A) + + 0000: 53 52 41 54 6A 00 00 00 03 AB 42 4F 43 48 53 20 // SRATj.....BOCHS + 0010: 42 58 50 43 53 52 41 54 01 00 00 00 42 58 50 43 // BXPCSRAT....BXPC + 0020: 01 00 00 00 01 00 00 00 00 00 00 00 00 00 00 00 // ................ + 0030: 03 12 00 00 00 00 00 00 00 00 01 00 00 00 00 00 // ................ + 0040: 00 00 01 28 00 00 00 00 00 00 00 00 00 40 00 00 // ...(.........@.. + 0050: 00 00 00 00 00 08 00 00 00 00 00 00 00 00 01 00 // ................ + 0060: 00 00 00 00 00 00 00 00 00 00 // .......... diff --git a/tests/data/acpi/virt/SSDT.dsl b/tests/data/acpi/virt/SSDT.dsl new file mode 100644 index 0000000000..cb220787b4 --- /dev/null +++ b/tests/data/acpi/virt/SSDT.dsl @@ -0,0 +1,205 @@ +/* + * Intel ACPI Component Architecture + * AML/ASL+ Disassembler version 20190509 (64-bit version) + * Copyright (c) 2000 - 2019 Intel Corporation + * + * Disassembling to symbolic ASL+ operators + * + * Disassembly of tests/data/acpi/virt/SSDT.memhp, Mon Sep 28 17:24:38 2020 + * + * Original Table Header: + * Signature "SSDT" + * Length 0x000002E0 (736) + * Revision 0x01 + * Checksum 0x3F + * OEM ID "BOCHS " + * OEM Table ID "NVDIMM" + * OEM Revision 0x00000001 (1) + * Compiler ID "BXPC" + * Compiler Version 0x00000001 (1) + */ +DefinitionBlock ("", "SSDT", 1, "BOCHS ", "NVDIMM", 0x00000001) +{ + Scope (\_SB) + { + Device (NVDR) + { + Name (_HID, "ACPI0012" /* NVDIMM Root Device */) // _HID: Hardware ID + Method (NCAL, 5, Serialized) + { + Local6 = MEMA /* \MEMA */ + OperationRegion (NPIO, SystemMemory, 0x09090000, 0x04) + OperationRegion (NRAM, SystemMemory, Local6, 0x1000) + Field (NPIO, DWordAcc, NoLock, Preserve) + { + NTFI, 32 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + HDLE, 32, + REVS, 32, + FUNC, 32, + FARG, 32672 + } + + Field (NRAM, DWordAcc, NoLock, Preserve) + { + RLEN, 32, + ODAT, 32736 + } + + If ((Arg4 == Zero)) + { + Local0 = ToUUID ("2f10e7a4-9e91-11e4-89d3-123b93f75cba") + } + ElseIf ((Arg4 == 0x00010000)) + { + Local0 = ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62") + } + Else + { + Local0 = ToUUID ("4309ac30-0d11-11e4-9191-0800200c9a66") + } + + If (((Local6 == Zero) | (Arg0 != Local0))) + { + If ((Arg2 == Zero)) + { + Return (Buffer (One) + { + 0x00 // . + }) + } + + Return (Buffer (One) + { + 0x01 // . + }) + } + + HDLE = Arg4 + REVS = Arg1 + FUNC = Arg2 + If (((ObjectType (Arg3) == 0x04) & (SizeOf (Arg3) == One))) + { + Local2 = Arg3 [Zero] + Local3 = DerefOf (Local2) + FARG = Local3 + } + + NTFI = Local6 + Local1 = (RLEN - 0x04) + If ((Local1 < 0x08)) + { + Local2 = Zero + Name (TBUF, Buffer (One) + { + 0x00 // . + }) + Local7 = Buffer (Zero){} + While ((Local2 < Local1)) + { + TBUF [Zero] = DerefOf (ODAT [Local2]) + Concatenate (Local7, TBUF, Local7) + Local2++ + } + + Return (Local7) + } + + Local1 = (Local1 << 0x03) + CreateField (ODAT, Zero, Local1, OBUF) + Return (OBUF) /* \_SB_.NVDR.NCAL.OBUF */ + } + + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, Zero)) + } + + Name (RSTA, Zero) + Method (RFIT, 1, Serialized) + { + Name (OFST, Zero) + OFST = Arg0 + Local0 = NCAL (ToUUID ("648b9cf2-cda1-4312-8ad9-49c4af32bd62"), One, One, Package (0x01) + { + OFST + }, 0x00010000) + CreateDWordField (Local0, Zero, STAU) + RSTA = STAU /* \_SB_.NVDR.RFIT.STAU */ + If ((Zero != STAU)) + { + Return (Buffer (Zero){}) + } + + Local1 = SizeOf (Local0) + Local1 -= 0x04 + If ((Local1 == Zero)) + { + Return (Buffer (Zero){}) + } + + CreateField (Local0, 0x20, (Local1 << 0x03), BUFF) + Return (BUFF) /* \_SB_.NVDR.RFIT.BUFF */ + } + + Method (_FIT, 0, Serialized) // _FIT: Firmware Interface Table + { + Local2 = Buffer (Zero){} + Local3 = Zero + While (One) + { + Local0 = RFIT (Local3) + Local1 = SizeOf (Local0) + If ((RSTA == 0x0100)) + { + Local2 = Buffer (Zero){} + Local3 = Zero + } + Else + { + If ((Local1 == Zero)) + { + Return (Local2) + } + + Local3 += Local1 + Concatenate (Local2, Local0, Local2) + } + } + } + + Device (NV00) + { + Name (_ADR, One) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, One)) + } + } + + Device (NV01) + { + Name (_ADR, 0x02) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x02)) + } + } + + Device (NV02) + { + Name (_ADR, 0x03) // _ADR: Address + Method (_DSM, 4, NotSerialized) // _DSM: Device-Specific Method + { + Return (NCAL (Arg0, Arg1, Arg2, Arg3, 0x03)) + } + } + } + } + + Name (MEMA, 0x43D10000) +} + diff --git a/tests/data/uefi-boot-images/bios-tables-test.x86_64.iso.raw b/tests/data/uefi-boot-images/bios-tables-test.x86_64.iso.raw new file mode 100644 index 0000000000..bd43ba50a3 --- /dev/null +++ b/tests/data/uefi-boot-images/bios-tables-test.x86_64.iso.raw Binary files differdiff --git a/tests/libqtest.c.orig b/tests/libqtest.c.orig new file mode 100644 index 0000000000..a1d33a1d0c --- /dev/null +++ b/tests/libqtest.c.orig @@ -0,0 +1,1106 @@ +/* + * QTest + * + * Copyright IBM, Corp. 2012 + * Copyright Red Hat, Inc. 2012 + * Copyright SUSE LINUX Products GmbH 2013 + * + * Authors: + * Anthony Liguori <aliguori@us.ibm.com> + * Paolo Bonzini <pbonzini@redhat.com> + * Andreas Färber <afaerber@suse.de> + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#include "qemu/osdep.h" + +#include <sys/socket.h> +#include <sys/wait.h> +#include <sys/un.h> + +#include "libqtest.h" +#include "qemu/cutils.h" +#include "qapi/error.h" +#include "qapi/qmp/json-parser.h" +#include "qapi/qmp/json-streamer.h" +#include "qapi/qmp/qdict.h" +#include "qapi/qmp/qjson.h" +#include "qapi/qmp/qlist.h" +#include "qapi/qmp/qstring.h" + +#define MAX_IRQ 256 +#define SOCKET_TIMEOUT 50 + +QTestState *global_qtest; + +struct QTestState +{ + int fd; + int qmp_fd; + bool irq_level[MAX_IRQ]; + GString *rx; + pid_t qemu_pid; /* our child QEMU process */ + bool big_endian; +}; + +static GHookList abrt_hooks; +static struct sigaction sigact_old; + +#define g_assert_no_errno(ret) do { \ + g_assert_cmpint(ret, !=, -1); \ +} while (0) + +static int qtest_query_target_endianness(QTestState *s); + +static int init_socket(const char *socket_path) +{ + struct sockaddr_un addr; + int sock; + int ret; + + sock = socket(PF_UNIX, SOCK_STREAM, 0); + g_assert_no_errno(sock); + + addr.sun_family = AF_UNIX; + snprintf(addr.sun_path, sizeof(addr.sun_path), "%s", socket_path); + qemu_set_cloexec(sock); + + do { + ret = bind(sock, (struct sockaddr *)&addr, sizeof(addr)); + } while (ret == -1 && errno == EINTR); + g_assert_no_errno(ret); + ret = listen(sock, 1); + g_assert_no_errno(ret); + + return sock; +} + +static int socket_accept(int sock) +{ + struct sockaddr_un addr; + socklen_t addrlen; + int ret; + struct timeval timeout = { .tv_sec = SOCKET_TIMEOUT, + .tv_usec = 0 }; + + setsockopt(sock, SOL_SOCKET, SO_RCVTIMEO, (void *)&timeout, + sizeof(timeout)); + + do { + addrlen = sizeof(addr); + ret = accept(sock, (struct sockaddr *)&addr, &addrlen); + } while (ret == -1 && errno == EINTR); + if (ret == -1) { + fprintf(stderr, "%s failed: %s\n", __func__, strerror(errno)); + } + close(sock); + + return ret; +} + +static void kill_qemu(QTestState *s) +{ + int wstatus = 0; + + if (s->qemu_pid != -1) { + kill(s->qemu_pid, SIGTERM); + waitpid(s->qemu_pid, &wstatus, 0); + + if (WIFSIGNALED(wstatus)) { + assert(!WCOREDUMP(wstatus)); + } + } +} + +static void kill_qemu_hook_func(void *s) +{ + kill_qemu(s); +} + +static void sigabrt_handler(int signo) +{ + g_hook_list_invoke(&abrt_hooks, FALSE); +} + +static void setup_sigabrt_handler(void) +{ + struct sigaction sigact; + + /* Catch SIGABRT to clean up on g_assert() failure */ + sigact = (struct sigaction){ + .sa_handler = sigabrt_handler, + .sa_flags = SA_RESETHAND, + }; + sigemptyset(&sigact.sa_mask); + sigaction(SIGABRT, &sigact, &sigact_old); +} + +static void cleanup_sigabrt_handler(void) +{ + sigaction(SIGABRT, &sigact_old, NULL); +} + +void qtest_add_abrt_handler(GHookFunc fn, const void *data) +{ + GHook *hook; + + /* Only install SIGABRT handler once */ + if (!abrt_hooks.is_setup) { + g_hook_list_init(&abrt_hooks, sizeof(GHook)); + } + setup_sigabrt_handler(); + + hook = g_hook_alloc(&abrt_hooks); + hook->func = fn; + hook->data = (void *)data; + + g_hook_prepend(&abrt_hooks, hook); +} + +static const char *qtest_qemu_binary(void) +{ + const char *qemu_bin; + + qemu_bin = getenv("QTEST_QEMU_BINARY"); + if (!qemu_bin) { + fprintf(stderr, "Environment variable QTEST_QEMU_BINARY required\n"); + exit(1); + } + + return qemu_bin; +} + +QTestState *qtest_init_without_qmp_handshake(bool use_oob, + const char *extra_args) +{ + QTestState *s; + int sock, qmpsock, i; + gchar *socket_path; + gchar *qmp_socket_path; + gchar *command; + const char *qemu_binary = qtest_qemu_binary(); + + s = g_new(QTestState, 1); + + socket_path = g_strdup_printf("/tmp/qtest-%d.sock", getpid()); + qmp_socket_path = g_strdup_printf("/tmp/qtest-%d.qmp", getpid()); + + /* It's possible that if an earlier test run crashed it might + * have left a stale unix socket lying around. Delete any + * stale old socket to avoid spurious test failures with + * tests/libqtest.c:70:init_socket: assertion failed (ret != -1): (-1 != -1) + */ + unlink(socket_path); + unlink(qmp_socket_path); + + sock = init_socket(socket_path); + qmpsock = init_socket(qmp_socket_path); + + qtest_add_abrt_handler(kill_qemu_hook_func, s); + + s->qemu_pid = fork(); + if (s->qemu_pid == 0) { + setenv("QEMU_AUDIO_DRV", "none", true); + command = g_strdup_printf("exec %s " + "-qtest unix:%s,nowait " + "-qtest-log %s " + "-chardev socket,path=%s,nowait,id=char0 " + "-mon chardev=char0,mode=control%s " + "-machine accel=qtest " + "-display none " + "%s", qemu_binary, socket_path, + getenv("QTEST_LOG") ? "/dev/fd/2" : "/dev/null", + qmp_socket_path, use_oob ? ",x-oob=on" : "", + extra_args ?: ""); + execlp("/bin/sh", "sh", "-c", command, NULL); + exit(1); + } + + s->fd = socket_accept(sock); + if (s->fd >= 0) { + s->qmp_fd = socket_accept(qmpsock); + } + unlink(socket_path); + unlink(qmp_socket_path); + g_free(socket_path); + g_free(qmp_socket_path); + + g_assert(s->fd >= 0 && s->qmp_fd >= 0); + + s->rx = g_string_new(""); + for (i = 0; i < MAX_IRQ; i++) { + s->irq_level[i] = false; + } + + if (getenv("QTEST_STOP")) { + kill(s->qemu_pid, SIGSTOP); + } + + /* ask endianness of the target */ + + s->big_endian = qtest_query_target_endianness(s); + + return s; +} + +QTestState *qtest_init(const char *extra_args) +{ + QTestState *s = qtest_init_without_qmp_handshake(false, extra_args); + + /* Read the QMP greeting and then do the handshake */ + qtest_qmp_discard_response(s, ""); + qtest_qmp_discard_response(s, "{ 'execute': 'qmp_capabilities' }"); + + return s; +} + +QTestState *qtest_vstartf(const char *fmt, va_list ap) +{ + char *args = g_strdup_vprintf(fmt, ap); + QTestState *s; + + s = qtest_start(args); + g_free(args); + global_qtest = NULL; + return s; +} + +QTestState *qtest_startf(const char *fmt, ...) +{ + va_list ap; + QTestState *s; + + va_start(ap, fmt); + s = qtest_vstartf(fmt, ap); + va_end(ap); + return s; +} + +void qtest_quit(QTestState *s) +{ + g_hook_destroy_link(&abrt_hooks, g_hook_find_data(&abrt_hooks, TRUE, s)); + + /* Uninstall SIGABRT handler on last instance */ + cleanup_sigabrt_handler(); + + kill_qemu(s); + close(s->fd); + close(s->qmp_fd); + g_string_free(s->rx, true); + g_free(s); +} + +static void socket_send(int fd, const char *buf, size_t size) +{ + size_t offset; + + offset = 0; + while (offset < size) { + ssize_t len; + + len = write(fd, buf + offset, size - offset); + if (len == -1 && errno == EINTR) { + continue; + } + + g_assert_no_errno(len); + g_assert_cmpint(len, >, 0); + + offset += len; + } +} + +static void socket_sendf(int fd, const char *fmt, va_list ap) +{ + gchar *str = g_strdup_vprintf(fmt, ap); + size_t size = strlen(str); + + socket_send(fd, str, size); + g_free(str); +} + +static void GCC_FMT_ATTR(2, 3) qtest_sendf(QTestState *s, const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + socket_sendf(s->fd, fmt, ap); + va_end(ap); +} + +static GString *qtest_recv_line(QTestState *s) +{ + GString *line; + size_t offset; + char *eol; + + while ((eol = strchr(s->rx->str, '\n')) == NULL) { + ssize_t len; + char buffer[1024]; + + len = read(s->fd, buffer, sizeof(buffer)); + if (len == -1 && errno == EINTR) { + continue; + } + + if (len == -1 || len == 0) { + fprintf(stderr, "Broken pipe\n"); + exit(1); + } + + g_string_append_len(s->rx, buffer, len); + } + + offset = eol - s->rx->str; + line = g_string_new_len(s->rx->str, offset); + g_string_erase(s->rx, 0, offset + 1); + + return line; +} + +static gchar **qtest_rsp(QTestState *s, int expected_args) +{ + GString *line; + gchar **words; + int i; + +redo: + line = qtest_recv_line(s); + words = g_strsplit(line->str, " ", 0); + g_string_free(line, TRUE); + + if (strcmp(words[0], "IRQ") == 0) { + long irq; + int ret; + + g_assert(words[1] != NULL); + g_assert(words[2] != NULL); + + ret = qemu_strtol(words[2], NULL, 0, &irq); + g_assert(!ret); + g_assert_cmpint(irq, >=, 0); + g_assert_cmpint(irq, <, MAX_IRQ); + + if (strcmp(words[1], "raise") == 0) { + s->irq_level[irq] = true; + } else { + s->irq_level[irq] = false; + } + + g_strfreev(words); + goto redo; + } + + g_assert(words[0] != NULL); + g_assert_cmpstr(words[0], ==, "OK"); + + if (expected_args) { + for (i = 0; i < expected_args; i++) { + g_assert(words[i] != NULL); + } + } else { + g_strfreev(words); + } + + return words; +} + +static int qtest_query_target_endianness(QTestState *s) +{ + gchar **args; + int big_endian; + + qtest_sendf(s, "endianness\n"); + args = qtest_rsp(s, 1); + g_assert(strcmp(args[1], "big") == 0 || strcmp(args[1], "little") == 0); + big_endian = strcmp(args[1], "big") == 0; + g_strfreev(args); + + return big_endian; +} + +typedef struct { + JSONMessageParser parser; + QDict *response; +} QMPResponseParser; + +static void qmp_response(JSONMessageParser *parser, GQueue *tokens) +{ + QMPResponseParser *qmp = container_of(parser, QMPResponseParser, parser); + QObject *obj; + + obj = json_parser_parse(tokens, NULL); + if (!obj) { + fprintf(stderr, "QMP JSON response parsing failed\n"); + exit(1); + } + + g_assert(!qmp->response); + qmp->response = qobject_to(QDict, obj); + g_assert(qmp->response); +} + +QDict *qmp_fd_receive(int fd) +{ + QMPResponseParser qmp; + bool log = getenv("QTEST_LOG") != NULL; + + qmp.response = NULL; + json_message_parser_init(&qmp.parser, qmp_response); + while (!qmp.response) { + ssize_t len; + char c; + + len = read(fd, &c, 1); + if (len == -1 && errno == EINTR) { + continue; + } + + if (len == -1 || len == 0) { + fprintf(stderr, "Broken pipe\n"); + exit(1); + } + + if (log) { + len = write(2, &c, 1); + } + json_message_parser_feed(&qmp.parser, &c, 1); + } + json_message_parser_destroy(&qmp.parser); + + return qmp.response; +} + +QDict *qtest_qmp_receive(QTestState *s) +{ + return qmp_fd_receive(s->qmp_fd); +} + +/** + * Allow users to send a message without waiting for the reply, + * in the case that they choose to discard all replies up until + * a particular EVENT is received. + */ +void qmp_fd_sendv(int fd, const char *fmt, va_list ap) +{ + va_list ap_copy; + QObject *qobj; + + /* qobject_from_jsonv() silently eats leading 0xff as invalid + * JSON, but we want to test sending them over the wire to force + * resyncs */ + if (*fmt == '\377') { + socket_send(fd, fmt, 1); + fmt++; + } + + /* Going through qobject ensures we escape strings properly. + * This seemingly unnecessary copy is required in case va_list + * is an array type. + */ + va_copy(ap_copy, ap); + qobj = qobject_from_jsonv(fmt, &ap_copy, &error_abort); + va_end(ap_copy); + + /* No need to send anything for an empty QObject. */ + if (qobj) { + int log = getenv("QTEST_LOG") != NULL; + QString *qstr = qobject_to_json(qobj); + const char *str; + + /* + * BUG: QMP doesn't react to input until it sees a newline, an + * object, or an array. Work-around: give it a newline. + */ + qstring_append_chr(qstr, '\n'); + str = qstring_get_str(qstr); + + if (log) { + fprintf(stderr, "%s", str); + } + /* Send QMP request */ + socket_send(fd, str, qstring_get_length(qstr)); + + qobject_unref(qstr); + qobject_unref(qobj); + } +} + +void qtest_async_qmpv(QTestState *s, const char *fmt, va_list ap) +{ + qmp_fd_sendv(s->qmp_fd, fmt, ap); +} + +QDict *qmp_fdv(int fd, const char *fmt, va_list ap) +{ + qmp_fd_sendv(fd, fmt, ap); + + return qmp_fd_receive(fd); +} + +QDict *qtest_qmpv(QTestState *s, const char *fmt, va_list ap) +{ + qtest_async_qmpv(s, fmt, ap); + + /* Receive reply */ + return qtest_qmp_receive(s); +} + +QDict *qmp_fd(int fd, const char *fmt, ...) +{ + va_list ap; + QDict *response; + + va_start(ap, fmt); + response = qmp_fdv(fd, fmt, ap); + va_end(ap); + return response; +} + +void qmp_fd_send(int fd, const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + qmp_fd_sendv(fd, fmt, ap); + va_end(ap); +} + +QDict *qtest_qmp(QTestState *s, const char *fmt, ...) +{ + va_list ap; + QDict *response; + + va_start(ap, fmt); + response = qtest_qmpv(s, fmt, ap); + va_end(ap); + return response; +} + +void qtest_async_qmp(QTestState *s, const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + qtest_async_qmpv(s, fmt, ap); + va_end(ap); +} + +void qtest_qmpv_discard_response(QTestState *s, const char *fmt, va_list ap) +{ + QDict *response = qtest_qmpv(s, fmt, ap); + qobject_unref(response); +} + +void qtest_qmp_discard_response(QTestState *s, const char *fmt, ...) +{ + va_list ap; + QDict *response; + + va_start(ap, fmt); + response = qtest_qmpv(s, fmt, ap); + va_end(ap); + qobject_unref(response); +} + +QDict *qtest_qmp_eventwait_ref(QTestState *s, const char *event) +{ + QDict *response; + + for (;;) { + response = qtest_qmp_receive(s); + if ((qdict_haskey(response, "event")) && + (strcmp(qdict_get_str(response, "event"), event) == 0)) { + return response; + } + qobject_unref(response); + } +} + +void qtest_qmp_eventwait(QTestState *s, const char *event) +{ + QDict *response; + + response = qtest_qmp_eventwait_ref(s, event); + qobject_unref(response); +} + +char *qtest_hmpv(QTestState *s, const char *fmt, va_list ap) +{ + char *cmd; + QDict *resp; + char *ret; + + cmd = g_strdup_vprintf(fmt, ap); + resp = qtest_qmp(s, "{'execute': 'human-monitor-command'," + " 'arguments': {'command-line': %s}}", + cmd); + ret = g_strdup(qdict_get_try_str(resp, "return")); + while (ret == NULL && qdict_get_try_str(resp, "event")) { + /* Ignore asynchronous QMP events */ + qobject_unref(resp); + resp = qtest_qmp_receive(s); + ret = g_strdup(qdict_get_try_str(resp, "return")); + } + g_assert(ret); + qobject_unref(resp); + g_free(cmd); + return ret; +} + +char *qtest_hmp(QTestState *s, const char *fmt, ...) +{ + va_list ap; + char *ret; + + va_start(ap, fmt); + ret = qtest_hmpv(s, fmt, ap); + va_end(ap); + return ret; +} + +const char *qtest_get_arch(void) +{ + const char *qemu = qtest_qemu_binary(); + const char *end = strrchr(qemu, '/'); + + return end + strlen("/qemu-system-"); +} + +bool qtest_get_irq(QTestState *s, int num) +{ + /* dummy operation in order to make sure irq is up to date */ + qtest_inb(s, 0); + + return s->irq_level[num]; +} + +static int64_t qtest_clock_rsp(QTestState *s) +{ + gchar **words; + int64_t clock; + words = qtest_rsp(s, 2); + clock = g_ascii_strtoll(words[1], NULL, 0); + g_strfreev(words); + return clock; +} + +int64_t qtest_clock_step_next(QTestState *s) +{ + qtest_sendf(s, "clock_step\n"); + return qtest_clock_rsp(s); +} + +int64_t qtest_clock_step(QTestState *s, int64_t step) +{ + qtest_sendf(s, "clock_step %"PRIi64"\n", step); + return qtest_clock_rsp(s); +} + +int64_t qtest_clock_set(QTestState *s, int64_t val) +{ + qtest_sendf(s, "clock_set %"PRIi64"\n", val); + return qtest_clock_rsp(s); +} + +void qtest_irq_intercept_out(QTestState *s, const char *qom_path) +{ + qtest_sendf(s, "irq_intercept_out %s\n", qom_path); + qtest_rsp(s, 0); +} + +void qtest_irq_intercept_in(QTestState *s, const char *qom_path) +{ + qtest_sendf(s, "irq_intercept_in %s\n", qom_path); + qtest_rsp(s, 0); +} + +static void qtest_out(QTestState *s, const char *cmd, uint16_t addr, uint32_t value) +{ + qtest_sendf(s, "%s 0x%x 0x%x\n", cmd, addr, value); + qtest_rsp(s, 0); +} + +void qtest_outb(QTestState *s, uint16_t addr, uint8_t value) +{ + qtest_out(s, "outb", addr, value); +} + +void qtest_outw(QTestState *s, uint16_t addr, uint16_t value) +{ + qtest_out(s, "outw", addr, value); +} + +void qtest_outl(QTestState *s, uint16_t addr, uint32_t value) +{ + qtest_out(s, "outl", addr, value); +} + +static uint32_t qtest_in(QTestState *s, const char *cmd, uint16_t addr) +{ + gchar **args; + int ret; + unsigned long value; + + qtest_sendf(s, "%s 0x%x\n", cmd, addr); + args = qtest_rsp(s, 2); + ret = qemu_strtoul(args[1], NULL, 0, &value); + g_assert(!ret && value <= UINT32_MAX); + g_strfreev(args); + + return value; +} + +uint8_t qtest_inb(QTestState *s, uint16_t addr) +{ + return qtest_in(s, "inb", addr); +} + +uint16_t qtest_inw(QTestState *s, uint16_t addr) +{ + return qtest_in(s, "inw", addr); +} + +uint32_t qtest_inl(QTestState *s, uint16_t addr) +{ + return qtest_in(s, "inl", addr); +} + +static void qtest_write(QTestState *s, const char *cmd, uint64_t addr, + uint64_t value) +{ + qtest_sendf(s, "%s 0x%" PRIx64 " 0x%" PRIx64 "\n", cmd, addr, value); + qtest_rsp(s, 0); +} + +void qtest_writeb(QTestState *s, uint64_t addr, uint8_t value) +{ + qtest_write(s, "writeb", addr, value); +} + +void qtest_writew(QTestState *s, uint64_t addr, uint16_t value) +{ + qtest_write(s, "writew", addr, value); +} + +void qtest_writel(QTestState *s, uint64_t addr, uint32_t value) +{ + qtest_write(s, "writel", addr, value); +} + +void qtest_writeq(QTestState *s, uint64_t addr, uint64_t value) +{ + qtest_write(s, "writeq", addr, value); +} + +static uint64_t qtest_read(QTestState *s, const char *cmd, uint64_t addr) +{ + gchar **args; + int ret; + uint64_t value; + + qtest_sendf(s, "%s 0x%" PRIx64 "\n", cmd, addr); + args = qtest_rsp(s, 2); + ret = qemu_strtou64(args[1], NULL, 0, &value); + g_assert(!ret); + g_strfreev(args); + + return value; +} + +uint8_t qtest_readb(QTestState *s, uint64_t addr) +{ + return qtest_read(s, "readb", addr); +} + +uint16_t qtest_readw(QTestState *s, uint64_t addr) +{ + return qtest_read(s, "readw", addr); +} + +uint32_t qtest_readl(QTestState *s, uint64_t addr) +{ + return qtest_read(s, "readl", addr); +} + +uint64_t qtest_readq(QTestState *s, uint64_t addr) +{ + return qtest_read(s, "readq", addr); +} + +static int hex2nib(char ch) +{ + if (ch >= '0' && ch <= '9') { + return ch - '0'; + } else if (ch >= 'a' && ch <= 'f') { + return 10 + (ch - 'a'); + } else if (ch >= 'A' && ch <= 'F') { + return 10 + (ch - 'a'); + } else { + return -1; + } +} + +void qtest_memread(QTestState *s, uint64_t addr, void *data, size_t size) +{ + uint8_t *ptr = data; + gchar **args; + size_t i; + + if (!size) { + return; + } + + qtest_sendf(s, "read 0x%" PRIx64 " 0x%zx\n", addr, size); + args = qtest_rsp(s, 2); + + for (i = 0; i < size; i++) { + ptr[i] = hex2nib(args[1][2 + (i * 2)]) << 4; + ptr[i] |= hex2nib(args[1][2 + (i * 2) + 1]); + } + + g_strfreev(args); +} + +uint64_t qtest_rtas_call(QTestState *s, const char *name, + uint32_t nargs, uint64_t args, + uint32_t nret, uint64_t ret) +{ + qtest_sendf(s, "rtas %s %u 0x%"PRIx64" %u 0x%"PRIx64"\n", + name, nargs, args, nret, ret); + qtest_rsp(s, 0); + return 0; +} + +void qtest_add_func(const char *str, void (*fn)(void)) +{ + gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str); + g_test_add_func(path, fn); + g_free(path); +} + +void qtest_add_data_func_full(const char *str, void *data, + void (*fn)(const void *), + GDestroyNotify data_free_func) +{ + gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str); + g_test_add_data_func_full(path, data, fn, data_free_func); + g_free(path); +} + +void qtest_add_data_func(const char *str, const void *data, + void (*fn)(const void *)) +{ + gchar *path = g_strdup_printf("/%s/%s", qtest_get_arch(), str); + g_test_add_data_func(path, data, fn); + g_free(path); +} + +void qtest_bufwrite(QTestState *s, uint64_t addr, const void *data, size_t size) +{ + gchar *bdata; + + bdata = g_base64_encode(data, size); + qtest_sendf(s, "b64write 0x%" PRIx64 " 0x%zx ", addr, size); + socket_send(s->fd, bdata, strlen(bdata)); + socket_send(s->fd, "\n", 1); + qtest_rsp(s, 0); + g_free(bdata); +} + +void qtest_bufread(QTestState *s, uint64_t addr, void *data, size_t size) +{ + gchar **args; + size_t len; + + qtest_sendf(s, "b64read 0x%" PRIx64 " 0x%zx\n", addr, size); + args = qtest_rsp(s, 2); + + g_base64_decode_inplace(args[1], &len); + if (size != len) { + fprintf(stderr, "bufread: asked for %zu bytes but decoded %zu\n", + size, len); + len = MIN(len, size); + } + + memcpy(data, args[1], len); + g_strfreev(args); +} + +void qtest_memwrite(QTestState *s, uint64_t addr, const void *data, size_t size) +{ + const uint8_t *ptr = data; + size_t i; + char *enc; + + if (!size) { + return; + } + + enc = g_malloc(2 * size + 1); + + for (i = 0; i < size; i++) { + sprintf(&enc[i * 2], "%02x", ptr[i]); + } + + qtest_sendf(s, "write 0x%" PRIx64 " 0x%zx 0x%s\n", addr, size, enc); + qtest_rsp(s, 0); + g_free(enc); +} + +void qtest_memset(QTestState *s, uint64_t addr, uint8_t pattern, size_t size) +{ + qtest_sendf(s, "memset 0x%" PRIx64 " 0x%zx 0x%02x\n", addr, size, pattern); + qtest_rsp(s, 0); +} + +QDict *qmp(const char *fmt, ...) +{ + va_list ap; + QDict *response; + + va_start(ap, fmt); + response = qtest_qmpv(global_qtest, fmt, ap); + va_end(ap); + return response; +} + +void qmp_async(const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + qtest_async_qmpv(global_qtest, fmt, ap); + va_end(ap); +} + +void qmp_discard_response(const char *fmt, ...) +{ + va_list ap; + + va_start(ap, fmt); + qtest_qmpv_discard_response(global_qtest, fmt, ap); + va_end(ap); +} +char *hmp(const char *fmt, ...) +{ + va_list ap; + char *ret; + + va_start(ap, fmt); + ret = qtest_hmpv(global_qtest, fmt, ap); + va_end(ap); + return ret; +} + +bool qtest_big_endian(QTestState *s) +{ + return s->big_endian; +} + +void qtest_cb_for_every_machine(void (*cb)(const char *machine)) +{ + QDict *response, *minfo; + QList *list; + const QListEntry *p; + QObject *qobj; + QString *qstr; + const char *mname; + + qtest_start("-machine none"); + response = qmp("{ 'execute': 'query-machines' }"); + g_assert(response); + list = qdict_get_qlist(response, "return"); + g_assert(list); + + for (p = qlist_first(list); p; p = qlist_next(p)) { + minfo = qobject_to(QDict, qlist_entry_obj(p)); + g_assert(minfo); + qobj = qdict_get(minfo, "name"); + g_assert(qobj); + qstr = qobject_to(QString, qobj); + g_assert(qstr); + mname = qstring_get_str(qstr); + cb(mname); + } + + qtest_end(); + qobject_unref(response); +} + +/* + * Generic hot-plugging test via the device_add QMP command. + */ +void qtest_qmp_device_add(const char *driver, const char *id, const char *fmt, + ...) +{ + QDict *response; + char *cmd, *opts = NULL; + va_list va; + + if (fmt) { + va_start(va, fmt); + opts = g_strdup_vprintf(fmt, va); + va_end(va); + } + + cmd = g_strdup_printf("{'execute': 'device_add'," + " 'arguments': { 'driver': '%s', 'id': '%s'%s%s }}", + driver, id, opts ? ", " : "", opts ? opts : ""); + g_free(opts); + + response = qmp(cmd); + g_free(cmd); + g_assert(response); + g_assert(!qdict_haskey(response, "event")); /* We don't expect any events */ + g_assert(!qdict_haskey(response, "error")); + qobject_unref(response); +} + +/* + * Generic hot-unplugging test via the device_del QMP command. + * Device deletion will get one response and one event. For example: + * + * {'execute': 'device_del','arguments': { 'id': 'scsi-hd'}} + * + * will get this one: + * + * {"timestamp": {"seconds": 1505289667, "microseconds": 569862}, + * "event": "DEVICE_DELETED", "data": {"device": "scsi-hd", + * "path": "/machine/peripheral/scsi-hd"}} + * + * and this one: + * + * {"return": {}} + * + * But the order of arrival may vary - so we've got to detect both. + */ +void qtest_qmp_device_del(const char *id) +{ + QDict *response1, *response2, *event = NULL; + char *cmd; + + cmd = g_strdup_printf("{'execute': 'device_del'," + " 'arguments': { 'id': '%s' }}", id); + response1 = qmp(cmd); + g_free(cmd); + g_assert(response1); + g_assert(!qdict_haskey(response1, "error")); + + response2 = qmp(""); + g_assert(response2); + g_assert(!qdict_haskey(response2, "error")); + + if (qdict_haskey(response1, "event")) { + event = response1; + } else if (qdict_haskey(response2, "event")) { + event = response2; + } + g_assert(event); + g_assert_cmpstr(qdict_get_str(event, "event"), ==, "DEVICE_DELETED"); + + qobject_unref(response1); + qobject_unref(response2); +} diff --git a/tests/qemu-iotests/core.12067 b/tests/qemu-iotests/core.12067 new file mode 100644 index 0000000000..0ddb68f76a --- /dev/null +++ b/tests/qemu-iotests/core.12067 Binary files differdiff --git a/tests/qtest/bios-tables-test-allowed-diff.h.orig b/tests/qtest/bios-tables-test-allowed-diff.h.orig new file mode 100644 index 0000000000..6a052c5044 --- /dev/null +++ b/tests/qtest/bios-tables-test-allowed-diff.h.orig @@ -0,0 +1,18 @@ +/* List of comma-separated changed AML files to ignore */ +"tests/data/acpi/pc/DSDT", +"tests/data/acpi/pc/DSDT.acpihmat", +"tests/data/acpi/pc/DSDT.bridge", +"tests/data/acpi/pc/DSDT.cphp", +"tests/data/acpi/pc/DSDT.dimmpxm", +"tests/data/acpi/pc/DSDT.ipmikcs", +"tests/data/acpi/pc/DSDT.memhp", +"tests/data/acpi/pc/DSDT.numamem", +"tests/data/acpi/q35/DSDT", +"tests/data/acpi/q35/DSDT.acpihmat", +"tests/data/acpi/q35/DSDT.bridge", +"tests/data/acpi/q35/DSDT.cphp", +"tests/data/acpi/q35/DSDT.dimmpxm", +"tests/data/acpi/q35/DSDT.ipmibt", +"tests/data/acpi/q35/DSDT.memhp", +"tests/data/acpi/q35/DSDT.mmio64", +"tests/data/acpi/q35/DSDT.numamem", diff --git a/tests/qtest/bios-tables-test-allowed-diff.h.rej b/tests/qtest/bios-tables-test-allowed-diff.h.rej new file mode 100644 index 0000000000..31b3352111 --- /dev/null +++ b/tests/qtest/bios-tables-test-allowed-diff.h.rej @@ -0,0 +1,9 @@ +--- tests/qtest/bios-tables-test-allowed-diff.h ++++ tests/qtest/bios-tables-test-allowed-diff.h +@@ -1,6 +1 @@ + /* List of comma-separated changed AML files to ignore */ +-"tests/data/acpi/pc/SSDT.dimmpxm", +-"tests/data/acpi/q35/SSDT.dimmpxm", +-"tests/data/acpi/virt/DSDT.memhp", +-"tests/data/acpi/virt/SSDT.memhp", +-"tests/data/acpi/virt/NFIT.memhp", diff --git a/tests/qtest/bios-tables-test.c b/tests/qtest/bios-tables-test.c index a9c8d478ae..3c09b844f9 100644 --- a/tests/qtest/bios-tables-test.c +++ b/tests/qtest/bios-tables-test.c @@ -742,6 +742,34 @@ static void test_acpi_piix4_tcg_bridge(void) free_test_data(&data); } +static void test_acpi_piix4_no_root_hotplug(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".roothp"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-global PIIX4_PM.acpi-root-pci-hotplug=off " + "-device pci-bridge,chassis_nr=1", &data); + free_test_data(&data); +} + +static void test_acpi_piix4_no_bridge_hotplug(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".hpbridge"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-global PIIX4_PM.acpi-pci-hotplug-with-bridge-support=off " + "-device pci-bridge,chassis_nr=1", &data); + free_test_data(&data); +} + static void test_acpi_q35_tcg(void) { test_data data; @@ -1160,6 +1188,10 @@ int main(int argc, char *argv[]) qtest_add_func("acpi/q35/tpm-tis", test_acpi_q35_tcg_tpm_tis); qtest_add_func("acpi/piix4", test_acpi_piix4_tcg); qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge); + qtest_add_func("acpi/piix4/pci-hotplug/no_root_hotplug", + test_acpi_piix4_no_root_hotplug); + qtest_add_func("acpi/piix4/pci-hotplug/no_bridge_hotplug", + test_acpi_piix4_no_bridge_hotplug); qtest_add_func("acpi/q35", test_acpi_q35_tcg); qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge); qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64); diff --git a/tests/qtest/bios-tables-test.c.orig b/tests/qtest/bios-tables-test.c.orig new file mode 100644 index 0000000000..a0b8d81659 --- /dev/null +++ b/tests/qtest/bios-tables-test.c.orig @@ -0,0 +1,1200 @@ +/* + * Boot order test cases. + * + * Copyright (c) 2013 Red Hat Inc. + * + * Authors: + * Michael S. Tsirkin <mst@redhat.com>, + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +/* + * How to add or update the tests: + * Contributor: + * 1. add empty files for new tables, if any, under tests/data/acpi + * 2. list any changed files in tests/qtest/bios-tables-test-allowed-diff.h + * 3. commit the above *before* making changes that affect the tables + * + * Contributor or ACPI Maintainer (steps 4-7 need to be redone to resolve conflicts + * in binary commit created in step 6): + * + * After 1-3 above tests will pass but ignore differences with the expected files. + * You will also notice that tests/qtest/bios-tables-test-allowed-diff.h lists + * a bunch of files. This is your hint that you need to do the below: + * 4. Run + * make check V=1 + * this will produce a bunch of warnings about differences + * beween actual and expected ACPI tables. If you have IASL installed, + * they will also be disassembled so you can look at the disassembled + * output. If not - disassemble them yourself in any way you like. + * Look at the differences - make sure they make sense and match what the + * changes you are merging are supposed to do. + * Save the changes, preferably in form of ASL diff for the commit log in + * step 6. + * + * 5. From build directory, run: + * $(SRC_PATH)/tests/data/acpi/rebuild-expected-aml.sh + * 6. Now commit any changes to the expected binary, include diff from step 4 + * in commit log. + * 7. Before sending patches to the list (Contributor) + * or before doing a pull request (Maintainer), make sure + * tests/qtest/bios-tables-test-allowed-diff.h is empty - this will ensure + * following changes to ACPI tables will be noticed. + * + * The resulting patchset/pull request then looks like this: + * - patch 1: list changed files in tests/qtest/bios-tables-test-allowed-diff.h. + * - patches 2 - n: real changes, may contain multiple patches. + * - patch n + 1: update golden master binaries and empty + * tests/qtest/bios-tables-test-allowed-diff.h + */ + +#include "qemu/osdep.h" +#include <glib/gstdio.h> +#include "qemu-common.h" +#include "hw/firmware/smbios.h" +#include "qemu/bitmap.h" +#include "acpi-utils.h" +#include "boot-sector.h" +#include "tpm-emu.h" +#include "hw/acpi/tpm.h" + + +#define MACHINE_PC "pc" +#define MACHINE_Q35 "q35" + +#define ACPI_REBUILD_EXPECTED_AML "TEST_ACPI_REBUILD_AML" + +typedef struct { + bool tcg_only; + const char *machine; + const char *variant; + const char *uefi_fl1; + const char *uefi_fl2; + const char *cd; + const uint64_t ram_start; + const uint64_t scan_len; + uint64_t rsdp_addr; + uint8_t rsdp_table[36 /* ACPI 2.0+ RSDP size */]; + GArray *tables; + uint32_t smbios_ep_addr; + struct smbios_21_entry_point smbios_ep_table; + uint16_t smbios_cpu_max_speed; + uint16_t smbios_cpu_curr_speed; + uint8_t *required_struct_types; + int required_struct_types_len; + QTestState *qts; +} test_data; + +static char disk[] = "tests/acpi-test-disk-XXXXXX"; +static const char *data_dir = "tests/data/acpi"; +#ifdef CONFIG_IASL +static const char *iasl = CONFIG_IASL; +#else +static const char *iasl; +#endif + +static bool compare_signature(const AcpiSdtTable *sdt, const char *signature) +{ + return !memcmp(sdt->aml, signature, 4); +} + +static void cleanup_table_descriptor(AcpiSdtTable *table) +{ + g_free(table->aml); + if (table->aml_file && + !table->tmp_files_retain && + g_strstr_len(table->aml_file, -1, "aml-")) { + unlink(table->aml_file); + } + g_free(table->aml_file); + g_free(table->asl); + if (table->asl_file && + !table->tmp_files_retain) { + unlink(table->asl_file); + } + g_free(table->asl_file); +} + +static void free_test_data(test_data *data) +{ + int i; + + for (i = 0; i < data->tables->len; ++i) { + cleanup_table_descriptor(&g_array_index(data->tables, AcpiSdtTable, i)); + } + + g_array_free(data->tables, true); +} + +static void test_acpi_rsdp_table(test_data *data) +{ + uint8_t *rsdp_table = data->rsdp_table; + + acpi_fetch_rsdp_table(data->qts, data->rsdp_addr, rsdp_table); + + switch (rsdp_table[15 /* Revision offset */]) { + case 0: /* ACPI 1.0 RSDP */ + /* With rev 1, checksum is only for the first 20 bytes */ + g_assert(!acpi_calc_checksum(rsdp_table, 20)); + break; + case 2: /* ACPI 2.0+ RSDP */ + /* With revision 2, we have 2 checksums */ + g_assert(!acpi_calc_checksum(rsdp_table, 20)); + g_assert(!acpi_calc_checksum(rsdp_table, 36)); + break; + default: + g_assert_not_reached(); + } +} + +static void test_acpi_rxsdt_table(test_data *data) +{ + const char *sig = "RSDT"; + AcpiSdtTable rsdt = {}; + int entry_size = 4; + int addr_off = 16 /* RsdtAddress */; + uint8_t *ent; + + if (data->rsdp_table[15 /* Revision offset */] != 0) { + addr_off = 24 /* XsdtAddress */; + entry_size = 8; + sig = "XSDT"; + } + /* read [RX]SDT table */ + acpi_fetch_table(data->qts, &rsdt.aml, &rsdt.aml_len, + &data->rsdp_table[addr_off], entry_size, sig, true); + + /* Load all tables and add to test list directly RSDT referenced tables */ + ACPI_FOREACH_RSDT_ENTRY(rsdt.aml, rsdt.aml_len, ent, entry_size) { + AcpiSdtTable ssdt_table = {}; + + acpi_fetch_table(data->qts, &ssdt_table.aml, &ssdt_table.aml_len, ent, + entry_size, NULL, true); + /* Add table to ASL test tables list */ + g_array_append_val(data->tables, ssdt_table); + } + cleanup_table_descriptor(&rsdt); +} + +static void test_acpi_fadt_table(test_data *data) +{ + /* FADT table is 1st */ + AcpiSdtTable table = g_array_index(data->tables, typeof(table), 0); + uint8_t *fadt_aml = table.aml; + uint32_t fadt_len = table.aml_len; + uint32_t val; + int dsdt_offset = 40 /* DSDT */; + int dsdt_entry_size = 4; + + g_assert(compare_signature(&table, "FACP")); + + /* Since DSDT/FACS isn't in RSDT, add them to ASL test list manually */ + memcpy(&val, fadt_aml + 112 /* Flags */, 4); + val = le32_to_cpu(val); + if (!(val & 1UL << 20 /* HW_REDUCED_ACPI */)) { + acpi_fetch_table(data->qts, &table.aml, &table.aml_len, + fadt_aml + 36 /* FIRMWARE_CTRL */, 4, "FACS", false); + g_array_append_val(data->tables, table); + } + + memcpy(&val, fadt_aml + dsdt_offset, 4); + val = le32_to_cpu(val); + if (!val) { + dsdt_offset = 140 /* X_DSDT */; + dsdt_entry_size = 8; + } + acpi_fetch_table(data->qts, &table.aml, &table.aml_len, + fadt_aml + dsdt_offset, dsdt_entry_size, "DSDT", true); + g_array_append_val(data->tables, table); + + memset(fadt_aml + 36, 0, 4); /* sanitize FIRMWARE_CTRL ptr */ + memset(fadt_aml + 40, 0, 4); /* sanitize DSDT ptr */ + if (fadt_aml[8 /* FADT Major Version */] >= 3) { + memset(fadt_aml + 132, 0, 8); /* sanitize X_FIRMWARE_CTRL ptr */ + memset(fadt_aml + 140, 0, 8); /* sanitize X_DSDT ptr */ + } + + /* update checksum */ + fadt_aml[9 /* Checksum */] = 0; + fadt_aml[9 /* Checksum */] -= acpi_calc_checksum(fadt_aml, fadt_len); +} + +static void dump_aml_files(test_data *data, bool rebuild) +{ + AcpiSdtTable *sdt; + GError *error = NULL; + gchar *aml_file = NULL; + gint fd; + ssize_t ret; + int i; + + for (i = 0; i < data->tables->len; ++i) { + const char *ext = data->variant ? data->variant : ""; + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + g_assert(sdt->aml); + + if (rebuild) { + aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine, + sdt->aml, ext); + fd = g_open(aml_file, O_WRONLY|O_TRUNC|O_CREAT, + S_IRUSR|S_IWUSR|S_IRGRP|S_IWGRP|S_IROTH); + if (fd < 0) { + perror(aml_file); + } + g_assert(fd >= 0); + } else { + fd = g_file_open_tmp("aml-XXXXXX", &sdt->aml_file, &error); + g_assert_no_error(error); + } + + ret = qemu_write_full(fd, sdt->aml, sdt->aml_len); + g_assert(ret == sdt->aml_len); + + close(fd); + + g_free(aml_file); + } +} + +static bool load_asl(GArray *sdts, AcpiSdtTable *sdt) +{ + AcpiSdtTable *temp; + GError *error = NULL; + GString *command_line = g_string_new(iasl); + gint fd; + gchar *out, *out_err; + gboolean ret; + int i; + + fd = g_file_open_tmp("asl-XXXXXX.dsl", &sdt->asl_file, &error); + g_assert_no_error(error); + close(fd); + + /* build command line */ + g_string_append_printf(command_line, " -p %s ", sdt->asl_file); + if (compare_signature(sdt, "DSDT") || + compare_signature(sdt, "SSDT")) { + for (i = 0; i < sdts->len; ++i) { + temp = &g_array_index(sdts, AcpiSdtTable, i); + if (compare_signature(temp, "DSDT") || + compare_signature(temp, "SSDT")) { + g_string_append_printf(command_line, "-e %s ", temp->aml_file); + } + } + } + g_string_append_printf(command_line, "-d %s", sdt->aml_file); + + /* pass 'out' and 'out_err' in order to be redirected */ + ret = g_spawn_command_line_sync(command_line->str, &out, &out_err, NULL, &error); + g_assert_no_error(error); + if (ret) { + ret = g_file_get_contents(sdt->asl_file, &sdt->asl, + &sdt->asl_len, &error); + g_assert(ret); + g_assert_no_error(error); + ret = (sdt->asl_len > 0); + } + + g_free(out); + g_free(out_err); + g_string_free(command_line, true); + + return !ret; +} + +#define COMMENT_END "*/" +#define DEF_BLOCK "DefinitionBlock (" +#define BLOCK_NAME_END "," + +static GString *normalize_asl(gchar *asl_code) +{ + GString *asl = g_string_new(asl_code); + gchar *comment, *block_name; + + /* strip comments (different generation days) */ + comment = g_strstr_len(asl->str, asl->len, COMMENT_END); + if (comment) { + comment += strlen(COMMENT_END); + while (*comment == '\n') { + comment++; + } + asl = g_string_erase(asl, 0, comment - asl->str); + } + + /* strip def block name (it has file path in it) */ + if (g_str_has_prefix(asl->str, DEF_BLOCK)) { + block_name = g_strstr_len(asl->str, asl->len, BLOCK_NAME_END); + g_assert(block_name); + asl = g_string_erase(asl, 0, + block_name + sizeof(BLOCK_NAME_END) - asl->str); + } + + return asl; +} + +static GArray *load_expected_aml(test_data *data) +{ + int i; + AcpiSdtTable *sdt; + GError *error = NULL; + gboolean ret; + gsize aml_len; + + GArray *exp_tables = g_array_new(false, true, sizeof(AcpiSdtTable)); + if (getenv("V")) { + fputc('\n', stderr); + } + for (i = 0; i < data->tables->len; ++i) { + AcpiSdtTable exp_sdt; + gchar *aml_file = NULL; + const char *ext = data->variant ? data->variant : ""; + + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + + memset(&exp_sdt, 0, sizeof(exp_sdt)); + +try_again: + aml_file = g_strdup_printf("%s/%s/%.4s%s", data_dir, data->machine, + sdt->aml, ext); + if (getenv("V")) { + fprintf(stderr, "Looking for expected file '%s'\n", aml_file); + } + if (g_file_test(aml_file, G_FILE_TEST_EXISTS)) { + exp_sdt.aml_file = aml_file; + } else if (*ext != '\0') { + /* try fallback to generic (extension less) expected file */ + ext = ""; + g_free(aml_file); + goto try_again; + } + g_assert(exp_sdt.aml_file); + if (getenv("V")) { + fprintf(stderr, "Using expected file '%s'\n", aml_file); + } + ret = g_file_get_contents(aml_file, (gchar **)&exp_sdt.aml, + &aml_len, &error); + exp_sdt.aml_len = aml_len; + g_assert(ret); + g_assert_no_error(error); + g_assert(exp_sdt.aml); + if (!exp_sdt.aml_len) { + fprintf(stderr, "Warning! zero length expected file '%s'\n", + aml_file); + } + + g_array_append_val(exp_tables, exp_sdt); + } + + return exp_tables; +} + +static bool test_acpi_find_diff_allowed(AcpiSdtTable *sdt) +{ + const gchar *allowed_diff_file[] = { +#include "bios-tables-test-allowed-diff.h" + NULL + }; + const gchar **f; + + for (f = allowed_diff_file; *f; ++f) { + if (!g_strcmp0(sdt->aml_file, *f)) { + return true; + } + } + return false; +} + +/* test the list of tables in @data->tables against reference tables */ +static void test_acpi_asl(test_data *data) +{ + int i; + AcpiSdtTable *sdt, *exp_sdt; + test_data exp_data; + gboolean exp_err, err, all_tables_match = true; + + memset(&exp_data, 0, sizeof(exp_data)); + exp_data.tables = load_expected_aml(data); + dump_aml_files(data, false); + for (i = 0; i < data->tables->len; ++i) { + GString *asl, *exp_asl; + + sdt = &g_array_index(data->tables, AcpiSdtTable, i); + exp_sdt = &g_array_index(exp_data.tables, AcpiSdtTable, i); + + if (sdt->aml_len == exp_sdt->aml_len && + !memcmp(sdt->aml, exp_sdt->aml, sdt->aml_len)) { + /* Identical table binaries: no need to disassemble. */ + continue; + } + + fprintf(stderr, + "acpi-test: Warning! %.4s binary file mismatch. " + "Actual [aml:%s], Expected [aml:%s].\n" + "See source file tests/qtest/bios-tables-test.c " + "for instructions on how to update expected files.\n", + exp_sdt->aml, sdt->aml_file, exp_sdt->aml_file); + + all_tables_match = all_tables_match && + test_acpi_find_diff_allowed(exp_sdt); + + /* + * don't try to decompile if IASL isn't present, in this case user + * will just 'get binary file mismatch' warnings and test failure + */ + if (!iasl) { + continue; + } + + err = load_asl(data->tables, sdt); + asl = normalize_asl(sdt->asl); + + exp_err = load_asl(exp_data.tables, exp_sdt); + exp_asl = normalize_asl(exp_sdt->asl); + + /* TODO: check for warnings */ + g_assert(!err || exp_err); + + if (g_strcmp0(asl->str, exp_asl->str)) { + sdt->tmp_files_retain = true; + if (exp_err) { + fprintf(stderr, + "Warning! iasl couldn't parse the expected aml\n"); + } else { + exp_sdt->tmp_files_retain = true; + fprintf(stderr, + "acpi-test: Warning! %.4s mismatch. " + "Actual [asl:%s, aml:%s], Expected [asl:%s, aml:%s].\n", + exp_sdt->aml, sdt->asl_file, sdt->aml_file, + exp_sdt->asl_file, exp_sdt->aml_file); + fflush(stderr); + if (getenv("V")) { + const char *diff_env = getenv("DIFF"); + const char *diff_cmd = diff_env ? diff_env : "diff -U 16"; + char *diff = g_strdup_printf("%s %s %s", diff_cmd, + exp_sdt->asl_file, sdt->asl_file); + int out = dup(STDOUT_FILENO); + int ret G_GNUC_UNUSED; + + dup2(STDERR_FILENO, STDOUT_FILENO); + ret = system(diff) ; + dup2(out, STDOUT_FILENO); + close(out); + g_free(diff); + } + } + } + g_string_free(asl, true); + g_string_free(exp_asl, true); + } + if (!iasl && !all_tables_match) { + fprintf(stderr, "to see ASL diff between mismatched files install IASL," + " rebuild QEMU from scratch and re-run tests with V=1" + " environment variable set"); + } + g_assert(all_tables_match); + + free_test_data(&exp_data); +} + +static bool smbios_ep_table_ok(test_data *data) +{ + struct smbios_21_entry_point *ep_table = &data->smbios_ep_table; + uint32_t addr = data->smbios_ep_addr; + + qtest_memread(data->qts, addr, ep_table, sizeof(*ep_table)); + if (memcmp(ep_table->anchor_string, "_SM_", 4)) { + return false; + } + if (memcmp(ep_table->intermediate_anchor_string, "_DMI_", 5)) { + return false; + } + if (ep_table->structure_table_length == 0) { + return false; + } + if (ep_table->number_of_structures == 0) { + return false; + } + if (acpi_calc_checksum((uint8_t *)ep_table, sizeof *ep_table) || + acpi_calc_checksum((uint8_t *)ep_table + 0x10, + sizeof *ep_table - 0x10)) { + return false; + } + return true; +} + +static void test_smbios_entry_point(test_data *data) +{ + uint32_t off; + + /* find smbios entry point structure */ + for (off = 0xf0000; off < 0x100000; off += 0x10) { + uint8_t sig[] = "_SM_"; + int i; + + for (i = 0; i < sizeof sig - 1; ++i) { + sig[i] = qtest_readb(data->qts, off + i); + } + + if (!memcmp(sig, "_SM_", sizeof sig)) { + /* signature match, but is this a valid entry point? */ + data->smbios_ep_addr = off; + if (smbios_ep_table_ok(data)) { + break; + } + } + } + + g_assert_cmphex(off, <, 0x100000); +} + +static inline bool smbios_single_instance(uint8_t type) +{ + switch (type) { + case 0: + case 1: + case 2: + case 3: + case 16: + case 32: + case 127: + return true; + default: + return false; + } +} + +static bool smbios_cpu_test(test_data *data, uint32_t addr) +{ + uint16_t expect_speed[2]; + uint16_t real; + int offset[2]; + int i; + + /* Check CPU speed for backward compatibility */ + offset[0] = offsetof(struct smbios_type_4, max_speed); + offset[1] = offsetof(struct smbios_type_4, current_speed); + expect_speed[0] = data->smbios_cpu_max_speed ? : 2000; + expect_speed[1] = data->smbios_cpu_curr_speed ? : 2000; + + for (i = 0; i < 2; i++) { + real = qtest_readw(data->qts, addr + offset[i]); + if (real != expect_speed[i]) { + fprintf(stderr, "Unexpected SMBIOS CPU speed: real %u expect %u\n", + real, expect_speed[i]); + return false; + } + } + + return true; +} + +static void test_smbios_structs(test_data *data) +{ + DECLARE_BITMAP(struct_bitmap, SMBIOS_MAX_TYPE+1) = { 0 }; + struct smbios_21_entry_point *ep_table = &data->smbios_ep_table; + uint32_t addr = le32_to_cpu(ep_table->structure_table_address); + int i, len, max_len = 0; + uint8_t type, prv, crt; + + /* walk the smbios tables */ + for (i = 0; i < le16_to_cpu(ep_table->number_of_structures); i++) { + + /* grab type and formatted area length from struct header */ + type = qtest_readb(data->qts, addr); + g_assert_cmpuint(type, <=, SMBIOS_MAX_TYPE); + len = qtest_readb(data->qts, addr + 1); + + /* single-instance structs must not have been encountered before */ + if (smbios_single_instance(type)) { + g_assert(!test_bit(type, struct_bitmap)); + } + set_bit(type, struct_bitmap); + + if (type == 4) { + g_assert(smbios_cpu_test(data, addr)); + } + + /* seek to end of unformatted string area of this struct ("\0\0") */ + prv = crt = 1; + while (prv || crt) { + prv = crt; + crt = qtest_readb(data->qts, addr + len); + len++; + } + + /* keep track of max. struct size */ + if (max_len < len) { + max_len = len; + g_assert_cmpuint(max_len, <=, ep_table->max_structure_size); + } + + /* start of next structure */ + addr += len; + } + + /* total table length and max struct size must match entry point values */ + g_assert_cmpuint(le16_to_cpu(ep_table->structure_table_length), ==, + addr - le32_to_cpu(ep_table->structure_table_address)); + g_assert_cmpuint(le16_to_cpu(ep_table->max_structure_size), ==, max_len); + + /* required struct types must all be present */ + for (i = 0; i < data->required_struct_types_len; i++) { + g_assert(test_bit(data->required_struct_types[i], struct_bitmap)); + } +} + +static void test_acpi_one(const char *params, test_data *data) +{ + char *args; + bool use_uefi = data->uefi_fl1 && data->uefi_fl2; + + if (use_uefi) { + /* + * TODO: convert '-drive if=pflash' to new syntax (see e33763be7cd3) + * when arm/virt boad starts to support it. + */ + args = g_strdup_printf("-machine %s %s -accel tcg -nodefaults -nographic " + "-drive if=pflash,format=raw,file=%s,readonly " + "-drive if=pflash,format=raw,file=%s,snapshot=on -cdrom %s %s", + data->machine, data->tcg_only ? "" : "-accel kvm", + data->uefi_fl1, data->uefi_fl2, data->cd, params ? params : ""); + + } else { + /* Disable kernel irqchip to be able to override apic irq0. */ + args = g_strdup_printf("-machine %s,kernel-irqchip=off %s -accel tcg " + "-net none -display none %s " + "-drive id=hd0,if=none,file=%s,format=raw " + "-device ide-hd,drive=hd0 ", + data->machine, data->tcg_only ? "" : "-accel kvm", + params ? params : "", disk); + } + + data->qts = qtest_init(args); + + if (use_uefi) { + g_assert(data->scan_len); + data->rsdp_addr = acpi_find_rsdp_address_uefi(data->qts, + data->ram_start, data->scan_len); + } else { + boot_sector_test(data->qts); + data->rsdp_addr = acpi_find_rsdp_address(data->qts); + g_assert_cmphex(data->rsdp_addr, <, 0x100000); + } + + data->tables = g_array_new(false, true, sizeof(AcpiSdtTable)); + test_acpi_rsdp_table(data); + test_acpi_rxsdt_table(data); + test_acpi_fadt_table(data); + + if (getenv(ACPI_REBUILD_EXPECTED_AML)) { + dump_aml_files(data, true); + } else { + test_acpi_asl(data); + } + + /* + * TODO: make SMBIOS tests work with UEFI firmware, + * Bug on uefi-test-tools to provide entry point: + * https://bugs.launchpad.net/qemu/+bug/1821884 + */ + if (!use_uefi) { + test_smbios_entry_point(data); + test_smbios_structs(data); + } + + qtest_quit(data->qts); + g_free(args); +} + +static uint8_t base_required_struct_types[] = { + 0, 1, 3, 4, 16, 17, 19, 32, 127 +}; + +static void test_acpi_piix4_tcg(void) +{ + test_data data; + + /* Supplying -machine accel argument overrides the default (qtest). + * This is to make guest actually run. + */ + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one(NULL, &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_bridge(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".bridge"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-device pci-bridge,chassis_nr=1", &data); + free_test_data(&data); +} + +<<<<<<< HEAD +static void test_acpi_piix4_bridge_hotplug(void) +======= +static void test_acpi_piix4_root_hotplug(void) +>>>>>>> tests/acpi: add a new unit test to test hotplug off/on feature on the root pci bus +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; +<<<<<<< HEAD + data.variant = ".hpbridge"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-global PIIX4_PM.acpi-pci-hotplug-with-bridge-support=off " + "-device pci-bridge,chassis_nr=1", &data); +======= + data.variant = ".roothp"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-global PIIX4_PM.acpi-root-pci-hotplug=off", &data); +>>>>>>> tests/acpi: add a new unit test to test hotplug off/on feature on the root pci bus + free_test_data(&data); +} + +static void test_acpi_q35_tcg(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one(NULL, &data); + free_test_data(&data); + + data.smbios_cpu_max_speed = 3000; + data.smbios_cpu_curr_speed = 2600; + test_acpi_one("-smbios type=4,max-speed=3000,current-speed=2600", &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_bridge(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".bridge"; + data.required_struct_types = base_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(base_required_struct_types); + test_acpi_one("-device pci-bridge,chassis_nr=1", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_mmio64(void) +{ + test_data data = { + .machine = MACHINE_Q35, + .variant = ".mmio64", + .required_struct_types = base_required_struct_types, + .required_struct_types_len = ARRAY_SIZE(base_required_struct_types) + }; + + test_acpi_one("-m 128M,slots=1,maxmem=2G " + "-object memory-backend-ram,id=ram0,size=128M " + "-numa node,memdev=ram0 " + "-device pci-testdev,membar=2G", + &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_cphp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".cphp"; + test_acpi_one("-smp 2,cores=3,sockets=2,maxcpus=6" + " -object memory-backend-ram,id=ram0,size=64M" + " -object memory-backend-ram,id=ram1,size=64M" + " -numa node,memdev=ram0 -numa node,memdev=ram1" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_cphp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".cphp"; + test_acpi_one(" -smp 2,cores=3,sockets=2,maxcpus=6" + " -object memory-backend-ram,id=ram0,size=64M" + " -object memory-backend-ram,id=ram1,size=64M" + " -numa node,memdev=ram0 -numa node,memdev=ram1" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static uint8_t ipmi_required_struct_types[] = { + 0, 1, 3, 4, 16, 17, 19, 32, 38, 127 +}; + +static void test_acpi_q35_tcg_ipmi(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".ipmibt"; + data.required_struct_types = ipmi_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types); + test_acpi_one("-device ipmi-bmc-sim,id=bmc0" + " -device isa-ipmi-bt,bmc=bmc0", + &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_ipmi(void) +{ + test_data data; + + /* Supplying -machine accel argument overrides the default (qtest). + * This is to make guest actually run. + */ + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".ipmikcs"; + data.required_struct_types = ipmi_required_struct_types; + data.required_struct_types_len = ARRAY_SIZE(ipmi_required_struct_types); + test_acpi_one("-device ipmi-bmc-sim,id=bmc0" + " -device isa-ipmi-kcs,irq=0,bmc=bmc0", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_memhp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".memhp"; + test_acpi_one(" -m 128,slots=3,maxmem=1G" + " -object memory-backend-ram,id=ram0,size=64M" + " -object memory-backend-ram,id=ram1,size=64M" + " -numa node,memdev=ram0 -numa node,memdev=ram1" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_memhp(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".memhp"; + test_acpi_one(" -m 128,slots=3,maxmem=1G" + " -object memory-backend-ram,id=ram0,size=64M" + " -object memory-backend-ram,id=ram1,size=64M" + " -numa node,memdev=ram0 -numa node,memdev=ram1" + " -numa dist,src=0,dst=1,val=21", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_numamem(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_Q35; + data.variant = ".numamem"; + test_acpi_one(" -object memory-backend-ram,id=ram0,size=128M" + " -numa node -numa node,memdev=ram0", &data); + free_test_data(&data); +} + +static void test_acpi_piix4_tcg_numamem(void) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = MACHINE_PC; + data.variant = ".numamem"; + test_acpi_one(" -object memory-backend-ram,id=ram0,size=128M" + " -numa node -numa node,memdev=ram0", &data); + free_test_data(&data); +} + +uint64_t tpm_tis_base_addr; + +static void test_acpi_tcg_tpm(const char *machine, const char *tpm_if, + uint64_t base) +{ +#ifdef CONFIG_TPM + gchar *tmp_dir_name = g_strdup_printf("qemu-test_acpi_%s_tcg_%s.XXXXXX", + machine, tpm_if); + char *tmp_path = g_dir_make_tmp(tmp_dir_name, NULL); + TestState test; + test_data data; + GThread *thread; + char *args, *variant = g_strdup_printf(".%s", tpm_if); + + tpm_tis_base_addr = base; + + module_call_init(MODULE_INIT_QOM); + + test.addr = g_new0(SocketAddress, 1); + test.addr->type = SOCKET_ADDRESS_TYPE_UNIX; + test.addr->u.q_unix.path = g_build_filename(tmp_path, "sock", NULL); + g_mutex_init(&test.data_mutex); + g_cond_init(&test.data_cond); + test.data_cond_signal = false; + + thread = g_thread_new(NULL, tpm_emu_ctrl_thread, &test); + tpm_emu_test_wait_cond(&test); + + memset(&data, 0, sizeof(data)); + data.machine = machine; + data.variant = variant; + + args = g_strdup_printf( + " -chardev socket,id=chr,path=%s" + " -tpmdev emulator,id=dev,chardev=chr" + " -device tpm-%s,tpmdev=dev", + test.addr->u.q_unix.path, tpm_if); + + test_acpi_one(args, &data); + + g_thread_join(thread); + g_unlink(test.addr->u.q_unix.path); + qapi_free_SocketAddress(test.addr); + g_rmdir(tmp_path); + g_free(variant); + g_free(tmp_path); + g_free(tmp_dir_name); + g_free(args); + free_test_data(&data); +#else + g_test_skip("TPM disabled"); +#endif +} + +static void test_acpi_q35_tcg_tpm_tis(void) +{ + test_acpi_tcg_tpm("q35", "tis", 0xFED40000); +} + +static void test_acpi_tcg_dimm_pxm(const char *machine) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = machine; + data.variant = ".dimmpxm"; + test_acpi_one(" -machine nvdimm=on,nvdimm-persistence=cpu" + " -smp 4,sockets=4" + " -m 128M,slots=3,maxmem=1G" + " -object memory-backend-ram,id=ram0,size=32M" + " -object memory-backend-ram,id=ram1,size=32M" + " -object memory-backend-ram,id=ram2,size=32M" + " -object memory-backend-ram,id=ram3,size=32M" + " -numa node,memdev=ram0,nodeid=0" + " -numa node,memdev=ram1,nodeid=1" + " -numa node,memdev=ram2,nodeid=2" + " -numa node,memdev=ram3,nodeid=3" + " -numa cpu,node-id=0,socket-id=0" + " -numa cpu,node-id=1,socket-id=1" + " -numa cpu,node-id=2,socket-id=2" + " -numa cpu,node-id=3,socket-id=3" + " -object memory-backend-ram,id=ram4,size=128M" + " -object memory-backend-ram,id=nvm0,size=128M" + " -device pc-dimm,id=dimm0,memdev=ram4,node=1" + " -device nvdimm,id=dimm1,memdev=nvm0,node=2", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_dimm_pxm(void) +{ + test_acpi_tcg_dimm_pxm(MACHINE_Q35); +} + +static void test_acpi_piix4_tcg_dimm_pxm(void) +{ + test_acpi_tcg_dimm_pxm(MACHINE_PC); +} + +static void test_acpi_virt_tcg_memhp(void) +{ + test_data data = { + .machine = "virt", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 256ULL * 1024 * 1024, + }; + + data.variant = ".memhp"; + test_acpi_one(" -machine nvdimm=on" + " -cpu cortex-a57" + " -m 256M,slots=3,maxmem=1G" + " -object memory-backend-ram,id=ram0,size=128M" + " -object memory-backend-ram,id=ram1,size=128M" + " -numa node,memdev=ram0 -numa node,memdev=ram1" + " -numa dist,src=0,dst=1,val=21" + " -object memory-backend-ram,id=ram2,size=128M" + " -object memory-backend-ram,id=nvm0,size=128M" + " -device pc-dimm,id=dimm0,memdev=ram2,node=0" + " -device nvdimm,id=dimm1,memdev=nvm0,node=1", + &data); + + free_test_data(&data); + +} + +static void test_acpi_virt_tcg_numamem(void) +{ + test_data data = { + .machine = "virt", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + + data.variant = ".numamem"; + test_acpi_one(" -cpu cortex-a57" + " -object memory-backend-ram,id=ram0,size=128M" + " -numa node,memdev=ram0", + &data); + + free_test_data(&data); + +} + +static void test_acpi_tcg_acpi_hmat(const char *machine) +{ + test_data data; + + memset(&data, 0, sizeof(data)); + data.machine = machine; + data.variant = ".acpihmat"; + test_acpi_one(" -machine hmat=on" + " -smp 2,sockets=2" + " -m 128M,slots=2,maxmem=1G" + " -object memory-backend-ram,size=64M,id=m0" + " -object memory-backend-ram,size=64M,id=m1" + " -numa node,nodeid=0,memdev=m0" + " -numa node,nodeid=1,memdev=m1,initiator=0" + " -numa cpu,node-id=0,socket-id=0" + " -numa cpu,node-id=0,socket-id=1" + " -numa hmat-lb,initiator=0,target=0,hierarchy=memory," + "data-type=access-latency,latency=1" + " -numa hmat-lb,initiator=0,target=0,hierarchy=memory," + "data-type=access-bandwidth,bandwidth=65534M" + " -numa hmat-lb,initiator=0,target=1,hierarchy=memory," + "data-type=access-latency,latency=65534" + " -numa hmat-lb,initiator=0,target=1,hierarchy=memory," + "data-type=access-bandwidth,bandwidth=32767M" + " -numa hmat-cache,node-id=0,size=10K,level=1," + "associativity=direct,policy=write-back,line=8" + " -numa hmat-cache,node-id=1,size=10K,level=1," + "associativity=direct,policy=write-back,line=8", + &data); + free_test_data(&data); +} + +static void test_acpi_q35_tcg_acpi_hmat(void) +{ + test_acpi_tcg_acpi_hmat(MACHINE_Q35); +} + +static void test_acpi_piix4_tcg_acpi_hmat(void) +{ + test_acpi_tcg_acpi_hmat(MACHINE_PC); +} + +static void test_acpi_virt_tcg(void) +{ + test_data data = { + .machine = "virt", + .tcg_only = true, + .uefi_fl1 = "pc-bios/edk2-aarch64-code.fd", + .uefi_fl2 = "pc-bios/edk2-arm-vars.fd", + .cd = "tests/data/uefi-boot-images/bios-tables-test.aarch64.iso.qcow2", + .ram_start = 0x40000000ULL, + .scan_len = 128ULL * 1024 * 1024, + }; + + test_acpi_one("-cpu cortex-a57", &data); + free_test_data(&data); + + data.smbios_cpu_max_speed = 2900; + data.smbios_cpu_curr_speed = 2700; + test_acpi_one("-cpu cortex-a57 " + "-smbios type=4,max-speed=2900,current-speed=2700", &data); + free_test_data(&data); +} + +int main(int argc, char *argv[]) +{ + const char *arch = qtest_get_arch(); + int ret; + + g_test_init(&argc, &argv, NULL); + + if (strcmp(arch, "i386") == 0 || strcmp(arch, "x86_64") == 0) { + ret = boot_sector_init(disk); + if (ret) { + return ret; + } + + qtest_add_func("acpi/q35/tpm-tis", test_acpi_q35_tcg_tpm_tis); + qtest_add_func("acpi/piix4", test_acpi_piix4_tcg); + qtest_add_func("acpi/piix4/bridge", test_acpi_piix4_tcg_bridge); +<<<<<<< HEAD + qtest_add_func("acpi/piix4/brhotplug", test_acpi_piix4_bridge_hotplug); +======= + qtest_add_func("acpi/piix4/hotplug", test_acpi_piix4_root_hotplug); +>>>>>>> tests/acpi: add a new unit test to test hotplug off/on feature on the root pci bus + qtest_add_func("acpi/q35", test_acpi_q35_tcg); + qtest_add_func("acpi/q35/bridge", test_acpi_q35_tcg_bridge); + qtest_add_func("acpi/q35/mmio64", test_acpi_q35_tcg_mmio64); + qtest_add_func("acpi/piix4/ipmi", test_acpi_piix4_tcg_ipmi); + qtest_add_func("acpi/q35/ipmi", test_acpi_q35_tcg_ipmi); + qtest_add_func("acpi/piix4/cpuhp", test_acpi_piix4_tcg_cphp); + qtest_add_func("acpi/q35/cpuhp", test_acpi_q35_tcg_cphp); + qtest_add_func("acpi/piix4/memhp", test_acpi_piix4_tcg_memhp); + qtest_add_func("acpi/q35/memhp", test_acpi_q35_tcg_memhp); + qtest_add_func("acpi/piix4/numamem", test_acpi_piix4_tcg_numamem); + qtest_add_func("acpi/q35/numamem", test_acpi_q35_tcg_numamem); + qtest_add_func("acpi/piix4/dimmpxm", test_acpi_piix4_tcg_dimm_pxm); + qtest_add_func("acpi/q35/dimmpxm", test_acpi_q35_tcg_dimm_pxm); + qtest_add_func("acpi/piix4/acpihmat", test_acpi_piix4_tcg_acpi_hmat); + qtest_add_func("acpi/q35/acpihmat", test_acpi_q35_tcg_acpi_hmat); + } else if (strcmp(arch, "aarch64") == 0) { + qtest_add_func("acpi/virt", test_acpi_virt_tcg); + qtest_add_func("acpi/virt/numamem", test_acpi_virt_tcg_numamem); + qtest_add_func("acpi/virt/memhp", test_acpi_virt_tcg_memhp); + } + ret = g_test_run(); + boot_sector_cleanup(disk); + return ret; +} diff --git a/tests/qtest/bios-tables-test.c.rej b/tests/qtest/bios-tables-test.c.rej new file mode 100644 index 0000000000..aacd6ae220 --- /dev/null +++ b/tests/qtest/bios-tables-test.c.rej @@ -0,0 +1,22 @@ +--- tests/qtest/bios-tables-test.c ++++ tests/qtest/bios-tables-test.c +@@ -927,12 +927,17 @@ static void test_acpi_virt_tcg_memhp(void) + }; + 20 + data.variant =3D ".memhp"; +- test_acpi_one(" -cpu cortex-a57" ++ test_acpi_one(" -machine nvdimm=3Don" ++ " -cpu cortex-a57" + " -m 256M,slots=3D3,maxmem=3D1G" + " -object memory-backend-ram,id=3Dram0,size=3D128M" + " -object memory-backend-ram,id=3Dram1,size=3D128M" + " -numa node,memdev=3Dram0 -numa node,memdev=3Dram1" +- " -numa dist,src=3D0,dst=3D1,val=3D21", ++ " -numa dist,src=3D0,dst=3D1,val=3D21" ++ " -object memory-backend-ram,id=3Dram2,size=3D128M" ++ " -object memory-backend-ram,id=3Dnvm0,size=3D128M" ++ " -device pc-dimm,id=3Ddimm0,memdev=3Dram2,node=3D0" ++ " -device nvdimm,id=3Ddimm1,memdev=3Dnvm0,node=3D1", + &data); + 20 + free_test_data(&data); diff --git a/tests/qtest/cpu-plug-test.c b/tests/qtest/cpu-plug-test.c index e8ffbbce4b..a1c689414b 100644 --- a/tests/qtest/cpu-plug-test.c +++ b/tests/qtest/cpu-plug-test.c @@ -25,54 +25,6 @@ struct PlugTestData { }; typedef struct PlugTestData PlugTestData; -static void test_plug_with_cpu_add(gconstpointer data) -{ - const PlugTestData *s = data; - char *args; - QDict *response; - unsigned int i; - - args = g_strdup_printf("-machine %s -cpu %s " - "-smp 1,sockets=%u,cores=%u,threads=%u,maxcpus=%u", - s->machine, s->cpu_model, - s->sockets, s->cores, s->threads, s->maxcpus); - qtest_start(args); - - for (i = 1; i < s->maxcpus; i++) { - response = qmp("{ 'execute': 'cpu-add'," - " 'arguments': { 'id': %d } }", i); - g_assert(response); - g_assert(!qdict_haskey(response, "error")); - qobject_unref(response); - } - - qtest_end(); - g_free(args); -} - -static void test_plug_without_cpu_add(gconstpointer data) -{ - const PlugTestData *s = data; - char *args; - QDict *response; - - args = g_strdup_printf("-machine %s -cpu %s " - "-smp 1,sockets=%u,cores=%u,threads=%u,maxcpus=%u", - s->machine, s->cpu_model, - s->sockets, s->cores, s->threads, s->maxcpus); - qtest_start(args); - - response = qmp("{ 'execute': 'cpu-add'," - " 'arguments': { 'id': %d } }", - s->sockets * s->cores * s->threads); - g_assert(response); - g_assert(qdict_haskey(response, "error")); - qobject_unref(response); - - qtest_end(); - g_free(args); -} - static void test_plug_with_device_add(gconstpointer data) { const PlugTestData *td = data; @@ -144,36 +96,13 @@ static void add_pc_test_case(const char *mname) data->cores = 3; data->threads = 2; data->maxcpus = data->sockets * data->cores * data->threads; - if (g_str_has_suffix(mname, "-1.4") || - (strcmp(mname, "pc-1.3") == 0) || - (strcmp(mname, "pc-1.2") == 0) || - (strcmp(mname, "pc-1.1") == 0) || - (strcmp(mname, "pc-1.0") == 0)) { - path = g_strdup_printf("cpu-plug/%s/init/%ux%ux%u&maxcpus=%u", - mname, data->sockets, data->cores, - data->threads, data->maxcpus); - qtest_add_data_func_full(path, data, test_plug_without_cpu_add, - test_data_free); - g_free(path); - } else { - PlugTestData *data2 = g_memdup(data, sizeof(PlugTestData)); - - data2->machine = g_strdup(data->machine); - data2->device_model = g_strdup(data->device_model); - path = g_strdup_printf("cpu-plug/%s/cpu-add/%ux%ux%u&maxcpus=%u", - mname, data->sockets, data->cores, - data->threads, data->maxcpus); - qtest_add_data_func_full(path, data, test_plug_with_cpu_add, - test_data_free); - g_free(path); - path = g_strdup_printf("cpu-plug/%s/device-add/%ux%ux%u&maxcpus=%u", - mname, data2->sockets, data2->cores, - data2->threads, data2->maxcpus); - qtest_add_data_func_full(path, data2, test_plug_with_device_add, - test_data_free); - g_free(path); - } + path = g_strdup_printf("cpu-plug/%s/device-add/%ux%ux%u&maxcpus=%u", + mname, data->sockets, data->cores, + data->threads, data->maxcpus); + qtest_add_data_func_full(path, data, test_plug_with_device_add, + test_data_free); + g_free(path); } static void add_pseries_test_case(const char *mname) @@ -205,7 +134,7 @@ static void add_pseries_test_case(const char *mname) static void add_s390x_test_case(const char *mname) { char *path; - PlugTestData *data, *data2; + PlugTestData *data; if (!g_str_has_prefix(mname, "s390-ccw-virtio-")) { return; @@ -220,21 +149,10 @@ static void add_s390x_test_case(const char *mname) data->threads = 1; data->maxcpus = data->sockets * data->cores * data->threads; - data2 = g_memdup(data, sizeof(PlugTestData)); - data2->machine = g_strdup(data->machine); - data2->device_model = g_strdup(data->device_model); - - path = g_strdup_printf("cpu-plug/%s/cpu-add/%ux%ux%u&maxcpus=%u", + path = g_strdup_printf("cpu-plug/%s/device-add/%ux%ux%u&maxcpus=%u", mname, data->sockets, data->cores, data->threads, data->maxcpus); - qtest_add_data_func_full(path, data, test_plug_with_cpu_add, - test_data_free); - g_free(path); - - path = g_strdup_printf("cpu-plug/%s/device-add/%ux%ux%u&maxcpus=%u", - mname, data2->sockets, data2->cores, - data2->threads, data2->maxcpus); - qtest_add_data_func_full(path, data2, test_plug_with_device_add, + qtest_add_data_func_full(path, data, test_plug_with_device_add, test_data_free); g_free(path); } diff --git a/tests/qtest/test-hmp.c b/tests/qtest/test-hmp.c index aea1384bac..94a8023173 100644 --- a/tests/qtest/test-hmp.c +++ b/tests/qtest/test-hmp.c @@ -27,7 +27,6 @@ static const char *hmp_cmds[] = { "chardev-change testchardev1 ringbuf", "chardev-remove testchardev1", "commit all", - "cpu-add 1", "cpu 0", "device_add ?", "device_add usb-mouse,id=mouse1", diff --git a/tests/qtest/vhost-user-test.c b/tests/qtest/vhost-user-test.c index 9ee0f1e4fd..3df5322614 100644 --- a/tests/qtest/vhost-user-test.c +++ b/tests/qtest/vhost-user-test.c @@ -135,6 +135,10 @@ enum { TEST_FLAGS_END, }; +enum { + VHOST_USER_NET, +}; + typedef struct TestServer { gchar *socket_path; gchar *mig_path; @@ -154,10 +158,25 @@ typedef struct TestServer { bool test_fail; int test_flags; int queues; + struct vhost_user_ops *vu_ops; } TestServer; +struct vhost_user_ops { + /* Device types. */ + int type; + void (*append_opts)(TestServer *s, GString *cmd_line, + const char *chr_opts); + + /* VHOST-USER commands. */ + void (*set_features)(TestServer *s, CharBackend *chr, + VhostUserMsg *msg); + void (*get_protocol_features)(TestServer *s, + CharBackend *chr, VhostUserMsg *msg); +}; + static const char *init_hugepagefs(void); -static TestServer *test_server_new(const gchar *name); +static TestServer *test_server_new(const gchar *name, + struct vhost_user_ops *ops); static void test_server_free(TestServer *server); static void test_server_listen(TestServer *server); @@ -167,7 +186,7 @@ enum test_memfd { TEST_MEMFD_NO, }; -static void append_vhost_opts(TestServer *s, GString *cmd_line, +static void append_vhost_net_opts(TestServer *s, GString *cmd_line, const char *chr_opts) { g_string_append_printf(cmd_line, QEMU_CMD_CHR QEMU_CMD_NETDEV, @@ -332,25 +351,15 @@ static void chr_read(void *opaque, const uint8_t *buf, int size) break; case VHOST_USER_SET_FEATURES: - g_assert_cmpint(msg.payload.u64 & (0x1ULL << VHOST_USER_F_PROTOCOL_FEATURES), - !=, 0ULL); - if (s->test_flags == TEST_FLAGS_DISCONNECT) { - qemu_chr_fe_disconnect(chr); - s->test_flags = TEST_FLAGS_BAD; + if (s->vu_ops->set_features) { + s->vu_ops->set_features(s, chr, &msg); } break; case VHOST_USER_GET_PROTOCOL_FEATURES: - /* send back features to qemu */ - msg.flags |= VHOST_USER_REPLY_MASK; - msg.size = sizeof(m.payload.u64); - msg.payload.u64 = 1 << VHOST_USER_PROTOCOL_F_LOG_SHMFD; - msg.payload.u64 |= 1 << VHOST_USER_PROTOCOL_F_CROSS_ENDIAN; - if (s->queues > 1) { - msg.payload.u64 |= 1 << VHOST_USER_PROTOCOL_F_MQ; + if (s->vu_ops->get_protocol_features) { + s->vu_ops->get_protocol_features(s, chr, &msg); } - p = (uint8_t *) &msg; - qemu_chr_fe_write_all(chr, p, VHOST_USER_HDR_SIZE + msg.size); break; case VHOST_USER_GET_VRING_BASE: @@ -467,7 +476,8 @@ static const char *init_hugepagefs(void) #endif } -static TestServer *test_server_new(const gchar *name) +static TestServer *test_server_new(const gchar *name, + struct vhost_user_ops *ops) { TestServer *server = g_new0(TestServer, 1); char template[] = "/tmp/vhost-test-XXXXXX"; @@ -495,6 +505,7 @@ static TestServer *test_server_new(const gchar *name) server->log_fd = -1; server->queues = 1; + server->vu_ops = ops; return server; } @@ -669,11 +680,11 @@ static void vhost_user_test_cleanup(void *s) static void *vhost_user_test_setup(GString *cmd_line, void *arg) { - TestServer *server = test_server_new("vhost-user-test"); + TestServer *server = test_server_new("vhost-user-test", arg); test_server_listen(server); append_mem_opts(server, cmd_line, 256, TEST_MEMFD_AUTO); - append_vhost_opts(server, cmd_line, ""); + server->vu_ops->append_opts(server, cmd_line, ""); g_test_queue_destroy(vhost_user_test_cleanup, server); @@ -682,11 +693,11 @@ static void *vhost_user_test_setup(GString *cmd_line, void *arg) static void *vhost_user_test_setup_memfd(GString *cmd_line, void *arg) { - TestServer *server = test_server_new("vhost-user-test"); + TestServer *server = test_server_new("vhost-user-test", arg); test_server_listen(server); append_mem_opts(server, cmd_line, 256, TEST_MEMFD_YES); - append_vhost_opts(server, cmd_line, ""); + server->vu_ops->append_opts(server, cmd_line, ""); g_test_queue_destroy(vhost_user_test_cleanup, server); @@ -720,7 +731,7 @@ static void test_migrate(void *obj, void *arg, QGuestAllocator *alloc) return; } - dest = test_server_new("dest"); + dest = test_server_new("dest", s->vu_ops); dest_cmdline = g_string_new(qos_get_current_command_line()); uri = g_strdup_printf("%s%s", "unix:", dest->mig_path); @@ -730,7 +741,7 @@ static void test_migrate(void *obj, void *arg, QGuestAllocator *alloc) test_server_listen(dest); g_string_append_printf(dest_cmdline, " -incoming %s", uri); append_mem_opts(dest, dest_cmdline, 256, TEST_MEMFD_AUTO); - append_vhost_opts(dest, dest_cmdline, ""); + dest->vu_ops->append_opts(dest, dest_cmdline, ""); to = qtest_init(dest_cmdline->str); /* This would be where you call qos_allocate_objects(to, NULL), if you want @@ -831,11 +842,11 @@ connect_thread(gpointer data) static void *vhost_user_test_setup_reconnect(GString *cmd_line, void *arg) { - TestServer *s = test_server_new("reconnect"); + TestServer *s = test_server_new("reconnect", arg); g_thread_new("connect", connect_thread, s); append_mem_opts(s, cmd_line, 256, TEST_MEMFD_AUTO); - append_vhost_opts(s, cmd_line, ",server"); + s->vu_ops->append_opts(s, cmd_line, ",server"); g_test_queue_destroy(vhost_user_test_cleanup, s); @@ -866,13 +877,13 @@ static void test_reconnect(void *obj, void *arg, QGuestAllocator *alloc) static void *vhost_user_test_setup_connect_fail(GString *cmd_line, void *arg) { - TestServer *s = test_server_new("connect-fail"); + TestServer *s = test_server_new("connect-fail", arg); s->test_fail = true; g_thread_new("connect", connect_thread, s); append_mem_opts(s, cmd_line, 256, TEST_MEMFD_AUTO); - append_vhost_opts(s, cmd_line, ",server"); + s->vu_ops->append_opts(s, cmd_line, ",server"); g_test_queue_destroy(vhost_user_test_cleanup, s); @@ -881,13 +892,13 @@ static void *vhost_user_test_setup_connect_fail(GString *cmd_line, void *arg) static void *vhost_user_test_setup_flags_mismatch(GString *cmd_line, void *arg) { - TestServer *s = test_server_new("flags-mismatch"); + TestServer *s = test_server_new("flags-mismatch", arg); s->test_flags = TEST_FLAGS_DISCONNECT; g_thread_new("connect", connect_thread, s); append_mem_opts(s, cmd_line, 256, TEST_MEMFD_AUTO); - append_vhost_opts(s, cmd_line, ",server"); + s->vu_ops->append_opts(s, cmd_line, ",server"); g_test_queue_destroy(vhost_user_test_cleanup, s); @@ -924,11 +935,47 @@ static void test_multiqueue(void *obj, void *arg, QGuestAllocator *alloc) wait_for_rings_started(s, s->queues * 2); } +static void vu_net_set_features(TestServer *s, CharBackend *chr, + VhostUserMsg *msg) +{ + g_assert_cmpint(msg->payload.u64 & + (0x1ULL << VHOST_USER_F_PROTOCOL_FEATURES), !=, 0ULL); + if (s->test_flags == TEST_FLAGS_DISCONNECT) { + qemu_chr_fe_disconnect(chr); + s->test_flags = TEST_FLAGS_BAD; + } +} + +static void vu_net_get_protocol_features(TestServer *s, CharBackend *chr, + VhostUserMsg *msg) +{ + /* send back features to qemu */ + msg->flags |= VHOST_USER_REPLY_MASK; + msg->size = sizeof(m.payload.u64); + msg->payload.u64 = 1 << VHOST_USER_PROTOCOL_F_LOG_SHMFD; + msg->payload.u64 |= 1 << VHOST_USER_PROTOCOL_F_CROSS_ENDIAN; + if (s->queues > 1) { + msg->payload.u64 |= 1 << VHOST_USER_PROTOCOL_F_MQ; + } + qemu_chr_fe_write_all(chr, (uint8_t *)msg, VHOST_USER_HDR_SIZE + msg->size); +} + +/* Each VHOST-USER device should have its ops structure defined. */ +static struct vhost_user_ops g_vu_net_ops = { + .type = VHOST_USER_NET, + + .append_opts = append_vhost_net_opts, + + .set_features = vu_net_set_features, + .get_protocol_features = vu_net_get_protocol_features, +}; + static void register_vhost_user_test(void) { QOSGraphTestOptions opts = { .before = vhost_user_test_setup, .subprocess = true, + .arg = &g_vu_net_ops, }; qemu_add_opts(&qemu_chardev_opts); diff --git a/tests/test-qapi-event.c b/tests/test-qapi-event.c new file mode 100644 index 0000000000..bdeb9095d4 --- /dev/null +++ b/tests/test-qapi-event.c @@ -0,0 +1,198 @@ +/* AUTOMATICALLY GENERATED, DO NOT MODIFY */ + +/* + * schema-defined QAPI event functions + * + * Copyright (c) 2014 Wenchao Xia + * + * Authors: + * Wenchao Xia <wenchaoqemu@gmail.com> + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING.LIB file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "test-qapi-event.h" +#include "test-qapi-visit.h" +#include "qapi/qmp-output-visitor.h" +#include "qapi/qmp-event.h" + + +void qapi_event_send_event_a(Error **errp) +{ + QDict *qmp; + Error *err = NULL; + QMPEventFuncEmit emit; + + emit = qmp_event_get_func_emit(); + if (!emit) { + return; + } + + qmp = qmp_event_build_dict("EVENT_A"); + + emit(TEST_QAPI_EVENT_EVENT_A, qmp, &err); + + error_propagate(errp, err); + QDECREF(qmp); +} + +void qapi_event_send_event_b(Error **errp) +{ + QDict *qmp; + Error *err = NULL; + QMPEventFuncEmit emit; + + emit = qmp_event_get_func_emit(); + if (!emit) { + return; + } + + qmp = qmp_event_build_dict("EVENT_B"); + + emit(TEST_QAPI_EVENT_EVENT_B, qmp, &err); + + error_propagate(errp, err); + QDECREF(qmp); +} + +void qapi_event_send_event_c(bool has_a, int64_t a, bool has_b, UserDefOne *b, const char *c, Error **errp) +{ + QDict *qmp; + Error *err = NULL; + QMPEventFuncEmit emit; + QmpOutputVisitor *qov; + Visitor *v; + q_obj_EVENT_C_arg param = { + has_a, a, has_b, b, (char *)c + }; + + emit = qmp_event_get_func_emit(); + if (!emit) { + return; + } + + qmp = qmp_event_build_dict("EVENT_C"); + + qov = qmp_output_visitor_new(); + v = qmp_output_get_visitor(qov); + + visit_start_struct(v, "EVENT_C", NULL, 0, &err); + if (err) { + goto out; + } + visit_type_q_obj_EVENT_C_arg_members(v, ¶m, &err); + if (!err) { + visit_check_struct(v, &err); + } + visit_end_struct(v); + if (err) { + goto out; + } + + qdict_put_obj(qmp, "data", qmp_output_get_qobject(qov)); + emit(TEST_QAPI_EVENT_EVENT_C, qmp, &err); + +out: + qmp_output_visitor_cleanup(qov); + error_propagate(errp, err); + QDECREF(qmp); +} + +void qapi_event_send_event_d(EventStructOne *a, const char *b, bool has_c, const char *c, bool has_enum3, EnumOne enum3, Error **errp) +{ + QDict *qmp; + Error *err = NULL; + QMPEventFuncEmit emit; + QmpOutputVisitor *qov; + Visitor *v; + q_obj_EVENT_D_arg param = { + a, (char *)b, has_c, (char *)c, has_enum3, enum3 + }; + + emit = qmp_event_get_func_emit(); + if (!emit) { + return; + } + + qmp = qmp_event_build_dict("EVENT_D"); + + qov = qmp_output_visitor_new(); + v = qmp_output_get_visitor(qov); + + visit_start_struct(v, "EVENT_D", NULL, 0, &err); + if (err) { + goto out; + } + visit_type_q_obj_EVENT_D_arg_members(v, ¶m, &err); + if (!err) { + visit_check_struct(v, &err); + } + visit_end_struct(v); + if (err) { + goto out; + } + + qdict_put_obj(qmp, "data", qmp_output_get_qobject(qov)); + emit(TEST_QAPI_EVENT_EVENT_D, qmp, &err); + +out: + qmp_output_visitor_cleanup(qov); + error_propagate(errp, err); + QDECREF(qmp); +} + +void qapi_event_send___org_qemu_x_event(__org_qemu_x_Enum __org_qemu_x_member1, const char *__org_qemu_x_member2, bool has_q_wchar_t, int64_t q_wchar_t, Error **errp) +{ + QDict *qmp; + Error *err = NULL; + QMPEventFuncEmit emit; + QmpOutputVisitor *qov; + Visitor *v; + __org_qemu_x_Struct param = { + __org_qemu_x_member1, (char *)__org_qemu_x_member2, has_q_wchar_t, q_wchar_t + }; + + emit = qmp_event_get_func_emit(); + if (!emit) { + return; + } + + qmp = qmp_event_build_dict("__ORG.QEMU_X-EVENT"); + + qov = qmp_output_visitor_new(); + v = qmp_output_get_visitor(qov); + + visit_start_struct(v, "__ORG.QEMU_X-EVENT", NULL, 0, &err); + if (err) { + goto out; + } + visit_type___org_qemu_x_Struct_members(v, ¶m, &err); + if (!err) { + visit_check_struct(v, &err); + } + visit_end_struct(v); + if (err) { + goto out; + } + + qdict_put_obj(qmp, "data", qmp_output_get_qobject(qov)); + emit(TEST_QAPI_EVENT___ORG_QEMU_X_EVENT, qmp, &err); + +out: + qmp_output_visitor_cleanup(qov); + error_propagate(errp, err); + QDECREF(qmp); +} + +const char *const test_QAPIEvent_lookup[] = { + [TEST_QAPI_EVENT_EVENT_A] = "EVENT_A", + [TEST_QAPI_EVENT_EVENT_B] = "EVENT_B", + [TEST_QAPI_EVENT_EVENT_C] = "EVENT_C", + [TEST_QAPI_EVENT_EVENT_D] = "EVENT_D", + [TEST_QAPI_EVENT___ORG_QEMU_X_EVENT] = "__ORG.QEMU_X-EVENT", + [TEST_QAPI_EVENT__MAX] = NULL, +}; diff --git a/tests/test-qmp-introspect.c b/tests/test-qmp-introspect.c new file mode 100644 index 0000000000..edae06c64e --- /dev/null +++ b/tests/test-qmp-introspect.c @@ -0,0 +1,58 @@ +/* AUTOMATICALLY GENERATED, DO NOT MODIFY */ + +/* + * QAPI/QMP schema introspection + * + * Copyright (C) 2015 Red Hat, Inc. + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING.LIB file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "test-qmp-introspect.h" + +const char test_qmp_schema_json[] = "[" + "{\"arg-type\": \"0\", \"meta-type\": \"event\", \"name\": \"EVENT_A\"}, " + "{\"arg-type\": \"0\", \"meta-type\": \"event\", \"name\": \"EVENT_B\"}, " + "{\"arg-type\": \"1\", \"meta-type\": \"event\", \"name\": \"EVENT_C\"}, " + "{\"arg-type\": \"2\", \"meta-type\": \"event\", \"name\": \"EVENT_D\"}, " + "{\"arg-type\": \"3\", \"meta-type\": \"event\", \"name\": \"__ORG.QEMU_X-EVENT\"}, " + "{\"arg-type\": \"4\", \"meta-type\": \"command\", \"name\": \"__org.qemu_x-command\", \"ret-type\": \"5\"}, " + "{\"arg-type\": \"6\", \"meta-type\": \"command\", \"name\": \"guest-get-time\", \"ret-type\": \"int\"}, " + "{\"arg-type\": \"7\", \"meta-type\": \"command\", \"name\": \"guest-sync\", \"ret-type\": \"any\"}, " + "{\"arg-type\": \"0\", \"meta-type\": \"command\", \"name\": \"user_def_cmd\", \"ret-type\": \"0\"}, " + "{\"arg-type\": \"8\", \"meta-type\": \"command\", \"name\": \"user_def_cmd0\", \"ret-type\": \"8\"}, " + "{\"arg-type\": \"9\", \"meta-type\": \"command\", \"name\": \"user_def_cmd1\", \"ret-type\": \"0\"}, " + "{\"arg-type\": \"10\", \"meta-type\": \"command\", \"name\": \"user_def_cmd2\", \"ret-type\": \"11\"}, " + "{\"members\": [], \"meta-type\": \"object\", \"name\": \"0\"}, " + "{\"members\": [{\"default\": null, \"name\": \"a\", \"type\": \"int\"}, {\"default\": null, \"name\": \"b\", \"type\": \"12\"}, {\"name\": \"c\", \"type\": \"str\"}], \"meta-type\": \"object\", \"name\": \"1\"}, " + "{\"members\": [{\"name\": \"a\", \"type\": \"13\"}, {\"name\": \"b\", \"type\": \"str\"}, {\"default\": null, \"name\": \"c\", \"type\": \"str\"}, {\"default\": null, \"name\": \"enum3\", \"type\": \"14\"}], \"meta-type\": \"object\", \"name\": \"2\"}, " + "{\"members\": [{\"name\": \"__org.qemu_x-member1\", \"type\": \"15\"}, {\"name\": \"__org.qemu_x-member2\", \"type\": \"str\"}, {\"default\": null, \"name\": \"wchar-t\", \"type\": \"int\"}], \"meta-type\": \"object\", \"name\": \"3\"}, " + "{\"members\": [{\"name\": \"a\", \"type\": \"[15]\"}, {\"name\": \"b\", \"type\": \"[3]\"}, {\"name\": \"c\", \"type\": \"16\"}, {\"name\": \"d\", \"type\": \"17\"}], \"meta-type\": \"object\", \"name\": \"4\"}, " + "{\"members\": [{\"name\": \"type\", \"type\": \"18\"}], \"meta-type\": \"object\", \"name\": \"5\", \"tag\": \"type\", \"variants\": [{\"case\": \"__org.qemu_x-branch\", \"type\": \"19\"}]}, " + "{\"members\": [{\"name\": \"a\", \"type\": \"int\"}, {\"default\": null, \"name\": \"b\", \"type\": \"int\"}], \"meta-type\": \"object\", \"name\": \"6\"}, " + "{\"json-type\": \"int\", \"meta-type\": \"builtin\", \"name\": \"int\"}, " + "{\"members\": [{\"name\": \"arg\", \"type\": \"any\"}], \"meta-type\": \"object\", \"name\": \"7\"}, " + "{\"json-type\": \"value\", \"meta-type\": \"builtin\", \"name\": \"any\"}, " + "{\"members\": [], \"meta-type\": \"object\", \"name\": \"8\"}, " + "{\"members\": [{\"name\": \"ud1a\", \"type\": \"12\"}], \"meta-type\": \"object\", \"name\": \"9\"}, " + "{\"members\": [{\"name\": \"ud1a\", \"type\": \"12\"}, {\"default\": null, \"name\": \"ud1b\", \"type\": \"12\"}], \"meta-type\": \"object\", \"name\": \"10\"}, " + "{\"members\": [{\"name\": \"string0\", \"type\": \"str\"}, {\"name\": \"dict1\", \"type\": \"20\"}], \"meta-type\": \"object\", \"name\": \"11\"}, " + "{\"members\": [{\"name\": \"integer\", \"type\": \"int\"}, {\"name\": \"string\", \"type\": \"str\"}, {\"default\": null, \"name\": \"enum1\", \"type\": \"14\"}], \"meta-type\": \"object\", \"name\": \"12\"}, " + "{\"json-type\": \"string\", \"meta-type\": \"builtin\", \"name\": \"str\"}, " + "{\"members\": [{\"name\": \"struct1\", \"type\": \"12\"}, {\"name\": \"string\", \"type\": \"str\"}, {\"default\": null, \"name\": \"enum2\", \"type\": \"14\"}], \"meta-type\": \"object\", \"name\": \"13\"}, " + "{\"meta-type\": \"enum\", \"name\": \"14\", \"values\": [\"value1\", \"value2\", \"value3\"]}, " + "{\"meta-type\": \"enum\", \"name\": \"15\", \"values\": [\"__org.qemu_x-value\"]}, " + "{\"element-type\": \"15\", \"meta-type\": \"array\", \"name\": \"[15]\"}, " + "{\"element-type\": \"3\", \"meta-type\": \"array\", \"name\": \"[3]\"}, " + "{\"members\": [{\"name\": \"__org.qemu_x-member1\", \"type\": \"15\"}], \"meta-type\": \"object\", \"name\": \"16\", \"tag\": \"__org.qemu_x-member1\", \"variants\": [{\"case\": \"__org.qemu_x-value\", \"type\": \"21\"}]}, " + "{\"members\": [{\"type\": \"str\"}, {\"type\": \"22\"}], \"meta-type\": \"alternate\", \"name\": \"17\"}, " + "{\"meta-type\": \"enum\", \"name\": \"18\", \"values\": [\"__org.qemu_x-branch\"]}, " + "{\"members\": [{\"name\": \"data\", \"type\": \"str\"}], \"meta-type\": \"object\", \"name\": \"19\"}, " + "{\"members\": [{\"name\": \"string1\", \"type\": \"str\"}, {\"name\": \"dict2\", \"type\": \"23\"}, {\"default\": null, \"name\": \"dict3\", \"type\": \"23\"}], \"meta-type\": \"object\", \"name\": \"20\"}, " + "{\"members\": [{\"name\": \"array\", \"type\": \"[5]\"}], \"meta-type\": \"object\", \"name\": \"21\"}, " + "{\"members\": [{\"name\": \"__org.qemu_x-member1\", \"type\": \"15\"}], \"meta-type\": \"object\", \"name\": \"22\"}, " + "{\"members\": [{\"name\": \"userdef\", \"type\": \"12\"}, {\"name\": \"string\", \"type\": \"str\"}], \"meta-type\": \"object\", \"name\": \"23\"}, " + "{\"element-type\": \"5\", \"meta-type\": \"array\", \"name\": \"[5]\"}]"; diff --git a/tests/test-qmp-marshal.c b/tests/test-qmp-marshal.c new file mode 100644 index 0000000000..54e3952d35 --- /dev/null +++ b/tests/test-qmp-marshal.c @@ -0,0 +1,383 @@ +/* AUTOMATICALLY GENERATED, DO NOT MODIFY */ + +/* + * schema-defined QMP->QAPI command dispatch + * + * Copyright IBM, Corp. 2011 + * + * Authors: + * Anthony Liguori <aliguori@us.ibm.com> + * + * This work is licensed under the terms of the GNU LGPL, version 2.1 or later. + * See the COPYING.LIB file in the top-level directory. + * + */ + +#include "qemu/osdep.h" +#include "qemu-common.h" +#include "qemu/module.h" +#include "qapi/qmp/types.h" +#include "qapi/qmp/dispatch.h" +#include "qapi/visitor.h" +#include "qapi/qmp-output-visitor.h" +#include "qapi/qmp-input-visitor.h" +#include "qapi/dealloc-visitor.h" +#include "test-qapi-types.h" +#include "test-qapi-visit.h" +#include "test-qmp-commands.h" + + +static void qmp_marshal_output___org_qemu_x_Union1(__org_qemu_x_Union1 *ret_in, QObject **ret_out, Error **errp) +{ + Error *err = NULL; + QmpOutputVisitor *qov = qmp_output_visitor_new(); + QapiDeallocVisitor *qdv; + Visitor *v; + + v = qmp_output_get_visitor(qov); + visit_type___org_qemu_x_Union1(v, "unused", &ret_in, &err); + if (err) { + goto out; + } + *ret_out = qmp_output_get_qobject(qov); + +out: + error_propagate(errp, err); + qmp_output_visitor_cleanup(qov); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_type___org_qemu_x_Union1(v, "unused", &ret_in, NULL); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_marshal___org_qemu_x_command(QDict *args, QObject **ret, Error **errp) +{ + Error *err = NULL; + __org_qemu_x_Union1 *retval; + QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true); + QapiDeallocVisitor *qdv; + Visitor *v; + q_obj___org_qemu_x_command_arg arg = {0}; + + v = qmp_input_get_visitor(qiv); + visit_start_struct(v, NULL, NULL, 0, &err); + if (err) { + goto out; + } + visit_type_q_obj___org_qemu_x_command_arg_members(v, &arg, &err); + if (!err) { + visit_check_struct(v, &err); + } + visit_end_struct(v); + if (err) { + goto out; + } + + retval = qmp___org_qemu_x_command(arg.a, arg.b, arg.c, arg.d, &err); + if (err) { + goto out; + } + + qmp_marshal_output___org_qemu_x_Union1(retval, ret, &err); + +out: + error_propagate(errp, err); + qmp_input_visitor_cleanup(qiv); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_start_struct(v, NULL, NULL, 0, NULL); + visit_type_q_obj___org_qemu_x_command_arg_members(v, &arg, NULL); + visit_end_struct(v); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_marshal_output_int(int64_t ret_in, QObject **ret_out, Error **errp) +{ + Error *err = NULL; + QmpOutputVisitor *qov = qmp_output_visitor_new(); + QapiDeallocVisitor *qdv; + Visitor *v; + + v = qmp_output_get_visitor(qov); + visit_type_int(v, "unused", &ret_in, &err); + if (err) { + goto out; + } + *ret_out = qmp_output_get_qobject(qov); + +out: + error_propagate(errp, err); + qmp_output_visitor_cleanup(qov); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_type_int(v, "unused", &ret_in, NULL); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_marshal_guest_get_time(QDict *args, QObject **ret, Error **errp) +{ + Error *err = NULL; + int64_t retval; + QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true); + QapiDeallocVisitor *qdv; + Visitor *v; + q_obj_guest_get_time_arg arg = {0}; + + v = qmp_input_get_visitor(qiv); + visit_start_struct(v, NULL, NULL, 0, &err); + if (err) { + goto out; + } + visit_type_q_obj_guest_get_time_arg_members(v, &arg, &err); + if (!err) { + visit_check_struct(v, &err); + } + visit_end_struct(v); + if (err) { + goto out; + } + + retval = qmp_guest_get_time(arg.a, arg.has_b, arg.b, &err); + if (err) { + goto out; + } + + qmp_marshal_output_int(retval, ret, &err); + +out: + error_propagate(errp, err); + qmp_input_visitor_cleanup(qiv); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_start_struct(v, NULL, NULL, 0, NULL); + visit_type_q_obj_guest_get_time_arg_members(v, &arg, NULL); + visit_end_struct(v); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_marshal_output_any(QObject *ret_in, QObject **ret_out, Error **errp) +{ + Error *err = NULL; + QmpOutputVisitor *qov = qmp_output_visitor_new(); + QapiDeallocVisitor *qdv; + Visitor *v; + + v = qmp_output_get_visitor(qov); + visit_type_any(v, "unused", &ret_in, &err); + if (err) { + goto out; + } + *ret_out = qmp_output_get_qobject(qov); + +out: + error_propagate(errp, err); + qmp_output_visitor_cleanup(qov); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_type_any(v, "unused", &ret_in, NULL); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_marshal_guest_sync(QDict *args, QObject **ret, Error **errp) +{ + Error *err = NULL; + QObject *retval; + QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true); + QapiDeallocVisitor *qdv; + Visitor *v; + q_obj_guest_sync_arg arg = {0}; + + v = qmp_input_get_visitor(qiv); + visit_start_struct(v, NULL, NULL, 0, &err); + if (err) { + goto out; + } + visit_type_q_obj_guest_sync_arg_members(v, &arg, &err); + if (!err) { + visit_check_struct(v, &err); + } + visit_end_struct(v); + if (err) { + goto out; + } + + retval = qmp_guest_sync(arg.arg, &err); + if (err) { + goto out; + } + + qmp_marshal_output_any(retval, ret, &err); + +out: + error_propagate(errp, err); + qmp_input_visitor_cleanup(qiv); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_start_struct(v, NULL, NULL, 0, NULL); + visit_type_q_obj_guest_sync_arg_members(v, &arg, NULL); + visit_end_struct(v); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_marshal_user_def_cmd(QDict *args, QObject **ret, Error **errp) +{ + Error *err = NULL; + + (void)args; + + qmp_user_def_cmd(&err); + error_propagate(errp, err); +} + +static void qmp_marshal_output_Empty2(Empty2 *ret_in, QObject **ret_out, Error **errp) +{ + Error *err = NULL; + QmpOutputVisitor *qov = qmp_output_visitor_new(); + QapiDeallocVisitor *qdv; + Visitor *v; + + v = qmp_output_get_visitor(qov); + visit_type_Empty2(v, "unused", &ret_in, &err); + if (err) { + goto out; + } + *ret_out = qmp_output_get_qobject(qov); + +out: + error_propagate(errp, err); + qmp_output_visitor_cleanup(qov); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_type_Empty2(v, "unused", &ret_in, NULL); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_marshal_user_def_cmd0(QDict *args, QObject **ret, Error **errp) +{ + Error *err = NULL; + Empty2 *retval; + + (void)args; + + retval = qmp_user_def_cmd0(&err); + if (err) { + goto out; + } + + qmp_marshal_output_Empty2(retval, ret, &err); + +out: + error_propagate(errp, err); +} + +static void qmp_marshal_user_def_cmd1(QDict *args, QObject **ret, Error **errp) +{ + Error *err = NULL; + QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true); + QapiDeallocVisitor *qdv; + Visitor *v; + q_obj_user_def_cmd1_arg arg = {0}; + + v = qmp_input_get_visitor(qiv); + visit_start_struct(v, NULL, NULL, 0, &err); + if (err) { + goto out; + } + visit_type_q_obj_user_def_cmd1_arg_members(v, &arg, &err); + if (!err) { + visit_check_struct(v, &err); + } + visit_end_struct(v); + if (err) { + goto out; + } + + qmp_user_def_cmd1(arg.ud1a, &err); + +out: + error_propagate(errp, err); + qmp_input_visitor_cleanup(qiv); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_start_struct(v, NULL, NULL, 0, NULL); + visit_type_q_obj_user_def_cmd1_arg_members(v, &arg, NULL); + visit_end_struct(v); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_marshal_output_UserDefTwo(UserDefTwo *ret_in, QObject **ret_out, Error **errp) +{ + Error *err = NULL; + QmpOutputVisitor *qov = qmp_output_visitor_new(); + QapiDeallocVisitor *qdv; + Visitor *v; + + v = qmp_output_get_visitor(qov); + visit_type_UserDefTwo(v, "unused", &ret_in, &err); + if (err) { + goto out; + } + *ret_out = qmp_output_get_qobject(qov); + +out: + error_propagate(errp, err); + qmp_output_visitor_cleanup(qov); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_type_UserDefTwo(v, "unused", &ret_in, NULL); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_marshal_user_def_cmd2(QDict *args, QObject **ret, Error **errp) +{ + Error *err = NULL; + UserDefTwo *retval; + QmpInputVisitor *qiv = qmp_input_visitor_new(QOBJECT(args), true); + QapiDeallocVisitor *qdv; + Visitor *v; + q_obj_user_def_cmd2_arg arg = {0}; + + v = qmp_input_get_visitor(qiv); + visit_start_struct(v, NULL, NULL, 0, &err); + if (err) { + goto out; + } + visit_type_q_obj_user_def_cmd2_arg_members(v, &arg, &err); + if (!err) { + visit_check_struct(v, &err); + } + visit_end_struct(v); + if (err) { + goto out; + } + + retval = qmp_user_def_cmd2(arg.ud1a, arg.has_ud1b, arg.ud1b, &err); + if (err) { + goto out; + } + + qmp_marshal_output_UserDefTwo(retval, ret, &err); + +out: + error_propagate(errp, err); + qmp_input_visitor_cleanup(qiv); + qdv = qapi_dealloc_visitor_new(); + v = qapi_dealloc_get_visitor(qdv); + visit_start_struct(v, NULL, NULL, 0, NULL); + visit_type_q_obj_user_def_cmd2_arg_members(v, &arg, NULL); + visit_end_struct(v); + qapi_dealloc_visitor_cleanup(qdv); +} + +static void qmp_init_marshal(void) +{ + qmp_register_command("__org.qemu_x-command", qmp_marshal___org_qemu_x_command, QCO_NO_OPTIONS); + qmp_register_command("guest-get-time", qmp_marshal_guest_get_time, QCO_NO_OPTIONS); + qmp_register_command("guest-sync", qmp_marshal_guest_sync, QCO_NO_OPTIONS); + qmp_register_command("user_def_cmd", qmp_marshal_user_def_cmd, QCO_NO_OPTIONS); + qmp_register_command("user_def_cmd0", qmp_marshal_user_def_cmd0, QCO_NO_OPTIONS); + qmp_register_command("user_def_cmd1", qmp_marshal_user_def_cmd1, QCO_NO_OPTIONS); + qmp_register_command("user_def_cmd2", qmp_marshal_user_def_cmd2, QCO_NO_OPTIONS); +} + +qapi_init(qmp_init_marshal); diff --git a/tests/vhost-user-bridge b/tests/vhost-user-bridge new file mode 100755 index 0000000000..36d1ece0dc --- /dev/null +++ b/tests/vhost-user-bridge Binary files differdiff --git a/tests/vhost-user-bridge.c.orig b/tests/vhost-user-bridge.c.orig new file mode 100644 index 0000000000..f907ce741f --- /dev/null +++ b/tests/vhost-user-bridge.c.orig @@ -0,0 +1,1432 @@ +/* + * Vhost User Bridge + * + * Copyright (c) 2015 Red Hat, Inc. + * + * Authors: + * Victor Kaplansky <victork@redhat.com> + * + * This work is licensed under the terms of the GNU GPL, version 2 or + * later. See the COPYING file in the top-level directory. + */ + +/* + * TODO: + * - main should get parameters from the command line. + * - implement all request handlers. Still not implemented: + * vubr_get_queue_num_exec() + * vubr_send_rarp_exec() + * - test for broken requests and virtqueue. + * - implement features defined by Virtio 1.0 spec. + * - support mergeable buffers and indirect descriptors. + * - implement clean shutdown. + * - implement non-blocking writes to UDP backend. + * - implement polling strategy. + * - implement clean starting/stopping of vq processing + * - implement clean starting/stopping of used and buffers + * dirty page logging. + */ + +#define _FILE_OFFSET_BITS 64 + +#include "qemu/osdep.h" +#include <sys/socket.h> +#include <sys/un.h> +#include <sys/unistd.h> +#include <sys/mman.h> +#include <sys/eventfd.h> +#include <arpa/inet.h> +#include <netdb.h> +#include <qemu/osdep.h> + +#include <linux/vhost.h> + +#include "qemu/atomic.h" +#include "standard-headers/linux/virtio_net.h" +#include "standard-headers/linux/virtio_ring.h" + +#define VHOST_USER_BRIDGE_DEBUG 1 + +#define DPRINT(...) \ + do { \ + if (VHOST_USER_BRIDGE_DEBUG) { \ + printf(__VA_ARGS__); \ + } \ + } while (0) + +typedef void (*CallbackFunc)(int sock, void *ctx); + +typedef struct Event { + void *ctx; + CallbackFunc callback; +} Event; + +typedef struct Dispatcher { + int max_sock; + fd_set fdset; + Event events[FD_SETSIZE]; +} Dispatcher; + +static void +vubr_die(const char *s) +{ + perror(s); + exit(1); +} + +static int +dispatcher_init(Dispatcher *dispr) +{ + FD_ZERO(&dispr->fdset); + dispr->max_sock = -1; + return 0; +} + +static int +dispatcher_add(Dispatcher *dispr, int sock, void *ctx, CallbackFunc cb) +{ + if (sock >= FD_SETSIZE) { + fprintf(stderr, + "Error: Failed to add new event. sock %d should be less than %d\n", + sock, FD_SETSIZE); + return -1; + } + + dispr->events[sock].ctx = ctx; + dispr->events[sock].callback = cb; + + FD_SET(sock, &dispr->fdset); + if (sock > dispr->max_sock) { + dispr->max_sock = sock; + } + DPRINT("Added sock %d for watching. max_sock: %d\n", + sock, dispr->max_sock); + return 0; +} + +/* dispatcher_remove() is not currently in use but may be useful + * in the future. */ +static int +dispatcher_remove(Dispatcher *dispr, int sock) +{ + if (sock >= FD_SETSIZE) { + fprintf(stderr, + "Error: Failed to remove event. sock %d should be less than %d\n", + sock, FD_SETSIZE); + return -1; + } + + FD_CLR(sock, &dispr->fdset); + DPRINT("Sock %d removed from dispatcher watch.\n", sock); + return 0; +} + +/* timeout in us */ +static int +dispatcher_wait(Dispatcher *dispr, uint32_t timeout) +{ + struct timeval tv; + tv.tv_sec = timeout / 1000000; + tv.tv_usec = timeout % 1000000; + + fd_set fdset = dispr->fdset; + + /* wait until some of sockets become readable. */ + int rc = select(dispr->max_sock + 1, &fdset, 0, 0, &tv); + + if (rc == -1) { + vubr_die("select"); + } + + /* Timeout */ + if (rc == 0) { + return 0; + } + + /* Now call callback for every ready socket. */ + + int sock; + for (sock = 0; sock < dispr->max_sock + 1; sock++) { + /* The callback on a socket can remove other sockets from the + * dispatcher, thus we have to check that the socket is + * still not removed from dispatcher's list + */ + if (FD_ISSET(sock, &fdset) && FD_ISSET(sock, &dispr->fdset)) { + Event *e = &dispr->events[sock]; + e->callback(sock, e->ctx); + } + } + + return 0; +} + +typedef struct VubrVirtq { + int call_fd; + int kick_fd; + uint32_t size; + uint16_t last_avail_index; + uint16_t last_used_index; + struct vring_desc *desc; + struct vring_avail *avail; + struct vring_used *used; + uint64_t log_guest_addr; + int enable; +} VubrVirtq; + +/* Based on qemu/hw/virtio/vhost-user.c */ + +#define VHOST_MEMORY_MAX_NREGIONS 8 +#define VHOST_USER_F_PROTOCOL_FEATURES 30 +/* v1.0 compliant. */ +#define VIRTIO_F_VERSION_1 32 + +#define VHOST_LOG_PAGE 4096 + +enum VhostUserProtocolFeature { + VHOST_USER_PROTOCOL_F_MQ = 0, + VHOST_USER_PROTOCOL_F_LOG_SHMFD = 1, + VHOST_USER_PROTOCOL_F_RARP = 2, + + VHOST_USER_PROTOCOL_F_MAX +}; + +#define VHOST_USER_PROTOCOL_FEATURE_MASK ((1 << VHOST_USER_PROTOCOL_F_MAX) - 1) + +typedef enum VhostUserRequest { + VHOST_USER_NONE = 0, + VHOST_USER_GET_FEATURES = 1, + VHOST_USER_SET_FEATURES = 2, + VHOST_USER_SET_OWNER = 3, + VHOST_USER_RESET_OWNER = 4, + VHOST_USER_SET_MEM_TABLE = 5, + VHOST_USER_SET_LOG_BASE = 6, + VHOST_USER_SET_LOG_FD = 7, + VHOST_USER_SET_VRING_NUM = 8, + VHOST_USER_SET_VRING_ADDR = 9, + VHOST_USER_SET_VRING_BASE = 10, + VHOST_USER_GET_VRING_BASE = 11, + VHOST_USER_SET_VRING_KICK = 12, + VHOST_USER_SET_VRING_CALL = 13, + VHOST_USER_SET_VRING_ERR = 14, + VHOST_USER_GET_PROTOCOL_FEATURES = 15, + VHOST_USER_SET_PROTOCOL_FEATURES = 16, + VHOST_USER_GET_QUEUE_NUM = 17, + VHOST_USER_SET_VRING_ENABLE = 18, + VHOST_USER_SEND_RARP = 19, + VHOST_USER_MAX +} VhostUserRequest; + +typedef struct VhostUserMemoryRegion { + uint64_t guest_phys_addr; + uint64_t memory_size; + uint64_t userspace_addr; + uint64_t mmap_offset; +} VhostUserMemoryRegion; + +typedef struct VhostUserMemory { + uint32_t nregions; + uint32_t padding; + VhostUserMemoryRegion regions[VHOST_MEMORY_MAX_NREGIONS]; +} VhostUserMemory; + +typedef struct VhostUserLog { + uint64_t mmap_size; + uint64_t mmap_offset; +} VhostUserLog; + +typedef struct VhostUserMsg { + VhostUserRequest request; + +#define VHOST_USER_VERSION_MASK (0x3) +#define VHOST_USER_REPLY_MASK (0x1<<2) + uint32_t flags; + uint32_t size; /* the following payload size */ + union { +#define VHOST_USER_VRING_IDX_MASK (0xff) +#define VHOST_USER_VRING_NOFD_MASK (0x1<<8) + uint64_t u64; + struct vhost_vring_state state; + struct vhost_vring_addr addr; + VhostUserMemory memory; + VhostUserLog log; + } payload; + int fds[VHOST_MEMORY_MAX_NREGIONS]; + int fd_num; +} QEMU_PACKED VhostUserMsg; + +#define VHOST_USER_HDR_SIZE offsetof(VhostUserMsg, payload.u64) + +/* The version of the protocol we support */ +#define VHOST_USER_VERSION (0x1) + +#define MAX_NR_VIRTQUEUE (8) + +typedef struct VubrDevRegion { + /* Guest Physical address. */ + uint64_t gpa; + /* Memory region size. */ + uint64_t size; + /* QEMU virtual address (userspace). */ + uint64_t qva; + /* Starting offset in our mmaped space. */ + uint64_t mmap_offset; + /* Start address of mmaped space. */ + uint64_t mmap_addr; +} VubrDevRegion; + +typedef struct VubrDev { + int sock; + Dispatcher dispatcher; + uint32_t nregions; + VubrDevRegion regions[VHOST_MEMORY_MAX_NREGIONS]; + VubrVirtq vq[MAX_NR_VIRTQUEUE]; + int log_call_fd; + uint64_t log_size; + uint8_t *log_table; + int backend_udp_sock; + struct sockaddr_in backend_udp_dest; + int ready; + uint64_t features; + int hdrlen; +} VubrDev; + +static const char *vubr_request_str[] = { + [VHOST_USER_NONE] = "VHOST_USER_NONE", + [VHOST_USER_GET_FEATURES] = "VHOST_USER_GET_FEATURES", + [VHOST_USER_SET_FEATURES] = "VHOST_USER_SET_FEATURES", + [VHOST_USER_SET_OWNER] = "VHOST_USER_SET_OWNER", + [VHOST_USER_RESET_OWNER] = "VHOST_USER_RESET_OWNER", + [VHOST_USER_SET_MEM_TABLE] = "VHOST_USER_SET_MEM_TABLE", + [VHOST_USER_SET_LOG_BASE] = "VHOST_USER_SET_LOG_BASE", + [VHOST_USER_SET_LOG_FD] = "VHOST_USER_SET_LOG_FD", + [VHOST_USER_SET_VRING_NUM] = "VHOST_USER_SET_VRING_NUM", + [VHOST_USER_SET_VRING_ADDR] = "VHOST_USER_SET_VRING_ADDR", + [VHOST_USER_SET_VRING_BASE] = "VHOST_USER_SET_VRING_BASE", + [VHOST_USER_GET_VRING_BASE] = "VHOST_USER_GET_VRING_BASE", + [VHOST_USER_SET_VRING_KICK] = "VHOST_USER_SET_VRING_KICK", + [VHOST_USER_SET_VRING_CALL] = "VHOST_USER_SET_VRING_CALL", + [VHOST_USER_SET_VRING_ERR] = "VHOST_USER_SET_VRING_ERR", + [VHOST_USER_GET_PROTOCOL_FEATURES] = "VHOST_USER_GET_PROTOCOL_FEATURES", + [VHOST_USER_SET_PROTOCOL_FEATURES] = "VHOST_USER_SET_PROTOCOL_FEATURES", + [VHOST_USER_GET_QUEUE_NUM] = "VHOST_USER_GET_QUEUE_NUM", + [VHOST_USER_SET_VRING_ENABLE] = "VHOST_USER_SET_VRING_ENABLE", + [VHOST_USER_SEND_RARP] = "VHOST_USER_SEND_RARP", + [VHOST_USER_MAX] = "VHOST_USER_MAX", +}; + +static void +print_buffer(uint8_t *buf, size_t len) +{ + int i; + printf("Raw buffer:\n"); + for (i = 0; i < len; i++) { + if (i % 16 == 0) { + printf("\n"); + } + if (i % 4 == 0) { + printf(" "); + } + printf("%02x ", buf[i]); + } + printf("\n............................................................\n"); +} + +/* Translate guest physical address to our virtual address. */ +static uint64_t +gpa_to_va(VubrDev *dev, uint64_t guest_addr) +{ + int i; + + /* Find matching memory region. */ + for (i = 0; i < dev->nregions; i++) { + VubrDevRegion *r = &dev->regions[i]; + + if ((guest_addr >= r->gpa) && (guest_addr < (r->gpa + r->size))) { + return guest_addr - r->gpa + r->mmap_addr + r->mmap_offset; + } + } + + assert(!"address not found in regions"); + return 0; +} + +/* Translate qemu virtual address to our virtual address. */ +static uint64_t +qva_to_va(VubrDev *dev, uint64_t qemu_addr) +{ + int i; + + /* Find matching memory region. */ + for (i = 0; i < dev->nregions; i++) { + VubrDevRegion *r = &dev->regions[i]; + + if ((qemu_addr >= r->qva) && (qemu_addr < (r->qva + r->size))) { + return qemu_addr - r->qva + r->mmap_addr + r->mmap_offset; + } + } + + assert(!"address not found in regions"); + return 0; +} + +static void +vubr_message_read(int conn_fd, VhostUserMsg *vmsg) +{ + char control[CMSG_SPACE(VHOST_MEMORY_MAX_NREGIONS * sizeof(int))] = { }; + struct iovec iov = { + .iov_base = (char *)vmsg, + .iov_len = VHOST_USER_HDR_SIZE, + }; + struct msghdr msg = { + .msg_iov = &iov, + .msg_iovlen = 1, + .msg_control = control, + .msg_controllen = sizeof(control), + }; + size_t fd_size; + struct cmsghdr *cmsg; + int rc; + + rc = recvmsg(conn_fd, &msg, 0); + + if (rc == 0) { + vubr_die("recvmsg"); + fprintf(stderr, "Peer disconnected.\n"); + exit(1); + } + if (rc < 0) { + vubr_die("recvmsg"); + } + + vmsg->fd_num = 0; + for (cmsg = CMSG_FIRSTHDR(&msg); + cmsg != NULL; + cmsg = CMSG_NXTHDR(&msg, cmsg)) + { + if (cmsg->cmsg_level == SOL_SOCKET && cmsg->cmsg_type == SCM_RIGHTS) { + fd_size = cmsg->cmsg_len - CMSG_LEN(0); + vmsg->fd_num = fd_size / sizeof(int); + memcpy(vmsg->fds, CMSG_DATA(cmsg), fd_size); + break; + } + } + + if (vmsg->size > sizeof(vmsg->payload)) { + fprintf(stderr, + "Error: too big message request: %d, size: vmsg->size: %u, " + "while sizeof(vmsg->payload) = %zu\n", + vmsg->request, vmsg->size, sizeof(vmsg->payload)); + exit(1); + } + + if (vmsg->size) { + rc = read(conn_fd, &vmsg->payload, vmsg->size); + if (rc == 0) { + vubr_die("recvmsg"); + fprintf(stderr, "Peer disconnected.\n"); + exit(1); + } + if (rc < 0) { + vubr_die("recvmsg"); + } + + assert(rc == vmsg->size); + } +} + +static void +vubr_message_write(int conn_fd, VhostUserMsg *vmsg) +{ + int rc; + + do { + rc = write(conn_fd, vmsg, VHOST_USER_HDR_SIZE + vmsg->size); + } while (rc < 0 && errno == EINTR); + + if (rc < 0) { + vubr_die("write"); + } +} + +static void +vubr_backend_udp_sendbuf(VubrDev *dev, uint8_t *buf, size_t len) +{ + int slen = sizeof(struct sockaddr_in); + + if (sendto(dev->backend_udp_sock, buf, len, 0, + (struct sockaddr *) &dev->backend_udp_dest, slen) == -1) { + vubr_die("sendto()"); + } +} + +static int +vubr_backend_udp_recvbuf(VubrDev *dev, uint8_t *buf, size_t buflen) +{ + int slen = sizeof(struct sockaddr_in); + int rc; + + rc = recvfrom(dev->backend_udp_sock, buf, buflen, 0, + (struct sockaddr *) &dev->backend_udp_dest, + (socklen_t *)&slen); + if (rc == -1) { + vubr_die("recvfrom()"); + } + + return rc; +} + +static void +vubr_consume_raw_packet(VubrDev *dev, uint8_t *buf, uint32_t len) +{ + int hdrlen = dev->hdrlen; + DPRINT(" hdrlen = %d\n", dev->hdrlen); + + if (VHOST_USER_BRIDGE_DEBUG) { + print_buffer(buf, len); + } + vubr_backend_udp_sendbuf(dev, buf + hdrlen, len - hdrlen); +} + +/* Kick the log_call_fd if required. */ +static void +vubr_log_kick(VubrDev *dev) +{ + if (dev->log_call_fd != -1) { + DPRINT("Kicking the QEMU's log...\n"); + eventfd_write(dev->log_call_fd, 1); + } +} + +/* Kick the guest if necessary. */ +static void +vubr_virtqueue_kick(VubrVirtq *vq) +{ + if (!(vq->avail->flags & VRING_AVAIL_F_NO_INTERRUPT)) { + DPRINT("Kicking the guest...\n"); + eventfd_write(vq->call_fd, 1); + } +} + +static void +vubr_log_page(uint8_t *log_table, uint64_t page) +{ + DPRINT("Logged dirty guest page: %"PRId64"\n", page); + atomic_or(&log_table[page / 8], 1 << (page % 8)); +} + +static void +vubr_log_write(VubrDev *dev, uint64_t address, uint64_t length) +{ + uint64_t page; + + if (!(dev->features & (1ULL << VHOST_F_LOG_ALL)) || + !dev->log_table || !length) { + return; + } + + assert(dev->log_size > ((address + length - 1) / VHOST_LOG_PAGE / 8)); + + page = address / VHOST_LOG_PAGE; + while (page * VHOST_LOG_PAGE < address + length) { + vubr_log_page(dev->log_table, page); + page += VHOST_LOG_PAGE; + } + vubr_log_kick(dev); +} + +static void +vubr_post_buffer(VubrDev *dev, VubrVirtq *vq, uint8_t *buf, int32_t len) +{ + struct vring_desc *desc = vq->desc; + struct vring_avail *avail = vq->avail; + struct vring_used *used = vq->used; + uint64_t log_guest_addr = vq->log_guest_addr; + int32_t remaining_len = len; + + unsigned int size = vq->size; + + uint16_t avail_index = atomic_mb_read(&avail->idx); + + /* We check the available descriptors before posting the + * buffer, so here we assume that enough available + * descriptors. */ + assert(vq->last_avail_index != avail_index); + uint16_t a_index = vq->last_avail_index % size; + uint16_t u_index = vq->last_used_index % size; + uint16_t d_index = avail->ring[a_index]; + + int i = d_index; + uint32_t written_len = 0; + + do { + DPRINT("Post packet to guest on vq:\n"); + DPRINT(" size = %d\n", vq->size); + DPRINT(" last_avail_index = %d\n", vq->last_avail_index); + DPRINT(" last_used_index = %d\n", vq->last_used_index); + DPRINT(" a_index = %d\n", a_index); + DPRINT(" u_index = %d\n", u_index); + DPRINT(" d_index = %d\n", d_index); + DPRINT(" desc[%d].addr = 0x%016"PRIx64"\n", i, desc[i].addr); + DPRINT(" desc[%d].len = %d\n", i, desc[i].len); + DPRINT(" desc[%d].flags = %d\n", i, desc[i].flags); + DPRINT(" avail->idx = %d\n", avail_index); + DPRINT(" used->idx = %d\n", used->idx); + + if (!(desc[i].flags & VRING_DESC_F_WRITE)) { + /* FIXME: we should find writable descriptor. */ + fprintf(stderr, "Error: descriptor is not writable. Exiting.\n"); + exit(1); + } + + void *chunk_start = (void *)(uintptr_t)gpa_to_va(dev, desc[i].addr); + uint32_t chunk_len = desc[i].len; + uint32_t chunk_write_len = MIN(remaining_len, chunk_len); + + memcpy(chunk_start, buf + written_len, chunk_write_len); + vubr_log_write(dev, desc[i].addr, chunk_write_len); + remaining_len -= chunk_write_len; + written_len += chunk_write_len; + + if ((remaining_len == 0) || !(desc[i].flags & VRING_DESC_F_NEXT)) { + break; + } + + i = desc[i].next; + } while (1); + + if (remaining_len > 0) { + fprintf(stderr, + "Too long packet for RX, remaining_len = %d, Dropping...\n", + remaining_len); + return; + } + + /* Add descriptor to the used ring. */ + used->ring[u_index].id = d_index; + used->ring[u_index].len = len; + vubr_log_write(dev, + log_guest_addr + offsetof(struct vring_used, ring[u_index]), + sizeof(used->ring[u_index])); + + vq->last_avail_index++; + vq->last_used_index++; + + atomic_mb_set(&used->idx, vq->last_used_index); + vubr_log_write(dev, + log_guest_addr + offsetof(struct vring_used, idx), + sizeof(used->idx)); + + /* Kick the guest if necessary. */ + vubr_virtqueue_kick(vq); +} + +static int +vubr_process_desc(VubrDev *dev, VubrVirtq *vq) +{ + struct vring_desc *desc = vq->desc; + struct vring_avail *avail = vq->avail; + struct vring_used *used = vq->used; + uint64_t log_guest_addr = vq->log_guest_addr; + + unsigned int size = vq->size; + + uint16_t a_index = vq->last_avail_index % size; + uint16_t u_index = vq->last_used_index % size; + uint16_t d_index = avail->ring[a_index]; + + uint32_t i, len = 0; + size_t buf_size = 4096; + uint8_t buf[4096]; + + DPRINT("Chunks: "); + i = d_index; + do { + void *chunk_start = (void *)(uintptr_t)gpa_to_va(dev, desc[i].addr); + uint32_t chunk_len = desc[i].len; + + assert(!(desc[i].flags & VRING_DESC_F_WRITE)); + + if (len + chunk_len < buf_size) { + memcpy(buf + len, chunk_start, chunk_len); + DPRINT("%d ", chunk_len); + } else { + fprintf(stderr, "Error: too long packet. Dropping...\n"); + break; + } + + len += chunk_len; + + if (!(desc[i].flags & VRING_DESC_F_NEXT)) { + break; + } + + i = desc[i].next; + } while (1); + DPRINT("\n"); + + if (!len) { + return -1; + } + + /* Add descriptor to the used ring. */ + used->ring[u_index].id = d_index; + used->ring[u_index].len = len; + vubr_log_write(dev, + log_guest_addr + offsetof(struct vring_used, ring[u_index]), + sizeof(used->ring[u_index])); + + vubr_consume_raw_packet(dev, buf, len); + + return 0; +} + +static void +vubr_process_avail(VubrDev *dev, VubrVirtq *vq) +{ + struct vring_avail *avail = vq->avail; + struct vring_used *used = vq->used; + uint64_t log_guest_addr = vq->log_guest_addr; + + while (vq->last_avail_index != atomic_mb_read(&avail->idx)) { + vubr_process_desc(dev, vq); + vq->last_avail_index++; + vq->last_used_index++; + } + + atomic_mb_set(&used->idx, vq->last_used_index); + vubr_log_write(dev, + log_guest_addr + offsetof(struct vring_used, idx), + sizeof(used->idx)); +} + +static void +vubr_backend_recv_cb(int sock, void *ctx) +{ + VubrDev *dev = (VubrDev *) ctx; + VubrVirtq *rx_vq = &dev->vq[0]; + uint8_t buf[4096]; + struct virtio_net_hdr_v1 *hdr = (struct virtio_net_hdr_v1 *)buf; + int hdrlen = dev->hdrlen; + int buflen = sizeof(buf); + int len; + + if (!dev->ready) { + return; + } + + DPRINT("\n\n *** IN UDP RECEIVE CALLBACK ***\n\n"); + DPRINT(" hdrlen = %d\n", hdrlen); + + uint16_t avail_index = atomic_mb_read(&rx_vq->avail->idx); + + /* If there is no available descriptors, just do nothing. + * The buffer will be handled by next arrived UDP packet, + * or next kick on receive virtq. */ + if (rx_vq->last_avail_index == avail_index) { + DPRINT("Got UDP packet, but no available descriptors on RX virtq.\n"); + return; + } + + memset(buf, 0, hdrlen); + /* TODO: support mergeable buffers. */ + if (hdrlen == 12) + hdr->num_buffers = 1; + len = vubr_backend_udp_recvbuf(dev, buf + hdrlen, buflen - hdrlen); + + vubr_post_buffer(dev, rx_vq, buf, len + hdrlen); +} + +static void +vubr_kick_cb(int sock, void *ctx) +{ + VubrDev *dev = (VubrDev *) ctx; + eventfd_t kick_data; + ssize_t rc; + + rc = eventfd_read(sock, &kick_data); + if (rc == -1) { + vubr_die("eventfd_read()"); + } else { + DPRINT("Got kick_data: %016"PRIx64"\n", kick_data); + vubr_process_avail(dev, &dev->vq[1]); + } +} + +static int +vubr_none_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + DPRINT("Function %s() not implemented yet.\n", __func__); + return 0; +} + +static int +vubr_get_features_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + vmsg->payload.u64 = + ((1ULL << VIRTIO_NET_F_MRG_RXBUF) | + (1ULL << VHOST_F_LOG_ALL) | + (1ULL << VIRTIO_NET_F_GUEST_ANNOUNCE) | + (1ULL << VHOST_USER_F_PROTOCOL_FEATURES)); + + vmsg->size = sizeof(vmsg->payload.u64); + + DPRINT("Sending back to guest u64: 0x%016"PRIx64"\n", vmsg->payload.u64); + + /* Reply */ + return 1; +} + +static int +vubr_set_features_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64); + + dev->features = vmsg->payload.u64; + if ((dev->features & (1ULL << VIRTIO_F_VERSION_1)) || + (dev->features & (1ULL << VIRTIO_NET_F_MRG_RXBUF))) { + dev->hdrlen = 12; + } else { + dev->hdrlen = 10; + } + + return 0; +} + +static int +vubr_set_owner_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + return 0; +} + +static void +vubr_close_log(VubrDev *dev) +{ + if (dev->log_table) { + if (munmap(dev->log_table, dev->log_size) != 0) { + vubr_die("munmap()"); + } + + dev->log_table = 0; + } + if (dev->log_call_fd != -1) { + close(dev->log_call_fd); + dev->log_call_fd = -1; + } +} + +static int +vubr_reset_device_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + vubr_close_log(dev); + dev->ready = 0; + dev->features = 0; + return 0; +} + +static int +vubr_set_mem_table_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + int i; + VhostUserMemory *memory = &vmsg->payload.memory; + dev->nregions = memory->nregions; + + DPRINT("Nregions: %d\n", memory->nregions); + for (i = 0; i < dev->nregions; i++) { + void *mmap_addr; + VhostUserMemoryRegion *msg_region = &memory->regions[i]; + VubrDevRegion *dev_region = &dev->regions[i]; + + DPRINT("Region %d\n", i); + DPRINT(" guest_phys_addr: 0x%016"PRIx64"\n", + msg_region->guest_phys_addr); + DPRINT(" memory_size: 0x%016"PRIx64"\n", + msg_region->memory_size); + DPRINT(" userspace_addr 0x%016"PRIx64"\n", + msg_region->userspace_addr); + DPRINT(" mmap_offset 0x%016"PRIx64"\n", + msg_region->mmap_offset); + + dev_region->gpa = msg_region->guest_phys_addr; + dev_region->size = msg_region->memory_size; + dev_region->qva = msg_region->userspace_addr; + dev_region->mmap_offset = msg_region->mmap_offset; + + /* We don't use offset argument of mmap() since the + * mapped address has to be page aligned, and we use huge + * pages. */ + mmap_addr = mmap(0, dev_region->size + dev_region->mmap_offset, + PROT_READ | PROT_WRITE, MAP_SHARED, + vmsg->fds[i], 0); + + if (mmap_addr == MAP_FAILED) { + vubr_die("mmap"); + } + dev_region->mmap_addr = (uint64_t)(uintptr_t)mmap_addr; + DPRINT(" mmap_addr: 0x%016"PRIx64"\n", dev_region->mmap_addr); + + close(vmsg->fds[i]); + } + + return 0; +} + +static int +vubr_set_log_base_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + int fd; + uint64_t log_mmap_size, log_mmap_offset; + void *rc; + + assert(vmsg->fd_num == 1); + fd = vmsg->fds[0]; + + assert(vmsg->size == sizeof(vmsg->payload.log)); + log_mmap_offset = vmsg->payload.log.mmap_offset; + log_mmap_size = vmsg->payload.log.mmap_size; + DPRINT("Log mmap_offset: %"PRId64"\n", log_mmap_offset); + DPRINT("Log mmap_size: %"PRId64"\n", log_mmap_size); + + rc = mmap(0, log_mmap_size, PROT_READ | PROT_WRITE, MAP_SHARED, fd, + log_mmap_offset); + if (rc == MAP_FAILED) { + vubr_die("mmap"); + } + dev->log_table = rc; + dev->log_size = log_mmap_size; + + vmsg->size = sizeof(vmsg->payload.u64); + /* Reply */ + return 1; +} + +static int +vubr_set_log_fd_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + assert(vmsg->fd_num == 1); + dev->log_call_fd = vmsg->fds[0]; + DPRINT("Got log_call_fd: %d\n", vmsg->fds[0]); + return 0; +} + +static int +vubr_set_vring_num_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + unsigned int index = vmsg->payload.state.index; + unsigned int num = vmsg->payload.state.num; + + DPRINT("State.index: %d\n", index); + DPRINT("State.num: %d\n", num); + dev->vq[index].size = num; + return 0; +} + +static int +vubr_set_vring_addr_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + struct vhost_vring_addr *vra = &vmsg->payload.addr; + unsigned int index = vra->index; + VubrVirtq *vq = &dev->vq[index]; + + DPRINT("vhost_vring_addr:\n"); + DPRINT(" index: %d\n", vra->index); + DPRINT(" flags: %d\n", vra->flags); + DPRINT(" desc_user_addr: 0x%016llx\n", vra->desc_user_addr); + DPRINT(" used_user_addr: 0x%016llx\n", vra->used_user_addr); + DPRINT(" avail_user_addr: 0x%016llx\n", vra->avail_user_addr); + DPRINT(" log_guest_addr: 0x%016llx\n", vra->log_guest_addr); + + vq->desc = (struct vring_desc *)(uintptr_t)qva_to_va(dev, vra->desc_user_addr); + vq->used = (struct vring_used *)(uintptr_t)qva_to_va(dev, vra->used_user_addr); + vq->avail = (struct vring_avail *)(uintptr_t)qva_to_va(dev, vra->avail_user_addr); + vq->log_guest_addr = vra->log_guest_addr; + + DPRINT("Setting virtq addresses:\n"); + DPRINT(" vring_desc at %p\n", vq->desc); + DPRINT(" vring_used at %p\n", vq->used); + DPRINT(" vring_avail at %p\n", vq->avail); + + vq->last_used_index = vq->used->idx; + return 0; +} + +static int +vubr_set_vring_base_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + unsigned int index = vmsg->payload.state.index; + unsigned int num = vmsg->payload.state.num; + + DPRINT("State.index: %d\n", index); + DPRINT("State.num: %d\n", num); + dev->vq[index].last_avail_index = num; + + return 0; +} + +static int +vubr_get_vring_base_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + unsigned int index = vmsg->payload.state.index; + + DPRINT("State.index: %d\n", index); + vmsg->payload.state.num = dev->vq[index].last_avail_index; + vmsg->size = sizeof(vmsg->payload.state); + /* FIXME: this is a work-around for a bug in QEMU enabling + * too early vrings. When protocol features are enabled, + * we have to respect * VHOST_USER_SET_VRING_ENABLE request. */ + dev->ready = 0; + + if (dev->vq[index].call_fd != -1) { + close(dev->vq[index].call_fd); + dispatcher_remove(&dev->dispatcher, dev->vq[index].call_fd); + dev->vq[index].call_fd = -1; + } + if (dev->vq[index].kick_fd != -1) { + close(dev->vq[index].kick_fd); + dispatcher_remove(&dev->dispatcher, dev->vq[index].kick_fd); + dev->vq[index].kick_fd = -1; + } + + /* Reply */ + return 1; +} + +static int +vubr_set_vring_kick_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + uint64_t u64_arg = vmsg->payload.u64; + int index = u64_arg & VHOST_USER_VRING_IDX_MASK; + + DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64); + + assert((u64_arg & VHOST_USER_VRING_NOFD_MASK) == 0); + assert(vmsg->fd_num == 1); + + if (dev->vq[index].kick_fd != -1) { + close(dev->vq[index].kick_fd); + dispatcher_remove(&dev->dispatcher, dev->vq[index].kick_fd); + } + dev->vq[index].kick_fd = vmsg->fds[0]; + DPRINT("Got kick_fd: %d for vq: %d\n", vmsg->fds[0], index); + + if (index % 2 == 1) { + /* TX queue. */ + dispatcher_add(&dev->dispatcher, dev->vq[index].kick_fd, + dev, vubr_kick_cb); + + DPRINT("Waiting for kicks on fd: %d for vq: %d\n", + dev->vq[index].kick_fd, index); + } + /* We temporarily use this hack to determine that both TX and RX + * queues are set up and ready for processing. + * FIXME: we need to rely in VHOST_USER_SET_VRING_ENABLE and + * actual kicks. */ + if (dev->vq[0].kick_fd != -1 && + dev->vq[1].kick_fd != -1) { + dev->ready = 1; + DPRINT("vhost-user-bridge is ready for processing queues.\n"); + } + return 0; + +} + +static int +vubr_set_vring_call_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + uint64_t u64_arg = vmsg->payload.u64; + int index = u64_arg & VHOST_USER_VRING_IDX_MASK; + + DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64); + assert((u64_arg & VHOST_USER_VRING_NOFD_MASK) == 0); + assert(vmsg->fd_num == 1); + + if (dev->vq[index].call_fd != -1) { + close(dev->vq[index].call_fd); + dispatcher_remove(&dev->dispatcher, dev->vq[index].call_fd); + } + dev->vq[index].call_fd = vmsg->fds[0]; + DPRINT("Got call_fd: %d for vq: %d\n", vmsg->fds[0], index); + + return 0; +} + +static int +vubr_set_vring_err_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64); + return 0; +} + +static int +vubr_get_protocol_features_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + vmsg->payload.u64 = 1ULL << VHOST_USER_PROTOCOL_F_LOG_SHMFD; + DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64); + vmsg->size = sizeof(vmsg->payload.u64); + + /* Reply */ + return 1; +} + +static int +vubr_set_protocol_features_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + /* FIXME: unimplented */ + DPRINT("u64: 0x%016"PRIx64"\n", vmsg->payload.u64); + return 0; +} + +static int +vubr_get_queue_num_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + DPRINT("Function %s() not implemented yet.\n", __func__); + return 0; +} + +static int +vubr_set_vring_enable_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + unsigned int index = vmsg->payload.state.index; + unsigned int enable = vmsg->payload.state.num; + + DPRINT("State.index: %d\n", index); + DPRINT("State.enable: %d\n", enable); + dev->vq[index].enable = enable; + return 0; +} + +static int +vubr_send_rarp_exec(VubrDev *dev, VhostUserMsg *vmsg) +{ + DPRINT("Function %s() not implemented yet.\n", __func__); + return 0; +} + +static int +vubr_execute_request(VubrDev *dev, VhostUserMsg *vmsg) +{ + /* Print out generic part of the request. */ + DPRINT( + "================== Vhost user message from QEMU ==================\n"); + DPRINT("Request: %s (%d)\n", vubr_request_str[vmsg->request], + vmsg->request); + DPRINT("Flags: 0x%x\n", vmsg->flags); + DPRINT("Size: %d\n", vmsg->size); + + if (vmsg->fd_num) { + int i; + DPRINT("Fds:"); + for (i = 0; i < vmsg->fd_num; i++) { + DPRINT(" %d", vmsg->fds[i]); + } + DPRINT("\n"); + } + + switch (vmsg->request) { + case VHOST_USER_NONE: + return vubr_none_exec(dev, vmsg); + case VHOST_USER_GET_FEATURES: + return vubr_get_features_exec(dev, vmsg); + case VHOST_USER_SET_FEATURES: + return vubr_set_features_exec(dev, vmsg); + case VHOST_USER_SET_OWNER: + return vubr_set_owner_exec(dev, vmsg); + case VHOST_USER_RESET_OWNER: + return vubr_reset_device_exec(dev, vmsg); + case VHOST_USER_SET_MEM_TABLE: + return vubr_set_mem_table_exec(dev, vmsg); + case VHOST_USER_SET_LOG_BASE: + return vubr_set_log_base_exec(dev, vmsg); + case VHOST_USER_SET_LOG_FD: + return vubr_set_log_fd_exec(dev, vmsg); + case VHOST_USER_SET_VRING_NUM: + return vubr_set_vring_num_exec(dev, vmsg); + case VHOST_USER_SET_VRING_ADDR: + return vubr_set_vring_addr_exec(dev, vmsg); + case VHOST_USER_SET_VRING_BASE: + return vubr_set_vring_base_exec(dev, vmsg); + case VHOST_USER_GET_VRING_BASE: + return vubr_get_vring_base_exec(dev, vmsg); + case VHOST_USER_SET_VRING_KICK: + return vubr_set_vring_kick_exec(dev, vmsg); + case VHOST_USER_SET_VRING_CALL: + return vubr_set_vring_call_exec(dev, vmsg); + case VHOST_USER_SET_VRING_ERR: + return vubr_set_vring_err_exec(dev, vmsg); + case VHOST_USER_GET_PROTOCOL_FEATURES: + return vubr_get_protocol_features_exec(dev, vmsg); + case VHOST_USER_SET_PROTOCOL_FEATURES: + return vubr_set_protocol_features_exec(dev, vmsg); + case VHOST_USER_GET_QUEUE_NUM: + return vubr_get_queue_num_exec(dev, vmsg); + case VHOST_USER_SET_VRING_ENABLE: + return vubr_set_vring_enable_exec(dev, vmsg); + case VHOST_USER_SEND_RARP: + return vubr_send_rarp_exec(dev, vmsg); + + case VHOST_USER_MAX: + assert(vmsg->request != VHOST_USER_MAX); + } + return 0; +} + +static void +vubr_receive_cb(int sock, void *ctx) +{ + VubrDev *dev = (VubrDev *) ctx; + VhostUserMsg vmsg; + int reply_requested; + + vubr_message_read(sock, &vmsg); + reply_requested = vubr_execute_request(dev, &vmsg); + if (reply_requested) { + /* Set the version in the flags when sending the reply */ + vmsg.flags &= ~VHOST_USER_VERSION_MASK; + vmsg.flags |= VHOST_USER_VERSION; + vmsg.flags |= VHOST_USER_REPLY_MASK; + vubr_message_write(sock, &vmsg); + } +} + +static void +vubr_accept_cb(int sock, void *ctx) +{ + VubrDev *dev = (VubrDev *)ctx; + int conn_fd; + struct sockaddr_un un; + socklen_t len = sizeof(un); + + conn_fd = accept(sock, (struct sockaddr *) &un, &len); + if (conn_fd == -1) { + vubr_die("accept()"); + } + DPRINT("Got connection from remote peer on sock %d\n", conn_fd); + dispatcher_add(&dev->dispatcher, conn_fd, ctx, vubr_receive_cb); +} + +static VubrDev * +vubr_new(const char *path, bool client) +{ + VubrDev *dev = (VubrDev *) calloc(1, sizeof(VubrDev)); + dev->nregions = 0; + int i; + struct sockaddr_un un; + CallbackFunc cb; + size_t len; + + for (i = 0; i < MAX_NR_VIRTQUEUE; i++) { + dev->vq[i] = (VubrVirtq) { + .call_fd = -1, .kick_fd = -1, + .size = 0, + .last_avail_index = 0, .last_used_index = 0, + .desc = 0, .avail = 0, .used = 0, + .enable = 0, + }; + } + + /* Init log */ + dev->log_call_fd = -1; + dev->log_size = 0; + dev->log_table = 0; + dev->ready = 0; + dev->features = 0; + + /* Get a UNIX socket. */ + dev->sock = socket(AF_UNIX, SOCK_STREAM, 0); + if (dev->sock == -1) { + vubr_die("socket"); + } + + un.sun_family = AF_UNIX; + strcpy(un.sun_path, path); + len = sizeof(un.sun_family) + strlen(path); + + if (!client) { + unlink(path); + + if (bind(dev->sock, (struct sockaddr *) &un, len) == -1) { + vubr_die("bind"); + } + + if (listen(dev->sock, 1) == -1) { + vubr_die("listen"); + } + cb = vubr_accept_cb; + } else { + if (connect(dev->sock, (struct sockaddr *)&un, len) == -1) { + vubr_die("connect"); + } + cb = vubr_receive_cb; + } + + dispatcher_init(&dev->dispatcher); + dispatcher_add(&dev->dispatcher, dev->sock, (void *)dev, cb); + + DPRINT("Waiting for connections on UNIX socket %s ...\n", path); + return dev; +} + +static void +vubr_set_host(struct sockaddr_in *saddr, const char *host) +{ + if (isdigit(host[0])) { + if (!inet_aton(host, &saddr->sin_addr)) { + fprintf(stderr, "inet_aton() failed.\n"); + exit(1); + } + } else { + struct hostent *he = gethostbyname(host); + + if (!he) { + fprintf(stderr, "gethostbyname() failed.\n"); + exit(1); + } + saddr->sin_addr = *(struct in_addr *)he->h_addr; + } +} + +static void +vubr_backend_udp_setup(VubrDev *dev, + const char *local_host, + const char *local_port, + const char *remote_host, + const char *remote_port) +{ + int sock; + const char *r; + + int lport, rport; + + lport = strtol(local_port, (char **)&r, 0); + if (r == local_port) { + fprintf(stderr, "lport parsing failed.\n"); + exit(1); + } + + rport = strtol(remote_port, (char **)&r, 0); + if (r == remote_port) { + fprintf(stderr, "rport parsing failed.\n"); + exit(1); + } + + struct sockaddr_in si_local = { + .sin_family = AF_INET, + .sin_port = htons(lport), + }; + + vubr_set_host(&si_local, local_host); + + /* setup destination for sends */ + dev->backend_udp_dest = (struct sockaddr_in) { + .sin_family = AF_INET, + .sin_port = htons(rport), + }; + vubr_set_host(&dev->backend_udp_dest, remote_host); + + sock = socket(AF_INET, SOCK_DGRAM, IPPROTO_UDP); + if (sock == -1) { + vubr_die("socket"); + } + + if (bind(sock, (struct sockaddr *)&si_local, sizeof(si_local)) == -1) { + vubr_die("bind"); + } + + dev->backend_udp_sock = sock; + dispatcher_add(&dev->dispatcher, sock, dev, vubr_backend_recv_cb); + DPRINT("Waiting for data from udp backend on %s:%d...\n", + local_host, lport); +} + +static void +vubr_run(VubrDev *dev) +{ + while (1) { + /* timeout 200ms */ + dispatcher_wait(&dev->dispatcher, 200000); + /* Here one can try polling strategy. */ + } +} + +static int +vubr_parse_host_port(const char **host, const char **port, const char *buf) +{ + char *p = strchr(buf, ':'); + + if (!p) { + return -1; + } + *p = '\0'; + *host = strdup(buf); + *port = strdup(p + 1); + return 0; +} + +#define DEFAULT_UD_SOCKET "/tmp/vubr.sock" +#define DEFAULT_LHOST "127.0.0.1" +#define DEFAULT_LPORT "4444" +#define DEFAULT_RHOST "127.0.0.1" +#define DEFAULT_RPORT "5555" + +static const char *ud_socket_path = DEFAULT_UD_SOCKET; +static const char *lhost = DEFAULT_LHOST; +static const char *lport = DEFAULT_LPORT; +static const char *rhost = DEFAULT_RHOST; +static const char *rport = DEFAULT_RPORT; + +int +main(int argc, char *argv[]) +{ + VubrDev *dev; + int opt; + bool client = false; + + while ((opt = getopt(argc, argv, "l:r:u:c")) != -1) { + + switch (opt) { + case 'l': + if (vubr_parse_host_port(&lhost, &lport, optarg) < 0) { + goto out; + } + break; + case 'r': + if (vubr_parse_host_port(&rhost, &rport, optarg) < 0) { + goto out; + } + break; + case 'u': + ud_socket_path = strdup(optarg); + break; + case 'c': + client = true; + break; + default: + goto out; + } + } + + DPRINT("ud socket: %s (%s)\n", ud_socket_path, + client ? "client" : "server"); + DPRINT("local: %s:%s\n", lhost, lport); + DPRINT("remote: %s:%s\n", rhost, rport); + + dev = vubr_new(ud_socket_path, client); + if (!dev) { + return 1; + } + + vubr_backend_udp_setup(dev, lhost, lport, rhost, rport); + vubr_run(dev); + return 0; + +out: + fprintf(stderr, "Usage: %s ", argv[0]); + fprintf(stderr, "[-u ud_socket_path] [-l lhost:lport] [-r rhost:rport]\n"); + fprintf(stderr, "\t-u path to unix doman socket. default: %s\n", + DEFAULT_UD_SOCKET); + fprintf(stderr, "\t-l local host and port. default: %s:%s\n", + DEFAULT_LHOST, DEFAULT_LPORT); + fprintf(stderr, "\t-r remote host and port. default: %s:%s\n", + DEFAULT_RHOST, DEFAULT_RPORT); + + return 1; +} diff --git a/tests/vhost-user-test.c.orig b/tests/vhost-user-test.c.orig new file mode 100644 index 0000000000..b491e6fcb6 --- /dev/null +++ b/tests/vhost-user-test.c.orig @@ -0,0 +1,364 @@ +/* + * QTest testcase for the vhost-user + * + * Copyright (c) 2014 Virtual Open Systems Sarl. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + * + */ + +#include <glib.h> + +#include "libqtest.h" +#include "qemu/option.h" +#include "sysemu/char.h" +#include "sysemu/sysemu.h" + +#include <linux/vhost.h> +#include <sys/mman.h> +#include <sys/vfs.h> +#include <qemu/sockets.h> + +/* GLIB version compatibility flags */ +#if !GLIB_CHECK_VERSION(2, 26, 0) +#define G_TIME_SPAN_SECOND (G_GINT64_CONSTANT(1000000)) +#endif + +#if GLIB_CHECK_VERSION(2, 28, 0) +#define HAVE_MONOTONIC_TIME +#endif + +#define QEMU_CMD_ACCEL " -machine accel=tcg" +#define QEMU_CMD_MEM " -m 512 -object memory-backend-file,id=mem,size=512M,"\ + "mem-path=%s,share=on -numa node,memdev=mem" +#define QEMU_CMD_CHR " -chardev socket,id=chr0,path=%s" +#define QEMU_CMD_NETDEV " -netdev vhost-user,id=net0,chardev=chr0,vhostforce" +#define QEMU_CMD_NET " -device virtio-net-pci,netdev=net0 " +#define QEMU_CMD_ROM " -option-rom ../pc-bios/pxe-virtio.rom" + +#define QEMU_CMD QEMU_CMD_ACCEL QEMU_CMD_MEM QEMU_CMD_CHR \ + QEMU_CMD_NETDEV QEMU_CMD_NET QEMU_CMD_ROM + +#define HUGETLBFS_MAGIC 0x958458f6 + +/*********** FROM hw/virtio/vhost-user.c *************************************/ + +#define VHOST_MEMORY_MAX_NREGIONS 8 + +#define VHOST_USER_F_PROTOCOL_FEATURES 30 + +typedef enum VhostUserRequest { + VHOST_USER_NONE = 0, + VHOST_USER_GET_FEATURES = 1, + VHOST_USER_SET_FEATURES = 2, + VHOST_USER_SET_OWNER = 3, + VHOST_USER_RESET_DEVICE = 4, + VHOST_USER_SET_MEM_TABLE = 5, + VHOST_USER_SET_LOG_BASE = 6, + VHOST_USER_SET_LOG_FD = 7, + VHOST_USER_SET_VRING_NUM = 8, + VHOST_USER_SET_VRING_ADDR = 9, + VHOST_USER_SET_VRING_BASE = 10, + VHOST_USER_GET_VRING_BASE = 11, + VHOST_USER_SET_VRING_KICK = 12, + VHOST_USER_SET_VRING_CALL = 13, + VHOST_USER_SET_VRING_ERR = 14, + VHOST_USER_GET_PROTOCOL_FEATURES = 15, + VHOST_USER_SET_PROTOCOL_FEATURES = 16, + VHOST_USER_MAX +} VhostUserRequest; + +typedef struct VhostUserMemoryRegion { + uint64_t guest_phys_addr; + uint64_t memory_size; + uint64_t userspace_addr; + uint64_t mmap_offset; +} VhostUserMemoryRegion; + +typedef struct VhostUserMemory { + uint32_t nregions; + uint32_t padding; + VhostUserMemoryRegion regions[VHOST_MEMORY_MAX_NREGIONS]; +} VhostUserMemory; + +typedef struct VhostUserMsg { + VhostUserRequest request; + +#define VHOST_USER_VERSION_MASK (0x3) +#define VHOST_USER_REPLY_MASK (0x1<<2) + uint32_t flags; + uint32_t size; /* the following payload size */ + union { + uint64_t u64; + struct vhost_vring_state state; + struct vhost_vring_addr addr; + VhostUserMemory memory; + }; +} QEMU_PACKED VhostUserMsg; + +static VhostUserMsg m __attribute__ ((unused)); +#define VHOST_USER_HDR_SIZE (sizeof(m.request) \ + + sizeof(m.flags) \ + + sizeof(m.size)) + +#define VHOST_USER_PAYLOAD_SIZE (sizeof(m) - VHOST_USER_HDR_SIZE) + +/* The version of the protocol we support */ +#define VHOST_USER_VERSION (0x1) +/*****************************************************************************/ + +int fds_num = 0, fds[VHOST_MEMORY_MAX_NREGIONS]; +static VhostUserMemory memory; +static CompatGMutex data_mutex; +static CompatGCond data_cond; + +#if !GLIB_CHECK_VERSION(2, 32, 0) +static gboolean g_cond_wait_until(CompatGCond cond, CompatGMutex mutex, + gint64 end_time) +{ + gboolean ret = FALSE; + end_time -= g_get_monotonic_time(); + GTimeVal time = { end_time / G_TIME_SPAN_SECOND, + end_time % G_TIME_SPAN_SECOND }; + ret = g_cond_timed_wait(cond, mutex, &time); + return ret; +} +#endif + +static void wait_for_fds(void) +{ + gint64 end_time; + + g_mutex_lock(&data_mutex); + end_time = g_get_monotonic_time() + 5 * G_TIME_SPAN_SECOND; + while (!fds_num) { + if (!g_cond_wait_until(&data_cond, &data_mutex, end_time)) { + /* timeout has passed */ + g_assert(fds_num); + break; + } + } + + /* check for sanity */ + g_assert_cmpint(fds_num, >, 0); + g_assert_cmpint(fds_num, ==, memory.nregions); + + g_mutex_unlock(&data_mutex); +} + +static void read_guest_mem(void) +{ + uint32_t *guest_mem; + int i, j; + size_t size; + + wait_for_fds(); + + /* iterate all regions */ + for (i = 0; i < fds_num; i++) { + + /* We'll check only the region statring at 0x0*/ + if (memory.regions[i].guest_phys_addr != 0x0) { + continue; + } + + g_assert_cmpint(memory.regions[i].memory_size, >, 1024); + + size = memory.regions[i].memory_size + memory.regions[i].mmap_offset; + + guest_mem = mmap(0, size, PROT_READ | PROT_WRITE, + MAP_SHARED, fds[i], 0); + + g_assert(guest_mem != MAP_FAILED); + guest_mem += (memory.regions[i].mmap_offset / sizeof(*guest_mem)); + + for (j = 0; j < 256; j++) { + uint32_t a = readl(memory.regions[i].guest_phys_addr + j*4); + uint32_t b = guest_mem[j]; + + g_assert_cmpint(a, ==, b); + } + + munmap(guest_mem, memory.regions[i].memory_size); + } + + g_mutex_unlock(&data_mutex); +} + +static void *thread_function(void *data) +{ + GMainLoop *loop; + loop = g_main_loop_new(NULL, FALSE); + g_main_loop_run(loop); + return NULL; +} + +static int chr_can_read(void *opaque) +{ + return VHOST_USER_HDR_SIZE; +} + +static void chr_read(void *opaque, const uint8_t *buf, int size) +{ + CharDriverState *chr = opaque; + VhostUserMsg msg; + uint8_t *p = (uint8_t *) &msg; + int fd; + + if (size != VHOST_USER_HDR_SIZE) { + g_test_message("Wrong message size received %d\n", size); + return; + } + + g_mutex_lock(&data_mutex); + memcpy(p, buf, VHOST_USER_HDR_SIZE); + + if (msg.size) { + p += VHOST_USER_HDR_SIZE; + qemu_chr_fe_read_all(chr, p, msg.size); + } + + switch (msg.request) { + case VHOST_USER_GET_FEATURES: + /* send back features to qemu */ + msg.flags |= VHOST_USER_REPLY_MASK; + msg.size = sizeof(m.u64); + msg.u64 = 0x1ULL << VHOST_USER_F_PROTOCOL_FEATURES; + p = (uint8_t *) &msg; + qemu_chr_fe_write_all(chr, p, VHOST_USER_HDR_SIZE + msg.size); + break; + + case VHOST_USER_SET_FEATURES: + g_assert_cmpint(msg.u64 & (0x1ULL << VHOST_USER_F_PROTOCOL_FEATURES), + !=, 0ULL); + break; + + case VHOST_USER_GET_PROTOCOL_FEATURES: + /* send back features to qemu */ + msg.flags |= VHOST_USER_REPLY_MASK; + msg.size = sizeof(m.u64); + msg.u64 = 0; + p = (uint8_t *) &msg; + qemu_chr_fe_write_all(chr, p, VHOST_USER_HDR_SIZE + msg.size); + break; + + case VHOST_USER_GET_VRING_BASE: + /* send back vring base to qemu */ + msg.flags |= VHOST_USER_REPLY_MASK; + msg.size = sizeof(m.state); + msg.state.num = 0; + p = (uint8_t *) &msg; + qemu_chr_fe_write_all(chr, p, VHOST_USER_HDR_SIZE + msg.size); + break; + + case VHOST_USER_SET_MEM_TABLE: + /* received the mem table */ + memcpy(&memory, &msg.memory, sizeof(msg.memory)); + fds_num = qemu_chr_fe_get_msgfds(chr, fds, sizeof(fds) / sizeof(int)); + + /* signal the test that it can continue */ + g_cond_signal(&data_cond); + break; + + case VHOST_USER_SET_VRING_KICK: + case VHOST_USER_SET_VRING_CALL: + /* consume the fd */ + qemu_chr_fe_get_msgfds(chr, &fd, 1); + /* + * This is a non-blocking eventfd. + * The receive function forces it to be blocking, + * so revert it back to non-blocking. + */ + qemu_set_nonblock(fd); + break; + default: + break; + } + g_mutex_unlock(&data_mutex); +} + +static const char *init_hugepagefs(void) +{ + const char *path; + struct statfs fs; + int ret; + + path = getenv("QTEST_HUGETLBFS_PATH"); + if (!path) { + path = "/hugetlbfs"; + } + + if (access(path, R_OK | W_OK | X_OK)) { + g_test_message("access on path (%s): %s\n", path, strerror(errno)); + return NULL; + } + + do { + ret = statfs(path, &fs); + } while (ret != 0 && errno == EINTR); + + if (ret != 0) { + g_test_message("statfs on path (%s): %s\n", path, strerror(errno)); + return NULL; + } + + if (fs.f_type != HUGETLBFS_MAGIC) { + g_test_message("Warning: path not on HugeTLBFS: %s\n", path); + return NULL; + } + + return path; +} + +int main(int argc, char **argv) +{ + QTestState *s = NULL; + CharDriverState *chr = NULL; + const char *hugefs = 0; + char *socket_path = 0; + char *qemu_cmd = 0; + char *chr_path = 0; + int ret; + + g_test_init(&argc, &argv, NULL); + + module_call_init(MODULE_INIT_QOM); + + hugefs = init_hugepagefs(); + if (!hugefs) { + return 0; + } + + socket_path = g_strdup_printf("/tmp/vhost-%d.sock", getpid()); + + /* create char dev and add read handlers */ + qemu_add_opts(&qemu_chardev_opts); + chr_path = g_strdup_printf("unix:%s,server,nowait", socket_path); + chr = qemu_chr_new("chr0", chr_path, NULL); + g_free(chr_path); + qemu_chr_add_handlers(chr, chr_can_read, chr_read, NULL, chr); + + /* run the main loop thread so the chardev may operate */ + g_mutex_init(&data_mutex); + g_cond_init(&data_cond); + g_thread_new(NULL, thread_function, NULL); + + qemu_cmd = g_strdup_printf(QEMU_CMD, hugefs, socket_path); + s = qtest_start(qemu_cmd); + g_free(qemu_cmd); + + qtest_add_func("/vhost-user/read-guest-mem", read_guest_mem); + + ret = g_test_run(); + + if (s) { + qtest_quit(s); + } + + /* cleanup */ + unlink(socket_path); + g_free(socket_path); + + return ret; +} diff --git a/util/hexdump.c b/util/hexdump.c index 0b4662e701..2c105a8846 100644 --- a/util/hexdump.c +++ b/util/hexdump.c @@ -16,36 +16,50 @@ #include "qemu/osdep.h" #include "qemu-common.h" -void qemu_hexdump(FILE *fp, const char *prefix, - const void *bufptr, size_t size) +void qemu_hexdump_line(char *line, unsigned int b, const void *bufptr, + unsigned int len, bool ascii) { const char *buf = bufptr; - unsigned int b, len, i, c; + int i, c; - for (b = 0; b < size; b += 16) { - len = size - b; - if (len > 16) { - len = 16; + if (len > QEMU_HEXDUMP_LINE_BYTES) { + len = QEMU_HEXDUMP_LINE_BYTES; + } + + line += snprintf(line, 6, "%04x:", b); + for (i = 0; i < QEMU_HEXDUMP_LINE_BYTES; i++) { + if ((i % 4) == 0) { + *line++ = ' '; } - fprintf(fp, "%s: %04x:", prefix, b); - for (i = 0; i < 16; i++) { - if ((i % 4) == 0) { - fprintf(fp, " "); - } - if (i < len) { - fprintf(fp, " %02x", (unsigned char)buf[b + i]); - } else { - fprintf(fp, " "); - } + if (i < len) { + line += sprintf(line, " %02x", (unsigned char)buf[b + i]); + } else { + line += sprintf(line, " "); } - fprintf(fp, " "); + } + if (ascii) { + *line++ = ' '; for (i = 0; i < len; i++) { c = buf[b + i]; if (c < ' ' || c > '~') { c = '.'; } - fprintf(fp, "%c", c); + *line++ = c; } - fprintf(fp, "\n"); } + *line = '\0'; +} + +void qemu_hexdump(FILE *fp, const char *prefix, + const void *bufptr, size_t size) +{ + unsigned int b, len; + char line[QEMU_HEXDUMP_LINE_LEN]; + + for (b = 0; b < size; b += QEMU_HEXDUMP_LINE_BYTES) { + len = size - b; + qemu_hexdump_line(line, b, bufptr, len, true); + fprintf(fp, "%s: %s\n", prefix, line); + } + } |