diff options
| -rw-r--r-- | target/hppa/insns.decode | 5 | ||||
| -rw-r--r-- | target/hppa/translate.c | 11 |
2 files changed, 12 insertions, 4 deletions
diff --git a/target/hppa/insns.decode b/target/hppa/insns.decode index c7a7e997f9..27341d27b2 100644 --- a/target/hppa/insns.decode +++ b/target/hppa/insns.decode @@ -388,10 +388,7 @@ fmpyfadd_d 101110 rm1:5 rm2:5 ... 0 1 ..0 0 0 neg:1 t:5 ra3=%rc32 # Floating point class 0 -# FID. With r = t = 0, which via fcpy puts 0 into fr0. -# This is machine/revision = 0, which is reserved for simulator. -fcpy_f 001100 00000 00000 00000 000000 00000 \ - &fclass01 r=0 t=0 +fid_f 001100 00000 00000 000 00 000000 00000 fcpy_f 001100 ..... ..... 010 00 ...... ..... @f0c_0 fabs_f 001100 ..... ..... 011 00 ...... ..... @f0c_0 diff --git a/target/hppa/translate.c b/target/hppa/translate.c index d15b9e27c7..981f8ee03d 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -3622,6 +3622,17 @@ static void gen_fcpy_f(TCGv_i32 dst, TCGv_env unused, TCGv_i32 src) tcg_gen_mov_i32(dst, src); } +static bool trans_fid_f(DisasContext *ctx, arg_fid_f *a) +{ + nullify_over(ctx); +#if TARGET_REGISTER_BITS == 64 + save_frd(0, tcg_const_i64(0x13080000000000ULL)); /* PA8700 (PCX-W2) */ +#else + save_frd(0, tcg_const_i64(0x0f080000000000ULL)); /* PA7300LC (PCX-L2) */ +#endif + return nullify_end(ctx); +} + static bool trans_fcpy_f(DisasContext *ctx, arg_fclass01 *a) { return do_fop_wew(ctx, a->t, a->r, gen_fcpy_f); |