diff options
| -rw-r--r-- | target/ppc/insn32.decode | 5 | ||||
| -rw-r--r-- | target/ppc/translate/vsx-impl.c.inc | 20 | ||||
| -rw-r--r-- | target/ppc/translate/vsx-ops.c.inc | 1 |
3 files changed, 11 insertions, 15 deletions
diff --git a/target/ppc/insn32.decode b/target/ppc/insn32.decode index 5d425ec076..fd73946122 100644 --- a/target/ppc/insn32.decode +++ b/target/ppc/insn32.decode @@ -96,6 +96,10 @@ &X_bfl bf l:bool ra rb @X_bfl ...... bf:3 - l:1 ra:5 rb:5 ..........- &X_bfl +%x_xt 0:1 21:5 +&X_imm8 xt imm:uint8_t +@X_imm8 ...... ..... .. imm:8 .......... . &X_imm8 xt=%x_xt + &X_tb_sp_rc rt rb sp rc:bool @X_tb_sp_rc ...... rt:5 sp:2 ... rb:5 .......... rc:1 &X_tb_sp_rc @@ -414,4 +418,5 @@ STXVPX 011111 ..... ..... ..... 0111001101 - @X_TSXP ## VSX splat instruction +XXSPLTIB 111100 ..... 00 ........ 0101101000 . @X_imm8 XXSPLTW 111100 ..... ---.. ..... 010100100 . . @XX2 diff --git a/target/ppc/translate/vsx-impl.c.inc b/target/ppc/translate/vsx-impl.c.inc index ce8796d139..ad25a0daf0 100644 --- a/target/ppc/translate/vsx-impl.c.inc +++ b/target/ppc/translate/vsx-impl.c.inc @@ -1455,23 +1455,15 @@ static bool trans_XXSPLTW(DisasContext *ctx, arg_XX2 *a) #define pattern(x) (((x) & 0xff) * (~(uint64_t)0 / 0xff)) -static void gen_xxspltib(DisasContext *ctx) +static bool trans_XXSPLTIB(DisasContext *ctx, arg_X_imm8 *a) { - uint8_t uim8 = IMM8(ctx->opcode); - int rt = xT(ctx->opcode); - - if (rt < 32) { - if (unlikely(!ctx->vsx_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VSXU); - return; - } + if (a->xt < 32) { + REQUIRE_VSX(ctx); } else { - if (unlikely(!ctx->altivec_enabled)) { - gen_exception(ctx, POWERPC_EXCP_VPU); - return; - } + REQUIRE_VECTOR(ctx); } - tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(rt), 16, 16, uim8); + tcg_gen_gvec_dup_imm(MO_8, vsr_full_offset(a->xt), 16, 16, a->imm); + return true; } static void gen_xxsldwi(DisasContext *ctx) diff --git a/target/ppc/translate/vsx-ops.c.inc b/target/ppc/translate/vsx-ops.c.inc index b669b64d35..152d1e5c3b 100644 --- a/target/ppc/translate/vsx-ops.c.inc +++ b/target/ppc/translate/vsx-ops.c.inc @@ -348,7 +348,6 @@ GEN_XX3FORM(xxmrghw, 0x08, 0x02, PPC2_VSX), GEN_XX3FORM(xxmrglw, 0x08, 0x06, PPC2_VSX), GEN_XX3FORM(xxperm, 0x08, 0x03, PPC2_ISA300), GEN_XX3FORM(xxpermr, 0x08, 0x07, PPC2_ISA300), -GEN_XX1FORM(xxspltib, 0x08, 0x0B, PPC2_ISA300), GEN_XX3FORM_DM(xxsldwi, 0x08, 0x00), GEN_XX2FORM_EXT(xxextractuw, 0x0A, 0x0A, PPC2_ISA300), GEN_XX2FORM_EXT(xxinsertw, 0x0A, 0x0B, PPC2_ISA300), |