diff options
| -rw-r--r-- | target/xtensa/cpu.h | 6 | ||||
| -rw-r--r-- | target/xtensa/overlay_tool.h | 2 | ||||
| -rw-r--r-- | target/xtensa/translate.c | 162 |
3 files changed, 170 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d4258fcc61..74ee7d1253 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -144,6 +144,12 @@ enum { CACHEATTR = 98, ATOMCTL = 99, DDR = 104, + MEPC = 106, + MEPS = 107, + MESAVE = 108, + MESR = 109, + MECR = 110, + MEVADDR = 111, IBREAKA = 128, DBREAKA = 144, DBREAKC = 160, diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index 8b380ce5e3..ffaab4b094 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -112,6 +112,8 @@ XCHAL_OPTION(XCHAL_DCACHE_LINE_LOCKABLE, \ XTENSA_OPTION_DCACHE_INDEX_LOCK) | \ XCHAL_OPTION(XCHAL_UNALIGNED_LOAD_HW, XTENSA_OPTION_HW_ALIGNMENT) | \ + XCHAL_OPTION(XCHAL_HAVE_MEM_ECC_PARITY, \ + XTENSA_OPTION_MEMORY_ECC_PARITY) | \ /* Memory protection and translation */ \ XCHAL_OPTION(XCHAL_HAVE_MIMIC_CACHEATTR, \ XTENSA_OPTION_REGION_PROTECTION) | \ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 100d6e1265..63a90fdd17 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -4216,6 +4216,60 @@ static const XtensaOpcodeOps core_ops[] = { .par = (const uint32_t[]){MEMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, }, { + .name = "rsr.mecr", + .translate = translate_rsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MECR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "rsr.mepc", + .translate = translate_rsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MEPC, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "rsr.meps", + .translate = translate_rsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MEPS, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "rsr.mesave", + .translate = translate_rsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MESAVE, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "rsr.mesr", + .translate = translate_rsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "rsr.mevaddr", + .translate = translate_rsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { .name = "rsr.misc0", .translate = translate_rsr, .test_ill = test_ill_sr, @@ -5036,6 +5090,60 @@ static const XtensaOpcodeOps core_ops[] = { .par = (const uint32_t[]){MEMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, }, { + .name = "wsr.mecr", + .translate = translate_wsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MECR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "wsr.mepc", + .translate = translate_wsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MEPC, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "wsr.meps", + .translate = translate_wsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MEPS, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "wsr.mesave", + .translate = translate_wsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MESAVE, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "wsr.mesr", + .translate = translate_wsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "wsr.mevaddr", + .translate = translate_wsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { .name = "wsr.misc0", .translate = translate_wsr, .test_ill = test_ill_sr, @@ -5702,6 +5810,60 @@ static const XtensaOpcodeOps core_ops[] = { .par = (const uint32_t[]){MEMCTL}, .op_flags = XTENSA_OP_PRIVILEGED, }, { + .name = "xsr.mecr", + .translate = translate_xsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MECR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "xsr.mepc", + .translate = translate_xsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MEPC, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "xsr.meps", + .translate = translate_xsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MEPS, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "xsr.mesave", + .translate = translate_xsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MESAVE, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "xsr.mesr", + .translate = translate_xsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { + .name = "xsr.mevaddr", + .translate = translate_xsr, + .test_ill = test_ill_sr, + .par = (const uint32_t[]){ + MESR, + XTENSA_OPTION_MEMORY_ECC_PARITY, + }, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { .name = "xsr.misc0", .translate = translate_xsr, .test_ill = test_ill_sr, |