diff options
| -rw-r--r-- | CODING_STYLE | 2 | ||||
| -rw-r--r-- | docs/ccid.txt | 2 | ||||
| -rw-r--r-- | docs/specs/ivshmem_device_spec.txt | 2 | ||||
| -rw-r--r-- | target-alpha/STATUS | 2 | ||||
| -rw-r--r-- | target-mips/TODO | 4 |
5 files changed, 6 insertions, 6 deletions
diff --git a/CODING_STYLE b/CODING_STYLE index 7c82d4d0af..dcbce28a27 100644 --- a/CODING_STYLE +++ b/CODING_STYLE @@ -1,4 +1,4 @@ -Qemu Coding Style +QEMU Coding Style ================= Please use the script checkpatch.pl in the scripts directory to check diff --git a/docs/ccid.txt b/docs/ccid.txt index b8e504a3cc..450a66ad99 100644 --- a/docs/ccid.txt +++ b/docs/ccid.txt @@ -1,4 +1,4 @@ -Qemu CCID Device Documentation. +QEMU CCID Device Documentation. Contents 1. USB CCID device diff --git a/docs/specs/ivshmem_device_spec.txt b/docs/specs/ivshmem_device_spec.txt index 23dd2ba89f..667a8628f0 100644 --- a/docs/specs/ivshmem_device_spec.txt +++ b/docs/specs/ivshmem_device_spec.txt @@ -24,7 +24,7 @@ The device currently supports 4 registers of 32-bits each. Registers are used for synchronization between guests sharing the same memory object when interrupts are supported (this requires using the shared memory server). -The server assigns each VM an ID number and sends this ID number to the Qemu +The server assigns each VM an ID number and sends this ID number to the QEMU process when the guest starts. enum ivshmem_registers { diff --git a/target-alpha/STATUS b/target-alpha/STATUS index 742e370b90..6c9744569e 100644 --- a/target-alpha/STATUS +++ b/target-alpha/STATUS @@ -4,7 +4,7 @@ Alpha emulation structure: cpu.h : CPU definitions globally exported exec.h : CPU definitions used only for translated code execution helper.c : helpers that can be called either by the translated code - or the Qemu core, including the exception handler. + or the QEMU core, including the exception handler. op_helper.c : helpers that can be called only from TCG helper.h : TCG helpers prototypes translate.c : Alpha instructions to micro-operations translator diff --git a/target-mips/TODO b/target-mips/TODO index 9101881a97..2a3546f624 100644 --- a/target-mips/TODO +++ b/target-mips/TODO @@ -16,7 +16,7 @@ General Existing documentation is x86-centric. - Reverse endianness bit not implemented - The TLB emulation is very inefficient: - Qemu's softmmu implements a x86-style MMU, with separate entries + QEMU's softmmu implements a x86-style MMU, with separate entries for read/write/execute, a TLB index which is just a modulo of the virtual address, and a set of TLBs for each user/kernel/supervisor MMU mode. @@ -25,7 +25,7 @@ General up to 256 ASID tags as additional matching criterion (which roughly equates to 256 MMU modes). It also has a global flag which causes entries to match regardless of ASID. - To cope with these differences, Qemu currently flushes the TLB at + To cope with these differences, QEMU currently flushes the TLB at each ASID change. Using the MMU modes to implement ASIDs hinges on implementing the global bit efficiently. - save/restore of the CPU state is not implemented (see machine.c). |