diff options
643 files changed, 2789 insertions, 1433 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index d4bf816287..8839f22e3e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -324,8 +324,10 @@ S: Supported F: configs/targets/riscv* F: docs/system/target-riscv.rst F: target/riscv/ +F: hw/char/riscv_htif.c F: hw/riscv/ F: hw/intc/riscv* +F: include/hw/char/riscv_htif.h F: include/hw/riscv/ F: linux-user/host/riscv32/ F: linux-user/host/riscv64/ @@ -1626,6 +1628,12 @@ F: docs/system/riscv/sifive_u.rst F: hw/*/*sifive*.c F: include/hw/*/*sifive*.h +AMD Microblaze-V Generic Board +M: Sai Pavan Boddu <sai.pavan.boddu@amd.com> +S: Maintained +F: hw/riscv/microblaze-v-generic.c +F: docs/system/riscv/microblaze-v-generic.rst + RX Machines ----------- rx-gdbsim diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index 672050e800..c65b790433 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -437,6 +437,16 @@ int kvm_unpark_vcpu(KVMState *s, unsigned long vcpu_id) return kvm_fd; } +static void kvm_reset_parked_vcpus(void *param) +{ + KVMState *s = param; + struct KVMParkedVcpu *cpu; + + QLIST_FOREACH(cpu, &s->kvm_parked_vcpus, node) { + kvm_arch_reset_parked_vcpu(cpu->vcpu_id, cpu->kvm_fd); + } +} + int kvm_create_vcpu(CPUState *cpu) { unsigned long vcpu_id = kvm_arch_vcpu_id(cpu); @@ -2728,6 +2738,7 @@ static int kvm_init(MachineState *ms) } qemu_register_reset(kvm_unpoison_all, NULL); + qemu_register_reset(kvm_reset_parked_vcpus, s); if (s->kernel_irqchip_allowed) { kvm_irqchip_create(s); @@ -2999,17 +3010,17 @@ int kvm_convert_memory(hwaddr start, hwaddr size, bool to_private) MemoryRegion *mr; RAMBlock *rb; void *addr; - int ret = -1; + int ret = -EINVAL; trace_kvm_convert_memory(start, size, to_private ? "shared_to_private" : "private_to_shared"); if (!QEMU_PTR_IS_ALIGNED(start, qemu_real_host_page_size()) || !QEMU_PTR_IS_ALIGNED(size, qemu_real_host_page_size())) { - return -1; + return ret; } if (!size) { - return -1; + return ret; } section = memory_region_find(get_system_memory(), start, size); @@ -3027,7 +3038,7 @@ int kvm_convert_memory(hwaddr start, hwaddr size, bool to_private) if (!to_private) { return 0; } - return -1; + return ret; } if (!memory_region_has_guest_memfd(mr)) { diff --git a/backends/tpm/tpm_util.c b/backends/tpm/tpm_util.c index f5feb48acf..3294625106 100644 --- a/backends/tpm/tpm_util.c +++ b/backends/tpm/tpm_util.c @@ -46,7 +46,7 @@ static void get_tpm(Object *obj, Visitor *v, const char *name, void *opaque, static void set_tpm(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; TPMBackend *s, **be = object_field_prop_ptr(obj, prop); char *str; @@ -66,7 +66,7 @@ static void set_tpm(Object *obj, Visitor *v, const char *name, void *opaque, static void release_tpm(Object *obj, const char *name, void *opaque) { - Property *prop = opaque; + const Property *prop = opaque; TPMBackend **be = object_field_prop_ptr(obj, prop); if (*be) { diff --git a/configs/targets/i386-softmmu.mak b/configs/targets/i386-softmmu.mak index 2ac69d5ba3..2eb0e86250 100644 --- a/configs/targets/i386-softmmu.mak +++ b/configs/targets/i386-softmmu.mak @@ -1,4 +1,5 @@ TARGET_ARCH=i386 TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y +TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-32bit.xml diff --git a/configs/targets/x86_64-softmmu.mak b/configs/targets/x86_64-softmmu.mak index e12ac3dc59..920e9a4200 100644 --- a/configs/targets/x86_64-softmmu.mak +++ b/configs/targets/x86_64-softmmu.mak @@ -2,4 +2,5 @@ TARGET_ARCH=x86_64 TARGET_BASE_ARCH=i386 TARGET_SUPPORTS_MTTCG=y TARGET_KVM_HAVE_GUEST_DEBUG=y +TARGET_KVM_HAVE_RESET_PARKED_VCPU=y TARGET_XML_FILES= gdb-xml/i386-64bit.xml diff --git a/cpu-target.c b/cpu-target.c index beec773790..667688332c 100644 --- a/cpu-target.c +++ b/cpu-target.c @@ -202,7 +202,6 @@ static const Property cpu_common_props[] = { DEFINE_PROP_LINK("memory", CPUState, memory, TYPE_MEMORY_REGION, MemoryRegion *), #endif - DEFINE_PROP_END_OF_LIST(), }; #ifndef CONFIG_USER_ONLY diff --git a/docs/devel/migration/compatibility.rst b/docs/devel/migration/compatibility.rst index c787f53738..ecb887e318 100644 --- a/docs/devel/migration/compatibility.rst +++ b/docs/devel/migration/compatibility.rst @@ -401,7 +401,6 @@ the old behaviour or the new behaviour:: DEFINE_PROP_UINT32("acpi-index", PCIDevice, acpi_index, 0), + DEFINE_PROP_BIT("x-pcie-err-unc-mask", PCIDevice, cap_present, + QEMU_PCIE_ERR_UNC_MASK_BITNR, true), - DEFINE_PROP_END_OF_LIST() }; Notice that we enable the feature for new machine types. diff --git a/docs/devel/virtio-backends.rst b/docs/devel/virtio-backends.rst index a6f9df4845..679d7544b8 100644 --- a/docs/devel/virtio-backends.rst +++ b/docs/devel/virtio-backends.rst @@ -107,7 +107,6 @@ manually instantiated: VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_blk_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/docs/specs/index.rst b/docs/specs/index.rst index ff5a1f03da..d7675cebc2 100644 --- a/docs/specs/index.rst +++ b/docs/specs/index.rst @@ -37,3 +37,4 @@ guest hardware that is specific to QEMU. rapl-msr rocker riscv-iommu + riscv-aia diff --git a/docs/specs/riscv-aia.rst b/docs/specs/riscv-aia.rst new file mode 100644 index 0000000000..8097e2f897 --- /dev/null +++ b/docs/specs/riscv-aia.rst @@ -0,0 +1,83 @@ +.. _riscv-aia: + +RISC-V AIA support for RISC-V machines +====================================== + +AIA (Advanced Interrupt Architecture) support is implemented in the ``virt`` +RISC-V machine for TCG and KVM accelerators. + +The support consists of two main modes: + +- "aia=aplic": adds one or more APLIC (Advanced Platform Level Interrupt Controller) + devices +- "aia=aplic-imsic": adds one or more APLIC device and an IMSIC (Incoming MSI + Controller) device for each CPU + +From an user standpoint, these modes will behave the same regardless of the accelerator +used. From a developer standpoint the accelerator settings will change what it being +emulated in userspace versus what is being emulated by an in-kernel irqchip. + +When running TCG, all controllers are emulated in userspace, including machine mode +(m-mode) APLIC and IMSIC (when applicable). + +When running KVM: + +- no m-mode is provided, so there is no m-mode APLIC or IMSIC emulation regardless of + the AIA mode chosen +- with "aia=aplic", s-mode APLIC will be emulated by userspace +- with "aia=aplic-imsic" there are two possibilities. If no additional KVM option + is provided there will be no APLIC or IMSIC emulation in userspace, and the virtual + machine will use the provided in-kernel APLIC and IMSIC controllers. If the user + chooses to use the irqchip in split mode via "-accel kvm,kernel-irqchip=split", + s-mode APLIC will be emulated while using the s-mode IMSIC from the irqchip + +The following table summarizes how the AIA and accelerator options defines what +we will emulate in userspace: + + +.. list-table:: How AIA and accel options changes controller emulation + :widths: 25 25 25 25 25 25 25 + :header-rows: 1 + + * - Accel + - Accel props + - AIA type + - APLIC m-mode + - IMSIC m-mode + - APLIC s-mode + - IMSIC s-mode + * - tcg + - --- + - aplic + - emul + - n/a + - emul + - n/a + * - tcg + - --- + - aplic-imsic + - emul + - emul + - emul + - emul + * - kvm + - --- + - aplic + - n/a + - n/a + - emul + - n/a + * - kvm + - none + - aplic-imsic + - n/a + - n/a + - in-kernel + - in-kernel + * - kvm + - irqchip=split + - aplic-imsic + - n/a + - n/a + - emul + - in-kernel diff --git a/docs/specs/riscv-iommu.rst b/docs/specs/riscv-iommu.rst index 463f4cffb6..b1538c9ead 100644 --- a/docs/specs/riscv-iommu.rst +++ b/docs/specs/riscv-iommu.rst @@ -6,9 +6,9 @@ RISC-V IOMMU support for RISC-V machines QEMU implements a RISC-V IOMMU emulation based on the RISC-V IOMMU spec version 1.0 `iommu1.0`_. -The emulation includes a PCI reference device, riscv-iommu-pci, that QEMU -RISC-V boards can use. The 'virt' RISC-V machine is compatible with this -device. +The emulation includes a PCI reference device (riscv-iommu-pci) and a platform +bus device (riscv-iommu-sys) that QEMU RISC-V boards can use. The 'virt' +RISC-V machine is compatible with both devices. riscv-iommu-pci reference device -------------------------------- @@ -83,6 +83,30 @@ Several options are available to control the capabilities of the device, namely: - "s-stage": enable s-stage support - "g-stage": enable g-stage support +riscv-iommu-sys device +---------------------- + +This device implements the RISC-V IOMMU emulation as a platform bus device that +RISC-V boards can use. + +For the 'virt' board the device is disabled by default. To enable it use the +'iommu-sys' machine option: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt,iommu-sys=on (...) + +There is no options to configure the capabilities of this device in the 'virt' +board using the QEMU command line. The device is configured with the following +riscv-iommu options: + +- "ioatc-limit": default value (2Mb) +- "intremap": enabled +- "ats": enabled +- "off": on (DMA disabled) +- "s-stage": enabled +- "g-stage": enabled + .. _iommu1.0: https://github.com/riscv-non-isa/riscv-iommu/releases/download/v1.0/riscv-iommu.pdf .. _linux-v8: https://lore.kernel.org/linux-riscv/cover.1718388908.git.tjeznach@rivosinc.com/ diff --git a/docs/system/riscv/microblaze-v-generic.rst b/docs/system/riscv/microblaze-v-generic.rst new file mode 100644 index 0000000000..5606f88d57 --- /dev/null +++ b/docs/system/riscv/microblaze-v-generic.rst @@ -0,0 +1,42 @@ +Microblaze-V generic board (``amd-microblaze-v-generic``) +========================================================= +The AMD MicroBlaze™ V processor is a soft-core RISC-V processor IP for AMD +adaptive SoCs and FPGAs. The MicroBlaze™ V processor is based on the 32-bit (or +64-bit) RISC-V instruction set architecture (ISA) and contains interfaces +compatible with the classic MicroBlaze™ V processor (i.e it is a drop in +replacement for the classic MicroBlaze™ processor in existing RTL designs). +More information can be found in below document. + +https://docs.amd.com/r/en-US/ug1629-microblaze-v-user-guide/MicroBlaze-V-Architecture + +The MicroBlaze™ V generic board in QEMU has following supported devices: + + - timer + - uartlite + - uart16550 + - emaclite + - timer2 + - axi emac + - axi dma + +The MicroBlaze™ V core in QEMU has the following configuration: + + - RV32I base integer instruction set + - "Zicsr" Control and Status register instructions + - "Zifencei" instruction-fetch + - Extensions: m, a, f, c + +Running +""""""" +Below is an example command line for launching mainline U-boot +(xilinx_mbv32_defconfig) on the Microblaze-V generic board. + +.. code-block:: bash + + $ qemu-system-riscv32 -M amd-microblaze-v-generic \ + -display none \ + -device loader,addr=0x80000000,file=u-boot-spl.bin,cpu-num=0 \ + -device loader,addr=0x80200000,file=u-boot.img \ + -serial mon:stdio \ + -device loader,addr=0x83000000,file=system.dtb \ + -m 2g diff --git a/docs/system/riscv/virt.rst b/docs/system/riscv/virt.rst index 8e9a2e4dda..60850970ce 100644 --- a/docs/system/riscv/virt.rst +++ b/docs/system/riscv/virt.rst @@ -94,6 +94,12 @@ command line: $ qemu-system-riscv64 -M virt -device riscv-iommu-pci (...) +It also has support for the riscv-iommu-sys platform device: + +.. code-block:: bash + + $ qemu-system-riscv64 -M virt,iommu-sys=on (...) + Refer to :ref:`riscv-iommu` for more information on how the RISC-V IOMMU support works. @@ -123,12 +129,23 @@ The following machine-specific options are supported: MSIs. When not specified, this option is assumed to be "none" which selects SiFive PLIC to handle wired interrupts. + This option also interacts with '-accel kvm'. When using "aia=aplic-imsic" + with KVM, it is possible to set the use of the kernel irqchip in split mode + by using "-accel kvm,kernel-irqchip=split". In this case the ``virt`` machine + will emulate the APLIC controller instead of using the APLIC controller from + the irqchip. See :ref:`riscv-aia` for more details on all available AIA + modes. + - aia-guests=nnn The number of per-HART VS-level AIA IMSIC pages to be emulated for a guest having AIA IMSIC (i.e. "aia=aplic-imsic" selected). When not specified, the default number of per-HART VS-level AIA IMSIC pages is 0. +- iommu-sys=[on|off] + + Enables the riscv-iommu-sys platform device. Defaults to 'off'. + Running Linux kernel -------------------- diff --git a/docs/system/target-riscv.rst b/docs/system/target-riscv.rst index ba195f1518..95457af130 100644 --- a/docs/system/target-riscv.rst +++ b/docs/system/target-riscv.rst @@ -66,6 +66,7 @@ undocumented; you can get a complete list by running .. toctree:: :maxdepth: 1 + riscv/microblaze-v-generic riscv/microchip-icicle-kit riscv/shakti-c riscv/sifive_u diff --git a/hw/9pfs/virtio-9p-device.c b/hw/9pfs/virtio-9p-device.c index 4f30054cc3..bb2843da0f 100644 --- a/hw/9pfs/virtio-9p-device.c +++ b/hw/9pfs/virtio-9p-device.c @@ -246,7 +246,6 @@ static const VMStateDescription vmstate_virtio_9p = { static const Property virtio_9p_properties[] = { DEFINE_PROP_STRING("mount_tag", V9fsVirtioState, state.fsconf.tag), DEFINE_PROP_STRING("fsdev", V9fsVirtioState, state.fsconf.fsdev_id), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_9p_class_init(ObjectClass *klass, void *data) diff --git a/hw/acpi/aml-build.c b/hw/acpi/aml-build.c index 331de43dad..f8f93a9f66 100644 --- a/hw/acpi/aml-build.c +++ b/hw/acpi/aml-build.c @@ -2078,7 +2078,7 @@ static void build_processor_hierarchy_node(GArray *tbl, uint32_t flags, void build_spcr(GArray *table_data, BIOSLinker *linker, const AcpiSpcrData *f, const uint8_t rev, - const char *oem_id, const char *oem_table_id) + const char *oem_id, const char *oem_table_id, const char *name) { AcpiTable table = { .sig = "SPCR", .rev = rev, .oem_id = oem_id, .oem_table_id = oem_table_id }; @@ -2124,9 +2124,21 @@ void build_spcr(GArray *table_data, BIOSLinker *linker, build_append_int_noprefix(table_data, f->pci_flags, 4); /* PCI Segment */ build_append_int_noprefix(table_data, f->pci_segment, 1); - /* Reserved */ - build_append_int_noprefix(table_data, 0, 4); - + if (rev < 4) { + /* Reserved */ + build_append_int_noprefix(table_data, 0, 4); + } else { + /* UartClkFreq */ + build_append_int_noprefix(table_data, f->uart_clk_freq, 4); + /* PreciseBaudrate */ + build_append_int_noprefix(table_data, f->precise_baudrate, 4); + /* NameSpaceStringLength */ + build_append_int_noprefix(table_data, f->namespace_string_length, 2); + /* NameSpaceStringOffset */ + build_append_int_noprefix(table_data, f->namespace_string_offset, 2); + /* NamespaceString[] */ + g_array_append_vals(table_data, name, f->namespace_string_length); + } acpi_table_end(linker, &table); } /* diff --git a/hw/acpi/erst.c b/hw/acpi/erst.c index 536092039b..ec64f92893 100644 --- a/hw/acpi/erst.c +++ b/hw/acpi/erst.c @@ -1016,7 +1016,6 @@ static const Property erst_properties[] = { TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_UINT32(ACPI_ERST_RECORD_SIZE_PROP, ERSTDeviceState, default_record_size, ERST_RECORD_SIZE), - DEFINE_PROP_END_OF_LIST(), }; static void erst_class_init(ObjectClass *klass, void *data) diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index dbcd0f5366..58540c0aaf 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -318,7 +318,6 @@ static void acpi_ged_send_event(AcpiDeviceIf *adev, AcpiEventStatusBits ev) static const Property acpi_ged_properties[] = { DEFINE_PROP_UINT32("ged-event", AcpiGedState, ged_event_bitmap, 0), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_memhp_state = { diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 85fbd1ab68..6d023e595b 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -617,7 +617,6 @@ static const Property piix4_pm_properties[] = { DEFINE_PROP_BOOL("smm-enabled", PIIX4PMState, smm_enabled, false), DEFINE_PROP_BOOL("x-not-migrate-acpi-index", PIIX4PMState, not_migrate_acpi_index, false), - DEFINE_PROP_END_OF_LIST(), }; static void piix4_pm_class_init(ObjectClass *klass, void *data) diff --git a/hw/acpi/vmgenid.c b/hw/acpi/vmgenid.c index 8f32c0c616..008768e036 100644 --- a/hw/acpi/vmgenid.c +++ b/hw/acpi/vmgenid.c @@ -216,7 +216,6 @@ static void vmgenid_realize(DeviceState *dev, Error **errp) static const Property vmgenid_device_properties[] = { DEFINE_PROP_UUID(VMGENID_GUID, VmGenIdState, guid), - DEFINE_PROP_END_OF_LIST(), }; static void vmgenid_device_class_init(ObjectClass *klass, void *data) diff --git a/hw/adc/aspeed_adc.c b/hw/adc/aspeed_adc.c index f94c6f2be3..1cc554f179 100644 --- a/hw/adc/aspeed_adc.c +++ b/hw/adc/aspeed_adc.c @@ -289,7 +289,6 @@ static const VMStateDescription vmstate_aspeed_adc_engine = { static const Property aspeed_adc_engine_properties[] = { DEFINE_PROP_UINT32("engine-id", AspeedADCEngineState, engine_id, 0), DEFINE_PROP_UINT32("nr-channels", AspeedADCEngineState, nr_channels, 0), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_adc_engine_class_init(ObjectClass *klass, void *data) diff --git a/hw/adc/npcm7xx_adc.c b/hw/adc/npcm7xx_adc.c index 1781ff4c0b..0a83d28605 100644 --- a/hw/adc/npcm7xx_adc.c +++ b/hw/adc/npcm7xx_adc.c @@ -269,7 +269,6 @@ static const VMStateDescription vmstate_npcm7xx_adc = { static const Property npcm7xx_timer_properties[] = { DEFINE_PROP_UINT32("iref", NPCM7xxADCState, iref, NPCM7XX_ADC_DEFAULT_IREF), - DEFINE_PROP_END_OF_LIST(), }; static void npcm7xx_adc_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/armsse.c b/hw/arm/armsse.c index 1cd6b4a4b2..ffd732f806 100644 --- a/hw/arm/armsse.c +++ b/hw/arm/armsse.c @@ -72,6 +72,7 @@ struct ARMSSEInfo { bool has_cpu_pwrctrl; bool has_sse_counter; bool has_tcms; + uint8_t props_count; const Property *props; const ARMSSEDeviceInfo *devinfo; const bool *irq_is_common; @@ -87,7 +88,6 @@ static const Property iotkit_properties[] = { DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), - DEFINE_PROP_END_OF_LIST() }; static const Property sse200_properties[] = { @@ -104,7 +104,6 @@ static const Property sse200_properties[] = { DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), DEFINE_PROP_UINT32("CPU1_MPU_NS", ARMSSE, cpu_mpu_ns[1], 8), DEFINE_PROP_UINT32("CPU1_MPU_S", ARMSSE, cpu_mpu_s[1], 8), - DEFINE_PROP_END_OF_LIST() }; static const Property sse300_properties[] = { @@ -117,7 +116,6 @@ static const Property sse300_properties[] = { DEFINE_PROP_BOOL("CPU0_DSP", ARMSSE, cpu_dsp[0], true), DEFINE_PROP_UINT32("CPU0_MPU_NS", ARMSSE, cpu_mpu_ns[0], 8), DEFINE_PROP_UINT32("CPU0_MPU_S", ARMSSE, cpu_mpu_s[0], 8), - DEFINE_PROP_END_OF_LIST() }; static const ARMSSEDeviceInfo iotkit_devices[] = { @@ -528,6 +526,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_sse_counter = false, .has_tcms = false, .props = iotkit_properties, + .props_count = ARRAY_SIZE(iotkit_properties), .devinfo = iotkit_devices, .irq_is_common = sse200_irq_is_common, }, @@ -549,6 +548,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_sse_counter = false, .has_tcms = false, .props = sse200_properties, + .props_count = ARRAY_SIZE(sse200_properties), .devinfo = sse200_devices, .irq_is_common = sse200_irq_is_common, }, @@ -570,6 +570,7 @@ static const ARMSSEInfo armsse_variants[] = { .has_sse_counter = true, .has_tcms = true, .props = sse300_properties, + .props_count = ARRAY_SIZE(sse300_properties), .devinfo = sse300_devices, .irq_is_common = sse300_irq_is_common, }, @@ -1699,7 +1700,7 @@ static void armsse_class_init(ObjectClass *klass, void *data) dc->realize = armsse_realize; dc->vmsd = &armsse_vmstate; - device_class_set_props(dc, info->props); + device_class_set_props_n(dc, info->props, info->props_count); device_class_set_legacy_reset(dc, armsse_reset); iic->check = armsse_idau_check; asc->info = info; diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 74f4d36e61..a67a890a33 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -552,7 +552,6 @@ static const Property armv7m_properties[] = { DEFINE_PROP_BOOL("dsp", ARMv7MState, dsp, true), DEFINE_PROP_UINT32("mpu-ns-regions", ARMv7MState, mpu_ns_regions, UINT_MAX), DEFINE_PROP_UINT32("mpu-s-regions", ARMv7MState, mpu_s_regions, UINT_MAX), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_armv7m = { @@ -635,7 +634,6 @@ static const Property bitband_properties[] = { DEFINE_PROP_UINT32("base", BitBandState, base, 0), DEFINE_PROP_LINK("source-memory", BitBandState, source_memory, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void bitband_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/aspeed_soc_common.c b/hw/arm/aspeed_soc_common.c index 4221cacd51..1ddcb26c1e 100644 --- a/hw/arm/aspeed_soc_common.c +++ b/hw/arm/aspeed_soc_common.c @@ -144,7 +144,6 @@ static const Property aspeed_soc_properties[] = { MemoryRegion *), DEFINE_PROP_LINK("memory", AspeedSoCState, memory, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_soc_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 58d818d002..5359a6d8d3 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -311,7 +311,6 @@ static void fsl_imx25_realize(DeviceState *dev, Error **errp) static const Property fsl_imx25_properties[] = { DEFINE_PROP_UINT32("fec-phy-num", FslIMX25State, phy_num, 0), - DEFINE_PROP_END_OF_LIST(), }; static void fsl_imx25_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/fsl-imx6.c b/hw/arm/fsl-imx6.c index 7f56d68b93..ac8c66e242 100644 --- a/hw/arm/fsl-imx6.c +++ b/hw/arm/fsl-imx6.c @@ -483,7 +483,6 @@ static void fsl_imx6_realize(DeviceState *dev, Error **errp) static const Property fsl_imx6_properties[] = { DEFINE_PROP_UINT32("fec-phy-num", FslIMX6State, phy_num, 0), - DEFINE_PROP_END_OF_LIST(), }; static void fsl_imx6_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/fsl-imx6ul.c b/hw/arm/fsl-imx6ul.c index 4aceefaa0f..79e4847953 100644 --- a/hw/arm/fsl-imx6ul.c +++ b/hw/arm/fsl-imx6ul.c @@ -725,7 +725,6 @@ static const Property fsl_imx6ul_properties[] = { true), DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX6ULState, phy_connected[1], true), - DEFINE_PROP_END_OF_LIST(), }; static void fsl_imx6ul_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/fsl-imx7.c b/hw/arm/fsl-imx7.c index 4c38876101..05e3389fbe 100644 --- a/hw/arm/fsl-imx7.c +++ b/hw/arm/fsl-imx7.c @@ -743,7 +743,6 @@ static const Property fsl_imx7_properties[] = { true), DEFINE_PROP_BOOL("fec2-phy-connected", FslIMX7State, phy_connected[1], true), - DEFINE_PROP_END_OF_LIST(), }; static void fsl_imx7_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index d85564893d..4e1b8627d3 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -696,7 +696,6 @@ DEFINE_MACHINE("integratorcp", integratorcp_machine_init) static const Property core_properties[] = { DEFINE_PROP_UINT32("memsz", IntegratorCMState, memsz, 0), - DEFINE_PROP_END_OF_LIST(), }; static void core_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index 0f0ac46dab..e8a5b231ba 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -234,7 +234,6 @@ static const Property m2sxxx_soc_properties[] = { /* default divisors in Libero GUI */ DEFINE_PROP_UINT8("apb0div", MSF2State, apb0div, 2), DEFINE_PROP_UINT8("apb1div", MSF2State, apb1div, 2), - DEFINE_PROP_END_OF_LIST(), }; static void m2sxxx_soc_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 49ea8f949b..386b2c35e9 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -813,7 +813,6 @@ static void npcm7xx_realize(DeviceState *dev, Error **errp) static const Property npcm7xx_properties[] = { DEFINE_PROP_LINK("dram-mr", NPCM7xxState, dram, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void npcm7xx_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index 43fac8a8db..37dd4cf5f4 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -214,7 +214,6 @@ static const Property nrf51_soc_properties[] = { DEFINE_PROP_UINT32("sram-size", NRF51State, sram_size, NRF51822_SRAM_SIZE), DEFINE_PROP_UINT32("flash-size", NRF51State, flash_size, NRF51822_FLASH_SIZE), - DEFINE_PROP_END_OF_LIST(), }; static void nrf51_soc_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 6baa9d0fc3..dd74c2e558 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -938,7 +938,6 @@ static const Property smmu_dev_properties[] = { DEFINE_PROP_UINT8("bus_num", SMMUState, bus_num, 0), DEFINE_PROP_LINK("primary-bus", SMMUState, primary_bus, TYPE_PCI_BUS, PCIBus *), - DEFINE_PROP_END_OF_LIST(), }; static void smmu_base_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 026838f9ac..c0cf5df0f6 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -1985,7 +1985,6 @@ static const Property smmuv3_properties[] = { * Defaults to stage 1 */ DEFINE_PROP_STRING("stage", SMMUv3State, stage), - DEFINE_PROP_END_OF_LIST() }; static void smmuv3_instance_init(Object *obj) diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 1fee37a7c1..1bba96df14 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -448,7 +448,6 @@ static const Property stellaris_sys_properties[] = { DEFINE_PROP_UINT32("dc2", ssys_state, dc2, 0), DEFINE_PROP_UINT32("dc3", ssys_state, dc3, 0), DEFINE_PROP_UINT32("dc4", ssys_state, dc4, 0), - DEFINE_PROP_END_OF_LIST() }; static void stellaris_sys_instance_init(Object *obj) diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index 051b1d87a1..a31f4b4c65 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -1334,7 +1334,6 @@ static const VMStateDescription vmstate_strongarm_uart_regs = { static const Property strongarm_uart_properties[] = { DEFINE_PROP_CHR("chardev", StrongARMUARTState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void strongarm_uart_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/virt-acpi-build.c b/hw/arm/virt-acpi-build.c index 94c3248212..c9b13057a3 100644 --- a/hw/arm/virt-acpi-build.c +++ b/hw/arm/virt-acpi-build.c @@ -463,8 +463,12 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, VirtMachineState *vms) .pci_flags = 0, .pci_segment = 0, }; - - build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id); + /* + * Passing NULL as the SPCR Table for Revision 2 doesn't support + * NameSpaceString. + */ + build_spcr(table_data, linker, &serial, 2, vms->oem_id, vms->oem_table_id, + NULL); } /* diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 6eb8acf4f1..cccdd99fcc 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -975,7 +975,6 @@ static const Property versal_properties[] = { TYPE_CAN_BUS, CanBusState *), DEFINE_PROP_LINK("canbus1", Versal, lpd.iou.canbus[1], TYPE_CAN_BUS, CanBusState *), - DEFINE_PROP_END_OF_LIST() }; static void versal_class_init(ObjectClass *klass, void *data) diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 3974392946..bd5b0dd5e7 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -867,7 +867,6 @@ static const Property xlnx_zynqmp_props[] = { CanBusState *), DEFINE_PROP_LINK("canbus1", XlnxZynqMPState, canbus[1], TYPE_CAN_BUS, CanBusState *), - DEFINE_PROP_END_OF_LIST() }; static void xlnx_zynqmp_class_init(ObjectClass *oc, void *data) diff --git a/hw/audio/ac97.c b/hw/audio/ac97.c index 667286207c..05c573776e 100644 --- a/hw/audio/ac97.c +++ b/hw/audio/ac97.c @@ -1326,7 +1326,6 @@ static void ac97_exit(PCIDevice *dev) static const Property ac97_properties[] = { DEFINE_AUDIO_PROPERTIES(AC97LinkState, card), - DEFINE_PROP_END_OF_LIST(), }; static void ac97_class_init(ObjectClass *klass, void *data) diff --git a/hw/audio/adlib.c b/hw/audio/adlib.c index c1d8faecb4..8c9767b537 100644 --- a/hw/audio/adlib.c +++ b/hw/audio/adlib.c @@ -301,7 +301,6 @@ static const Property adlib_properties[] = { DEFINE_AUDIO_PROPERTIES(AdlibState, card), DEFINE_PROP_UINT32 ("iobase", AdlibState, port, 0x220), DEFINE_PROP_UINT32 ("freq", AdlibState, freq, 44100), - DEFINE_PROP_END_OF_LIST (), }; static void adlib_class_initfn (ObjectClass *klass, void *data) diff --git a/hw/audio/asc.c b/hw/audio/asc.c index 452039418d..cc205bf063 100644 --- a/hw/audio/asc.c +++ b/hw/audio/asc.c @@ -698,7 +698,6 @@ static void asc_init(Object *obj) static const Property asc_properties[] = { DEFINE_AUDIO_PROPERTIES(ASCState, card), DEFINE_PROP_UINT8("asctype", ASCState, type, ASC_TYPE_ASC), - DEFINE_PROP_END_OF_LIST(), }; static void asc_class_init(ObjectClass *oc, void *data) diff --git a/hw/audio/cs4231a.c b/hw/audio/cs4231a.c index abc38720a3..5a9be80ba3 100644 --- a/hw/audio/cs4231a.c +++ b/hw/audio/cs4231a.c @@ -694,7 +694,6 @@ static const Property cs4231a_properties[] = { DEFINE_PROP_UINT32 ("iobase", CSState, port, 0x534), DEFINE_PROP_UINT32 ("irq", CSState, irq, 9), DEFINE_PROP_UINT32 ("dma", CSState, dma, 3), - DEFINE_PROP_END_OF_LIST (), }; static void cs4231a_class_initfn (ObjectClass *klass, void *data) diff --git a/hw/audio/es1370.c b/hw/audio/es1370.c index 513f987cc4..75f71e5d78 100644 --- a/hw/audio/es1370.c +++ b/hw/audio/es1370.c @@ -870,7 +870,6 @@ static void es1370_exit(PCIDevice *dev) static const Property es1370_properties[] = { DEFINE_AUDIO_PROPERTIES(ES1370State, card), - DEFINE_PROP_END_OF_LIST(), }; static void es1370_class_init (ObjectClass *klass, void *data) diff --git a/hw/audio/gus.c b/hw/audio/gus.c index dd5a5a3441..e718c1183e 100644 --- a/hw/audio/gus.c +++ b/hw/audio/gus.c @@ -296,7 +296,6 @@ static const Property gus_properties[] = { DEFINE_PROP_UINT32 ("iobase", GUSState, port, 0x240), DEFINE_PROP_UINT32 ("irq", GUSState, emu.gusirq, 7), DEFINE_PROP_UINT32 ("dma", GUSState, emu.gusdma, 3), - DEFINE_PROP_END_OF_LIST (), }; static void gus_class_initfn (ObjectClass *klass, void *data) diff --git a/hw/audio/hda-codec.c b/hw/audio/hda-codec.c index 8bd8f62c48..6f3a8f691b 100644 --- a/hw/audio/hda-codec.c +++ b/hw/audio/hda-codec.c @@ -862,7 +862,6 @@ static const Property hda_audio_properties[] = { DEFINE_PROP_UINT32("debug", HDAAudioState, debug, 0), DEFINE_PROP_BOOL("mixer", HDAAudioState, mixer, true), DEFINE_PROP_BOOL("use-timer", HDAAudioState, use_timer, true), - DEFINE_PROP_END_OF_LIST(), }; static void hda_audio_init_output(HDACodecDevice *hda, Error **errp) diff --git a/hw/audio/intel-hda.c b/hw/audio/intel-hda.c index fe9f4058fe..3214992ddc 100644 --- a/hw/audio/intel-hda.c +++ b/hw/audio/intel-hda.c @@ -39,7 +39,6 @@ static const Property hda_props[] = { DEFINE_PROP_UINT32("cad", HDACodecDevice, cad, -1), - DEFINE_PROP_END_OF_LIST() }; static const TypeInfo hda_codec_bus_info = { @@ -1219,7 +1218,6 @@ static const Property intel_hda_properties[] = { DEFINE_PROP_UINT32("debug", IntelHDAState, debug, 0), DEFINE_PROP_ON_OFF_AUTO("msi", IntelHDAState, msi, ON_OFF_AUTO_AUTO), DEFINE_PROP_BOOL("old_msi_addr", IntelHDAState, old_msi_addr, false), - DEFINE_PROP_END_OF_LIST(), }; static void intel_hda_class_init(ObjectClass *klass, void *data) diff --git a/hw/audio/pcspk.c b/hw/audio/pcspk.c index 7a6b9f52d3..17be185547 100644 --- a/hw/audio/pcspk.c +++ b/hw/audio/pcspk.c @@ -219,7 +219,6 @@ static const Property pcspk_properties[] = { DEFINE_AUDIO_PROPERTIES(PCSpkState, card), DEFINE_PROP_UINT32("iobase", PCSpkState, iobase, 0x61), DEFINE_PROP_BOOL("migrate", PCSpkState, migrate, true), - DEFINE_PROP_END_OF_LIST(), }; static void pcspk_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/audio/pl041.c b/hw/audio/pl041.c index 6c66a240cb..f771d725fa 100644 --- a/hw/audio/pl041.c +++ b/hw/audio/pl041.c @@ -630,7 +630,6 @@ static const Property pl041_device_properties[] = { /* Non-compact FIFO depth property */ DEFINE_PROP_UINT32("nc_fifo_depth", PL041State, fifo_depth, DEFAULT_FIFO_DEPTH), - DEFINE_PROP_END_OF_LIST(), }; static void pl041_device_class_init(ObjectClass *klass, void *data) diff --git a/hw/audio/sb16.c b/hw/audio/sb16.c index 143b9e71e1..0c661b4947 100644 --- a/hw/audio/sb16.c +++ b/hw/audio/sb16.c @@ -1447,7 +1447,6 @@ static const Property sb16_properties[] = { DEFINE_PROP_UINT32 ("irq", SB16State, irq, 5), DEFINE_PROP_UINT32 ("dma", SB16State, dma, 1), DEFINE_PROP_UINT32 ("dma16", SB16State, hdma, 5), - DEFINE_PROP_END_OF_LIST (), }; static void sb16_class_initfn (ObjectClass *klass, void *data) diff --git a/hw/audio/via-ac97.c b/hw/audio/via-ac97.c index e43ddf37f3..4e115e011e 100644 --- a/hw/audio/via-ac97.c +++ b/hw/audio/via-ac97.c @@ -461,7 +461,6 @@ static void via_ac97_exit(PCIDevice *dev) static const Property via_ac97_properties[] = { DEFINE_AUDIO_PROPERTIES(ViaAC97State, card), - DEFINE_PROP_END_OF_LIST(), }; static void via_ac97_class_init(ObjectClass *klass, void *data) diff --git a/hw/audio/virtio-snd-pci.c b/hw/audio/virtio-snd-pci.c index b762d7e81e..74d93f4e9c 100644 --- a/hw/audio/virtio-snd-pci.c +++ b/hw/audio/virtio-snd-pci.c @@ -31,7 +31,6 @@ static const Property virtio_snd_pci_properties[] = { DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_snd_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/audio/virtio-snd.c b/hw/audio/virtio-snd.c index 4c89ed3fc9..0b47741f01 100644 --- a/hw/audio/virtio-snd.c +++ b/hw/audio/virtio-snd.c @@ -85,7 +85,6 @@ static const Property virtio_snd_properties[] = { VIRTIO_SOUND_STREAM_DEFAULT), DEFINE_PROP_UINT32("chmaps", VirtIOSound, snd_conf.chmaps, VIRTIO_SOUND_CHMAP_DEFAULT), - DEFINE_PROP_END_OF_LIST(), }; static void diff --git a/hw/audio/wm8750.c b/hw/audio/wm8750.c index 19e7755060..8d381dbc65 100644 --- a/hw/audio/wm8750.c +++ b/hw/audio/wm8750.c @@ -708,7 +708,6 @@ void wm8750_set_bclk_in(void *opaque, int new_hz) static const Property wm8750_properties[] = { DEFINE_AUDIO_PROPERTIES(WM8750State, card), - DEFINE_PROP_END_OF_LIST(), }; static void wm8750_class_init(ObjectClass *klass, void *data) diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 1f38fa21c8..f6844bf118 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -358,7 +358,6 @@ static void atmega_realize(DeviceState *dev, Error **errp) static const Property atmega_props[] = { DEFINE_PROP_UINT64("xtal-frequency-hz", AtmegaMcuState, xtal_freq_hz, 0), - DEFINE_PROP_END_OF_LIST() }; static void atmega_class_init(ObjectClass *oc, void *data) diff --git a/hw/block/fdc-isa.c b/hw/block/fdc-isa.c index 4d9b6d53d3..a10c24aab1 100644 --- a/hw/block/fdc-isa.c +++ b/hw/block/fdc-isa.c @@ -296,7 +296,6 @@ static const Property isa_fdc_properties[] = { DEFINE_PROP_SIGNED("fallback", FDCtrlISABus, state.fallback, FLOPPY_DRIVE_TYPE_288, qdev_prop_fdc_drive_type, FloppyDriveType), - DEFINE_PROP_END_OF_LIST(), }; static void isabus_fdc_class_init(ObjectClass *klass, void *data) diff --git a/hw/block/fdc-sysbus.c b/hw/block/fdc-sysbus.c index f17e04b138..381b492aec 100644 --- a/hw/block/fdc-sysbus.c +++ b/hw/block/fdc-sysbus.c @@ -206,7 +206,6 @@ static const Property sysbus_fdc_properties[] = { DEFINE_PROP_SIGNED("fallback", FDCtrlSysBus, state.fallback, FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, FloppyDriveType), - DEFINE_PROP_END_OF_LIST(), }; static void sysbus_fdc_class_init(ObjectClass *klass, void *data) @@ -230,7 +229,6 @@ static const Property sun4m_fdc_properties[] = { DEFINE_PROP_SIGNED("fallback", FDCtrlSysBus, state.fallback, FLOPPY_DRIVE_TYPE_144, qdev_prop_fdc_drive_type, FloppyDriveType), - DEFINE_PROP_END_OF_LIST(), }; static void sun4m_fdc_class_init(ObjectClass *klass, void *data) diff --git a/hw/block/fdc.c b/hw/block/fdc.c index 3790d5685f..2df941d3f4 100644 --- a/hw/block/fdc.c +++ b/hw/block/fdc.c @@ -460,7 +460,6 @@ static const Property floppy_drive_properties[] = { DEFINE_PROP_SIGNED("drive-type", FloppyDrive, type, FLOPPY_DRIVE_TYPE_AUTO, qdev_prop_fdc_drive_type, FloppyDriveType), - DEFINE_PROP_END_OF_LIST(), }; static void floppy_drive_realize(DeviceState *qdev, Error **errp) diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index bc055c9d85..b84c6afb32 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -1729,7 +1729,6 @@ static const Property m25p80_properties[] = { DEFINE_PROP_UINT8("spansion-cr3nv", Flash, spansion_cr3nv, 0x2), DEFINE_PROP_UINT8("spansion-cr4nv", Flash, spansion_cr4nv, 0x10), DEFINE_PROP_DRIVE("drive", Flash, blk), - DEFINE_PROP_END_OF_LIST(), }; static int m25p80_pre_load(void *opaque) diff --git a/hw/block/nand.c b/hw/block/nand.c index 385deb2a91..e98c55b729 100644 --- a/hw/block/nand.c +++ b/hw/block/nand.c @@ -449,7 +449,6 @@ static const Property nand_properties[] = { DEFINE_PROP_UINT8("manufacturer_id", NANDFlashState, manf_id, 0), DEFINE_PROP_UINT8("chip_id", NANDFlashState, chip_id, 0), DEFINE_PROP_DRIVE("drive", NANDFlashState, blk), - DEFINE_PROP_END_OF_LIST(), }; static void nand_class_init(ObjectClass *klass, void *data) diff --git a/hw/block/pflash_cfi01.c b/hw/block/pflash_cfi01.c index 26bf6e4601..b5ea927f36 100644 --- a/hw/block/pflash_cfi01.c +++ b/hw/block/pflash_cfi01.c @@ -932,7 +932,6 @@ static const Property pflash_cfi01_properties[] = { DEFINE_PROP_STRING("name", PFlashCFI01, name), DEFINE_PROP_BOOL("old-multiple-chip-handling", PFlashCFI01, old_multiple_chip_handling, false), - DEFINE_PROP_END_OF_LIST(), }; static void pflash_cfi01_class_init(ObjectClass *klass, void *data) diff --git a/hw/block/pflash_cfi02.c b/hw/block/pflash_cfi02.c index 6a7d16b855..315a53629a 100644 --- a/hw/block/pflash_cfi02.c +++ b/hw/block/pflash_cfi02.c @@ -959,7 +959,6 @@ static const Property pflash_cfi02_properties[] = { DEFINE_PROP_UINT16("unlock-addr0", PFlashCFI02, unlock_addr0, 0), DEFINE_PROP_UINT16("unlock-addr1", PFlashCFI02, unlock_addr1, 0), DEFINE_PROP_STRING("name", PFlashCFI02, name), - DEFINE_PROP_END_OF_LIST(), }; static void pflash_cfi02_unrealize(DeviceState *dev) diff --git a/hw/block/swim.c b/hw/block/swim.c index 7b392e0dea..4645468dcf 100644 --- a/hw/block/swim.c +++ b/hw/block/swim.c @@ -169,7 +169,6 @@ static const BlockDevOps swim_block_ops = { static const Property swim_drive_properties[] = { DEFINE_PROP_INT32("unit", SWIMDrive, unit, -1), DEFINE_BLOCK_PROPERTIES(SWIMDrive, conf), - DEFINE_PROP_END_OF_LIST(), }; static void swim_drive_realize(DeviceState *qdev, Error **errp) diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 879913a42b..ae42327cf8 100644 --- a/hw/block/vhost-user-blk.c +++ b/hw/block/vhost-user-blk.c @@ -581,7 +581,6 @@ static const Property vhost_user_blk_properties[] = { VIRTIO_BLK_F_DISCARD, true), DEFINE_PROP_BIT64("write-zeroes", VHostUserBlk, parent_obj.host_features, VIRTIO_BLK_F_WRITE_ZEROES, true), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_user_blk_class_init(ObjectClass *klass, void *data) diff --git a/hw/block/virtio-blk.c b/hw/block/virtio-blk.c index 89d9279eda..8806c03f7c 100644 --- a/hw/block/virtio-blk.c +++ b/hw/block/virtio-blk.c @@ -2014,7 +2014,6 @@ static const Property virtio_blk_properties[] = { conf.max_write_zeroes_sectors, BDRV_REQUEST_MAX_SECTORS), DEFINE_PROP_BOOL("x-enable-wce-if-config-wce", VirtIOBlock, conf.x_enable_wce_if_config_wce, true), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_blk_class_init(ObjectClass *klass, void *data) diff --git a/hw/block/xen-block.c b/hw/block/xen-block.c index 990d8f3d76..306d38927c 100644 --- a/hw/block/xen-block.c +++ b/hw/block/xen-block.c @@ -485,7 +485,7 @@ static char *disk_to_vbd_name(unsigned int disk) static void xen_block_get_vdev(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; XenBlockVdev *vdev = object_field_prop_ptr(obj, prop); char *str; @@ -545,7 +545,7 @@ static int vbd_name_to_disk(const char *name, const char **endp, static void xen_block_set_vdev(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; XenBlockVdev *vdev = object_field_prop_ptr(obj, prop); char *str, *p; const char *end; @@ -674,7 +674,6 @@ static const Property xen_block_props[] = { props.max_ring_page_order, 4), DEFINE_PROP_LINK("iothread", XenBlockDevice, props.iothread, TYPE_IOTHREAD, IOThread *), - DEFINE_PROP_END_OF_LIST() }; static void xen_block_class_init(ObjectClass *class, void *data) diff --git a/hw/char/avr_usart.c b/hw/char/avr_usart.c index 3421576e45..e8012cae3a 100644 --- a/hw/char/avr_usart.c +++ b/hw/char/avr_usart.c @@ -261,7 +261,6 @@ static const MemoryRegionOps avr_usart_ops = { static const Property avr_usart_properties[] = { DEFINE_PROP_CHR("chardev", AVRUsartState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void avr_usart_pr(void *opaque, int irq, int level) diff --git a/hw/char/bcm2835_aux.c b/hw/char/bcm2835_aux.c index 30285c97b0..73ad593406 100644 --- a/hw/char/bcm2835_aux.c +++ b/hw/char/bcm2835_aux.c @@ -292,7 +292,6 @@ static void bcm2835_aux_realize(DeviceState *dev, Error **errp) static const Property bcm2835_aux_props[] = { DEFINE_PROP_CHR("chardev", BCM2835AuxState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void bcm2835_aux_class_init(ObjectClass *oc, void *data) diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c index 2e778f7a9c..ebd846a083 100644 --- a/hw/char/cadence_uart.c +++ b/hw/char/cadence_uart.c @@ -619,7 +619,6 @@ static const VMStateDescription vmstate_cadence_uart = { static const Property cadence_uart_properties[] = { DEFINE_PROP_CHR("chardev", CadenceUARTState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void cadence_uart_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/cmsdk-apb-uart.c b/hw/char/cmsdk-apb-uart.c index e37e14e0f2..0506500215 100644 --- a/hw/char/cmsdk-apb-uart.c +++ b/hw/char/cmsdk-apb-uart.c @@ -380,7 +380,6 @@ static const VMStateDescription cmsdk_apb_uart_vmstate = { static const Property cmsdk_apb_uart_properties[] = { DEFINE_PROP_CHR("chardev", CMSDKAPBUART, chr), DEFINE_PROP_UINT32("pclk-frq", CMSDKAPBUART, pclk_frq, 0), - DEFINE_PROP_END_OF_LIST(), }; static void cmsdk_apb_uart_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/debugcon.c b/hw/char/debugcon.c index c0f16e9bd6..1bc3bf85fe 100644 --- a/hw/char/debugcon.c +++ b/hw/char/debugcon.c @@ -118,7 +118,6 @@ static const Property debugcon_isa_properties[] = { DEFINE_PROP_UINT32("iobase", ISADebugconState, iobase, 0xe9), DEFINE_PROP_CHR("chardev", ISADebugconState, state.chr), DEFINE_PROP_UINT32("readback", ISADebugconState, state.readback, 0xe9), - DEFINE_PROP_END_OF_LIST(), }; static void debugcon_isa_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/char/digic-uart.c b/hw/char/digic-uart.c index 03beba11ad..b0b0714e0f 100644 --- a/hw/char/digic-uart.c +++ b/hw/char/digic-uart.c @@ -174,7 +174,6 @@ static const VMStateDescription vmstate_digic_uart = { static const Property digic_uart_properties[] = { DEFINE_PROP_CHR("chardev", DigicUartState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void digic_uart_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/escc.c b/hw/char/escc.c index 08bc65ef2c..a5fdd8f698 100644 --- a/hw/char/escc.c +++ b/hw/char/escc.c @@ -1099,7 +1099,6 @@ static const Property escc_properties[] = { DEFINE_PROP_CHR("chrB", ESCCState, chn[0].chr), DEFINE_PROP_CHR("chrA", ESCCState, chn[1].chr), DEFINE_PROP_STRING("chnA-sunkbd-layout", ESCCState, chn[1].sunkbd_layout), - DEFINE_PROP_END_OF_LIST(), }; static void escc_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/exynos4210_uart.c b/hw/char/exynos4210_uart.c index c2836ff8fd..a1a9a12caf 100644 --- a/hw/char/exynos4210_uart.c +++ b/hw/char/exynos4210_uart.c @@ -709,7 +709,6 @@ static const Property exynos4210_uart_properties[] = { DEFINE_PROP_UINT32("channel", Exynos4210UartState, channel, 0), DEFINE_PROP_UINT32("rx-size", Exynos4210UartState, rx.size, 16), DEFINE_PROP_UINT32("tx-size", Exynos4210UartState, tx.size, 16), - DEFINE_PROP_END_OF_LIST(), }; static void exynos4210_uart_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/goldfish_tty.c b/hw/char/goldfish_tty.c index e3461e00a8..7374561141 100644 --- a/hw/char/goldfish_tty.c +++ b/hw/char/goldfish_tty.c @@ -243,7 +243,6 @@ static const VMStateDescription vmstate_goldfish_tty = { static const Property goldfish_tty_properties[] = { DEFINE_PROP_CHR("chardev", GoldfishTTYState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void goldfish_tty_instance_init(Object *obj) diff --git a/hw/char/grlib_apbuart.c b/hw/char/grlib_apbuart.c index caae88d77d..db6bcdad41 100644 --- a/hw/char/grlib_apbuart.c +++ b/hw/char/grlib_apbuart.c @@ -279,7 +279,6 @@ static void grlib_apbuart_reset(DeviceState *d) static const Property grlib_apbuart_properties[] = { DEFINE_PROP_CHR("chrdev", UART, chr), - DEFINE_PROP_END_OF_LIST(), }; static void grlib_apbuart_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/ibex_uart.c b/hw/char/ibex_uart.c index b1bdb2ad15..392375ad55 100644 --- a/hw/char/ibex_uart.c +++ b/hw/char/ibex_uart.c @@ -510,7 +510,6 @@ static const VMStateDescription vmstate_ibex_uart = { static const Property ibex_uart_properties[] = { DEFINE_PROP_CHR("chardev", IbexUartState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void ibex_uart_init(Object *obj) diff --git a/hw/char/imx_serial.c b/hw/char/imx_serial.c index 6376f2cadc..12705a1337 100644 --- a/hw/char/imx_serial.c +++ b/hw/char/imx_serial.c @@ -440,7 +440,6 @@ static void imx_serial_init(Object *obj) static const Property imx_serial_properties[] = { DEFINE_PROP_CHR("chardev", IMXSerialState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void imx_serial_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/ipoctal232.c b/hw/char/ipoctal232.c index fb8cb6c2b7..d1e5f6dad2 100644 --- a/hw/char/ipoctal232.c +++ b/hw/char/ipoctal232.c @@ -567,7 +567,6 @@ static const Property ipoctal_properties[] = { DEFINE_PROP_CHR("chardev5", IPOctalState, ch[5].dev), DEFINE_PROP_CHR("chardev6", IPOctalState, ch[6].dev), DEFINE_PROP_CHR("chardev7", IPOctalState, ch[7].dev), - DEFINE_PROP_END_OF_LIST(), }; static void ipoctal_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/mcf_uart.c b/hw/char/mcf_uart.c index c044536d5d..980a12fcb7 100644 --- a/hw/char/mcf_uart.c +++ b/hw/char/mcf_uart.c @@ -314,7 +314,6 @@ static void mcf_uart_realize(DeviceState *dev, Error **errp) static const Property mcf_uart_properties[] = { DEFINE_PROP_CHR("chardev", mcf_uart_state, chr), - DEFINE_PROP_END_OF_LIST(), }; static void mcf_uart_class_init(ObjectClass *oc, void *data) diff --git a/hw/char/nrf51_uart.c b/hw/char/nrf51_uart.c index b164c70f52..82a61ee95f 100644 --- a/hw/char/nrf51_uart.c +++ b/hw/char/nrf51_uart.c @@ -306,7 +306,6 @@ static const VMStateDescription nrf51_uart_vmstate = { static const Property nrf51_uart_properties[] = { DEFINE_PROP_CHR("chardev", NRF51UARTState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void nrf51_uart_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/parallel.c b/hw/char/parallel.c index 6560341419..e1651d52a4 100644 --- a/hw/char/parallel.c +++ b/hw/char/parallel.c @@ -608,7 +608,6 @@ static const Property parallel_isa_properties[] = { DEFINE_PROP_UINT32("iobase", ISAParallelState, iobase, -1), DEFINE_PROP_UINT32("irq", ISAParallelState, isairq, 7), DEFINE_PROP_CHR("chardev", ISAParallelState, state.chr), - DEFINE_PROP_END_OF_LIST(), }; static void parallel_isa_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/char/pl011.c b/hw/char/pl011.c index 5fbee5e6c5..06ce851044 100644 --- a/hw/char/pl011.c +++ b/hw/char/pl011.c @@ -606,7 +606,6 @@ static const VMStateDescription vmstate_pl011 = { static const Property pl011_properties[] = { DEFINE_PROP_CHR("chardev", PL011State, chr), DEFINE_PROP_BOOL("migrate-clk", PL011State, migrate_clk, true), - DEFINE_PROP_END_OF_LIST(), }; static void pl011_init(Object *obj) diff --git a/hw/char/renesas_sci.c b/hw/char/renesas_sci.c index 516b48648b..ea94494932 100644 --- a/hw/char/renesas_sci.c +++ b/hw/char/renesas_sci.c @@ -322,7 +322,6 @@ static const VMStateDescription vmstate_rsci = { static const Property rsci_properties[] = { DEFINE_PROP_UINT64("input-freq", RSCIState, input_freq, 0), DEFINE_PROP_CHR("chardev", RSCIState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void rsci_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 2a283a2dec..11a0e1a7b7 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -212,11 +212,11 @@ static void htif_handle_tohost_write(HTIFState *s, uint64_t val_written) } else { uint64_t syscall[8]; cpu_physical_memory_read(payload, syscall, sizeof(syscall)); - if (tswap64(syscall[0]) == PK_SYS_WRITE && - tswap64(syscall[1]) == HTIF_DEV_CONSOLE && - tswap64(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) { + if (le64_to_cpu(syscall[0]) == PK_SYS_WRITE && + le64_to_cpu(syscall[1]) == HTIF_DEV_CONSOLE && + le64_to_cpu(syscall[3]) == HTIF_CONSOLE_CMD_PUTC) { uint8_t ch; - cpu_physical_memory_read(tswap64(syscall[2]), &ch, 1); + cpu_physical_memory_read(le64_to_cpu(syscall[2]), &ch, 1); /* * XXX this blocks entire thread. Rewrite to use * qemu_chr_fe_write and background I/O callbacks @@ -324,6 +324,11 @@ static void htif_mm_write(void *opaque, hwaddr addr, static const MemoryRegionOps htif_mm_ops = { .read = htif_mm_read, .write = htif_mm_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .impl = { + .min_access_size = 4, + .max_access_size = 4, + }, }; HTIFState *htif_mm_init(MemoryRegion *address_space, Chardev *chr, diff --git a/hw/char/sclpconsole-lm.c b/hw/char/sclpconsole-lm.c index 536b283471..ddb9a726d5 100644 --- a/hw/char/sclpconsole-lm.c +++ b/hw/char/sclpconsole-lm.c @@ -337,7 +337,6 @@ static const Property console_properties[] = { DEFINE_PROP_CHR("chardev", SCLPConsoleLM, chr), DEFINE_PROP_UINT32("write_errors", SCLPConsoleLM, write_errors, 0), DEFINE_PROP_BOOL("echo", SCLPConsoleLM, echo, true), - DEFINE_PROP_END_OF_LIST(), }; static void console_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/sclpconsole.c b/hw/char/sclpconsole.c index a90b892d1d..01233b933d 100644 --- a/hw/char/sclpconsole.c +++ b/hw/char/sclpconsole.c @@ -253,7 +253,6 @@ static void console_reset(DeviceState *dev) static const Property console_properties[] = { DEFINE_PROP_CHR("chardev", SCLPConsole, chr), - DEFINE_PROP_END_OF_LIST(), }; static void console_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c index 9472abf917..3d913891dc 100644 --- a/hw/char/serial-isa.c +++ b/hw/char/serial-isa.c @@ -117,7 +117,6 @@ static const Property serial_isa_properties[] = { DEFINE_PROP_UINT32("index", ISASerialState, index, -1), DEFINE_PROP_UINT32("iobase", ISASerialState, iobase, -1), DEFINE_PROP_UINT32("irq", ISASerialState, isairq, -1), - DEFINE_PROP_END_OF_LIST(), }; static void serial_isa_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/char/serial-mm.c b/hw/char/serial-mm.c index 8f51f1d3b8..6338e7c0ba 100644 --- a/hw/char/serial-mm.c +++ b/hw/char/serial-mm.c @@ -132,7 +132,6 @@ static const Property serial_mm_properties[] = { */ DEFINE_PROP_UINT8("regshift", SerialMM, regshift, 0), DEFINE_PROP_UINT8("endianness", SerialMM, endianness, DEVICE_NATIVE_ENDIAN), - DEFINE_PROP_END_OF_LIST(), }; static void serial_mm_class_init(ObjectClass *oc, void *data) diff --git a/hw/char/serial-pci-multi.c b/hw/char/serial-pci-multi.c index c2f20d8e74..7578e863cf 100644 --- a/hw/char/serial-pci-multi.c +++ b/hw/char/serial-pci-multi.c @@ -136,7 +136,6 @@ static const Property multi_2x_serial_pci_properties[] = { DEFINE_PROP_CHR("chardev1", PCIMultiSerialState, state[0].chr), DEFINE_PROP_CHR("chardev2", PCIMultiSerialState, state[1].chr), DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02), - DEFINE_PROP_END_OF_LIST(), }; static const Property multi_4x_serial_pci_properties[] = { @@ -145,7 +144,6 @@ static const Property multi_4x_serial_pci_properties[] = { DEFINE_PROP_CHR("chardev3", PCIMultiSerialState, state[2].chr), DEFINE_PROP_CHR("chardev4", PCIMultiSerialState, state[3].chr), DEFINE_PROP_UINT8("prog_if", PCIMultiSerialState, prog_if, 0x02), - DEFINE_PROP_END_OF_LIST(), }; static void multi_2x_serial_pci_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/char/serial-pci.c b/hw/char/serial-pci.c index 2f487a3a79..6659cef5d4 100644 --- a/hw/char/serial-pci.c +++ b/hw/char/serial-pci.c @@ -83,7 +83,6 @@ static const VMStateDescription vmstate_pci_serial = { static const Property serial_pci_properties[] = { DEFINE_PROP_UINT8("prog_if", PCISerialState, prog_if, 0x02), - DEFINE_PROP_END_OF_LIST(), }; static void serial_pci_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/char/serial.c b/hw/char/serial.c index 76a17f1a4b..70044e14a0 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -968,7 +968,6 @@ static const Property serial_properties[] = { DEFINE_PROP_CHR("chardev", SerialState, chr), DEFINE_PROP_UINT32("baudbase", SerialState, baudbase, 115200), DEFINE_PROP_BOOL("wakeup", SerialState, wakeup, false), - DEFINE_PROP_END_OF_LIST(), }; static void serial_class_init(ObjectClass *klass, void* data) diff --git a/hw/char/sh_serial.c b/hw/char/sh_serial.c index 2ab7197aee..247aeb071a 100644 --- a/hw/char/sh_serial.c +++ b/hw/char/sh_serial.c @@ -450,7 +450,6 @@ static void sh_serial_init(Object *obj) static const Property sh_serial_properties[] = { DEFINE_PROP_CHR("chardev", SHSerialState, chr), DEFINE_PROP_UINT8("features", SHSerialState, feat, 0), - DEFINE_PROP_END_OF_LIST() }; static void sh_serial_class_init(ObjectClass *oc, void *data) diff --git a/hw/char/shakti_uart.c b/hw/char/shakti_uart.c index 6e56754ca6..09975d9d34 100644 --- a/hw/char/shakti_uart.c +++ b/hw/char/shakti_uart.c @@ -159,7 +159,6 @@ static void shakti_uart_instance_init(Object *obj) static const Property shakti_uart_properties[] = { DEFINE_PROP_CHR("chardev", ShaktiUartState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void shakti_uart_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index 97e4be37c0..4bc5767284 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -253,7 +253,6 @@ static int sifive_uart_be_change(void *opaque) static const Property sifive_uart_properties[] = { DEFINE_PROP_CHR("chardev", SiFiveUARTState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void sifive_uart_init(Object *obj) diff --git a/hw/char/spapr_vty.c b/hw/char/spapr_vty.c index cd91dad709..6451d010ac 100644 --- a/hw/char/spapr_vty.c +++ b/hw/char/spapr_vty.c @@ -166,7 +166,6 @@ void spapr_vty_create(SpaprVioBus *bus, Chardev *chardev) static const Property spapr_vty_properties[] = { DEFINE_SPAPR_PROPERTIES(SpaprVioVty, sdev), DEFINE_PROP_CHR("chardev", SpaprVioVty, chardev), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_spapr_vty = { diff --git a/hw/char/stm32f2xx_usart.c b/hw/char/stm32f2xx_usart.c index 4a3c30eddb..ebcc510f4e 100644 --- a/hw/char/stm32f2xx_usart.c +++ b/hw/char/stm32f2xx_usart.c @@ -201,7 +201,6 @@ static const MemoryRegionOps stm32f2xx_usart_ops = { static const Property stm32f2xx_usart_properties[] = { DEFINE_PROP_CHR("chardev", STM32F2XXUsartState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void stm32f2xx_usart_init(Object *obj) diff --git a/hw/char/stm32l4x5_usart.c b/hw/char/stm32l4x5_usart.c index 360e79cc3f..bcc310bd97 100644 --- a/hw/char/stm32l4x5_usart.c +++ b/hw/char/stm32l4x5_usart.c @@ -536,7 +536,6 @@ static const MemoryRegionOps stm32l4x5_usart_base_ops = { static const Property stm32l4x5_usart_base_properties[] = { DEFINE_PROP_CHR("chardev", Stm32l4x5UsartBaseState, chr), - DEFINE_PROP_END_OF_LIST(), }; static void stm32l4x5_usart_base_init(Object *obj) diff --git a/hw/char/terminal3270.c b/hw/char/terminal3270.c index c2aafda0ce..04ee26dcbd 100644 --- a/hw/char/terminal3270.c +++ b/hw/char/terminal3270.c @@ -285,7 +285,6 @@ static int write_payload_3270(EmulatedCcw3270Device *dev, uint8_t cmd) static const Property terminal_properties[] = { DEFINE_PROP_CHR("chardev", Terminal3270, chr), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription terminal3270_vmstate = { diff --git a/hw/char/virtio-console.c b/hw/char/virtio-console.c index f58292e2bb..aa6d611a47 100644 --- a/hw/char/virtio-console.c +++ b/hw/char/virtio-console.c @@ -276,7 +276,6 @@ static const TypeInfo virtconsole_info = { static const Property virtserialport_properties[] = { DEFINE_PROP_CHR("chardev", VirtConsole, chr), - DEFINE_PROP_END_OF_LIST(), }; static void virtserialport_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index 1e631bcb2b..b6d2743a9c 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -838,7 +838,6 @@ static void virtser_bus_dev_print(Monitor *mon, DeviceState *qdev, int indent); static const Property virtser_props[] = { DEFINE_PROP_UINT32("nr", VirtIOSerialPort, id, VIRTIO_CONSOLE_BAD_ID), DEFINE_PROP_STRING("name", VirtIOSerialPort, name), - DEFINE_PROP_END_OF_LIST() }; static void virtser_bus_class_init(ObjectClass *klass, void *data) @@ -1158,7 +1157,6 @@ static const Property virtio_serial_properties[] = { 31), DEFINE_PROP_BIT64("emergency-write", VirtIOSerial, host_features, VIRTIO_CONSOLE_F_EMERG_WRITE, true), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_serial_class_init(ObjectClass *klass, void *data) diff --git a/hw/char/xen_console.c b/hw/char/xen_console.c index 88e12bb410..ef0c2912ef 100644 --- a/hw/char/xen_console.c +++ b/hw/char/xen_console.c @@ -490,7 +490,6 @@ static char *xen_console_get_frontend_path(XenDevice *xendev, Error **errp) static const Property xen_console_properties[] = { DEFINE_PROP_CHR("chardev", XenConsole, chr), DEFINE_PROP_INT32("idx", XenConsole, dev, -1), - DEFINE_PROP_END_OF_LIST(), }; static void xen_console_class_init(ObjectClass *class, void *data) diff --git a/hw/char/xilinx_uartlite.c b/hw/char/xilinx_uartlite.c index ad77226217..56955e0d74 100644 --- a/hw/char/xilinx_uartlite.c +++ b/hw/char/xilinx_uartlite.c @@ -178,7 +178,6 @@ static const MemoryRegionOps uart_ops = { static const Property xilinx_uartlite_properties[] = { DEFINE_PROP_CHR("chardev", XilinxUARTLite, chr), - DEFINE_PROP_END_OF_LIST(), }; static void uart_rx(void *opaque, const uint8_t *buf, int size) diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index fca9ac0e36..fb354693af 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -187,7 +187,6 @@ static const Property generic_loader_props[] = { DEFINE_PROP_UINT32("cpu-num", GenericLoaderState, cpu_num, CPU_NONE), DEFINE_PROP_BOOL("force-raw", GenericLoaderState, force_raw, false), DEFINE_PROP_STRING("file", GenericLoaderState, file), - DEFINE_PROP_END_OF_LIST(), }; static void generic_loader_class_init(ObjectClass *klass, void *data) diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c index fb23882786..76271df9f5 100644 --- a/hw/core/guest-loader.c +++ b/hw/core/guest-loader.c @@ -116,7 +116,6 @@ static const Property guest_loader_props[] = { DEFINE_PROP_STRING("kernel", GuestLoaderState, kernel), DEFINE_PROP_STRING("bootargs", GuestLoaderState, args), DEFINE_PROP_STRING("initrd", GuestLoaderState, initrd), - DEFINE_PROP_END_OF_LIST(), }; static void guest_loader_class_init(ObjectClass *klass, void *data) diff --git a/hw/core/or-irq.c b/hw/core/or-irq.c index fc52796f54..4d0d3cabf1 100644 --- a/hw/core/or-irq.c +++ b/hw/core/or-irq.c @@ -117,7 +117,6 @@ static const VMStateDescription vmstate_or_irq = { static const Property or_irq_properties[] = { DEFINE_PROP_UINT16("num-lines", OrIRQState, num_lines, 1), - DEFINE_PROP_END_OF_LIST(), }; static void or_irq_class_init(ObjectClass *klass, void *data) diff --git a/hw/core/platform-bus.c b/hw/core/platform-bus.c index a29c9c6e59..1d00c4d36d 100644 --- a/hw/core/platform-bus.c +++ b/hw/core/platform-bus.c @@ -207,7 +207,6 @@ static void platform_bus_realize(DeviceState *dev, Error **errp) static const Property platform_bus_properties[] = { DEFINE_PROP_UINT32("num_irqs", PlatformBusDevice, num_irqs, 0), DEFINE_PROP_UINT32("mmio_size", PlatformBusDevice, mmio_size, 0), - DEFINE_PROP_END_OF_LIST() }; static void platform_bus_class_init(ObjectClass *klass, void *data) diff --git a/hw/core/qdev-properties-system.c b/hw/core/qdev-properties-system.c index c91c383511..a96675beb0 100644 --- a/hw/core/qdev-properties-system.c +++ b/hw/core/qdev-properties-system.c @@ -90,7 +90,7 @@ bool qdev_prop_sanitize_s390x_loadparm(uint8_t *loadparm, const char *str, static void get_drive(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; void **ptr = object_field_prop_ptr(obj, prop); const char *value; char *p; @@ -116,7 +116,7 @@ static void set_drive_helper(Object *obj, Visitor *v, const char *name, void *opaque, bool iothread, Error **errp) { DeviceState *dev = DEVICE(obj); - Property *prop = opaque; + const Property *prop = opaque; void **ptr = object_field_prop_ptr(obj, prop); char *str; BlockBackend *blk; @@ -225,7 +225,7 @@ static void set_drive_iothread(Object *obj, Visitor *v, const char *name, static void release_drive(Object *obj, const char *name, void *opaque) { DeviceState *dev = DEVICE(obj); - Property *prop = opaque; + const Property *prop = opaque; BlockBackend **ptr = object_field_prop_ptr(obj, prop); if (*ptr) { @@ -269,7 +269,7 @@ static void set_chr(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ERRP_GUARD(); - Property *prop = opaque; + const Property *prop = opaque; CharBackend *be = object_field_prop_ptr(obj, prop); Chardev *s; char *str; @@ -305,7 +305,7 @@ static void set_chr(Object *obj, Visitor *v, const char *name, void *opaque, static void release_chr(Object *obj, const char *name, void *opaque) { - Property *prop = opaque; + const Property *prop = opaque; CharBackend *be = object_field_prop_ptr(obj, prop); qemu_chr_fe_deinit(be, false); @@ -329,7 +329,7 @@ const PropertyInfo qdev_prop_chr = { static void get_mac(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; MACAddr *mac = object_field_prop_ptr(obj, prop); char buffer[2 * 6 + 5 + 1]; char *p = buffer; @@ -344,7 +344,7 @@ static void get_mac(Object *obj, Visitor *v, const char *name, void *opaque, static void set_mac(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; MACAddr *mac = object_field_prop_ptr(obj, prop); int i, pos; char *str; @@ -406,7 +406,7 @@ void qdev_prop_set_macaddr(DeviceState *dev, const char *name, static void get_netdev(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; NICPeers *peers_ptr = object_field_prop_ptr(obj, prop); char *p = g_strdup(peers_ptr->ncs[0] ? peers_ptr->ncs[0]->name : ""); @@ -417,7 +417,7 @@ static void get_netdev(Object *obj, Visitor *v, const char *name, static void set_netdev(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; NICPeers *peers_ptr = object_field_prop_ptr(obj, prop); NetClientState **ncs = peers_ptr->ncs; NetClientState *peers[MAX_QUEUE_NUM]; @@ -485,7 +485,7 @@ const PropertyInfo qdev_prop_netdev = { static void get_audiodev(Object *obj, Visitor *v, const char* name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; QEMUSoundCard *card = object_field_prop_ptr(obj, prop); char *p = g_strdup(audio_get_id(card)); @@ -496,7 +496,7 @@ static void get_audiodev(Object *obj, Visitor *v, const char* name, static void set_audiodev(Object *obj, Visitor *v, const char* name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; QEMUSoundCard *card = object_field_prop_ptr(obj, prop); AudioState *state; g_autofree char *str = NULL; @@ -578,7 +578,7 @@ static void qdev_propinfo_set_losttickpolicy(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; int *ptr = object_field_prop_ptr(obj, prop); int value; @@ -614,7 +614,7 @@ const PropertyInfo qdev_prop_losttickpolicy = { static void set_blocksize(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint32_t *ptr = object_field_prop_ptr(obj, prop); uint64_t value; @@ -737,7 +737,7 @@ const PropertyInfo qdev_prop_zero_page_detection = { static void get_reserved_region(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; ReservedRegion *rr = object_field_prop_ptr(obj, prop); char buffer[64]; char *p = buffer; @@ -753,7 +753,7 @@ static void get_reserved_region(Object *obj, Visitor *v, const char *name, static void set_reserved_region(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; ReservedRegion *rr = object_field_prop_ptr(obj, prop); const char *endptr; uint64_t lob, upb; @@ -815,7 +815,7 @@ const PropertyInfo qdev_prop_reserved_region = { static void set_pci_devfn(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; g_autofree GenericAlternate *alt; int32_t value, *ptr = object_field_prop_ptr(obj, prop); unsigned int slot, fn, n; @@ -869,7 +869,7 @@ out: visit_end_alternate(v, (void **) &alt); } -static int print_pci_devfn(Object *obj, Property *prop, char *dest, +static int print_pci_devfn(Object *obj, const Property *prop, char *dest, size_t len) { int32_t *ptr = object_field_prop_ptr(obj, prop); @@ -895,7 +895,7 @@ const PropertyInfo qdev_prop_pci_devfn = { static void get_pci_host_devaddr(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; PCIHostDeviceAddress *addr = object_field_prop_ptr(obj, prop); char buffer[] = "ffff:ff:ff.f"; char *p = buffer; @@ -921,7 +921,7 @@ static void get_pci_host_devaddr(Object *obj, Visitor *v, const char *name, static void set_pci_host_devaddr(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; PCIHostDeviceAddress *addr = object_field_prop_ptr(obj, prop); char *str, *p; char *e; @@ -1011,7 +1011,7 @@ const PropertyInfo qdev_prop_off_auto_pcibar = { static void get_prop_pcielinkspeed(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; PCIExpLinkSpeed *p = object_field_prop_ptr(obj, prop); int speed; @@ -1045,7 +1045,7 @@ static void get_prop_pcielinkspeed(Object *obj, Visitor *v, const char *name, static void set_prop_pcielinkspeed(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; PCIExpLinkSpeed *p = object_field_prop_ptr(obj, prop); int speed; @@ -1093,7 +1093,7 @@ const PropertyInfo qdev_prop_pcie_link_speed = { static void get_prop_pcielinkwidth(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; PCIExpLinkWidth *p = object_field_prop_ptr(obj, prop); int width; @@ -1130,7 +1130,7 @@ static void get_prop_pcielinkwidth(Object *obj, Visitor *v, const char *name, static void set_prop_pcielinkwidth(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; PCIExpLinkWidth *p = object_field_prop_ptr(obj, prop); int width; @@ -1181,7 +1181,7 @@ const PropertyInfo qdev_prop_pcie_link_width = { static void get_uuid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; QemuUUID *uuid = object_field_prop_ptr(obj, prop); char buffer[UUID_STR_LEN]; char *p = buffer; @@ -1196,7 +1196,7 @@ static void get_uuid(Object *obj, Visitor *v, const char *name, void *opaque, static void set_uuid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; QemuUUID *uuid = object_field_prop_ptr(obj, prop); char *str; diff --git a/hw/core/qdev-properties.c b/hw/core/qdev-properties.c index 315196bd85..434a76f503 100644 --- a/hw/core/qdev-properties.c +++ b/hw/core/qdev-properties.c @@ -51,7 +51,7 @@ void qdev_prop_allow_set_link_before_realize(const Object *obj, } } -void *object_field_prop_ptr(Object *obj, Property *prop) +void *object_field_prop_ptr(Object *obj, const Property *prop) { void *ptr = obj; ptr += prop->offset; @@ -61,7 +61,7 @@ void *object_field_prop_ptr(Object *obj, Property *prop) static void field_prop_get(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; return prop->info->get(obj, v, name, opaque, errp); } @@ -78,7 +78,7 @@ static ObjectPropertyAccessor *field_prop_getter(const PropertyInfo *info) static void field_prop_set(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; if (!qdev_prop_allow_set(obj, name, prop->info, errp)) { return; @@ -100,7 +100,7 @@ static ObjectPropertyAccessor *field_prop_setter(const PropertyInfo *info) void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; int *ptr = object_field_prop_ptr(obj, prop); visit_type_enum(v, name, ptr, prop->info->enum_table, errp); @@ -109,7 +109,7 @@ void qdev_propinfo_get_enum(Object *obj, Visitor *v, const char *name, void qdev_propinfo_set_enum(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; int *ptr = object_field_prop_ptr(obj, prop); visit_type_enum(v, name, ptr, prop->info->enum_table, errp); @@ -131,13 +131,13 @@ const PropertyInfo qdev_prop_enum = { /* Bit */ -static uint32_t qdev_get_prop_mask(Property *prop) +static uint32_t qdev_get_prop_mask(const Property *prop) { assert(prop->info == &qdev_prop_bit); return 0x1 << prop->bitnr; } -static void bit_prop_set(Object *obj, Property *props, bool val) +static void bit_prop_set(Object *obj, const Property *props, bool val) { uint32_t *p = object_field_prop_ptr(obj, props); uint32_t mask = qdev_get_prop_mask(props); @@ -151,7 +151,7 @@ static void bit_prop_set(Object *obj, Property *props, bool val) static void prop_get_bit(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint32_t *p = object_field_prop_ptr(obj, prop); bool value = (*p & qdev_get_prop_mask(prop)) != 0; @@ -161,7 +161,7 @@ static void prop_get_bit(Object *obj, Visitor *v, const char *name, static void prop_set_bit(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; bool value; if (!visit_type_bool(v, name, &value, errp)) { @@ -185,13 +185,13 @@ const PropertyInfo qdev_prop_bit = { /* Bit64 */ -static uint64_t qdev_get_prop_mask64(Property *prop) +static uint64_t qdev_get_prop_mask64(const Property *prop) { assert(prop->info == &qdev_prop_bit64); return 0x1ull << prop->bitnr; } -static void bit64_prop_set(Object *obj, Property *props, bool val) +static void bit64_prop_set(Object *obj, const Property *props, bool val) { uint64_t *p = object_field_prop_ptr(obj, props); uint64_t mask = qdev_get_prop_mask64(props); @@ -205,7 +205,7 @@ static void bit64_prop_set(Object *obj, Property *props, bool val) static void prop_get_bit64(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint64_t *p = object_field_prop_ptr(obj, prop); bool value = (*p & qdev_get_prop_mask64(prop)) != 0; @@ -215,7 +215,7 @@ static void prop_get_bit64(Object *obj, Visitor *v, const char *name, static void prop_set_bit64(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; bool value; if (!visit_type_bool(v, name, &value, errp)) { @@ -237,7 +237,7 @@ const PropertyInfo qdev_prop_bit64 = { static void get_bool(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; bool *ptr = object_field_prop_ptr(obj, prop); visit_type_bool(v, name, ptr, errp); @@ -246,7 +246,7 @@ static void get_bool(Object *obj, Visitor *v, const char *name, void *opaque, static void set_bool(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; bool *ptr = object_field_prop_ptr(obj, prop); visit_type_bool(v, name, ptr, errp); @@ -264,7 +264,7 @@ const PropertyInfo qdev_prop_bool = { static void get_uint8(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint8_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint8(v, name, ptr, errp); @@ -273,7 +273,7 @@ static void get_uint8(Object *obj, Visitor *v, const char *name, void *opaque, static void set_uint8(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint8_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint8(v, name, ptr, errp); @@ -303,7 +303,7 @@ const PropertyInfo qdev_prop_uint8 = { static void get_uint16(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint16_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint16(v, name, ptr, errp); @@ -312,7 +312,7 @@ static void get_uint16(Object *obj, Visitor *v, const char *name, static void set_uint16(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint16_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint16(v, name, ptr, errp); @@ -330,7 +330,7 @@ const PropertyInfo qdev_prop_uint16 = { static void get_uint32(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint32_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint32(v, name, ptr, errp); @@ -339,7 +339,7 @@ static void get_uint32(Object *obj, Visitor *v, const char *name, static void set_uint32(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint32_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint32(v, name, ptr, errp); @@ -348,7 +348,7 @@ static void set_uint32(Object *obj, Visitor *v, const char *name, void qdev_propinfo_get_int32(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; int32_t *ptr = object_field_prop_ptr(obj, prop); visit_type_int32(v, name, ptr, errp); @@ -357,7 +357,7 @@ void qdev_propinfo_get_int32(Object *obj, Visitor *v, const char *name, static void set_int32(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; int32_t *ptr = object_field_prop_ptr(obj, prop); visit_type_int32(v, name, ptr, errp); @@ -382,7 +382,7 @@ const PropertyInfo qdev_prop_int32 = { static void get_uint64(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint64_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint64(v, name, ptr, errp); @@ -391,7 +391,7 @@ static void get_uint64(Object *obj, Visitor *v, const char *name, static void set_uint64(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint64_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint64(v, name, ptr, errp); @@ -400,7 +400,7 @@ static void set_uint64(Object *obj, Visitor *v, const char *name, static void get_int64(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; int64_t *ptr = object_field_prop_ptr(obj, prop); visit_type_int64(v, name, ptr, errp); @@ -409,7 +409,7 @@ static void get_int64(Object *obj, Visitor *v, const char *name, static void set_int64(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; int64_t *ptr = object_field_prop_ptr(obj, prop); visit_type_int64(v, name, ptr, errp); @@ -432,7 +432,7 @@ const PropertyInfo qdev_prop_int64 = { static void set_uint64_checkmask(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint64_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint64(v, name, ptr, errp); @@ -452,14 +452,14 @@ const PropertyInfo qdev_prop_uint64_checkmask = { static void release_string(Object *obj, const char *name, void *opaque) { - Property *prop = opaque; + const Property *prop = opaque; g_free(*(char **)object_field_prop_ptr(obj, prop)); } static void get_string(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; char **ptr = object_field_prop_ptr(obj, prop); if (!*ptr) { @@ -473,7 +473,7 @@ static void get_string(Object *obj, Visitor *v, const char *name, static void set_string(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; char **ptr = object_field_prop_ptr(obj, prop); char *str; @@ -507,7 +507,7 @@ const PropertyInfo qdev_prop_on_off_auto = { void qdev_propinfo_get_size32(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint32_t *ptr = object_field_prop_ptr(obj, prop); uint64_t value = *ptr; @@ -517,7 +517,7 @@ void qdev_propinfo_get_size32(Object *obj, Visitor *v, const char *name, static void set_size32(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint32_t *ptr = object_field_prop_ptr(obj, prop); uint64_t value; @@ -557,7 +557,7 @@ struct ArrayElementList { * specific element of the array. Arrays are backed by an uint32_t length field * and an element array. @elem points at an element in this element array. */ -static Property array_elem_prop(Object *obj, Property *parent_prop, +static Property array_elem_prop(Object *obj, const Property *parent_prop, const char *name, char *elem) { return (Property) { @@ -582,7 +582,7 @@ static Property array_elem_prop(Object *obj, Property *parent_prop, */ static void release_prop_array(Object *obj, const char *name, void *opaque) { - Property *prop = opaque; + const Property *prop = opaque; uint32_t *alenptr = object_field_prop_ptr(obj, prop); void **arrayptr = (void *)obj + prop->arrayoffset; char *elem = *arrayptr; @@ -609,7 +609,7 @@ static void set_prop_array(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ERRP_GUARD(); - Property *prop = opaque; + const Property *prop = opaque; uint32_t *alenptr = object_field_prop_ptr(obj, prop); void **arrayptr = (void *)obj + prop->arrayoffset; ArrayElementList *list, *elem, *next; @@ -685,7 +685,7 @@ static void get_prop_array(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { ERRP_GUARD(); - Property *prop = opaque; + const Property *prop = opaque; uint32_t *alenptr = object_field_prop_ptr(obj, prop); void **arrayptr = (void *)obj + prop->arrayoffset; char *elemptr = *arrayptr; @@ -749,16 +749,13 @@ const PropertyInfo qdev_prop_array = { /* --- public helpers --- */ -static const Property *qdev_prop_walk(const Property *props, const char *name) +static const Property *qdev_prop_walk(DeviceClass *cls, const char *name) { - if (!props) { - return NULL; - } - while (props->name) { - if (strcmp(props->name, name) == 0) { - return props; + for (int i = 0, n = cls->props_count_; i < n; ++i) { + const Property *prop = &cls->props_[i]; + if (strcmp(prop->name, name) == 0) { + return prop; } - props++; } return NULL; } @@ -771,7 +768,7 @@ static const Property *qdev_prop_find(DeviceState *dev, const char *name) /* device properties */ class = object_get_class(OBJECT(dev)); do { - prop = qdev_prop_walk(DEVICE_CLASS(class)->props_, name); + prop = qdev_prop_walk(DEVICE_CLASS(class), name); if (prop) { return prop; } @@ -931,7 +928,7 @@ void qdev_prop_set_globals(DeviceState *dev) static void get_size(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint64_t *ptr = object_field_prop_ptr(obj, prop); visit_type_size(v, name, ptr, errp); @@ -940,7 +937,7 @@ static void get_size(Object *obj, Visitor *v, const char *name, void *opaque, static void set_size(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint64_t *ptr = object_field_prop_ptr(obj, prop); visit_type_size(v, name, ptr, errp); @@ -1023,7 +1020,7 @@ static void qdev_get_legacy_property(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; char buffer[1024]; char *ptr = buffer; @@ -1061,12 +1058,18 @@ static void qdev_class_add_legacy_property(DeviceClass *dc, const Property *prop NULL, NULL, (Property *)prop); } -void device_class_set_props(DeviceClass *dc, const Property *props) +void device_class_set_props_n(DeviceClass *dc, const Property *props, size_t n) { - const Property *prop; + /* We used a hole in DeviceClass because that's still a lot. */ + assert(n <= UINT16_MAX); + assert(n != 0); dc->props_ = props; - for (prop = props; prop && prop->name; prop++) { + dc->props_count_ = n; + + for (size_t i = 0; i < n; ++i) { + const Property *prop = &props[i]; + assert(prop->name); qdev_class_add_legacy_property(dc, prop); qdev_class_add_property(dc, prop->name, prop); } diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 5f13111b77..57c1d9df3a 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -703,6 +703,7 @@ static void device_class_base_init(ObjectClass *class, void *data) * so do not propagate them to the subclasses. */ klass->props_ = NULL; + klass->props_count_ = 0; } static void device_unparent(Object *obj) diff --git a/hw/core/split-irq.c b/hw/core/split-irq.c index 40fc7e2e77..fc12274811 100644 --- a/hw/core/split-irq.c +++ b/hw/core/split-irq.c @@ -61,7 +61,6 @@ static void split_irq_realize(DeviceState *dev, Error **errp) static const Property split_irq_properties[] = { DEFINE_PROP_UINT16("num-lines", SplitIRQ, num_lines, 1), - DEFINE_PROP_END_OF_LIST(), }; static void split_irq_class_init(ObjectClass *klass, void *data) diff --git a/hw/cpu/a15mpcore.c b/hw/cpu/a15mpcore.c index 993550583f..3b0897e54e 100644 --- a/hw/cpu/a15mpcore.c +++ b/hw/cpu/a15mpcore.c @@ -153,7 +153,6 @@ static const Property a15mp_priv_properties[] = { * Other boards may differ and should set this property appropriately. */ DEFINE_PROP_UINT32("num-irq", A15MPPrivState, num_irq, 160), - DEFINE_PROP_END_OF_LIST(), }; static void a15mp_priv_class_init(ObjectClass *klass, void *data) diff --git a/hw/cpu/a9mpcore.c b/hw/cpu/a9mpcore.c index c3fdfb92e1..9671585b5f 100644 --- a/hw/cpu/a9mpcore.c +++ b/hw/cpu/a9mpcore.c @@ -167,7 +167,6 @@ static const Property a9mp_priv_properties[] = { * Other boards may differ and should set this property appropriately. */ DEFINE_PROP_UINT32("num-irq", A9MPPrivState, num_irq, 96), - DEFINE_PROP_END_OF_LIST(), }; static void a9mp_priv_class_init(ObjectClass *klass, void *data) diff --git a/hw/cpu/arm11mpcore.c b/hw/cpu/arm11mpcore.c index 193fc182ab..94861a06d9 100644 --- a/hw/cpu/arm11mpcore.c +++ b/hw/cpu/arm11mpcore.c @@ -142,7 +142,6 @@ static const Property mpcore_priv_properties[] = { * has more IRQ lines than the kernel expects. */ DEFINE_PROP_UINT32("num-irq", ARM11MPCorePriveState, num_irq, 64), - DEFINE_PROP_END_OF_LIST(), }; static void mpcore_priv_class_init(ObjectClass *klass, void *data) diff --git a/hw/cpu/cluster.c b/hw/cpu/cluster.c index 8e43621b5c..9da5221f88 100644 --- a/hw/cpu/cluster.c +++ b/hw/cpu/cluster.c @@ -27,7 +27,6 @@ static const Property cpu_cluster_properties[] = { DEFINE_PROP_UINT32("cluster-id", CPUClusterState, cluster_id, 0), - DEFINE_PROP_END_OF_LIST() }; typedef struct CallbackData { diff --git a/hw/cpu/realview_mpcore.c b/hw/cpu/realview_mpcore.c index 9a0ff1df86..4268735e3a 100644 --- a/hw/cpu/realview_mpcore.c +++ b/hw/cpu/realview_mpcore.c @@ -110,7 +110,6 @@ static void mpcore_rirq_init(Object *obj) static const Property mpcore_rirq_properties[] = { DEFINE_PROP_UINT32("num-cpu", mpcore_rirq_state, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), }; static void mpcore_rirq_class_init(ObjectClass *klass, void *data) diff --git a/hw/cxl/switch-mailbox-cci.c b/hw/cxl/switch-mailbox-cci.c index 3fde0f8aae..65cdac6cc1 100644 --- a/hw/cxl/switch-mailbox-cci.c +++ b/hw/cxl/switch-mailbox-cci.c @@ -68,7 +68,6 @@ static void cswmbcci_exit(PCIDevice *pci_dev) static const Property cxl_switch_cci_props[] = { DEFINE_PROP_LINK("target", CSWMBCCIDev, target, TYPE_CXL_USP, PCIDevice *), - DEFINE_PROP_END_OF_LIST(), }; static void cswmbcci_class_init(ObjectClass *oc, void *data) diff --git a/hw/display/artist.c b/hw/display/artist.c index 49deed328d..8b719b11ed 100644 --- a/hw/display/artist.c +++ b/hw/display/artist.c @@ -1478,7 +1478,6 @@ static const Property artist_properties[] = { DEFINE_PROP_UINT16("width", ARTISTState, width, 1280), DEFINE_PROP_UINT16("height", ARTISTState, height, 1024), DEFINE_PROP_UINT16("depth", ARTISTState, depth, 8), - DEFINE_PROP_END_OF_LIST(), }; static void artist_reset(DeviceState *qdev) diff --git a/hw/display/ati.c b/hw/display/ati.c index e24e092bbc..864fa4fc2c 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -1047,7 +1047,6 @@ static const Property ati_vga_properties[] = { DEFINE_PROP_BOOL("guest_hwcursor", ATIVGAState, cursor_guest_mode, false), /* this is a debug option, prefer PROP_UINT over PROP_BIT for simplicity */ DEFINE_PROP_UINT8("x-pixman", ATIVGAState, use_pixman, DEFAULT_X_PIXMAN), - DEFINE_PROP_END_OF_LIST() }; static void ati_vga_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/bcm2835_fb.c b/hw/display/bcm2835_fb.c index 2539fcc8ab..a5bded5156 100644 --- a/hw/display/bcm2835_fb.c +++ b/hw/display/bcm2835_fb.c @@ -440,7 +440,6 @@ static const Property bcm2835_fb_props[] = { initial_config.pixo, 1), /* 1=RGB, 0=BGR */ DEFINE_PROP_UINT32("alpha", BCM2835FBState, initial_config.alpha, 2), /* alpha ignored */ - DEFINE_PROP_END_OF_LIST() }; static void bcm2835_fb_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/bochs-display.c b/hw/display/bochs-display.c index 9a3263aa01..086f7a0f06 100644 --- a/hw/display/bochs-display.c +++ b/hw/display/bochs-display.c @@ -349,7 +349,6 @@ static const Property bochs_display_properties[] = { DEFINE_PROP_SIZE("vgamem", BochsDisplayState, vgamem, 16 * MiB), DEFINE_PROP_BOOL("edid", BochsDisplayState, enable_edid, true), DEFINE_EDID_PROPERTIES(BochsDisplayState, edid_info), - DEFINE_PROP_END_OF_LIST(), }; static void bochs_display_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/cg3.c b/hw/display/cg3.c index 75b3312c24..3f971d875f 100644 --- a/hw/display/cg3.c +++ b/hw/display/cg3.c @@ -366,7 +366,6 @@ static const Property cg3_properties[] = { DEFINE_PROP_UINT16("width", CG3State, width, -1), DEFINE_PROP_UINT16("height", CG3State, height, -1), DEFINE_PROP_UINT16("depth", CG3State, depth, -1), - DEFINE_PROP_END_OF_LIST(), }; static void cg3_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/cirrus_vga.c b/hw/display/cirrus_vga.c index 6dbf06f6e9..76124d3656 100644 --- a/hw/display/cirrus_vga.c +++ b/hw/display/cirrus_vga.c @@ -2989,7 +2989,6 @@ static const Property pci_vga_cirrus_properties[] = { cirrus_vga.enable_blitter, true), DEFINE_PROP_BOOL("global-vmstate", struct PCICirrusVGAState, cirrus_vga.vga.global_vmstate, false), - DEFINE_PROP_END_OF_LIST(), }; static void cirrus_vga_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/cirrus_vga_isa.c b/hw/display/cirrus_vga_isa.c index d0d134470f..60b7fd20f1 100644 --- a/hw/display/cirrus_vga_isa.c +++ b/hw/display/cirrus_vga_isa.c @@ -74,7 +74,6 @@ static const Property isa_cirrus_vga_properties[] = { cirrus_vga.vga.vram_size_mb, 4), DEFINE_PROP_BOOL("blitter", struct ISACirrusVGAState, cirrus_vga.enable_blitter, true), - DEFINE_PROP_END_OF_LIST(), }; static void isa_cirrus_vga_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/exynos4210_fimd.c b/hw/display/exynos4210_fimd.c index 4f097a172c..04c864a308 100644 --- a/hw/display/exynos4210_fimd.c +++ b/hw/display/exynos4210_fimd.c @@ -1928,7 +1928,6 @@ static const GraphicHwOps exynos4210_fimd_ops = { static const Property exynos4210_fimd_properties[] = { DEFINE_PROP_LINK("framebuffer-memory", Exynos4210fimdState, fbmem, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void exynos4210_fimd_init(Object *obj) diff --git a/hw/display/g364fb.c b/hw/display/g364fb.c index a7533c6908..30b5ea67f2 100644 --- a/hw/display/g364fb.c +++ b/hw/display/g364fb.c @@ -514,7 +514,6 @@ static void g364fb_sysbus_reset(DeviceState *d) static const Property g364fb_sysbus_properties[] = { DEFINE_PROP_UINT32("vram_size", G364SysBusState, g364.vram_size, 8 * MiB), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_g364fb_sysbus = { diff --git a/hw/display/i2c-ddc.c b/hw/display/i2c-ddc.c index a2d1f2b044..d8ab9eee40 100644 --- a/hw/display/i2c-ddc.c +++ b/hw/display/i2c-ddc.c @@ -97,7 +97,6 @@ static const VMStateDescription vmstate_i2c_ddc = { static const Property i2c_ddc_properties[] = { DEFINE_EDID_PROPERTIES(I2CDDCState, edid_info), - DEFINE_PROP_END_OF_LIST(), }; static void i2c_ddc_class_init(ObjectClass *oc, void *data) diff --git a/hw/display/macfb.c b/hw/display/macfb.c index 977901bfdd..e83fc863be 100644 --- a/hw/display/macfb.c +++ b/hw/display/macfb.c @@ -764,7 +764,6 @@ static const Property macfb_sysbus_properties[] = { DEFINE_PROP_UINT8("depth", MacfbSysBusState, macfb.depth, 8), DEFINE_PROP_UINT8("display", MacfbSysBusState, macfb.type, MACFB_DISPLAY_VGA), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_macfb_sysbus = { @@ -783,7 +782,6 @@ static const Property macfb_nubus_properties[] = { DEFINE_PROP_UINT8("depth", MacfbNubusState, macfb.depth, 8), DEFINE_PROP_UINT8("display", MacfbNubusState, macfb.type, MACFB_DISPLAY_VGA), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_macfb_nubus = { diff --git a/hw/display/pl110.c b/hw/display/pl110.c index eca00b4279..4d4f477b94 100644 --- a/hw/display/pl110.c +++ b/hw/display/pl110.c @@ -538,7 +538,6 @@ static const GraphicHwOps pl110_gfx_ops = { static const Property pl110_properties[] = { DEFINE_PROP_LINK("framebuffer-memory", PL110State, fbmem, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void pl110_realize(DeviceState *dev, Error **errp) diff --git a/hw/display/qxl.c b/hw/display/qxl.c index f38a602aab..f54a15e740 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -2475,7 +2475,6 @@ static const Property qxl_properties[] = { DEFINE_PROP_UINT32("xres", PCIQXLDevice, xres, 0), DEFINE_PROP_UINT32("yres", PCIQXLDevice, yres, 0), DEFINE_PROP_BOOL("global-vmstate", PCIQXLDevice, vga.global_vmstate, false), - DEFINE_PROP_END_OF_LIST(), }; static void qxl_pci_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/ramfb-standalone.c b/hw/display/ramfb-standalone.c index e677f44be6..6c35028965 100644 --- a/hw/display/ramfb-standalone.c +++ b/hw/display/ramfb-standalone.c @@ -62,7 +62,6 @@ static const VMStateDescription ramfb_dev_vmstate = { static const Property ramfb_properties[] = { DEFINE_PROP_BOOL("x-migrate", RAMFBStandaloneState, migrate, true), - DEFINE_PROP_END_OF_LIST(), }; static void ramfb_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 446b648f1a..09edcf86f8 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -2058,7 +2058,6 @@ static const Property sm501_sysbus_properties[] = { DEFINE_PROP_UINT32("vram-size", SM501SysBusState, vram_size, 0), /* this a debug option, prefer PROP_UINT over PROP_BIT for simplicity */ DEFINE_PROP_UINT8("x-pixman", SM501SysBusState, state.use_pixman, DEFAULT_X_PIXMAN), - DEFINE_PROP_END_OF_LIST(), }; static void sm501_reset_sysbus(DeviceState *dev) @@ -2146,7 +2145,6 @@ static void sm501_realize_pci(PCIDevice *dev, Error **errp) static const Property sm501_pci_properties[] = { DEFINE_PROP_UINT32("vram-size", SM501PCIState, vram_size, 64 * MiB), DEFINE_PROP_UINT8("x-pixman", SM501PCIState, state.use_pixman, DEFAULT_X_PIXMAN), - DEFINE_PROP_END_OF_LIST(), }; static void sm501_reset_pci(DeviceState *dev) diff --git a/hw/display/tcx.c b/hw/display/tcx.c index 3eb0a91ff9..2cfc1e8f01 100644 --- a/hw/display/tcx.c +++ b/hw/display/tcx.c @@ -884,7 +884,6 @@ static const Property tcx_properties[] = { DEFINE_PROP_UINT16("width", TCXState, width, -1), DEFINE_PROP_UINT16("height", TCXState, height, -1), DEFINE_PROP_UINT16("depth", TCXState, depth, -1), - DEFINE_PROP_END_OF_LIST(), }; static void tcx_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/vga-isa.c b/hw/display/vga-isa.c index a6cbf77103..2920628f78 100644 --- a/hw/display/vga-isa.c +++ b/hw/display/vga-isa.c @@ -90,7 +90,6 @@ static void vga_isa_realizefn(DeviceState *dev, Error **errp) static const Property vga_isa_properties[] = { DEFINE_PROP_UINT32("vgamem_mb", ISAVGAState, state.vram_size_mb, 8), - DEFINE_PROP_END_OF_LIST(), }; static void vga_isa_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/display/vga-mmio.c b/hw/display/vga-mmio.c index b759efdde7..1e0c2dbf74 100644 --- a/hw/display/vga-mmio.c +++ b/hw/display/vga-mmio.c @@ -114,7 +114,6 @@ static void vga_mmio_realizefn(DeviceState *dev, Error **errp) static const Property vga_mmio_properties[] = { DEFINE_PROP_UINT8("it_shift", VGAMmioState, it_shift, 0), DEFINE_PROP_UINT32("vgamem_mb", VGAMmioState, vga.vram_size_mb, 8), - DEFINE_PROP_END_OF_LIST(), }; static void vga_mmio_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/display/vga-pci.c b/hw/display/vga-pci.c index 3145c448f5..dd084c20b1 100644 --- a/hw/display/vga-pci.c +++ b/hw/display/vga-pci.c @@ -339,7 +339,6 @@ static const Property vga_pci_properties[] = { PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), DEFINE_PROP_BOOL("global-vmstate", PCIVGAState, vga.global_vmstate, false), - DEFINE_PROP_END_OF_LIST(), }; static const Property secondary_pci_properties[] = { @@ -349,7 +348,6 @@ static const Property secondary_pci_properties[] = { DEFINE_PROP_BIT("edid", PCIVGAState, flags, PCI_VGA_FLAG_ENABLE_EDID, true), DEFINE_EDID_PROPERTIES(PCIVGAState, edid_info), - DEFINE_PROP_END_OF_LIST(), }; static void vga_pci_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/vhost-user-gpu.c b/hw/display/vhost-user-gpu.c index a36eddcb12..12d5c37ee5 100644 --- a/hw/display/vhost-user-gpu.c +++ b/hw/display/vhost-user-gpu.c @@ -647,7 +647,6 @@ static struct vhost_dev *vhost_user_gpu_get_vhost(VirtIODevice *vdev) static const Property vhost_user_gpu_properties[] = { VIRTIO_GPU_BASE_PROPERTIES(VhostUserGPU, parent_obj.conf), - DEFINE_PROP_END_OF_LIST(), }; static void diff --git a/hw/display/virtio-gpu-gl.c b/hw/display/virtio-gpu-gl.c index d8a1e1d8db..683fad3bf8 100644 --- a/hw/display/virtio-gpu-gl.c +++ b/hw/display/virtio-gpu-gl.c @@ -159,7 +159,6 @@ static const Property virtio_gpu_gl_properties[] = { VIRTIO_GPU_FLAG_STATS_ENABLED, false), DEFINE_PROP_BIT("venus", VirtIOGPU, parent_obj.conf.flags, VIRTIO_GPU_FLAG_VENUS_ENABLED, false), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_gpu_gl_device_unrealize(DeviceState *qdev) diff --git a/hw/display/virtio-gpu-pci.c b/hw/display/virtio-gpu-pci.c index 89d27c9d85..6d789701a3 100644 --- a/hw/display/virtio-gpu-pci.c +++ b/hw/display/virtio-gpu-pci.c @@ -23,7 +23,6 @@ static const Property virtio_gpu_pci_base_properties[] = { DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_gpu_pci_base_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/display/virtio-gpu-rutabaga.c b/hw/display/virtio-gpu-rutabaga.c index f6486acdda..f6eb29472e 100644 --- a/hw/display/virtio-gpu-rutabaga.c +++ b/hw/display/virtio-gpu-rutabaga.c @@ -1108,7 +1108,6 @@ static const Property virtio_gpu_rutabaga_properties[] = { DEFINE_PROP_STRING("wayland-socket-path", VirtIOGPURutabaga, wayland_socket_path), DEFINE_PROP_STRING("wsi", VirtIOGPURutabaga, wsi), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_gpu_rutabaga_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/virtio-gpu.c b/hw/display/virtio-gpu.c index 96baa40231..11a7a85750 100644 --- a/hw/display/virtio-gpu.c +++ b/hw/display/virtio-gpu.c @@ -1682,7 +1682,6 @@ static const Property virtio_gpu_properties[] = { VIRTIO_GPU_FLAG_BLOB_ENABLED, false), DEFINE_PROP_SIZE("hostmem", VirtIOGPU, parent_obj.conf.hostmem, 0), DEFINE_PROP_UINT8("x-scanout-vmstate-version", VirtIOGPU, scanout_vmstate_version, 2), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_gpu_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/virtio-vga.c b/hw/display/virtio-vga.c index 532e4c62d5..fefbdb61e1 100644 --- a/hw/display/virtio-vga.c +++ b/hw/display/virtio-vga.c @@ -211,7 +211,6 @@ static void virtio_vga_set_big_endian_fb(Object *obj, bool value, Error **errp) static const Property virtio_vga_base_properties[] = { DEFINE_VIRTIO_GPU_PCI_PROPERTIES(VirtIOPCIProxy), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_vga_base_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index f49bbf393a..2dd661e3c1 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -1337,7 +1337,6 @@ static const Property vga_vmware_properties[] = { chip.vga.vram_size_mb, 16), DEFINE_PROP_BOOL("global-vmstate", struct pci_vmsvga_state_s, chip.vga.global_vmstate, false), - DEFINE_PROP_END_OF_LIST(), }; static void vmsvga_class_init(ObjectClass *klass, void *data) diff --git a/hw/display/xlnx_dp.c b/hw/display/xlnx_dp.c index 7838f28bca..1272da0133 100644 --- a/hw/display/xlnx_dp.c +++ b/hw/display/xlnx_dp.c @@ -1389,7 +1389,6 @@ static void xlnx_dp_reset(DeviceState *dev) static const Property xlnx_dp_device_properties[] = { DEFINE_AUDIO_PROPERTIES(XlnxDPState, aud_card), - DEFINE_PROP_END_OF_LIST(), }; static void xlnx_dp_class_init(ObjectClass *oc, void *data) diff --git a/hw/dma/i82374.c b/hw/dma/i82374.c index 032afedde2..9652d47adc 100644 --- a/hw/dma/i82374.c +++ b/hw/dma/i82374.c @@ -141,7 +141,6 @@ static void i82374_realize(DeviceState *dev, Error **errp) static const Property i82374_properties[] = { DEFINE_PROP_UINT32("iobase", I82374State, iobase, 0x400), - DEFINE_PROP_END_OF_LIST() }; static void i82374_class_init(ObjectClass *klass, void *data) diff --git a/hw/dma/i8257.c b/hw/dma/i8257.c index 8b04177393..74c38d2ee8 100644 --- a/hw/dma/i8257.c +++ b/hw/dma/i8257.c @@ -590,7 +590,6 @@ static const Property i8257_properties[] = { DEFINE_PROP_INT32("page-base", I8257State, page_base, 0x80), DEFINE_PROP_INT32("pageh-base", I8257State, pageh_base, 0x480), DEFINE_PROP_INT32("dshift", I8257State, dshift, 0), - DEFINE_PROP_END_OF_LIST() }; static void i8257_class_init(ObjectClass *klass, void *data) diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c index 3f392822ed..8a9b073b24 100644 --- a/hw/dma/pl080.c +++ b/hw/dma/pl080.c @@ -411,7 +411,6 @@ static void pl081_init(Object *obj) static const Property pl080_properties[] = { DEFINE_PROP_LINK("downstream", PL080State, downstream, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void pl080_class_init(ObjectClass *oc, void *data) diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index 94f42c933b..545aa44e45 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -1669,8 +1669,6 @@ static const Property pl330_properties[] = { DEFINE_PROP_LINK("memory", PL330State, mem_mr, TYPE_MEMORY_REGION, MemoryRegion *), - - DEFINE_PROP_END_OF_LIST(), }; static void pl330_class_init(ObjectClass *klass, void *data) diff --git a/hw/dma/xilinx_axidma.c b/hw/dma/xilinx_axidma.c index e02aec78bc..22fe35751a 100644 --- a/hw/dma/xilinx_axidma.c +++ b/hw/dma/xilinx_axidma.c @@ -619,7 +619,6 @@ static const Property axidma_properties[] = { tx_control_dev, TYPE_STREAM_SINK, StreamSink *), DEFINE_PROP_LINK("dma", XilinxAXIDMA, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void axidma_class_init(ObjectClass *klass, void *data) diff --git a/hw/dma/xlnx-zdma.c b/hw/dma/xlnx-zdma.c index 1a63d5f3b2..bb27cb2e64 100644 --- a/hw/dma/xlnx-zdma.c +++ b/hw/dma/xlnx-zdma.c @@ -814,7 +814,6 @@ static const Property zdma_props[] = { DEFINE_PROP_UINT32("bus-width", XlnxZDMA, cfg.bus_width, 64), DEFINE_PROP_LINK("dma", XlnxZDMA, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void zdma_class_init(ObjectClass *klass, void *data) diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index 4170714351..1afaa0bf51 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -710,7 +710,6 @@ static const Property xlnx_csu_dma_properties[] = { TYPE_STREAM_SINK, StreamSink *), DEFINE_PROP_LINK("dma", XlnxCSUDMA, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void xlnx_csu_dma_class_init(ObjectClass *klass, void *data) diff --git a/hw/gpio/imx_gpio.c b/hw/gpio/imx_gpio.c index 919d53701f..898f80f8c8 100644 --- a/hw/gpio/imx_gpio.c +++ b/hw/gpio/imx_gpio.c @@ -294,7 +294,6 @@ static const Property imx_gpio_properties[] = { DEFINE_PROP_BOOL("has-edge-sel", IMXGPIOState, has_edge_sel, true), DEFINE_PROP_BOOL("has-upper-pin-irq", IMXGPIOState, has_upper_pin_irq, false), - DEFINE_PROP_END_OF_LIST(), }; static void imx_gpio_reset(DeviceState *dev) diff --git a/hw/gpio/npcm7xx_gpio.c b/hw/gpio/npcm7xx_gpio.c index db6792b2ad..23e67424c9 100644 --- a/hw/gpio/npcm7xx_gpio.c +++ b/hw/gpio/npcm7xx_gpio.c @@ -395,7 +395,6 @@ static const Property npcm7xx_gpio_properties[] = { DEFINE_PROP_UINT32("reset-osrc", NPCM7xxGPIOState, reset_osrc, 0), /* Bit n set => pin n has high drive strength by default. */ DEFINE_PROP_UINT32("reset-odsc", NPCM7xxGPIOState, reset_odsc, 0), - DEFINE_PROP_END_OF_LIST(), }; static void npcm7xx_gpio_class_init(ObjectClass *klass, void *data) diff --git a/hw/gpio/omap_gpio.c b/hw/gpio/omap_gpio.c index 03ee9e47c6..8a9f14ba15 100644 --- a/hw/gpio/omap_gpio.c +++ b/hw/gpio/omap_gpio.c @@ -227,7 +227,6 @@ void omap_gpio_set_clk(Omap1GpioState *gpio, omap_clk clk) static const Property omap_gpio_properties[] = { DEFINE_PROP_INT32("mpu_model", Omap1GpioState, mpu_model, 0), - DEFINE_PROP_END_OF_LIST(), }; static void omap_gpio_class_init(ObjectClass *klass, void *data) diff --git a/hw/gpio/pca9552.c b/hw/gpio/pca9552.c index 427419d218..1ac0cf6c46 100644 --- a/hw/gpio/pca9552.c +++ b/hw/gpio/pca9552.c @@ -430,7 +430,6 @@ static void pca955x_realize(DeviceState *dev, Error **errp) static const Property pca955x_properties[] = { DEFINE_PROP_STRING("description", PCA955xState, description), - DEFINE_PROP_END_OF_LIST(), }; static void pca955x_class_init(ObjectClass *klass, void *data) diff --git a/hw/gpio/pca9554.c b/hw/gpio/pca9554.c index e8b0458aac..fe03bb4b5e 100644 --- a/hw/gpio/pca9554.c +++ b/hw/gpio/pca9554.c @@ -293,7 +293,6 @@ static void pca9554_realize(DeviceState *dev, Error **errp) static const Property pca9554_properties[] = { DEFINE_PROP_STRING("description", PCA9554State, description), - DEFINE_PROP_END_OF_LIST(), }; static void pca9554_class_init(ObjectClass *klass, void *data) diff --git a/hw/gpio/pl061.c b/hw/gpio/pl061.c index 9b8ca6de32..60ce4a7f62 100644 --- a/hw/gpio/pl061.c +++ b/hw/gpio/pl061.c @@ -565,7 +565,6 @@ static void pl061_realize(DeviceState *dev, Error **errp) static const Property pl061_props[] = { DEFINE_PROP_UINT32("pullups", PL061State, pullups, 0xff), DEFINE_PROP_UINT32("pulldowns", PL061State, pulldowns, 0x0), - DEFINE_PROP_END_OF_LIST() }; static void pl061_class_init(ObjectClass *klass, void *data) diff --git a/hw/gpio/sifive_gpio.c b/hw/gpio/sifive_gpio.c index 5603f0c235..0d5206ae6b 100644 --- a/hw/gpio/sifive_gpio.c +++ b/hw/gpio/sifive_gpio.c @@ -351,7 +351,6 @@ static const VMStateDescription vmstate_sifive_gpio = { static const Property sifive_gpio_properties[] = { DEFINE_PROP_UINT32("ngpio", SIFIVEGPIOState, ngpio, SIFIVE_GPIO_PINS), - DEFINE_PROP_END_OF_LIST(), }; static void sifive_gpio_realize(DeviceState *dev, Error **errp) diff --git a/hw/gpio/stm32l4x5_gpio.c b/hw/gpio/stm32l4x5_gpio.c index d1394f3f55..f69fc1db4f 100644 --- a/hw/gpio/stm32l4x5_gpio.c +++ b/hw/gpio/stm32l4x5_gpio.c @@ -452,7 +452,6 @@ static const Property stm32l4x5_gpio_properties[] = { DEFINE_PROP_UINT32("mode-reset", Stm32l4x5GpioState, moder_reset, 0), DEFINE_PROP_UINT32("ospeed-reset", Stm32l4x5GpioState, ospeedr_reset, 0), DEFINE_PROP_UINT32("pupd-reset", Stm32l4x5GpioState, pupdr_reset, 0), - DEFINE_PROP_END_OF_LIST(), }; static void stm32l4x5_gpio_class_init(ObjectClass *klass, void *data) diff --git a/hw/hyperv/hv-balloon.c b/hw/hyperv/hv-balloon.c index ba622e80ff..e21fc675a6 100644 --- a/hw/hyperv/hv-balloon.c +++ b/hw/hyperv/hv-balloon.c @@ -1741,8 +1741,6 @@ static const Property hv_balloon_properties[] = { DEFINE_PROP_LINK(HV_BALLOON_MEMDEV_PROP, HvBalloon, hostmem, TYPE_MEMORY_BACKEND, HostMemoryBackend *), DEFINE_PROP_UINT64(HV_BALLOON_ADDR_PROP, HvBalloon, addr, 0), - - DEFINE_PROP_END_OF_LIST(), }; static void hv_balloon_class_init(ObjectClass *klass, void *data) diff --git a/hw/hyperv/syndbg.c b/hw/hyperv/syndbg.c index 0193addd42..d3e3917077 100644 --- a/hw/hyperv/syndbg.c +++ b/hw/hyperv/syndbg.c @@ -370,7 +370,6 @@ static const Property hv_syndbg_properties[] = { DEFINE_PROP_STRING("host_ip", HvSynDbg, host_ip), DEFINE_PROP_UINT16("host_port", HvSynDbg, host_port, 50000), DEFINE_PROP_BOOL("use_hcalls", HvSynDbg, use_hcalls, false), - DEFINE_PROP_END_OF_LIST(), }; static void hv_syndbg_class_init(ObjectClass *klass, void *data) diff --git a/hw/hyperv/vmbus.c b/hw/hyperv/vmbus.c index 3d1f4d14e8..12a7dc4312 100644 --- a/hw/hyperv/vmbus.c +++ b/hw/hyperv/vmbus.c @@ -2348,7 +2348,6 @@ static void vmbus_dev_unrealize(DeviceState *dev) static const Property vmbus_dev_props[] = { DEFINE_PROP_UUID("instanceid", VMBusDevice, instanceid), - DEFINE_PROP_END_OF_LIST() }; @@ -2655,7 +2654,6 @@ static const VMStateDescription vmstate_vmbus_bridge = { static const Property vmbus_bridge_props[] = { DEFINE_PROP_UINT8("irq", VMBusBridge, irq, 7), - DEFINE_PROP_END_OF_LIST() }; static void vmbus_bridge_class_init(ObjectClass *klass, void *data) diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 2ea68c3090..a8fbb9f44a 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -1261,7 +1261,6 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) static const Property aspeed_i2c_properties[] = { DEFINE_PROP_LINK("dram", AspeedI2CState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_i2c_class_init(ObjectClass *klass, void *data) @@ -1450,7 +1449,6 @@ static const Property aspeed_i2c_bus_properties[] = { DEFINE_PROP_UINT8("bus-id", AspeedI2CBus, id, 0), DEFINE_PROP_LINK("controller", AspeedI2CBus, controller, TYPE_ASPEED_I2C, AspeedI2CState *), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_i2c_bus_class_init(ObjectClass *klass, void *data) diff --git a/hw/i2c/core.c b/hw/i2c/core.c index 4118d3db50..26bb18514a 100644 --- a/hw/i2c/core.c +++ b/hw/i2c/core.c @@ -20,7 +20,6 @@ static const Property i2c_props[] = { DEFINE_PROP_UINT8("address", struct I2CSlave, address, 0), - DEFINE_PROP_END_OF_LIST(), }; static const TypeInfo i2c_bus_info = { diff --git a/hw/i2c/i2c_mux_pca954x.c b/hw/i2c/i2c_mux_pca954x.c index 80c570fd10..779cc4e66e 100644 --- a/hw/i2c/i2c_mux_pca954x.c +++ b/hw/i2c/i2c_mux_pca954x.c @@ -213,7 +213,6 @@ static void pca954x_init(Object *obj) static const Property pca954x_props[] = { DEFINE_PROP_STRING("name", Pca954xState, name), - DEFINE_PROP_END_OF_LIST() }; static void pca954x_class_init(ObjectClass *klass, void *data) diff --git a/hw/i2c/omap_i2c.c b/hw/i2c/omap_i2c.c index 172df135f5..a641db2348 100644 --- a/hw/i2c/omap_i2c.c +++ b/hw/i2c/omap_i2c.c @@ -513,7 +513,6 @@ void omap_i2c_set_fclk(OMAPI2CState *i2c, omap_clk clk) static const Property omap_i2c_properties[] = { DEFINE_PROP_UINT8("revision", OMAPI2CState, revision, 0), - DEFINE_PROP_END_OF_LIST(), }; static void omap_i2c_class_init(ObjectClass *klass, void *data) diff --git a/hw/i386/amd_iommu.c b/hw/i386/amd_iommu.c index ca3e62a244..be522b5d7d 100644 --- a/hw/i386/amd_iommu.c +++ b/hw/i386/amd_iommu.c @@ -1670,7 +1670,6 @@ static void amdvi_sysbus_realize(DeviceState *dev, Error **errp) static const Property amdvi_properties[] = { DEFINE_PROP_BOOL("xtsup", AMDVIState, xtsup, false), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_amdvi_sysbus = { diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index fa28c33f21..a8c275f9ce 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -3418,7 +3418,6 @@ static const Property vtd_properties[] = { DEFINE_PROP_BOOL("dma-drain", IntelIOMMUState, dma_drain, true), DEFINE_PROP_BOOL("dma-translation", IntelIOMMUState, dma_translation, true), DEFINE_PROP_BOOL("stale-tm", IntelIOMMUState, stale_tm, false), - DEFINE_PROP_END_OF_LIST(), }; /* Read IRTE entry with specific index */ diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 610af634cc..63be508842 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -308,7 +308,6 @@ static const VMStateDescription kvmclock_vmsd = { static const Property kvmclock_properties[] = { DEFINE_PROP_BOOL("x-mach-use-reliable-get-clock", KVMClockState, mach_use_reliable_get_clock, true), - DEFINE_PROP_END_OF_LIST(), }; static void kvmclock_class_init(ObjectClass *klass, void *data) diff --git a/hw/i386/kvm/i8254.c b/hw/i386/kvm/i8254.c index eb9a6f79fe..3b92771c79 100644 --- a/hw/i386/kvm/i8254.c +++ b/hw/i386/kvm/i8254.c @@ -290,7 +290,6 @@ static void kvm_pit_realizefn(DeviceState *dev, Error **errp) static const Property kvm_pit_properties[] = { DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", KVMPITState, lost_tick_policy, LOST_TICK_POLICY_DELAY), - DEFINE_PROP_END_OF_LIST(), }; static void kvm_pit_class_init(ObjectClass *klass, void *data) diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapic.c index b8bc46518b..5419e191b5 100644 --- a/hw/i386/kvm/ioapic.c +++ b/hw/i386/kvm/ioapic.c @@ -135,7 +135,6 @@ static void kvm_ioapic_realize(DeviceState *dev, Error **errp) static const Property kvm_ioapic_properties[] = { DEFINE_PROP_UINT32("gsi_base", KVMIOAPICState, kvm_gsi_base, 0), - DEFINE_PROP_END_OF_LIST() }; static void kvm_ioapic_class_init(ObjectClass *klass, void *data) diff --git a/hw/i386/sgx-epc.c b/hw/i386/sgx-epc.c index c232e825e0..875e1c5c33 100644 --- a/hw/i386/sgx-epc.c +++ b/hw/i386/sgx-epc.c @@ -24,7 +24,6 @@ static const Property sgx_epc_properties[] = { DEFINE_PROP_UINT32(SGX_EPC_NUMA_NODE_PROP, SGXEPCDevice, node, 0), DEFINE_PROP_LINK(SGX_EPC_MEMDEV_PROP, SGXEPCDevice, hostmem, TYPE_MEMORY_BACKEND_EPC, HostMemoryBackendEpc *), - DEFINE_PROP_END_OF_LIST(), }; static void sgx_epc_get_size(Object *obj, Visitor *v, const char *name, diff --git a/hw/i386/vmmouse.c b/hw/i386/vmmouse.c index da9c35c1ec..3e07d12512 100644 --- a/hw/i386/vmmouse.c +++ b/hw/i386/vmmouse.c @@ -319,7 +319,6 @@ static void vmmouse_realizefn(DeviceState *dev, Error **errp) static const Property vmmouse_properties[] = { DEFINE_PROP_LINK("i8042", VMMouseState, i8042, TYPE_I8042, ISAKBDState *), - DEFINE_PROP_END_OF_LIST(), }; static void vmmouse_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/i386/vmport.c b/hw/i386/vmport.c index 7be25524f1..2f19b970b5 100644 --- a/hw/i386/vmport.c +++ b/hw/i386/vmport.c @@ -284,8 +284,6 @@ static const Property vmport_properties[] = { * 5 - ACE 1.x (Deprecated) */ DEFINE_PROP_UINT8("vmware-vmx-type", VMPortState, vmware_vmx_type, 2), - - DEFINE_PROP_END_OF_LIST(), }; static void vmport_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index 06d91c6c13..fed34b2fcf 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -130,7 +130,6 @@ static const Property x86_iommu_properties[] = { intr_supported, ON_OFF_AUTO_AUTO), DEFINE_PROP_BOOL("device-iotlb", X86IOMMUState, dt_supported, false), DEFINE_PROP_BOOL("pt", X86IOMMUState, pt_supported, true), - DEFINE_PROP_END_OF_LIST(), }; static void x86_iommu_class_init(ObjectClass *klass, void *data) diff --git a/hw/i386/xen/xen_pvdevice.c b/hw/i386/xen/xen_pvdevice.c index e71483e6e3..9453da97bd 100644 --- a/hw/i386/xen/xen_pvdevice.c +++ b/hw/i386/xen/xen_pvdevice.c @@ -120,7 +120,6 @@ static const Property xen_pv_props[] = { DEFINE_PROP_UINT16("device-id", XenPVDevice, device_id, 0xffff), DEFINE_PROP_UINT8("revision", XenPVDevice, revision, 0x01), DEFINE_PROP_UINT32("size", XenPVDevice, size, 0x400000), - DEFINE_PROP_END_OF_LIST() }; static void xen_pv_class_init(ObjectClass *klass, void *data) diff --git a/hw/ide/ahci-sysbus.c b/hw/ide/ahci-sysbus.c index d43db0923f..03a5bd42d0 100644 --- a/hw/ide/ahci-sysbus.c +++ b/hw/ide/ahci-sysbus.c @@ -62,9 +62,8 @@ static void sysbus_ahci_realize(DeviceState *dev, Error **errp) ahci_realize(&s->ahci, dev, &address_space_memory); } -static Property sysbus_ahci_properties[] = { +static const Property sysbus_ahci_properties[] = { DEFINE_PROP_UINT32("num-ports", SysbusAHCIState, ahci.ports, 1), - DEFINE_PROP_END_OF_LIST(), }; static void sysbus_ahci_class_init(ObjectClass *klass, void *data) diff --git a/hw/ide/cf.c b/hw/ide/cf.c index 190914f513..cfb4394f80 100644 --- a/hw/ide/cf.c +++ b/hw/ide/cf.c @@ -29,7 +29,6 @@ static const Property ide_cf_properties[] = { DEFINE_BLOCK_CHS_PROPERTIES(IDEDrive, dev.conf), DEFINE_PROP_BIOS_CHS_TRANS("bios-chs-trans", IDEDrive, dev.chs_trans, BIOS_ATA_TRANSLATION_AUTO), - DEFINE_PROP_END_OF_LIST(), }; static void ide_cf_class_init(ObjectClass *klass, void *data) diff --git a/hw/ide/cmd646.c b/hw/ide/cmd646.c index 20410c81fa..8e568e4c35 100644 --- a/hw/ide/cmd646.c +++ b/hw/ide/cmd646.c @@ -315,7 +315,6 @@ static void pci_cmd646_ide_exitfn(PCIDevice *dev) static const Property cmd646_ide_properties[] = { DEFINE_PROP_UINT32("secondary", PCIIDEState, secondary, 0), - DEFINE_PROP_END_OF_LIST(), }; static void cmd646_ide_class_init(ObjectClass *klass, void *data) diff --git a/hw/ide/ide-dev.c b/hw/ide/ide-dev.c index 6eae80c588..26f0517019 100644 --- a/hw/ide/ide-dev.c +++ b/hw/ide/ide-dev.c @@ -32,7 +32,6 @@ static const Property ide_props[] = { DEFINE_PROP_UINT32("unit", IDEDevice, unit, -1), DEFINE_PROP_BOOL("win2k-install-hack", IDEDevice, win2k_install_hack, false), - DEFINE_PROP_END_OF_LIST(), }; static void ide_qdev_realize(DeviceState *qdev, Error **errp) @@ -197,7 +196,6 @@ static const Property ide_hd_properties[] = { DEFINE_PROP_BIOS_CHS_TRANS("bios-chs-trans", IDEDrive, dev.chs_trans, BIOS_ATA_TRANSLATION_AUTO), DEFINE_PROP_UINT16("rotation_rate", IDEDrive, dev.rotation_rate, 0), - DEFINE_PROP_END_OF_LIST(), }; static void ide_hd_class_init(ObjectClass *klass, void *data) @@ -220,7 +218,6 @@ static const TypeInfo ide_hd_info = { static const Property ide_cd_properties[] = { DEFINE_IDE_DEV_PROPERTIES(), - DEFINE_PROP_END_OF_LIST(), }; static void ide_cd_class_init(ObjectClass *klass, void *data) diff --git a/hw/ide/isa.c b/hw/ide/isa.c index b542549160..4863ad8080 100644 --- a/hw/ide/isa.c +++ b/hw/ide/isa.c @@ -105,7 +105,6 @@ static const Property isa_ide_properties[] = { DEFINE_PROP_UINT32("iobase", ISAIDEState, iobase, 0x1f0), DEFINE_PROP_UINT32("iobase2", ISAIDEState, iobase2, 0x3f6), DEFINE_PROP_UINT32("irq", ISAIDEState, irqnum, 14), - DEFINE_PROP_END_OF_LIST(), }; static void isa_ide_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/ide/macio.c b/hw/ide/macio.c index f5579bb896..5fe764b49b 100644 --- a/hw/ide/macio.c +++ b/hw/ide/macio.c @@ -462,7 +462,6 @@ static void macio_ide_initfn(Object *obj) static const Property macio_ide_properties[] = { DEFINE_PROP_UINT32("channel", MACIOIDEState, channel, 0), DEFINE_PROP_UINT32("addr", MACIOIDEState, addr, -1), - DEFINE_PROP_END_OF_LIST(), }; static void macio_ide_class_init(ObjectClass *oc, void *data) diff --git a/hw/ide/mmio.c b/hw/ide/mmio.c index 71a17fe41c..13f16170ff 100644 --- a/hw/ide/mmio.c +++ b/hw/ide/mmio.c @@ -143,7 +143,6 @@ static void mmio_ide_initfn(Object *obj) static const Property mmio_ide_properties[] = { DEFINE_PROP_UINT32("shift", MMIOIDEState, shift, 0), - DEFINE_PROP_END_OF_LIST() }; static void mmio_ide_class_init(ObjectClass *oc, void *data) diff --git a/hw/input/pckbd.c b/hw/input/pckbd.c index 6338a7525a..fa0c549eb9 100644 --- a/hw/input/pckbd.c +++ b/hw/input/pckbd.c @@ -738,7 +738,6 @@ static void i8042_mmio_init(Object *obj) static const Property i8042_mmio_properties[] = { DEFINE_PROP_UINT64("mask", MMIOKBDState, kbd.mask, UINT64_MAX), DEFINE_PROP_UINT32("size", MMIOKBDState, size, -1), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_kbd_mmio = { @@ -938,7 +937,6 @@ static const Property i8042_properties[] = { DEFINE_PROP_BOOL("kbd-throttle", ISAKBDState, kbd_throttle, false), DEFINE_PROP_UINT8("kbd-irq", ISAKBDState, kbd_irq, 1), DEFINE_PROP_UINT8("mouse-irq", ISAKBDState, mouse_irq, 12), - DEFINE_PROP_END_OF_LIST(), }; static void i8042_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/input/stellaris_gamepad.c b/hw/input/stellaris_gamepad.c index b1cc693189..98382a0e15 100644 --- a/hw/input/stellaris_gamepad.c +++ b/hw/input/stellaris_gamepad.c @@ -80,7 +80,6 @@ static void stellaris_gamepad_reset_enter(Object *obj, ResetType type) static const Property stellaris_gamepad_properties[] = { DEFINE_PROP_ARRAY("keycodes", StellarisGamepad, num_buttons, keycodes, qdev_prop_uint32, uint32_t), - DEFINE_PROP_END_OF_LIST(), }; static void stellaris_gamepad_class_init(ObjectClass *klass, void *data) diff --git a/hw/input/virtio-input-hid.c b/hw/input/virtio-input-hid.c index 7396385508..812faaef8f 100644 --- a/hw/input/virtio-input-hid.c +++ b/hw/input/virtio-input-hid.c @@ -240,7 +240,6 @@ static void virtio_input_hid_handle_status(VirtIOInput *vinput, static const Property virtio_input_hid_properties[] = { DEFINE_PROP_STRING("display", VirtIOInputHID, display), DEFINE_PROP_UINT32("head", VirtIOInputHID, head, 0), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_input_hid_class_init(ObjectClass *klass, void *data) @@ -382,7 +381,6 @@ static struct virtio_input_config virtio_mouse_config_v2[] = { static const Property virtio_mouse_properties[] = { DEFINE_PROP_BOOL("wheel-axis", VirtIOInputHID, wheel_axis, true), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_mouse_class_init(ObjectClass *klass, void *data) @@ -507,7 +505,6 @@ static struct virtio_input_config virtio_tablet_config_v2[] = { static const Property virtio_tablet_properties[] = { DEFINE_PROP_BOOL("wheel-axis", VirtIOInputHID, wheel_axis, true), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_tablet_class_init(ObjectClass *klass, void *data) diff --git a/hw/input/virtio-input-host.c b/hw/input/virtio-input-host.c index 2be2c633ab..8bfb17f3c4 100644 --- a/hw/input/virtio-input-host.c +++ b/hw/input/virtio-input-host.c @@ -223,7 +223,6 @@ static const VMStateDescription vmstate_virtio_input_host = { static const Property virtio_input_host_properties[] = { DEFINE_PROP_STRING("evdev", VirtIOInputHost, evdev), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_input_host_class_init(ObjectClass *klass, void *data) diff --git a/hw/input/virtio-input.c b/hw/input/virtio-input.c index edcd94dedb..1394d99c6b 100644 --- a/hw/input/virtio-input.c +++ b/hw/input/virtio-input.c @@ -302,7 +302,6 @@ static const VMStateDescription vmstate_virtio_input = { static const Property virtio_input_properties[] = { DEFINE_PROP_STRING("serial", VirtIOInput, serial), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_input_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 85ded28032..2a3e878c4d 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -414,7 +414,6 @@ static const Property apic_properties_common[] = { true), DEFINE_PROP_BOOL("legacy-instance-id", APICCommonState, legacy_instance_id, false), - DEFINE_PROP_END_OF_LIST(), }; static void apic_common_get_id(Object *obj, Visitor *v, const char *name, diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index 5eba8badb8..5ac56e3389 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -360,7 +360,6 @@ static const Property arm_gic_common_properties[] = { /* True if the GIC should implement the virtualization extensions */ DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0), DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8), - DEFINE_PROP_END_OF_LIST(), }; static void arm_gic_common_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/arm_gicv2m.c b/hw/intc/arm_gicv2m.c index 66d4377cde..3a8c62698c 100644 --- a/hw/intc/arm_gicv2m.c +++ b/hw/intc/arm_gicv2m.c @@ -173,7 +173,6 @@ static void gicv2m_init(Object *obj) static const Property gicv2m_properties[] = { DEFINE_PROP_UINT32("base-spi", ARMGICv2mState, base_spi, 0), DEFINE_PROP_UINT32("num-spi", ARMGICv2mState, num_spi, 64), - DEFINE_PROP_END_OF_LIST(), }; static void gicv2m_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/arm_gicv3_common.c b/hw/intc/arm_gicv3_common.c index 67d0ab71cc..76b2283c92 100644 --- a/hw/intc/arm_gicv3_common.c +++ b/hw/intc/arm_gicv3_common.c @@ -621,7 +621,6 @@ static const Property arm_gicv3_common_properties[] = { redist_region_count, qdev_prop_uint32, uint32_t), DEFINE_PROP_LINK("sysmem", GICv3State, dma, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void arm_gicv3_common_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/arm_gicv3_its.c b/hw/intc/arm_gicv3_its.c index 0de7643008..936368c901 100644 --- a/hw/intc/arm_gicv3_its.c +++ b/hw/intc/arm_gicv3_its.c @@ -2005,7 +2005,6 @@ static void gicv3_its_post_load(GICv3ITSState *s) static const Property gicv3_its_props[] = { DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "arm-gicv3", GICv3State *), - DEFINE_PROP_END_OF_LIST(), }; static void gicv3_its_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/arm_gicv3_its_kvm.c b/hw/intc/arm_gicv3_its_kvm.c index 62961b62b4..e198974560 100644 --- a/hw/intc/arm_gicv3_its_kvm.c +++ b/hw/intc/arm_gicv3_its_kvm.c @@ -237,7 +237,6 @@ static void kvm_arm_its_reset_hold(Object *obj, ResetType type) static const Property kvm_arm_its_props[] = { DEFINE_PROP_LINK("parent-gicv3", GICv3ITSState, gicv3, "kvm-arm-gicv3", GICv3State *), - DEFINE_PROP_END_OF_LIST(), }; static void kvm_arm_its_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 10a773c07f..5fd0760982 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -2577,7 +2577,6 @@ static const Property props_nvic[] = { * to use a reasonable default. */ DEFINE_PROP_UINT8("num-prio-bits", NVICState, num_prio_bits, 0), - DEFINE_PROP_END_OF_LIST() }; static void armv7m_nvic_reset(DeviceState *dev) diff --git a/hw/intc/exynos4210_combiner.c b/hw/intc/exynos4210_combiner.c index 221dfa912a..6ddbcd4c6d 100644 --- a/hw/intc/exynos4210_combiner.c +++ b/hw/intc/exynos4210_combiner.c @@ -327,7 +327,6 @@ static void exynos4210_combiner_init(Object *obj) static const Property exynos4210_combiner_properties[] = { DEFINE_PROP_UINT32("external", Exynos4210CombinerState, external, 0), - DEFINE_PROP_END_OF_LIST(), }; static void exynos4210_combiner_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/exynos4210_gic.c b/hw/intc/exynos4210_gic.c index e1b956d990..01a53936d3 100644 --- a/hw/intc/exynos4210_gic.c +++ b/hw/intc/exynos4210_gic.c @@ -113,7 +113,6 @@ static void exynos4210_gic_realize(DeviceState *dev, Error **errp) static const Property exynos4210_gic_properties[] = { DEFINE_PROP_UINT32("num-cpu", Exynos4210GicState, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), }; static void exynos4210_gic_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/goldfish_pic.c b/hw/intc/goldfish_pic.c index f5343c9d2f..aa5162c18f 100644 --- a/hw/intc/goldfish_pic.c +++ b/hw/intc/goldfish_pic.c @@ -183,7 +183,6 @@ static void goldfish_pic_instance_init(Object *obj) static const Property goldfish_pic_properties[] = { DEFINE_PROP_UINT8("index", GoldfishPICState, idx, 0), - DEFINE_PROP_END_OF_LIST(), }; static void goldfish_pic_class_init(ObjectClass *oc, void *data) diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index bf53251ea2..95cdb411d2 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -378,7 +378,6 @@ static void grlib_irqmp_realize(DeviceState *dev, Error **errp) static const Property grlib_irqmp_properties[] = { DEFINE_PROP_UINT32("ncpus", IRQMP, ncpus, 1), - DEFINE_PROP_END_OF_LIST(), }; static void grlib_irqmp_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/i8259_common.c b/hw/intc/i8259_common.c index c3174f4fdc..c77ff683bb 100644 --- a/hw/intc/i8259_common.c +++ b/hw/intc/i8259_common.c @@ -198,7 +198,6 @@ static const Property pic_properties_common[] = { DEFINE_PROP_UINT32("elcr_addr", PICCommonState, elcr_addr, -1), DEFINE_PROP_UINT8("elcr_mask", PICCommonState, elcr_mask, -1), DEFINE_PROP_BIT("master", PICCommonState, master, 0, false), - DEFINE_PROP_END_OF_LIST(), }; static void pic_common_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/ioapic.c b/hw/intc/ioapic.c index d101df1ca0..8cd1d85e06 100644 --- a/hw/intc/ioapic.c +++ b/hw/intc/ioapic.c @@ -478,7 +478,6 @@ static void ioapic_unrealize(DeviceState *dev) static const Property ioapic_properties[] = { DEFINE_PROP_UINT8("version", IOAPICCommonState, version, IOAPIC_VER_DEF), - DEFINE_PROP_END_OF_LIST(), }; static void ioapic_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/loongarch_extioi_common.c b/hw/intc/loongarch_extioi_common.c index e50431f124..e4c1cc3c98 100644 --- a/hw/intc/loongarch_extioi_common.c +++ b/hw/intc/loongarch_extioi_common.c @@ -85,7 +85,6 @@ static const Property extioi_properties[] = { DEFINE_PROP_UINT32("num-cpu", LoongArchExtIOICommonState, num_cpu, 1), DEFINE_PROP_BIT("has-virtualization-extension", LoongArchExtIOICommonState, features, EXTIOI_HAS_VIRT_EXTENSION, 0), - DEFINE_PROP_END_OF_LIST(), }; static void loongarch_extioi_common_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/loongarch_pch_msi.c b/hw/intc/loongarch_pch_msi.c index e2eca30660..66b5c1e660 100644 --- a/hw/intc/loongarch_pch_msi.c +++ b/hw/intc/loongarch_pch_msi.c @@ -86,7 +86,6 @@ static void loongarch_pch_msi_init(Object *obj) static const Property loongarch_msi_properties[] = { DEFINE_PROP_UINT32("msi_irq_base", LoongArchPCHMSI, irq_base, 0), DEFINE_PROP_UINT32("msi_irq_num", LoongArchPCHMSI, irq_num, 0), - DEFINE_PROP_END_OF_LIST(), }; static void loongarch_pch_msi_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/loongarch_pic_common.c b/hw/intc/loongarch_pic_common.c index bcb6b7b3fc..e7f541db4b 100644 --- a/hw/intc/loongarch_pic_common.c +++ b/hw/intc/loongarch_pic_common.c @@ -46,7 +46,6 @@ static void loongarch_pic_common_realize(DeviceState *dev, Error **errp) static const Property loongarch_pic_common_properties[] = { DEFINE_PROP_UINT32("pch_pic_irq_num", LoongArchPICCommonState, irq_num, 0), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_loongarch_pic_common = { diff --git a/hw/intc/loongson_ipi_common.c b/hw/intc/loongson_ipi_common.c index d3f894a5bd..9a081565f5 100644 --- a/hw/intc/loongson_ipi_common.c +++ b/hw/intc/loongson_ipi_common.c @@ -317,7 +317,6 @@ static const VMStateDescription vmstate_loongson_ipi_common = { static const Property ipi_common_properties[] = { DEFINE_PROP_UINT32("num-cpu", LoongsonIPICommonState, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), }; static void loongson_ipi_common_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/m68k_irqc.c b/hw/intc/m68k_irqc.c index b5d10ab1f6..a82b80f5c6 100644 --- a/hw/intc/m68k_irqc.c +++ b/hw/intc/m68k_irqc.c @@ -88,7 +88,6 @@ static const VMStateDescription vmstate_m68k_irqc = { static const Property m68k_irqc_properties[] = { DEFINE_PROP_LINK("m68k-cpu", M68KIRQCState, cpu, TYPE_M68K_CPU, ArchCPU *), - DEFINE_PROP_END_OF_LIST(), }; static void m68k_irqc_class_init(ObjectClass *oc, void *data) diff --git a/hw/intc/mips_gic.c b/hw/intc/mips_gic.c index f34f0bc350..5e3cbeabec 100644 --- a/hw/intc/mips_gic.c +++ b/hw/intc/mips_gic.c @@ -441,7 +441,6 @@ static void mips_gic_realize(DeviceState *dev, Error **errp) static const Property mips_gic_properties[] = { DEFINE_PROP_UINT32("num-vp", MIPSGICState, num_vps, 1), DEFINE_PROP_UINT32("num-irq", MIPSGICState, num_irq, 256), - DEFINE_PROP_END_OF_LIST(), }; static void mips_gic_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/omap_intc.c b/hw/intc/omap_intc.c index 28606f102b..095a3d504f 100644 --- a/hw/intc/omap_intc.c +++ b/hw/intc/omap_intc.c @@ -377,7 +377,6 @@ void omap_intc_set_fclk(OMAPIntcState *intc, omap_clk clk) static const Property omap_intc_properties[] = { DEFINE_PROP_UINT32("size", OMAPIntcState, size, 0x100), - DEFINE_PROP_END_OF_LIST(), }; static void omap_intc_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/ompic.c b/hw/intc/ompic.c index 8ee1bd64bd..42af4567c6 100644 --- a/hw/intc/ompic.c +++ b/hw/intc/ompic.c @@ -130,7 +130,6 @@ static void or1k_ompic_realize(DeviceState *dev, Error **errp) static const Property or1k_ompic_properties[] = { DEFINE_PROP_UINT32("num-cpus", OR1KOMPICState, num_cpus, 1), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_or1k_ompic_cpu = { diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 2257ae2ee7..78a82d0d30 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -1609,7 +1609,6 @@ static void openpic_realize(DeviceState *dev, Error **errp) static const Property openpic_properties[] = { DEFINE_PROP_UINT32("model", OpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20), DEFINE_PROP_UINT32("nb_cpus", OpenPICState, nb_cpus, 1), - DEFINE_PROP_END_OF_LIST(), }; static void openpic_class_init(ObjectClass *oc, void *data) diff --git a/hw/intc/openpic_kvm.c b/hw/intc/openpic_kvm.c index 13aa653aa1..9cdaa97004 100644 --- a/hw/intc/openpic_kvm.c +++ b/hw/intc/openpic_kvm.c @@ -265,7 +265,6 @@ int kvm_openpic_connect_vcpu(DeviceState *d, CPUState *cs) static const Property kvm_openpic_properties[] = { DEFINE_PROP_UINT32("model", KVMOpenPICState, model, OPENPIC_MODEL_FSL_MPIC_20), - DEFINE_PROP_END_OF_LIST(), }; static void kvm_openpic_class_init(ObjectClass *oc, void *data) diff --git a/hw/intc/pnv_xive.c b/hw/intc/pnv_xive.c index c374aed43a..b755ddf0ff 100644 --- a/hw/intc/pnv_xive.c +++ b/hw/intc/pnv_xive.c @@ -2066,7 +2066,6 @@ static const Property pnv_xive_properties[] = { DEFINE_PROP_UINT64("tm-bar", PnvXive, tm_base, 0), /* The PnvChip id identifies the XIVE interrupt controller. */ DEFINE_PROP_LINK("chip", PnvXive, chip, TYPE_PNV_CHIP, PnvChip *), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_xive_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/pnv_xive2.c b/hw/intc/pnv_xive2.c index ae6da95df2..9ed759417e 100644 --- a/hw/intc/pnv_xive2.c +++ b/hw/intc/pnv_xive2.c @@ -2366,7 +2366,6 @@ static const Property pnv_xive2_properties[] = { DEFINE_PROP_UINT64("config", PnvXive2, config, PNV_XIVE2_CONFIGURATION), DEFINE_PROP_LINK("chip", PnvXive2, chip, TYPE_PNV_CHIP, PnvChip *), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_xive2_instance_init(Object *obj) diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c index d683413a83..7de4bf9885 100644 --- a/hw/intc/ppc-uic.c +++ b/hw/intc/ppc-uic.c @@ -262,7 +262,6 @@ static void ppc_uic_realize(DeviceState *dev, Error **errp) static const Property ppc_uic_properties[] = { DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0xc0), DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true), - DEFINE_PROP_END_OF_LIST() }; static const VMStateDescription ppc_uic_vmstate = { diff --git a/hw/intc/riscv_aclint.c b/hw/intc/riscv_aclint.c index db195fb1ff..db374a7c2d 100644 --- a/hw/intc/riscv_aclint.c +++ b/hw/intc/riscv_aclint.c @@ -274,7 +274,6 @@ static const Property riscv_aclint_mtimer_properties[] = { aperture_size, RISCV_ACLINT_DEFAULT_MTIMER_SIZE), DEFINE_PROP_UINT32("timebase-freq", RISCVAclintMTimerState, timebase_freq, 0), - DEFINE_PROP_END_OF_LIST(), }; static void riscv_aclint_mtimer_realize(DeviceState *dev, Error **errp) @@ -466,7 +465,6 @@ static const Property riscv_aclint_swi_properties[] = { DEFINE_PROP_UINT32("hartid-base", RISCVAclintSwiState, hartid_base, 0), DEFINE_PROP_UINT32("num-harts", RISCVAclintSwiState, num_harts, 1), DEFINE_PROP_UINT32("sswi", RISCVAclintSwiState, sswi, false), - DEFINE_PROP_END_OF_LIST(), }; static void riscv_aclint_swi_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/riscv_aplic.c b/hw/intc/riscv_aplic.c index b56edecb50..4866649115 100644 --- a/hw/intc/riscv_aplic.c +++ b/hw/intc/riscv_aplic.c @@ -32,6 +32,7 @@ #include "target/riscv/cpu.h" #include "system/system.h" #include "system/kvm.h" +#include "system/tcg.h" #include "kvm/kvm_riscv.h" #include "migration/vmstate.h" @@ -154,11 +155,38 @@ * KVM AIA only supports APLIC MSI, fallback to QEMU emulation if we want to use * APLIC Wired. */ -static bool is_kvm_aia(bool msimode) +bool riscv_is_kvm_aia_aplic_imsic(bool msimode) { return kvm_irqchip_in_kernel() && msimode; } +bool riscv_use_emulated_aplic(bool msimode) +{ +#ifdef CONFIG_KVM + if (tcg_enabled()) { + return true; + } + + if (!riscv_is_kvm_aia_aplic_imsic(msimode)) { + return true; + } + + return kvm_kernel_irqchip_split(); +#else + return true; +#endif +} + +void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr) +{ +#ifdef CONFIG_KVM + if (riscv_use_emulated_aplic(aplic->msimode)) { + aplic->kvm_msicfgaddr = extract64(addr, 0, 32); + aplic->kvm_msicfgaddrH = extract64(addr, 32, 32); + } +#endif +} + static bool riscv_aplic_irq_rectified_val(RISCVAPLICState *aplic, uint32_t irq) { @@ -248,9 +276,12 @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic, if ((sm == APLIC_SOURCECFG_SM_LEVEL_HIGH) || (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) { - if (!aplic->msimode || (aplic->msimode && !pending)) { + if (!aplic->msimode) { return; } + if (aplic->msimode && !pending) { + goto noskip_write_pending; + } if ((aplic->state[irq] & APLIC_ISTATE_INPUT) && (sm == APLIC_SOURCECFG_SM_LEVEL_LOW)) { return; @@ -261,6 +292,7 @@ static void riscv_aplic_set_pending(RISCVAPLICState *aplic, } } +noskip_write_pending: riscv_aplic_set_pending_raw(aplic, irq, pending); } @@ -359,13 +391,16 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic, uint32_t lhxs, lhxw, hhxs, hhxw, group_idx, msicfgaddr, msicfgaddrH; aplic_m = aplic; - while (aplic_m && !aplic_m->mmode) { - aplic_m = aplic_m->parent; - } - if (!aplic_m) { - qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n", - __func__); - return; + + if (!aplic->kvm_splitmode) { + while (aplic_m && !aplic_m->mmode) { + aplic_m = aplic_m->parent; + } + if (!aplic_m) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: m-level APLIC not found\n", + __func__); + return; + } } if (aplic->mmode) { @@ -397,6 +432,11 @@ static void riscv_aplic_msi_send(RISCVAPLICState *aplic, addr |= (uint64_t)(guest_idx & APLIC_xMSICFGADDR_PPN_HART(lhxs)); addr <<= APLIC_xMSICFGADDR_PPN_SHIFT; + if (aplic->kvm_splitmode) { + addr |= aplic->kvm_msicfgaddr; + addr |= ((uint64_t)aplic->kvm_msicfgaddrH << 32); + } + address_space_stl_le(&address_space_memory, addr, eiid, MEMTXATTRS_UNSPECIFIED, &result); if (result != MEMTX_OK) { @@ -853,7 +893,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) uint32_t i; RISCVAPLICState *aplic = RISCV_APLIC(dev); - if (!is_kvm_aia(aplic->msimode)) { + if (riscv_use_emulated_aplic(aplic->msimode)) { aplic->bitfield_words = (aplic->num_irqs + 31) >> 5; aplic->sourcecfg = g_new0(uint32_t, aplic->num_irqs); aplic->state = g_new0(uint32_t, aplic->num_irqs); @@ -870,6 +910,10 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) memory_region_init_io(&aplic->mmio, OBJECT(dev), &riscv_aplic_ops, aplic, TYPE_RISCV_APLIC, aplic->aperture_size); sysbus_init_mmio(SYS_BUS_DEVICE(dev), &aplic->mmio); + + if (kvm_enabled()) { + aplic->kvm_splitmode = true; + } } /* @@ -877,7 +921,7 @@ static void riscv_aplic_realize(DeviceState *dev, Error **errp) * have IRQ lines delegated by their parent APLIC. */ if (!aplic->parent) { - if (kvm_enabled() && is_kvm_aia(aplic->msimode)) { + if (kvm_enabled() && !riscv_use_emulated_aplic(aplic->msimode)) { qdev_init_gpio_in(dev, riscv_kvm_aplic_request, aplic->num_irqs); } else { qdev_init_gpio_in(dev, riscv_aplic_request, aplic->num_irqs); @@ -912,13 +956,12 @@ static const Property riscv_aplic_properties[] = { DEFINE_PROP_UINT32("num-irqs", RISCVAPLICState, num_irqs, 0), DEFINE_PROP_BOOL("msimode", RISCVAPLICState, msimode, 0), DEFINE_PROP_BOOL("mmode", RISCVAPLICState, mmode, 0), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_riscv_aplic = { .name = "riscv_aplic", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = (const VMStateField[]) { VMSTATE_UINT32(domaincfg, RISCVAPLICState), VMSTATE_UINT32(mmsicfgaddr, RISCVAPLICState), @@ -926,6 +969,8 @@ static const VMStateDescription vmstate_riscv_aplic = { VMSTATE_UINT32(smsicfgaddr, RISCVAPLICState), VMSTATE_UINT32(smsicfgaddrH, RISCVAPLICState), VMSTATE_UINT32(genmsi, RISCVAPLICState), + VMSTATE_UINT32(kvm_msicfgaddr, RISCVAPLICState), + VMSTATE_UINT32(kvm_msicfgaddrH, RISCVAPLICState), VMSTATE_VARRAY_UINT32(sourcecfg, RISCVAPLICState, num_irqs, 0, vmstate_info_uint32, uint32_t), @@ -1021,7 +1066,7 @@ DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - if (!is_kvm_aia(msimode)) { + if (riscv_use_emulated_aplic(msimode)) { sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); } diff --git a/hw/intc/riscv_imsic.c b/hw/intc/riscv_imsic.c index cfd9eca8bc..dc8162c0a7 100644 --- a/hw/intc/riscv_imsic.c +++ b/hw/intc/riscv_imsic.c @@ -393,7 +393,6 @@ static const Property riscv_imsic_properties[] = { DEFINE_PROP_UINT32("hartid", RISCVIMSICState, hartid, 0), DEFINE_PROP_UINT32("num-pages", RISCVIMSICState, num_pages, 0), DEFINE_PROP_UINT32("num-irqs", RISCVIMSICState, num_irqs, 0), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_riscv_imsic = { diff --git a/hw/intc/rx_icu.c b/hw/intc/rx_icu.c index dfe11ade20..ca13c5fb37 100644 --- a/hw/intc/rx_icu.c +++ b/hw/intc/rx_icu.c @@ -366,7 +366,6 @@ static const Property rxicu_properties[] = { qdev_prop_uint8, uint8_t), DEFINE_PROP_ARRAY("trigger-level", RXICUState, nr_sense, init_sense, qdev_prop_uint8, uint8_t), - DEFINE_PROP_END_OF_LIST(), }; static void rxicu_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/s390_flic.c b/hw/intc/s390_flic.c index 2963bd5bd6..3f3fa939d3 100644 --- a/hw/intc/s390_flic.c +++ b/hw/intc/s390_flic.c @@ -448,7 +448,6 @@ static void qemu_s390_flic_instance_init(Object *obj) static const Property qemu_s390_flic_properties[] = { DEFINE_PROP_BOOL("migrate-all-state", QEMUS390FLICState, migrate_all_state, true), - DEFINE_PROP_END_OF_LIST(), }; static void qemu_s390_flic_class_init(ObjectClass *oc, void *data) @@ -476,7 +475,6 @@ static const Property s390_flic_common_properties[] = { adapter_routes_max_batch, ADAPTER_ROUTES_MAX_GSI), DEFINE_PROP_BOOL("migration-enabled", S390FLICState, migration_enabled, true), - DEFINE_PROP_END_OF_LIST(), }; static void s390_flic_common_realize(DeviceState *dev, Error **errp) diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 5b011b2a7d..a5b0f6ef1b 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -444,7 +444,6 @@ static const Property sifive_plic_properties[] = { DEFINE_PROP_UINT32("context-base", SiFivePLICState, context_base, 0), DEFINE_PROP_UINT32("context-stride", SiFivePLICState, context_stride, 0), DEFINE_PROP_UINT32("aperture-size", SiFivePLICState, aperture_size, 0), - DEFINE_PROP_END_OF_LIST(), }; static void sifive_plic_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index bb9b2a4a12..a764c0bb57 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -633,7 +633,6 @@ static const Property spapr_xive_properties[] = { DEFINE_PROP_UINT64("vc-base", SpaprXive, vc_base, SPAPR_XIVE_VC_BASE), DEFINE_PROP_UINT64("tm-base", SpaprXive, tm_base, SPAPR_XIVE_TM_BASE), DEFINE_PROP_UINT8("hv-prio", SpaprXive, hv_prio, 7), - DEFINE_PROP_END_OF_LIST(), }; static int spapr_xive_cpu_intc_create(SpaprInterruptController *intc, diff --git a/hw/intc/xics.c b/hw/intc/xics.c index aa3f7d7daa..9c1b7bbe9e 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -348,7 +348,6 @@ static const Property icp_properties[] = { DEFINE_PROP_LINK(ICP_PROP_XICS, ICPState, xics, TYPE_XICS_FABRIC, XICSFabric *), DEFINE_PROP_LINK(ICP_PROP_CPU, ICPState, cs, TYPE_CPU, CPUState *), - DEFINE_PROP_END_OF_LIST(), }; static void icp_class_init(ObjectClass *klass, void *data) @@ -680,7 +679,6 @@ static const Property ics_properties[] = { DEFINE_PROP_UINT32("nr-irqs", ICSState, nr_irqs, 0), DEFINE_PROP_LINK(ICS_PROP_XICS, ICSState, xics, TYPE_XICS_FABRIC, XICSFabric *), - DEFINE_PROP_END_OF_LIST(), }; static void ics_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/xilinx_intc.c b/hw/intc/xilinx_intc.c index 3e860ab582..d99cf567ae 100644 --- a/hw/intc/xilinx_intc.c +++ b/hw/intc/xilinx_intc.c @@ -178,7 +178,6 @@ static void xilinx_intc_init(Object *obj) static const Property xilinx_intc_properties[] = { DEFINE_PROP_UINT32("kind-of-intr", XpsIntc, c_kind_of_intr, 0), - DEFINE_PROP_END_OF_LIST(), }; static void xilinx_intc_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/xive.c b/hw/intc/xive.c index 5994e4ce36..139cfdf9bf 100644 --- a/hw/intc/xive.c +++ b/hw/intc/xive.c @@ -931,7 +931,6 @@ static const Property xive_tctx_properties[] = { DEFINE_PROP_LINK("cpu", XiveTCTX, cs, TYPE_CPU, CPUState *), DEFINE_PROP_LINK("presenter", XiveTCTX, xptr, TYPE_XIVE_PRESENTER, XivePresenter *), - DEFINE_PROP_END_OF_LIST(), }; static void xive_tctx_class_init(ObjectClass *klass, void *data) @@ -1414,7 +1413,6 @@ static const Property xive_source_properties[] = { DEFINE_PROP_UINT8("reset-pq", XiveSource, reset_pq, XIVE_ESB_OFF), DEFINE_PROP_LINK("xive", XiveSource, xive, TYPE_XIVE_NOTIFIER, XiveNotifier *), - DEFINE_PROP_END_OF_LIST(), }; static void xive_source_class_init(ObjectClass *klass, void *data) @@ -2005,7 +2003,6 @@ void xive_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) static const Property xive_router_properties[] = { DEFINE_PROP_LINK("xive-fabric", XiveRouter, xfb, TYPE_XIVE_FABRIC, XiveFabric *), - DEFINE_PROP_END_OF_LIST(), }; static void xive_router_class_init(ObjectClass *klass, void *data) @@ -2175,7 +2172,6 @@ static const Property xive_end_source_properties[] = { DEFINE_PROP_UINT32("shift", XiveENDSource, esb_shift, XIVE_ESB_64K), DEFINE_PROP_LINK("xive", XiveENDSource, xrtr, TYPE_XIVE_ROUTER, XiveRouter *), - DEFINE_PROP_END_OF_LIST(), }; static void xive_end_source_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/xive2.c b/hw/intc/xive2.c index 91d3d68705..fc5aed3315 100644 --- a/hw/intc/xive2.c +++ b/hw/intc/xive2.c @@ -1031,7 +1031,6 @@ void xive2_router_notify(XiveNotifier *xn, uint32_t lisn, bool pq_checked) static const Property xive2_router_properties[] = { DEFINE_PROP_LINK("xive-fabric", Xive2Router, xfb, TYPE_XIVE_FABRIC, XiveFabric *), - DEFINE_PROP_END_OF_LIST(), }; static void xive2_router_class_init(ObjectClass *klass, void *data) @@ -1247,7 +1246,6 @@ static const Property xive2_end_source_properties[] = { DEFINE_PROP_UINT32("shift", Xive2EndSource, esb_shift, XIVE_ESB_64K), DEFINE_PROP_LINK("xive", Xive2EndSource, xrtr, TYPE_XIVE2_ROUTER, Xive2Router *), - DEFINE_PROP_END_OF_LIST(), }; static void xive2_end_source_class_init(ObjectClass *klass, void *data) diff --git a/hw/intc/xlnx-pmu-iomod-intc.c b/hw/intc/xlnx-pmu-iomod-intc.c index 21b9c83658..ccdab244b3 100644 --- a/hw/intc/xlnx-pmu-iomod-intc.c +++ b/hw/intc/xlnx-pmu-iomod-intc.c @@ -478,7 +478,6 @@ static const Property xlnx_pmu_io_intc_properties[] = { DEFINE_PROP_UINT32("intc-intr-size", XlnxPMUIOIntc, cfg.intr_size, 0), DEFINE_PROP_UINT32("intc-level-edge", XlnxPMUIOIntc, cfg.level_edge, 0), DEFINE_PROP_UINT32("intc-positive", XlnxPMUIOIntc, cfg.positive, 0), - DEFINE_PROP_END_OF_LIST(), }; static void xlnx_pmu_io_intc_realize(DeviceState *dev, Error **errp) diff --git a/hw/ipack/ipack.c b/hw/ipack/ipack.c index 7ffc4ffe6f..ed75f79183 100644 --- a/hw/ipack/ipack.c +++ b/hw/ipack/ipack.c @@ -75,7 +75,6 @@ static void ipack_device_unrealize(DeviceState *dev) static const Property ipack_device_props[] = { DEFINE_PROP_INT32("slot", IPackDevice, slot, -1), - DEFINE_PROP_END_OF_LIST() }; static void ipack_device_class_init(ObjectClass *klass, void *data) diff --git a/hw/ipmi/ipmi.c b/hw/ipmi/ipmi.c index a1cb853d92..fdeaa5269f 100644 --- a/hw/ipmi/ipmi.c +++ b/hw/ipmi/ipmi.c @@ -110,7 +110,6 @@ void ipmi_bmc_find_and_link(Object *obj, Object **bmc) static const Property ipmi_bmc_properties[] = { DEFINE_PROP_UINT8("slave_addr", IPMIBmc, slave_addr, 0x20), - DEFINE_PROP_END_OF_LIST(), }; static void bmc_class_init(ObjectClass *oc, void *data) diff --git a/hw/ipmi/ipmi_bmc_extern.c b/hw/ipmi/ipmi_bmc_extern.c index cfec1da87c..d015500254 100644 --- a/hw/ipmi/ipmi_bmc_extern.c +++ b/hw/ipmi/ipmi_bmc_extern.c @@ -517,7 +517,6 @@ static void ipmi_bmc_extern_finalize(Object *obj) static const Property ipmi_bmc_extern_properties[] = { DEFINE_PROP_CHR("chardev", IPMIBmcExtern, chr), - DEFINE_PROP_END_OF_LIST(), }; static void ipmi_bmc_extern_class_init(ObjectClass *oc, void *data) diff --git a/hw/ipmi/ipmi_bmc_sim.c b/hw/ipmi/ipmi_bmc_sim.c index bd02e8244e..6157ac7120 100644 --- a/hw/ipmi/ipmi_bmc_sim.c +++ b/hw/ipmi/ipmi_bmc_sim.c @@ -2203,7 +2203,6 @@ static const Property ipmi_sim_properties[] = { DEFINE_PROP_UINT32("mfg_id", IPMIBmcSim, mfg_id, 0), DEFINE_PROP_UINT16("product_id", IPMIBmcSim, product_id, 0), DEFINE_PROP_UUID_NODEFAULT("guid", IPMIBmcSim, uuid), - DEFINE_PROP_END_OF_LIST(), }; static void ipmi_sim_class_init(ObjectClass *oc, void *data) diff --git a/hw/ipmi/isa_ipmi_bt.c b/hw/ipmi/isa_ipmi_bt.c index 16062abb31..a1b66d5ee8 100644 --- a/hw/ipmi/isa_ipmi_bt.c +++ b/hw/ipmi/isa_ipmi_bt.c @@ -138,7 +138,6 @@ static void *isa_ipmi_bt_get_backend_data(IPMIInterface *ii) static const Property ipmi_isa_properties[] = { DEFINE_PROP_UINT32("ioport", ISAIPMIBTDevice, bt.io_base, 0xe4), DEFINE_PROP_INT32("irq", ISAIPMIBTDevice, isairq, 5), - DEFINE_PROP_END_OF_LIST(), }; static void isa_ipmi_bt_class_init(ObjectClass *oc, void *data) diff --git a/hw/ipmi/isa_ipmi_kcs.c b/hw/ipmi/isa_ipmi_kcs.c index 7e7a37659e..d9ebdd5371 100644 --- a/hw/ipmi/isa_ipmi_kcs.c +++ b/hw/ipmi/isa_ipmi_kcs.c @@ -145,7 +145,6 @@ static void *isa_ipmi_kcs_get_backend_data(IPMIInterface *ii) static const Property ipmi_isa_properties[] = { DEFINE_PROP_UINT32("ioport", ISAIPMIKCSDevice, kcs.io_base, 0xca2), DEFINE_PROP_INT32("irq", ISAIPMIKCSDevice, isairq, 5), - DEFINE_PROP_END_OF_LIST(), }; static void isa_ipmi_kcs_class_init(ObjectClass *oc, void *data) diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 46a74fd6ef..dcb0ac2848 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -840,7 +840,6 @@ static const Property ich9_lpc_properties[] = { pm.swsmi_timer_enabled, true), DEFINE_PROP_BOOL("x-smi-periodic-timer", ICH9LPCState, pm.periodic_timer_enabled, true), - DEFINE_PROP_END_OF_LIST(), }; static void ich9_send_gpe(AcpiDeviceIf *adev, AcpiEventStatusBits ev) diff --git a/hw/isa/pc87312.c b/hw/isa/pc87312.c index 7bb2af817d..5f5868442a 100644 --- a/hw/isa/pc87312.c +++ b/hw/isa/pc87312.c @@ -330,7 +330,6 @@ static const VMStateDescription vmstate_pc87312 = { static const Property pc87312_properties[] = { DEFINE_PROP_UINT16("iobase", PC87312State, iobase, 0x398), DEFINE_PROP_UINT8("config", PC87312State, config, 1), - DEFINE_PROP_END_OF_LIST() }; static void pc87312_class_init(ObjectClass *klass, void *data) diff --git a/hw/isa/piix.c b/hw/isa/piix.c index fee4d8804c..7fc9e3ec9d 100644 --- a/hw/isa/piix.c +++ b/hw/isa/piix.c @@ -415,7 +415,6 @@ static const Property pci_piix_props[] = { DEFINE_PROP_BOOL("has-pit", PIIXState, has_pit, true), DEFINE_PROP_BOOL("has-usb", PIIXState, has_usb, true), DEFINE_PROP_BOOL("smm-enabled", PIIXState, smm_enabled, false), - DEFINE_PROP_END_OF_LIST(), }; static void pci_piix_class_init(ObjectClass *klass, void *data) diff --git a/hw/loongarch/acpi-build.c b/hw/loongarch/acpi-build.c index d538946bc3..9eb5fb68bf 100644 --- a/hw/loongarch/acpi-build.c +++ b/hw/loongarch/acpi-build.c @@ -276,8 +276,12 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, MachineState *machine) }; lvms = LOONGARCH_VIRT_MACHINE(machine); + /* + * Passing NULL as the SPCR Table for Revision 2 doesn't support + * NameSpaceString. + */ build_spcr(table_data, linker, &serial, 2, lvms->oem_id, - lvms->oem_table_id); + lvms->oem_table_id, NULL); } typedef diff --git a/hw/m68k/mcf5206.c b/hw/m68k/mcf5206.c index 427b2ba095..ef619cb9a4 100644 --- a/hw/m68k/mcf5206.c +++ b/hw/m68k/mcf5206.c @@ -603,7 +603,6 @@ static void mcf5206_mbar_realize(DeviceState *dev, Error **errp) static const Property mcf5206_mbar_properties[] = { DEFINE_PROP_LINK("m68k-cpu", m5206_mbar_state, cpu, TYPE_M68K_CPU, M68kCPU *), - DEFINE_PROP_END_OF_LIST(), }; static void mcf5206_mbar_class_init(ObjectClass *oc, void *data) diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c index c24b0b715d..008626f813 100644 --- a/hw/m68k/mcf_intc.c +++ b/hw/m68k/mcf_intc.c @@ -180,7 +180,6 @@ static void mcf_intc_instance_init(Object *obj) static const Property mcf_intc_properties[] = { DEFINE_PROP_LINK("m68k-cpu", mcf_intc_state, cpu, TYPE_M68K_CPU, M68kCPU *), - DEFINE_PROP_END_OF_LIST(), }; static void mcf_intc_class_init(ObjectClass *oc, void *data) diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index ec0794adba..0ecdcea823 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -916,7 +916,6 @@ static void next_pc_realize(DeviceState *dev, Error **errp) */ static const Property next_pc_properties[] = { DEFINE_PROP_LINK("cpu", NeXTPC, cpu, TYPE_M68K_CPU, M68kCPU *), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription next_rtc_vmstate = { diff --git a/hw/m68k/q800-glue.c b/hw/m68k/q800-glue.c index 0d8cb8b1cb..168665b382 100644 --- a/hw/m68k/q800-glue.c +++ b/hw/m68k/q800-glue.c @@ -205,7 +205,6 @@ static const VMStateDescription vmstate_glue = { */ static const Property glue_properties[] = { DEFINE_PROP_LINK("cpu", GLUEState, cpu, TYPE_M68K_CPU, M68kCPU *), - DEFINE_PROP_END_OF_LIST(), }; static void glue_finalize(Object *obj) diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c index dcaf401764..bd7652740f 100644 --- a/hw/mem/cxl_type3.c +++ b/hw/mem/cxl_type3.c @@ -1234,7 +1234,6 @@ static const Property ct3_props[] = { speed, PCIE_LINK_SPEED_32), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLType3Dev, width, PCIE_LINK_WIDTH_16), - DEFINE_PROP_END_OF_LIST(), }; static uint64_t get_lsa_size(CXLType3Dev *ct3d) diff --git a/hw/mem/nvdimm.c b/hw/mem/nvdimm.c index 9786319f27..c05007ab21 100644 --- a/hw/mem/nvdimm.c +++ b/hw/mem/nvdimm.c @@ -248,7 +248,6 @@ static void nvdimm_write_label_data(NVDIMMDevice *nvdimm, const void *buf, static const Property nvdimm_properties[] = { DEFINE_PROP_BOOL(NVDIMM_UNARMED_PROP, NVDIMMDevice, unarmed, false), - DEFINE_PROP_END_OF_LIST(), }; static void nvdimm_class_init(ObjectClass *oc, void *data) diff --git a/hw/mem/pc-dimm.c b/hw/mem/pc-dimm.c index d2783523a8..799a618c1c 100644 --- a/hw/mem/pc-dimm.c +++ b/hw/mem/pc-dimm.c @@ -157,7 +157,6 @@ static const Property pc_dimm_properties[] = { PC_DIMM_UNASSIGNED_SLOT), DEFINE_PROP_LINK(PC_DIMM_MEMDEV_PROP, PCDIMMDevice, hostmem, TYPE_MEMORY_BACKEND, HostMemoryBackend *), - DEFINE_PROP_END_OF_LIST(), }; static void pc_dimm_get_size(Object *obj, Visitor *v, const char *name, diff --git a/hw/mem/sparse-mem.c b/hw/mem/sparse-mem.c index 1f647f8096..6a9a591370 100644 --- a/hw/mem/sparse-mem.c +++ b/hw/mem/sparse-mem.c @@ -103,7 +103,6 @@ static const Property sparse_mem_properties[] = { DEFINE_PROP_UINT64("length", SparseMemState, length, UINT64_MAX), /* Max amount of actual memory that can be used to back the sparse memory */ DEFINE_PROP_UINT64("maxsize", SparseMemState, maxsize, 10 * MiB), - DEFINE_PROP_END_OF_LIST(), }; MemoryRegion *sparse_mem_init(uint64_t addr, uint64_t length) diff --git a/hw/mips/cps.c b/hw/mips/cps.c index 2d442fe113..0d8cbdc892 100644 --- a/hw/mips/cps.c +++ b/hw/mips/cps.c @@ -171,7 +171,6 @@ static const Property mips_cps_properties[] = { DEFINE_PROP_UINT32("num-irq", MIPSCPSState, num_irq, 256), DEFINE_PROP_STRING("cpu-type", MIPSCPSState, cpu_type), DEFINE_PROP_BOOL("cpu-big-endian", MIPSCPSState, cpu_is_bigendian, false), - DEFINE_PROP_END_OF_LIST() }; static void mips_cps_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/a9scu.c b/hw/misc/a9scu.c index e2d73edde8..088d4adb0d 100644 --- a/hw/misc/a9scu.c +++ b/hw/misc/a9scu.c @@ -125,7 +125,6 @@ static const VMStateDescription vmstate_a9_scu = { static const Property a9_scu_properties[] = { DEFINE_PROP_UINT32("num-cpu", A9SCUState, num_cpu, 1), - DEFINE_PROP_END_OF_LIST(), }; static void a9_scu_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/allwinner-h3-dramc.c b/hw/misc/allwinner-h3-dramc.c index 247bf62c43..13bba26d0e 100644 --- a/hw/misc/allwinner-h3-dramc.c +++ b/hw/misc/allwinner-h3-dramc.c @@ -317,7 +317,6 @@ static void allwinner_h3_dramc_init(Object *obj) static const Property allwinner_h3_dramc_properties[] = { DEFINE_PROP_UINT64("ram-addr", AwH3DramCtlState, ram_addr, 0x0), DEFINE_PROP_UINT32("ram-size", AwH3DramCtlState, ram_size, 256 * MiB), - DEFINE_PROP_END_OF_LIST() }; static const VMStateDescription allwinner_h3_dramc_vmstate = { diff --git a/hw/misc/allwinner-r40-dramc.c b/hw/misc/allwinner-r40-dramc.c index a51284ff91..97c3664e3a 100644 --- a/hw/misc/allwinner-r40-dramc.c +++ b/hw/misc/allwinner-r40-dramc.c @@ -467,7 +467,6 @@ static void allwinner_r40_dramc_init(Object *obj) static const Property allwinner_r40_dramc_properties[] = { DEFINE_PROP_UINT64("ram-addr", AwR40DramCtlState, ram_addr, 0x0), DEFINE_PROP_UINT32("ram-size", AwR40DramCtlState, ram_size, 256), /* MiB */ - DEFINE_PROP_END_OF_LIST() }; static const VMStateDescription allwinner_r40_dramc_vmstate = { diff --git a/hw/misc/allwinner-sid.c b/hw/misc/allwinner-sid.c index 3a09dca111..042b747f30 100644 --- a/hw/misc/allwinner-sid.c +++ b/hw/misc/allwinner-sid.c @@ -129,7 +129,6 @@ static void allwinner_sid_init(Object *obj) static const Property allwinner_sid_properties[] = { DEFINE_PROP_UUID_NODEFAULT("identifier", AwSidState, identifier), - DEFINE_PROP_END_OF_LIST() }; static const VMStateDescription allwinner_sid_vmstate = { diff --git a/hw/misc/applesmc.c b/hw/misc/applesmc.c index 9d0e273e33..97ea842d60 100644 --- a/hw/misc/applesmc.c +++ b/hw/misc/applesmc.c @@ -354,7 +354,6 @@ static const Property applesmc_isa_properties[] = { DEFINE_PROP_UINT32(APPLESMC_PROP_IO_BASE, AppleSMCState, iobase, APPLESMC_DEFAULT_IOBASE), DEFINE_PROP_STRING("osk", AppleSMCState, osk), - DEFINE_PROP_END_OF_LIST(), }; static void build_applesmc_aml(AcpiDevAmlIf *adev, Aml *scope) diff --git a/hw/misc/arm11scu.c b/hw/misc/arm11scu.c index 37feed9da7..02493cec31 100644 --- a/hw/misc/arm11scu.c +++ b/hw/misc/arm11scu.c @@ -77,7 +77,6 @@ static void arm11_scu_init(Object *obj) static const Property arm11_scu_properties[] = { DEFINE_PROP_UINT32("num-cpu", ARM11SCUState, num_cpu, 1), - DEFINE_PROP_END_OF_LIST() }; static void arm11_scu_class_init(ObjectClass *oc, void *data) diff --git a/hw/misc/arm_l2x0.c b/hw/misc/arm_l2x0.c index 9c209f13b0..39b4642da7 100644 --- a/hw/misc/arm_l2x0.c +++ b/hw/misc/arm_l2x0.c @@ -175,7 +175,6 @@ static void l2x0_priv_init(Object *obj) static const Property l2x0_properties[] = { DEFINE_PROP_UINT32("cache-type", L2x0State, cache_type, 0x1c100100), - DEFINE_PROP_END_OF_LIST(), }; static void l2x0_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/arm_sysctl.c b/hw/misc/arm_sysctl.c index d13a070204..016a302e67 100644 --- a/hw/misc/arm_sysctl.c +++ b/hw/misc/arm_sysctl.c @@ -632,7 +632,6 @@ static const Property arm_sysctl_properties[] = { /* Daughterboard clock reset values (as reported via SYS_CFG) */ DEFINE_PROP_ARRAY("db-clock", arm_sysctl_state, db_num_clocks, db_clock_reset, qdev_prop_uint32, uint32_t), - DEFINE_PROP_END_OF_LIST(), }; static void arm_sysctl_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/armsse-cpuid.c b/hw/misc/armsse-cpuid.c index b05bcdcabc..58cb37333f 100644 --- a/hw/misc/armsse-cpuid.c +++ b/hw/misc/armsse-cpuid.c @@ -94,7 +94,6 @@ static const MemoryRegionOps armsse_cpuid_ops = { static const Property armsse_cpuid_props[] = { DEFINE_PROP_UINT32("CPUID", ARMSSECPUID, cpuid, 0), - DEFINE_PROP_END_OF_LIST() }; static void armsse_cpuid_init(Object *obj) diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c index 5cefbadf9a..e3f7df2e86 100644 --- a/hw/misc/aspeed_hace.c +++ b/hw/misc/aspeed_hace.c @@ -439,7 +439,6 @@ static void aspeed_hace_realize(DeviceState *dev, Error **errp) static const Property aspeed_hace_properties[] = { DEFINE_PROP_LINK("dram", AspeedHACEState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/misc/aspeed_i3c.c b/hw/misc/aspeed_i3c.c index 7f5a389864..ab39c6435b 100644 --- a/hw/misc/aspeed_i3c.c +++ b/hw/misc/aspeed_i3c.c @@ -325,7 +325,6 @@ static void aspeed_i3c_realize(DeviceState *dev, Error **errp) static const Property aspeed_i3c_device_properties[] = { DEFINE_PROP_UINT8("device-id", AspeedI3CDevice, id, 0), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_i3c_device_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/aspeed_lpc.c b/hw/misc/aspeed_lpc.c index bb9066b0f0..228d250dc0 100644 --- a/hw/misc/aspeed_lpc.c +++ b/hw/misc/aspeed_lpc.c @@ -456,7 +456,6 @@ static const VMStateDescription vmstate_aspeed_lpc = { static const Property aspeed_lpc_properties[] = { DEFINE_PROP_UINT32("hicr7", AspeedLPCState, hicr7, 0), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_lpc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/aspeed_sbc.c b/hw/misc/aspeed_sbc.c index b97cf51fa1..e4a6bd1581 100644 --- a/hw/misc/aspeed_sbc.c +++ b/hw/misc/aspeed_sbc.c @@ -139,7 +139,6 @@ static const VMStateDescription vmstate_aspeed_sbc = { static const Property aspeed_sbc_properties[] = { DEFINE_PROP_BOOL("emmc-abr", AspeedSBCState, emmc_abr, 0), DEFINE_PROP_UINT32("signing-settings", AspeedSBCState, signing_settings, 0), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_sbc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index ac33b8d6cb..bac1441b06 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -607,7 +607,6 @@ static const Property aspeed_scu_properties[] = { DEFINE_PROP_UINT32("hw-strap1", AspeedSCUState, hw_strap1, 0), DEFINE_PROP_UINT32("hw-strap2", AspeedSCUState, hw_strap2, 0), DEFINE_PROP_UINT32("hw-prot-key", AspeedSCUState, hw_prot_key, 0), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_scu_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/aspeed_sdmc.c b/hw/misc/aspeed_sdmc.c index 4980080f74..f359640a9a 100644 --- a/hw/misc/aspeed_sdmc.c +++ b/hw/misc/aspeed_sdmc.c @@ -297,7 +297,6 @@ static const VMStateDescription vmstate_aspeed_sdmc = { static const Property aspeed_sdmc_properties[] = { DEFINE_PROP_UINT64("max-ram-size", AspeedSDMCState, max_ram_size, 0), DEFINE_PROP_BOOL("unlocked", AspeedSDMCState, unlocked, false), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_sdmc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/bcm2835_cprman.c b/hw/misc/bcm2835_cprman.c index 1a20cd0bc8..aa14cd931f 100644 --- a/hw/misc/bcm2835_cprman.c +++ b/hw/misc/bcm2835_cprman.c @@ -780,7 +780,6 @@ static const VMStateDescription cprman_vmstate = { static const Property cprman_properties[] = { DEFINE_PROP_UINT32("xosc-freq-hz", BCM2835CprmanState, xosc_freq, 19200000), - DEFINE_PROP_END_OF_LIST() }; static void cprman_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/bcm2835_property.c b/hw/misc/bcm2835_property.c index ffba747f8c..2bae64b64c 100644 --- a/hw/misc/bcm2835_property.c +++ b/hw/misc/bcm2835_property.c @@ -554,7 +554,6 @@ static void bcm2835_property_realize(DeviceState *dev, Error **errp) static const Property bcm2835_property_props[] = { DEFINE_PROP_UINT32("board-rev", BCM2835PropertyState, board_rev, 0), DEFINE_PROP_STRING("command-line", BCM2835PropertyState, command_line), - DEFINE_PROP_END_OF_LIST() }; static void bcm2835_property_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/debugexit.c b/hw/misc/debugexit.c index 8bd4563ae9..577b884494 100644 --- a/hw/misc/debugexit.c +++ b/hw/misc/debugexit.c @@ -59,7 +59,6 @@ static void debug_exit_realizefn(DeviceState *d, Error **errp) static const Property debug_exit_properties[] = { DEFINE_PROP_UINT32("iobase", ISADebugExitState, iobase, 0x501), DEFINE_PROP_UINT32("iosize", ISADebugExitState, iosize, 0x02), - DEFINE_PROP_END_OF_LIST(), }; static void debug_exit_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/misc/eccmemctl.c b/hw/misc/eccmemctl.c index 4fc88bd4e5..d7452c4cc8 100644 --- a/hw/misc/eccmemctl.c +++ b/hw/misc/eccmemctl.c @@ -327,7 +327,6 @@ static void ecc_realize(DeviceState *dev, Error **errp) static const Property ecc_properties[] = { DEFINE_PROP_UINT32("version", ECCState, version, -1), - DEFINE_PROP_END_OF_LIST(), }; static void ecc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/empty_slot.c b/hw/misc/empty_slot.c index 79572c5be0..221ea7cb54 100644 --- a/hw/misc/empty_slot.c +++ b/hw/misc/empty_slot.c @@ -82,7 +82,6 @@ static void empty_slot_realize(DeviceState *dev, Error **errp) static const Property empty_slot_properties[] = { DEFINE_PROP_UINT64("size", EmptySlot, size, 0), DEFINE_PROP_STRING("name", EmptySlot, name), - DEFINE_PROP_END_OF_LIST(), }; static void empty_slot_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/iotkit-secctl.c b/hw/misc/iotkit-secctl.c index abb6a963ca..04ced3559c 100644 --- a/hw/misc/iotkit-secctl.c +++ b/hw/misc/iotkit-secctl.c @@ -816,7 +816,6 @@ static const VMStateDescription iotkit_secctl_vmstate = { static const Property iotkit_secctl_props[] = { DEFINE_PROP_UINT32("sse-version", IoTKitSecCtl, sse_version, 0), - DEFINE_PROP_END_OF_LIST() }; static void iotkit_secctl_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/iotkit-sysctl.c b/hw/misc/iotkit-sysctl.c index 93db754ce0..c654af2e88 100644 --- a/hw/misc/iotkit-sysctl.c +++ b/hw/misc/iotkit-sysctl.c @@ -842,7 +842,6 @@ static const Property iotkit_sysctl_props[] = { 0x10000000), DEFINE_PROP_UINT32("INITSVTOR1_RST", IoTKitSysCtl, initsvtor1_rst, 0x10000000), - DEFINE_PROP_END_OF_LIST() }; static void iotkit_sysctl_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/iotkit-sysinfo.c b/hw/misc/iotkit-sysinfo.c index 7d4eea6bfb..75260f7fab 100644 --- a/hw/misc/iotkit-sysinfo.c +++ b/hw/misc/iotkit-sysinfo.c @@ -136,7 +136,6 @@ static const Property iotkit_sysinfo_props[] = { DEFINE_PROP_UINT32("SYS_CONFIG", IoTKitSysInfo, sys_config, 0), DEFINE_PROP_UINT32("sse-version", IoTKitSysInfo, sse_version, 0), DEFINE_PROP_UINT32("IIDR", IoTKitSysInfo, iidr, 0), - DEFINE_PROP_END_OF_LIST() }; static void iotkit_sysinfo_init(Object *obj) diff --git a/hw/misc/ivshmem.c b/hw/misc/ivshmem.c index e7c1d23570..900d523334 100644 --- a/hw/misc/ivshmem.c +++ b/hw/misc/ivshmem.c @@ -1026,7 +1026,6 @@ static const Property ivshmem_plain_properties[] = { DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), DEFINE_PROP_LINK("memdev", IVShmemState, hostmem, TYPE_MEMORY_BACKEND, HostMemoryBackend *), - DEFINE_PROP_END_OF_LIST(), }; static void ivshmem_plain_realize(PCIDevice *dev, Error **errp) @@ -1083,7 +1082,6 @@ static const Property ivshmem_doorbell_properties[] = { DEFINE_PROP_BIT("ioeventfd", IVShmemState, features, IVSHMEM_IOEVENTFD, true), DEFINE_PROP_ON_OFF_AUTO("master", IVShmemState, master, ON_OFF_AUTO_OFF), - DEFINE_PROP_END_OF_LIST(), }; static void ivshmem_doorbell_init(Object *obj) diff --git a/hw/misc/led.c b/hw/misc/led.c index 76efdbc3f1..9364d9945e 100644 --- a/hw/misc/led.c +++ b/hw/misc/led.c @@ -105,7 +105,6 @@ static const Property led_properties[] = { DEFINE_PROP_STRING("color", LEDState, color), DEFINE_PROP_STRING("description", LEDState, description), DEFINE_PROP_BOOL("gpio-active-high", LEDState, gpio_active_high, true), - DEFINE_PROP_END_OF_LIST(), }; static void led_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/mac_via.c b/hw/misc/mac_via.c index ed767cde60..03b1feda50 100644 --- a/hw/misc/mac_via.c +++ b/hw/misc/mac_via.c @@ -1324,7 +1324,6 @@ static const VMStateDescription vmstate_q800_via1 = { static const Property mos6522_q800_via1_properties[] = { DEFINE_PROP_DRIVE("drive", MOS6522Q800VIA1State, blk), - DEFINE_PROP_END_OF_LIST(), }; static void mos6522_q800_via1_class_init(ObjectClass *oc, void *data) diff --git a/hw/misc/macio/cuda.c b/hw/misc/macio/cuda.c index 8130421d5d..34731ae560 100644 --- a/hw/misc/macio/cuda.c +++ b/hw/misc/macio/cuda.c @@ -556,7 +556,6 @@ static void cuda_init(Object *obj) static const Property cuda_properties[] = { DEFINE_PROP_UINT64("timebase-frequency", CUDAState, tb_frequency, 0), - DEFINE_PROP_END_OF_LIST() }; static void cuda_class_init(ObjectClass *oc, void *data) diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index 7e3d5aa977..194b152eff 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -408,7 +408,6 @@ static const VMStateDescription vmstate_macio_newworld = { static const Property macio_newworld_properties[] = { DEFINE_PROP_BOOL("has-pmu", NewWorldMacIOState, has_pmu, false), DEFINE_PROP_BOOL("has-adb", NewWorldMacIOState, has_adb, false), - DEFINE_PROP_END_OF_LIST() }; static void macio_newworld_class_init(ObjectClass *oc, void *data) @@ -424,7 +423,6 @@ static void macio_newworld_class_init(ObjectClass *oc, void *data) static const Property macio_properties[] = { DEFINE_PROP_UINT64("frequency", MacIOState, frequency, 0), - DEFINE_PROP_END_OF_LIST() }; static void macio_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/macio/pmu.c b/hw/misc/macio/pmu.c index 2dd8af1ae6..73190559a8 100644 --- a/hw/misc/macio/pmu.c +++ b/hw/misc/macio/pmu.c @@ -762,7 +762,6 @@ static void pmu_init(Object *obj) static const Property pmu_properties[] = { DEFINE_PROP_BOOL("has-adb", PMUState, has_adb, true), - DEFINE_PROP_END_OF_LIST() }; static void pmu_class_init(ObjectClass *oc, void *data) diff --git a/hw/misc/mips_cmgcr.c b/hw/misc/mips_cmgcr.c index 80ca224f76..95f19912b4 100644 --- a/hw/misc/mips_cmgcr.c +++ b/hw/misc/mips_cmgcr.c @@ -219,7 +219,6 @@ static const Property mips_gcr_properties[] = { MemoryRegion *), DEFINE_PROP_LINK("cpc", MIPSGCRState, cpc_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void mips_gcr_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/mips_cpc.c b/hw/misc/mips_cpc.c index 86ff0f7ad8..772b8c0017 100644 --- a/hw/misc/mips_cpc.c +++ b/hw/misc/mips_cpc.c @@ -166,7 +166,6 @@ static const VMStateDescription vmstate_mips_cpc = { static const Property mips_cpc_properties[] = { DEFINE_PROP_UINT32("num-vp", MIPSCPCState, num_vp, 0x1), DEFINE_PROP_UINT64("vp-start-running", MIPSCPCState, vp_start_running, 0x1), - DEFINE_PROP_END_OF_LIST(), }; static void mips_cpc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index d84a7dbf15..2d126ebaf8 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -538,7 +538,6 @@ static const Property mips_itu_properties[] = { ITC_FIFO_NUM_MAX), DEFINE_PROP_UINT32("num-semaphores", MIPSITUState, num_semaphores, ITC_SEMAPH_NUM_MAX), - DEFINE_PROP_END_OF_LIST(), }; static void mips_itu_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/mos6522.c b/hw/misc/mos6522.c index 0225a5869b..0b8f6a4cb4 100644 --- a/hw/misc/mos6522.c +++ b/hw/misc/mos6522.c @@ -698,7 +698,6 @@ static void mos6522_finalize(Object *obj) static const Property mos6522_properties[] = { DEFINE_PROP_UINT64("frequency", MOS6522State, frequency, 0), - DEFINE_PROP_END_OF_LIST() }; static void mos6522_class_init(ObjectClass *oc, void *data) diff --git a/hw/misc/mps2-fpgaio.c b/hw/misc/mps2-fpgaio.c index 2e8d1c721c..d07568248d 100644 --- a/hw/misc/mps2-fpgaio.c +++ b/hw/misc/mps2-fpgaio.c @@ -326,7 +326,6 @@ static const Property mps2_fpgaio_properties[] = { DEFINE_PROP_UINT32("num-leds", MPS2FPGAIO, num_leds, 2), DEFINE_PROP_BOOL("has-switches", MPS2FPGAIO, has_switches, false), DEFINE_PROP_BOOL("has-dbgctrl", MPS2FPGAIO, has_dbgctrl, false), - DEFINE_PROP_END_OF_LIST(), }; static void mps2_fpgaio_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/mps2-scc.c b/hw/misc/mps2-scc.c index f378b75571..5f8d6bca43 100644 --- a/hw/misc/mps2-scc.c +++ b/hw/misc/mps2-scc.c @@ -472,7 +472,6 @@ static const Property mps2_scc_properties[] = { */ DEFINE_PROP_ARRAY("oscclk", MPS2SCC, num_oscclk, oscclk_reset, qdev_prop_uint32, uint32_t), - DEFINE_PROP_END_OF_LIST(), }; static void mps2_scc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/msf2-sysreg.c b/hw/misc/msf2-sysreg.c index 0d7a713c76..20009adbd9 100644 --- a/hw/misc/msf2-sysreg.c +++ b/hw/misc/msf2-sysreg.c @@ -122,7 +122,6 @@ static const Property msf2_sysreg_properties[] = { /* default divisors in Libero GUI */ DEFINE_PROP_UINT8("apb0divisor", MSF2SysregState, apb0div, 2), DEFINE_PROP_UINT8("apb1divisor", MSF2SysregState, apb1div, 2), - DEFINE_PROP_END_OF_LIST(), }; static void msf2_sysreg_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/npcm7xx_gcr.c b/hw/misc/npcm7xx_gcr.c index 17aeaf22cb..07464a4dc9 100644 --- a/hw/misc/npcm7xx_gcr.c +++ b/hw/misc/npcm7xx_gcr.c @@ -232,7 +232,6 @@ static const VMStateDescription vmstate_npcm7xx_gcr = { static const Property npcm7xx_gcr_properties[] = { DEFINE_PROP_UINT32("disabled-modules", NPCM7xxGCRState, reset_mdlr, 0), DEFINE_PROP_UINT32("power-on-straps", NPCM7xxGCRState, reset_pwron, 0), - DEFINE_PROP_END_OF_LIST(), }; static void npcm7xx_gcr_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/nrf51_rng.c b/hw/misc/nrf51_rng.c index 2b550a6bca..1e67acdf23 100644 --- a/hw/misc/nrf51_rng.c +++ b/hw/misc/nrf51_rng.c @@ -224,7 +224,6 @@ static const Property nrf51_rng_properties[] = { period_unfiltered_us, 167), DEFINE_PROP_UINT16("period_filtered_us", NRF51RNGState, period_filtered_us, 660), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_rng = { diff --git a/hw/misc/pci-testdev.c b/hw/misc/pci-testdev.c index 6268f5c048..f6718a7c37 100644 --- a/hw/misc/pci-testdev.c +++ b/hw/misc/pci-testdev.c @@ -321,7 +321,6 @@ static void qdev_pci_testdev_reset(DeviceState *dev) static const Property pci_testdev_properties[] = { DEFINE_PROP_SIZE("membar", PCITestDevState, membar_size, 0), - DEFINE_PROP_END_OF_LIST(), }; static void pci_testdev_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c index 89ccd8b575..c3713dc5c4 100644 --- a/hw/misc/pvpanic-isa.c +++ b/hw/misc/pvpanic-isa.c @@ -102,7 +102,6 @@ static const Property pvpanic_isa_properties[] = { DEFINE_PROP_UINT16(PVPANIC_IOPORT_PROP, PVPanicISAState, ioport, 0x505), DEFINE_PROP_UINT8("events", PVPanicISAState, pvpanic.events, PVPANIC_EVENTS), - DEFINE_PROP_END_OF_LIST(), }; static void pvpanic_isa_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c index 590b9d39ff..e5f0788ec0 100644 --- a/hw/misc/pvpanic-pci.c +++ b/hw/misc/pvpanic-pci.c @@ -56,7 +56,6 @@ static void pvpanic_pci_realizefn(PCIDevice *dev, Error **errp) static const Property pvpanic_pci_properties[] = { DEFINE_PROP_UINT8("events", PVPanicPCIState, pvpanic.events, PVPANIC_EVENTS), - DEFINE_PROP_END_OF_LIST(), }; static void pvpanic_pci_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/sifive_e_aon.c b/hw/misc/sifive_e_aon.c index b3595d0460..17a522ccf9 100644 --- a/hw/misc/sifive_e_aon.c +++ b/hw/misc/sifive_e_aon.c @@ -292,7 +292,6 @@ static void sifive_e_aon_init(Object *obj) static const Property sifive_e_aon_properties[] = { DEFINE_PROP_UINT64("wdogclk-frequency", SiFiveEAONState, wdogclk_freq, SIFIVE_E_LFCLK_DEFAULT_FREQ), - DEFINE_PROP_END_OF_LIST(), }; static void sifive_e_aon_class_init(ObjectClass *oc, void *data) diff --git a/hw/misc/sifive_u_otp.c b/hw/misc/sifive_u_otp.c index 2ac41f0e78..d6df867fbd 100644 --- a/hw/misc/sifive_u_otp.c +++ b/hw/misc/sifive_u_otp.c @@ -197,7 +197,6 @@ static const MemoryRegionOps sifive_u_otp_ops = { static const Property sifive_u_otp_properties[] = { DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0), DEFINE_PROP_DRIVE("drive", SiFiveUOTPState, blk), - DEFINE_PROP_END_OF_LIST(), }; static void sifive_u_otp_realize(DeviceState *dev, Error **errp) diff --git a/hw/misc/stm32l4x5_rcc.c b/hw/misc/stm32l4x5_rcc.c index b61241d195..fd8466dff3 100644 --- a/hw/misc/stm32l4x5_rcc.c +++ b/hw/misc/stm32l4x5_rcc.c @@ -1433,7 +1433,6 @@ static const Property stm32l4x5_rcc_properties[] = { sai1_extclk_frequency, 0), DEFINE_PROP_UINT64("sai2_extclk_frequency", Stm32l4x5RccState, sai2_extclk_frequency, 0), - DEFINE_PROP_END_OF_LIST(), }; static void stm32l4x5_rcc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/tz-mpc.c b/hw/misc/tz-mpc.c index b06eb9f119..6d827d21dc 100644 --- a/hw/misc/tz-mpc.c +++ b/hw/misc/tz-mpc.c @@ -590,7 +590,6 @@ static const VMStateDescription tz_mpc_vmstate = { static const Property tz_mpc_properties[] = { DEFINE_PROP_LINK("downstream", TZMPC, downstream, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void tz_mpc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/tz-msc.c b/hw/misc/tz-msc.c index 96413a502d..505df4e190 100644 --- a/hw/misc/tz-msc.c +++ b/hw/misc/tz-msc.c @@ -283,7 +283,6 @@ static const Property tz_msc_properties[] = { TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_LINK("idau", TZMSC, idau, TYPE_IDAU_INTERFACE, IDAUInterface *), - DEFINE_PROP_END_OF_LIST(), }; static void tz_msc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/tz-ppc.c b/hw/misc/tz-ppc.c index 1943d8d165..1daa54c5e6 100644 --- a/hw/misc/tz-ppc.c +++ b/hw/misc/tz-ppc.c @@ -323,7 +323,6 @@ static const Property tz_ppc_properties[] = { DEFINE_PORT(13), DEFINE_PORT(14), DEFINE_PORT(15), - DEFINE_PROP_END_OF_LIST(), }; static void tz_ppc_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/unimp.c b/hw/misc/unimp.c index 62e1153627..257282a3a9 100644 --- a/hw/misc/unimp.c +++ b/hw/misc/unimp.c @@ -73,7 +73,6 @@ static void unimp_realize(DeviceState *dev, Error **errp) static const Property unimp_properties[] = { DEFINE_PROP_UINT64("size", UnimplementedDeviceState, size, 0), DEFINE_PROP_STRING("name", UnimplementedDeviceState, name), - DEFINE_PROP_END_OF_LIST(), }; static void unimp_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/xlnx-versal-cframe-reg.c b/hw/misc/xlnx-versal-cframe-reg.c index 8281a9baff..8db0f7e658 100644 --- a/hw/misc/xlnx-versal-cframe-reg.c +++ b/hw/misc/xlnx-versal-cframe-reg.c @@ -737,7 +737,6 @@ static const Property cframe_regs_props[] = { cfg.blktype_num_frames[5], 0), DEFINE_PROP_UINT32("blktype6-frames", XlnxVersalCFrameReg, cfg.blktype_num_frames[6], 0), - DEFINE_PROP_END_OF_LIST(), }; static void cframe_bcast_reg_init(Object *obj) @@ -802,7 +801,6 @@ static const Property cframe_bcast_regs_props[] = { TYPE_XLNX_CFI_IF, XlnxCfiIf *), DEFINE_PROP_LINK("cframe14", XlnxVersalCFrameBcastReg, cfg.cframe[14], TYPE_XLNX_CFI_IF, XlnxCfiIf *), - DEFINE_PROP_END_OF_LIST(), }; static void cframe_reg_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/xlnx-versal-cfu.c b/hw/misc/xlnx-versal-cfu.c index 7cfdabdb8e..26d06e2557 100644 --- a/hw/misc/xlnx-versal-cfu.c +++ b/hw/misc/xlnx-versal-cfu.c @@ -457,13 +457,11 @@ static const Property cfu_props[] = { TYPE_XLNX_CFI_IF, XlnxCfiIf *), DEFINE_PROP_LINK("cframe14", XlnxVersalCFUAPB, cfg.cframe[14], TYPE_XLNX_CFI_IF, XlnxCfiIf *), - DEFINE_PROP_END_OF_LIST(), }; static const Property cfu_sfr_props[] = { DEFINE_PROP_LINK("cfu", XlnxVersalCFUSFR, cfg.cfu, TYPE_XLNX_VERSAL_CFU_APB, XlnxVersalCFUAPB *), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_cfu_apb = { diff --git a/hw/misc/xlnx-versal-trng.c b/hw/misc/xlnx-versal-trng.c index 2f6af4f680..dbd9b58a4e 100644 --- a/hw/misc/xlnx-versal-trng.c +++ b/hw/misc/xlnx-versal-trng.c @@ -641,7 +641,7 @@ static void trng_prop_fault_event_set(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint32_t *events = object_field_prop_ptr(obj, prop); if (!visit_type_uint32(v, name, events, errp)) { @@ -666,8 +666,6 @@ static const Property trng_props[] = { DEFINE_PROP_UINT32("hw-version", XlnxVersalTRng, hw_version, 0x0200), DEFINE_PROP("fips-fault-events", XlnxVersalTRng, forced_faults, trng_prop_fault_events, uint32_t), - - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_trng = { diff --git a/hw/misc/xlnx-versal-xramc.c b/hw/misc/xlnx-versal-xramc.c index a06b9fbc05..d1e76be027 100644 --- a/hw/misc/xlnx-versal-xramc.c +++ b/hw/misc/xlnx-versal-xramc.c @@ -220,7 +220,6 @@ static const VMStateDescription vmstate_xram_ctrl = { static const Property xram_ctrl_properties[] = { DEFINE_PROP_UINT64("size", XlnxXramCtrl, cfg.size, 1 * MiB), - DEFINE_PROP_END_OF_LIST(), }; static void xram_ctrl_class_init(ObjectClass *klass, void *data) diff --git a/hw/misc/zynq_slcr.c b/hw/misc/zynq_slcr.c index d01ba87e11..a766bab182 100644 --- a/hw/misc/zynq_slcr.c +++ b/hw/misc/zynq_slcr.c @@ -625,7 +625,6 @@ static const VMStateDescription vmstate_zynq_slcr = { static const Property zynq_slcr_props[] = { DEFINE_PROP_UINT8("boot-mode", ZynqSLCRState, boot_mode, 1), - DEFINE_PROP_END_OF_LIST(), }; static void zynq_slcr_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/allwinner-sun8i-emac.c b/hw/net/allwinner-sun8i-emac.c index 8cbcceca46..ff44554e95 100644 --- a/hw/net/allwinner-sun8i-emac.c +++ b/hw/net/allwinner-sun8i-emac.c @@ -834,7 +834,6 @@ static const Property allwinner_sun8i_emac_properties[] = { DEFINE_PROP_UINT8("phy-addr", AwSun8iEmacState, mii_phy_addr, 0), DEFINE_PROP_LINK("dma-memory", AwSun8iEmacState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static int allwinner_sun8i_emac_post_load(void *opaque, int version_id) diff --git a/hw/net/allwinner_emac.c b/hw/net/allwinner_emac.c index 39c10426cf..3eb9e09dc5 100644 --- a/hw/net/allwinner_emac.c +++ b/hw/net/allwinner_emac.c @@ -465,7 +465,6 @@ static void aw_emac_realize(DeviceState *dev, Error **errp) static const Property aw_emac_properties[] = { DEFINE_NIC_PROPERTIES(AwEmacState, conf), DEFINE_PROP_UINT8("phy-addr", AwEmacState, phy_addr, 0), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_mii = { diff --git a/hw/net/cadence_gem.c b/hw/net/cadence_gem.c index 1c9681cabc..f744054a6d 100644 --- a/hw/net/cadence_gem.c +++ b/hw/net/cadence_gem.c @@ -1799,7 +1799,6 @@ static const Property gem_properties[] = { jumbo_max_len, 10240), DEFINE_PROP_LINK("dma", CadenceGEMState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void gem_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/can/xlnx-versal-canfd.c b/hw/net/can/xlnx-versal-canfd.c index 97fa46c4b3..dc242e9215 100644 --- a/hw/net/can/xlnx-versal-canfd.c +++ b/hw/net/can/xlnx-versal-canfd.c @@ -2052,7 +2052,6 @@ static const Property canfd_core_properties[] = { CANFD_DEFAULT_CLOCK), DEFINE_PROP_LINK("canfdbus", XlnxVersalCANFDState, canfdbus, TYPE_CAN_BUS, CanBusState *), - DEFINE_PROP_END_OF_LIST(), }; static void canfd_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index 61c104c18b..9fbdeea368 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -1174,7 +1174,6 @@ static const Property xlnx_zynqmp_can_properties[] = { CAN_DEFAULT_CLOCK), DEFINE_PROP_LINK("canbus", XlnxZynqMPCANState, canbus, TYPE_CAN_BUS, CanBusState *), - DEFINE_PROP_END_OF_LIST(), }; static void xlnx_zynqmp_can_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/dp8393x.c b/hw/net/dp8393x.c index e3ca11991b..c80ddb12e3 100644 --- a/hw/net/dp8393x.c +++ b/hw/net/dp8393x.c @@ -937,7 +937,6 @@ static const Property dp8393x_properties[] = { TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT8("it_shift", dp8393xState, it_shift, 0), DEFINE_PROP_BOOL("big_endian", dp8393xState, big_endian, false), - DEFINE_PROP_END_OF_LIST(), }; static void dp8393x_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/e1000.c b/hw/net/e1000.c index 9fc71fd1c7..3d0b227703 100644 --- a/hw/net/e1000.c +++ b/hw/net/e1000.c @@ -1685,7 +1685,6 @@ static const Property e1000_properties[] = { compat_flags, E1000_FLAG_TSO_BIT, true), DEFINE_PROP_BIT("init-vet", E1000State, compat_flags, E1000_FLAG_VET_BIT, true), - DEFINE_PROP_END_OF_LIST(), }; typedef struct E1000Info { diff --git a/hw/net/e1000e.c b/hw/net/e1000e.c index 8c7a2cddfc..f637853073 100644 --- a/hw/net/e1000e.c +++ b/hw/net/e1000e.c @@ -672,7 +672,6 @@ static const Property e1000e_properties[] = { e1000e_prop_subsys, uint16_t), DEFINE_PROP_BOOL("init-vet", E1000EState, init_vet, true), DEFINE_PROP_BOOL("migrate-timadj", E1000EState, timadj, true), - DEFINE_PROP_END_OF_LIST(), }; static void e1000e_class_init(ObjectClass *class, void *data) diff --git a/hw/net/eepro100.c b/hw/net/eepro100.c index 50c287e3bb..6d853229ae 100644 --- a/hw/net/eepro100.c +++ b/hw/net/eepro100.c @@ -2060,7 +2060,6 @@ static E100PCIDeviceInfo *eepro100_get_class(EEPRO100State *s) static const Property e100_properties[] = { DEFINE_NIC_PROPERTIES(EEPRO100State, conf), - DEFINE_PROP_END_OF_LIST(), }; static void eepro100_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/fsl_etsec/etsec.c b/hw/net/fsl_etsec/etsec.c index 764be2c6a2..781b900395 100644 --- a/hw/net/fsl_etsec/etsec.c +++ b/hw/net/fsl_etsec/etsec.c @@ -416,7 +416,6 @@ static void etsec_instance_init(Object *obj) static const Property etsec_properties[] = { DEFINE_NIC_PROPERTIES(eTSEC, conf), - DEFINE_PROP_END_OF_LIST(), }; static void etsec_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/ftgmac100.c b/hw/net/ftgmac100.c index d3f84b2205..1f524d7a01 100644 --- a/hw/net/ftgmac100.c +++ b/hw/net/ftgmac100.c @@ -1258,7 +1258,6 @@ static const Property ftgmac100_properties[] = { DEFINE_PROP_BOOL("aspeed", FTGMAC100State, aspeed, false), DEFINE_NIC_PROPERTIES(FTGMAC100State, conf), DEFINE_PROP_BOOL("dma64", FTGMAC100State, dma64, false), - DEFINE_PROP_END_OF_LIST(), }; static void ftgmac100_class_init(ObjectClass *klass, void *data) @@ -1418,7 +1417,6 @@ static const VMStateDescription vmstate_aspeed_mii = { static const Property aspeed_mii_properties[] = { DEFINE_PROP_LINK("nic", AspeedMiiState, nic, TYPE_FTGMAC100, FTGMAC100State *), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_mii_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/igb.c b/hw/net/igb.c index bea4d446bf..4d93ce629f 100644 --- a/hw/net/igb.c +++ b/hw/net/igb.c @@ -594,7 +594,6 @@ static const VMStateDescription igb_vmstate = { static const Property igb_properties[] = { DEFINE_NIC_PROPERTIES(IGBState, conf), DEFINE_PROP_BOOL("x-pcie-flr-init", IGBState, has_flr, true), - DEFINE_PROP_END_OF_LIST(), }; static void igb_class_init(ObjectClass *class, void *data) diff --git a/hw/net/imx_fec.c b/hw/net/imx_fec.c index eb405f2d46..0f0afda58a 100644 --- a/hw/net/imx_fec.c +++ b/hw/net/imx_fec.c @@ -1229,7 +1229,6 @@ static const Property imx_eth_properties[] = { DEFINE_PROP_BOOL("phy-connected", IMXFECState, phy_connected, true), DEFINE_PROP_LINK("phy-consumer", IMXFECState, phy_consumer, TYPE_IMX_FEC, IMXFECState *), - DEFINE_PROP_END_OF_LIST(), }; static void imx_eth_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/lan9118.c b/hw/net/lan9118.c index 237e9b97d5..afee68c7db 100644 --- a/hw/net/lan9118.c +++ b/hw/net/lan9118.c @@ -1307,7 +1307,6 @@ static void lan9118_realize(DeviceState *dev, Error **errp) static const Property lan9118_properties[] = { DEFINE_NIC_PROPERTIES(lan9118_state, conf), DEFINE_PROP_UINT32("mode_16bit", lan9118_state, mode_16bit, 0), - DEFINE_PROP_END_OF_LIST(), }; static void lan9118_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/lance.c b/hw/net/lance.c index a5d72d4fe4..15492382f9 100644 --- a/hw/net/lance.c +++ b/hw/net/lance.c @@ -141,7 +141,6 @@ static const Property lance_properties[] = { DEFINE_PROP_LINK("dma", SysBusPCNetState, state.dma_opaque, TYPE_DEVICE, DeviceState *), DEFINE_NIC_PROPERTIES(SysBusPCNetState, state.conf), - DEFINE_PROP_END_OF_LIST(), }; static void lance_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/lasi_i82596.c b/hw/net/lasi_i82596.c index e5076d55e1..cad01f5351 100644 --- a/hw/net/lasi_i82596.c +++ b/hw/net/lasi_i82596.c @@ -160,7 +160,6 @@ static void lasi_82596_instance_init(Object *obj) static const Property lasi_82596_properties[] = { DEFINE_NIC_PROPERTIES(SysBusI82596State, state.conf), - DEFINE_PROP_END_OF_LIST(), }; static void lasi_82596_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/mcf_fec.c b/hw/net/mcf_fec.c index 55bad4c069..d5572a81d3 100644 --- a/hw/net/mcf_fec.c +++ b/hw/net/mcf_fec.c @@ -662,7 +662,6 @@ static void mcf_fec_instance_init(Object *obj) static const Property mcf_fec_properties[] = { DEFINE_NIC_PROPERTIES(mcf_fec_state, conf), - DEFINE_PROP_END_OF_LIST(), }; static void mcf_fec_class_init(ObjectClass *oc, void *data) diff --git a/hw/net/mipsnet.c b/hw/net/mipsnet.c index c9ef1beb7b..8852b6f3a1 100644 --- a/hw/net/mipsnet.c +++ b/hw/net/mipsnet.c @@ -268,7 +268,6 @@ static void mipsnet_sysbus_reset(DeviceState *dev) static const Property mipsnet_properties[] = { DEFINE_NIC_PROPERTIES(MIPSnetState, conf), - DEFINE_PROP_END_OF_LIST(), }; static void mipsnet_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c index 8d9015f962..80f75f19dd 100644 --- a/hw/net/msf2-emac.c +++ b/hw/net/msf2-emac.c @@ -550,7 +550,6 @@ static const Property msf2_emac_properties[] = { DEFINE_PROP_LINK("ahb-bus", MSF2EmacState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_NIC_PROPERTIES(MSF2EmacState, conf), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_msf2_emac = { diff --git a/hw/net/mv88w8618_eth.c b/hw/net/mv88w8618_eth.c index b8abffdfa2..5a9d14bef6 100644 --- a/hw/net/mv88w8618_eth.c +++ b/hw/net/mv88w8618_eth.c @@ -375,7 +375,6 @@ static const Property mv88w8618_eth_properties[] = { DEFINE_NIC_PROPERTIES(mv88w8618_eth_state, conf), DEFINE_PROP_LINK("dma-memory", mv88w8618_eth_state, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void mv88w8618_eth_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/ne2000-isa.c b/hw/net/ne2000-isa.c index 98d5b93a3f..20973651f3 100644 --- a/hw/net/ne2000-isa.c +++ b/hw/net/ne2000-isa.c @@ -83,7 +83,6 @@ static const Property ne2000_isa_properties[] = { DEFINE_PROP_UINT32("iobase", ISANE2000State, iobase, 0x300), DEFINE_PROP_UINT32("irq", ISANE2000State, isairq, 9), DEFINE_NIC_PROPERTIES(ISANE2000State, ne2000.c), - DEFINE_PROP_END_OF_LIST(), }; static void isa_ne2000_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/net/ne2000-pci.c b/hw/net/ne2000-pci.c index b2b0eacd06..6840d0e720 100644 --- a/hw/net/ne2000-pci.c +++ b/hw/net/ne2000-pci.c @@ -98,7 +98,6 @@ static void ne2000_instance_init(Object *obj) static const Property ne2000_properties[] = { DEFINE_NIC_PROPERTIES(PCINE2000State, ne2000.c), - DEFINE_PROP_END_OF_LIST(), }; static void ne2000_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/npcm7xx_emc.c b/hw/net/npcm7xx_emc.c index 5173364b64..e06f652629 100644 --- a/hw/net/npcm7xx_emc.c +++ b/hw/net/npcm7xx_emc.c @@ -847,7 +847,6 @@ static const VMStateDescription vmstate_npcm7xx_emc = { static const Property npcm7xx_emc_properties[] = { DEFINE_NIC_PROPERTIES(NPCM7xxEMCState, conf), - DEFINE_PROP_END_OF_LIST(), }; static void npcm7xx_emc_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/npcm_gmac.c b/hw/net/npcm_gmac.c index 98465024f3..e1fb383772 100644 --- a/hw/net/npcm_gmac.c +++ b/hw/net/npcm_gmac.c @@ -914,7 +914,6 @@ static const VMStateDescription vmstate_npcm_gmac = { static const Property npcm_gmac_properties[] = { DEFINE_NIC_PROPERTIES(NPCMGMACState, conf), - DEFINE_PROP_END_OF_LIST(), }; static void npcm_gmac_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/opencores_eth.c b/hw/net/opencores_eth.c index 003b452bc9..54daab7b04 100644 --- a/hw/net/opencores_eth.c +++ b/hw/net/opencores_eth.c @@ -745,7 +745,6 @@ static void qdev_open_eth_reset(DeviceState *dev) static const Property open_eth_properties[] = { DEFINE_NIC_PROPERTIES(OpenEthState, conf), - DEFINE_PROP_END_OF_LIST(), }; static void open_eth_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/pcnet-pci.c b/hw/net/pcnet-pci.c index 1a6f60e4b4..b314ea7d6d 100644 --- a/hw/net/pcnet-pci.c +++ b/hw/net/pcnet-pci.c @@ -254,7 +254,6 @@ static void pcnet_instance_init(Object *obj) static const Property pcnet_properties[] = { DEFINE_NIC_PROPERTIES(PCIPCNetState, state.conf), - DEFINE_PROP_END_OF_LIST(), }; static void pcnet_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/rocker/rocker.c b/hw/net/rocker/rocker.c index efc20396aa..aa5d87fbc5 100644 --- a/hw/net/rocker/rocker.c +++ b/hw/net/rocker/rocker.c @@ -1468,7 +1468,6 @@ static const Property rocker_properties[] = { switch_id, 0), DEFINE_PROP_ARRAY("ports", Rocker, fp_ports, fp_ports_peers, qdev_prop_netdev, NICPeers), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription rocker_vmsd = { diff --git a/hw/net/rtl8139.c b/hw/net/rtl8139.c index e6b13054f9..135ab57160 100644 --- a/hw/net/rtl8139.c +++ b/hw/net/rtl8139.c @@ -3412,7 +3412,6 @@ static void rtl8139_instance_init(Object *obj) static const Property rtl8139_properties[] = { DEFINE_NIC_PROPERTIES(RTL8139State, conf), - DEFINE_PROP_END_OF_LIST(), }; static void rtl8139_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/smc91c111.c b/hw/net/smc91c111.c index a853c30fa2..b18d5c23c3 100644 --- a/hw/net/smc91c111.c +++ b/hw/net/smc91c111.c @@ -790,7 +790,6 @@ static void smc91c111_realize(DeviceState *dev, Error **errp) static const Property smc91c111_properties[] = { DEFINE_NIC_PROPERTIES(smc91c111_state, conf), - DEFINE_PROP_END_OF_LIST(), }; static void smc91c111_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c index 5ce29bd9aa..13fc6565f0 100644 --- a/hw/net/spapr_llan.c +++ b/hw/net/spapr_llan.c @@ -791,7 +791,6 @@ static const Property spapr_vlan_properties[] = { DEFINE_NIC_PROPERTIES(SpaprVioVlan, nicconf), DEFINE_PROP_BIT("use-rx-buffer-pools", SpaprVioVlan, compat_flags, SPAPRVLAN_FLAG_RX_BUF_POOLS_BIT, true), - DEFINE_PROP_END_OF_LIST(), }; static bool spapr_vlan_rx_buffer_pools_needed(void *opaque) diff --git a/hw/net/stellaris_enet.c b/hw/net/stellaris_enet.c index 4af1afa733..a420732d48 100644 --- a/hw/net/stellaris_enet.c +++ b/hw/net/stellaris_enet.c @@ -499,7 +499,6 @@ static void stellaris_enet_realize(DeviceState *dev, Error **errp) static const Property stellaris_enet_properties[] = { DEFINE_NIC_PROPERTIES(stellaris_enet_state, conf), - DEFINE_PROP_END_OF_LIST(), }; static void stellaris_enet_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/sungem.c b/hw/net/sungem.c index af0ff0a3db..12a9a9df46 100644 --- a/hw/net/sungem.c +++ b/hw/net/sungem.c @@ -1427,7 +1427,6 @@ static const Property sungem_properties[] = { * override. */ DEFINE_PROP_UINT32("phy_addr", SunGEMState, phy_addr, 0), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_sungem = { diff --git a/hw/net/sunhme.c b/hw/net/sunhme.c index 9961901bad..fa234d0da1 100644 --- a/hw/net/sunhme.c +++ b/hw/net/sunhme.c @@ -179,7 +179,6 @@ struct SunHMEState { static const Property sunhme_properties[] = { DEFINE_NIC_PROPERTIES(SunHMEState, conf), - DEFINE_PROP_END_OF_LIST(), }; static void sunhme_reset_tx(SunHMEState *s) diff --git a/hw/net/tulip.c b/hw/net/tulip.c index 9adbfa7bb1..a0646bb84c 100644 --- a/hw/net/tulip.c +++ b/hw/net/tulip.c @@ -1009,7 +1009,6 @@ static void tulip_instance_init(Object *obj) static const Property tulip_properties[] = { DEFINE_NIC_PROPERTIES(TULIPState, c), - DEFINE_PROP_END_OF_LIST(), }; static void tulip_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/virtio-net.c b/hw/net/virtio-net.c index 250fe1c0ff..06f096abf6 100644 --- a/hw/net/virtio-net.c +++ b/hw/net/virtio-net.c @@ -4057,7 +4057,6 @@ static const Property virtio_net_properties[] = { VIRTIO_NET_F_GUEST_USO6, true), DEFINE_PROP_BIT64("host_uso", VirtIONet, host_features, VIRTIO_NET_F_HOST_USO, true), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_net_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c index 5ede2a38c9..7abed66469 100644 --- a/hw/net/vmxnet3.c +++ b/hw/net/vmxnet3.c @@ -2477,7 +2477,6 @@ static const Property vmxnet3_properties[] = { VMXNET3_COMPAT_FLAG_OLD_MSI_OFFSETS_BIT, false), DEFINE_PROP_BIT("x-disable-pcie", VMXNET3State, compat_flags, VMXNET3_COMPAT_FLAG_DISABLE_PCIE_BIT, false), - DEFINE_PROP_END_OF_LIST(), }; static void vmxnet3_realize(DeviceState *qdev, Error **errp) diff --git a/hw/net/xen_nic.c b/hw/net/xen_nic.c index 5a5259150a..97ebd9fa30 100644 --- a/hw/net/xen_nic.c +++ b/hw/net/xen_nic.c @@ -558,7 +558,6 @@ static void xen_netdev_unrealize(XenDevice *xendev) static const Property xen_netdev_properties[] = { DEFINE_NIC_PROPERTIES(XenNetDev, conf), DEFINE_PROP_INT32("idx", XenNetDev, dev, -1), - DEFINE_PROP_END_OF_LIST(), }; static void xen_netdev_class_init(ObjectClass *class, void *data) diff --git a/hw/net/xgmac.c b/hw/net/xgmac.c index 6e0f96f485..e3cc4c60eb 100644 --- a/hw/net/xgmac.c +++ b/hw/net/xgmac.c @@ -416,7 +416,6 @@ static void xgmac_enet_realize(DeviceState *dev, Error **errp) static const Property xgmac_properties[] = { DEFINE_NIC_PROPERTIES(XgmacState, conf), - DEFINE_PROP_END_OF_LIST(), }; static void xgmac_enet_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/xilinx_axienet.c b/hw/net/xilinx_axienet.c index 9d0c618e2f..457952af19 100644 --- a/hw/net/xilinx_axienet.c +++ b/hw/net/xilinx_axienet.c @@ -1005,7 +1005,6 @@ static const Property xilinx_enet_properties[] = { tx_data_dev, TYPE_STREAM_SINK, StreamSink *), DEFINE_PROP_LINK("axistream-control-connected", XilinxAXIEnet, tx_control_dev, TYPE_STREAM_SINK, StreamSink *), - DEFINE_PROP_END_OF_LIST(), }; static void xilinx_enet_class_init(ObjectClass *klass, void *data) diff --git a/hw/net/xilinx_ethlite.c b/hw/net/xilinx_ethlite.c index 9413731d20..f3eb2af193 100644 --- a/hw/net/xilinx_ethlite.c +++ b/hw/net/xilinx_ethlite.c @@ -255,7 +255,6 @@ static const Property xilinx_ethlite_properties[] = { DEFINE_PROP_UINT32("tx-ping-pong", struct xlx_ethlite, c_tx_pingpong, 1), DEFINE_PROP_UINT32("rx-ping-pong", struct xlx_ethlite, c_rx_pingpong, 1), DEFINE_NIC_PROPERTIES(struct xlx_ethlite, conf), - DEFINE_PROP_END_OF_LIST(), }; static void xilinx_ethlite_class_init(ObjectClass *klass, void *data) diff --git a/hw/nubus/nubus-bridge.c b/hw/nubus/nubus-bridge.c index 83893e5a46..8fe4362723 100644 --- a/hw/nubus/nubus-bridge.c +++ b/hw/nubus/nubus-bridge.c @@ -26,7 +26,6 @@ static void nubus_bridge_init(Object *obj) static const Property nubus_bridge_properties[] = { DEFINE_PROP_UINT16("slot-available-mask", NubusBridge, bus.slot_available_mask, 0xffff), - DEFINE_PROP_END_OF_LIST() }; static void nubus_bridge_class_init(ObjectClass *klass, void *data) diff --git a/hw/nubus/nubus-device.c b/hw/nubus/nubus-device.c index 7cafc13427..6755c3dc43 100644 --- a/hw/nubus/nubus-device.c +++ b/hw/nubus/nubus-device.c @@ -110,7 +110,6 @@ static void nubus_device_realize(DeviceState *dev, Error **errp) static const Property nubus_device_properties[] = { DEFINE_PROP_INT32("slot", NubusDevice, slot, -1), DEFINE_PROP_STRING("romfile", NubusDevice, romfile), - DEFINE_PROP_END_OF_LIST() }; static void nubus_device_class_init(ObjectClass *oc, void *data) diff --git a/hw/nvme/ctrl.c b/hw/nvme/ctrl.c index fe10c8e076..68903d1d70 100644 --- a/hw/nvme/ctrl.c +++ b/hw/nvme/ctrl.c @@ -8965,7 +8965,6 @@ static const Property nvme_props[] = { DEFINE_PROP_BOOL("atomic.dn", NvmeCtrl, params.atomic_dn, 0), DEFINE_PROP_UINT16("atomic.awun", NvmeCtrl, params.atomic_awun, 0), DEFINE_PROP_UINT16("atomic.awupf", NvmeCtrl, params.atomic_awupf, 0), - DEFINE_PROP_END_OF_LIST(), }; static void nvme_get_smart_warning(Object *obj, Visitor *v, const char *name, diff --git a/hw/nvme/nguid.c b/hw/nvme/nguid.c index 829832bd9f..be63cb75e1 100644 --- a/hw/nvme/nguid.c +++ b/hw/nvme/nguid.c @@ -149,7 +149,7 @@ static void nvme_nguid_stringify(const NvmeNGUID *nguid, char *out) static void get_nguid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; NvmeNGUID *nguid = object_field_prop_ptr(obj, prop); char buffer[NGUID_STR_LEN]; char *p = buffer; @@ -162,7 +162,7 @@ static void get_nguid(Object *obj, Visitor *v, const char *name, void *opaque, static void set_nguid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; NvmeNGUID *nguid = object_field_prop_ptr(obj, prop); char *str; diff --git a/hw/nvme/ns.c b/hw/nvme/ns.c index 76d185d948..410df29591 100644 --- a/hw/nvme/ns.c +++ b/hw/nvme/ns.c @@ -834,7 +834,6 @@ static const Property nvme_ns_props[] = { DEFINE_PROP_BOOL("eui64-default", NvmeNamespace, params.eui64_default, false), DEFINE_PROP_STRING("fdp.ruhs", NvmeNamespace, params.fdp.ruhs), - DEFINE_PROP_END_OF_LIST(), }; static void nvme_ns_class_init(ObjectClass *oc, void *data) diff --git a/hw/nvme/subsys.c b/hw/nvme/subsys.c index 3171c3888c..2ae56f12a5 100644 --- a/hw/nvme/subsys.c +++ b/hw/nvme/subsys.c @@ -223,7 +223,6 @@ static const Property nvme_subsystem_props[] = { NVME_DEFAULT_RU_SIZE), DEFINE_PROP_UINT32("fdp.nrg", NvmeSubsystem, params.fdp.nrg, 1), DEFINE_PROP_UINT16("fdp.nruh", NvmeSubsystem, params.fdp.nruh, 0), - DEFINE_PROP_END_OF_LIST(), }; static void nvme_subsys_class_init(ObjectClass *oc, void *data) diff --git a/hw/nvram/ds1225y.c b/hw/nvram/ds1225y.c index 19bf8d2091..6b2aa8c7d2 100644 --- a/hw/nvram/ds1225y.c +++ b/hw/nvram/ds1225y.c @@ -145,7 +145,6 @@ static void nvram_sysbus_realize(DeviceState *dev, Error **errp) static const Property nvram_sysbus_properties[] = { DEFINE_PROP_UINT32("size", SysBusNvRamState, nvram.chip_size, 0x2000), DEFINE_PROP_STRING("filename", SysBusNvRamState, nvram.filename), - DEFINE_PROP_END_OF_LIST(), }; static void nvram_sysbus_class_init(ObjectClass *klass, void *data) diff --git a/hw/nvram/eeprom_at24c.c b/hw/nvram/eeprom_at24c.c index 32069881f5..a40cc5dd15 100644 --- a/hw/nvram/eeprom_at24c.c +++ b/hw/nvram/eeprom_at24c.c @@ -239,7 +239,6 @@ static const Property at24c_eeprom_props[] = { DEFINE_PROP_UINT8("address-size", EEPROMState, asize, 0), DEFINE_PROP_BOOL("writable", EEPROMState, writable, true), DEFINE_PROP_DRIVE("drive", EEPROMState, blk), - DEFINE_PROP_END_OF_LIST() }; static diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index a2db79bf6f..c5537166d9 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -1084,7 +1084,6 @@ static void fw_cfg_machine_ready(struct Notifier *n, void *data) static const Property fw_cfg_properties[] = { DEFINE_PROP_BOOL("acpi-mr-restore", FWCfgState, acpi_mr_restore, true), - DEFINE_PROP_END_OF_LIST(), }; static void fw_cfg_common_realize(DeviceState *dev, Error **errp) @@ -1278,7 +1277,6 @@ static const Property fw_cfg_io_properties[] = { true), DEFINE_PROP_UINT16("x-file-slots", FWCfgIoState, parent_obj.file_slots, FW_CFG_FILE_SLOTS_DFLT), - DEFINE_PROP_END_OF_LIST(), }; static void fw_cfg_io_realize(DeviceState *dev, Error **errp) @@ -1328,7 +1326,6 @@ static const Property fw_cfg_mem_properties[] = { true), DEFINE_PROP_UINT16("x-file-slots", FWCfgMemState, parent_obj.file_slots, FW_CFG_FILE_SLOTS_DFLT), - DEFINE_PROP_END_OF_LIST(), }; static void fw_cfg_mem_realize(DeviceState *dev, Error **errp) diff --git a/hw/nvram/mac_nvram.c b/hw/nvram/mac_nvram.c index d18575a3ee..0d82e5a128 100644 --- a/hw/nvram/mac_nvram.c +++ b/hw/nvram/mac_nvram.c @@ -138,7 +138,6 @@ static const Property macio_nvram_properties[] = { DEFINE_PROP_UINT32("size", MacIONVRAMState, size, 0), DEFINE_PROP_UINT32("it_shift", MacIONVRAMState, it_shift, 0), DEFINE_PROP_DRIVE("drive", MacIONVRAMState, blk), - DEFINE_PROP_END_OF_LIST() }; static void macio_nvram_class_init(ObjectClass *oc, void *data) diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c index 236049462b..2ed4078858 100644 --- a/hw/nvram/nrf51_nvm.c +++ b/hw/nvram/nrf51_nvm.c @@ -356,7 +356,6 @@ static void nrf51_nvm_reset(DeviceState *dev) static const Property nrf51_nvm_properties[] = { DEFINE_PROP_UINT32("flash-size", NRF51NVMState, flash_size, 0x40000), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_nvm = { diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c index fa884e9bbb..a45827f6aa 100644 --- a/hw/nvram/spapr_nvram.c +++ b/hw/nvram/spapr_nvram.c @@ -255,7 +255,6 @@ static const VMStateDescription vmstate_spapr_nvram = { static const Property spapr_nvram_properties[] = { DEFINE_SPAPR_PROPERTIES(SpaprNvram, sdev), DEFINE_PROP_DRIVE("drive", SpaprNvram, blk), - DEFINE_PROP_END_OF_LIST(), }; static void spapr_nvram_class_init(ObjectClass *klass, void *data) diff --git a/hw/nvram/xlnx-bbram.c b/hw/nvram/xlnx-bbram.c index d5a6930e8c..0e8552ce65 100644 --- a/hw/nvram/xlnx-bbram.c +++ b/hw/nvram/xlnx-bbram.c @@ -523,7 +523,6 @@ static const VMStateDescription vmstate_bbram_ctrl = { static const Property bbram_ctrl_props[] = { DEFINE_PROP("drive", XlnxBBRam, blk, bbram_prop_drive, BlockBackend *), DEFINE_PROP_UINT32("crc-zpads", XlnxBBRam, crc_zpads, 1), - DEFINE_PROP_END_OF_LIST(), }; static void bbram_ctrl_class_init(ObjectClass *klass, void *data) diff --git a/hw/nvram/xlnx-efuse.c b/hw/nvram/xlnx-efuse.c index 7cd3d401ce..e2e8311a48 100644 --- a/hw/nvram/xlnx-efuse.c +++ b/hw/nvram/xlnx-efuse.c @@ -272,7 +272,6 @@ static const Property efuse_properties[] = { DEFINE_PROP_BOOL("init-factory-tbits", XlnxEFuse, init_tbits, true), DEFINE_PROP_ARRAY("read-only", XlnxEFuse, ro_bits_cnt, ro_bits, qdev_prop_uint32, uint32_t), - DEFINE_PROP_END_OF_LIST(), }; static void efuse_class_init(ObjectClass *klass, void *data) diff --git a/hw/nvram/xlnx-versal-efuse-cache.c b/hw/nvram/xlnx-versal-efuse-cache.c index 1aea27afd3..2fb599422c 100644 --- a/hw/nvram/xlnx-versal-efuse-cache.c +++ b/hw/nvram/xlnx-versal-efuse-cache.c @@ -87,8 +87,6 @@ static const Property efuse_cache_props[] = { DEFINE_PROP_LINK("efuse", XlnxVersalEFuseCache, efuse, TYPE_XLNX_EFUSE, XlnxEFuse *), - - DEFINE_PROP_END_OF_LIST(), }; static void efuse_cache_class_init(ObjectClass *klass, void *data) diff --git a/hw/nvram/xlnx-versal-efuse-ctrl.c b/hw/nvram/xlnx-versal-efuse-ctrl.c index 599aa126fb..3246eb3ca6 100644 --- a/hw/nvram/xlnx-versal-efuse-ctrl.c +++ b/hw/nvram/xlnx-versal-efuse-ctrl.c @@ -750,8 +750,6 @@ static const Property efuse_ctrl_props[] = { DEFINE_PROP_ARRAY("pg0-lock", XlnxVersalEFuseCtrl, extra_pg0_lock_n16, extra_pg0_lock_spec, qdev_prop_uint16, uint16_t), - - DEFINE_PROP_END_OF_LIST(), }; static void efuse_ctrl_class_init(ObjectClass *klass, void *data) diff --git a/hw/nvram/xlnx-zynqmp-efuse.c b/hw/nvram/xlnx-zynqmp-efuse.c index af53187905..15024daf4f 100644 --- a/hw/nvram/xlnx-zynqmp-efuse.c +++ b/hw/nvram/xlnx-zynqmp-efuse.c @@ -837,8 +837,6 @@ static const Property zynqmp_efuse_props[] = { DEFINE_PROP_LINK("efuse", XlnxZynqMPEFuse, efuse, TYPE_XLNX_EFUSE, XlnxEFuse *), - - DEFINE_PROP_END_OF_LIST(), }; static void zynqmp_efuse_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-bridge/cxl_downstream.c b/hw/pci-bridge/cxl_downstream.c index cfe50e60e9..e337f1ac50 100644 --- a/hw/pci-bridge/cxl_downstream.c +++ b/hw/pci-bridge/cxl_downstream.c @@ -217,7 +217,6 @@ static const Property cxl_dsp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_16), - DEFINE_PROP_END_OF_LIST() }; static void cxl_dsp_class_init(ObjectClass *oc, void *data) diff --git a/hw/pci-bridge/cxl_root_port.c b/hw/pci-bridge/cxl_root_port.c index 5824ba3c75..c0037f2cfb 100644 --- a/hw/pci-bridge/cxl_root_port.c +++ b/hw/pci-bridge/cxl_root_port.c @@ -211,7 +211,6 @@ static const Property gen_rp_props[] = { speed, PCIE_LINK_SPEED_64), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_END_OF_LIST() }; static void cxl_rp_dvsec_write_config(PCIDevice *dev, uint32_t addr, diff --git a/hw/pci-bridge/cxl_upstream.c b/hw/pci-bridge/cxl_upstream.c index ef94aa3654..28b109c49a 100644 --- a/hw/pci-bridge/cxl_upstream.c +++ b/hw/pci-bridge/cxl_upstream.c @@ -369,7 +369,6 @@ static const Property cxl_upstream_props[] = { speed, PCIE_LINK_SPEED_32), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", CXLUpstreamPort, width, PCIE_LINK_WIDTH_16), - DEFINE_PROP_END_OF_LIST() }; static void cxl_upstream_class_init(ObjectClass *oc, void *data) diff --git a/hw/pci-bridge/gen_pcie_root_port.c b/hw/pci-bridge/gen_pcie_root_port.c index c319ca8263..3c0b41ef1a 100644 --- a/hw/pci-bridge/gen_pcie_root_port.c +++ b/hw/pci-bridge/gen_pcie_root_port.c @@ -145,7 +145,6 @@ static const Property gen_rp_props[] = { speed, PCIE_LINK_SPEED_16), DEFINE_PROP_PCIE_LINK_WIDTH("x-width", PCIESlot, width, PCIE_LINK_WIDTH_32), - DEFINE_PROP_END_OF_LIST() }; static void gen_rp_dev_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-bridge/pci_bridge_dev.c b/hw/pci-bridge/pci_bridge_dev.c index 35a37e056a..0a91a8ae6c 100644 --- a/hw/pci-bridge/pci_bridge_dev.c +++ b/hw/pci-bridge/pci_bridge_dev.c @@ -186,7 +186,6 @@ static const Property pci_bridge_dev_properties[] = { res_reserve.mem_pref_32, -1), DEFINE_PROP_SIZE("pref64-reserve", PCIBridgeDev, res_reserve.mem_pref_64, -1), - DEFINE_PROP_END_OF_LIST(), }; static bool pci_device_shpc_present(void *opaque, int version_id) diff --git a/hw/pci-bridge/pci_expander_bridge.c b/hw/pci-bridge/pci_expander_bridge.c index 7e8f4ae5ea..3396ab4bdd 100644 --- a/hw/pci-bridge/pci_expander_bridge.c +++ b/hw/pci-bridge/pci_expander_bridge.c @@ -425,7 +425,6 @@ static const Property pxb_dev_properties[] = { DEFINE_PROP_UINT8("bus_nr", PXBDev, bus_nr, 0), DEFINE_PROP_UINT16("numa_node", PXBDev, numa_node, NUMA_NODE_UNASSIGNED), DEFINE_PROP_BOOL("bypass_iommu", PXBDev, bypass_iommu, false), - DEFINE_PROP_END_OF_LIST(), }; static void pxb_dev_class_init(ObjectClass *klass, void *data) @@ -509,7 +508,6 @@ static void pxb_cxl_dev_realize(PCIDevice *dev, Error **errp) static const Property pxb_cxl_dev_properties[] = { DEFINE_PROP_BOOL("hdm_for_passthrough", PXBCXLDev, hdm_for_passthrough, false), - DEFINE_PROP_END_OF_LIST(), }; static void pxb_cxl_dev_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-bridge/pcie_pci_bridge.c b/hw/pci-bridge/pcie_pci_bridge.c index 8834ff3dbf..fd4514a595 100644 --- a/hw/pci-bridge/pcie_pci_bridge.c +++ b/hw/pci-bridge/pcie_pci_bridge.c @@ -126,7 +126,6 @@ static void pcie_pci_bridge_write_config(PCIDevice *d, static const Property pcie_pci_bridge_dev_properties[] = { DEFINE_PROP_ON_OFF_AUTO("msi", PCIEPCIBridge, msi, ON_OFF_AUTO_AUTO), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription pcie_pci_bridge_dev_vmstate = { diff --git a/hw/pci-bridge/pcie_root_port.c b/hw/pci-bridge/pcie_root_port.c index a7f87a1bc4..dd40b366bf 100644 --- a/hw/pci-bridge/pcie_root_port.c +++ b/hw/pci-bridge/pcie_root_port.c @@ -152,7 +152,6 @@ static const Property rp_props[] = { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), DEFINE_PROP_BOOL("disable-acs", PCIESlot, disable_acs, false), - DEFINE_PROP_END_OF_LIST() }; static void rp_instance_post_init(Object *obj) diff --git a/hw/pci-bridge/xio3130_downstream.c b/hw/pci-bridge/xio3130_downstream.c index 92e5fb72ec..d4e94f2657 100644 --- a/hw/pci-bridge/xio3130_downstream.c +++ b/hw/pci-bridge/xio3130_downstream.c @@ -137,7 +137,6 @@ static void xio3130_downstream_exitfn(PCIDevice *d) static const Property xio3130_downstream_props[] = { DEFINE_PROP_BIT(COMPAT_PROP_PCP, PCIDevice, cap_present, QEMU_PCIE_SLTCAP_PCP_BITNR, true), - DEFINE_PROP_END_OF_LIST() }; static const VMStateDescription vmstate_xio3130_downstream = { diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index 379095b356..62e9c8acbf 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -461,10 +461,6 @@ static void elroy_pcihost_init(Object *obj) qdev_init_gpio_in(DEVICE(obj), elroy_set_irq, ELROY_IRQS); } -static Property elroy_pcihost_properties[] = { - DEFINE_PROP_END_OF_LIST(), -}; - static const VMStateDescription vmstate_elroy = { .name = "Elroy", .version_id = 1, @@ -490,7 +486,6 @@ static void elroy_pcihost_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); device_class_set_legacy_reset(dc, elroy_reset); - device_class_set_props(dc, elroy_pcihost_properties); dc->vmsd = &vmstate_elroy; dc->user_creatable = false; } diff --git a/hw/pci-host/dino.c b/hw/pci-host/dino.c index ead9893f21..58fdbf7bc9 100644 --- a/hw/pci-host/dino.c +++ b/hw/pci-host/dino.c @@ -495,7 +495,6 @@ static void dino_pcihost_init(Object *obj) static const Property dino_pcihost_properties[] = { DEFINE_PROP_LINK("memory-as", DinoState, memory_as, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void dino_pcihost_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/gpex.c b/hw/pci-host/gpex.c index 8a955ca130..c6aa8e87a2 100644 --- a/hw/pci-host/gpex.c +++ b/hw/pci-host/gpex.c @@ -166,7 +166,6 @@ static const Property gpex_host_properties[] = { gpex_cfg.mmio64.base, 0), DEFINE_PROP_SIZE(PCI_HOST_ABOVE_4G_MMIO_SIZE, GPEXHost, gpex_cfg.mmio64.size, 0), - DEFINE_PROP_END_OF_LIST(), }; static void gpex_host_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/grackle.c b/hw/pci-host/grackle.c index d64de73774..84e5ee8c6e 100644 --- a/hw/pci-host/grackle.c +++ b/hw/pci-host/grackle.c @@ -131,7 +131,6 @@ static char *grackle_ofw_unit_address(const SysBusDevice *dev) static const Property grackle_properties[] = { DEFINE_PROP_UINT32("ofw-addr", GrackleState, ofw_addr, -1), - DEFINE_PROP_END_OF_LIST() }; static void grackle_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/gt64120.c b/hw/pci-host/gt64120.c index 3c73ebe83f..d5c13a89b6 100644 --- a/hw/pci-host/gt64120.c +++ b/hw/pci-host/gt64120.c @@ -1277,7 +1277,6 @@ static const TypeInfo gt64120_pci_info = { static const Property gt64120_properties[] = { DEFINE_PROP_BOOL("cpu-little-endian", GT64120State, cpu_little_endian, false), - DEFINE_PROP_END_OF_LIST(), }; static void gt64120_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/i440fx.c b/hw/pci-host/i440fx.c index 40780fbc52..1e69691c6d 100644 --- a/hw/pci-host/i440fx.c +++ b/hw/pci-host/i440fx.c @@ -362,7 +362,6 @@ static const Property i440fx_props[] = { above_4g_mem_size, 0), DEFINE_PROP_BOOL("x-pci-hole64-fix", I440FXState, pci_hole64_fix, true), DEFINE_PROP_STRING(I440FX_HOST_PROP_PCI_TYPE, I440FXState, pci_type), - DEFINE_PROP_END_OF_LIST(), }; static void i440fx_pcihost_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/mv64361.c b/hw/pci-host/mv64361.c index 2518d5abe6..9c41c155fb 100644 --- a/hw/pci-host/mv64361.c +++ b/hw/pci-host/mv64361.c @@ -100,7 +100,6 @@ static void mv64361_pcihost_realize(DeviceState *dev, Error **errp) static const Property mv64361_pcihost_props[] = { DEFINE_PROP_UINT8("index", MV64361PCIState, index, 0), - DEFINE_PROP_END_OF_LIST() }; static void mv64361_pcihost_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/pnv_phb.c b/hw/pci-host/pnv_phb.c index 350c04e69d..6c1e76fbbb 100644 --- a/hw/pci-host/pnv_phb.c +++ b/hw/pci-host/pnv_phb.c @@ -192,8 +192,6 @@ static const Property pnv_phb_properties[] = { DEFINE_PROP_LINK("pec", PnvPHB, pec, TYPE_PNV_PHB4_PEC, PnvPhb4PecState *), - - DEFINE_PROP_END_OF_LIST(), }; static void pnv_phb_class_init(ObjectClass *klass, void *data) @@ -304,8 +302,6 @@ static void pnv_phb_root_port_realize(DeviceState *dev, Error **errp) static const Property pnv_phb_root_port_properties[] = { DEFINE_PROP_UINT32("version", PnvPHBRootPort, version, 0), - - DEFINE_PROP_END_OF_LIST(), }; static void pnv_phb_root_port_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/pnv_phb3.c b/hw/pci-host/pnv_phb3.c index dbd26a68a8..82884e1e92 100644 --- a/hw/pci-host/pnv_phb3.c +++ b/hw/pci-host/pnv_phb3.c @@ -1095,7 +1095,6 @@ static const Property pnv_phb3_properties[] = { DEFINE_PROP_UINT32("chip-id", PnvPHB3, chip_id, 0), DEFINE_PROP_LINK("chip", PnvPHB3, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_LINK("phb-base", PnvPHB3, phb_base, TYPE_PNV_PHB, PnvPHB *), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_phb3_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/pnv_phb4.c b/hw/pci-host/pnv_phb4.c index 482fe25803..178c73f519 100644 --- a/hw/pci-host/pnv_phb4.c +++ b/hw/pci-host/pnv_phb4.c @@ -1694,7 +1694,6 @@ static const Property pnv_phb4_properties[] = { DEFINE_PROP_LINK("pec", PnvPHB4, pec, TYPE_PNV_PHB4_PEC, PnvPhb4PecState *), DEFINE_PROP_LINK("phb-base", PnvPHB4, phb_base, TYPE_PNV_PHB, PnvPHB *), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_phb4_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/pnv_phb4_pec.c b/hw/pci-host/pnv_phb4_pec.c index 28c35b40c8..a156839caf 100644 --- a/hw/pci-host/pnv_phb4_pec.c +++ b/hw/pci-host/pnv_phb4_pec.c @@ -288,7 +288,6 @@ static const Property pnv_pec_properties[] = { DEFINE_PROP_UINT32("chip-id", PnvPhb4PecState, chip_id, 0), DEFINE_PROP_LINK("chip", PnvPhb4PecState, chip, TYPE_PNV_CHIP, PnvChip *), - DEFINE_PROP_END_OF_LIST(), }; static uint32_t pnv_pec_xscom_pci_base(PnvPhb4PecState *pec) diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 67b22537c5..9b905d1971 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -510,7 +510,6 @@ static void e500_host_bridge_class_init(ObjectClass *klass, void *data) static const Property pcihost_properties[] = { DEFINE_PROP_UINT32("first_slot", PPCE500PCIState, first_slot, 0x11), DEFINE_PROP_UINT32("first_pin_irq", PPCE500PCIState, first_pin_irq, 0x1), - DEFINE_PROP_END_OF_LIST(), }; static void e500_pcihost_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/q35.c b/hw/pci-host/q35.c index af0b77ea1e..06be3d77cb 100644 --- a/hw/pci-host/q35.c +++ b/hw/pci-host/q35.c @@ -182,7 +182,6 @@ static const Property q35_host_props[] = { DEFINE_PROP_BOOL(PCI_HOST_PROP_SMM_RANGES, Q35PCIHost, mch.has_smm_ranges, true), DEFINE_PROP_BOOL("x-pci-hole64-fix", Q35PCIHost, pci_hole64_fix, true), - DEFINE_PROP_END_OF_LIST(), }; static void q35_host_class_init(ObjectClass *klass, void *data) @@ -666,7 +665,6 @@ static const Property mch_props[] = { DEFINE_PROP_UINT16("extended-tseg-mbytes", MCHPCIState, ext_tseg_mbytes, 16), DEFINE_PROP_BOOL("smbase-smram", MCHPCIState, has_smram_at_smbase, true), - DEFINE_PROP_END_OF_LIST(), }; static void mch_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/raven.c b/hw/pci-host/raven.c index b0a4a669f5..918a3237a9 100644 --- a/hw/pci-host/raven.c +++ b/hw/pci-host/raven.c @@ -429,7 +429,6 @@ static const Property raven_pcihost_properties[] = { /* Temporary workaround until legacy prep machine is removed */ DEFINE_PROP_BOOL("is-legacy-prep", PREPPCIState, is_legacy_prep, false), - DEFINE_PROP_END_OF_LIST() }; static void raven_pcihost_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index d3e6943136..be6641de15 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -495,7 +495,6 @@ static char *sabre_ofw_unit_address(const SysBusDevice *dev) static const Property sabre_properties[] = { DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), - DEFINE_PROP_END_OF_LIST(), }; static void sabre_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/uninorth.c b/hw/pci-host/uninorth.c index bd670cfa9d..37e2461bbb 100644 --- a/hw/pci-host/uninorth.c +++ b/hw/pci-host/uninorth.c @@ -425,7 +425,6 @@ static const TypeInfo unin_internal_pci_host_info = { static const Property pci_unin_main_pci_host_props[] = { DEFINE_PROP_UINT32("ofw-addr", UNINHostState, ofw_addr, -1), - DEFINE_PROP_END_OF_LIST() }; static void pci_unin_main_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/versatile.c b/hw/pci-host/versatile.c index 5d59640691..c3fbf4cbf9 100644 --- a/hw/pci-host/versatile.c +++ b/hw/pci-host/versatile.c @@ -501,7 +501,6 @@ static const TypeInfo versatile_pci_host_info = { static const Property pci_vpb_properties[] = { DEFINE_PROP_UINT8("broken-irq-mapping", PCIVPBState, irq_mapping_prop, PCI_VPB_IRQMAP_ASSUME_OK), - DEFINE_PROP_END_OF_LIST() }; static void pci_vpb_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci-host/xilinx-pcie.c b/hw/pci-host/xilinx-pcie.c index 848403970b..18688485f4 100644 --- a/hw/pci-host/xilinx-pcie.c +++ b/hw/pci-host/xilinx-pcie.c @@ -163,7 +163,6 @@ static const Property xilinx_pcie_host_props[] = { DEFINE_PROP_SIZE("mmio_base", XilinxPCIEHost, mmio_base, 0), DEFINE_PROP_SIZE("mmio_size", XilinxPCIEHost, mmio_size, 1 * MiB), DEFINE_PROP_BOOL("link_up", XilinxPCIEHost, link_up, true), - DEFINE_PROP_END_OF_LIST(), }; static void xilinx_pcie_host_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci/pci.c b/hw/pci/pci.c index c7f898cbf6..b6c630c323 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -104,7 +104,6 @@ static const Property pci_props[] = { DEFINE_PROP_BIT("x-pcie-ext-tag", PCIDevice, cap_present, QEMU_PCIE_EXT_TAG_BITNR, true), { .name = "busnr", .info = &prop_pci_busnr }, - DEFINE_PROP_END_OF_LIST() }; static const VMStateDescription vmstate_pcibus = { diff --git a/hw/pci/pci_bridge.c b/hw/pci/pci_bridge.c index dd4fd3674f..aee4dd7d1f 100644 --- a/hw/pci/pci_bridge.c +++ b/hw/pci/pci_bridge.c @@ -480,7 +480,6 @@ int pci_bridge_qemu_reserve_cap_init(PCIDevice *dev, int cap_offset, static const Property pci_bridge_properties[] = { DEFINE_PROP_BOOL("x-pci-express-writeable-slt-bug", PCIBridge, pcie_writeable_slt_bug, false), - DEFINE_PROP_END_OF_LIST(), }; static void pci_bridge_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci/pci_host.c b/hw/pci/pci_host.c index 321e7be709..4510890dfc 100644 --- a/hw/pci/pci_host.c +++ b/hw/pci/pci_host.c @@ -244,7 +244,6 @@ static const Property pci_host_properties_common[] = { DEFINE_PROP_BOOL("x-config-reg-migration-enabled", PCIHostState, mig_enabled, true), DEFINE_PROP_BOOL(PCI_HOST_BYPASS_IOMMU, PCIHostState, bypass_iommu, false), - DEFINE_PROP_END_OF_LIST(), }; static void pci_host_class_init(ObjectClass *klass, void *data) diff --git a/hw/pci/pcie_port.c b/hw/pci/pcie_port.c index bac2822e98..c73db30e98 100644 --- a/hw/pci/pcie_port.c +++ b/hw/pci/pcie_port.c @@ -116,7 +116,6 @@ static const Property pcie_port_props[] = { DEFINE_PROP_UINT16("aer_log_max", PCIEPort, parent_obj.parent_obj.exp.aer_log.log_max, PCIE_AER_LOG_MAX_DEFAULT), - DEFINE_PROP_END_OF_LIST() }; static void pcie_port_class_init(ObjectClass *oc, void *data) @@ -210,7 +209,6 @@ static const Property pcie_slot_props[] = { DEFINE_PROP_BOOL("hotplug", PCIESlot, hotplug, true), DEFINE_PROP_BOOL("x-do-not-expose-native-hotplug-cap", PCIESlot, hide_native_hotplug_cap, false), - DEFINE_PROP_END_OF_LIST() }; static void pcie_slot_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index d2be6502d2..11fd477b71 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -2431,7 +2431,6 @@ static const Property pnv_chip_properties[] = { DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), DEFINE_PROP_BOOL("big-core", PnvChip, big_core, false), DEFINE_PROP_BOOL("lpar-per-core", PnvChip, lpar_per_core, false), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_chip_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_adu.c b/hw/ppc/pnv_adu.c index 646736f7e9..d09a167466 100644 --- a/hw/ppc/pnv_adu.c +++ b/hw/ppc/pnv_adu.c @@ -187,7 +187,6 @@ static void pnv_adu_realize(DeviceState *dev, Error **errp) static const Property pnv_adu_properties[] = { DEFINE_PROP_LINK("lpc", PnvADU, lpc, TYPE_PNV_LPC, PnvLpcController *), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_adu_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_chiptod.c b/hw/ppc/pnv_chiptod.c index 9f2eb994ca..c8987ae67a 100644 --- a/hw/ppc/pnv_chiptod.c +++ b/hw/ppc/pnv_chiptod.c @@ -454,7 +454,6 @@ static const Property pnv_chiptod_properties[] = { DEFINE_PROP_BOOL("primary", PnvChipTOD, primary, false), DEFINE_PROP_BOOL("secondary", PnvChipTOD, secondary, false), DEFINE_PROP_LINK("chip", PnvChipTOD , chip, TYPE_PNV_CHIP, PnvChip *), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_chiptod_power9_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_core.c b/hw/ppc/pnv_core.c index 3b7cf38f5f..99d9644ee3 100644 --- a/hw/ppc/pnv_core.c +++ b/hw/ppc/pnv_core.c @@ -443,7 +443,6 @@ static const Property pnv_core_properties[] = { false), DEFINE_PROP_BOOL("lpar-per-core", PnvCore, lpar_per_core, false), DEFINE_PROP_LINK("chip", PnvCore, chip, TYPE_PNV_CHIP, PnvChip *), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_core_power8_class_init(ObjectClass *oc, void *data) @@ -695,7 +694,6 @@ static void pnv_quad_power10_realize(DeviceState *dev, Error **errp) static const Property pnv_quad_properties[] = { DEFINE_PROP_UINT32("quad-id", PnvQuad, quad_id, 0), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_quad_power9_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/pnv_homer.c b/hw/ppc/pnv_homer.c index 0f0b42bbeb..a1d83c8149 100644 --- a/hw/ppc/pnv_homer.c +++ b/hw/ppc/pnv_homer.c @@ -414,7 +414,6 @@ static void pnv_homer_realize(DeviceState *dev, Error **errp) static const Property pnv_homer_properties[] = { DEFINE_PROP_LINK("chip", PnvHomer, chip, TYPE_PNV_CHIP, PnvChip *), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_homer_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_i2c.c b/hw/ppc/pnv_i2c.c index b56582899f..8d35f452a2 100644 --- a/hw/ppc/pnv_i2c.c +++ b/hw/ppc/pnv_i2c.c @@ -547,7 +547,6 @@ static const Property pnv_i2c_properties[] = { DEFINE_PROP_LINK("chip", PnvI2C, chip, TYPE_PNV_CHIP, PnvChip *), DEFINE_PROP_UINT32("engine", PnvI2C, engine, 1), DEFINE_PROP_UINT32("num-busses", PnvI2C, num_busses, 1), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_i2c_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_lpc.c b/hw/ppc/pnv_lpc.c index 4d47167163..0480a60f3f 100644 --- a/hw/ppc/pnv_lpc.c +++ b/hw/ppc/pnv_lpc.c @@ -830,7 +830,6 @@ static void pnv_lpc_realize(DeviceState *dev, Error **errp) static const Property pnv_lpc_properties[] = { DEFINE_PROP_BOOL("psi-serirq", PnvLpcController, psi_has_serirq, false), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_lpc_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c index 07e5fcbdb6..863e2e70ac 100644 --- a/hw/ppc/pnv_pnor.c +++ b/hw/ppc/pnv_pnor.c @@ -115,7 +115,6 @@ static void pnv_pnor_realize(DeviceState *dev, Error **errp) static const Property pnv_pnor_properties[] = { DEFINE_PROP_INT64("size", PnvPnor, size, 128 * MiB), DEFINE_PROP_DRIVE("drive", PnvPnor, blk), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_pnor_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index e953e4990e..1fe11dde50 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -555,7 +555,6 @@ static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) static const Property pnv_psi_properties[] = { DEFINE_PROP_UINT64("bar", PnvPsi, bar, 0), DEFINE_PROP_UINT64("fsp-bar", PnvPsi, fsp_bar, 0), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_psi_power8_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index b5cff8d3c5..8250824a1a 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -967,7 +967,6 @@ static void ppc405_cpc_realize(DeviceState *dev, Error **errp) static const Property ppc405_cpc_properties[] = { DEFINE_PROP_UINT32("sys-clk", Ppc405CpcState, sysclk, 0), - DEFINE_PROP_END_OF_LIST(), }; static void ppc405_cpc_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index a1b0145c30..9da30a1724 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -1025,7 +1025,6 @@ static const Property ppc460ex_pcie_props[] = { DEFINE_PROP_INT32("dcrn-base", PPC460EXPCIEState, dcrn_base, -1), DEFINE_PROP_LINK("cpu", PPC460EXPCIEState, cpu, TYPE_POWERPC_CPU, PowerPCCPU *), - DEFINE_PROP_END_OF_LIST(), }; static void ppc460ex_pcie_class_init(ObjectClass *klass, void *data) diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index 530a392f2a..9ce9777510 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -234,7 +234,6 @@ static void ppc4xx_mal_finalize(Object *obj) static const Property ppc4xx_mal_properties[] = { DEFINE_PROP_UINT8("txc-num", Ppc4xxMalState, txcnum, 0), DEFINE_PROP_UINT8("rxc-num", Ppc4xxMalState, rxcnum, 0), - DEFINE_PROP_END_OF_LIST(), }; static void ppc4xx_mal_class_init(ObjectClass *oc, void *data) @@ -542,7 +541,6 @@ bool ppc4xx_dcr_realize(Ppc4xxDcrDeviceState *dev, PowerPCCPU *cpu, static const Property ppc4xx_dcr_properties[] = { DEFINE_PROP_LINK("cpu", Ppc4xxDcrDeviceState, cpu, TYPE_POWERPC_CPU, PowerPCCPU *), - DEFINE_PROP_END_OF_LIST(), }; static void ppc4xx_dcr_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/ppc4xx_sdram.c b/hw/ppc/ppc4xx_sdram.c index 6cfb07a11f..562bff8d53 100644 --- a/hw/ppc/ppc4xx_sdram.c +++ b/hw/ppc/ppc4xx_sdram.c @@ -429,7 +429,6 @@ static const Property ppc4xx_sdram_ddr_props[] = { DEFINE_PROP_LINK("dram", Ppc4xxSdramDdrState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdrState, nbanks, 4), - DEFINE_PROP_END_OF_LIST(), }; static void ppc4xx_sdram_ddr_class_init(ObjectClass *oc, void *data) @@ -714,7 +713,6 @@ static const Property ppc4xx_sdram_ddr2_props[] = { DEFINE_PROP_LINK("dram", Ppc4xxSdramDdr2State, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_UINT32("nbanks", Ppc4xxSdramDdr2State, nbanks, 4), - DEFINE_PROP_END_OF_LIST(), }; static void ppc4xx_sdram_ddr2_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/prep_systemio.c b/hw/ppc/prep_systemio.c index b5380eaee4..b1f2e130f0 100644 --- a/hw/ppc/prep_systemio.c +++ b/hw/ppc/prep_systemio.c @@ -288,7 +288,6 @@ static const VMStateDescription vmstate_prep_systemio = { static const Property prep_systemio_properties[] = { DEFINE_PROP_UINT8("ibm-planar-id", PrepSystemIoState, ibm_planar_id, 0), DEFINE_PROP_UINT8("equipment", PrepSystemIoState, equipment, 0), - DEFINE_PROP_END_OF_LIST() }; static void prep_systemio_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c index bee9bc62d4..0e5d53b8b6 100644 --- a/hw/ppc/rs6000_mc.c +++ b/hw/ppc/rs6000_mc.c @@ -210,7 +210,6 @@ static const VMStateDescription vmstate_rs6000mc = { static const Property rs6000mc_properties[] = { DEFINE_PROP_UINT32("ram-size", RS6000MCState, ram_size, 0), DEFINE_PROP_BOOL("auto-configure", RS6000MCState, autoconfigure, true), - DEFINE_PROP_END_OF_LIST() }; static void rs6000mc_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/ppc/spapr_cpu_core.c b/hw/ppc/spapr_cpu_core.c index d725dd05ca..9e0e0648a7 100644 --- a/hw/ppc/spapr_cpu_core.c +++ b/hw/ppc/spapr_cpu_core.c @@ -363,7 +363,6 @@ static void spapr_cpu_core_realize(DeviceState *dev, Error **errp) static const Property spapr_cpu_core_properties[] = { DEFINE_PROP_INT32("node-id", SpaprCpuCore, node_id, CPU_UNSET_NUMA_NODE_ID), - DEFINE_PROP_END_OF_LIST() }; static void spapr_cpu_core_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/spapr_nvdimm.c b/hw/ppc/spapr_nvdimm.c index 2ef6f29f3d..6f875d73b2 100644 --- a/hw/ppc/spapr_nvdimm.c +++ b/hw/ppc/spapr_nvdimm.c @@ -884,22 +884,22 @@ static void spapr_nvdimm_unrealize(NVDIMMDevice *dimm) vmstate_unregister(NULL, &vmstate_spapr_nvdimm_states, dimm); } -static const Property spapr_nvdimm_properties[] = { #ifdef CONFIG_LIBPMEM +static const Property spapr_nvdimm_properties[] = { DEFINE_PROP_BOOL("pmem-override", SpaprNVDIMMDevice, pmem_override, false), -#endif - DEFINE_PROP_END_OF_LIST(), }; +#endif static void spapr_nvdimm_class_init(ObjectClass *oc, void *data) { - DeviceClass *dc = DEVICE_CLASS(oc); NVDIMMClass *nvc = NVDIMM_CLASS(oc); nvc->realize = spapr_nvdimm_realize; nvc->unrealize = spapr_nvdimm_unrealize; - device_class_set_props(dc, spapr_nvdimm_properties); +#ifdef CONFIG_LIBPMEM + device_class_set_props(DEVICE_CLASS(oc), spapr_nvdimm_properties); +#endif } static void spapr_nvdimm_init(Object *obj) diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index 42eef8c501..904227d9aa 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -2055,7 +2055,6 @@ static const Property spapr_phb_properties[] = { pcie_ecs, true), DEFINE_PROP_BOOL("pre-5.1-associativity", SpaprPhbState, pre_5_1_assoc, false), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_spapr_pci_lsi = { diff --git a/hw/ppc/spapr_rng.c b/hw/ppc/spapr_rng.c index 8cfd61b7db..95def5b1e5 100644 --- a/hw/ppc/spapr_rng.c +++ b/hw/ppc/spapr_rng.c @@ -134,7 +134,6 @@ static const Property spapr_rng_properties[] = { DEFINE_PROP_BOOL("use-kvm", SpaprRngState, use_kvm, false), DEFINE_PROP_LINK("rng", SpaprRngState, backend, TYPE_RNG_BACKEND, RngBackend *), - DEFINE_PROP_END_OF_LIST(), }; static void spapr_rng_class_init(ObjectClass *oc, void *data) diff --git a/hw/ppc/spapr_tpm_proxy.c b/hw/ppc/spapr_tpm_proxy.c index dc0d09eca3..ceaa0acaa1 100644 --- a/hw/ppc/spapr_tpm_proxy.c +++ b/hw/ppc/spapr_tpm_proxy.c @@ -147,7 +147,6 @@ static void spapr_tpm_proxy_unrealize(DeviceState *d) static const Property spapr_tpm_proxy_properties[] = { DEFINE_PROP_STRING("host-path", SpaprTpmProxy, host_path), - DEFINE_PROP_END_OF_LIST(), }; static void spapr_tpm_proxy_class_init(ObjectClass *k, void *data) diff --git a/hw/remote/proxy.c b/hw/remote/proxy.c index 3c08291c61..96d831a579 100644 --- a/hw/remote/proxy.c +++ b/hw/remote/proxy.c @@ -193,7 +193,6 @@ static void pci_proxy_write_config(PCIDevice *d, uint32_t addr, uint32_t val, static const Property proxy_properties[] = { DEFINE_PROP_STRING("fd", PCIProxyDev, fd), - DEFINE_PROP_END_OF_LIST(), }; static void pci_proxy_dev_class_init(ObjectClass *klass, void *data) diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 2e88467c4a..e6a0ac1fa1 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -25,6 +25,14 @@ config MICROCHIP_PFSOC select SIFIVE_PLIC select UNIMP +config MICROBLAZE_V + bool + default y + depends on RISCV32 || RISCV64 + select XILINX + select XILINX_AXI + select XILINX_ETHLITE + config OPENTITAN bool default y diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 7731b88f8a..90e75c69a0 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -67,9 +67,16 @@ char *riscv_plic_hart_config_string(int hart_count) return g_strjoinv(",", (char **)vals); } -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, +void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts) +{ + info->kernel_size = 0; + info->initrd_size = 0; + info->is_32bit = riscv_is_32bit(harts); +} + +target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, target_ulong firmware_end_addr) { - if (riscv_is_32bit(harts)) { + if (info->is_32bit) { return QEMU_ALIGN_UP(firmware_end_addr, 4 * MiB); } else { return QEMU_ALIGN_UP(firmware_end_addr, 2 * MiB); @@ -175,7 +182,7 @@ target_ulong riscv_load_firmware(const char *firmware_filename, exit(1); } -static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) +static void riscv_load_initrd(MachineState *machine, RISCVBootInfo *info) { const char *filename = machine->initrd_filename; uint64_t mem_size = machine->ram_size; @@ -196,7 +203,7 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) * halfway into RAM, and for boards with 1GB of RAM or more we put * the initrd at 512MB. */ - start = kernel_entry + MIN(mem_size / 2, 512 * MiB); + start = info->image_low_addr + MIN(mem_size / 2, 512 * MiB); size = load_ramdisk(filename, start, mem_size - start); if (size == -1) { @@ -207,6 +214,9 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) } } + info->initrd_start = start; + info->initrd_size = size; + /* Some RISC-V machines (e.g. opentitan) don't have a fdt. */ if (fdt) { end = start + size; @@ -215,14 +225,14 @@ static void riscv_load_initrd(MachineState *machine, uint64_t kernel_entry) } } -target_ulong riscv_load_kernel(MachineState *machine, - RISCVHartArrayState *harts, - target_ulong kernel_start_addr, - bool load_initrd, - symbol_fn_t sym_cb) +void riscv_load_kernel(MachineState *machine, + RISCVBootInfo *info, + target_ulong kernel_start_addr, + bool load_initrd, + symbol_fn_t sym_cb) { const char *kernel_filename = machine->kernel_filename; - uint64_t kernel_load_base, kernel_entry; + ssize_t kernel_size; void *fdt = machine->fdt; g_assert(kernel_filename != NULL); @@ -234,21 +244,28 @@ target_ulong riscv_load_kernel(MachineState *machine, * the (expected) load address load address. This allows kernels to have * separate SBI and ELF entry points (used by FreeBSD, for example). */ - if (load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, - NULL, &kernel_load_base, NULL, NULL, 0, - EM_RISCV, 1, 0, NULL, true, sym_cb) > 0) { - kernel_entry = kernel_load_base; + kernel_size = load_elf_ram_sym(kernel_filename, NULL, NULL, NULL, NULL, + &info->image_low_addr, &info->image_high_addr, + NULL, 0, EM_RISCV, 1, 0, NULL, true, sym_cb); + if (kernel_size > 0) { + info->kernel_size = kernel_size; goto out; } - if (load_uimage_as(kernel_filename, &kernel_entry, NULL, NULL, - NULL, NULL, NULL) > 0) { + kernel_size = load_uimage_as(kernel_filename, &info->image_low_addr, + NULL, NULL, NULL, NULL, NULL); + if (kernel_size > 0) { + info->kernel_size = kernel_size; + info->image_high_addr = info->image_low_addr + kernel_size; goto out; } - if (load_image_targphys_as(kernel_filename, kernel_start_addr, - current_machine->ram_size, NULL) > 0) { - kernel_entry = kernel_start_addr; + kernel_size = load_image_targphys_as(kernel_filename, kernel_start_addr, + current_machine->ram_size, NULL); + if (kernel_size > 0) { + info->kernel_size = kernel_size; + info->image_low_addr = kernel_start_addr; + info->image_high_addr = info->image_low_addr + kernel_size; goto out; } @@ -257,23 +274,21 @@ target_ulong riscv_load_kernel(MachineState *machine, out: /* - * For 32 bit CPUs 'kernel_entry' can be sign-extended by + * For 32 bit CPUs 'image_low_addr' can be sign-extended by * load_elf_ram_sym(). */ - if (riscv_is_32bit(harts)) { - kernel_entry = extract64(kernel_entry, 0, 32); + if (info->is_32bit) { + info->image_low_addr = extract64(info->image_low_addr, 0, 32); } if (load_initrd && machine->initrd_filename) { - riscv_load_initrd(machine, kernel_entry); + riscv_load_initrd(machine, info); } if (fdt && machine->kernel_cmdline && *machine->kernel_cmdline) { qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", machine->kernel_cmdline); } - - return kernel_entry; } /* @@ -293,11 +308,12 @@ out: * The FDT is fdt_packed() during the calculation. */ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, - MachineState *ms) + MachineState *ms, RISCVBootInfo *info) { int ret = fdt_pack(ms->fdt); hwaddr dram_end, temp; int fdtsize; + uint64_t dtb_start, dtb_start_limit; /* Should only fail if we've built a corrupted tree */ g_assert(ret == 0); @@ -308,6 +324,17 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, exit(1); } + if (info->initrd_size) { + /* If initrd is successfully loaded, place DTB after it. */ + dtb_start_limit = info->initrd_start + info->initrd_size; + } else if (info->kernel_size) { + /* If only kernel is successfully loaded, place DTB after it. */ + dtb_start_limit = info->image_high_addr; + } else { + /* Otherwise, do not check DTB overlapping */ + dtb_start_limit = 0; + } + /* * A dram_size == 0, usually from a MemMapEntry[].size element, * means that the DRAM block goes all the way to ms->ram_size. @@ -317,13 +344,24 @@ uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, /* * We should put fdt as far as possible to avoid kernel/initrd overwriting - * its content. But it should be addressable by 32 bit system as well. - * Thus, put it at an 2MB aligned address that less than fdt size from the - * end of dram or 3GB whichever is lesser. + * its content. But it should be addressable by 32 bit system as well in RV32. + * Thus, put it near to the end of dram in RV64, and put it near to the end + * of dram or 3GB whichever is lesser in RV32. */ - temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; + if (!info->is_32bit) { + temp = dram_end; + } else { + temp = (dram_base < 3072 * MiB) ? MIN(dram_end, 3072 * MiB) : dram_end; + } + + dtb_start = QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); + + if (dtb_start_limit && (dtb_start < dtb_start_limit)) { + error_report("No enough memory to place DTB after kernel/initrd"); + exit(1); + } - return QEMU_ALIGN_DOWN(temp - fdtsize, 2 * MiB); + return dtb_start; } /* diff --git a/hw/riscv/meson.build b/hw/riscv/meson.build index adbef8a9b2..3c7e083aca 100644 --- a/hw/riscv/meson.build +++ b/hw/riscv/meson.build @@ -10,6 +10,7 @@ riscv_ss.add(when: 'CONFIG_SIFIVE_U', if_true: files('sifive_u.c')) riscv_ss.add(when: 'CONFIG_SPIKE', if_true: files('spike.c')) riscv_ss.add(when: 'CONFIG_MICROCHIP_PFSOC', if_true: files('microchip_pfsoc.c')) riscv_ss.add(when: 'CONFIG_ACPI', if_true: files('virt-acpi-build.c')) -riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c')) +riscv_ss.add(when: 'CONFIG_RISCV_IOMMU', if_true: files('riscv-iommu.c', 'riscv-iommu-pci.c', 'riscv-iommu-sys.c')) +riscv_ss.add(when: 'CONFIG_MICROBLAZE_V', if_true: files('microblaze-v-generic.c')) hw_arch += {'riscv': riscv_ss} diff --git a/hw/riscv/microblaze-v-generic.c b/hw/riscv/microblaze-v-generic.c new file mode 100644 index 0000000000..26788a1824 --- /dev/null +++ b/hw/riscv/microblaze-v-generic.c @@ -0,0 +1,184 @@ +/* + * QEMU model of Microblaze V generic board. + * + * based on hw/microblaze/petalogix_ml605_mmu.c + * + * Copyright (c) 2011 Michal Simek <monstr@monstr.eu> + * Copyright (c) 2011 PetaLogix + * Copyright (c) 2009 Edgar E. Iglesias. + * Copyright (C) 2024, Advanced Micro Devices, Inc. + * SPDX-License-Identifier: GPL-2.0-or-later + * + * Written by Sai Pavan Boddu <sai.pavan.boddu@amd.com + * and by Michal Simek <michal.simek@amd.com>. + */ + +#include "qemu/osdep.h" +#include "qemu/units.h" +#include "qapi/error.h" +#include "cpu.h" +#include "hw/sysbus.h" +#include "system/system.h" +#include "net/net.h" +#include "hw/boards.h" +#include "hw/char/serial-mm.h" +#include "exec/address-spaces.h" +#include "hw/char/xilinx_uartlite.h" +#include "hw/misc/unimp.h" + +#define LMB_BRAM_SIZE (128 * KiB) +#define MEMORY_BASEADDR 0x80000000 +#define INTC_BASEADDR 0x41200000 +#define TIMER_BASEADDR 0x41c00000 +#define TIMER_BASEADDR2 0x41c10000 +#define UARTLITE_BASEADDR 0x40600000 +#define ETHLITE_BASEADDR 0x40e00000 +#define UART16550_BASEADDR 0x44a10000 +#define AXIENET_BASEADDR 0x40c00000 +#define AXIDMA_BASEADDR 0x41e00000 +#define GPIO_BASEADDR 0x40000000 +#define GPIO_BASEADDR2 0x40010000 +#define GPIO_BASEADDR3 0x40020000 +#define I2C_BASEADDR 0x40800000 +#define QSPI_BASEADDR 0x44a00000 + +#define TIMER_IRQ 0 +#define UARTLITE_IRQ 1 +#define UART16550_IRQ 4 +#define ETHLITE_IRQ 5 +#define TIMER_IRQ2 6 +#define AXIENET_IRQ 7 +#define AXIDMA_IRQ1 8 +#define AXIDMA_IRQ0 9 + +static void mb_v_generic_init(MachineState *machine) +{ + ram_addr_t ram_size = machine->ram_size; + DeviceState *dev, *dma, *eth0; + Object *ds, *cs; + int i; + RISCVCPU *cpu; + hwaddr ddr_base = MEMORY_BASEADDR; + MemoryRegion *phys_lmb_bram = g_new(MemoryRegion, 1); + MemoryRegion *phys_ram = g_new(MemoryRegion, 1); + qemu_irq irq[32]; + MemoryRegion *sysmem = get_system_memory(); + + cpu = RISCV_CPU(object_new(machine->cpu_type)); + object_property_set_bool(OBJECT(cpu), "h", false, NULL); + object_property_set_bool(OBJECT(cpu), "d", false, NULL); + qdev_realize(DEVICE(cpu), NULL, &error_abort); + /* Attach emulated BRAM through the LMB. */ + memory_region_init_ram(phys_lmb_bram, NULL, + "mb_v.lmb_bram", LMB_BRAM_SIZE, + &error_fatal); + memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram); + + memory_region_init_ram(phys_ram, NULL, "mb_v.ram", + ram_size, &error_fatal); + memory_region_add_subregion(sysmem, ddr_base, phys_ram); + + dev = qdev_new("xlnx.xps-intc"); + qdev_prop_set_uint32(dev, "kind-of-intr", + 1 << UARTLITE_IRQ); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, + qdev_get_gpio_in(DEVICE(cpu), 11)); + for (i = 0; i < 32; i++) { + irq[i] = qdev_get_gpio_in(dev, i); + } + + /* Uartlite */ + dev = qdev_new(TYPE_XILINX_UARTLITE); + qdev_prop_set_chr(dev, "chardev", serial_hd(0)); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, UARTLITE_BASEADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[UARTLITE_IRQ]); + + /* Full uart */ + serial_mm_init(sysmem, UART16550_BASEADDR + 0x1000, 2, + irq[UART16550_IRQ], 115200, serial_hd(1), + DEVICE_LITTLE_ENDIAN); + + /* 2 timers at irq 0 @ 100 Mhz. */ + dev = qdev_new("xlnx.xps-timer"); + qdev_prop_set_uint32(dev, "one-timer-only", 0); + qdev_prop_set_uint32(dev, "clock-frequency", 100000000); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ]); + + /* 2 timers at irq 3 @ 100 Mhz. */ + dev = qdev_new("xlnx.xps-timer"); + qdev_prop_set_uint32(dev, "one-timer-only", 0); + qdev_prop_set_uint32(dev, "clock-frequency", 100000000); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, TIMER_BASEADDR2); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[TIMER_IRQ2]); + + /* Emaclite */ + dev = qdev_new("xlnx.xps-ethernetlite"); + qemu_configure_nic_device(dev, true, NULL); + qdev_prop_set_uint32(dev, "tx-ping-pong", 0); + qdev_prop_set_uint32(dev, "rx-ping-pong", 0); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, ETHLITE_BASEADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, irq[ETHLITE_IRQ]); + + /* axi ethernet and dma initialization. */ + eth0 = qdev_new("xlnx.axi-ethernet"); + dma = qdev_new("xlnx.axi-dma"); + + /* FIXME: attach to the sysbus instead */ + object_property_add_child(qdev_get_machine(), "xilinx-eth", OBJECT(eth0)); + object_property_add_child(qdev_get_machine(), "xilinx-dma", OBJECT(dma)); + + ds = object_property_get_link(OBJECT(dma), + "axistream-connected-target", NULL); + cs = object_property_get_link(OBJECT(dma), + "axistream-control-connected-target", NULL); + qemu_configure_nic_device(eth0, true, NULL); + qdev_prop_set_uint32(eth0, "rxmem", 0x1000); + qdev_prop_set_uint32(eth0, "txmem", 0x1000); + object_property_set_link(OBJECT(eth0), "axistream-connected", ds, + &error_abort); + object_property_set_link(OBJECT(eth0), "axistream-control-connected", cs, + &error_abort); + sysbus_realize_and_unref(SYS_BUS_DEVICE(eth0), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(eth0), 0, AXIENET_BASEADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(eth0), 0, irq[AXIENET_IRQ]); + + ds = object_property_get_link(OBJECT(eth0), + "axistream-connected-target", NULL); + cs = object_property_get_link(OBJECT(eth0), + "axistream-control-connected-target", NULL); + qdev_prop_set_uint32(dma, "freqhz", 100000000); + object_property_set_link(OBJECT(dma), "axistream-connected", ds, + &error_abort); + object_property_set_link(OBJECT(dma), "axistream-control-connected", cs, + &error_abort); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dma), &error_fatal); + sysbus_mmio_map(SYS_BUS_DEVICE(dma), 0, AXIDMA_BASEADDR); + sysbus_connect_irq(SYS_BUS_DEVICE(dma), 0, irq[AXIDMA_IRQ0]); + sysbus_connect_irq(SYS_BUS_DEVICE(dma), 1, irq[AXIDMA_IRQ1]); + + /* unimplemented devices */ + create_unimplemented_device("gpio", GPIO_BASEADDR, 0x10000); + create_unimplemented_device("gpio2", GPIO_BASEADDR2, 0x10000); + create_unimplemented_device("gpio3", GPIO_BASEADDR3, 0x10000); + create_unimplemented_device("i2c", I2C_BASEADDR, 0x10000); + create_unimplemented_device("qspi", QSPI_BASEADDR, 0x10000); +} + +static void mb_v_generic_machine_init(MachineClass *mc) +{ + mc->desc = "AMD Microblaze-V generic platform"; + mc->init = mb_v_generic_init; + mc->min_cpus = 1; + mc->max_cpus = 1; + mc->default_cpu_type = TYPE_RISCV_CPU_BASE; + mc->default_cpus = 1; +} + +DEFINE_MACHINE("amd-microblaze-v-generic", mb_v_generic_machine_init) diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index 1208d684a4..ec7e2e4226 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -519,8 +519,9 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) bool kernel_as_payload = false; target_ulong firmware_end_addr, kernel_start_addr; uint64_t kernel_entry; - uint32_t fdt_load_addr; + uint64_t fdt_load_addr; DriveInfo *dinfo = drive_get(IF_SD, 0, 0); + RISCVBootInfo boot_info; /* Sanity check on RAM size */ if (machine->ram_size < mc->default_ram_size) { @@ -615,17 +616,19 @@ static void microchip_icicle_kit_machine_init(MachineState *machine) firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, &firmware_load_addr, NULL); + riscv_boot_info_init(&boot_info, &s->soc.u_cpus); if (kernel_as_payload) { - kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, + kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, true, NULL); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, + true, NULL); + kernel_entry = boot_info.image_low_addr; /* Compute the fdt load address in dram */ fdt_load_addr = riscv_compute_fdt_addr(memmap[MICROCHIP_PFSOC_DRAM_LO].base, memmap[MICROCHIP_PFSOC_DRAM_LO].size, - machine); + machine, &boot_info); riscv_load_fdt(fdt_load_addr, machine->fdt); /* Load the reset vector */ diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index e4f643cb52..b9e56235d8 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -81,6 +81,7 @@ static void opentitan_machine_init(MachineState *machine) OpenTitanState *s = OPENTITAN_MACHINE(machine); const MemMapEntry *memmap = ibex_memmap; MemoryRegion *sys_mem = get_system_memory(); + RISCVBootInfo boot_info; if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); @@ -102,8 +103,9 @@ static void opentitan_machine_init(MachineState *machine) riscv_load_firmware(machine->firmware, &firmware_load_addr, NULL); } + riscv_boot_info_init(&boot_info, &s->soc.cpus); if (machine->kernel_filename) { - riscv_load_kernel(machine, &s->soc.cpus, + riscv_load_kernel(machine, &boot_info, memmap[IBEX_DEV_RAM].base, false, NULL); } @@ -308,7 +310,6 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp) static const Property lowrisc_ibex_soc_props[] = { DEFINE_PROP_UINT32("resetvec", LowRISCIbexSoCState, resetvec, 0x20000400), - DEFINE_PROP_END_OF_LIST() }; static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data) diff --git a/hw/riscv/riscv-iommu-bits.h b/hw/riscv/riscv-iommu-bits.h index 6359ae0353..485f36b9c9 100644 --- a/hw/riscv/riscv-iommu-bits.h +++ b/hw/riscv/riscv-iommu-bits.h @@ -88,6 +88,12 @@ struct riscv_iommu_pq_record { #define RISCV_IOMMU_CAP_PD17 BIT_ULL(39) #define RISCV_IOMMU_CAP_PD20 BIT_ULL(40) +enum riscv_iommu_igs_modes { + RISCV_IOMMU_CAP_IGS_MSI = 0, + RISCV_IOMMU_CAP_IGS_WSI, + RISCV_IOMMU_CAP_IGS_BOTH +}; + /* 5.4 Features control register (32bits) */ #define RISCV_IOMMU_REG_FCTL 0x0008 #define RISCV_IOMMU_FCTL_BE BIT(0) diff --git a/hw/riscv/riscv-iommu-pci.c b/hw/riscv/riscv-iommu-pci.c index a695314bbe..12451869e4 100644 --- a/hw/riscv/riscv-iommu-pci.c +++ b/hw/riscv/riscv-iommu-pci.c @@ -31,6 +31,7 @@ #include "cpu_bits.h" #include "riscv-iommu.h" #include "riscv-iommu-bits.h" +#include "trace.h" /* RISC-V IOMMU PCI Device Emulation */ #define RISCV_PCI_CLASS_SYSTEM_IOMMU 0x0806 @@ -66,6 +67,12 @@ typedef struct RISCVIOMMUStatePci { RISCVIOMMUState iommu; /* common IOMMU state */ } RISCVIOMMUStatePci; +struct RISCVIOMMUPciClass { + /*< public >*/ + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + /* interrupt delivery callback */ static void riscv_iommu_pci_notify(RISCVIOMMUState *iommu, unsigned vector) { @@ -155,6 +162,7 @@ static void riscv_iommu_pci_init(Object *obj) qdev_alias_all_properties(DEVICE(iommu), obj); iommu->icvec_avail_vectors = RISCV_IOMMU_PCI_ICVEC_VECTORS; + riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_MSI); } static const Property riscv_iommu_pci_properties[] = { @@ -163,13 +171,25 @@ static const Property riscv_iommu_pci_properties[] = { DEFINE_PROP_UINT16("device-id", RISCVIOMMUStatePci, device_id, PCI_DEVICE_ID_REDHAT_RISCV_IOMMU), DEFINE_PROP_UINT8("revision", RISCVIOMMUStatePci, revision, 0x01), - DEFINE_PROP_END_OF_LIST(), }; +static void riscv_iommu_pci_reset_hold(Object *obj, ResetType type) +{ + RISCVIOMMUStatePci *pci = RISCV_IOMMU_PCI(obj); + RISCVIOMMUState *iommu = &pci->iommu; + + riscv_iommu_reset(iommu); + + trace_riscv_iommu_pci_reset_hold(type); +} + static void riscv_iommu_pci_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + rc->phases.hold = riscv_iommu_pci_reset_hold; k->realize = riscv_iommu_pci_realize; k->exit = riscv_iommu_pci_exit; diff --git a/hw/riscv/riscv-iommu-sys.c b/hw/riscv/riscv-iommu-sys.c new file mode 100644 index 0000000000..28153f38da --- /dev/null +++ b/hw/riscv/riscv-iommu-sys.c @@ -0,0 +1,255 @@ +/* + * QEMU emulation of an RISC-V IOMMU Platform Device + * + * Copyright (C) 2022-2023 Rivos Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License along + * with this program; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/irq.h" +#include "hw/pci/pci_bus.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "qapi/error.h" +#include "qemu/error-report.h" +#include "qemu/host-utils.h" +#include "qemu/module.h" +#include "qom/object.h" +#include "exec/exec-all.h" +#include "trace.h" + +#include "riscv-iommu.h" + +#define RISCV_IOMMU_SYSDEV_ICVEC_VECTORS 0x3333 + +#define RISCV_IOMMU_PCI_MSIX_VECTORS 5 + +/* RISC-V IOMMU System Platform Device Emulation */ + +struct RISCVIOMMUStateSys { + SysBusDevice parent; + uint64_t addr; + uint32_t base_irq; + DeviceState *irqchip; + RISCVIOMMUState iommu; + + /* Wired int support */ + qemu_irq irqs[RISCV_IOMMU_INTR_COUNT]; + + /* Memory Regions for MSIX table and pending bit entries. */ + MemoryRegion msix_table_mmio; + MemoryRegion msix_pba_mmio; + uint8_t *msix_table; + uint8_t *msix_pba; +}; + +struct RISCVIOMMUSysClass { + /*< public >*/ + DeviceRealize parent_realize; + ResettablePhases parent_phases; +}; + +static uint64_t msix_table_mmio_read(void *opaque, hwaddr addr, + unsigned size) +{ + RISCVIOMMUStateSys *s = opaque; + + g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE); + return pci_get_long(s->msix_table + addr); +} + +static void msix_table_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ + RISCVIOMMUStateSys *s = opaque; + + g_assert(addr + size <= RISCV_IOMMU_PCI_MSIX_VECTORS * PCI_MSIX_ENTRY_SIZE); + pci_set_long(s->msix_table + addr, val); +} + +static const MemoryRegionOps msix_table_mmio_ops = { + .read = msix_table_mmio_read, + .write = msix_table_mmio_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 8, + }, + .impl = { + .max_access_size = 4, + }, +}; + +static uint64_t msix_pba_mmio_read(void *opaque, hwaddr addr, + unsigned size) +{ + RISCVIOMMUStateSys *s = opaque; + + return pci_get_long(s->msix_pba + addr); +} + +static void msix_pba_mmio_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) +{ +} + +static const MemoryRegionOps msix_pba_mmio_ops = { + .read = msix_pba_mmio_read, + .write = msix_pba_mmio_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 8, + }, + .impl = { + .max_access_size = 4, + }, +}; + +static void riscv_iommu_sysdev_init_msi(RISCVIOMMUStateSys *s, + uint32_t n_vectors) +{ + RISCVIOMMUState *iommu = &s->iommu; + uint32_t table_size = table_size = n_vectors * PCI_MSIX_ENTRY_SIZE; + uint32_t table_offset = RISCV_IOMMU_REG_MSI_CONFIG; + uint32_t pba_size = QEMU_ALIGN_UP(n_vectors, 64) / 8; + uint32_t pba_offset = RISCV_IOMMU_REG_MSI_CONFIG + 256; + + s->msix_table = g_malloc0(table_size); + s->msix_pba = g_malloc0(pba_size); + + memory_region_init_io(&s->msix_table_mmio, OBJECT(s), &msix_table_mmio_ops, + s, "msix-table", table_size); + memory_region_add_subregion(&iommu->regs_mr, table_offset, + &s->msix_table_mmio); + + memory_region_init_io(&s->msix_pba_mmio, OBJECT(s), &msix_pba_mmio_ops, s, + "msix-pba", pba_size); + memory_region_add_subregion(&iommu->regs_mr, pba_offset, + &s->msix_pba_mmio); +} + +static void riscv_iommu_sysdev_send_MSI(RISCVIOMMUStateSys *s, + uint32_t vector) +{ + uint8_t *table_entry = s->msix_table + vector * PCI_MSIX_ENTRY_SIZE; + uint64_t msi_addr = pci_get_quad(table_entry + PCI_MSIX_ENTRY_LOWER_ADDR); + uint32_t msi_data = pci_get_long(table_entry + PCI_MSIX_ENTRY_DATA); + MemTxResult result; + + address_space_stl_le(&address_space_memory, msi_addr, + msi_data, MEMTXATTRS_UNSPECIFIED, &result); + trace_riscv_iommu_sys_msi_sent(vector, msi_addr, msi_data, result); +} + +static void riscv_iommu_sysdev_notify(RISCVIOMMUState *iommu, + unsigned vector) +{ + RISCVIOMMUStateSys *s = container_of(iommu, RISCVIOMMUStateSys, iommu); + uint32_t fctl = riscv_iommu_reg_get32(iommu, RISCV_IOMMU_REG_FCTL); + + if (fctl & RISCV_IOMMU_FCTL_WSI) { + qemu_irq_pulse(s->irqs[vector]); + trace_riscv_iommu_sys_irq_sent(vector); + return; + } + + riscv_iommu_sysdev_send_MSI(s, vector); +} + +static void riscv_iommu_sys_realize(DeviceState *dev, Error **errp) +{ + RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(dev); + SysBusDevice *sysdev = SYS_BUS_DEVICE(s); + PCIBus *pci_bus; + qemu_irq irq; + + qdev_realize(DEVICE(&s->iommu), NULL, errp); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->iommu.regs_mr); + if (s->addr) { + sysbus_mmio_map(SYS_BUS_DEVICE(s), 0, s->addr); + } + + pci_bus = (PCIBus *) object_resolve_path_type("", TYPE_PCI_BUS, NULL); + if (pci_bus) { + riscv_iommu_pci_setup_iommu(&s->iommu, pci_bus, errp); + } + + s->iommu.notify = riscv_iommu_sysdev_notify; + + /* 4 IRQs are defined starting from s->base_irq */ + for (int i = 0; i < RISCV_IOMMU_INTR_COUNT; i++) { + sysbus_init_irq(sysdev, &s->irqs[i]); + irq = qdev_get_gpio_in(s->irqchip, s->base_irq + i); + sysbus_connect_irq(sysdev, i, irq); + } + + riscv_iommu_sysdev_init_msi(s, RISCV_IOMMU_PCI_MSIX_VECTORS); +} + +static void riscv_iommu_sys_init(Object *obj) +{ + RISCVIOMMUStateSys *s = RISCV_IOMMU_SYS(obj); + RISCVIOMMUState *iommu = &s->iommu; + + object_initialize_child(obj, "iommu", iommu, TYPE_RISCV_IOMMU); + qdev_alias_all_properties(DEVICE(iommu), obj); + + iommu->icvec_avail_vectors = RISCV_IOMMU_SYSDEV_ICVEC_VECTORS; + riscv_iommu_set_cap_igs(iommu, RISCV_IOMMU_CAP_IGS_BOTH); +} + +static const Property riscv_iommu_sys_properties[] = { + DEFINE_PROP_UINT64("addr", RISCVIOMMUStateSys, addr, 0), + DEFINE_PROP_UINT32("base-irq", RISCVIOMMUStateSys, base_irq, 0), + DEFINE_PROP_LINK("irqchip", RISCVIOMMUStateSys, irqchip, + TYPE_DEVICE, DeviceState *), +}; + +static void riscv_iommu_sys_reset_hold(Object *obj, ResetType type) +{ + RISCVIOMMUStateSys *sys = RISCV_IOMMU_SYS(obj); + RISCVIOMMUState *iommu = &sys->iommu; + + riscv_iommu_reset(iommu); + + trace_riscv_iommu_sys_reset_hold(type); +} + +static void riscv_iommu_sys_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + ResettableClass *rc = RESETTABLE_CLASS(klass); + + rc->phases.hold = riscv_iommu_sys_reset_hold; + + dc->realize = riscv_iommu_sys_realize; + set_bit(DEVICE_CATEGORY_MISC, dc->categories); + device_class_set_props(dc, riscv_iommu_sys_properties); +} + +static const TypeInfo riscv_iommu_sys = { + .name = TYPE_RISCV_IOMMU_SYS, + .parent = TYPE_SYS_BUS_DEVICE, + .class_init = riscv_iommu_sys_class_init, + .instance_init = riscv_iommu_sys_init, + .instance_size = sizeof(RISCVIOMMUStateSys), +}; + +static void riscv_iommu_register_sys(void) +{ + type_register_static(&riscv_iommu_sys); +} + +type_init(riscv_iommu_register_sys) diff --git a/hw/riscv/riscv-iommu.c b/hw/riscv/riscv-iommu.c index 07fed36986..8bf920deab 100644 --- a/hw/riscv/riscv-iommu.c +++ b/hw/riscv/riscv-iommu.c @@ -94,10 +94,9 @@ static uint8_t riscv_iommu_get_icvec_vector(uint32_t icvec, uint32_t vec_type) static void riscv_iommu_notify(RISCVIOMMUState *s, int vec_type) { - const uint32_t fctl = riscv_iommu_reg_get32(s, RISCV_IOMMU_REG_FCTL); uint32_t ipsr, icvec, vector; - if (fctl & RISCV_IOMMU_FCTL_WSI || !s->notify) { + if (!s->notify) { return; } @@ -392,9 +391,26 @@ static int riscv_iommu_spa_fetch(RISCVIOMMUState *s, RISCVIOMMUContext *ctx, /* Address range check before first level lookup */ if (!sc[pass].step) { - const uint64_t va_mask = (1ULL << (va_skip + va_bits)) - 1; - if ((addr & va_mask) != addr) { - return RISCV_IOMMU_FQ_CAUSE_DMA_DISABLED; + const uint64_t va_len = va_skip + va_bits; + const uint64_t va_mask = (1ULL << va_len) - 1; + + if (pass == S_STAGE && va_len > 32) { + target_ulong mask, masked_msbs; + + mask = (1L << (TARGET_LONG_BITS - (va_len - 1))) - 1; + masked_msbs = (addr >> (va_len - 1)) & mask; + + if (masked_msbs != 0 && masked_msbs != mask) { + return (iotlb->perm & IOMMU_WO) ? + RISCV_IOMMU_FQ_CAUSE_WR_FAULT_S : + RISCV_IOMMU_FQ_CAUSE_RD_FAULT_S; + } + } else { + if ((addr & va_mask) != addr) { + return (iotlb->perm & IOMMU_WO) ? + RISCV_IOMMU_FQ_CAUSE_WR_FAULT_VS : + RISCV_IOMMU_FQ_CAUSE_RD_FAULT_VS; + } } } @@ -2113,11 +2129,53 @@ static const MemoryRegionOps riscv_iommu_trap_ops = { } }; +void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode) +{ + s->cap = set_field(s->cap, RISCV_IOMMU_CAP_IGS, mode); +} + +static void riscv_iommu_instance_init(Object *obj) +{ + RISCVIOMMUState *s = RISCV_IOMMU(obj); + + /* Enable translation debug interface */ + s->cap = RISCV_IOMMU_CAP_DBG; + + /* Report QEMU target physical address space limits */ + s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, + TARGET_PHYS_ADDR_SPACE_BITS); + + /* TODO: method to report supported PID bits */ + s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */ + s->cap |= RISCV_IOMMU_CAP_PD8; + + /* register storage */ + s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); + s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); + s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); + + /* Mark all registers read-only */ + memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE); + + /* Device translation context cache */ + s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash, + riscv_iommu_ctx_equal, + g_free, NULL); + + s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash, + riscv_iommu_iot_equal, + g_free, NULL); + + s->iommus.le_next = NULL; + s->iommus.le_prev = NULL; + QLIST_INIT(&s->spaces); +} + static void riscv_iommu_realize(DeviceState *dev, Error **errp) { RISCVIOMMUState *s = RISCV_IOMMU(dev); - s->cap = s->version & RISCV_IOMMU_CAP_VERSION; + s->cap |= s->version & RISCV_IOMMU_CAP_VERSION; if (s->enable_msi) { s->cap |= RISCV_IOMMU_CAP_MSI_FLAT | RISCV_IOMMU_CAP_MSI_MRIF; } @@ -2132,29 +2190,11 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp) s->cap |= RISCV_IOMMU_CAP_SV32X4 | RISCV_IOMMU_CAP_SV39X4 | RISCV_IOMMU_CAP_SV48X4 | RISCV_IOMMU_CAP_SV57X4; } - /* Enable translation debug interface */ - s->cap |= RISCV_IOMMU_CAP_DBG; - - /* Report QEMU target physical address space limits */ - s->cap = set_field(s->cap, RISCV_IOMMU_CAP_PAS, - TARGET_PHYS_ADDR_SPACE_BITS); - - /* TODO: method to report supported PID bits */ - s->pid_bits = 8; /* restricted to size of MemTxAttrs.pid */ - s->cap |= RISCV_IOMMU_CAP_PD8; /* Out-of-reset translation mode: OFF (DMA disabled) BARE (passthrough) */ s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, s->enable_off ? RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE); - /* register storage */ - s->regs_rw = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); - s->regs_ro = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); - s->regs_wc = g_new0(uint8_t, RISCV_IOMMU_REG_SIZE); - - /* Mark all registers read-only */ - memset(s->regs_ro, 0xff, RISCV_IOMMU_REG_SIZE); - /* * Register complete MMIO space, including MSI/PBA registers. * Note, PCIDevice implementation will add overlapping MR for MSI/PBA, @@ -2212,19 +2252,6 @@ static void riscv_iommu_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->trap_mr, OBJECT(dev), &riscv_iommu_trap_ops, s, "riscv-iommu-trap", ~0ULL); address_space_init(&s->trap_as, &s->trap_mr, "riscv-iommu-trap-as"); - - /* Device translation context cache */ - s->ctx_cache = g_hash_table_new_full(riscv_iommu_ctx_hash, - riscv_iommu_ctx_equal, - g_free, NULL); - - s->iot_cache = g_hash_table_new_full(riscv_iommu_iot_hash, - riscv_iommu_iot_equal, - g_free, NULL); - - s->iommus.le_next = NULL; - s->iommus.le_prev = NULL; - QLIST_INIT(&s->spaces); } static void riscv_iommu_unrealize(DeviceState *dev) @@ -2235,6 +2262,41 @@ static void riscv_iommu_unrealize(DeviceState *dev) g_hash_table_unref(s->ctx_cache); } +void riscv_iommu_reset(RISCVIOMMUState *s) +{ + uint32_t reg_clr; + int ddtp_mode; + + /* + * Clear DDTP while setting DDTP_mode back to user + * initial setting. + */ + ddtp_mode = s->enable_off ? + RISCV_IOMMU_DDTP_MODE_OFF : RISCV_IOMMU_DDTP_MODE_BARE; + s->ddtp = set_field(0, RISCV_IOMMU_DDTP_MODE, ddtp_mode); + riscv_iommu_reg_set64(s, RISCV_IOMMU_REG_DDTP, s->ddtp); + + reg_clr = RISCV_IOMMU_CQCSR_CQEN | RISCV_IOMMU_CQCSR_CIE | + RISCV_IOMMU_CQCSR_CQON | RISCV_IOMMU_CQCSR_BUSY; + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_CQCSR, 0, reg_clr); + + reg_clr = RISCV_IOMMU_FQCSR_FQEN | RISCV_IOMMU_FQCSR_FIE | + RISCV_IOMMU_FQCSR_FQON | RISCV_IOMMU_FQCSR_BUSY; + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_FQCSR, 0, reg_clr); + + reg_clr = RISCV_IOMMU_PQCSR_PQEN | RISCV_IOMMU_PQCSR_PIE | + RISCV_IOMMU_PQCSR_PQON | RISCV_IOMMU_PQCSR_BUSY; + riscv_iommu_reg_mod32(s, RISCV_IOMMU_REG_PQCSR, 0, reg_clr); + + riscv_iommu_reg_mod64(s, RISCV_IOMMU_REG_TR_REQ_CTL, 0, + RISCV_IOMMU_TR_REQ_CTL_GO_BUSY); + + riscv_iommu_reg_set32(s, RISCV_IOMMU_REG_IPSR, 0); + + g_hash_table_remove_all(s->ctx_cache); + g_hash_table_remove_all(s->iot_cache); +} + static const Property riscv_iommu_properties[] = { DEFINE_PROP_UINT32("version", RISCVIOMMUState, version, RISCV_IOMMU_SPEC_DOT_VER), @@ -2248,7 +2310,6 @@ static const Property riscv_iommu_properties[] = { DEFINE_PROP_BOOL("g-stage", RISCVIOMMUState, enable_g_stage, TRUE), DEFINE_PROP_LINK("downstream-mr", RISCVIOMMUState, target_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void riscv_iommu_class_init(ObjectClass *klass, void* data) @@ -2266,6 +2327,7 @@ static const TypeInfo riscv_iommu_info = { .name = TYPE_RISCV_IOMMU, .parent = TYPE_DEVICE, .instance_size = sizeof(RISCVIOMMUState), + .instance_init = riscv_iommu_instance_init, .class_init = riscv_iommu_class_init, }; diff --git a/hw/riscv/riscv-iommu.h b/hw/riscv/riscv-iommu.h index da3f03440c..9424989df4 100644 --- a/hw/riscv/riscv-iommu.h +++ b/hw/riscv/riscv-iommu.h @@ -21,6 +21,9 @@ #include "qom/object.h" #include "hw/riscv/iommu.h" +#include "hw/riscv/riscv-iommu-bits.h" + +typedef enum riscv_iommu_igs_modes riscv_iommu_igs_mode; struct RISCVIOMMUState { /*< private >*/ @@ -85,6 +88,8 @@ struct RISCVIOMMUState { void riscv_iommu_pci_setup_iommu(RISCVIOMMUState *iommu, PCIBus *bus, Error **errp); +void riscv_iommu_set_cap_igs(RISCVIOMMUState *s, riscv_iommu_igs_mode mode); +void riscv_iommu_reset(RISCVIOMMUState *s); /* private helpers */ diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index e73479a943..bc9ffdd2d4 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -33,7 +33,6 @@ static const Property riscv_harts_props[] = { DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec, DEFAULT_RSTVEC), - DEFINE_PROP_END_OF_LIST(), }; static void riscv_harts_cpu_reset(void *opaque) diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 407bf51ff1..73d3b74281 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -78,6 +78,7 @@ static void sifive_e_machine_init(MachineState *machine) SiFiveEState *s = RISCV_E_MACHINE(machine); MemoryRegion *sys_mem = get_system_memory(); int i; + RISCVBootInfo boot_info; if (machine->ram_size != mc->default_ram_size) { char *sz = size_to_str(mc->default_ram_size); @@ -113,8 +114,9 @@ static void sifive_e_machine_init(MachineState *machine) rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec), memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory); + riscv_boot_info_init(&boot_info, &s->soc.cpus); if (machine->kernel_filename) { - riscv_load_kernel(machine, &s->soc.cpus, + riscv_load_kernel(machine, &boot_info, memmap[SIFIVE_E_DEV_DTIM].base, false, NULL); } diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 506779db7c..9a20bcbf7f 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -518,13 +518,15 @@ static void sifive_u_machine_init(MachineState *machine) target_ulong firmware_end_addr, kernel_start_addr; const char *firmware_name; uint32_t start_addr_hi32 = 0x00000000; + uint32_t fdt_load_addr_hi32 = 0x00000000; int i; - uint32_t fdt_load_addr; + uint64_t fdt_load_addr; uint64_t kernel_entry; DriveInfo *dinfo; BlockBackend *blk; DeviceState *flash_dev, *sd_dev, *card_dev; qemu_irq flash_cs, sd_cs; + RISCVBootInfo boot_info; /* Initialize SoC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, TYPE_RISCV_U_SOC); @@ -590,12 +592,13 @@ static void sifive_u_machine_init(MachineState *machine) firmware_end_addr = riscv_find_and_load_firmware(machine, firmware_name, &start_addr, NULL); + riscv_boot_info_init(&boot_info, &s->soc.u_cpus); if (machine->kernel_filename) { - kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc.u_cpus, + kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr); - - kernel_entry = riscv_load_kernel(machine, &s->soc.u_cpus, - kernel_start_addr, true, NULL); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, + true, NULL); + kernel_entry = boot_info.image_low_addr; } else { /* * If dynamic firmware is used, it doesn't know where is the next mode @@ -606,11 +609,12 @@ static void sifive_u_machine_init(MachineState *machine) fdt_load_addr = riscv_compute_fdt_addr(memmap[SIFIVE_U_DEV_DRAM].base, memmap[SIFIVE_U_DEV_DRAM].size, - machine); + machine, &boot_info); riscv_load_fdt(fdt_load_addr, machine->fdt); if (!riscv_is_32bit(&s->soc.u_cpus)) { start_addr_hi32 = (uint64_t)start_addr >> 32; + fdt_load_addr_hi32 = fdt_load_addr >> 32; } /* reset vector */ @@ -625,7 +629,7 @@ static void sifive_u_machine_init(MachineState *machine) start_addr, /* start: .dword */ start_addr_hi32, fdt_load_addr, /* fdt_laddr: .dword */ - 0x00000000, + fdt_load_addr_hi32, 0x00000000, /* fw_dyn: */ }; @@ -939,7 +943,6 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp) static const Property sifive_u_soc_props[] = { DEFINE_PROP_UINT32("serial", SiFiveUSoCState, serial, OTP_SERIAL), DEFINE_PROP_STRING("cpu-type", SiFiveUSoCState, cpu_type), - DEFINE_PROP_END_OF_LIST() }; static void sifive_u_soc_class_init(ObjectClass *oc, void *data) diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 586168b6ef..74a20016f1 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -201,11 +201,12 @@ static void spike_board_init(MachineState *machine) hwaddr firmware_load_addr = memmap[SPIKE_DRAM].base; target_ulong kernel_start_addr; char *firmware_name; - uint32_t fdt_load_addr; + uint64_t fdt_load_addr; uint64_t kernel_entry; char *soc_name; int i, base_hartid, hart_count; bool htif_custom_base = false; + RISCVBootInfo boot_info; /* Check socket count limit */ if (SPIKE_SOCKETS_MAX < riscv_socket_count(machine)) { @@ -300,13 +301,14 @@ static void spike_board_init(MachineState *machine) create_fdt(s, memmap, riscv_is_32bit(&s->soc[0]), htif_custom_base); /* Load kernel */ + riscv_boot_info_init(&boot_info, &s->soc[0]); if (machine->kernel_filename) { - kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], + kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr); - kernel_entry = riscv_load_kernel(machine, &s->soc[0], - kernel_start_addr, - true, htif_symbol_callback); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, + true, htif_symbol_callback); + kernel_entry = boot_info.image_low_addr; } else { /* * If dynamic firmware is used, it doesn't know where is the next mode @@ -317,7 +319,7 @@ static void spike_board_init(MachineState *machine) fdt_load_addr = riscv_compute_fdt_addr(memmap[SPIKE_DRAM].base, memmap[SPIKE_DRAM].size, - machine); + machine, &boot_info); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ diff --git a/hw/riscv/trace-events b/hw/riscv/trace-events index 0527c56c91..7bcbb03d08 100644 --- a/hw/riscv/trace-events +++ b/hw/riscv/trace-events @@ -15,3 +15,7 @@ riscv_iommu_icvec_write(uint32_t orig, uint32_t actual) "ICVEC write: incoming 0 riscv_iommu_ats(const char *id, unsigned b, unsigned d, unsigned f, uint64_t iova) "%s: translate request %04x:%02x.%u iova: 0x%"PRIx64 riscv_iommu_ats_inval(const char *id) "%s: dev-iotlb invalidate" riscv_iommu_ats_prgr(const char *id) "%s: dev-iotlb page request group response" +riscv_iommu_sys_irq_sent(uint32_t vector) "IRQ sent to vector %u" +riscv_iommu_sys_msi_sent(uint32_t vector, uint64_t msi_addr, uint32_t msi_data, uint32_t result) "MSI sent to vector %u msi_addr 0x%"PRIx64" msi_data 0x%x result %u" +riscv_iommu_sys_reset_hold(int reset_type) "reset type %d" +riscv_iommu_pci_reset_hold(int reset_type) "reset type %d" diff --git a/hw/riscv/virt-acpi-build.c b/hw/riscv/virt-acpi-build.c index 825bd321ea..1ad6800508 100644 --- a/hw/riscv/virt-acpi-build.c +++ b/hw/riscv/virt-acpi-build.c @@ -200,14 +200,15 @@ acpi_dsdt_add_uart(Aml *scope, const MemMapEntry *uart_memmap, /* * Serial Port Console Redirection Table (SPCR) - * Rev: 1.07 + * Rev: 1.10 */ static void spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s) { + const char name[] = "."; AcpiSpcrData serial = { - .interface_type = 0, /* 16550 compatible */ + .interface_type = 0x12, /* 16550 compatible */ .base_addr.id = AML_AS_SYSTEM_MEMORY, .base_addr.width = 32, .base_addr.offset = 0, @@ -229,9 +230,14 @@ spcr_setup(GArray *table_data, BIOSLinker *linker, RISCVVirtState *s) .pci_function = 0, .pci_flags = 0, .pci_segment = 0, + .uart_clk_freq = 0, + .precise_baudrate = 0, + .namespace_string_length = sizeof(name), + .namespace_string_offset = 88, }; - build_spcr(table_data, linker, &serial, 2, s->oem_id, s->oem_table_id); + build_spcr(table_data, linker, &serial, 4, s->oem_id, s->oem_table_id, + name); } /* RHCT Node[N] starts at offset 56 */ diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 80eda67f39..c792ab9c35 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -33,6 +33,7 @@ #include "target/riscv/pmu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/iommu.h" +#include "hw/riscv/riscv-iommu-bits.h" #include "hw/riscv/virt.h" #include "hw/riscv/boot.h" #include "hw/riscv/numa.h" @@ -58,9 +59,18 @@ #include "hw/virtio/virtio-iommu.h" /* KVM AIA only supports APLIC MSI. APLIC Wired is always emulated by QEMU. */ -static bool virt_use_kvm_aia(RISCVVirtState *s) +static bool virt_use_kvm_aia_aplic_imsic(RISCVVirtAIAType aia_type) { - return kvm_irqchip_in_kernel() && s->aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; + bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; + + return riscv_is_kvm_aia_aplic_imsic(msimode); +} + +static bool virt_use_emulated_aplic(RISCVVirtAIAType aia_type) +{ + bool msimode = aia_type == VIRT_AIA_TYPE_APLIC_IMSIC; + + return riscv_use_emulated_aplic(msimode); } static bool virt_aclint_allowed(void) @@ -76,6 +86,7 @@ static const MemMapEntry virt_memmap[] = { [VIRT_CLINT] = { 0x2000000, 0x10000 }, [VIRT_ACLINT_SSWI] = { 0x2F00000, 0x4000 }, [VIRT_PCIE_PIO] = { 0x3000000, 0x10000 }, + [VIRT_IOMMU_SYS] = { 0x3010000, 0x1000 }, [VIRT_PLATFORM_BUS] = { 0x4000000, 0x2000000 }, [VIRT_PLIC] = { 0xc000000, VIRT_PLIC_SIZE(VIRT_CPUS_MAX * 2) }, [VIRT_APLIC_M] = { 0xc000000, APLIC_SIZE(VIRT_CPUS_MAX) }, @@ -775,12 +786,19 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, *msi_pcie_phandle = msi_s_phandle; } - /* KVM AIA only has one APLIC instance */ - if (kvm_enabled() && virt_use_kvm_aia(s)) { + /* + * With KVM AIA aplic-imsic, using an irqchip without split + * mode, we'll use only one APLIC instance. + */ + if (!virt_use_emulated_aplic(s->aia_type)) { create_fdt_socket_aplic(s, memmap, 0, msi_m_phandle, msi_s_phandle, phandle, &intc_phandles[0], xplic_phandles, ms->smp.cpus); + + *irq_mmio_phandle = xplic_phandles[0]; + *irq_virtio_phandle = xplic_phandles[0]; + *irq_pcie_phandle = xplic_phandles[0]; } else { phandle_pos = ms->smp.cpus; for (socket = (socket_count - 1); socket >= 0; socket--) { @@ -798,13 +816,7 @@ static void create_fdt_sockets(RISCVVirtState *s, const MemMapEntry *memmap, s->soc[socket].num_harts); } } - } - if (kvm_enabled() && virt_use_kvm_aia(s)) { - *irq_mmio_phandle = xplic_phandles[0]; - *irq_virtio_phandle = xplic_phandles[0]; - *irq_pcie_phandle = xplic_phandles[0]; - } else { for (socket = 0; socket < socket_count; socket++) { if (socket == 0) { *irq_mmio_phandle = xplic_phandles[socket]; @@ -853,7 +865,8 @@ static void create_fdt_virtio(RISCVVirtState *s, const MemMapEntry *memmap, static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, uint32_t irq_pcie_phandle, - uint32_t msi_pcie_phandle) + uint32_t msi_pcie_phandle, + uint32_t iommu_sys_phandle) { g_autofree char *name = NULL; MachineState *ms = MACHINE(s); @@ -887,6 +900,12 @@ static void create_fdt_pcie(RISCVVirtState *s, const MemMapEntry *memmap, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.base, 2, virt_high_pcie_memmap.size); + if (virt_is_iommu_sys_enabled(s)) { + qemu_fdt_setprop_cells(ms->fdt, name, "iommu-map", + 0, iommu_sys_phandle, 0, 0, 0, + iommu_sys_phandle, 0, 0xffff); + } + create_pcie_irq_map(s, ms->fdt, name, irq_pcie_phandle); } @@ -1033,6 +1052,47 @@ static void create_fdt_virtio_iommu(RISCVVirtState *s, uint16_t bdf) bdf + 1, iommu_phandle, bdf + 1, 0xffff - bdf); } +static void create_fdt_iommu_sys(RISCVVirtState *s, uint32_t irq_chip, + uint32_t msi_phandle, + uint32_t *iommu_sys_phandle) +{ + const char comp[] = "riscv,iommu"; + void *fdt = MACHINE(s)->fdt; + uint32_t iommu_phandle; + g_autofree char *iommu_node = NULL; + hwaddr addr = s->memmap[VIRT_IOMMU_SYS].base; + hwaddr size = s->memmap[VIRT_IOMMU_SYS].size; + uint32_t iommu_irq_map[RISCV_IOMMU_INTR_COUNT] = { + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_CQ, + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_FQ, + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PM, + IOMMU_SYS_IRQ + RISCV_IOMMU_INTR_PQ, + }; + + iommu_node = g_strdup_printf("/soc/iommu@%x", + (unsigned int) s->memmap[VIRT_IOMMU_SYS].base); + iommu_phandle = qemu_fdt_alloc_phandle(fdt); + qemu_fdt_add_subnode(fdt, iommu_node); + + qemu_fdt_setprop(fdt, iommu_node, "compatible", comp, sizeof(comp)); + qemu_fdt_setprop_cell(fdt, iommu_node, "#iommu-cells", 1); + qemu_fdt_setprop_cell(fdt, iommu_node, "phandle", iommu_phandle); + + qemu_fdt_setprop_cells(fdt, iommu_node, "reg", + addr >> 32, addr, size >> 32, size); + qemu_fdt_setprop_cell(fdt, iommu_node, "interrupt-parent", irq_chip); + + qemu_fdt_setprop_cells(fdt, iommu_node, "interrupts", + iommu_irq_map[0], FDT_IRQ_TYPE_EDGE_LOW, + iommu_irq_map[1], FDT_IRQ_TYPE_EDGE_LOW, + iommu_irq_map[2], FDT_IRQ_TYPE_EDGE_LOW, + iommu_irq_map[3], FDT_IRQ_TYPE_EDGE_LOW); + + qemu_fdt_setprop_cell(fdt, iommu_node, "msi-parent", msi_phandle); + + *iommu_sys_phandle = iommu_phandle; +} + static void create_fdt_iommu(RISCVVirtState *s, uint16_t bdf) { const char comp[] = "riscv,pci-iommu"; @@ -1061,6 +1121,7 @@ static void finalize_fdt(RISCVVirtState *s) { uint32_t phandle = 1, irq_mmio_phandle = 1, msi_pcie_phandle = 1; uint32_t irq_pcie_phandle = 1, irq_virtio_phandle = 1; + uint32_t iommu_sys_phandle = 1; create_fdt_sockets(s, virt_memmap, &phandle, &irq_mmio_phandle, &irq_pcie_phandle, &irq_virtio_phandle, @@ -1068,7 +1129,12 @@ static void finalize_fdt(RISCVVirtState *s) create_fdt_virtio(s, virt_memmap, irq_virtio_phandle); - create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle); + if (virt_is_iommu_sys_enabled(s)) { + create_fdt_iommu_sys(s, irq_mmio_phandle, msi_pcie_phandle, + &iommu_sys_phandle); + } + create_fdt_pcie(s, virt_memmap, irq_pcie_phandle, msi_pcie_phandle, + iommu_sys_phandle); create_fdt_reset(s, virt_memmap, &phandle); @@ -1234,7 +1300,7 @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, int base_hartid, int hart_count) { int i; - hwaddr addr; + hwaddr addr = 0; uint32_t guest_bits; DeviceState *aplic_s = NULL; DeviceState *aplic_m = NULL; @@ -1284,6 +1350,10 @@ static DeviceState *virt_create_aia(RISCVVirtAIAType aia_type, int aia_guests, VIRT_IRQCHIP_NUM_PRIO_BITS, msimode, false, aplic_m); + if (kvm_enabled() && msimode) { + riscv_aplic_set_kvm_msicfgaddr(RISCV_APLIC(aplic_s), addr); + } + return kvm_enabled() ? aplic_s : aplic_m; } @@ -1364,6 +1434,7 @@ static void virt_machine_done(Notifier *notifier, void *data) uint64_t fdt_load_addr; uint64_t kernel_entry = 0; BlockBackend *pflash_blk0; + RISCVBootInfo boot_info; /* * An user provided dtb must include everything, including @@ -1412,17 +1483,19 @@ static void virt_machine_done(Notifier *notifier, void *data) } } + riscv_boot_info_init(&boot_info, &s->soc[0]); + if (machine->kernel_filename && !kernel_entry) { - kernel_start_addr = riscv_calc_kernel_start_addr(&s->soc[0], + kernel_start_addr = riscv_calc_kernel_start_addr(&boot_info, firmware_end_addr); - - kernel_entry = riscv_load_kernel(machine, &s->soc[0], - kernel_start_addr, true, NULL); + riscv_load_kernel(machine, &boot_info, kernel_start_addr, + true, NULL); + kernel_entry = boot_info.image_low_addr; } fdt_load_addr = riscv_compute_fdt_addr(memmap[VIRT_DRAM].base, memmap[VIRT_DRAM].size, - machine); + machine, &boot_info); riscv_load_fdt(fdt_load_addr, machine->fdt); /* load the reset vector */ @@ -1565,7 +1638,7 @@ static void virt_machine_init(MachineState *machine) } } - if (kvm_enabled() && virt_use_kvm_aia(s)) { + if (kvm_enabled() && virt_use_kvm_aia_aplic_imsic(s->aia_type)) { kvm_riscv_aia_create(machine, IMSIC_MMIO_GROUP_MIN_SHIFT, VIRT_IRQCHIP_NUM_SOURCES, VIRT_IRQCHIP_NUM_MSIS, memmap[VIRT_APLIC_S].base, @@ -1648,6 +1721,22 @@ static void virt_machine_init(MachineState *machine) create_fdt(s, memmap); } + if (virt_is_iommu_sys_enabled(s)) { + DeviceState *iommu_sys = qdev_new(TYPE_RISCV_IOMMU_SYS); + + object_property_set_uint(OBJECT(iommu_sys), "addr", + s->memmap[VIRT_IOMMU_SYS].base, + &error_fatal); + object_property_set_uint(OBJECT(iommu_sys), "base-irq", + IOMMU_SYS_IRQ, + &error_fatal); + object_property_set_link(OBJECT(iommu_sys), "irqchip", + OBJECT(mmio_irqchip), + &error_fatal); + + sysbus_realize_and_unref(SYS_BUS_DEVICE(iommu_sys), &error_fatal); + } + s->machine_done.notify = virt_machine_done; qemu_add_machine_init_done_notifier(&s->machine_done); } @@ -1661,6 +1750,7 @@ static void virt_machine_instance_init(Object *obj) s->oem_id = g_strndup(ACPI_BUILD_APPNAME6, 6); s->oem_table_id = g_strndup(ACPI_BUILD_APPNAME8, 8); s->acpi = ON_OFF_AUTO_AUTO; + s->iommu_sys = ON_OFF_AUTO_AUTO; } static char *virt_get_aia_guests(Object *obj, Error **errp) @@ -1733,6 +1823,28 @@ static void virt_set_aclint(Object *obj, bool value, Error **errp) s->have_aclint = value; } +bool virt_is_iommu_sys_enabled(RISCVVirtState *s) +{ + return s->iommu_sys == ON_OFF_AUTO_ON; +} + +static void virt_get_iommu_sys(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); + OnOffAuto iommu_sys = s->iommu_sys; + + visit_type_OnOffAuto(v, name, &iommu_sys, errp); +} + +static void virt_set_iommu_sys(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + RISCVVirtState *s = RISCV_VIRT_MACHINE(obj); + + visit_type_OnOffAuto(v, name, &s->iommu_sys, errp); +} + bool virt_is_acpi_enabled(RISCVVirtState *s) { return s->acpi != ON_OFF_AUTO_OFF; @@ -1759,10 +1871,12 @@ static HotplugHandler *virt_machine_get_hotplug_handler(MachineState *machine, DeviceState *dev) { MachineClass *mc = MACHINE_GET_CLASS(machine); + RISCVVirtState *s = RISCV_VIRT_MACHINE(machine); if (device_is_dynamic_sysbus(mc, dev) || object_dynamic_cast(OBJECT(dev), TYPE_VIRTIO_IOMMU_PCI) || object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { + s->iommu_sys = ON_OFF_AUTO_OFF; return HOTPLUG_HANDLER(machine); } @@ -1789,6 +1903,7 @@ static void virt_machine_device_plug_cb(HotplugHandler *hotplug_dev, if (object_dynamic_cast(OBJECT(dev), TYPE_RISCV_IOMMU_PCI)) { create_fdt_iommu(s, pci_get_bdf(PCI_DEVICE(dev))); + s->iommu_sys = ON_OFF_AUTO_OFF; } } @@ -1851,6 +1966,12 @@ static void virt_machine_class_init(ObjectClass *oc, void *data) NULL, NULL); object_class_property_set_description(oc, "acpi", "Enable ACPI"); + + object_class_property_add(oc, "iommu-sys", "OnOffAuto", + virt_get_iommu_sys, virt_set_iommu_sys, + NULL, NULL); + object_class_property_set_description(oc, "iommu-sys", + "Enable IOMMU platform device"); } static const TypeInfo virt_machine_typeinfo = { diff --git a/hw/rtc/allwinner-rtc.c b/hw/rtc/allwinner-rtc.c index be591f77ab..a19e4310bb 100644 --- a/hw/rtc/allwinner-rtc.c +++ b/hw/rtc/allwinner-rtc.c @@ -313,7 +313,6 @@ static const VMStateDescription allwinner_rtc_vmstate = { static const Property allwinner_rtc_properties[] = { DEFINE_PROP_INT32("base-year", AwRtcState, base_year, 0), - DEFINE_PROP_END_OF_LIST(), }; static void allwinner_rtc_class_init(ObjectClass *klass, void *data) diff --git a/hw/rtc/goldfish_rtc.c b/hw/rtc/goldfish_rtc.c index 425c8ba0c2..fa1d9051f4 100644 --- a/hw/rtc/goldfish_rtc.c +++ b/hw/rtc/goldfish_rtc.c @@ -289,7 +289,6 @@ static void goldfish_rtc_realize(DeviceState *d, Error **errp) static const Property goldfish_rtc_properties[] = { DEFINE_PROP_BOOL("big-endian", GoldfishRTCState, big_endian, false), - DEFINE_PROP_END_OF_LIST(), }; static void goldfish_rtc_class_init(ObjectClass *klass, void *data) diff --git a/hw/rtc/m48t59-isa.c b/hw/rtc/m48t59-isa.c index 51f80d27ef..38bc8dcf10 100644 --- a/hw/rtc/m48t59-isa.c +++ b/hw/rtc/m48t59-isa.c @@ -81,7 +81,6 @@ static const Property m48t59_isa_properties[] = { DEFINE_PROP_INT32("base-year", M48txxISAState, state.base_year, 0), DEFINE_PROP_UINT32("iobase", M48txxISAState, io_base, 0x74), DEFINE_PROP_UINT8("irq", M48txxISAState, isairq, 8), - DEFINE_PROP_END_OF_LIST(), }; static void m48t59_reset_isa(DeviceState *d) diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c index 4c578e7c54..c9bd6f878f 100644 --- a/hw/rtc/m48t59.c +++ b/hw/rtc/m48t59.c @@ -620,7 +620,6 @@ static void m48txx_sysbus_toggle_lock(Nvram *obj, int lock) static const Property m48t59_sysbus_properties[] = { DEFINE_PROP_INT32("base-year", M48txxSysBusState, state.base_year, 0), - DEFINE_PROP_END_OF_LIST(), }; static void m48txx_sysbus_class_init(ObjectClass *klass, void *data) diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index 2103f774e9..e322fc2ffb 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -966,7 +966,6 @@ static const Property mc146818rtc_properties[] = { DEFINE_PROP_UINT8("irq", MC146818RtcState, isairq, RTC_ISA_IRQ), DEFINE_PROP_LOSTTICKPOLICY("lost_tick_policy", MC146818RtcState, lost_tick_policy, LOST_TICK_POLICY_DISCARD), - DEFINE_PROP_END_OF_LIST(), }; static void rtc_reset_enter(Object *obj, ResetType type) diff --git a/hw/rtc/pl031.c b/hw/rtc/pl031.c index a037bdbf42..ed439bd3ad 100644 --- a/hw/rtc/pl031.c +++ b/hw/rtc/pl031.c @@ -330,7 +330,6 @@ static const Property pl031_properties[] = { */ DEFINE_PROP_BOOL("migrate-tick-offset", PL031State, migrate_tick_offset, true), - DEFINE_PROP_END_OF_LIST() }; static void pl031_class_init(ObjectClass *klass, void *data) diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index f421de4e6f..8c1d1023ed 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -262,7 +262,6 @@ static const Property rx62n_properties[] = { MemoryRegion *), DEFINE_PROP_BOOL("load-kernel", RX62NState, kernel, false), DEFINE_PROP_UINT32("xtal-frequency-hz", RX62NState, xtal_freq_hz, 0), - DEFINE_PROP_END_OF_LIST(), }; static void rx62n_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/3270-ccw.c b/hw/s390x/3270-ccw.c index 69e6783ade..3a8930dfd1 100644 --- a/hw/s390x/3270-ccw.c +++ b/hw/s390x/3270-ccw.c @@ -150,15 +150,10 @@ out_err: g_free(sch); } -static Property emulated_ccw_3270_properties[] = { - DEFINE_PROP_END_OF_LIST(), -}; - static void emulated_ccw_3270_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - device_class_set_props(dc, emulated_ccw_3270_properties); dc->realize = emulated_ccw_3270_realize; dc->hotpluggable = false; set_bit(DEVICE_CATEGORY_DISPLAY, dc->categories); diff --git a/hw/s390x/ccw-device.c b/hw/s390x/ccw-device.c index 0d10c3ed55..494faebb5a 100644 --- a/hw/s390x/ccw-device.c +++ b/hw/s390x/ccw-device.c @@ -85,7 +85,6 @@ static const Property ccw_device_properties[] = { DEFINE_PROP_CSS_DEV_ID("devno", CcwDevice, devno), DEFINE_PROP_CSS_DEV_ID_RO("dev_id", CcwDevice, dev_id), DEFINE_PROP_CSS_DEV_ID_RO("subch_id", CcwDevice, subch_id), - DEFINE_PROP_END_OF_LIST(), }; static void ccw_device_reset_hold(Object *obj, ResetType type) diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c index 860a04a7da..04ab1f6402 100644 --- a/hw/s390x/css-bridge.c +++ b/hw/s390x/css-bridge.c @@ -123,7 +123,6 @@ VirtualCssBus *virtual_css_bus_init(void) static const Property virtual_css_bridge_properties[] = { DEFINE_PROP_BOOL("css_dev_path", VirtualCssBridge, css_dev_path, true), - DEFINE_PROP_END_OF_LIST(), }; static bool prop_get_true(Object *obj, Error **errp) diff --git a/hw/s390x/css.c b/hw/s390x/css.c index b2d5327dbf..4e27b2961b 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -2463,7 +2463,7 @@ void css_reset(void) static void get_css_devid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; CssDevId *dev_id = object_field_prop_ptr(obj, prop); char buffer[] = "xx.x.xxxx"; char *p = buffer; @@ -2492,7 +2492,7 @@ static void get_css_devid(Object *obj, Visitor *v, const char *name, static void set_css_devid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; CssDevId *dev_id = object_field_prop_ptr(obj, prop); char *str; int num, n1, n2; diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index f0275bf34c..3a946be7a5 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -299,7 +299,6 @@ static const Property s390_ipl_properties[] = { DEFINE_PROP_BOOL("enforce_bios", S390IPLState, enforce_bios, false), DEFINE_PROP_BOOL("iplbext_migration", S390IPLState, iplbext_migration, true), - DEFINE_PROP_END_OF_LIST(), }; static void s390_ipl_set_boot_menu(S390IPLState *ipl) diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index 1a507ea472..eead269cc2 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -1453,7 +1453,7 @@ static void s390_pci_device_reset(DeviceState *dev) static void s390_pci_get_fid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint32_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint32(v, name, ptr, errp); @@ -1463,7 +1463,7 @@ static void s390_pci_set_fid(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { S390PCIBusDevice *zpci = S390_PCI_DEVICE(obj); - Property *prop = opaque; + const Property *prop = opaque; uint32_t *ptr = object_field_prop_ptr(obj, prop); if (!visit_type_uint32(v, name, ptr, errp)) { @@ -1488,7 +1488,6 @@ static const Property s390_pci_device_properties[] = { DEFINE_PROP_BOOL("interpret", S390PCIBusDevice, interp, true), DEFINE_PROP_BOOL("forwarding-assist", S390PCIBusDevice, forwarding_assist, true), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription s390_pci_device_vmstate = { diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c index c6a4db5f7e..c853ab7e3d 100644 --- a/hw/s390x/s390-skeys.c +++ b/hw/s390x/s390-skeys.c @@ -477,7 +477,6 @@ static void s390_skeys_realize(DeviceState *dev, Error **errp) static const Property s390_skeys_props[] = { DEFINE_PROP_BOOL("migration-enabled", S390SKeysState, migration_enabled, true), - DEFINE_PROP_END_OF_LIST(), }; static void s390_skeys_class_init(ObjectClass *oc, void *data) diff --git a/hw/s390x/s390-stattrib.c b/hw/s390x/s390-stattrib.c index 6c69c01e1f..8e07acbddc 100644 --- a/hw/s390x/s390-stattrib.c +++ b/hw/s390x/s390-stattrib.c @@ -362,7 +362,6 @@ static void s390_stattrib_realize(DeviceState *dev, Error **errp) static const Property s390_stattrib_props[] = { DEFINE_PROP_BOOL("migration-enabled", S390StAttribState, migration_enabled, true), - DEFINE_PROP_END_OF_LIST(), }; static void s390_stattrib_class_init(ObjectClass *oc, void *data) diff --git a/hw/s390x/vhost-scsi-ccw.c b/hw/s390x/vhost-scsi-ccw.c index 0be0f8a82c..e6bf0c55bc 100644 --- a/hw/s390x/vhost-scsi-ccw.c +++ b/hw/s390x/vhost-scsi-ccw.c @@ -44,7 +44,6 @@ static void vhost_ccw_scsi_instance_init(Object *obj) static const Property vhost_ccw_scsi_properties[] = { DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_ccw_scsi_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/vhost-user-fs-ccw.c b/hw/s390x/vhost-user-fs-ccw.c index 934378aaec..6a9654d77b 100644 --- a/hw/s390x/vhost-user-fs-ccw.c +++ b/hw/s390x/vhost-user-fs-ccw.c @@ -28,7 +28,6 @@ static const Property vhost_user_fs_ccw_properties[] = { VIRTIO_CCW_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_user_fs_ccw_realize(VirtioCcwDevice *ccw_dev, Error **errp) diff --git a/hw/s390x/vhost-vsock-ccw.c b/hw/s390x/vhost-vsock-ccw.c index 3ba4008b4b..875ccf3485 100644 --- a/hw/s390x/vhost-vsock-ccw.c +++ b/hw/s390x/vhost-vsock-ccw.c @@ -25,7 +25,6 @@ struct VHostVSockCCWState { static const Property vhost_vsock_ccw_properties[] = { DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_vsock_ccw_realize(VirtioCcwDevice *ccw_dev, Error **errp) diff --git a/hw/s390x/virtio-ccw-9p.c b/hw/s390x/virtio-ccw-9p.c index c10b084d40..287ae2ba76 100644 --- a/hw/s390x/virtio-ccw-9p.c +++ b/hw/s390x/virtio-ccw-9p.c @@ -46,7 +46,6 @@ static const Property virtio_ccw_9p_properties[] = { VIRTIO_CCW_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_9p_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/virtio-ccw-balloon.c b/hw/s390x/virtio-ccw-balloon.c index bbbed494b3..1180efaf6d 100644 --- a/hw/s390x/virtio-ccw-balloon.c +++ b/hw/s390x/virtio-ccw-balloon.c @@ -51,7 +51,6 @@ static const Property virtio_ccw_balloon_properties[] = { VIRTIO_CCW_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_balloon_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/virtio-ccw-blk.c b/hw/s390x/virtio-ccw-blk.c index 3182851234..db9d442ffb 100644 --- a/hw/s390x/virtio-ccw-blk.c +++ b/hw/s390x/virtio-ccw-blk.c @@ -49,7 +49,6 @@ static const Property virtio_ccw_blk_properties[] = { DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), DEFINE_PROP_CCW_LOADPARM("loadparm", CcwDevice, loadparm), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_blk_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/virtio-ccw-crypto.c b/hw/s390x/virtio-ccw-crypto.c index b4cd7605c9..b693f87c70 100644 --- a/hw/s390x/virtio-ccw-crypto.c +++ b/hw/s390x/virtio-ccw-crypto.c @@ -49,7 +49,6 @@ static const Property virtio_ccw_crypto_properties[] = { VIRTIO_CCW_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_crypto_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/virtio-ccw-gpu.c b/hw/s390x/virtio-ccw-gpu.c index c44dc2d355..a6b14c25d9 100644 --- a/hw/s390x/virtio-ccw-gpu.c +++ b/hw/s390x/virtio-ccw-gpu.c @@ -47,7 +47,6 @@ static const Property virtio_ccw_gpu_properties[] = { VIRTIO_CCW_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_gpu_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/virtio-ccw-input.c b/hw/s390x/virtio-ccw-input.c index 040a9e04a9..6ca10d58ee 100644 --- a/hw/s390x/virtio-ccw-input.c +++ b/hw/s390x/virtio-ccw-input.c @@ -48,7 +48,6 @@ static const Property virtio_ccw_input_properties[] = { VIRTIO_CCW_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_input_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/virtio-ccw-net.c b/hw/s390x/virtio-ccw-net.c index c41d347034..80a5581baf 100644 --- a/hw/s390x/virtio-ccw-net.c +++ b/hw/s390x/virtio-ccw-net.c @@ -52,7 +52,6 @@ static const Property virtio_ccw_net_properties[] = { DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), DEFINE_PROP_CCW_LOADPARM("loadparm", CcwDevice, loadparm), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_net_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/virtio-ccw-rng.c b/hw/s390x/virtio-ccw-rng.c index c9a15c4eb6..ccd124ee91 100644 --- a/hw/s390x/virtio-ccw-rng.c +++ b/hw/s390x/virtio-ccw-rng.c @@ -48,7 +48,6 @@ static const Property virtio_ccw_rng_properties[] = { VIRTIO_CCW_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_rng_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/virtio-ccw-scsi.c b/hw/s390x/virtio-ccw-scsi.c index bec9a73518..bfcea3cfe7 100644 --- a/hw/s390x/virtio-ccw-scsi.c +++ b/hw/s390x/virtio-ccw-scsi.c @@ -58,7 +58,6 @@ static const Property virtio_ccw_scsi_properties[] = { VIRTIO_CCW_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_scsi_class_init(ObjectClass *klass, void *data) diff --git a/hw/s390x/virtio-ccw-serial.c b/hw/s390x/virtio-ccw-serial.c index 037d4f9db1..59743d1e25 100644 --- a/hw/s390x/virtio-ccw-serial.c +++ b/hw/s390x/virtio-ccw-serial.c @@ -58,7 +58,6 @@ static const Property virtio_ccw_serial_properties[] = { VIRTIO_CCW_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("max_revision", VirtioCcwDevice, max_rev, VIRTIO_CCW_MAX_REV), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_ccw_serial_class_init(ObjectClass *klass, void *data) diff --git a/hw/scsi/megasas.c b/hw/scsi/megasas.c index 70d444e093..9f3b30e6ce 100644 --- a/hw/scsi/megasas.c +++ b/hw/scsi/megasas.c @@ -2459,7 +2459,6 @@ static const Property megasas_properties_gen1[] = { DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO), DEFINE_PROP_BIT("use_jbod", MegasasState, flags, MEGASAS_FLAG_USE_JBOD, false), - DEFINE_PROP_END_OF_LIST(), }; static const Property megasas_properties_gen2[] = { @@ -2473,7 +2472,6 @@ static const Property megasas_properties_gen2[] = { DEFINE_PROP_ON_OFF_AUTO("msix", MegasasState, msix, ON_OFF_AUTO_AUTO), DEFINE_PROP_BIT("use_jbod", MegasasState, flags, MEGASAS_FLAG_USE_JBOD, false), - DEFINE_PROP_END_OF_LIST(), }; typedef struct MegasasInfo { @@ -2488,6 +2486,7 @@ typedef struct MegasasInfo { int osts; const VMStateDescription *vmsd; const Property *props; + size_t props_count; InterfaceInfo *interfaces; } MegasasInfo; @@ -2504,6 +2503,7 @@ static struct MegasasInfo megasas_devices[] = { .osts = MFI_1078_RM | 1, .vmsd = &vmstate_megasas_gen1, .props = megasas_properties_gen1, + .props_count = ARRAY_SIZE(megasas_properties_gen1), .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, @@ -2520,6 +2520,7 @@ static struct MegasasInfo megasas_devices[] = { .osts = MFI_GEN2_RM, .vmsd = &vmstate_megasas_gen2, .props = megasas_properties_gen2, + .props_count = ARRAY_SIZE(megasas_properties_gen2), .interfaces = (InterfaceInfo[]) { { INTERFACE_PCIE_DEVICE }, { } @@ -2546,7 +2547,7 @@ static void megasas_class_init(ObjectClass *oc, void *data) e->osts = info->osts; e->product_name = info->product_name; e->product_version = info->product_version; - device_class_set_props(dc, info->props); + device_class_set_props_n(dc, info->props, info->props_count); device_class_set_legacy_reset(dc, megasas_scsi_reset); dc->vmsd = info->vmsd; set_bit(DEVICE_CATEGORY_STORAGE, dc->categories); diff --git a/hw/scsi/mptsas.c b/hw/scsi/mptsas.c index 8397c93bf2..ba7a7d0770 100644 --- a/hw/scsi/mptsas.c +++ b/hw/scsi/mptsas.c @@ -1414,7 +1414,6 @@ static const Property mptsas_properties[] = { DEFINE_PROP_UINT64("sas_address", MPTSASState, sas_addr, 0), /* TODO: test MSI support under Windows */ DEFINE_PROP_ON_OFF_AUTO("msi", MPTSASState, msi, ON_OFF_AUTO_AUTO), - DEFINE_PROP_END_OF_LIST(), }; static void mptsas1068_class_init(ObjectClass *oc, void *data) diff --git a/hw/scsi/scsi-bus.c b/hw/scsi/scsi-bus.c index 5bfdcfca45..7d4546800f 100644 --- a/hw/scsi/scsi-bus.c +++ b/hw/scsi/scsi-bus.c @@ -1947,7 +1947,6 @@ static const Property scsi_props[] = { DEFINE_PROP_UINT32("channel", SCSIDevice, channel, 0), DEFINE_PROP_UINT32("scsi-id", SCSIDevice, id, -1), DEFINE_PROP_UINT32("lun", SCSIDevice, lun, -1), - DEFINE_PROP_END_OF_LIST(), }; static void scsi_device_class_init(ObjectClass *klass, void *data) diff --git a/hw/scsi/scsi-disk.c b/hw/scsi/scsi-disk.c index 33c169b013..e7f738b484 100644 --- a/hw/scsi/scsi-disk.c +++ b/hw/scsi/scsi-disk.c @@ -3227,7 +3227,6 @@ static const Property scsi_hd_properties[] = { quirks, SCSI_DISK_QUIRK_MODE_PAGE_VENDOR_SPECIFIC_APPLE, 0), DEFINE_BLOCK_CHS_PROPERTIES(SCSIDiskState, qdev.conf), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_scsi_disk_state = { @@ -3285,7 +3284,6 @@ static const Property scsi_cd_properties[] = { 0), DEFINE_PROP_BIT("quirk_mode_page_truncated", SCSIDiskState, quirks, SCSI_DISK_QUIRK_MODE_PAGE_TRUNCATED, 0), - DEFINE_PROP_END_OF_LIST(), }; static void scsi_cd_class_initfn(ObjectClass *klass, void *data) @@ -3323,7 +3321,6 @@ static const Property scsi_block_properties[] = { -1), DEFINE_PROP_UINT32("io_timeout", SCSIDiskState, qdev.io_timeout, DEFAULT_IO_TIMEOUT), - DEFINE_PROP_END_OF_LIST(), }; static void scsi_block_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/scsi/scsi-generic.c b/hw/scsi/scsi-generic.c index 5748060a9a..6566720064 100644 --- a/hw/scsi/scsi-generic.c +++ b/hw/scsi/scsi-generic.c @@ -777,7 +777,6 @@ static const Property scsi_generic_properties[] = { DEFINE_PROP_BOOL("share-rw", SCSIDevice, conf.share_rw, false), DEFINE_PROP_UINT32("io_timeout", SCSIDevice, io_timeout, DEFAULT_IO_TIMEOUT), - DEFINE_PROP_END_OF_LIST(), }; static int scsi_generic_parse_cdb(SCSIDevice *dev, SCSICommand *cmd, diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c index 7c55e4d40f..6962194eaa 100644 --- a/hw/scsi/spapr_vscsi.c +++ b/hw/scsi/spapr_vscsi.c @@ -1252,7 +1252,6 @@ static int spapr_vscsi_devnode(SpaprVioDevice *dev, void *fdt, int node_off) static const Property spapr_vscsi_properties[] = { DEFINE_SPAPR_PROPERTIES(VSCSIState, vdev), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_spapr_vscsi = { diff --git a/hw/scsi/vhost-scsi.c b/hw/scsi/vhost-scsi.c index 4bd6d2d7a8..8039d13fd9 100644 --- a/hw/scsi/vhost-scsi.c +++ b/hw/scsi/vhost-scsi.c @@ -362,7 +362,6 @@ static const Property vhost_scsi_properties[] = { DEFINE_PROP_BOOL("migratable", VHostSCSICommon, migratable, false), DEFINE_PROP_BOOL("worker_per_virtqueue", VirtIOSCSICommon, conf.worker_per_virtqueue, false), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_scsi_class_init(ObjectClass *klass, void *data) diff --git a/hw/scsi/vhost-user-scsi.c b/hw/scsi/vhost-user-scsi.c index 8b84f9508e..adb41b9816 100644 --- a/hw/scsi/vhost-user-scsi.c +++ b/hw/scsi/vhost-user-scsi.c @@ -360,7 +360,6 @@ static const Property vhost_user_scsi_properties[] = { DEFINE_PROP_BIT64("t10_pi", VHostSCSICommon, host_features, VIRTIO_SCSI_F_T10_PI, false), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_user_scsi_reset(VirtIODevice *vdev) diff --git a/hw/scsi/virtio-scsi.c b/hw/scsi/virtio-scsi.c index e4d01e4adb..23516995dc 100644 --- a/hw/scsi/virtio-scsi.c +++ b/hw/scsi/virtio-scsi.c @@ -1302,7 +1302,6 @@ static const Property virtio_scsi_properties[] = { VIRTIO_SCSI_F_CHANGE, true), DEFINE_PROP_LINK("iothread", VirtIOSCSI, parent_obj.conf.iothread, TYPE_IOTHREAD, IOThread *), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_virtio_scsi = { diff --git a/hw/scsi/vmw_pvscsi.c b/hw/scsi/vmw_pvscsi.c index 46cec531cc..f07e377cb8 100644 --- a/hw/scsi/vmw_pvscsi.c +++ b/hw/scsi/vmw_pvscsi.c @@ -1302,7 +1302,6 @@ static const Property pvscsi_properties[] = { PVSCSI_COMPAT_OLD_PCI_CONFIGURATION_BIT, false), DEFINE_PROP_BIT("x-disable-pcie", PVSCSIState, compat_flags, PVSCSI_COMPAT_DISABLE_PCIE_BIT, false), - DEFINE_PROP_END_OF_LIST(), }; static void pvscsi_realize(DeviceState *qdev, Error **errp) diff --git a/hw/sd/allwinner-sdhost.c b/hw/sd/allwinner-sdhost.c index f46213dfc7..ee5c5c78a8 100644 --- a/hw/sd/allwinner-sdhost.c +++ b/hw/sd/allwinner-sdhost.c @@ -811,7 +811,6 @@ static const VMStateDescription vmstate_allwinner_sdhost = { static const Property allwinner_sdhost_properties[] = { DEFINE_PROP_LINK("dma-memory", AwSdHostState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void allwinner_sdhost_init(Object *obj) diff --git a/hw/sd/aspeed_sdhci.c b/hw/sd/aspeed_sdhci.c index 99703f1842..12cbbae5e7 100644 --- a/hw/sd/aspeed_sdhci.c +++ b/hw/sd/aspeed_sdhci.c @@ -206,7 +206,6 @@ static const VMStateDescription vmstate_aspeed_sdhci = { static const Property aspeed_sdhci_properties[] = { DEFINE_PROP_UINT8("num-slots", AspeedSDHCIState, num_slots, 0), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_sdhci_class_init(ObjectClass *classp, void *data) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 5b7b07194a..0330d432fd 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -2800,19 +2800,16 @@ static void emmc_realize(DeviceState *dev, Error **errp) static const Property sdmmc_common_properties[] = { DEFINE_PROP_DRIVE("drive", SDState, blk), - DEFINE_PROP_END_OF_LIST() }; static const Property sd_properties[] = { DEFINE_PROP_UINT8("spec_version", SDState, spec_version, SD_PHY_SPECv3_01_VERS), - DEFINE_PROP_END_OF_LIST() }; static const Property emmc_properties[] = { DEFINE_PROP_UINT64("boot-partition-size", SDState, boot_part_size, 0), DEFINE_PROP_UINT8("boot-config", SDState, boot_config, 0x0), - DEFINE_PROP_END_OF_LIST() }; static void sdmmc_common_class_init(ObjectClass *klass, void *data) diff --git a/hw/sd/sdhci-pci.c b/hw/sd/sdhci-pci.c index 83892a7a15..5268c0dee5 100644 --- a/hw/sd/sdhci-pci.c +++ b/hw/sd/sdhci-pci.c @@ -24,7 +24,6 @@ static const Property sdhci_pci_properties[] = { DEFINE_SDHCI_COMMON_PROPERTIES(SDHCIState), - DEFINE_PROP_END_OF_LIST(), }; static void sdhci_pci_realize(PCIDevice *dev, Error **errp) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index 11a298f4b8..299cd4bc1b 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -1550,7 +1550,6 @@ static const Property sdhci_sysbus_properties[] = { false), DEFINE_PROP_LINK("dma", SDHCIState, dma_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void sdhci_sysbus_init(Object *obj) diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index 470b6877cd..217a69e4d5 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -732,15 +732,10 @@ static void prom_realize(DeviceState *ds, Error **errp) sysbus_init_mmio(dev, &s->prom); } -static Property prom_properties[] = { - {/* end of property list */}, -}; - static void prom_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - device_class_set_props(dc, prom_properties); dc->realize = prom_realize; } diff --git a/hw/sparc/sun4m_iommu.c b/hw/sparc/sun4m_iommu.c index 3d6fcdf576..8c1fc82534 100644 --- a/hw/sparc/sun4m_iommu.c +++ b/hw/sparc/sun4m_iommu.c @@ -370,7 +370,6 @@ static void iommu_init(Object *obj) static const Property iommu_properties[] = { DEFINE_PROP_UINT32("version", IOMMUState, version, 0), - DEFINE_PROP_END_OF_LIST(), }; static void iommu_class_init(ObjectClass *klass, void *data) diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index 8546b30266..5778709b41 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -377,7 +377,6 @@ static void ebus_realize(PCIDevice *pci_dev, Error **errp) static const Property ebus_properties[] = { DEFINE_PROP_UINT64("console-serial-base", EbusState, console_serial_base, 0), - DEFINE_PROP_END_OF_LIST(), }; static void ebus_class_init(ObjectClass *klass, void *data) @@ -471,15 +470,10 @@ static void prom_realize(DeviceState *ds, Error **errp) sysbus_init_mmio(dev, &s->prom); } -static Property prom_properties[] = { - {/* end of property list */}, -}; - static void prom_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - device_class_set_props(dc, prom_properties); dc->realize = prom_realize; } @@ -534,7 +528,6 @@ static void ram_init(hwaddr addr, ram_addr_t RAM_size) static const Property ram_properties[] = { DEFINE_PROP_UINT64("size", RamDevice, size, 0), - DEFINE_PROP_END_OF_LIST(), }; static void ram_class_init(ObjectClass *klass, void *data) diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index bbdd4e4786..faef1a8e5b 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -1292,7 +1292,6 @@ static const Property aspeed_smc_properties[] = { DEFINE_PROP_UINT64("dram-base", AspeedSMCState, dram_base, 0), DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_smc_class_init(ObjectClass *klass, void *data) @@ -1340,7 +1339,6 @@ static const Property aspeed_smc_flash_properties[] = { DEFINE_PROP_UINT8("cs", AspeedSMCFlash, cs, 0), DEFINE_PROP_LINK("controller", AspeedSMCFlash, controller, TYPE_ASPEED_SMC, AspeedSMCState *), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_smc_flash_class_init(ObjectClass *klass, void *data) diff --git a/hw/ssi/ibex_spi_host.c b/hw/ssi/ibex_spi_host.c index 60a0b17b62..46c7b633c2 100644 --- a/hw/ssi/ibex_spi_host.c +++ b/hw/ssi/ibex_spi_host.c @@ -563,7 +563,6 @@ static const MemoryRegionOps ibex_spi_ops = { static const Property ibex_spi_properties[] = { DEFINE_PROP_UINT32("num_cs", IbexSPIHostState, num_cs, 1), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_ibex = { diff --git a/hw/ssi/npcm7xx_fiu.c b/hw/ssi/npcm7xx_fiu.c index fdd3ad2fdc..21fc489038 100644 --- a/hw/ssi/npcm7xx_fiu.c +++ b/hw/ssi/npcm7xx_fiu.c @@ -543,7 +543,6 @@ static const VMStateDescription vmstate_npcm7xx_fiu = { static const Property npcm7xx_fiu_properties[] = { DEFINE_PROP_INT32("cs-count", NPCM7xxFIUState, cs_count, 0), - DEFINE_PROP_END_OF_LIST(), }; static void npcm7xx_fiu_class_init(ObjectClass *klass, void *data) diff --git a/hw/ssi/pnv_spi.c b/hw/ssi/pnv_spi.c index 4ca9c469a4..15e25bd1be 100644 --- a/hw/ssi/pnv_spi.c +++ b/hw/ssi/pnv_spi.c @@ -1198,7 +1198,6 @@ static const MemoryRegionOps pnv_spi_xscom_ops = { static const Property pnv_spi_properties[] = { DEFINE_PROP_UINT32("spic_num", PnvSpi, spic_num, 0), DEFINE_PROP_UINT8("transfer_len", PnvSpi, transfer_len, 4), - DEFINE_PROP_END_OF_LIST(), }; static void pnv_spi_realize(DeviceState *dev, Error **errp) diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c index 7458747779..76f8654f41 100644 --- a/hw/ssi/sifive_spi.c +++ b/hw/ssi/sifive_spi.c @@ -330,7 +330,6 @@ static void sifive_spi_realize(DeviceState *dev, Error **errp) static const Property sifive_spi_properties[] = { DEFINE_PROP_UINT32("num-cs", SiFiveSPIState, num_cs, 1), - DEFINE_PROP_END_OF_LIST(), }; static void sifive_spi_class_init(ObjectClass *klass, void *data) diff --git a/hw/ssi/ssi.c b/hw/ssi/ssi.c index cab0014c3f..872c4e8036 100644 --- a/hw/ssi/ssi.c +++ b/hw/ssi/ssi.c @@ -110,7 +110,6 @@ static void ssi_peripheral_realize(DeviceState *dev, Error **errp) static const Property ssi_peripheral_properties[] = { DEFINE_PROP_UINT8("cs", SSIPeripheral, cs_index, 0), - DEFINE_PROP_END_OF_LIST(), }; static void ssi_peripheral_class_init(ObjectClass *klass, void *data) diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 588c1ec071..fd1ff12eb1 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -363,7 +363,6 @@ static const VMStateDescription vmstate_xilinx_spi = { static const Property xilinx_spi_properties[] = { DEFINE_PROP_UINT8("num-ss-bits", XilinxSPI, num_cs, 1), - DEFINE_PROP_END_OF_LIST(), }; static void xilinx_spi_class_init(ObjectClass *klass, void *data) diff --git a/hw/ssi/xilinx_spips.c b/hw/ssi/xilinx_spips.c index 0acac4ef70..60d092039f 100644 --- a/hw/ssi/xilinx_spips.c +++ b/hw/ssi/xilinx_spips.c @@ -1422,14 +1422,12 @@ static const VMStateDescription vmstate_xlnx_zynqmp_qspips = { static const Property xilinx_zynqmp_qspips_properties[] = { DEFINE_PROP_UINT32("dma-burst-size", XlnxZynqMPQSPIPS, dma_burst_size, 64), - DEFINE_PROP_END_OF_LIST(), }; static const Property xilinx_spips_properties[] = { DEFINE_PROP_UINT8("num-busses", XilinxSPIPS, num_busses, 1), DEFINE_PROP_UINT8("num-ss-bits", XilinxSPIPS, num_cs, 4), DEFINE_PROP_UINT8("num-txrx-bytes", XilinxSPIPS, num_txrx_bytes, 1), - DEFINE_PROP_END_OF_LIST(), }; static void xilinx_qspips_class_init(ObjectClass *klass, void * data) diff --git a/hw/ssi/xlnx-versal-ospi.c b/hw/ssi/xlnx-versal-ospi.c index e51abe9de2..9e96c9b69a 100644 --- a/hw/ssi/xlnx-versal-ospi.c +++ b/hw/ssi/xlnx-versal-ospi.c @@ -1829,7 +1829,6 @@ static const Property xlnx_versal_ospi_properties[] = { DEFINE_PROP_BOOL("dac-with-indac", XlnxVersalOspi, dac_with_indac, false), DEFINE_PROP_BOOL("indac-write-disabled", XlnxVersalOspi, ind_write_disabled, false), - DEFINE_PROP_END_OF_LIST(), }; static void xlnx_versal_ospi_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/a9gtimer.c b/hw/timer/a9gtimer.c index 0c226d6ea6..9835c35483 100644 --- a/hw/timer/a9gtimer.c +++ b/hw/timer/a9gtimer.c @@ -375,7 +375,6 @@ static const VMStateDescription vmstate_a9_gtimer = { static const Property a9_gtimer_properties[] = { DEFINE_PROP_UINT32("num-cpu", A9GTimerState, num_cpu, 0), - DEFINE_PROP_END_OF_LIST() }; static void a9_gtimer_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/allwinner-a10-pit.c b/hw/timer/allwinner-a10-pit.c index 2904ccfb42..ddaf2128c2 100644 --- a/hw/timer/allwinner-a10-pit.c +++ b/hw/timer/allwinner-a10-pit.c @@ -193,7 +193,6 @@ static const Property a10_pit_properties[] = { DEFINE_PROP_UINT32("clk1-freq", AwA10PITState, clk_freq[1], 0), DEFINE_PROP_UINT32("clk2-freq", AwA10PITState, clk_freq[2], 0), DEFINE_PROP_UINT32("clk3-freq", AwA10PITState, clk_freq[3], 0), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_a10_pit = { diff --git a/hw/timer/arm_mptimer.c b/hw/timer/arm_mptimer.c index 6244a7a84f..803dad1e8a 100644 --- a/hw/timer/arm_mptimer.c +++ b/hw/timer/arm_mptimer.c @@ -302,7 +302,6 @@ static const VMStateDescription vmstate_arm_mptimer = { static const Property arm_mptimer_properties[] = { DEFINE_PROP_UINT32("num-cpu", ARMMPTimerState, num_cpu, 0), - DEFINE_PROP_END_OF_LIST() }; static void arm_mptimer_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/arm_timer.c b/hw/timer/arm_timer.c index dfa034296c..1213b77aa0 100644 --- a/hw/timer/arm_timer.c +++ b/hw/timer/arm_timer.c @@ -390,7 +390,6 @@ static const TypeInfo icp_pit_info = { static const Property sp804_properties[] = { DEFINE_PROP_UINT32("freq0", SP804State, freq0, 1000000), DEFINE_PROP_UINT32("freq1", SP804State, freq1, 1000000), - DEFINE_PROP_END_OF_LIST(), }; static void sp804_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 4c16b5016e..4868651ad4 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -677,7 +677,6 @@ static const VMStateDescription vmstate_aspeed_timer_state = { static const Property aspeed_timer_properties[] = { DEFINE_PROP_LINK("scu", AspeedTimerCtrlState, scu, TYPE_ASPEED_SCU, AspeedSCUState *), - DEFINE_PROP_END_OF_LIST(), }; static void timer_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/avr_timer16.c b/hw/timer/avr_timer16.c index 2e3ce83c43..96baf9cf60 100644 --- a/hw/timer/avr_timer16.c +++ b/hw/timer/avr_timer16.c @@ -546,7 +546,6 @@ static const Property avr_timer16_properties[] = { DEFINE_PROP_UINT8("id", struct AVRTimer16State, id, 0), DEFINE_PROP_UINT64("cpu-frequency-hz", struct AVRTimer16State, cpu_freq_hz, 0), - DEFINE_PROP_END_OF_LIST(), }; static void avr_timer16_pr(void *opaque, int irq, int level) diff --git a/hw/timer/grlib_gptimer.c b/hw/timer/grlib_gptimer.c index a7428ed938..f0802b6eb6 100644 --- a/hw/timer/grlib_gptimer.c +++ b/hw/timer/grlib_gptimer.c @@ -407,7 +407,6 @@ static const Property grlib_gptimer_properties[] = { DEFINE_PROP_UINT32("frequency", GPTimerUnit, freq_hz, 40000000), DEFINE_PROP_UINT32("irq-line", GPTimerUnit, irq_line, 8), DEFINE_PROP_UINT32("nr-timers", GPTimerUnit, nr_timers, 2), - DEFINE_PROP_END_OF_LIST(), }; static void grlib_gptimer_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/hpet.c b/hw/timer/hpet.c index 46886c379e..2a45410c0d 100644 --- a/hw/timer/hpet.c +++ b/hw/timer/hpet.c @@ -750,7 +750,6 @@ static const Property hpet_device_properties[] = { DEFINE_PROP_BIT("msi", HPETState, flags, HPET_MSI_SUPPORT, false), DEFINE_PROP_UINT32(HPET_INTCAP, HPETState, intcap, 0), DEFINE_PROP_BOOL("hpet-offset-saved", HPETState, hpet_offset_saved, true), - DEFINE_PROP_END_OF_LIST(), }; static void hpet_device_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/i8254_common.c b/hw/timer/i8254_common.c index 953c1e11eb..29105afcc3 100644 --- a/hw/timer/i8254_common.c +++ b/hw/timer/i8254_common.c @@ -240,7 +240,6 @@ static const VMStateDescription vmstate_pit_common = { static const Property pit_common_properties[] = { DEFINE_PROP_UINT32("iobase", PITCommonState, iobase, -1), - DEFINE_PROP_END_OF_LIST(), }; static void pit_common_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/ibex_timer.c b/hw/timer/ibex_timer.c index fba4466a89..3ebc870097 100644 --- a/hw/timer/ibex_timer.c +++ b/hw/timer/ibex_timer.c @@ -265,7 +265,6 @@ static const VMStateDescription vmstate_ibex_timer = { static const Property ibex_timer_properties[] = { DEFINE_PROP_UINT32("timebase-freq", IbexTimerState, timebase_freq, 10000), - DEFINE_PROP_END_OF_LIST(), }; static void ibex_timer_init(Object *obj) diff --git a/hw/timer/mss-timer.c b/hw/timer/mss-timer.c index e5c5cd6a84..594da64eae 100644 --- a/hw/timer/mss-timer.c +++ b/hw/timer/mss-timer.c @@ -283,7 +283,6 @@ static const Property mss_timer_properties[] = { /* Libero GUI shows 100Mhz as default for clocks */ DEFINE_PROP_UINT32("clock-frequency", MSSTimerState, freq_hz, 100 * 1000000), - DEFINE_PROP_END_OF_LIST(), }; static void mss_timer_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/nrf51_timer.c b/hw/timer/nrf51_timer.c index 48fccec1bf..11ad8b575e 100644 --- a/hw/timer/nrf51_timer.c +++ b/hw/timer/nrf51_timer.c @@ -381,7 +381,6 @@ static const VMStateDescription vmstate_nrf51_timer = { static const Property nrf51_timer_properties[] = { DEFINE_PROP_UINT8("id", NRF51TimerState, id, 0), - DEFINE_PROP_END_OF_LIST(), }; static void nrf51_timer_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/pxa2xx_timer.c b/hw/timer/pxa2xx_timer.c index 6328ad6ab7..9e4dd0fd9f 100644 --- a/hw/timer/pxa2xx_timer.c +++ b/hw/timer/pxa2xx_timer.c @@ -553,7 +553,6 @@ static const Property pxa25x_timer_dev_properties[] = { DEFINE_PROP_UINT32("freq", PXA2xxTimerInfo, freq, PXA25X_FREQ), DEFINE_PROP_BIT("tm4", PXA2xxTimerInfo, flags, PXA2XX_TIMER_HAVE_TM4, false), - DEFINE_PROP_END_OF_LIST(), }; static void pxa25x_timer_dev_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/renesas_cmt.c b/hw/timer/renesas_cmt.c index 6d451fa86b..93e7f58cc2 100644 --- a/hw/timer/renesas_cmt.c +++ b/hw/timer/renesas_cmt.c @@ -255,7 +255,6 @@ static const VMStateDescription vmstate_rcmt = { static const Property rcmt_properties[] = { DEFINE_PROP_UINT64("input-freq", RCMTState, input_freq, 0), - DEFINE_PROP_END_OF_LIST(), }; static void rcmt_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/renesas_tmr.c b/hw/timer/renesas_tmr.c index 890f803cf8..884349c2cc 100644 --- a/hw/timer/renesas_tmr.c +++ b/hw/timer/renesas_tmr.c @@ -465,7 +465,6 @@ static const VMStateDescription vmstate_rtmr = { static const Property rtmr_properties[] = { DEFINE_PROP_UINT64("input-freq", RTMRState, input_freq, 0), - DEFINE_PROP_END_OF_LIST(), }; static void rtmr_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/sifive_pwm.c b/hw/timer/sifive_pwm.c index 042c89c67a..fc796e9bc3 100644 --- a/hw/timer/sifive_pwm.c +++ b/hw/timer/sifive_pwm.c @@ -408,7 +408,6 @@ static const Property sifive_pwm_properties[] = { /* 0.5Ghz per spec after FSBL */ DEFINE_PROP_UINT64("clock-frequency", struct SiFivePwmState, freq_hz, 500000000ULL), - DEFINE_PROP_END_OF_LIST(), }; static void sifive_pwm_init(Object *obj) diff --git a/hw/timer/slavio_timer.c b/hw/timer/slavio_timer.c index 32991f4436..65b24e4f06 100644 --- a/hw/timer/slavio_timer.c +++ b/hw/timer/slavio_timer.c @@ -422,7 +422,6 @@ static void slavio_timer_init(Object *obj) static const Property slavio_timer_properties[] = { DEFINE_PROP_UINT32("num_cpus", SLAVIO_TIMERState, num_cpus, 0), - DEFINE_PROP_END_OF_LIST(), }; static void slavio_timer_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/sse-timer.c b/hw/timer/sse-timer.c index 6b7a67941c..e106739ea9 100644 --- a/hw/timer/sse-timer.c +++ b/hw/timer/sse-timer.c @@ -442,7 +442,6 @@ static const VMStateDescription sse_timer_vmstate = { static const Property sse_timer_properties[] = { DEFINE_PROP_LINK("counter", SSETimer, counter, TYPE_SSE_COUNTER, SSECounter *), - DEFINE_PROP_END_OF_LIST(), }; static void sse_timer_class_init(ObjectClass *klass, void *data) diff --git a/hw/timer/stm32f2xx_timer.c b/hw/timer/stm32f2xx_timer.c index d9d745cd76..4707190d6a 100644 --- a/hw/timer/stm32f2xx_timer.c +++ b/hw/timer/stm32f2xx_timer.c @@ -301,7 +301,6 @@ static const VMStateDescription vmstate_stm32f2xx_timer = { static const Property stm32f2xx_timer_properties[] = { DEFINE_PROP_UINT64("clock-frequency", struct STM32F2XXTimerState, freq_hz, 1000000000), - DEFINE_PROP_END_OF_LIST(), }; static void stm32f2xx_timer_init(Object *obj) diff --git a/hw/timer/xilinx_timer.c b/hw/timer/xilinx_timer.c index 7fe3e83baa..4955fe1b01 100644 --- a/hw/timer/xilinx_timer.c +++ b/hw/timer/xilinx_timer.c @@ -245,7 +245,6 @@ static void xilinx_timer_init(Object *obj) static const Property xilinx_timer_properties[] = { DEFINE_PROP_UINT32("clock-frequency", XpsTimerState, freq_hz, 62 * 1000000), DEFINE_PROP_UINT8("one-timer-only", XpsTimerState, one_timer_only, 0), - DEFINE_PROP_END_OF_LIST(), }; static void xilinx_timer_class_init(ObjectClass *klass, void *data) diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index a9f7aba303..6cdeb72df0 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -229,7 +229,6 @@ static const VMStateDescription vmstate_tpm_crb = { static const Property tpm_crb_properties[] = { DEFINE_PROP_TPMBE("tpmdev", CRBState, tpmbe), DEFINE_PROP_BOOL("ppi", CRBState, ppi_enabled, true), - DEFINE_PROP_END_OF_LIST(), }; static void tpm_crb_reset(void *dev) diff --git a/hw/tpm/tpm_spapr.c b/hw/tpm/tpm_spapr.c index 645079f2e5..9a031e1e75 100644 --- a/hw/tpm/tpm_spapr.c +++ b/hw/tpm/tpm_spapr.c @@ -367,7 +367,6 @@ static const VMStateDescription vmstate_spapr_vtpm = { static const Property tpm_spapr_properties[] = { DEFINE_SPAPR_PROPERTIES(SpaprTpmState, vdev), DEFINE_PROP_TPMBE("tpmdev", SpaprTpmState, be_driver), - DEFINE_PROP_END_OF_LIST(), }; static void tpm_spapr_realizefn(SpaprVioDevice *dev, Error **errp) diff --git a/hw/tpm/tpm_tis_i2c.c b/hw/tpm/tpm_tis_i2c.c index b27af230cd..504328e3b0 100644 --- a/hw/tpm/tpm_tis_i2c.c +++ b/hw/tpm/tpm_tis_i2c.c @@ -493,7 +493,6 @@ static int tpm_tis_i2c_send(I2CSlave *i2c, uint8_t data) static const Property tpm_tis_i2c_properties[] = { DEFINE_PROP_TPMBE("tpmdev", TPMStateI2C, state.be_driver), - DEFINE_PROP_END_OF_LIST(), }; static void tpm_tis_i2c_realizefn(DeviceState *dev, Error **errp) diff --git a/hw/tpm/tpm_tis_isa.c b/hw/tpm/tpm_tis_isa.c index 9b2160972a..876cb02cb5 100644 --- a/hw/tpm/tpm_tis_isa.c +++ b/hw/tpm/tpm_tis_isa.c @@ -95,7 +95,6 @@ static const Property tpm_tis_isa_properties[] = { DEFINE_PROP_UINT32("irq", TPMStateISA, state.irq_num, TPM_TIS_IRQ), DEFINE_PROP_TPMBE("tpmdev", TPMStateISA, state.be_driver), DEFINE_PROP_BOOL("ppi", TPMStateISA, state.ppi_enabled, true), - DEFINE_PROP_END_OF_LIST(), }; static void tpm_tis_isa_initfn(Object *obj) diff --git a/hw/tpm/tpm_tis_sysbus.c b/hw/tpm/tpm_tis_sysbus.c index 88c1f1e478..ee0bfe9538 100644 --- a/hw/tpm/tpm_tis_sysbus.c +++ b/hw/tpm/tpm_tis_sysbus.c @@ -93,7 +93,6 @@ static void tpm_tis_sysbus_reset(DeviceState *dev) static const Property tpm_tis_sysbus_properties[] = { DEFINE_PROP_UINT32("irq", TPMStateSysBus, state.irq_num, TPM_TIS_IRQ), DEFINE_PROP_TPMBE("tpmdev", TPMStateSysBus, state.be_driver), - DEFINE_PROP_END_OF_LIST(), }; static void tpm_tis_sysbus_initfn(Object *obj) diff --git a/hw/tricore/tc27x_soc.c b/hw/tricore/tc27x_soc.c index ecd92717b5..81bb16d89b 100644 --- a/hw/tricore/tc27x_soc.c +++ b/hw/tricore/tc27x_soc.c @@ -201,16 +201,11 @@ static void tc27x_soc_init(Object *obj) object_initialize_child(obj, "tc27x", &s->cpu, sc->cpu_type); } -static Property tc27x_soc_properties[] = { - DEFINE_PROP_END_OF_LIST(), -}; - static void tc27x_soc_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); dc->realize = tc27x_soc_realize; - device_class_set_props(dc, tc27x_soc_properties); } static void tc277d_soc_class_init(ObjectClass *oc, void *data) diff --git a/hw/tricore/tricore_testdevice.c b/hw/tricore/tricore_testdevice.c index ae95c49565..e60866d76f 100644 --- a/hw/tricore/tricore_testdevice.c +++ b/hw/tricore/tricore_testdevice.c @@ -58,15 +58,10 @@ static void tricore_testdevice_init(Object *obj) "tricore_testdevice", 0x4); } -static Property tricore_testdevice_properties[] = { - DEFINE_PROP_END_OF_LIST() -}; - static void tricore_testdevice_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - device_class_set_props(dc, tricore_testdevice_properties); device_class_set_legacy_reset(dc, tricore_testdevice_reset); } diff --git a/hw/ufs/lu.c b/hw/ufs/lu.c index 34e4bd8936..1c3794b2d4 100644 --- a/hw/ufs/lu.c +++ b/hw/ufs/lu.c @@ -277,7 +277,6 @@ static UfsReqResult ufs_process_scsi_cmd(UfsLu *lu, UfsRequest *req) static const Property ufs_lu_props[] = { DEFINE_PROP_DRIVE("drive", UfsLu, conf.blk), DEFINE_PROP_UINT8("lun", UfsLu, lun, 0), - DEFINE_PROP_END_OF_LIST(), }; static bool ufs_add_lu(UfsHc *u, UfsLu *lu, Error **errp) diff --git a/hw/ufs/ufs.c b/hw/ufs/ufs.c index fe77158439..8d26d13791 100644 --- a/hw/ufs/ufs.c +++ b/hw/ufs/ufs.c @@ -1758,7 +1758,6 @@ static const Property ufs_props[] = { DEFINE_PROP_UINT8("nutmrs", UfsHc, params.nutmrs, 8), DEFINE_PROP_BOOL("mcq", UfsHc, params.mcq, false), DEFINE_PROP_UINT8("mcq-maxq", UfsHc, params.mcq_maxq, 2), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription ufs_vmstate = { diff --git a/hw/usb/bus.c b/hw/usb/bus.c index 8277efb98d..b19b0b13eb 100644 --- a/hw/usb/bus.c +++ b/hw/usb/bus.c @@ -24,7 +24,6 @@ static const Property usb_props[] = { DEFINE_PROP_BIT("msos-desc", USBDevice, flags, USB_DEV_FLAG_MSOS_DESC_ENABLE, true), DEFINE_PROP_STRING("pcap", USBDevice, pcap_filename), - DEFINE_PROP_END_OF_LIST() }; static void usb_bus_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/canokey.c b/hw/usb/canokey.c index 7cb600e3c8..fae212f053 100644 --- a/hw/usb/canokey.c +++ b/hw/usb/canokey.c @@ -298,7 +298,6 @@ static void canokey_unrealize(USBDevice *base) static const Property canokey_properties[] = { DEFINE_PROP_STRING("file", CanoKeyState, file), - DEFINE_PROP_END_OF_LIST(), }; static void canokey_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/ccid-card-emulated.c b/hw/usb/ccid-card-emulated.c index dd58333943..b1e330f21d 100644 --- a/hw/usb/ccid-card-emulated.c +++ b/hw/usb/ccid-card-emulated.c @@ -589,7 +589,6 @@ static const Property emulated_card_properties[] = { DEFINE_PROP_STRING("cert3", EmulatedState, cert3), DEFINE_PROP_STRING("db", EmulatedState, db), DEFINE_PROP_UINT8("debug", EmulatedState, debug, 0), - DEFINE_PROP_END_OF_LIST(), }; static void emulated_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c index f97dcf767f..bf81485f87 100644 --- a/hw/usb/ccid-card-passthru.c +++ b/hw/usb/ccid-card-passthru.c @@ -391,7 +391,6 @@ static const VMStateDescription passthru_vmstate = { static const Property passthru_card_properties[] = { DEFINE_PROP_CHR("chardev", PassthruState, cs), DEFINE_PROP_UINT8("debug", PassthruState, debug, 0), - DEFINE_PROP_END_OF_LIST(), }; static void passthru_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/dev-audio.c b/hw/usb/dev-audio.c index 6007f16d30..40f031252a 100644 --- a/hw/usb/dev-audio.c +++ b/hw/usb/dev-audio.c @@ -995,7 +995,6 @@ static const Property usb_audio_properties[] = { DEFINE_PROP_UINT32("debug", USBAudioState, debug, 0), DEFINE_PROP_UINT32("buffer", USBAudioState, buffer_user, 0), DEFINE_PROP_BOOL("multi", USBAudioState, multi, false), - DEFINE_PROP_END_OF_LIST(), }; static void usb_audio_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/dev-hid.c b/hw/usb/dev-hid.c index d83f67b984..accdd460e3 100644 --- a/hw/usb/dev-hid.c +++ b/hw/usb/dev-hid.c @@ -797,7 +797,6 @@ static const Property usb_tablet_properties[] = { DEFINE_PROP_UINT32("usb_version", USBHIDState, usb_version, 2), DEFINE_PROP_STRING("display", USBHIDState, display), DEFINE_PROP_UINT32("head", USBHIDState, head, 0), - DEFINE_PROP_END_OF_LIST(), }; static void usb_tablet_class_initfn(ObjectClass *klass, void *data) @@ -820,7 +819,6 @@ static const TypeInfo usb_tablet_info = { static const Property usb_mouse_properties[] = { DEFINE_PROP_UINT32("usb_version", USBHIDState, usb_version, 2), - DEFINE_PROP_END_OF_LIST(), }; static void usb_mouse_class_initfn(ObjectClass *klass, void *data) @@ -844,7 +842,6 @@ static const TypeInfo usb_mouse_info = { static const Property usb_keyboard_properties[] = { DEFINE_PROP_UINT32("usb_version", USBHIDState, usb_version, 2), DEFINE_PROP_STRING("display", USBHIDState, display), - DEFINE_PROP_END_OF_LIST(), }; static void usb_keyboard_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/dev-hub.c b/hw/usb/dev-hub.c index 317ca0b081..3880e2aca8 100644 --- a/hw/usb/dev-hub.c +++ b/hw/usb/dev-hub.c @@ -668,7 +668,6 @@ static const VMStateDescription vmstate_usb_hub = { static const Property usb_hub_properties[] = { DEFINE_PROP_UINT32("ports", USBHubState, num_ports, 8), DEFINE_PROP_BOOL("port-power", USBHubState, port_power, false), - DEFINE_PROP_END_OF_LIST(), }; static void usb_hub_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/dev-mtp.c b/hw/usb/dev-mtp.c index 7994727e5e..326c92a43d 100644 --- a/hw/usb/dev-mtp.c +++ b/hw/usb/dev-mtp.c @@ -2082,7 +2082,6 @@ static const Property mtp_properties[] = { DEFINE_PROP_STRING("rootdir", MTPState, root), DEFINE_PROP_STRING("desc", MTPState, desc), DEFINE_PROP_BOOL("readonly", MTPState, readonly, true), - DEFINE_PROP_END_OF_LIST(), }; static void usb_mtp_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/dev-network.c b/hw/usb/dev-network.c index 39e8905f0e..a87a0ffb95 100644 --- a/hw/usb/dev-network.c +++ b/hw/usb/dev-network.c @@ -1409,7 +1409,6 @@ static const VMStateDescription vmstate_usb_net = { static const Property net_properties[] = { DEFINE_NIC_PROPERTIES(USBNetState, conf), - DEFINE_PROP_END_OF_LIST(), }; static void usb_net_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/dev-serial.c b/hw/usb/dev-serial.c index 0c3e9160ec..a0821db902 100644 --- a/hw/usb/dev-serial.c +++ b/hw/usb/dev-serial.c @@ -637,7 +637,6 @@ static const VMStateDescription vmstate_usb_serial = { static const Property serial_properties[] = { DEFINE_PROP_CHR("chardev", USBSerialState, cs), DEFINE_PROP_BOOL("always-plugged", USBSerialState, always_plugged, false), - DEFINE_PROP_END_OF_LIST(), }; static void usb_serial_dev_class_init(ObjectClass *klass, void *data) @@ -679,7 +678,6 @@ static const TypeInfo serial_info = { static const Property braille_properties[] = { DEFINE_PROP_CHR("chardev", USBSerialState, cs), - DEFINE_PROP_END_OF_LIST(), }; static void usb_braille_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c index c3c02f0aad..73deb3ce83 100644 --- a/hw/usb/dev-smartcard-reader.c +++ b/hw/usb/dev-smartcard-reader.c @@ -1173,7 +1173,6 @@ static Answer *ccid_peek_next_answer(USBCCIDState *s) static const Property ccid_props[] = { DEFINE_PROP_UINT32("slot", struct CCIDCardState, slot, 0), - DEFINE_PROP_END_OF_LIST(), }; static const TypeInfo ccid_bus_info = { @@ -1433,7 +1432,6 @@ static const VMStateDescription ccid_vmstate = { static const Property ccid_properties[] = { DEFINE_PROP_UINT8("debug", USBCCIDState, debug, 0), - DEFINE_PROP_END_OF_LIST(), }; static void ccid_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/dev-storage-classic.c b/hw/usb/dev-storage-classic.c index 9e54006c60..56ef39da2e 100644 --- a/hw/usb/dev-storage-classic.c +++ b/hw/usb/dev-storage-classic.c @@ -72,7 +72,6 @@ static const Property msd_properties[] = { DEFINE_BLOCK_ERROR_PROPERTIES(MSDState, conf), DEFINE_PROP_BOOL("removable", MSDState, removable, false), DEFINE_PROP_BOOL("commandlog", MSDState, commandlog, false), - DEFINE_PROP_END_OF_LIST(), }; static void usb_msd_class_storage_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/dev-uas.c b/hw/usb/dev-uas.c index 57e8d20051..44e30013d7 100644 --- a/hw/usb/dev-uas.c +++ b/hw/usb/dev-uas.c @@ -955,7 +955,6 @@ static const VMStateDescription vmstate_usb_uas = { static const Property uas_properties[] = { DEFINE_PROP_UINT32("log-scsi-req", UASDevice, requestlog, 0), - DEFINE_PROP_END_OF_LIST(), }; static void usb_uas_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/hcd-dwc2.c b/hw/usb/hcd-dwc2.c index 6a10f3e9cd..e8152719f8 100644 --- a/hw/usb/hcd-dwc2.c +++ b/hw/usb/hcd-dwc2.c @@ -1450,7 +1450,6 @@ const VMStateDescription vmstate_dwc2_state = { static const Property dwc2_usb_properties[] = { DEFINE_PROP_UINT32("usb_version", DWC2State, usb_version, 2), - DEFINE_PROP_END_OF_LIST(), }; static void dwc2_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c index ff970bd989..9ce9ba0b04 100644 --- a/hw/usb/hcd-dwc3.c +++ b/hw/usb/hcd-dwc3.c @@ -659,7 +659,6 @@ static const VMStateDescription vmstate_usb_dwc3 = { static const Property usb_dwc3_properties[] = { DEFINE_PROP_UINT32("DWC_USB3_USERID", USBDWC3, cfg.dwc_usb3_user, 0x12345678), - DEFINE_PROP_END_OF_LIST(), }; static void usb_dwc3_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/hcd-ehci-pci.c b/hw/usb/hcd-ehci-pci.c index 374f25c5ed..d410c38a8a 100644 --- a/hw/usb/hcd-ehci-pci.c +++ b/hw/usb/hcd-ehci-pci.c @@ -137,7 +137,6 @@ static void usb_ehci_pci_write_config(PCIDevice *dev, uint32_t addr, static const Property ehci_pci_properties[] = { DEFINE_PROP_UINT32("maxframes", EHCIPCIState, ehci.maxframes, 128), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_ehci_pci = { diff --git a/hw/usb/hcd-ehci-sysbus.c b/hw/usb/hcd-ehci-sysbus.c index f4e08aab89..768c3dd797 100644 --- a/hw/usb/hcd-ehci-sysbus.c +++ b/hw/usb/hcd-ehci-sysbus.c @@ -34,7 +34,6 @@ static const Property ehci_sysbus_properties[] = { DEFINE_PROP_UINT32("maxframes", EHCISysBusState, ehci.maxframes, 128), DEFINE_PROP_BOOL("companion-enable", EHCISysBusState, ehci.companion_enable, false), - DEFINE_PROP_END_OF_LIST(), }; static void usb_ehci_sysbus_realize(DeviceState *dev, Error **errp) diff --git a/hw/usb/hcd-ohci-pci.c b/hw/usb/hcd-ohci-pci.c index 459644cc1b..b3684a2ef6 100644 --- a/hw/usb/hcd-ohci-pci.c +++ b/hw/usb/hcd-ohci-pci.c @@ -113,7 +113,6 @@ static const Property ohci_pci_properties[] = { DEFINE_PROP_STRING("masterbus", OHCIPCIState, masterbus), DEFINE_PROP_UINT32("num-ports", OHCIPCIState, num_ports, 3), DEFINE_PROP_UINT32("firstport", OHCIPCIState, firstport, 0), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_ohci = { diff --git a/hw/usb/hcd-ohci-sysbus.c b/hw/usb/hcd-ohci-sysbus.c index 81cf2e558d..15311949b3 100644 --- a/hw/usb/hcd-ohci-sysbus.c +++ b/hw/usb/hcd-ohci-sysbus.c @@ -62,7 +62,6 @@ static const Property ohci_sysbus_properties[] = { DEFINE_PROP_UINT32("num-ports", OHCISysBusState, num_ports, 3), DEFINE_PROP_UINT32("firstport", OHCISysBusState, firstport, 0), DEFINE_PROP_DMAADDR("dma-offset", OHCISysBusState, dma_offset, 0), - DEFINE_PROP_END_OF_LIST(), }; static void ohci_sysbus_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/hcd-uhci.c b/hw/usb/hcd-uhci.c index b6e6316a65..0559b3ae3e 100644 --- a/hw/usb/hcd-uhci.c +++ b/hw/usb/hcd-uhci.c @@ -1232,12 +1232,10 @@ static const Property uhci_properties_companion[] = { DEFINE_PROP_UINT32("firstport", UHCIState, firstport, 0), DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), - DEFINE_PROP_END_OF_LIST(), }; static const Property uhci_properties_standalone[] = { DEFINE_PROP_UINT32("bandwidth", UHCIState, frame_bandwidth, 1280), DEFINE_PROP_UINT32("maxframes", UHCIState, maxframes, 128), - DEFINE_PROP_END_OF_LIST(), }; static void uhci_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/hcd-xhci-nec.c b/hw/usb/hcd-xhci-nec.c index f06e7403e2..b1df95b52a 100644 --- a/hw/usb/hcd-xhci-nec.c +++ b/hw/usb/hcd-xhci-nec.c @@ -41,7 +41,6 @@ static const Property nec_xhci_properties[] = { DEFINE_PROP_ON_OFF_AUTO("msix", XHCIPciState, msix, ON_OFF_AUTO_AUTO), DEFINE_PROP_UINT32("intrs", XHCINecState, intrs, XHCI_MAXINTRS), DEFINE_PROP_UINT32("slots", XHCINecState, slots, XHCI_MAXSLOTS), - DEFINE_PROP_END_OF_LIST(), }; static void nec_xhci_instance_init(Object *obj) diff --git a/hw/usb/hcd-xhci-sysbus.c b/hw/usb/hcd-xhci-sysbus.c index f4dbad7cc6..ce43322396 100644 --- a/hw/usb/hcd-xhci-sysbus.c +++ b/hw/usb/hcd-xhci-sysbus.c @@ -85,7 +85,6 @@ void xhci_sysbus_build_aml(Aml *scope, uint32_t mmio, unsigned int irq) static const Property xhci_sysbus_props[] = { DEFINE_PROP_UINT32("intrs", XHCISysbusState, xhci.numintrs, XHCI_MAXINTRS), DEFINE_PROP_UINT32("slots", XHCISysbusState, xhci.numslots, XHCI_MAXSLOTS), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_xhci_sysbus = { diff --git a/hw/usb/hcd-xhci.c b/hw/usb/hcd-xhci.c index 3c5006f425..3719c0f190 100644 --- a/hw/usb/hcd-xhci.c +++ b/hw/usb/hcd-xhci.c @@ -3612,7 +3612,6 @@ static const Property xhci_properties[] = { DEFINE_PROP_UINT32("p3", XHCIState, numports_3, 4), DEFINE_PROP_LINK("host", XHCIState, hostOpaque, TYPE_DEVICE, DeviceState *), - DEFINE_PROP_END_OF_LIST(), }; static void xhci_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/host-libusb.c b/hw/usb/host-libusb.c index 7d716ef0bc..c3d642c9d3 100644 --- a/hw/usb/host-libusb.c +++ b/hw/usb/host-libusb.c @@ -1779,7 +1779,6 @@ static const Property usb_host_dev_properties[] = { USB_HOST_OPT_PIPELINE, true), DEFINE_PROP_BOOL("suppress-remote-wake", USBHostDevice, suppress_remote_wake, true), - DEFINE_PROP_END_OF_LIST(), }; static void usb_host_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/redirect.c b/hw/usb/redirect.c index 39000740e6..f3a83b3f4c 100644 --- a/hw/usb/redirect.c +++ b/hw/usb/redirect.c @@ -2580,7 +2580,6 @@ static const Property usbredir_properties[] = { DEFINE_PROP_BOOL("streams", USBRedirDevice, enable_streams, true), DEFINE_PROP_BOOL("suppress-remote-wake", USBRedirDevice, suppress_remote_wake, true), - DEFINE_PROP_END_OF_LIST(), }; static void usbredir_class_initfn(ObjectClass *klass, void *data) diff --git a/hw/usb/u2f-emulated.c b/hw/usb/u2f-emulated.c index df86ce97fc..e1dd19ee92 100644 --- a/hw/usb/u2f-emulated.c +++ b/hw/usb/u2f-emulated.c @@ -375,7 +375,6 @@ static const Property u2f_emulated_properties[] = { DEFINE_PROP_STRING("privkey", U2FEmulatedState, privkey), DEFINE_PROP_STRING("entropy", U2FEmulatedState, entropy), DEFINE_PROP_STRING("counter", U2FEmulatedState, counter), - DEFINE_PROP_END_OF_LIST(), }; static void u2f_emulated_class_init(ObjectClass *klass, void *data) diff --git a/hw/usb/u2f-passthru.c b/hw/usb/u2f-passthru.c index ec4f6165d8..8df5215a1f 100644 --- a/hw/usb/u2f-passthru.c +++ b/hw/usb/u2f-passthru.c @@ -518,7 +518,6 @@ static const VMStateDescription u2f_passthru_vmstate = { static const Property u2f_passthru_properties[] = { DEFINE_PROP_STRING("hidraw", U2FPassthruState, hidraw), - DEFINE_PROP_END_OF_LIST(), }; static void u2f_passthru_class_init(ObjectClass *klass, void *data) diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c index 6dff88e630..30b08ad375 100644 --- a/hw/vfio/ap.c +++ b/hw/vfio/ap.c @@ -197,7 +197,6 @@ static const Property vfio_ap_properties[] = { DEFINE_PROP_LINK("iommufd", VFIOAPDevice, vdev.iommufd, TYPE_IOMMUFD_BACKEND, IOMMUFDBackend *), #endif - DEFINE_PROP_END_OF_LIST(), }; static void vfio_ap_reset(DeviceState *dev) diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c index 87b58d8f66..67bc137f9b 100644 --- a/hw/vfio/ccw.c +++ b/hw/vfio/ccw.c @@ -663,7 +663,6 @@ static const Property vfio_ccw_properties[] = { TYPE_IOMMUFD_BACKEND, IOMMUFDBackend *), #endif DEFINE_PROP_CCW_LOADPARM("loadparm", CcwDevice, loadparm), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vfio_ccw_vmstate = { diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index d37f722cce..c8e60475d5 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -1499,7 +1499,7 @@ static void get_nv_gpudirect_clique_id(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint8_t *ptr = object_field_prop_ptr(obj, prop); visit_type_uint8(v, name, ptr, errp); @@ -1509,7 +1509,7 @@ static void set_nv_gpudirect_clique_id(Object *obj, Visitor *v, const char *name, void *opaque, Error **errp) { - Property *prop = opaque; + const Property *prop = opaque; uint8_t value, *ptr = object_field_prop_ptr(obj, prop); if (!visit_type_uint8(v, name, &value, errp)) { diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index bd8565c50e..17080b9dc0 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -3409,7 +3409,6 @@ static const Property vfio_pci_dev_properties[] = { TYPE_IOMMUFD_BACKEND, IOMMUFDBackend *), #endif DEFINE_PROP_BOOL("skip-vsc-check", VFIOPCIDevice, skip_vsc_check, true), - DEFINE_PROP_END_OF_LIST(), }; #ifdef CONFIG_IOMMUFD @@ -3455,7 +3454,6 @@ static const Property vfio_pci_dev_nohotplug_properties[] = { DEFINE_PROP_BOOL("ramfb", VFIOPCIDevice, enable_ramfb, false), DEFINE_PROP_ON_OFF_AUTO("x-ramfb-migrate", VFIOPCIDevice, ramfb_migrate, ON_OFF_AUTO_AUTO), - DEFINE_PROP_END_OF_LIST(), }; static void vfio_pci_nohotplug_dev_class_init(ObjectClass *klass, void *data) diff --git a/hw/vfio/platform.c b/hw/vfio/platform.c index 2e17fb96b2..1070a2113a 100644 --- a/hw/vfio/platform.c +++ b/hw/vfio/platform.c @@ -640,7 +640,6 @@ static const Property vfio_platform_dev_properties[] = { DEFINE_PROP_LINK("iommufd", VFIOPlatformDevice, vbasedev.iommufd, TYPE_IOMMUFD_BACKEND, IOMMUFDBackend *), #endif - DEFINE_PROP_END_OF_LIST(), }; static void vfio_platform_instance_init(Object *obj) diff --git a/hw/virtio/vdpa-dev-pci.c b/hw/virtio/vdpa-dev-pci.c index 5446e6b393..787926801a 100644 --- a/hw/virtio/vdpa-dev-pci.c +++ b/hw/virtio/vdpa-dev-pci.c @@ -48,10 +48,6 @@ static void vhost_vdpa_device_pci_instance_init(Object *obj) "bootindex"); } -static Property vhost_vdpa_device_pci_properties[] = { - DEFINE_PROP_END_OF_LIST(), -}; - static int vhost_vdpa_device_pci_post_init(VhostVdpaDevice *v, Error **errp) { VhostVdpaDevicePCI *dev = container_of(v, VhostVdpaDevicePCI, vdev); @@ -80,7 +76,6 @@ static void vhost_vdpa_device_pci_class_init(ObjectClass *klass, void *data) VirtioPCIClass *k = VIRTIO_PCI_CLASS(klass); set_bit(DEVICE_CATEGORY_MISC, dc->categories); - device_class_set_props(dc, vhost_vdpa_device_pci_properties); k->realize = vhost_vdpa_device_pci_realize; } diff --git a/hw/virtio/vdpa-dev.c b/hw/virtio/vdpa-dev.c index 78f8feed2b..a7e73b1c99 100644 --- a/hw/virtio/vdpa-dev.c +++ b/hw/virtio/vdpa-dev.c @@ -340,7 +340,6 @@ static void vhost_vdpa_device_set_status(VirtIODevice *vdev, uint8_t status) static const Property vhost_vdpa_device_properties[] = { DEFINE_PROP_STRING("vhostdev", VhostVdpaDevice, vhostdev), DEFINE_PROP_UINT16("queue-size", VhostVdpaDevice, queue_size, 0), - DEFINE_PROP_END_OF_LIST(), }; static const VMStateDescription vmstate_vhost_vdpa_device = { diff --git a/hw/virtio/vhost-scsi-pci.c b/hw/virtio/vhost-scsi-pci.c index 7536b37f18..3778f6131e 100644 --- a/hw/virtio/vhost-scsi-pci.c +++ b/hw/virtio/vhost-scsi-pci.c @@ -41,7 +41,6 @@ struct VHostSCSIPCI { static const Property vhost_scsi_pci_properties[] = { DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/vhost-user-blk-pci.c b/hw/virtio/vhost-user-blk-pci.c index 99f1472023..1767ef2c9c 100644 --- a/hw/virtio/vhost-user-blk-pci.c +++ b/hw/virtio/vhost-user-blk-pci.c @@ -47,7 +47,6 @@ static const Property vhost_user_blk_pci_properties[] = { DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_user_blk_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/vhost-user-device.c b/hw/virtio/vhost-user-device.c index 3222b67bd9..86eba138b4 100644 --- a/hw/virtio/vhost-user-device.c +++ b/hw/virtio/vhost-user-device.c @@ -35,7 +35,6 @@ static const Property vud_properties[] = { DEFINE_PROP_UINT32("vq_size", VHostUserBase, vq_size, 64), DEFINE_PROP_UINT32("num_vqs", VHostUserBase, num_vqs, 1), DEFINE_PROP_UINT32("config_size", VHostUserBase, config_size, 0), - DEFINE_PROP_END_OF_LIST(), }; static void vud_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/vhost-user-fs-pci.c b/hw/virtio/vhost-user-fs-pci.c index 9ba6c40655..116eaab907 100644 --- a/hw/virtio/vhost-user-fs-pci.c +++ b/hw/virtio/vhost-user-fs-pci.c @@ -32,7 +32,6 @@ DECLARE_INSTANCE_CHECKER(VHostUserFSPCI, VHOST_USER_FS_PCI, static const Property vhost_user_fs_pci_properties[] = { DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_user_fs_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/vhost-user-fs.c b/hw/virtio/vhost-user-fs.c index 83201ad232..3f00d79ed0 100644 --- a/hw/virtio/vhost-user-fs.c +++ b/hw/virtio/vhost-user-fs.c @@ -409,7 +409,6 @@ static const Property vuf_properties[] = { DEFINE_PROP_UINT16("num-request-queues", VHostUserFS, conf.num_request_queues, 1), DEFINE_PROP_UINT16("queue-size", VHostUserFS, conf.queue_size, 128), - DEFINE_PROP_END_OF_LIST(), }; static void vuf_instance_init(Object *obj) diff --git a/hw/virtio/vhost-user-gpio.c b/hw/virtio/vhost-user-gpio.c index c997c66d80..4a08814904 100644 --- a/hw/virtio/vhost-user-gpio.c +++ b/hw/virtio/vhost-user-gpio.c @@ -16,7 +16,6 @@ static const Property vgpio_properties[] = { DEFINE_PROP_CHR("chardev", VHostUserBase, chardev), - DEFINE_PROP_END_OF_LIST(), }; static void vgpio_realize(DeviceState *dev, Error **errp) diff --git a/hw/virtio/vhost-user-i2c.c b/hw/virtio/vhost-user-i2c.c index b0a5cbf3ea..1c7cde503c 100644 --- a/hw/virtio/vhost-user-i2c.c +++ b/hw/virtio/vhost-user-i2c.c @@ -16,7 +16,6 @@ static const Property vi2c_properties[] = { DEFINE_PROP_CHR("chardev", VHostUserBase, chardev), - DEFINE_PROP_END_OF_LIST(), }; static void vi2c_realize(DeviceState *dev, Error **errp) diff --git a/hw/virtio/vhost-user-input.c b/hw/virtio/vhost-user-input.c index c57cc461bb..917405329f 100644 --- a/hw/virtio/vhost-user-input.c +++ b/hw/virtio/vhost-user-input.c @@ -9,7 +9,6 @@ static const Property vinput_properties[] = { DEFINE_PROP_CHR("chardev", VHostUserBase, chardev), - DEFINE_PROP_END_OF_LIST(), }; static void vinput_realize(DeviceState *dev, Error **errp) diff --git a/hw/virtio/vhost-user-rng-pci.c b/hw/virtio/vhost-user-rng-pci.c index 0016ee74ce..a4e690148d 100644 --- a/hw/virtio/vhost-user-rng-pci.c +++ b/hw/virtio/vhost-user-rng-pci.c @@ -26,7 +26,6 @@ DECLARE_INSTANCE_CHECKER(VHostUserRNGPCI, VHOST_USER_RNG_PCI, static const Property vhost_user_rng_pci_properties[] = { DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_user_rng_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/vhost-user-rng.c b/hw/virtio/vhost-user-rng.c index c9985b5fad..5aa432e5e1 100644 --- a/hw/virtio/vhost-user-rng.c +++ b/hw/virtio/vhost-user-rng.c @@ -22,7 +22,6 @@ static const VMStateDescription vu_rng_vmstate = { static const Property vrng_properties[] = { DEFINE_PROP_CHR("chardev", VHostUserBase, chardev), - DEFINE_PROP_END_OF_LIST(), }; static void vu_rng_base_realize(DeviceState *dev, Error **errp) diff --git a/hw/virtio/vhost-user-scmi.c b/hw/virtio/vhost-user-scmi.c index a15e6916ef..410a936ca7 100644 --- a/hw/virtio/vhost-user-scmi.c +++ b/hw/virtio/vhost-user-scmi.c @@ -279,7 +279,6 @@ static const VMStateDescription vu_scmi_vmstate = { static const Property vu_scmi_properties[] = { DEFINE_PROP_CHR("chardev", VHostUserSCMI, chardev), - DEFINE_PROP_END_OF_LIST(), }; static void vu_scmi_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/vhost-user-scsi-pci.c b/hw/virtio/vhost-user-scsi-pci.c index 510981b39b..4a4128d961 100644 --- a/hw/virtio/vhost-user-scsi-pci.c +++ b/hw/virtio/vhost-user-scsi-pci.c @@ -47,7 +47,6 @@ struct VHostUserSCSIPCI { static const Property vhost_user_scsi_pci_properties[] = { DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_user_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/vhost-user-snd-pci.c b/hw/virtio/vhost-user-snd-pci.c index d61cfdae63..0cb86b7d85 100644 --- a/hw/virtio/vhost-user-snd-pci.c +++ b/hw/virtio/vhost-user-snd-pci.c @@ -23,10 +23,6 @@ typedef struct VHostUserSoundPCI VHostUserSoundPCI; DECLARE_INSTANCE_CHECKER(VHostUserSoundPCI, VHOST_USER_SND_PCI, TYPE_VHOST_USER_SND_PCI) -static Property vhost_user_snd_pci_properties[] = { - DEFINE_PROP_END_OF_LIST(), -}; - static void vhost_user_snd_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) { VHostUserSoundPCI *dev = VHOST_USER_SND_PCI(vpci_dev); @@ -44,7 +40,6 @@ static void vhost_user_snd_pci_class_init(ObjectClass *klass, void *data) PCIDeviceClass *pcidev_k = PCI_DEVICE_CLASS(klass); k->realize = vhost_user_snd_pci_realize; set_bit(DEVICE_CATEGORY_SOUND, dc->categories); - device_class_set_props(dc, vhost_user_snd_pci_properties); pcidev_k->vendor_id = PCI_VENDOR_ID_REDHAT_QUMRANET; pcidev_k->device_id = 0; /* Set by virtio-pci based on virtio id */ pcidev_k->revision = 0x00; diff --git a/hw/virtio/vhost-user-snd.c b/hw/virtio/vhost-user-snd.c index 8810a9f699..8610370af8 100644 --- a/hw/virtio/vhost-user-snd.c +++ b/hw/virtio/vhost-user-snd.c @@ -23,7 +23,6 @@ static const VMStateDescription vu_snd_vmstate = { static const Property vsnd_properties[] = { DEFINE_PROP_CHR("chardev", VHostUserBase, chardev), - DEFINE_PROP_END_OF_LIST(), }; static void vu_snd_base_realize(DeviceState *dev, Error **errp) diff --git a/hw/virtio/vhost-user-vsock-pci.c b/hw/virtio/vhost-user-vsock-pci.c index 529d967059..f730a05e78 100644 --- a/hw/virtio/vhost-user-vsock-pci.c +++ b/hw/virtio/vhost-user-vsock-pci.c @@ -33,7 +33,6 @@ struct VHostUserVSockPCI { static const Property vhost_user_vsock_pci_properties[] = { DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_user_vsock_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/vhost-user-vsock.c b/hw/virtio/vhost-user-vsock.c index 97885bfeab..293273080b 100644 --- a/hw/virtio/vhost-user-vsock.c +++ b/hw/virtio/vhost-user-vsock.c @@ -150,7 +150,6 @@ static void vuv_device_unrealize(DeviceState *dev) static const Property vuv_properties[] = { DEFINE_PROP_CHR("chardev", VHostUserVSock, conf.chardev), - DEFINE_PROP_END_OF_LIST(), }; static void vuv_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/vhost-vsock-common.c b/hw/virtio/vhost-vsock-common.c index cb2253c39f..9ac587d20c 100644 --- a/hw/virtio/vhost-vsock-common.c +++ b/hw/virtio/vhost-vsock-common.c @@ -288,7 +288,6 @@ static struct vhost_dev *vhost_vsock_common_get_vhost(VirtIODevice *vdev) static const Property vhost_vsock_common_properties[] = { DEFINE_PROP_ON_OFF_AUTO("seqpacket", VHostVSockCommon, seqpacket, ON_OFF_AUTO_AUTO), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_vsock_common_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/vhost-vsock-pci.c b/hw/virtio/vhost-vsock-pci.c index 1d9abd02bd..6c618ee908 100644 --- a/hw/virtio/vhost-vsock-pci.c +++ b/hw/virtio/vhost-vsock-pci.c @@ -37,7 +37,6 @@ struct VHostVSockPCI { static const Property vhost_vsock_pci_properties[] = { DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 3), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_vsock_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/vhost-vsock.c b/hw/virtio/vhost-vsock.c index ce80e84494..940b30fa27 100644 --- a/hw/virtio/vhost-vsock.c +++ b/hw/virtio/vhost-vsock.c @@ -208,7 +208,6 @@ static void vhost_vsock_device_unrealize(DeviceState *dev) static const Property vhost_vsock_properties[] = { DEFINE_PROP_UINT64("guest-cid", VHostVSock, conf.guest_cid, 0), DEFINE_PROP_STRING("vhostfd", VHostVSock, conf.vhostfd), - DEFINE_PROP_END_OF_LIST(), }; static void vhost_vsock_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/virtio-9p-pci.c b/hw/virtio/virtio-9p-pci.c index b33faf2fbb..aa1dce8f28 100644 --- a/hw/virtio/virtio-9p-pci.c +++ b/hw/virtio/virtio-9p-pci.c @@ -47,7 +47,6 @@ static const Property virtio_9p_pci_properties[] = { DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_9p_pci_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/virtio-balloon.c b/hw/virtio/virtio-balloon.c index e2ce18c258..ad05768ded 100644 --- a/hw/virtio/virtio-balloon.c +++ b/hw/virtio/virtio-balloon.c @@ -1032,7 +1032,6 @@ static const Property virtio_balloon_properties[] = { qemu_4_0_config_size, false), DEFINE_PROP_LINK("iothread", VirtIOBalloon, iothread, TYPE_IOTHREAD, IOThread *), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_balloon_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/virtio-blk-pci.c b/hw/virtio/virtio-blk-pci.c index abdcc11b2e..fc06cec656 100644 --- a/hw/virtio/virtio-blk-pci.c +++ b/hw/virtio/virtio-blk-pci.c @@ -44,7 +44,6 @@ static const Property virtio_blk_pci_properties[] = { VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_blk_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/virtio-crypto-pci.c b/hw/virtio/virtio-crypto-pci.c index 23c85fe586..8699481375 100644 --- a/hw/virtio/virtio-crypto-pci.c +++ b/hw/virtio/virtio-crypto-pci.c @@ -41,7 +41,6 @@ static const Property virtio_crypto_pci_properties[] = { DEFINE_PROP_BIT("ioeventfd", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_crypto_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/virtio-crypto.c b/hw/virtio/virtio-crypto.c index 74669145d2..a1b3c90618 100644 --- a/hw/virtio/virtio-crypto.c +++ b/hw/virtio/virtio-crypto.c @@ -1131,7 +1131,6 @@ static const VMStateDescription vmstate_virtio_crypto = { static const Property virtio_crypto_properties[] = { DEFINE_PROP_LINK("cryptodev", VirtIOCrypto, conf.cryptodev, TYPE_CRYPTODEV_BACKEND, CryptoDevBackend *), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_crypto_get_config(VirtIODevice *vdev, uint8_t *config) diff --git a/hw/virtio/virtio-input-pci.c b/hw/virtio/virtio-input-pci.c index 55c0b0555b..9e3c106777 100644 --- a/hw/virtio/virtio-input-pci.c +++ b/hw/virtio/virtio-input-pci.c @@ -39,7 +39,6 @@ struct VirtIOInputHIDPCI { static const Property virtio_input_pci_properties[] = { DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_input_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/virtio-iommu-pci.c b/hw/virtio/virtio-iommu-pci.c index 92adf63684..97e03ce803 100644 --- a/hw/virtio/virtio-iommu-pci.c +++ b/hw/virtio/virtio-iommu-pci.c @@ -39,7 +39,6 @@ static const Property virtio_iommu_pci_properties[] = { DEFINE_PROP_ARRAY("reserved-regions", VirtIOIOMMUPCI, vdev.nr_prop_resv_regions, vdev.prop_resv_regions, qdev_prop_reserved_region, ReservedRegion), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_iommu_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/virtio-iommu.c b/hw/virtio/virtio-iommu.c index 3d645a5339..f41104a952 100644 --- a/hw/virtio/virtio-iommu.c +++ b/hw/virtio/virtio-iommu.c @@ -1662,7 +1662,6 @@ static const Property virtio_iommu_properties[] = { DEFINE_PROP_GRANULE_MODE("granule", VirtIOIOMMU, granule_mode, GRANULE_MODE_HOST), DEFINE_PROP_UINT8("aw-bits", VirtIOIOMMU, aw_bits, 64), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_iommu_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/virtio-mem.c b/hw/virtio/virtio-mem.c index 80362a39f3..cf362a4aa5 100644 --- a/hw/virtio/virtio-mem.c +++ b/hw/virtio/virtio-mem.c @@ -1694,7 +1694,6 @@ static const Property virtio_mem_properties[] = { early_migration, true), DEFINE_PROP_BOOL(VIRTIO_MEM_DYNAMIC_MEMSLOTS_PROP, VirtIOMEM, dynamic_memslots, false), - DEFINE_PROP_END_OF_LIST(), }; static uint64_t virtio_mem_rdm_get_min_granularity(const RamDiscardManager *rdm, diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index 0bcb9a6faf..029817139b 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -757,7 +757,6 @@ static const Property virtio_mmio_properties[] = { DEFINE_PROP_BOOL("force-legacy", VirtIOMMIOProxy, legacy, true), DEFINE_PROP_BIT("ioeventfd", VirtIOMMIOProxy, flags, VIRTIO_IOMMIO_FLAG_USE_IOEVENTFD_BIT, true), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_mmio_realizefn(DeviceState *d, Error **errp) diff --git a/hw/virtio/virtio-net-pci.c b/hw/virtio/virtio-net-pci.c index e86094ae22..e18953ad67 100644 --- a/hw/virtio/virtio-net-pci.c +++ b/hw/virtio/virtio-net-pci.c @@ -43,7 +43,6 @@ static const Property virtio_net_properties[] = { VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_net_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/virtio-nsm.c b/hw/virtio/virtio-nsm.c index 685c548361..098e1aeac6 100644 --- a/hw/virtio/virtio-nsm.c +++ b/hw/virtio/virtio-nsm.c @@ -1707,7 +1707,6 @@ static const VMStateDescription vmstate_virtio_nsm = { static const Property virtio_nsm_properties[] = { DEFINE_PROP_STRING("module-id", VirtIONSM, module_id), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_nsm_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/virtio-pci.c b/hw/virtio/virtio-pci.c index ce2927e99b..c773a9130c 100644 --- a/hw/virtio/virtio-pci.c +++ b/hw/virtio/virtio-pci.c @@ -2378,7 +2378,6 @@ static const Property virtio_pci_properties[] = { VIRTIO_PCI_FLAG_INIT_FLR_BIT, true), DEFINE_PROP_BIT("aer", VirtIOPCIProxy, flags, VIRTIO_PCI_FLAG_AER_BIT, false), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_pci_dc_realize(DeviceState *qdev, Error **errp) @@ -2435,7 +2434,6 @@ static const Property virtio_pci_generic_properties[] = { DEFINE_PROP_ON_OFF_AUTO("disable-legacy", VirtIOPCIProxy, disable_legacy, ON_OFF_AUTO_AUTO), DEFINE_PROP_BOOL("disable-modern", VirtIOPCIProxy, disable_modern, false), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_pci_base_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/virtio-pmem.c b/hw/virtio/virtio-pmem.c index 4583e3ffe3..adb3268bd4 100644 --- a/hw/virtio/virtio-pmem.c +++ b/hw/virtio/virtio-pmem.c @@ -159,7 +159,6 @@ static const Property virtio_pmem_properties[] = { DEFINE_PROP_UINT64(VIRTIO_PMEM_ADDR_PROP, VirtIOPMEM, start, 0), DEFINE_PROP_LINK(VIRTIO_PMEM_MEMDEV_PROP, VirtIOPMEM, memdev, TYPE_MEMORY_BACKEND, HostMemoryBackend *), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_pmem_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/virtio-rng-pci.c b/hw/virtio/virtio-rng-pci.c index 398f432237..a94ff767b2 100644 --- a/hw/virtio/virtio-rng-pci.c +++ b/hw/virtio/virtio-rng-pci.c @@ -37,7 +37,6 @@ static const Property virtio_rng_properties[] = { VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_rng_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/virtio-rng.c b/hw/virtio/virtio-rng.c index a551c4c3a3..a515fc5cd9 100644 --- a/hw/virtio/virtio-rng.c +++ b/hw/virtio/virtio-rng.c @@ -258,7 +258,6 @@ static const Property virtio_rng_properties[] = { DEFINE_PROP_UINT64("max-bytes", VirtIORNG, conf.max_bytes, INT64_MAX), DEFINE_PROP_UINT32("period", VirtIORNG, conf.period_ms, 1 << 16), DEFINE_PROP_LINK("rng", VirtIORNG, conf.rng, TYPE_RNG_BACKEND, RngBackend *), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_rng_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/virtio-scsi-pci.c b/hw/virtio/virtio-scsi-pci.c index 733b5756db..d44fd2fffb 100644 --- a/hw/virtio/virtio-scsi-pci.c +++ b/hw/virtio/virtio-scsi-pci.c @@ -40,7 +40,6 @@ static const Property virtio_scsi_pci_properties[] = { VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, DEV_NVECTORS_UNSPECIFIED), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_scsi_pci_realize(VirtIOPCIProxy *vpci_dev, Error **errp) diff --git a/hw/virtio/virtio-serial-pci.c b/hw/virtio/virtio-serial-pci.c index bda643ec54..b5b77eb266 100644 --- a/hw/virtio/virtio-serial-pci.c +++ b/hw/virtio/virtio-serial-pci.c @@ -74,7 +74,6 @@ static const Property virtio_serial_pci_properties[] = { VIRTIO_PCI_FLAG_USE_IOEVENTFD_BIT, true), DEFINE_PROP_UINT32("vectors", VirtIOPCIProxy, nvectors, 2), DEFINE_PROP_UINT32("class", VirtIOPCIProxy, class_code, 0), - DEFINE_PROP_END_OF_LIST(), }; static void virtio_serial_pci_class_init(ObjectClass *klass, void *data) diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index f290c8ce7b..85110bce37 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -4018,7 +4018,6 @@ static const Property virtio_properties[] = { DEFINE_PROP_BOOL("use-disabled-flag", VirtIODevice, use_disabled_flag, true), DEFINE_PROP_BOOL("x-disable-legacy-check", VirtIODevice, disable_legacy_check, false), - DEFINE_PROP_END_OF_LIST(), }; static int virtio_device_start_ioeventfd_impl(VirtIODevice *vdev) diff --git a/hw/watchdog/sbsa_gwdt.c b/hw/watchdog/sbsa_gwdt.c index dd7e2a4708..65ac42a187 100644 --- a/hw/watchdog/sbsa_gwdt.c +++ b/hw/watchdog/sbsa_gwdt.c @@ -270,7 +270,6 @@ static const Property wdt_sbsa_gwdt_props[] = { */ DEFINE_PROP_UINT64("clock-frequency", struct SBSA_GWDTState, freq, 62500000), - DEFINE_PROP_END_OF_LIST(), }; static void wdt_sbsa_gwdt_class_init(ObjectClass *klass, void *data) diff --git a/hw/watchdog/wdt_aspeed.c b/hw/watchdog/wdt_aspeed.c index 9b86772cc1..81f5c5189a 100644 --- a/hw/watchdog/wdt_aspeed.c +++ b/hw/watchdog/wdt_aspeed.c @@ -291,7 +291,6 @@ static void aspeed_wdt_realize(DeviceState *dev, Error **errp) static const Property aspeed_wdt_properties[] = { DEFINE_PROP_LINK("scu", AspeedWDTState, scu, TYPE_ASPEED_SCU, AspeedSCUState *), - DEFINE_PROP_END_OF_LIST(), }; static void aspeed_wdt_class_init(ObjectClass *klass, void *data) diff --git a/hw/watchdog/wdt_imx2.c b/hw/watchdog/wdt_imx2.c index 3a4c15d1a4..18e40bd466 100644 --- a/hw/watchdog/wdt_imx2.c +++ b/hw/watchdog/wdt_imx2.c @@ -284,7 +284,6 @@ static void imx2_wdt_realize(DeviceState *dev, Error **errp) static const Property imx2_wdt_properties[] = { DEFINE_PROP_BOOL("pretimeout-support", IMX2WdtState, pretimeout_support, false), - DEFINE_PROP_END_OF_LIST() }; static void imx2_wdt_class_init(ObjectClass *klass, void *data) diff --git a/hw/xen/xen-bus.c b/hw/xen/xen-bus.c index 7919f8ef79..adfc4efad0 100644 --- a/hw/xen/xen-bus.c +++ b/hw/xen/xen-bus.c @@ -1095,7 +1095,6 @@ unrealize: static const Property xen_device_props[] = { DEFINE_PROP_UINT16("frontend-id", XenDevice, frontend_id, DOMID_INVALID), - DEFINE_PROP_END_OF_LIST() }; static void xen_device_class_init(ObjectClass *class, void *data) diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c index e8e1ee4f7d..118c571b3a 100644 --- a/hw/xen/xen-legacy-backend.c +++ b/hw/xen/xen-legacy-backend.c @@ -635,15 +635,10 @@ int xen_be_bind_evtchn(struct XenLegacyDevice *xendev) } -static Property xendev_properties[] = { - DEFINE_PROP_END_OF_LIST(), -}; - static void xendev_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - device_class_set_props(dc, xendev_properties); set_bit(DEVICE_CATEGORY_MISC, dc->categories); /* xen-backend devices can be plugged/unplugged dynamically */ dc->user_creatable = true; @@ -674,22 +669,10 @@ static const TypeInfo xensysbus_info = { } }; -static Property xen_sysdev_properties[] = { - {/* end of property list */}, -}; - -static void xen_sysdev_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - device_class_set_props(dc, xen_sysdev_properties); -} - static const TypeInfo xensysdev_info = { .name = TYPE_XENSYSDEV, .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(SysBusDevice), - .class_init = xen_sysdev_class_init, }; static void xenbe_register_types(void) diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index 557aa98be4..e2bd4c7d41 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -934,7 +934,6 @@ static void xen_pt_unregister_device(PCIDevice *d) static const Property xen_pci_passthrough_properties[] = { DEFINE_PROP_PCI_HOST_DEVADDR("hostaddr", XenPCIPassthroughState, hostaddr), DEFINE_PROP_BOOL("permissive", XenPCIPassthroughState, permissive, false), - DEFINE_PROP_END_OF_LIST(), }; static void xen_pci_passthrough_instance_init(Object *obj) diff --git a/include/hw/acpi/acpi-defs.h b/include/hw/acpi/acpi-defs.h index 0e6e82b339..2e6e341998 100644 --- a/include/hw/acpi/acpi-defs.h +++ b/include/hw/acpi/acpi-defs.h @@ -112,7 +112,6 @@ typedef struct AcpiSpcrData { uint8_t flow_control; uint8_t terminal_type; uint8_t language; - uint8_t reserved1; uint16_t pci_device_id; /* Must be 0xffff if not PCI device */ uint16_t pci_vendor_id; /* Must be 0xffff if not PCI device */ uint8_t pci_bus; @@ -120,7 +119,11 @@ typedef struct AcpiSpcrData { uint8_t pci_function; uint32_t pci_flags; uint8_t pci_segment; - uint32_t reserved2; + uint32_t uart_clk_freq; + uint32_t precise_baudrate; + uint32_t namespace_string_length; + uint32_t namespace_string_offset; + char namespace_string[]; } AcpiSpcrData; #define ACPI_FADT_ARM_PSCI_COMPLIANT (1 << 0) diff --git a/include/hw/acpi/aml-build.h b/include/hw/acpi/aml-build.h index 4fd5da49e7..c18f681342 100644 --- a/include/hw/acpi/aml-build.h +++ b/include/hw/acpi/aml-build.h @@ -507,5 +507,5 @@ void build_tpm2(GArray *table_data, BIOSLinker *linker, GArray *tcpalog, void build_spcr(GArray *table_data, BIOSLinker *linker, const AcpiSpcrData *f, const uint8_t rev, - const char *oem_id, const char *oem_table_id); + const char *oem_id, const char *oem_table_id, const char *name); #endif diff --git a/include/hw/intc/riscv_aplic.h b/include/hw/intc/riscv_aplic.h index de8532fbc3..489b9133c2 100644 --- a/include/hw/intc/riscv_aplic.h +++ b/include/hw/intc/riscv_aplic.h @@ -68,9 +68,17 @@ struct RISCVAPLICState { uint32_t num_irqs; bool msimode; bool mmode; + + /* To support KVM aia=aplic-imsic with irqchip split mode */ + bool kvm_splitmode; + uint32_t kvm_msicfgaddr; + uint32_t kvm_msicfgaddrH; }; void riscv_aplic_add_child(DeviceState *parent, DeviceState *child); +bool riscv_is_kvm_aia_aplic_imsic(bool msimode); +bool riscv_use_emulated_aplic(bool msimode); +void riscv_aplic_set_kvm_msicfgaddr(RISCVAPLICState *aplic, hwaddr addr); DeviceState *riscv_aplic_create(hwaddr addr, hwaddr size, uint32_t hartid_base, uint32_t num_harts, uint32_t num_sources, diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index 5be9844412..e6ef80b7fd 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -139,6 +139,12 @@ struct DeviceClass { const Property *props_; /** + * @props_count_: number of elements in @props_; should only be + * assigned by using device_class_set_props(). + */ + uint16_t props_count_; + + /** * @user_creatable: Can user instantiate with -device / device_add? * * All devices should support instantiation with device_add, and @@ -935,13 +941,38 @@ char *qdev_get_own_fw_dev_path_from_handler(BusState *bus, DeviceState *dev); /** * device_class_set_props(): add a set of properties to an device * @dc: the parent DeviceClass all devices inherit - * @props: an array of properties, terminate by DEFINE_PROP_END_OF_LIST() + * @props: an array of properties + * + * This will add a set of properties to the object. It will fault if + * you attempt to add an existing property defined by a parent class. + * To modify an inherited property you need to use???? + * + * Validate that @props has at least one Property. + * Validate that @props is an array, not a pointer, via ARRAY_SIZE. + * Validate that the array does not have a legacy terminator at compile-time; + * requires -O2 and the array to be const. + */ +#define device_class_set_props(dc, props) \ + do { \ + QEMU_BUILD_BUG_ON(sizeof(props) == 0); \ + size_t props_count_ = ARRAY_SIZE(props); \ + if ((props)[props_count_ - 1].name == NULL) { \ + qemu_build_not_reached(); \ + } \ + device_class_set_props_n((dc), (props), props_count_); \ + } while (0) + +/** + * device_class_set_props_n(): add a set of properties to an device + * @dc: the parent DeviceClass all devices inherit + * @props: an array of properties + * @n: ARRAY_SIZE(@props) * * This will add a set of properties to the object. It will fault if * you attempt to add an existing property defined by a parent class. * To modify an inherited property you need to use???? */ -void device_class_set_props(DeviceClass *dc, const Property *props); +void device_class_set_props_n(DeviceClass *dc, const Property *props, size_t n); /** * device_class_set_parent_realize() - set up for chaining realize fns diff --git a/include/hw/qdev-properties.h b/include/hw/qdev-properties.h index 26ebd23068..bf27375a3c 100644 --- a/include/hw/qdev-properties.h +++ b/include/hw/qdev-properties.h @@ -16,17 +16,17 @@ struct Property { const char *name; const PropertyInfo *info; ptrdiff_t offset; - uint8_t bitnr; + const char *link_type; uint64_t bitmask; - bool set_default; union { int64_t i; uint64_t u; } defval; - int arrayoffset; const PropertyInfo *arrayinfo; + int arrayoffset; int arrayfieldsize; - const char *link_type; + uint8_t bitnr; + bool set_default; }; struct PropertyInfo { @@ -34,7 +34,7 @@ struct PropertyInfo { const char *description; const QEnumLookup *enum_table; bool realized_set_allowed; /* allow setting property on realized device */ - int (*print)(Object *obj, Property *prop, char *dest, size_t len); + int (*print)(Object *obj, const Property *prop, char *dest, size_t len); void (*set_default_value)(ObjectProperty *op, const Property *prop); ObjectProperty *(*create)(ObjectClass *oc, const char *name, const Property *prop); @@ -171,9 +171,6 @@ extern const PropertyInfo qdev_prop_link; #define DEFINE_PROP_SIZE32(_n, _s, _f, _d) \ DEFINE_PROP_UNSIGNED(_n, _s, _f, _d, qdev_prop_size32, uint32_t) -#define DEFINE_PROP_END_OF_LIST() \ - {} - /* * Set properties between creation and realization. * @@ -204,7 +201,7 @@ void qdev_prop_set_enum(DeviceState *dev, const char *name, int value); /* Takes ownership of @values */ void qdev_prop_set_array(DeviceState *dev, const char *name, QList *values); -void *object_field_prop_ptr(Object *obj, Property *prop); +void *object_field_prop_ptr(Object *obj, const Property *prop); void qdev_prop_register_global(GlobalProperty *prop); const GlobalProperty *qdev_find_global_prop(Object *obj, diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index f778b560de..7d59b2e6c6 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -27,11 +27,23 @@ #define RISCV32_BIOS_BIN "opensbi-riscv32-generic-fw_dynamic.bin" #define RISCV64_BIOS_BIN "opensbi-riscv64-generic-fw_dynamic.bin" +typedef struct RISCVBootInfo { + ssize_t kernel_size; + hwaddr image_low_addr; + hwaddr image_high_addr; + + hwaddr initrd_start; + ssize_t initrd_size; + + bool is_32bit; +} RISCVBootInfo; + bool riscv_is_32bit(RISCVHartArrayState *harts); char *riscv_plic_hart_config_string(int hart_count); -target_ulong riscv_calc_kernel_start_addr(RISCVHartArrayState *harts, +void riscv_boot_info_init(RISCVBootInfo *info, RISCVHartArrayState *harts); +target_ulong riscv_calc_kernel_start_addr(RISCVBootInfo *info, target_ulong firmware_end_addr); target_ulong riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, @@ -43,13 +55,13 @@ char *riscv_find_firmware(const char *firmware_filename, target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr *firmware_load_addr, symbol_fn_t sym_cb); -target_ulong riscv_load_kernel(MachineState *machine, - RISCVHartArrayState *harts, - target_ulong firmware_end_addr, - bool load_initrd, - symbol_fn_t sym_cb); -uint64_t riscv_compute_fdt_addr(hwaddr dram_start, uint64_t dram_size, - MachineState *ms); +void riscv_load_kernel(MachineState *machine, + RISCVBootInfo *info, + target_ulong kernel_start_addr, + bool load_initrd, + symbol_fn_t sym_cb); +uint64_t riscv_compute_fdt_addr(hwaddr dram_base, hwaddr dram_size, + MachineState *ms, RISCVBootInfo *info); void riscv_load_fdt(hwaddr fdt_addr, void *fdt); void riscv_setup_rom_reset_vec(MachineState *machine, RISCVHartArrayState *harts, hwaddr saddr, diff --git a/include/hw/riscv/iommu.h b/include/hw/riscv/iommu.h index 80769a1400..b03339d75c 100644 --- a/include/hw/riscv/iommu.h +++ b/include/hw/riscv/iommu.h @@ -30,7 +30,15 @@ typedef struct RISCVIOMMUState RISCVIOMMUState; typedef struct RISCVIOMMUSpace RISCVIOMMUSpace; #define TYPE_RISCV_IOMMU_PCI "riscv-iommu-pci" -OBJECT_DECLARE_SIMPLE_TYPE(RISCVIOMMUStatePci, RISCV_IOMMU_PCI) +OBJECT_DECLARE_TYPE(RISCVIOMMUStatePci, RISCVIOMMUPciClass, RISCV_IOMMU_PCI) typedef struct RISCVIOMMUStatePci RISCVIOMMUStatePci; +typedef struct RISCVIOMMUPciClass RISCVIOMMUPciClass; + +#define TYPE_RISCV_IOMMU_SYS "riscv-iommu-device" +OBJECT_DECLARE_TYPE(RISCVIOMMUStateSys, RISCVIOMMUSysClass, RISCV_IOMMU_SYS) +typedef struct RISCVIOMMUStateSys RISCVIOMMUStateSys; +typedef struct RISCVIOMMUSysClass RISCVIOMMUSysClass; + +#define FDT_IRQ_TYPE_EDGE_LOW 1 #endif diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index c0dc41ff9a..48a14bea2e 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -62,6 +62,7 @@ struct RISCVVirtState { OnOffAuto acpi; const MemMapEntry *memmap; struct GPEXHost *gpex_host; + OnOffAuto iommu_sys; }; enum { @@ -84,7 +85,8 @@ enum { VIRT_PCIE_MMIO, VIRT_PCIE_PIO, VIRT_PLATFORM_BUS, - VIRT_PCIE_ECAM + VIRT_PCIE_ECAM, + VIRT_IOMMU_SYS, }; enum { @@ -93,6 +95,7 @@ enum { VIRTIO_IRQ = 1, /* 1 to 8 */ VIRTIO_COUNT = 8, PCIE_IRQ = 0x20, /* 32 to 35 */ + IOMMU_SYS_IRQ = 0x24, /* 36-39 */ VIRT_PLATFORM_BUS_IRQ = 64, /* 64 to 95 */ }; @@ -129,6 +132,7 @@ enum { 1 + FDT_APLIC_INT_CELLS) bool virt_is_acpi_enabled(RISCVVirtState *s); +bool virt_is_iommu_sys_enabled(RISCVVirtState *s); void virt_acpi_setup(RISCVVirtState *vms); uint32_t imsic_num_bits(uint32_t count); diff --git a/include/qemu/main-loop.h b/include/qemu/main-loop.h index 2d71f24cb3..4e2436b196 100644 --- a/include/qemu/main-loop.h +++ b/include/qemu/main-loop.h @@ -248,6 +248,14 @@ GSource *iohandler_get_g_source(void); AioContext *iohandler_get_aio_context(void); /** + * rust_bql_mock_lock: + * + * Called from Rust doctests to make bql_lock() return true. + * Do not touch. + */ +void rust_bql_mock_lock(void); + +/** * bql_locked: Return lock status of the Big QEMU Lock (BQL) * * The Big QEMU Lock (BQL) is the coarsest lock in QEMU, and as such it diff --git a/include/system/kvm.h b/include/system/kvm.h index c3a60b2890..ab17c09a55 100644 --- a/include/system/kvm.h +++ b/include/system/kvm.h @@ -377,6 +377,14 @@ int kvm_arch_init(MachineState *ms, KVMState *s); int kvm_arch_init_vcpu(CPUState *cpu); int kvm_arch_destroy_vcpu(CPUState *cpu); +#ifdef TARGET_KVM_HAVE_RESET_PARKED_VCPU +void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd); +#else +static inline void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd) +{ +} +#endif + bool kvm_vcpu_id_is_valid(int vcpu_id); /* Returns VCPU ID to be used on KVM_CREATE_VCPU ioctl() */ diff --git a/migration/migration.c b/migration/migration.c index b3e5156643..056a90daaf 100644 --- a/migration/migration.c +++ b/migration/migration.c @@ -3822,7 +3822,8 @@ static void migration_class_init(ObjectClass *klass, void *data) DeviceClass *dc = DEVICE_CLASS(klass); dc->user_creatable = false; - device_class_set_props(dc, migration_properties); + device_class_set_props_n(dc, migration_properties, + migration_properties_count); } static void migration_instance_finalize(Object *obj) diff --git a/migration/options.c b/migration/options.c index daac3c4514..b8d5300326 100644 --- a/migration/options.c +++ b/migration/options.c @@ -85,7 +85,7 @@ #define DEFAULT_MIGRATE_VCPU_DIRTY_LIMIT_PERIOD 1000 /* milliseconds */ #define DEFAULT_MIGRATE_VCPU_DIRTY_LIMIT 1 /* MB/s */ -Property migration_properties[] = { +const Property migration_properties[] = { DEFINE_PROP_BOOL("store-global-state", MigrationState, store_global_state, true), DEFINE_PROP_BOOL("send-configuration", MigrationState, @@ -196,8 +196,8 @@ Property migration_properties[] = { MIGRATION_CAPABILITY_SWITCHOVER_ACK), DEFINE_PROP_MIG_CAP("x-dirty-limit", MIGRATION_CAPABILITY_DIRTY_LIMIT), DEFINE_PROP_MIG_CAP("mapped-ram", MIGRATION_CAPABILITY_MAPPED_RAM), - DEFINE_PROP_END_OF_LIST(), }; +const size_t migration_properties_count = ARRAY_SIZE(migration_properties); bool migrate_auto_converge(void) { diff --git a/migration/options.h b/migration/options.h index 79084eed0d..762be4e641 100644 --- a/migration/options.h +++ b/migration/options.h @@ -20,7 +20,8 @@ /* migration properties */ -extern Property migration_properties[]; +extern const Property migration_properties[]; +extern const size_t migration_properties_count; /* capabilities */ diff --git a/rust/Cargo.toml b/rust/Cargo.toml index 6ec19b6729..5b6b6ca438 100644 --- a/rust/Cargo.toml +++ b/rust/Cargo.toml @@ -38,6 +38,7 @@ should_implement_trait = "deny" unused_self = "allow" # default-allow lints +as_ptr_cast_mut = "deny" as_underscore = "deny" assertions_on_result_states = "deny" bool_to_int_with_if = "deny" diff --git a/rust/hw/char/pl011/src/device.rs b/rust/hw/char/pl011/src/device.rs index 3e29442a62..18cc122951 100644 --- a/rust/hw/char/pl011/src/device.rs +++ b/rust/hw/char/pl011/src/device.rs @@ -11,11 +11,10 @@ use std::{ use qemu_api::{ bindings::{self, *}, c_str, - definitions::ObjectImpl, - device_class::DeviceImpl, - impl_device_class, irq::InterruptSource, prelude::*, + qdev::DeviceImpl, + qom::ObjectImpl, }; use crate::{ @@ -31,10 +30,8 @@ const IBRD_MASK: u32 = 0xffff; /// Fractional Baud Rate Divider, `UARTFBRD` const FBRD_MASK: u32 = 0x3f; -const DATA_BREAK: u32 = 1 << 10; - /// QEMU sourced constant. -pub const PL011_FIFO_DEPTH: usize = 16_usize; +pub const PL011_FIFO_DEPTH: u32 = 16; #[derive(Clone, Copy, Debug)] enum DeviceId { @@ -59,6 +56,32 @@ impl DeviceId { const PL011_ID_LUMINARY: [c_uchar; 8] = [0x11, 0x00, 0x18, 0x01, 0x0d, 0xf0, 0x05, 0xb1]; } +// FIFOs use 32-bit indices instead of usize, for compatibility with +// the migration stream produced by the C version of this device. +#[repr(transparent)] +#[derive(Debug, Default)] +pub struct Fifo([registers::Data; PL011_FIFO_DEPTH as usize]); + +impl Fifo { + const fn len(&self) -> u32 { + self.0.len() as u32 + } +} + +impl std::ops::IndexMut<u32> for Fifo { + fn index_mut(&mut self, idx: u32) -> &mut Self::Output { + &mut self.0[idx as usize] + } +} + +impl std::ops::Index<u32> for Fifo { + type Output = registers::Data; + + fn index(&self, idx: u32) -> &Self::Output { + &self.0[idx as usize] + } +} + #[repr(C)] #[derive(Debug, qemu_api_macros::Object, qemu_api_macros::offsets)] /// PL011 Device Model in QEMU @@ -76,14 +99,14 @@ pub struct PL011State { pub dmacr: u32, pub int_enabled: u32, pub int_level: u32, - pub read_fifo: [u32; PL011_FIFO_DEPTH], + pub read_fifo: Fifo, pub ilpr: u32, pub ibrd: u32, pub fbrd: u32, pub ifl: u32, - pub read_pos: usize, - pub read_count: usize, - pub read_trigger: usize, + pub read_pos: u32, + pub read_count: u32, + pub read_trigger: u32, #[doc(alias = "chr")] pub char_backend: CharBackend, /// QEMU interrupts @@ -107,8 +130,10 @@ pub struct PL011State { device_id: DeviceId, } +qom_isa!(PL011State : SysBusDevice, DeviceState, Object); + unsafe impl ObjectType for PL011State { - type Class = PL011Class; + type Class = <SysBusDevice as ObjectType>::Class; const TYPE_NAME: &'static CStr = crate::TYPE_PL011; } @@ -118,11 +143,6 @@ impl ObjectImpl for PL011State { const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = Some(Self::init); } -#[repr(C)] -pub struct PL011Class { - _inner: [u8; 0], -} - impl DeviceImpl for PL011State { fn properties() -> &'static [Property] { &device_class::PL011_PROPERTIES @@ -134,8 +154,6 @@ impl DeviceImpl for PL011State { const RESET: Option<fn(&mut Self)> = Some(Self::reset); } -impl_device_class!(PL011State); - impl PL011State { /// Initializes a pre-allocated, unitialized instance of `PL011State`. /// @@ -148,8 +166,6 @@ impl PL011State { unsafe fn init(&mut self) { const CLK_NAME: &CStr = c_str!("clk"); - let sbd = unsafe { &mut *(addr_of_mut!(*self).cast::<SysBusDevice>()) }; - // SAFETY: // // self and self.iomem are guaranteed to be valid at this point since callers @@ -163,15 +179,16 @@ impl PL011State { Self::TYPE_NAME.as_ptr(), 0x1000, ); + + let sbd: &mut SysBusDevice = self.upcast_mut(); sysbus_init_mmio(sbd, addr_of_mut!(self.iomem)); } for irq in self.interrupts.iter() { + let sbd: &SysBusDevice = self.upcast(); sbd.init_irq(irq); } - let dev = addr_of_mut!(*self).cast::<DeviceState>(); - // SAFETY: // // self.clock is not initialized at this point; but since `NonNull<_>` is Copy, @@ -180,6 +197,7 @@ impl PL011State { // calls this function to initialize the fields; therefore no code is // able to access an invalid self.clock value. unsafe { + let dev: &mut DeviceState = self.upcast_mut(); self.clock = NonNull::new(qdev_init_clock_in( dev, CLK_NAME.as_ptr(), @@ -194,9 +212,9 @@ impl PL011State { pub fn read(&mut self, offset: hwaddr, _size: c_uint) -> std::ops::ControlFlow<u64, u64> { use RegisterOffset::*; - std::ops::ControlFlow::Break(match RegisterOffset::try_from(offset) { + let value = match RegisterOffset::try_from(offset) { Err(v) if (0x3f8..0x400).contains(&(v >> 2)) => { - u64::from(self.device_id[(offset - 0xfe0) >> 2]) + u32::from(self.device_id[(offset - 0xfe0) >> 2]) } Err(_) => { // qemu_log_mask(LOG_GUEST_ERROR, "pl011_read: Bad offset 0x%x\n", (int)offset); @@ -216,32 +234,31 @@ impl PL011State { self.int_level &= !registers::INT_RX; } // Update error bits. - self.receive_status_error_clear = c.to_be_bytes()[3].into(); + self.receive_status_error_clear.set_from_data(c); self.update(); // Must call qemu_chr_fe_accept_input, so return Continue: - return std::ops::ControlFlow::Continue(c.into()); + let c = u32::from(c); + return std::ops::ControlFlow::Continue(u64::from(c)); } - Ok(RSR) => u8::from(self.receive_status_error_clear).into(), - Ok(FR) => u16::from(self.flags).into(), - Ok(FBRD) => self.fbrd.into(), - Ok(ILPR) => self.ilpr.into(), - Ok(IBRD) => self.ibrd.into(), - Ok(LCR_H) => u16::from(self.line_control).into(), - Ok(CR) => { - // We exercise our self-control. - u16::from(self.control).into() - } - Ok(FLS) => self.ifl.into(), - Ok(IMSC) => self.int_enabled.into(), - Ok(RIS) => self.int_level.into(), - Ok(MIS) => u64::from(self.int_level & self.int_enabled), + Ok(RSR) => u32::from(self.receive_status_error_clear), + Ok(FR) => u32::from(self.flags), + Ok(FBRD) => self.fbrd, + Ok(ILPR) => self.ilpr, + Ok(IBRD) => self.ibrd, + Ok(LCR_H) => u32::from(self.line_control), + Ok(CR) => u32::from(self.control), + Ok(FLS) => self.ifl, + Ok(IMSC) => self.int_enabled, + Ok(RIS) => self.int_level, + Ok(MIS) => self.int_level & self.int_enabled, Ok(ICR) => { // "The UARTICR Register is the interrupt clear register and is write-only" // Source: ARM DDI 0183G 3.3.13 Interrupt Clear Register, UARTICR 0 } - Ok(DMACR) => self.dmacr.into(), - }) + Ok(DMACR) => self.dmacr, + }; + std::ops::ControlFlow::Break(value.into()) } pub fn write(&mut self, offset: hwaddr, value: u64) { @@ -268,7 +285,7 @@ impl PL011State { self.update(); } Ok(RSR) => { - self.receive_status_error_clear = 0.into(); + self.receive_status_error_clear.reset(); } Ok(FR) => { // flag writes are ignored @@ -283,13 +300,11 @@ impl PL011State { self.fbrd = value; } Ok(LCR_H) => { - let value = value as u16; let new_val: registers::LineControl = value.into(); // Reset the FIFO state on FIFO enable or disable - if bool::from(self.line_control.fifos_enabled()) - ^ bool::from(new_val.fifos_enabled()) - { - self.reset_fifo(); + if self.line_control.fifos_enabled() != new_val.fifos_enabled() { + self.reset_rx_fifo(); + self.reset_tx_fifo(); } if self.line_control.send_break() ^ new_val.send_break() { let mut break_enable: c_int = new_val.send_break().into(); @@ -309,7 +324,6 @@ impl PL011State { } Ok(CR) => { // ??? Need to implement the enable bit. - let value = value as u16; self.control = value.into(); self.loopback_mdmctrl(); } @@ -411,7 +425,7 @@ impl PL011State { fn loopback_break(&mut self, enable: bool) { if enable { - self.loopback_tx(DATA_BREAK); + self.loopback_tx(registers::Data::BREAK.into()); } } @@ -448,16 +462,24 @@ impl PL011State { self.read_trigger = 1; self.ifl = 0x12; self.control.reset(); - self.flags = 0.into(); - self.reset_fifo(); + self.flags.reset(); + self.reset_rx_fifo(); + self.reset_tx_fifo(); } - pub fn reset_fifo(&mut self) { + pub fn reset_rx_fifo(&mut self) { self.read_count = 0; self.read_pos = 0; - /* Reset FIFO flags */ - self.flags.reset(); + // Reset FIFO flags + self.flags.set_receive_fifo_full(false); + self.flags.set_receive_fifo_empty(true); + } + + pub fn reset_tx_fifo(&mut self) { + // Reset FIFO flags + self.flags.set_transmit_fifo_full(false); + self.flags.set_transmit_fifo_empty(true); } pub fn can_receive(&self) -> bool { @@ -466,15 +488,14 @@ impl PL011State { } pub fn event(&mut self, event: QEMUChrEvent) { - if event == bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.fifo_enabled() { - self.put_fifo(DATA_BREAK); - self.receive_status_error_clear.set_break_error(true); + if event == bindings::QEMUChrEvent::CHR_EVENT_BREAK && !self.loopback_enabled() { + self.put_fifo(registers::Data::BREAK.into()); } } #[inline] pub fn fifo_enabled(&self) -> bool { - matches!(self.line_control.fifos_enabled(), registers::Mode::FIFO) + self.line_control.fifos_enabled() == registers::Mode::FIFO } #[inline] @@ -483,7 +504,7 @@ impl PL011State { } #[inline] - pub fn fifo_depth(&self) -> usize { + pub fn fifo_depth(&self) -> u32 { // Note: FIFO depth is expected to be power-of-2 if self.fifo_enabled() { return PL011_FIFO_DEPTH; @@ -495,7 +516,7 @@ impl PL011State { let depth = self.fifo_depth(); assert!(depth > 0); let slot = (self.read_pos + self.read_count) & (depth - 1); - self.read_fifo[slot] = value; + self.read_fifo[slot] = registers::Data::from(value); self.read_count += 1; self.flags.set_receive_fifo_empty(false); if self.read_count == depth { @@ -627,11 +648,6 @@ pub struct PL011Luminary { parent_obj: PL011State, } -#[repr(C)] -pub struct PL011LuminaryClass { - _inner: [u8; 0], -} - impl PL011Luminary { /// Initializes a pre-allocated, unitialized instance of `PL011Luminary`. /// @@ -645,8 +661,10 @@ impl PL011Luminary { } } +qom_isa!(PL011Luminary : PL011State, SysBusDevice, DeviceState, Object); + unsafe impl ObjectType for PL011Luminary { - type Class = PL011LuminaryClass; + type Class = <PL011State as ObjectType>::Class; const TYPE_NAME: &'static CStr = crate::TYPE_PL011_LUMINARY; } @@ -657,5 +675,3 @@ impl ObjectImpl for PL011Luminary { } impl DeviceImpl for PL011Luminary {} - -impl_device_class!(PL011Luminary); diff --git a/rust/hw/char/pl011/src/device_class.rs b/rust/hw/char/pl011/src/device_class.rs index 975c3d42be..7f3ca89507 100644 --- a/rust/hw/char/pl011/src/device_class.rs +++ b/rust/hw/char/pl011/src/device_class.rs @@ -6,8 +6,8 @@ use core::ptr::NonNull; use std::os::raw::{c_int, c_void}; use qemu_api::{ - bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_int32, vmstate_subsections, - vmstate_uint32, vmstate_uint32_array, vmstate_unused, zeroable::Zeroable, + bindings::*, c_str, vmstate_clock, vmstate_fields, vmstate_subsections, vmstate_uint32, + vmstate_uint32_array, vmstate_unused, zeroable::Zeroable, }; use crate::device::{PL011State, PL011_FIFO_DEPTH}; @@ -64,9 +64,9 @@ pub static VMSTATE_PL011: VMStateDescription = VMStateDescription { vmstate_uint32!(ibrd, PL011State), vmstate_uint32!(fbrd, PL011State), vmstate_uint32!(ifl, PL011State), - vmstate_int32!(read_pos, PL011State), - vmstate_int32!(read_count, PL011State), - vmstate_int32!(read_trigger, PL011State), + vmstate_uint32!(read_pos, PL011State), + vmstate_uint32!(read_count, PL011State), + vmstate_uint32!(read_trigger, PL011State), }, subsections: vmstate_subsections! { VMSTATE_PL011_CLOCK diff --git a/rust/hw/char/pl011/src/lib.rs b/rust/hw/char/pl011/src/lib.rs index 4dc0e8f345..69064d6929 100644 --- a/rust/hw/char/pl011/src/lib.rs +++ b/rust/hw/char/pl011/src/lib.rs @@ -131,14 +131,23 @@ impl core::convert::TryFrom<u64> for RegisterOffset { pub mod registers { //! Device registers exposed as typed structs which are backed by arbitrary //! integer bitmaps. [`Data`], [`Control`], [`LineControl`], etc. - //! - //! All PL011 registers are essentially 32-bit wide, but are typed here as - //! bitmaps with only the necessary width. That is, if a struct bitmap - //! in this module is for example 16 bits long, it should be conceived - //! as a 32-bit register where the unmentioned higher bits are always - //! unused thus treated as zero when read or written. use bilge::prelude::*; + /// Receive Status Register / Data Register common error bits + /// + /// The `UARTRSR` register is updated only when a read occurs + /// from the `UARTDR` register with the same status information + /// that can also be obtained by reading the `UARTDR` register + #[bitsize(8)] + #[derive(Clone, Copy, Default, DebugBits, FromBits)] + pub struct Errors { + pub framing_error: bool, + pub parity_error: bool, + pub break_error: bool, + pub overrun_error: bool, + _reserved_unpredictable: u4, + } + // TODO: FIFO Mode has different semantics /// Data Register, `UARTDR` /// @@ -181,16 +190,18 @@ pub mod registers { /// /// # Source /// ARM DDI 0183G 3.3.1 Data Register, UARTDR - #[bitsize(16)] - #[derive(Clone, Copy, DebugBits, FromBits)] + #[bitsize(32)] + #[derive(Clone, Copy, Default, DebugBits, FromBits)] #[doc(alias = "UARTDR")] pub struct Data { - _reserved: u4, pub data: u8, - pub framing_error: bool, - pub parity_error: bool, - pub break_error: bool, - pub overrun_error: bool, + pub errors: Errors, + _reserved: u16, + } + + impl Data { + // bilge is not very const-friendly, unfortunately + pub const BREAK: Self = Self { value: 1 << 10 }; } // TODO: FIFO Mode has different semantics @@ -217,20 +228,21 @@ pub mod registers { /// # Source /// ARM DDI 0183G 3.3.2 Receive Status Register/Error Clear Register, /// UARTRSR/UARTECR - #[bitsize(8)] + #[bitsize(32)] #[derive(Clone, Copy, DebugBits, FromBits)] pub struct ReceiveStatusErrorClear { - pub framing_error: bool, - pub parity_error: bool, - pub break_error: bool, - pub overrun_error: bool, - _reserved_unpredictable: u4, + pub errors: Errors, + _reserved_unpredictable: u24, } impl ReceiveStatusErrorClear { + pub fn set_from_data(&mut self, data: Data) { + self.set_errors(data.errors()); + } + pub fn reset(&mut self) { // All the bits are cleared to 0 on reset. - *self = 0.into(); + *self = Self::default(); } } @@ -240,7 +252,7 @@ pub mod registers { } } - #[bitsize(16)] + #[bitsize(32)] #[derive(Clone, Copy, DebugBits, FromBits)] /// Flag Register, `UARTFR` #[doc(alias = "UARTFR")] @@ -292,59 +304,45 @@ pub mod registers { pub transmit_fifo_empty: bool, /// `RI`, is `true` when `nUARTRI` is `LOW`. pub ring_indicator: bool, - _reserved_zero_no_modify: u7, + _reserved_zero_no_modify: u23, } impl Flags { pub fn reset(&mut self) { - // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1 - self.set_receive_fifo_full(false); - self.set_transmit_fifo_full(false); - self.set_busy(false); - self.set_receive_fifo_empty(true); - self.set_transmit_fifo_empty(true); + *self = Self::default(); } } impl Default for Flags { fn default() -> Self { let mut ret: Self = 0.into(); - ret.reset(); + // After reset TXFF, RXFF, and BUSY are 0, and TXFE and RXFE are 1 + ret.set_receive_fifo_empty(true); + ret.set_transmit_fifo_empty(true); ret } } - #[bitsize(16)] + #[bitsize(32)] #[derive(Clone, Copy, DebugBits, FromBits)] /// Line Control Register, `UARTLCR_H` #[doc(alias = "UARTLCR_H")] pub struct LineControl { - /// 15:8 - Reserved, do not modify, read as zero. - _reserved_zero_no_modify: u8, - /// 7 SPS Stick parity select. - /// 0 = stick parity is disabled - /// 1 = either: - /// • if the EPS bit is 0 then the parity bit is transmitted and checked - /// as a 1 • if the EPS bit is 1 then the parity bit is - /// transmitted and checked as a 0. This bit has no effect when - /// the PEN bit disables parity checking and generation. See Table 3-11 - /// on page 3-14 for the parity truth table. - pub sticky_parity: bool, - /// WLEN Word length. These bits indicate the number of data bits - /// transmitted or received in a frame as follows: b11 = 8 bits - /// b10 = 7 bits - /// b01 = 6 bits - /// b00 = 5 bits. - pub word_length: WordLength, - /// FEN Enable FIFOs: - /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become - /// 1-byte-deep holding registers 1 = transmit and receive FIFO - /// buffers are enabled (FIFO mode). - pub fifos_enabled: Mode, - /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits - /// are transmitted at the end of the frame. The receive - /// logic does not check for two stop bits being received. - pub two_stops_bits: bool, + /// BRK Send break. + /// + /// If this bit is set to `1`, a low-level is continually output on the + /// `UARTTXD` output, after completing transmission of the + /// current character. For the proper execution of the break command, + /// the software must set this bit for at least two complete + /// frames. For normal use, this bit must be cleared to `0`. + pub send_break: bool, + /// 1 PEN Parity enable: + /// + /// - 0 = parity is disabled and no parity bit added to the data frame + /// - 1 = parity checking and generation is enabled. + /// + /// See Table 3-11 on page 3-14 for the parity truth table. + pub parity_enabled: bool, /// EPS Even parity select. Controls the type of parity the UART uses /// during transmission and reception: /// - 0 = odd parity. The UART generates or checks for an odd number of @@ -355,21 +353,32 @@ pub mod registers { /// and generation. See Table 3-11 on page 3-14 for the parity /// truth table. pub parity: Parity, - /// 1 PEN Parity enable: - /// - /// - 0 = parity is disabled and no parity bit added to the data frame - /// - 1 = parity checking and generation is enabled. - /// - /// See Table 3-11 on page 3-14 for the parity truth table. - pub parity_enabled: bool, - /// BRK Send break. - /// - /// If this bit is set to `1`, a low-level is continually output on the - /// `UARTTXD` output, after completing transmission of the - /// current character. For the proper execution of the break command, - /// the software must set this bit for at least two complete - /// frames. For normal use, this bit must be cleared to `0`. - pub send_break: bool, + /// 3 STP2 Two stop bits select. If this bit is set to 1, two stop bits + /// are transmitted at the end of the frame. The receive + /// logic does not check for two stop bits being received. + pub two_stops_bits: bool, + /// FEN Enable FIFOs: + /// 0 = FIFOs are disabled (character mode) that is, the FIFOs become + /// 1-byte-deep holding registers 1 = transmit and receive FIFO + /// buffers are enabled (FIFO mode). + pub fifos_enabled: Mode, + /// WLEN Word length. These bits indicate the number of data bits + /// transmitted or received in a frame as follows: b11 = 8 bits + /// b10 = 7 bits + /// b01 = 6 bits + /// b00 = 5 bits. + pub word_length: WordLength, + /// 7 SPS Stick parity select. + /// 0 = stick parity is disabled + /// 1 = either: + /// • if the EPS bit is 0 then the parity bit is transmitted and checked + /// as a 1 • if the EPS bit is 1 then the parity bit is + /// transmitted and checked as a 0. This bit has no effect when + /// the PEN bit disables parity checking and generation. See Table 3-11 + /// on page 3-14 for the parity truth table. + pub sticky_parity: bool, + /// 31:8 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify: u24, } impl LineControl { @@ -410,12 +419,6 @@ pub mod registers { FIFO = 1, } - impl From<Mode> for bool { - fn from(val: Mode) -> Self { - matches!(val, Mode::FIFO) - } - } - #[bitsize(2)] #[derive(Clone, Copy, Debug, Eq, FromBits, PartialEq)] /// `WLEN` Word length, field of [Line Control register](LineControl). @@ -440,7 +443,7 @@ pub mod registers { /// /// # Source /// ARM DDI 0183G, 3.3.8 Control Register, `UARTCR`, Table 3-12 - #[bitsize(16)] + #[bitsize(32)] #[doc(alias = "UARTCR")] #[derive(Clone, Copy, DebugBits, FromBits)] pub struct Control { @@ -518,6 +521,8 @@ pub mod registers { /// CTS hardware flow control is enabled. Data is only transmitted when /// the `nUARTCTS` signal is asserted. pub cts_hardware_flow_control_enable: bool, + /// 31:16 - Reserved, do not modify, read as zero. + _reserved_zero_no_modify2: u16, } impl Control { diff --git a/rust/qemu-api-macros/src/lib.rs b/rust/qemu-api-macros/src/lib.rs index cf99ac04b8..74a8bc7503 100644 --- a/rust/qemu-api-macros/src/lib.rs +++ b/rust/qemu-api-macros/src/lib.rs @@ -40,7 +40,7 @@ pub fn derive_object(input: TokenStream) -> TokenStream { let expanded = quote! { ::qemu_api::module_init! { MODULE_INIT_QOM => unsafe { - ::qemu_api::bindings::type_register_static(&<#name as ::qemu_api::definitions::ObjectImpl>::TYPE_INFO); + ::qemu_api::bindings::type_register_static(&<#name as ::qemu_api::qom::ObjectImpl>::TYPE_INFO); } } }; diff --git a/rust/qemu-api/meson.build b/rust/qemu-api/meson.build index adcee66115..ccb20f38c1 100644 --- a/rust/qemu-api/meson.build +++ b/rust/qemu-api/meson.build @@ -17,13 +17,15 @@ _qemu_api_rs = static_library( 'src/lib.rs', 'src/bindings.rs', 'src/bitops.rs', + 'src/callbacks.rs', 'src/cell.rs', 'src/c_str.rs', - 'src/definitions.rs', - 'src/device_class.rs', 'src/irq.rs', + 'src/module.rs', 'src/offset_of.rs', 'src/prelude.rs', + 'src/qdev.rs', + 'src/qom.rs', 'src/sysbus.rs', 'src/vmstate.rs', 'src/zeroable.rs', @@ -59,7 +61,7 @@ test('rust-qemu-api-integration', dependencies: [qemu_api, qemu_api_macros], link_whole: [rust_qemu_api_objs, libqemuutil]), args: [ - '--test', + '--test', '--test-threads', '1', '--format', 'pretty', ], protocol: 'rust', diff --git a/rust/qemu-api/src/callbacks.rs b/rust/qemu-api/src/callbacks.rs new file mode 100644 index 0000000000..314f9dce96 --- /dev/null +++ b/rust/qemu-api/src/callbacks.rs @@ -0,0 +1,144 @@ +// SPDX-License-Identifier: MIT + +//! Utility functions to deal with callbacks from C to Rust. + +use std::{mem, ptr::NonNull}; + +/// Trait for functions (types implementing [`Fn`]) that can be used as +/// callbacks. These include both zero-capture closures and function pointers. +/// +/// In Rust, calling a function through the `Fn` trait normally requires a +/// `self` parameter, even though for zero-sized functions (including function +/// pointers) the type itself contains all necessary information to call the +/// function. This trait provides a `call` function that doesn't require `self`, +/// allowing zero-sized functions to be called using only their type. +/// +/// This enables zero-sized functions to be passed entirely through generic +/// parameters and resolved at compile-time. A typical use is a function +/// receiving an unused parameter of generic type `F` and calling it via +/// `F::call` or passing it to another function via `func::<F>`. +/// +/// QEMU uses this trick to create wrappers to C callbacks. The wrappers +/// are needed to convert an opaque `*mut c_void` into a Rust reference, +/// but they only have a single opaque that they can use. The `FnCall` +/// trait makes it possible to use that opaque for `self` or any other +/// reference: +/// +/// ```ignore +/// // The compiler creates a new `rust_bh_cb` wrapper for each function +/// // passed to `qemu_bh_schedule_oneshot` below. +/// unsafe extern "C" fn rust_bh_cb<T, F: for<'a> FnCall<(&'a T,)>>( +/// opaque: *mut c_void, +/// ) { +/// // SAFETY: the opaque was passed as a reference to `T`. +/// F::call((unsafe { &*(opaque.cast::<T>()) }, )) +/// } +/// +/// // The `_f` parameter is unused but it helps the compiler build the appropriate `F`. +/// // Using a reference allows usage in const context. +/// fn qemu_bh_schedule_oneshot<T, F: for<'a> FnCall<(&'a T,)>>(_f: &F, opaque: &T) { +/// let cb: unsafe extern "C" fn(*mut c_void) = rust_bh_cb::<T, F>; +/// unsafe { +/// bindings::qemu_bh_schedule_oneshot(cb, opaque as *const T as *const c_void as *mut c_void) +/// } +/// } +/// ``` +/// +/// Each wrapper is a separate instance of `rust_bh_cb` and is therefore +/// compiled to a separate function ("monomorphization"). If you wanted +/// to pass `self` as the opaque value, the generic parameters would be +/// `rust_bh_cb::<Self, F>`. +/// +/// `Args` is a tuple type whose types are the arguments of the function, +/// while `R` is the returned type. +/// +/// # Examples +/// +/// ``` +/// # use qemu_api::callbacks::FnCall; +/// fn call_it<F: for<'a> FnCall<(&'a str,), String>>(_f: &F, s: &str) -> String { +/// F::call((s,)) +/// } +/// +/// let s: String = call_it(&str::to_owned, "hello world"); +/// assert_eq!(s, "hello world"); +/// ``` +/// +/// Note that the compiler will produce a different version of `call_it` for +/// each function that is passed to it. Therefore the argument is not really +/// used, except to decide what is `F` and what `F::call` does. +/// +/// Attempting to pass a non-zero-sized closure causes a compile-time failure: +/// +/// ```compile_fail +/// # use qemu_api::callbacks::FnCall; +/// # fn call_it<'a, F: FnCall<(&'a str,), String>>(_f: &F, s: &'a str) -> String { +/// # F::call((s,)) +/// # } +/// let x: &'static str = "goodbye world"; +/// call_it(&move |_| String::from(x), "hello workd"); +/// ``` +/// +/// # Safety +/// +/// Because `Self` is a zero-sized type, all instances of the type are +/// equivalent. However, in addition to this, `Self` must have no invariants +/// that could be violated by creating a reference to it. +/// +/// This is always true for zero-capture closures and function pointers, as long +/// as the code is able to name the function in the first place. +pub unsafe trait FnCall<Args, R = ()>: 'static + Sync + Sized { + /// Referring to this internal constant asserts that the `Self` type is + /// zero-sized. Can be replaced by an inline const expression in + /// Rust 1.79.0+. + const ASSERT_ZERO_SIZED: () = { assert!(mem::size_of::<Self>() == 0) }; + + /// Call the function with the arguments in args. + fn call(a: Args) -> R; +} + +macro_rules! impl_call { + ($($args:ident,)* ) => ( + // SAFETY: because each function is treated as a separate type, + // accessing `FnCall` is only possible in code that would be + // allowed to call the function. + unsafe impl<F, $($args,)* R> FnCall<($($args,)*), R> for F + where + F: 'static + Sync + Sized + Fn($($args, )*) -> R, + { + #[inline(always)] + fn call(a: ($($args,)*)) -> R { + let _: () = Self::ASSERT_ZERO_SIZED; + + // SAFETY: the safety of this method is the condition for implementing + // `FnCall`. As to the `NonNull` idiom to create a zero-sized type, + // see https://github.com/rust-lang/libs-team/issues/292. + let f: &'static F = unsafe { &*NonNull::<Self>::dangling().as_ptr() }; + let ($($args,)*) = a; + f($($args,)*) + } + } + ) +} + +impl_call!(_1, _2, _3, _4, _5,); +impl_call!(_1, _2, _3, _4,); +impl_call!(_1, _2, _3,); +impl_call!(_1, _2,); +impl_call!(_1,); +impl_call!(); + +#[cfg(test)] +mod tests { + use super::*; + + // The `_f` parameter is unused but it helps the compiler infer `F`. + fn do_test_call<'a, F: FnCall<(&'a str,), String>>(_f: &F) -> String { + F::call(("hello world",)) + } + + #[test] + fn test_call() { + assert_eq!(do_test_call(&str::to_owned), "hello world") + } +} diff --git a/rust/qemu-api/src/cell.rs b/rust/qemu-api/src/cell.rs index 28349de291..eae4e2ce78 100644 --- a/rust/qemu-api/src/cell.rs +++ b/rust/qemu-api/src/cell.rs @@ -124,9 +124,18 @@ use std::{ use crate::bindings; -// TODO: When building doctests do not include the actual BQL, because cargo -// does not know how to link them to libqemuutil. This can be fixed by -// running rustdoc from "meson test" instead of relying on cargo. +/// An internal function that is used by doctests. +pub fn bql_start_test() { + if cfg!(MESON) { + // SAFETY: integration tests are run with --test-threads=1, while + // unit tests and doctests are not multithreaded and do not have + // any BQL-protected data. Just set bql_locked to true. + unsafe { + bindings::rust_bql_mock_lock(); + } + } +} + pub fn bql_locked() -> bool { // SAFETY: the function does nothing but return a thread-local bool !cfg!(MESON) || unsafe { bindings::bql_locked() } @@ -220,6 +229,7 @@ impl<T> BqlCell<T> { /// /// ``` /// use qemu_api::cell::BqlCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlCell::new(5); /// ``` @@ -236,6 +246,7 @@ impl<T> BqlCell<T> { /// /// ``` /// use qemu_api::cell::BqlCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlCell::new(5); /// @@ -253,6 +264,7 @@ impl<T> BqlCell<T> { /// /// ``` /// use qemu_api::cell::BqlCell; + /// # qemu_api::cell::bql_start_test(); /// /// let cell = BqlCell::new(5); /// assert_eq!(cell.get(), 5); @@ -274,6 +286,7 @@ impl<T> BqlCell<T> { /// /// ``` /// use qemu_api::cell::BqlCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlCell::new(5); /// let five = c.into_inner(); @@ -293,6 +306,7 @@ impl<T: Copy> BqlCell<T> { /// /// ``` /// use qemu_api::cell::BqlCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlCell::new(5); /// @@ -315,6 +329,7 @@ impl<T> BqlCell<T> { /// /// ``` /// use qemu_api::cell::BqlCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlCell::new(5); /// @@ -333,6 +348,7 @@ impl<T: Default> BqlCell<T> { /// /// ``` /// use qemu_api::cell::BqlCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlCell::new(5); /// let five = c.take(); @@ -461,6 +477,7 @@ impl<T> BqlRefCell<T> { /// /// ``` /// use qemu_api::cell::BqlRefCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlRefCell::new(5); /// @@ -472,6 +489,7 @@ impl<T> BqlRefCell<T> { /// /// ```should_panic /// use qemu_api::cell::BqlRefCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlRefCell::new(5); /// @@ -513,6 +531,7 @@ impl<T> BqlRefCell<T> { /// /// ``` /// use qemu_api::cell::BqlRefCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlRefCell::new("hello".to_owned()); /// @@ -525,6 +544,7 @@ impl<T> BqlRefCell<T> { /// /// ```should_panic /// use qemu_api::cell::BqlRefCell; + /// # qemu_api::cell::bql_start_test(); /// /// let c = BqlRefCell::new(5); /// let m = c.borrow(); diff --git a/rust/qemu-api/src/definitions.rs b/rust/qemu-api/src/definitions.rs deleted file mode 100644 index df91a2e31a..0000000000 --- a/rust/qemu-api/src/definitions.rs +++ /dev/null @@ -1,168 +0,0 @@ -// Copyright 2024, Linaro Limited -// Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org> -// SPDX-License-Identifier: GPL-2.0-or-later - -//! Definitions required by QEMU when registering a device. - -use std::{ffi::CStr, os::raw::c_void}; - -use crate::bindings::{Object, ObjectClass, TypeInfo}; - -unsafe extern "C" fn rust_instance_init<T: ObjectImpl>(obj: *mut Object) { - // SAFETY: obj is an instance of T, since rust_instance_init<T> - // is called from QOM core as the instance_init function - // for class T - unsafe { T::INSTANCE_INIT.unwrap()(&mut *obj.cast::<T>()) } -} - -unsafe extern "C" fn rust_instance_post_init<T: ObjectImpl>(obj: *mut Object) { - // SAFETY: obj is an instance of T, since rust_instance_post_init<T> - // is called from QOM core as the instance_post_init function - // for class T - // - // FIXME: it's not really guaranteed that there are no backpointers to - // obj; it's quite possible that they have been created by instance_init(). - // The receiver should be &self, not &mut self. - T::INSTANCE_POST_INIT.unwrap()(unsafe { &mut *obj.cast::<T>() }) -} - -/// Trait exposed by all structs corresponding to QOM objects. -/// -/// # Safety -/// -/// For classes declared in C: -/// -/// - `Class` and `TYPE` must match the data in the `TypeInfo`; -/// -/// - the first field of the struct must be of the instance type corresponding -/// to the superclass, as declared in the `TypeInfo` -/// -/// - likewise, the first field of the `Class` struct must be of the class type -/// corresponding to the superclass -/// -/// For classes declared in Rust and implementing [`ObjectImpl`]: -/// -/// - the struct must be `#[repr(C)]`; -/// -/// - the first field of the struct must be of the instance struct corresponding -/// to the superclass, which is `ObjectImpl::ParentType` -/// -/// - likewise, the first field of the `Class` must be of the class struct -/// corresponding to the superclass, which is `ObjectImpl::ParentType::Class`. -pub unsafe trait ObjectType: Sized { - /// The QOM class object corresponding to this struct. Not used yet. - type Class; - - /// The name of the type, which can be passed to `object_new()` to - /// generate an instance of this type. - const TYPE_NAME: &'static CStr; -} - -/// Trait a type must implement to be registered with QEMU. -pub trait ObjectImpl: ObjectType + ClassInitImpl { - /// The parent of the type. This should match the first field of - /// the struct that implements `ObjectImpl`: - type ParentType: ObjectType; - - /// Whether the object can be instantiated - const ABSTRACT: bool = false; - const INSTANCE_FINALIZE: Option<unsafe extern "C" fn(obj: *mut Object)> = None; - - /// Function that is called to initialize an object. The parent class will - /// have already been initialized so the type is only responsible for - /// initializing its own members. - /// - /// FIXME: The argument is not really a valid reference. `&mut - /// MaybeUninit<Self>` would be a better description. - const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = None; - - /// Function that is called to finish initialization of an object, once - /// `INSTANCE_INIT` functions have been called. - const INSTANCE_POST_INIT: Option<fn(&mut Self)> = None; - - const TYPE_INFO: TypeInfo = TypeInfo { - name: Self::TYPE_NAME.as_ptr(), - parent: Self::ParentType::TYPE_NAME.as_ptr(), - instance_size: core::mem::size_of::<Self>(), - instance_align: core::mem::align_of::<Self>(), - instance_init: match Self::INSTANCE_INIT { - None => None, - Some(_) => Some(rust_instance_init::<Self>), - }, - instance_post_init: match Self::INSTANCE_POST_INIT { - None => None, - Some(_) => Some(rust_instance_post_init::<Self>), - }, - instance_finalize: Self::INSTANCE_FINALIZE, - abstract_: Self::ABSTRACT, - class_size: core::mem::size_of::<Self::Class>(), - class_init: <Self as ClassInitImpl>::CLASS_INIT, - class_base_init: <Self as ClassInitImpl>::CLASS_BASE_INIT, - class_data: core::ptr::null_mut(), - interfaces: core::ptr::null_mut(), - }; -} - -/// Trait used to fill in a class struct. -/// -/// Each QOM class that has virtual methods describes them in a -/// _class struct_. Class structs include a parent field corresponding -/// to the vtable of the parent class, all the way up to [`ObjectClass`]. -/// Each QOM type has one such class struct. -/// -/// The Rust implementation of methods will usually come from a trait -/// like [`ObjectImpl`] or [`DeviceImpl`](crate::device_class::DeviceImpl). -pub trait ClassInitImpl { - /// Function that is called after all parent class initialization - /// has occurred. On entry, the virtual method pointers are set to - /// the default values coming from the parent classes; the function - /// can change them to override virtual methods of a parent class. - const CLASS_INIT: Option<unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut c_void)>; - - /// Called on descendent classes after all parent class initialization - /// has occurred, but before the class itself is initialized. This - /// is only useful if a class is not a leaf, and can be used to undo - /// the effects of copying the contents of the parent's class struct - /// to the descendants. - const CLASS_BASE_INIT: Option< - unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut c_void), - >; -} - -#[macro_export] -macro_rules! module_init { - ($type:ident => $body:block) => { - const _: () = { - #[used] - #[cfg_attr( - not(any(target_vendor = "apple", target_os = "windows")), - link_section = ".init_array" - )] - #[cfg_attr(target_vendor = "apple", link_section = "__DATA,__mod_init_func")] - #[cfg_attr(target_os = "windows", link_section = ".CRT$XCU")] - pub static LOAD_MODULE: extern "C" fn() = { - extern "C" fn init_fn() { - $body - } - - extern "C" fn ctor_fn() { - unsafe { - $crate::bindings::register_module_init( - Some(init_fn), - $crate::bindings::module_init_type::$type, - ); - } - } - - ctor_fn - }; - }; - }; - - // shortcut because it's quite common that $body needs unsafe {} - ($type:ident => unsafe $body:block) => { - $crate::module_init! { - $type => { unsafe { $body } } - } - }; -} diff --git a/rust/qemu-api/src/lib.rs b/rust/qemu-api/src/lib.rs index 9e007e1635..4b43e02c0f 100644 --- a/rust/qemu-api/src/lib.rs +++ b/rust/qemu-api/src/lib.rs @@ -14,11 +14,13 @@ pub mod prelude; pub mod bitops; pub mod c_str; +pub mod callbacks; pub mod cell; -pub mod definitions; -pub mod device_class; pub mod irq; +pub mod module; pub mod offset_of; +pub mod qdev; +pub mod qom; pub mod sysbus; pub mod vmstate; pub mod zeroable; diff --git a/rust/qemu-api/src/module.rs b/rust/qemu-api/src/module.rs new file mode 100644 index 0000000000..fa5cea3598 --- /dev/null +++ b/rust/qemu-api/src/module.rs @@ -0,0 +1,43 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org> +// SPDX-License-Identifier: GPL-2.0-or-later + +//! Macro to register blocks of code that run as QEMU starts up. + +#[macro_export] +macro_rules! module_init { + ($type:ident => $body:block) => { + const _: () = { + #[used] + #[cfg_attr( + not(any(target_vendor = "apple", target_os = "windows")), + link_section = ".init_array" + )] + #[cfg_attr(target_vendor = "apple", link_section = "__DATA,__mod_init_func")] + #[cfg_attr(target_os = "windows", link_section = ".CRT$XCU")] + pub static LOAD_MODULE: extern "C" fn() = { + extern "C" fn init_fn() { + $body + } + + extern "C" fn ctor_fn() { + unsafe { + $crate::bindings::register_module_init( + Some(init_fn), + $crate::bindings::module_init_type::$type, + ); + } + } + + ctor_fn + }; + }; + }; + + // shortcut because it's quite common that $body needs unsafe {} + ($type:ident => unsafe $body:block) => { + $crate::module_init! { + $type => { unsafe { $body } } + } + }; +} diff --git a/rust/qemu-api/src/prelude.rs b/rust/qemu-api/src/prelude.rs index 1b8677b2d9..6f32deeb2e 100644 --- a/rust/qemu-api/src/prelude.rs +++ b/rust/qemu-api/src/prelude.rs @@ -7,4 +7,12 @@ pub use crate::bitops::IntegerExt; pub use crate::cell::BqlCell; pub use crate::cell::BqlRefCell; -pub use crate::definitions::ObjectType; +pub use crate::qom::IsA; +pub use crate::qom::Object; +pub use crate::qom::ObjectCast; +pub use crate::qom::ObjectCastMut; +pub use crate::qom::ObjectDeref; +pub use crate::qom::ObjectMethods; +pub use crate::qom::ObjectType; + +pub use crate::qom_isa; diff --git a/rust/qemu-api/src/device_class.rs b/rust/qemu-api/src/qdev.rs index 03d03feee8..686054e737 100644 --- a/rust/qemu-api/src/device_class.rs +++ b/rust/qemu-api/src/qdev.rs @@ -2,12 +2,17 @@ // Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org> // SPDX-License-Identifier: GPL-2.0-or-later -use std::{ffi::CStr, os::raw::c_void}; +//! Bindings to create devices and access device functionality from Rust. + +use std::ffi::CStr; + +pub use bindings::{DeviceClass, DeviceState, Property}; use crate::{ - bindings::{self, DeviceClass, DeviceState, Error, ObjectClass, Property, VMStateDescription}, + bindings::{self, Error}, prelude::*, - zeroable::Zeroable, + qom::{ClassInitImpl, ObjectClass}, + vmstate::VMStateDescription, }; /// Trait providing the contents of [`DeviceClass`]. @@ -31,7 +36,7 @@ pub trait DeviceImpl { /// device. Not a `const` because referencing statics in constants /// is unstable until Rust 1.83.0. fn properties() -> &'static [Property] { - &[Zeroable::ZERO; 1] + &[] } /// A `VMStateDescription` providing the migration format for the device @@ -45,7 +50,7 @@ pub trait DeviceImpl { /// # Safety /// /// This function is only called through the QOM machinery and -/// the `impl_device_class!` macro. +/// used by the `ClassInitImpl<DeviceClass>` trait. /// We expect the FFI user of this function to pass a valid pointer that /// can be downcasted to type `T`. We also expect the device is /// readable/writeable from one thread at any time. @@ -66,43 +71,31 @@ unsafe extern "C" fn rust_reset_fn<T: DeviceImpl>(dev: *mut DeviceState) { T::RESET.unwrap()(unsafe { &mut *state }); } -/// # Safety -/// -/// We expect the FFI user of this function to pass a valid pointer that -/// can be downcasted to type `DeviceClass`, because `T` implements -/// `DeviceImpl`. -pub unsafe extern "C" fn rust_device_class_init<T: DeviceImpl>( - klass: *mut ObjectClass, - _: *mut c_void, -) { - let mut dc = ::core::ptr::NonNull::new(klass.cast::<DeviceClass>()).unwrap(); - unsafe { - let dc = dc.as_mut(); +impl<T> ClassInitImpl<DeviceClass> for T +where + T: ClassInitImpl<ObjectClass> + DeviceImpl, +{ + fn class_init(dc: &mut DeviceClass) { if <T as DeviceImpl>::REALIZE.is_some() { dc.realize = Some(rust_realize_fn::<T>); } if <T as DeviceImpl>::RESET.is_some() { - bindings::device_class_set_legacy_reset(dc, Some(rust_reset_fn::<T>)); + unsafe { + bindings::device_class_set_legacy_reset(dc, Some(rust_reset_fn::<T>)); + } } if let Some(vmsd) = <T as DeviceImpl>::vmsd() { dc.vmsd = vmsd; } - bindings::device_class_set_props(dc, <T as DeviceImpl>::properties().as_ptr()); - } -} - -#[macro_export] -macro_rules! impl_device_class { - ($type:ty) => { - impl $crate::definitions::ClassInitImpl for $type { - const CLASS_INIT: Option< - unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut ::std::os::raw::c_void), - > = Some($crate::device_class::rust_device_class_init::<$type>); - const CLASS_BASE_INIT: Option< - unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut ::std::os::raw::c_void), - > = None; + let prop = <T as DeviceImpl>::properties(); + if !prop.is_empty() { + unsafe { + bindings::device_class_set_props_n(dc, prop.as_ptr(), prop.len()); + } } - }; + + <T as ClassInitImpl<ObjectClass>>::class_init(&mut dc.parent_class); + } } #[macro_export] @@ -134,7 +127,7 @@ macro_rules! define_property { macro_rules! declare_properties { ($ident:ident, $($prop:expr),*$(,)*) => { pub static $ident: [$crate::bindings::Property; { - let mut len = 1; + let mut len = 0; $({ _ = stringify!($prop); len += 1; @@ -142,13 +135,13 @@ macro_rules! declare_properties { len }] = [ $($prop),*, - $crate::zeroable::Zeroable::ZERO, ]; }; } -unsafe impl ObjectType for bindings::DeviceState { - type Class = bindings::DeviceClass; +unsafe impl ObjectType for DeviceState { + type Class = DeviceClass; const TYPE_NAME: &'static CStr = unsafe { CStr::from_bytes_with_nul_unchecked(bindings::TYPE_DEVICE) }; } +qom_isa!(DeviceState: Object); diff --git a/rust/qemu-api/src/qom.rs b/rust/qemu-api/src/qom.rs new file mode 100644 index 0000000000..7d5fbef1e1 --- /dev/null +++ b/rust/qemu-api/src/qom.rs @@ -0,0 +1,584 @@ +// Copyright 2024, Linaro Limited +// Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org> +// SPDX-License-Identifier: GPL-2.0-or-later + +//! Bindings to access QOM functionality from Rust. +//! +//! The QEMU Object Model (QOM) provides inheritance and dynamic typing for QEMU +//! devices. This module makes QOM's features available in Rust through three +//! main mechanisms: +//! +//! * Automatic creation and registration of `TypeInfo` for classes that are +//! written in Rust, as well as mapping between Rust traits and QOM vtables. +//! +//! * Type-safe casting between parent and child classes, through the [`IsA`] +//! trait and methods such as [`upcast`](ObjectCast::upcast) and +//! [`downcast`](ObjectCast::downcast). +//! +//! * Automatic delegation of parent class methods to child classes. When a +//! trait uses [`IsA`] as a bound, its contents become available to all child +//! classes through blanket implementations. This works both for class methods +//! and for instance methods accessed through references or smart pointers. +//! +//! # Structure of a class +//! +//! A leaf class only needs a struct holding instance state. The struct must +//! implement the [`ObjectType`] and [`IsA`] traits, as well as any `*Impl` +//! traits that exist for its superclasses. +//! +//! If a class has subclasses, it will also provide a struct for instance data, +//! with the same characteristics as for concrete classes, but it also needs +//! additional components to support virtual methods: +//! +//! * a struct for class data, for example `DeviceClass`. This corresponds to +//! the C "class struct" and holds the vtable that is used by instances of the +//! class and its subclasses. It must start with its parent's class struct. +//! +//! * a trait for virtual method implementations, for example `DeviceImpl`. +//! Child classes implement this trait to provide their own behavior for +//! virtual methods. The trait's methods take `&self` to access instance data. +//! +//! * an implementation of [`ClassInitImpl`], for example +//! `ClassInitImpl<DeviceClass>`. This fills the vtable in the class struct; +//! the source for this is the `*Impl` trait; the associated consts and +//! functions if needed are wrapped to map C types into Rust types. +//! +//! * a trait for instance methods, for example `DeviceMethods`. This trait is +//! automatically implemented for any reference or smart pointer to a device +//! instance. It calls into the vtable provides access across all subclasses +//! to methods defined for the class. +//! +//! * optionally, a trait for class methods, for example `DeviceClassMethods`. +//! This provides access to class-wide functionality that doesn't depend on +//! instance data. Like instance methods, these are automatically inherited by +//! child classes. + +use std::{ + ffi::CStr, + ops::{Deref, DerefMut}, + os::raw::c_void, +}; + +pub use bindings::{Object, ObjectClass}; + +use crate::bindings::{self, object_dynamic_cast, object_get_class, object_get_typename, TypeInfo}; + +/// Marker trait: `Self` can be statically upcasted to `P` (i.e. `P` is a direct +/// or indirect parent of `Self`). +/// +/// # Safety +/// +/// The struct `Self` must be `#[repr(C)]` and must begin, directly or +/// indirectly, with a field of type `P`. This ensures that invalid casts, +/// which rely on `IsA<>` for static checking, are rejected at compile time. +pub unsafe trait IsA<P: ObjectType>: ObjectType {} + +// SAFETY: it is always safe to cast to your own type +unsafe impl<T: ObjectType> IsA<T> for T {} + +/// Macro to mark superclasses of QOM classes. This enables type-safe +/// up- and downcasting. +/// +/// # Safety +/// +/// This macro is a thin wrapper around the [`IsA`] trait and performs +/// no checking whatsoever of what is declared. It is the caller's +/// responsibility to have $struct begin, directly or indirectly, with +/// a field of type `$parent`. +#[macro_export] +macro_rules! qom_isa { + ($struct:ty : $($parent:ty),* ) => { + $( + // SAFETY: it is the caller responsibility to have $parent as the + // first field + unsafe impl $crate::qom::IsA<$parent> for $struct {} + + impl AsRef<$parent> for $struct { + fn as_ref(&self) -> &$parent { + // SAFETY: follows the same rules as for IsA<U>, which is + // declared above. + let ptr: *const Self = self; + unsafe { &*ptr.cast::<$parent>() } + } + } + )* + }; +} + +unsafe extern "C" fn rust_instance_init<T: ObjectImpl>(obj: *mut Object) { + // SAFETY: obj is an instance of T, since rust_instance_init<T> + // is called from QOM core as the instance_init function + // for class T + unsafe { T::INSTANCE_INIT.unwrap()(&mut *obj.cast::<T>()) } +} + +unsafe extern "C" fn rust_instance_post_init<T: ObjectImpl>(obj: *mut Object) { + // SAFETY: obj is an instance of T, since rust_instance_post_init<T> + // is called from QOM core as the instance_post_init function + // for class T + // + // FIXME: it's not really guaranteed that there are no backpointers to + // obj; it's quite possible that they have been created by instance_init(). + // The receiver should be &self, not &mut self. + T::INSTANCE_POST_INIT.unwrap()(unsafe { &mut *obj.cast::<T>() }) +} + +unsafe extern "C" fn rust_class_init<T: ObjectType + ClassInitImpl<T::Class>>( + klass: *mut ObjectClass, + _data: *mut c_void, +) { + // SAFETY: klass is a T::Class, since rust_class_init<T> + // is called from QOM core as the class_init function + // for class T + T::class_init(unsafe { &mut *klass.cast::<T::Class>() }) +} + +/// Trait exposed by all structs corresponding to QOM objects. +/// +/// # Safety +/// +/// For classes declared in C: +/// +/// - `Class` and `TYPE` must match the data in the `TypeInfo`; +/// +/// - the first field of the struct must be of the instance type corresponding +/// to the superclass, as declared in the `TypeInfo` +/// +/// - likewise, the first field of the `Class` struct must be of the class type +/// corresponding to the superclass +/// +/// For classes declared in Rust and implementing [`ObjectImpl`]: +/// +/// - the struct must be `#[repr(C)]`; +/// +/// - the first field of the struct must be of the instance struct corresponding +/// to the superclass, which is `ObjectImpl::ParentType` +/// +/// - likewise, the first field of the `Class` must be of the class struct +/// corresponding to the superclass, which is `ObjectImpl::ParentType::Class`. +pub unsafe trait ObjectType: Sized { + /// The QOM class object corresponding to this struct. This is used + /// to automatically generate a `class_init` method. + type Class; + + /// The name of the type, which can be passed to `object_new()` to + /// generate an instance of this type. + const TYPE_NAME: &'static CStr; + + /// Return the receiver as an Object. This is always safe, even + /// if this type represents an interface. + fn as_object(&self) -> &Object { + unsafe { &*self.as_object_ptr() } + } + + /// Return the receiver as a const raw pointer to Object. + /// This is preferrable to `as_object_mut_ptr()` if a C + /// function only needs a `const Object *`. + fn as_object_ptr(&self) -> *const Object { + self.as_ptr().cast() + } + + /// Return the receiver as a mutable raw pointer to Object. + /// + /// # Safety + /// + /// This cast is always safe, but because the result is mutable + /// and the incoming reference is not, this should only be used + /// for calls to C functions, and only if needed. + unsafe fn as_object_mut_ptr(&self) -> *mut Object { + self.as_object_ptr() as *mut _ + } +} + +/// This trait provides safe casting operations for QOM objects to raw pointers, +/// to be used for example for FFI. The trait can be applied to any kind of +/// reference or smart pointers, and enforces correctness through the [`IsA`] +/// trait. +pub trait ObjectDeref: Deref +where + Self::Target: ObjectType, +{ + /// Convert to a const Rust pointer, to be used for example for FFI. + /// The target pointer type must be the type of `self` or a superclass + fn as_ptr<U: ObjectType>(&self) -> *const U + where + Self::Target: IsA<U>, + { + let ptr: *const Self::Target = self.deref(); + ptr.cast::<U>() + } + + /// Convert to a mutable Rust pointer, to be used for example for FFI. + /// The target pointer type must be the type of `self` or a superclass. + /// Used to implement interior mutability for objects. + /// + /// # Safety + /// + /// This method is unsafe because it overrides const-ness of `&self`. + /// Bindings to C APIs will use it a lot, but otherwise it should not + /// be necessary. + unsafe fn as_mut_ptr<U: ObjectType>(&self) -> *mut U + where + Self::Target: IsA<U>, + { + #[allow(clippy::as_ptr_cast_mut)] + { + self.as_ptr::<U>() as *mut _ + } + } +} + +/// Trait that adds extra functionality for `&T` where `T` is a QOM +/// object type. Allows conversion to/from C objects in generic code. +pub trait ObjectCast: ObjectDeref + Copy +where + Self::Target: ObjectType, +{ + /// Safely convert from a derived type to one of its parent types. + /// + /// This is always safe; the [`IsA`] trait provides static verification + /// trait that `Self` dereferences to `U` or a child of `U`. + fn upcast<'a, U: ObjectType>(self) -> &'a U + where + Self::Target: IsA<U>, + Self: 'a, + { + // SAFETY: soundness is declared via IsA<U>, which is an unsafe trait + unsafe { self.unsafe_cast::<U>() } + } + + /// Attempt to convert to a derived type. + /// + /// Returns `None` if the object is not actually of type `U`. This is + /// verified at runtime by checking the object's type information. + fn downcast<'a, U: IsA<Self::Target>>(self) -> Option<&'a U> + where + Self: 'a, + { + self.dynamic_cast::<U>() + } + + /// Attempt to convert between any two types in the QOM hierarchy. + /// + /// Returns `None` if the object is not actually of type `U`. This is + /// verified at runtime by checking the object's type information. + fn dynamic_cast<'a, U: ObjectType>(self) -> Option<&'a U> + where + Self: 'a, + { + unsafe { + // SAFETY: upcasting to Object is always valid, and the + // return type is either NULL or the argument itself + let result: *const U = + object_dynamic_cast(self.as_object_mut_ptr(), U::TYPE_NAME.as_ptr()).cast(); + + result.as_ref() + } + } + + /// Convert to any QOM type without verification. + /// + /// # Safety + /// + /// What safety? You need to know yourself that the cast is correct; only + /// use when performance is paramount. It is still better than a raw + /// pointer `cast()`, which does not even check that you remain in the + /// realm of QOM `ObjectType`s. + /// + /// `unsafe_cast::<Object>()` is always safe. + unsafe fn unsafe_cast<'a, U: ObjectType>(self) -> &'a U + where + Self: 'a, + { + unsafe { &*(self.as_ptr::<Self::Target>().cast::<U>()) } + } +} + +impl<T: ObjectType> ObjectDeref for &T {} +impl<T: ObjectType> ObjectCast for &T {} + +/// Trait for mutable type casting operations in the QOM hierarchy. +/// +/// This trait provides the mutable counterparts to [`ObjectCast`]'s conversion +/// functions. Unlike `ObjectCast`, this trait returns `Result` for fallible +/// conversions to preserve the original smart pointer if the cast fails. This +/// is necessary because mutable references cannot be copied, so a failed cast +/// must return ownership of the original reference. For example: +/// +/// ```ignore +/// let mut dev = get_device(); +/// // If this fails, we need the original `dev` back to try something else +/// match dev.dynamic_cast_mut::<FooDevice>() { +/// Ok(foodev) => /* use foodev */, +/// Err(dev) => /* still have ownership of dev */ +/// } +/// ``` +pub trait ObjectCastMut: Sized + ObjectDeref + DerefMut +where + Self::Target: ObjectType, +{ + /// Safely convert from a derived type to one of its parent types. + /// + /// This is always safe; the [`IsA`] trait provides static verification + /// that `Self` dereferences to `U` or a child of `U`. + fn upcast_mut<'a, U: ObjectType>(self) -> &'a mut U + where + Self::Target: IsA<U>, + Self: 'a, + { + // SAFETY: soundness is declared via IsA<U>, which is an unsafe trait + unsafe { self.unsafe_cast_mut::<U>() } + } + + /// Attempt to convert to a derived type. + /// + /// Returns `Ok(..)` if the object is of type `U`, or `Err(self)` if the + /// object if the conversion failed. This is verified at runtime by + /// checking the object's type information. + fn downcast_mut<'a, U: IsA<Self::Target>>(self) -> Result<&'a mut U, Self> + where + Self: 'a, + { + self.dynamic_cast_mut::<U>() + } + + /// Attempt to convert between any two types in the QOM hierarchy. + /// + /// Returns `Ok(..)` if the object is of type `U`, or `Err(self)` if the + /// object if the conversion failed. This is verified at runtime by + /// checking the object's type information. + fn dynamic_cast_mut<'a, U: ObjectType>(self) -> Result<&'a mut U, Self> + where + Self: 'a, + { + unsafe { + // SAFETY: upcasting to Object is always valid, and the + // return type is either NULL or the argument itself + let result: *mut U = + object_dynamic_cast(self.as_object_mut_ptr(), U::TYPE_NAME.as_ptr()).cast(); + + result.as_mut().ok_or(self) + } + } + + /// Convert to any QOM type without verification. + /// + /// # Safety + /// + /// What safety? You need to know yourself that the cast is correct; only + /// use when performance is paramount. It is still better than a raw + /// pointer `cast()`, which does not even check that you remain in the + /// realm of QOM `ObjectType`s. + /// + /// `unsafe_cast::<Object>()` is always safe. + unsafe fn unsafe_cast_mut<'a, U: ObjectType>(self) -> &'a mut U + where + Self: 'a, + { + unsafe { &mut *self.as_mut_ptr::<Self::Target>().cast::<U>() } + } +} + +impl<T: ObjectType> ObjectDeref for &mut T {} +impl<T: ObjectType> ObjectCastMut for &mut T {} + +/// Trait a type must implement to be registered with QEMU. +pub trait ObjectImpl: ObjectType + ClassInitImpl<Self::Class> { + /// The parent of the type. This should match the first field of + /// the struct that implements `ObjectImpl`: + type ParentType: ObjectType; + + /// Whether the object can be instantiated + const ABSTRACT: bool = false; + const INSTANCE_FINALIZE: Option<unsafe extern "C" fn(obj: *mut Object)> = None; + + /// Function that is called to initialize an object. The parent class will + /// have already been initialized so the type is only responsible for + /// initializing its own members. + /// + /// FIXME: The argument is not really a valid reference. `&mut + /// MaybeUninit<Self>` would be a better description. + const INSTANCE_INIT: Option<unsafe fn(&mut Self)> = None; + + /// Function that is called to finish initialization of an object, once + /// `INSTANCE_INIT` functions have been called. + const INSTANCE_POST_INIT: Option<fn(&mut Self)> = None; + + /// Called on descendent classes after all parent class initialization + /// has occurred, but before the class itself is initialized. This + /// is only useful if a class is not a leaf, and can be used to undo + /// the effects of copying the contents of the parent's class struct + /// to the descendants. + const CLASS_BASE_INIT: Option< + unsafe extern "C" fn(klass: *mut ObjectClass, data: *mut c_void), + > = None; + + const TYPE_INFO: TypeInfo = TypeInfo { + name: Self::TYPE_NAME.as_ptr(), + parent: Self::ParentType::TYPE_NAME.as_ptr(), + instance_size: core::mem::size_of::<Self>(), + instance_align: core::mem::align_of::<Self>(), + instance_init: match Self::INSTANCE_INIT { + None => None, + Some(_) => Some(rust_instance_init::<Self>), + }, + instance_post_init: match Self::INSTANCE_POST_INIT { + None => None, + Some(_) => Some(rust_instance_post_init::<Self>), + }, + instance_finalize: Self::INSTANCE_FINALIZE, + abstract_: Self::ABSTRACT, + class_size: core::mem::size_of::<Self::Class>(), + class_init: Some(rust_class_init::<Self>), + class_base_init: Self::CLASS_BASE_INIT, + class_data: core::ptr::null_mut(), + interfaces: core::ptr::null_mut(), + }; + + // methods on ObjectClass + const UNPARENT: Option<fn(&Self)> = None; +} + +/// Internal trait used to automatically fill in a class struct. +/// +/// Each QOM class that has virtual methods describes them in a +/// _class struct_. Class structs include a parent field corresponding +/// to the vtable of the parent class, all the way up to [`ObjectClass`]. +/// Each QOM type has one such class struct; this trait takes care of +/// initializing the `T` part of the class struct, for the type that +/// implements the trait. +/// +/// Each struct will implement this trait with `T` equal to each +/// superclass. For example, a device should implement at least +/// `ClassInitImpl<`[`DeviceClass`](crate::qdev::DeviceClass)`>` and +/// `ClassInitImpl<`[`ObjectClass`]`>`. Such implementations are made +/// in one of two ways. +/// +/// For most superclasses, `ClassInitImpl` is provided by the `qemu-api` +/// crate itself. The Rust implementation of methods will come from a +/// trait like [`ObjectImpl`] or [`DeviceImpl`](crate::qdev::DeviceImpl), +/// and `ClassInitImpl` is provided by blanket implementations that +/// operate on all implementors of the `*Impl`* trait. For example: +/// +/// ```ignore +/// impl<T> ClassInitImpl<DeviceClass> for T +/// where +/// T: ClassInitImpl<ObjectClass> + DeviceImpl, +/// ``` +/// +/// The bound on `ClassInitImpl<ObjectClass>` is needed so that, +/// after initializing the `DeviceClass` part of the class struct, +/// the parent [`ObjectClass`] is initialized as well. +/// +/// The other case is when manual implementation of the trait is needed. +/// This covers the following cases: +/// +/// * if a class implements a QOM interface, the Rust code _has_ to define its +/// own class struct `FooClass` and implement `ClassInitImpl<FooClass>`. +/// `ClassInitImpl<FooClass>`'s `class_init` method will then forward to +/// multiple other `class_init`s, for the interfaces as well as the +/// superclass. (Note that there is no Rust example yet for using interfaces). +/// +/// * for classes implemented outside the ``qemu-api`` crate, it's not possible +/// to add blanket implementations like the above one, due to orphan rules. In +/// that case, the easiest solution is to implement +/// `ClassInitImpl<YourSuperclass>` for each subclass and not have a +/// `YourSuperclassImpl` trait at all. +/// +/// ```ignore +/// impl ClassInitImpl<YourSuperclass> for YourSubclass { +/// fn class_init(klass: &mut YourSuperclass) { +/// klass.some_method = Some(Self::some_method); +/// <Self as ClassInitImpl<SysBusDeviceClass>>::class_init(&mut klass.parent_class); +/// } +/// } +/// ``` +/// +/// While this method incurs a small amount of code duplication, +/// it is generally limited to the recursive call on the last line. +/// This is because classes defined in Rust do not need the same +/// glue code that is needed when the classes are defined in C code. +/// You may consider using a macro if you have many subclasses. +pub trait ClassInitImpl<T> { + /// Initialize `klass` to point to the virtual method implementations + /// for `Self`. On entry, the virtual method pointers are set to + /// the default values coming from the parent classes; the function + /// can change them to override virtual methods of a parent class. + /// + /// The virtual method implementations usually come from another + /// trait, for example [`DeviceImpl`](crate::qdev::DeviceImpl) + /// when `T` is [`DeviceClass`](crate::qdev::DeviceClass). + /// + /// On entry, `klass`'s parent class is initialized, while the other fields + /// are all zero; it is therefore assumed that all fields in `T` can be + /// zeroed, otherwise it would not be possible to provide the class as a + /// `&mut T`. TODO: add a bound of [`Zeroable`](crate::zeroable::Zeroable) + /// to T; this is more easily done once Zeroable does not require a manual + /// implementation (Rust 1.75.0). + fn class_init(klass: &mut T); +} + +/// # Safety +/// +/// We expect the FFI user of this function to pass a valid pointer that +/// can be downcasted to type `T`. We also expect the device is +/// readable/writeable from one thread at any time. +unsafe extern "C" fn rust_unparent_fn<T: ObjectImpl>(dev: *mut Object) { + unsafe { + assert!(!dev.is_null()); + let state = core::ptr::NonNull::new_unchecked(dev.cast::<T>()); + T::UNPARENT.unwrap()(state.as_ref()); + } +} + +impl<T> ClassInitImpl<ObjectClass> for T +where + T: ObjectImpl, +{ + fn class_init(oc: &mut ObjectClass) { + if <T as ObjectImpl>::UNPARENT.is_some() { + oc.unparent = Some(rust_unparent_fn::<T>); + } + } +} + +unsafe impl ObjectType for Object { + type Class = ObjectClass; + const TYPE_NAME: &'static CStr = + unsafe { CStr::from_bytes_with_nul_unchecked(bindings::TYPE_OBJECT) }; +} + +/// Trait for methods exposed by the Object class. The methods can be +/// called on all objects that have the trait `IsA<Object>`. +/// +/// The trait should only be used through the blanket implementation, +/// which guarantees safety via `IsA` +pub trait ObjectMethods: ObjectDeref +where + Self::Target: IsA<Object>, +{ + /// Return the name of the type of `self` + fn typename(&self) -> std::borrow::Cow<'_, str> { + let obj = self.upcast::<Object>(); + // SAFETY: safety of this is the requirement for implementing IsA + // The result of the C API has static lifetime + unsafe { + let p = object_get_typename(obj.as_mut_ptr()); + CStr::from_ptr(p).to_string_lossy() + } + } + + fn get_class(&self) -> &'static <Self::Target as ObjectType>::Class { + let obj = self.upcast::<Object>(); + + // SAFETY: all objects can call object_get_class; the actual class + // type is guaranteed by the implementation of `ObjectType` and + // `ObjectImpl`. + let klass: &'static <Self::Target as ObjectType>::Class = + unsafe { &*object_get_class(obj.as_mut_ptr()).cast() }; + + klass + } +} + +impl<R: ObjectDeref> ObjectMethods for R where R::Target: IsA<Object> {} diff --git a/rust/qemu-api/src/sysbus.rs b/rust/qemu-api/src/sysbus.rs index 5ee068541c..8193734bde 100644 --- a/rust/qemu-api/src/sysbus.rs +++ b/rust/qemu-api/src/sysbus.rs @@ -6,13 +6,31 @@ use std::{ffi::CStr, ptr::addr_of}; pub use bindings::{SysBusDevice, SysBusDeviceClass}; -use crate::{bindings, cell::bql_locked, irq::InterruptSource, prelude::*}; +use crate::{ + bindings, + cell::bql_locked, + irq::InterruptSource, + prelude::*, + qdev::{DeviceClass, DeviceState}, + qom::ClassInitImpl, +}; unsafe impl ObjectType for SysBusDevice { type Class = SysBusDeviceClass; const TYPE_NAME: &'static CStr = unsafe { CStr::from_bytes_with_nul_unchecked(bindings::TYPE_SYS_BUS_DEVICE) }; } +qom_isa!(SysBusDevice: DeviceState, Object); + +// TODO: add SysBusDeviceImpl +impl<T> ClassInitImpl<SysBusDeviceClass> for T +where + T: ClassInitImpl<DeviceClass>, +{ + fn class_init(sdc: &mut SysBusDeviceClass) { + <T as ClassInitImpl<DeviceClass>>::class_init(&mut sdc.parent_class); + } +} impl SysBusDevice { /// Return `self` cast to a mutable pointer, for use in calls to C code. diff --git a/rust/qemu-api/src/vmstate.rs b/rust/qemu-api/src/vmstate.rs index bedcf1e8f3..63c897abcd 100644 --- a/rust/qemu-api/src/vmstate.rs +++ b/rust/qemu-api/src/vmstate.rs @@ -10,6 +10,8 @@ //! [`vmstate_fields`](crate::vmstate_fields) are meant to be used when //! declaring a device model state struct. +pub use crate::bindings::VMStateDescription; + #[doc(alias = "VMSTATE_UNUSED_BUFFER")] #[macro_export] macro_rules! vmstate_unused_buffer { @@ -104,28 +106,6 @@ macro_rules! vmstate_uint32 { }}; } -#[doc(alias = "VMSTATE_INT32_V")] -#[macro_export] -macro_rules! vmstate_int32_v { - ($field_name:ident, $struct_name:ty, $version_id:expr) => {{ - $crate::vmstate_single!( - $field_name, - $struct_name, - $version_id, - ::core::ptr::addr_of!($crate::bindings::vmstate_info_int32), - ::core::mem::size_of::<i32>() - ) - }}; -} - -#[doc(alias = "VMSTATE_INT32")] -#[macro_export] -macro_rules! vmstate_int32 { - ($field_name:ident, $struct_name:ty) => {{ - $crate::vmstate_int32_v!($field_name, $struct_name, 0) - }}; -} - #[doc(alias = "VMSTATE_ARRAY")] #[macro_export] macro_rules! vmstate_array { @@ -328,7 +308,7 @@ macro_rules! vmstate_fields { } /// A transparent wrapper type for the `subsections` field of -/// [`VMStateDescription`](crate::bindings::VMStateDescription). +/// [`VMStateDescription`]. /// /// This is necessary to be able to declare subsection descriptions as statics, /// because the only way to implement `Sync` for a foreign type (and `*const` @@ -342,9 +322,8 @@ pub struct VMStateSubsectionsWrapper(pub &'static [*const crate::bindings::VMSta unsafe impl Sync for VMStateSubsectionsWrapper {} -/// Helper macro to declare a list of subsections -/// ([`VMStateDescription`](`crate::bindings::VMStateDescription`)) into a -/// static and return a pointer to the array of pointers it created. +/// Helper macro to declare a list of subsections ([`VMStateDescription`]) +/// into a static and return a pointer to the array of pointers it created. #[macro_export] macro_rules! vmstate_subsections { ($($subsection:expr),*$(,)*) => {{ diff --git a/rust/qemu-api/tests/tests.rs b/rust/qemu-api/tests/tests.rs index 278efe967f..1d2825b098 100644 --- a/rust/qemu-api/tests/tests.rs +++ b/rust/qemu-api/tests/tests.rs @@ -2,69 +2,160 @@ // Author(s): Manos Pitsidianakis <manos.pitsidianakis@linaro.org> // SPDX-License-Identifier: GPL-2.0-or-later -use std::ffi::CStr; +use std::{ + ffi::CStr, + os::raw::c_void, + ptr::{addr_of, addr_of_mut}, +}; use qemu_api::{ - bindings::*, c_str, declare_properties, define_property, definitions::ObjectImpl, - device_class::DeviceImpl, impl_device_class, prelude::*, zeroable::Zeroable, + bindings::*, + c_str, + cell::{self, BqlCell}, + declare_properties, define_property, + prelude::*, + qdev::{DeviceImpl, DeviceState, Property}, + qom::ObjectImpl, + vmstate::VMStateDescription, + zeroable::Zeroable, }; -#[test] -fn test_device_decl_macros() { - // Test that macros can compile. - pub static VMSTATE: VMStateDescription = VMStateDescription { - name: c_str!("name").as_ptr(), - unmigratable: true, - ..Zeroable::ZERO - }; - - #[derive(qemu_api_macros::offsets)] - #[repr(C)] - #[derive(qemu_api_macros::Object)] - pub struct DummyState { - pub _parent: DeviceState, - pub migrate_clock: bool, - } +// Test that macros can compile. +pub static VMSTATE: VMStateDescription = VMStateDescription { + name: c_str!("name").as_ptr(), + unmigratable: true, + ..Zeroable::ZERO +}; + +#[derive(qemu_api_macros::offsets)] +#[repr(C)] +#[derive(qemu_api_macros::Object)] +pub struct DummyState { + parent: DeviceState, + migrate_clock: bool, +} + +qom_isa!(DummyState: Object, DeviceState); + +declare_properties! { + DUMMY_PROPERTIES, + define_property!( + c_str!("migrate-clk"), + DummyState, + migrate_clock, + unsafe { &qdev_prop_bool }, + bool + ), +} + +unsafe impl ObjectType for DummyState { + type Class = <DeviceState as ObjectType>::Class; + const TYPE_NAME: &'static CStr = c_str!("dummy"); +} - #[repr(C)] - pub struct DummyClass { - pub _parent: DeviceClass, +impl ObjectImpl for DummyState { + type ParentType = DeviceState; + const ABSTRACT: bool = false; +} + +impl DeviceImpl for DummyState { + fn properties() -> &'static [Property] { + &DUMMY_PROPERTIES + } + fn vmsd() -> Option<&'static VMStateDescription> { + Some(&VMSTATE) } +} + +fn init_qom() { + static ONCE: BqlCell<bool> = BqlCell::new(false); - declare_properties! { - DUMMY_PROPERTIES, - define_property!( - c_str!("migrate-clk"), - DummyState, - migrate_clock, - unsafe { &qdev_prop_bool }, - bool - ), + cell::bql_start_test(); + if !ONCE.get() { + unsafe { + module_call_init(module_init_type::MODULE_INIT_QOM); + } + ONCE.set(true); } +} - unsafe impl ObjectType for DummyState { - type Class = DummyClass; - const TYPE_NAME: &'static CStr = c_str!("dummy"); +#[test] +/// Create and immediately drop an instance. +fn test_object_new() { + init_qom(); + unsafe { + object_unref(object_new(DummyState::TYPE_NAME.as_ptr()).cast()); } +} - impl ObjectImpl for DummyState { - type ParentType = DeviceState; - const ABSTRACT: bool = false; +#[test] +/// Try invoking a method on an object. +fn test_typename() { + init_qom(); + let p: *mut DummyState = unsafe { object_new(DummyState::TYPE_NAME.as_ptr()).cast() }; + let p_ref: &DummyState = unsafe { &*p }; + assert_eq!(p_ref.typename(), "dummy"); + unsafe { + object_unref(p_ref.as_object_mut_ptr().cast::<c_void>()); } +} - impl DeviceImpl for DummyState { - fn properties() -> &'static [Property] { - &DUMMY_PROPERTIES - } - fn vmsd() -> Option<&'static VMStateDescription> { - Some(&VMSTATE) - } +// a note on all "cast" tests: usually, especially for downcasts the desired +// class would be placed on the right, for example: +// +// let sbd_ref = p.dynamic_cast::<SysBusDevice>(); +// +// Here I am doing the opposite to check that the resulting type is correct. + +#[test] +#[allow(clippy::shadow_unrelated)] +/// Test casts on shared references. +fn test_cast() { + init_qom(); + let p: *mut DummyState = unsafe { object_new(DummyState::TYPE_NAME.as_ptr()).cast() }; + + let p_ref: &DummyState = unsafe { &*p }; + let obj_ref: &Object = p_ref.upcast(); + assert_eq!(addr_of!(*obj_ref), p.cast()); + + let sbd_ref: Option<&SysBusDevice> = obj_ref.dynamic_cast(); + assert!(sbd_ref.is_none()); + + let dev_ref: Option<&DeviceState> = obj_ref.downcast(); + assert_eq!(addr_of!(*dev_ref.unwrap()), p.cast()); + + // SAFETY: the cast is wrong, but the value is only used for comparison + unsafe { + let sbd_ref: &SysBusDevice = obj_ref.unsafe_cast(); + assert_eq!(addr_of!(*sbd_ref), p.cast()); + + object_unref(p_ref.as_object_mut_ptr().cast::<c_void>()); } +} + +#[test] +#[allow(clippy::shadow_unrelated)] +/// Test casts on mutable references. +fn test_cast_mut() { + init_qom(); + let p: *mut DummyState = unsafe { object_new(DummyState::TYPE_NAME.as_ptr()).cast() }; + + let p_ref: &mut DummyState = unsafe { &mut *p }; + let obj_ref: &mut Object = p_ref.upcast_mut(); + assert_eq!(addr_of_mut!(*obj_ref), p.cast()); + + let sbd_ref: Result<&mut SysBusDevice, &mut Object> = obj_ref.dynamic_cast_mut(); + let obj_ref = sbd_ref.unwrap_err(); - impl_device_class!(DummyState); + let dev_ref: Result<&mut DeviceState, &mut Object> = obj_ref.downcast_mut(); + let dev_ref = dev_ref.unwrap(); + assert_eq!(addr_of_mut!(*dev_ref), p.cast()); + // SAFETY: the cast is wrong, but the value is only used for comparison unsafe { - module_call_init(module_init_type::MODULE_INIT_QOM); - object_unref(object_new(DummyState::TYPE_NAME.as_ptr()).cast()); + let sbd_ref: &mut SysBusDevice = obj_ref.unsafe_cast_mut(); + assert_eq!(addr_of_mut!(*sbd_ref), p.cast()); + + object_unref(p_ref.as_object_mut_ptr().cast::<c_void>()); } } diff --git a/stubs/iothread-lock.c b/stubs/iothread-lock.c index 5467659895..6050c081f5 100644 --- a/stubs/iothread-lock.c +++ b/stubs/iothread-lock.c @@ -1,11 +1,17 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" +static bool bql_is_locked = false; static uint32_t bql_unlock_blocked; bool bql_locked(void) { - return false; + return bql_is_locked; +} + +void rust_bql_mock_lock(void) +{ + bql_is_locked = true; } void bql_lock_impl(const char *file, int line) diff --git a/system/cpus.c b/system/cpus.c index 3460a80482..99f83806c1 100644 --- a/system/cpus.c +++ b/system/cpus.c @@ -538,6 +538,12 @@ bool qemu_in_main_thread(void) return bql_locked(); } +void rust_bql_mock_lock(void) +{ + error_report("This function should be used only from tests"); + abort(); +} + /* * The BQL is taken from so many places that it is worth profiling the * callers directly, instead of funneling them all through a single function. diff --git a/system/qdev-monitor.c b/system/qdev-monitor.c index efa284750e..c844f53802 100644 --- a/system/qdev-monitor.c +++ b/system/qdev-monitor.c @@ -752,19 +752,18 @@ DeviceState *qdev_device_add(QemuOpts *opts, Error **errp) #define qdev_printf(fmt, ...) monitor_printf(mon, "%*s" fmt, indent, "", ## __VA_ARGS__) -static void qdev_print_props(Monitor *mon, DeviceState *dev, const Property *props, +static void qdev_print_props(Monitor *mon, DeviceState *dev, DeviceClass *dc, int indent) { - if (!props) - return; - for (; props->name; props++) { + for (int i = 0, n = dc->props_count_; i < n; ++i) { + const Property *prop = &dc->props_[i]; char *value; - char *legacy_name = g_strdup_printf("legacy-%s", props->name); + char *legacy_name = g_strdup_printf("legacy-%s", prop->name); if (object_property_get_type(OBJECT(dev), legacy_name, NULL)) { value = object_property_get_str(OBJECT(dev), legacy_name, NULL); } else { - value = object_property_print(OBJECT(dev), props->name, true, + value = object_property_print(OBJECT(dev), prop->name, true, NULL); } g_free(legacy_name); @@ -772,7 +771,7 @@ static void qdev_print_props(Monitor *mon, DeviceState *dev, const Property *pro if (!value) { continue; } - qdev_printf("%s = %s\n", props->name, + qdev_printf("%s = %s\n", prop->name, *value ? value : "<null>"); g_free(value); } @@ -812,7 +811,7 @@ static void qdev_print(Monitor *mon, DeviceState *dev, int indent) } class = object_get_class(OBJECT(dev)); do { - qdev_print_props(mon, dev, DEVICE_CLASS(class)->props_, indent); + qdev_print_props(mon, dev, DEVICE_CLASS(class), indent); class = object_class_get_parent(class); } while (class != object_class_by_name(TYPE_DEVICE)); bus_print_dev(dev->parent_bus, mon, dev, indent); diff --git a/target/arm/cpu.c b/target/arm/cpu.c index f45cd18ff7..019183c9ea 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -2653,7 +2653,6 @@ static const Property arm_cpu_properties[] = { DEFINE_PROP_INT32("core-count", ARMCPU, core_count, -1), /* True to default to the backward-compat old CNTFRQ rather than 1Ghz */ DEFINE_PROP_BOOL("backcompat-cntfrq", ARMCPU, backcompat_cntfrq, false), - DEFINE_PROP_END_OF_LIST() }; static const gchar *arm_gdb_arch_name(CPUState *cs) diff --git a/target/avr/cpu.c b/target/avr/cpu.c index 698e0c5161..2dccb09c5e 100644 --- a/target/avr/cpu.c +++ b/target/avr/cpu.c @@ -152,7 +152,6 @@ static void avr_cpu_initfn(Object *obj) static const Property avr_cpu_properties[] = { DEFINE_PROP_UINT32("init-sp", AVRCPU, init_sp, 0), - DEFINE_PROP_END_OF_LIST() }; static ObjectClass *avr_cpu_class_by_name(const char *cpu_model) diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index c213ce8d88..c9817c7192 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -54,7 +54,6 @@ static const Property hexagon_cpu_properties[] = { DEFINE_PROP_UNSIGNED("lldb-stack-adjust", HexagonCPU, lldb_stack_adjust, 0, qdev_prop_uint32, target_ulong), DEFINE_PROP_BOOL("short-circuit", HexagonCPU, short_circuit, true), - DEFINE_PROP_END_OF_LIST() }; const char * const hexagon_regnames[TOTAL_PER_THREAD_REGS] = { diff --git a/target/i386/cpu.c b/target/i386/cpu.c index f3a97dc61b..660ddafc28 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -5388,7 +5388,6 @@ static X86CPUVersion x86_cpu_model_resolve_version(const X86CPUModel *model) static const Property max_x86_cpu_properties[] = { DEFINE_PROP_BOOL("migratable", X86CPU, migratable, true), DEFINE_PROP_BOOL("host-cache-info", X86CPU, cache_info_passthrough, false), - DEFINE_PROP_END_OF_LIST() }; static void max_x86_cpu_realize(DeviceState *dev, Error **errp) @@ -8549,7 +8548,6 @@ static const Property x86_cpu_properties[] = { DEFINE_PROP_BOOL("x-intel-pt-auto-level", X86CPU, intel_pt_auto_level, true), DEFINE_PROP_BOOL("x-l1-cache-per-thread", X86CPU, l1_cache_per_core, true), - DEFINE_PROP_END_OF_LIST() }; #ifndef CONFIG_USER_ONLY diff --git a/target/i386/kvm/kvm.c b/target/i386/kvm/kvm.c index 80fa3bac11..2f66e63b88 100644 --- a/target/i386/kvm/kvm.c +++ b/target/i386/kvm/kvm.c @@ -2415,6 +2415,21 @@ void kvm_arch_after_reset_vcpu(X86CPU *cpu) } } +void kvm_arch_reset_parked_vcpu(unsigned long vcpu_id, int kvm_fd) +{ + g_autofree struct kvm_msrs *msrs = NULL; + + msrs = g_malloc0(sizeof(*msrs) + sizeof(msrs->entries[0])); + msrs->entries[0].index = MSR_IA32_TSC; + msrs->entries[0].data = 1; /* match the value in x86_cpu_reset() */ + msrs->nmsrs++; + + if (ioctl(kvm_fd, KVM_SET_MSRS, msrs) != 1) { + warn_report("parked vCPU %lu TSC reset failed: %d", + vcpu_id, errno); + } +} + void kvm_arch_do_init_vcpu(X86CPU *cpu) { CPUX86State *env = &cpu->env; diff --git a/target/microblaze/cpu.c b/target/microblaze/cpu.c index 9db5c4d2a3..eba819378d 100644 --- a/target/microblaze/cpu.c +++ b/target/microblaze/cpu.c @@ -404,7 +404,6 @@ static const Property mb_properties[] = { /* * End of properties reserved by Xilinx DTS conversion tool. */ - DEFINE_PROP_END_OF_LIST(), }; static ObjectClass *mb_cpu_class_by_name(const char *cpu_model) diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 270611ce96..1b0cf6df9c 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -541,7 +541,6 @@ static const struct SysemuCPUOps mips_sysemu_ops = { static const Property mips_cpu_properties[] = { DEFINE_PROP_BOOL("big-endian", MIPSCPU, is_big_endian, TARGET_BIG_ENDIAN), - DEFINE_PROP_END_OF_LIST(), }; #ifdef CONFIG_TCG diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c index c04ecafef9..0fcef630f1 100644 --- a/target/ppc/cpu_init.c +++ b/target/ppc/cpu_init.c @@ -7414,11 +7414,6 @@ static void ppc_disas_set_info(CPUState *cs, disassemble_info *info) #endif } -static Property ppc_cpu_properties[] = { - /* add default property here */ - DEFINE_PROP_END_OF_LIST(), -}; - #ifndef CONFIG_USER_ONLY #include "hw/core/sysemu-cpu-ops.h" @@ -7468,7 +7463,6 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_unrealize(dc, ppc_cpu_unrealize, &pcc->parent_unrealize); pcc->pvr_match = ppc_pvr_match_default; - device_class_set_props(dc, ppc_cpu_properties); resettable_class_set_parent_phases(rc, NULL, ppc_cpu_reset_hold, NULL, &pcc->parent_phases); diff --git a/target/riscv/cpu-qom.h b/target/riscv/cpu-qom.h index 62115375cd..d56b067bf2 100644 --- a/target/riscv/cpu-qom.h +++ b/target/riscv/cpu-qom.h @@ -49,6 +49,8 @@ #define TYPE_RISCV_CPU_SIFIVE_U54 RISCV_CPU_TYPE_NAME("sifive-u54") #define TYPE_RISCV_CPU_THEAD_C906 RISCV_CPU_TYPE_NAME("thead-c906") #define TYPE_RISCV_CPU_VEYRON_V1 RISCV_CPU_TYPE_NAME("veyron-v1") +#define TYPE_RISCV_CPU_TT_ASCALON RISCV_CPU_TYPE_NAME("tt-ascalon") +#define TYPE_RISCV_CPU_XIANGSHAN_NANHU RISCV_CPU_TYPE_NAME("xiangshan-nanhu") #define TYPE_RISCV_CPU_HOST RISCV_CPU_TYPE_NAME("host") OBJECT_DECLARE_CPU_TYPE(RISCVCPU, RISCVCPUClass, RISCV_CPU) diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 3b316184fd..b8d5120106 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -191,6 +191,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(ssccptr, PRIV_VERSION_1_11_0, has_priv_1_11), ISA_EXT_DATA_ENTRY(sscofpmf, PRIV_VERSION_1_12_0, ext_sscofpmf), ISA_EXT_DATA_ENTRY(sscounterenw, PRIV_VERSION_1_12_0, has_priv_1_12), + ISA_EXT_DATA_ENTRY(ssstateen, PRIV_VERSION_1_12_0, ext_ssstateen), ISA_EXT_DATA_ENTRY(sstc, PRIV_VERSION_1_12_0, ext_sstc), ISA_EXT_DATA_ENTRY(sstvala, PRIV_VERSION_1_12_0, has_priv_1_12), ISA_EXT_DATA_ENTRY(sstvecd, PRIV_VERSION_1_12_0, has_priv_1_12), @@ -199,6 +200,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(svinval, PRIV_VERSION_1_12_0, ext_svinval), ISA_EXT_DATA_ENTRY(svnapot, PRIV_VERSION_1_12_0, ext_svnapot), ISA_EXT_DATA_ENTRY(svpbmt, PRIV_VERSION_1_12_0, ext_svpbmt), + ISA_EXT_DATA_ENTRY(svukte, PRIV_VERSION_1_13_0, ext_svukte), ISA_EXT_DATA_ENTRY(svvptc, PRIV_VERSION_1_13_0, ext_svvptc), ISA_EXT_DATA_ENTRY(xtheadba, PRIV_VERSION_1_11_0, ext_xtheadba), ISA_EXT_DATA_ENTRY(xtheadbb, PRIV_VERSION_1_11_0, ext_xtheadbb), @@ -213,7 +215,7 @@ const RISCVIsaExtData isa_edata_arr[] = { ISA_EXT_DATA_ENTRY(xtheadsync, PRIV_VERSION_1_11_0, ext_xtheadsync), ISA_EXT_DATA_ENTRY(xventanacondops, PRIV_VERSION_1_12_0, ext_XVentanaCondOps), - DEFINE_PROP_END_OF_LIST(), + { }, }; bool isa_ext_is_enabled(RISCVCPU *cpu, uint32_t ext_offset) @@ -579,6 +581,100 @@ static void rv64_veyron_v1_cpu_init(Object *obj) #endif } +/* Tenstorrent Ascalon */ +static void rv64_tt_ascalon_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + riscv_cpu_set_misa_ext(env, RVG | RVC | RVS | RVU | RVH | RVV); + env->priv_ver = PRIV_VERSION_1_13_0; + + /* Enable ISA extensions */ + cpu->cfg.mmu = true; + cpu->cfg.vlenb = 256 >> 3; + cpu->cfg.elen = 64; + cpu->env.vext_ver = VEXT_VERSION_1_00_0; + cpu->cfg.rvv_ma_all_1s = true; + cpu->cfg.rvv_ta_all_1s = true; + cpu->cfg.misa_w = true; + cpu->cfg.pmp = true; + cpu->cfg.cbom_blocksize = 64; + cpu->cfg.cbop_blocksize = 64; + cpu->cfg.cboz_blocksize = 64; + cpu->cfg.ext_zic64b = true; + cpu->cfg.ext_zicbom = true; + cpu->cfg.ext_zicbop = true; + cpu->cfg.ext_zicboz = true; + cpu->cfg.ext_zicntr = true; + cpu->cfg.ext_zicond = true; + cpu->cfg.ext_zicsr = true; + cpu->cfg.ext_zifencei = true; + cpu->cfg.ext_zihintntl = true; + cpu->cfg.ext_zihintpause = true; + cpu->cfg.ext_zihpm = true; + cpu->cfg.ext_zimop = true; + cpu->cfg.ext_zawrs = true; + cpu->cfg.ext_zfa = true; + cpu->cfg.ext_zfbfmin = true; + cpu->cfg.ext_zfh = true; + cpu->cfg.ext_zfhmin = true; + cpu->cfg.ext_zcb = true; + cpu->cfg.ext_zcmop = true; + cpu->cfg.ext_zba = true; + cpu->cfg.ext_zbb = true; + cpu->cfg.ext_zbs = true; + cpu->cfg.ext_zkt = true; + cpu->cfg.ext_zvbb = true; + cpu->cfg.ext_zvbc = true; + cpu->cfg.ext_zvfbfmin = true; + cpu->cfg.ext_zvfbfwma = true; + cpu->cfg.ext_zvfh = true; + cpu->cfg.ext_zvfhmin = true; + cpu->cfg.ext_zvkng = true; + cpu->cfg.ext_smaia = true; + cpu->cfg.ext_smstateen = true; + cpu->cfg.ext_ssaia = true; + cpu->cfg.ext_sscofpmf = true; + cpu->cfg.ext_sstc = true; + cpu->cfg.ext_svade = true; + cpu->cfg.ext_svinval = true; + cpu->cfg.ext_svnapot = true; + cpu->cfg.ext_svpbmt = true; + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV57); +#endif +} + +static void rv64_xiangshan_nanhu_cpu_init(Object *obj) +{ + CPURISCVState *env = &RISCV_CPU(obj)->env; + RISCVCPU *cpu = RISCV_CPU(obj); + + riscv_cpu_set_misa_ext(env, RVG | RVC | RVB | RVS | RVU); + env->priv_ver = PRIV_VERSION_1_12_0; + + /* Enable ISA extensions */ + cpu->cfg.ext_zbc = true; + cpu->cfg.ext_zbkb = true; + cpu->cfg.ext_zbkc = true; + cpu->cfg.ext_zbkx = true; + cpu->cfg.ext_zknd = true; + cpu->cfg.ext_zkne = true; + cpu->cfg.ext_zknh = true; + cpu->cfg.ext_zksed = true; + cpu->cfg.ext_zksh = true; + cpu->cfg.ext_svinval = true; + + cpu->cfg.mmu = true; + cpu->cfg.pmp = true; + +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV39); +#endif +} + #ifdef CONFIG_TCG static void rv128_base_cpu_init(Object *obj) { @@ -1575,7 +1671,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_extensions[] = { MULTI_EXT_CFG_BOOL("zvksc", ext_zvksc, false), MULTI_EXT_CFG_BOOL("zvksg", ext_zvksg, false), - DEFINE_PROP_END_OF_LIST(), + { }, }; const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { @@ -1592,12 +1688,14 @@ const RISCVCPUMultiExtConfig riscv_cpu_vendor_exts[] = { MULTI_EXT_CFG_BOOL("xtheadsync", ext_xtheadsync, false), MULTI_EXT_CFG_BOOL("xventanacondops", ext_XVentanaCondOps, false), - DEFINE_PROP_END_OF_LIST(), + { }, }; /* These are experimental so mark with 'x-' */ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { - DEFINE_PROP_END_OF_LIST(), + MULTI_EXT_CFG_BOOL("x-svukte", ext_svukte, false), + + { }, }; /* @@ -1609,8 +1707,9 @@ const RISCVCPUMultiExtConfig riscv_cpu_experimental_exts[] = { */ const RISCVCPUMultiExtConfig riscv_cpu_named_features[] = { MULTI_EXT_CFG_BOOL("zic64b", ext_zic64b, true), + MULTI_EXT_CFG_BOOL("ssstateen", ext_ssstateen, true), - DEFINE_PROP_END_OF_LIST(), + { }, }; /* Deprecated entries marked for future removal */ @@ -1627,7 +1726,7 @@ const RISCVCPUMultiExtConfig riscv_cpu_deprecated_exts[] = { MULTI_EXT_CFG_BOOL("Zve64f", ext_zve64f, false), MULTI_EXT_CFG_BOOL("Zve64d", ext_zve64d, false), - DEFINE_PROP_END_OF_LIST(), + { }, }; static void cpu_set_prop_err(RISCVCPU *cpu, const char *propname, @@ -2699,7 +2798,6 @@ static const Property riscv_cpu_properties[] = { * it with -x and default to 'false'. */ DEFINE_PROP_BOOL("x-misa-w", RISCVCPU, cfg.misa_w, false), - DEFINE_PROP_END_OF_LIST(), }; #if defined(TARGET_RISCV64) @@ -2984,7 +3082,10 @@ static const TypeInfo riscv_cpu_type_infos[] = { DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SIFIVE_U54, MXL_RV64, rv64_sifive_u_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_SHAKTI_C, MXL_RV64, rv64_sifive_u_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_THEAD_C906, MXL_RV64, rv64_thead_c906_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_TT_ASCALON, MXL_RV64, rv64_tt_ascalon_cpu_init), DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_VEYRON_V1, MXL_RV64, rv64_veyron_v1_cpu_init), + DEFINE_VENDOR_CPU(TYPE_RISCV_CPU_XIANGSHAN_NANHU, + MXL_RV64, rv64_xiangshan_nanhu_cpu_init), #ifdef CONFIG_TCG DEFINE_DYNAMIC_CPU(TYPE_RISCV_CPU_BASE128, MXL_RV128, rv128_base_cpu_init), #endif /* CONFIG_TCG */ diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 385a2c67c2..fe4e34c64a 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -604,6 +604,7 @@ typedef enum { #define HSTATUS_VTVM 0x00100000 #define HSTATUS_VTW 0x00200000 #define HSTATUS_VTSR 0x00400000 +#define HSTATUS_HUKTE 0x01000000 #define HSTATUS_VSXL 0x300000000 #define HSTATUS32_WPRI 0xFF8FF87E @@ -785,6 +786,7 @@ typedef enum RISCVException { #define SENVCFG_CBIE MENVCFG_CBIE #define SENVCFG_CBCFE MENVCFG_CBCFE #define SENVCFG_CBZE MENVCFG_CBZE +#define SENVCFG_UKTE BIT(8) #define HENVCFG_FIOM MENVCFG_FIOM #define HENVCFG_LPE MENVCFG_LPE diff --git a/target/riscv/cpu_cfg.h b/target/riscv/cpu_cfg.h index 59d6fc445d..a1457ab4f4 100644 --- a/target/riscv/cpu_cfg.h +++ b/target/riscv/cpu_cfg.h @@ -84,6 +84,7 @@ struct RISCVCPUConfig { bool ext_svnapot; bool ext_svpbmt; bool ext_svvptc; + bool ext_svukte; bool ext_zdinx; bool ext_zaamo; bool ext_zacas; @@ -139,6 +140,7 @@ struct RISCVCPUConfig { /* Named features */ bool ext_svade; bool ext_zic64b; + bool ext_ssstateen; /* * Always 'true' booleans for named features diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 39e1dd76a5..f62b21e182 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -857,6 +857,55 @@ static int get_physical_address_pmp(CPURISCVState *env, int *prot, hwaddr addr, return TRANSLATE_SUCCESS; } +/* Returns 'true' if a svukte address check is needed */ +static bool do_svukte_check(CPURISCVState *env, bool first_stage, + int mode, bool virt) +{ + /* Svukte extension depends on Sv39. */ + if (!(env_archcpu(env)->cfg.ext_svukte || + !first_stage || + VM_1_10_SV39 != get_field(env->satp, SATP64_MODE))) { + return false; + } + + /* + * Check hstatus.HUKTE if the effective mode is switched to VU-mode by + * executing HLV/HLVX/HSV in U-mode. + * For other cases, check senvcfg.UKTE. + */ + if (env->priv == PRV_U && !env->virt_enabled && virt) { + if (!get_field(env->hstatus, HSTATUS_HUKTE)) { + return false; + } + } else if (!get_field(env->senvcfg, SENVCFG_UKTE)) { + return false; + } + + /* + * Svukte extension is qualified only in U or VU-mode. + * + * Effective mode can be switched to U or VU-mode by: + * - M-mode + mstatus.MPRV=1 + mstatus.MPP=U-mode. + * - Execute HLV/HLVX/HSV from HS-mode + hstatus.SPVP=0. + * - U-mode. + * - VU-mode. + * - Execute HLV/HLVX/HSV from U-mode + hstatus.HU=1. + */ + if (mode != PRV_U) { + return false; + } + + return true; +} + +static bool check_svukte_addr(CPURISCVState *env, vaddr addr) +{ + /* svukte extension excludes RV32 */ + uint32_t sxlen = 32 * riscv_cpu_sxl(env); + uint64_t high_bit = addr & (1UL << (sxlen - 1)); + return !high_bit; +} + /* * get_physical_address - get the physical address for this virtual address * @@ -894,6 +943,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, MemTxResult res; MemTxAttrs attrs = MEMTXATTRS_UNSPECIFIED; int mode = mmuidx_priv(mmu_idx); + bool virt = mmuidx_2stage(mmu_idx); bool use_background = false; hwaddr ppn; int napot_bits = 0; @@ -901,6 +951,11 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, bool is_sstack_idx = ((mmu_idx & MMU_IDX_SS_WRITE) == MMU_IDX_SS_WRITE); bool sstack_page = false; + if (do_svukte_check(env, first_stage, mode, virt) && + !check_svukte_addr(env, addr)) { + return TRANSLATE_FAIL; + } + /* * Check if we should use the background registers for the two * stage translation. We don't need to check if we actually need diff --git a/target/riscv/csr.c b/target/riscv/csr.c index 7f8c76e229..381cda81f8 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -2453,6 +2453,10 @@ static RISCVException write_senvcfg(CPURISCVState *env, int csrno, mask |= SENVCFG_SSE; } + if (env_archcpu(env)->cfg.ext_svukte) { + mask |= SENVCFG_UKTE; + } + env->senvcfg = (env->senvcfg & ~mask) | (val & mask); return RISCV_EXCP_NONE; } @@ -3536,6 +3540,9 @@ static RISCVException read_hstatus(CPURISCVState *env, int csrno, static RISCVException write_hstatus(CPURISCVState *env, int csrno, target_ulong val) { + if (!env_archcpu(env)->cfg.ext_svukte) { + val = val & (~HSTATUS_HUKTE); + } env->hstatus = val; if (riscv_cpu_mxl(env) != MXL_RV32 && get_field(val, HSTATUS_VSXL) != 2) { qemu_log_mask(LOG_UNIMP, diff --git a/target/riscv/internals.h b/target/riscv/internals.h index ddbdee885b..76934eaa7b 100644 --- a/target/riscv/internals.h +++ b/target/riscv/internals.h @@ -19,7 +19,10 @@ #ifndef RISCV_CPU_INTERNALS_H #define RISCV_CPU_INTERNALS_H +#include "exec/cpu-common.h" #include "hw/registerfields.h" +#include "fpu/softfloat-types.h" +#include "target/riscv/cpu_bits.h" /* * The current MMU Modes are: diff --git a/target/riscv/kvm/kvm-cpu.c b/target/riscv/kvm/kvm-cpu.c index 189e460ee2..11278ea778 100644 --- a/target/riscv/kvm/kvm-cpu.c +++ b/target/riscv/kvm/kvm-cpu.c @@ -1408,11 +1408,6 @@ int kvm_arch_init(MachineState *ms, KVMState *s) int kvm_arch_irqchip_create(KVMState *s) { - if (kvm_kernel_irqchip_split()) { - error_report("-machine kernel_irqchip=split is not supported on RISC-V."); - exit(1); - } - /* * We can create the VAIA using the newer device control API. */ @@ -1734,13 +1729,29 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, } } - ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, - KVM_DEV_RISCV_AIA_CONFIG_SRCS, - &aia_irq_num, true, NULL); - if (ret < 0) { - error_report("KVM AIA: failed to set number of input irq lines"); - exit(1); - } + /* + * Skip APLIC creation in KVM if we're running split mode. + * This is done by leaving KVM_DEV_RISCV_AIA_CONFIG_SRCS + * unset. We can also skip KVM_DEV_RISCV_AIA_ADDR_APLIC + * since KVM won't be using it. + */ + if (!kvm_kernel_irqchip_split()) { + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, + KVM_DEV_RISCV_AIA_CONFIG_SRCS, + &aia_irq_num, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set number of input irq lines"); + exit(1); + } + + ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, + KVM_DEV_RISCV_AIA_ADDR_APLIC, + &aplic_base, true, NULL); + if (ret < 0) { + error_report("KVM AIA: failed to set the base address of APLIC"); + exit(1); + } + } ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_CONFIG, KVM_DEV_RISCV_AIA_CONFIG_IDS, @@ -1781,14 +1792,6 @@ void kvm_riscv_aia_create(MachineState *machine, uint64_t group_shift, exit(1); } - ret = kvm_device_access(aia_fd, KVM_DEV_RISCV_AIA_GRP_ADDR, - KVM_DEV_RISCV_AIA_ADDR_APLIC, - &aplic_base, true, NULL); - if (ret < 0) { - error_report("KVM AIA: failed to set the base address of APLIC"); - exit(1); - } - for (socket = 0; socket < socket_count; socket++) { socket_imsic_base = imsic_base + socket * (1U << group_shift); hart_count = riscv_socket_hart_count(machine, socket); diff --git a/target/riscv/tcg/tcg-cpu.c b/target/riscv/tcg/tcg-cpu.c index 958b8c89cb..f0129811fd 100644 --- a/target/riscv/tcg/tcg-cpu.c +++ b/target/riscv/tcg/tcg-cpu.c @@ -205,10 +205,15 @@ static void riscv_cpu_enable_named_feat(RISCVCPU *cpu, uint32_t feat_offset) * All other named features are already enabled * in riscv_tcg_cpu_instance_init(). */ - if (feat_offset == CPU_CFG_OFFSET(ext_zic64b)) { + switch (feat_offset) { + case CPU_CFG_OFFSET(ext_zic64b): cpu->cfg.cbom_blocksize = 64; cpu->cfg.cbop_blocksize = 64; cpu->cfg.cboz_blocksize = 64; + break; + case CPU_CFG_OFFSET(ext_ssstateen): + cpu->cfg.ext_smstateen = true; + break; } } @@ -305,6 +310,15 @@ static void riscv_cpu_disable_priv_spec_isa_exts(RISCVCPU *cpu) } isa_ext_update_enabled(cpu, edata->ext_enable_offset, false); + + /* + * Do not show user warnings for named features that users + * can't enable/disable in the command line. See commit + * 68c9e54bea for more info. + */ + if (cpu_cfg_offset_is_named_feat(edata->ext_enable_offset)) { + continue; + } #ifndef CONFIG_USER_ONLY warn_report("disabling %s extension for hart 0x" TARGET_FMT_lx " because privilege spec version does not match", @@ -332,11 +346,11 @@ static void riscv_cpu_update_named_features(RISCVCPU *cpu) cpu->cfg.has_priv_1_13 = true; } - /* zic64b is 1.12 or later */ cpu->cfg.ext_zic64b = cpu->cfg.cbom_blocksize == 64 && cpu->cfg.cbop_blocksize == 64 && - cpu->cfg.cboz_blocksize == 64 && - cpu->cfg.has_priv_1_12; + cpu->cfg.cboz_blocksize == 64; + + cpu->cfg.ext_ssstateen = cpu->cfg.ext_smstateen; } static void riscv_cpu_validate_g(RISCVCPU *cpu) @@ -653,6 +667,11 @@ void riscv_cpu_validate_set_extensions(RISCVCPU *cpu, Error **errp) return; } + if (mcc->misa_mxl_max == MXL_RV32 && cpu->cfg.ext_svukte) { + error_setg(errp, "svukte is not supported for RV32"); + return; + } + /* * Disable isa extensions based on priv spec after we * validated and set everything we need. diff --git a/target/riscv/vector_internals.h b/target/riscv/vector_internals.h index 9e1e15b575..a11cc8366d 100644 --- a/target/riscv/vector_internals.h +++ b/target/riscv/vector_internals.h @@ -20,6 +20,7 @@ #define TARGET_RISCV_VECTOR_INTERNALS_H #include "qemu/bitops.h" +#include "hw/registerfields.h" #include "cpu.h" #include "tcg/tcg-gvec-desc.h" #include "internals.h" diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index a149dbd848..0a6847b027 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -309,8 +309,8 @@ static const gchar *s390_gdb_arch_name(CPUState *cs) return "s390:64-bit"; } +#ifndef CONFIG_USER_ONLY static const Property s390x_cpu_properties[] = { -#if !defined(CONFIG_USER_ONLY) DEFINE_PROP_UINT32("core-id", S390CPU, env.core_id, 0), DEFINE_PROP_INT32("socket-id", S390CPU, env.socket_id, -1), DEFINE_PROP_INT32("book-id", S390CPU, env.book_id, -1), @@ -318,9 +318,8 @@ static const Property s390x_cpu_properties[] = { DEFINE_PROP_BOOL("dedicated", S390CPU, env.dedicated, false), DEFINE_PROP_CPUS390ENTITLEMENT("entitlement", S390CPU, env.entitlement, S390_CPU_ENTITLEMENT_AUTO), -#endif - DEFINE_PROP_END_OF_LIST() }; +#endif #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" @@ -388,7 +387,6 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) device_class_set_parent_realize(dc, s390_cpu_realizefn, &scc->parent_realize); - device_class_set_props(dc, s390x_cpu_properties); dc->user_creatable = true; resettable_class_set_parent_phases(rc, NULL, s390_cpu_reset_hold, NULL, @@ -404,6 +402,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_read_register = s390_cpu_gdb_read_register; cc->gdb_write_register = s390_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY + device_class_set_props(dc, s390x_cpu_properties); s390_cpu_system_class_init(cc); #endif cc->disas_set_info = s390_cpu_disas_set_info; diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index 960ed90351..373a335c39 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -980,7 +980,6 @@ static const Property sparc_cpu_properties[] = { DEFINE_PROP_UINT32("mmu-version", SPARCCPU, env.def.mmu_version, 0), DEFINE_PROP("nwindows", SPARCCPU, env.def.nwindows, qdev_prop_nwindows, uint32_t), - DEFINE_PROP_END_OF_LIST() }; #ifndef CONFIG_USER_ONLY diff --git a/tests/data/acpi/riscv64/virt/SPCR b/tests/data/acpi/riscv64/virt/SPCR index 4da9daf65f..09617f8793 100644 --- a/tests/data/acpi/riscv64/virt/SPCR +++ b/tests/data/acpi/riscv64/virt/SPCR Binary files differdiff --git a/tests/unit/test-qdev-global-props.c b/tests/unit/test-qdev-global-props.c index d2f9800148..6f6a306788 100644 --- a/tests/unit/test-qdev-global-props.c +++ b/tests/unit/test-qdev-global-props.c @@ -49,7 +49,6 @@ struct MyType { static const Property static_props[] = { DEFINE_PROP_UINT32("prop1", MyType, prop1, PROP_DEFAULT), DEFINE_PROP_UINT32("prop2", MyType, prop2, PROP_DEFAULT), - DEFINE_PROP_END_OF_LIST() }; static void static_prop_class_init(ObjectClass *oc, void *data) |