diff options
| -rw-r--r-- | target/i386/cpu.c | 43 |
1 files changed, 34 insertions, 9 deletions
diff --git a/target/i386/cpu.c b/target/i386/cpu.c index ca85603077..565eaf0071 100644 --- a/target/i386/cpu.c +++ b/target/i386/cpu.c @@ -7507,7 +7507,35 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, encode_cache_cpuid2(cpu, caches, eax, ebx, ecx, edx); break; } - case 4: + case 4: { + const CPUCaches *caches; + + if (env->enable_legacy_vendor_cache) { + caches = &legacy_intel_cache_info; + } else { + /* + * FIXME: Temporarily select cache info model here based on + * vendor, and merge these 2 cache info models later. + * + * This condition covers the following cases (with + * enable_legacy_vendor_cache=false): + * - When CPU model has its own cache model and doesn't use legacy + * cache model (legacy_model=off). Then cache_info_amd and + * cache_info_cpuid4 are the same. + * + * - For v10.1 and newer machines, when CPU model uses legacy cache + * model. Non-AMD CPUs use cache_info_cpuid4 like before and AMD + * CPU will use cache_info_amd. But this doesn't matter for AMD + * CPU, because this leaf encodes all-0 for AMD whatever its cache + * model is. + */ + if (IS_AMD_CPU(env)) { + caches = &env->cache_info_amd; + } else { + caches = &env->cache_info_cpuid4; + } + } + /* cache info: needed for Core compatibility */ if (cpu->cache_info_passthrough) { x86_cpu_get_cache_cpuid(index, count, eax, ebx, ecx, edx); @@ -7535,30 +7563,26 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, switch (count) { case 0: /* L1 dcache info */ - encode_cache_cpuid4(env->cache_info_cpuid4.l1d_cache, - topo_info, + encode_cache_cpuid4(caches->l1d_cache, topo_info, eax, ebx, ecx, edx); if (!cpu->l1_cache_per_core) { *eax &= ~MAKE_64BIT_MASK(14, 12); } break; case 1: /* L1 icache info */ - encode_cache_cpuid4(env->cache_info_cpuid4.l1i_cache, - topo_info, + encode_cache_cpuid4(caches->l1i_cache, topo_info, eax, ebx, ecx, edx); if (!cpu->l1_cache_per_core) { *eax &= ~MAKE_64BIT_MASK(14, 12); } break; case 2: /* L2 cache info */ - encode_cache_cpuid4(env->cache_info_cpuid4.l2_cache, - topo_info, + encode_cache_cpuid4(caches->l2_cache, topo_info, eax, ebx, ecx, edx); break; case 3: /* L3 cache info */ if (cpu->enable_l3_cache) { - encode_cache_cpuid4(env->cache_info_cpuid4.l3_cache, - topo_info, + encode_cache_cpuid4(caches->l3_cache, topo_info, eax, ebx, ecx, edx); break; } @@ -7569,6 +7593,7 @@ void cpu_x86_cpuid(CPUX86State *env, uint32_t index, uint32_t count, } } break; + } case 5: /* MONITOR/MWAIT Leaf */ *eax = cpu->mwait.eax; /* Smallest monitor-line size in bytes */ |