diff options
| -rw-r--r-- | target/xtensa/cpu.h | 1 | ||||
| -rw-r--r-- | target/xtensa/overlay_tool.h | 1 | ||||
| -rw-r--r-- | target/xtensa/translate.c | 10 |
3 files changed, 12 insertions, 0 deletions
diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index d6e6bf6ca1..ba4ef2b6a7 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -466,6 +466,7 @@ struct XtensaConfig { unsigned icache_ways; unsigned dcache_ways; + unsigned dcache_line_bytes; uint32_t memctl_mask; XtensaMemory instrom; diff --git a/target/xtensa/overlay_tool.h b/target/xtensa/overlay_tool.h index b61c925398..4925b21f0e 100644 --- a/target/xtensa/overlay_tool.h +++ b/target/xtensa/overlay_tool.h @@ -425,6 +425,7 @@ #define CACHE_SECTION \ .icache_ways = XCHAL_ICACHE_WAYS, \ .dcache_ways = XCHAL_DCACHE_WAYS, \ + .dcache_line_bytes = XCHAL_DCACHE_LINESIZE, \ .memctl_mask = \ (XCHAL_ICACHE_SIZE ? MEMCTL_IUSEWAYS_MASK : 0) | \ (XCHAL_DCACHE_SIZE ? \ diff --git a/target/xtensa/translate.c b/target/xtensa/translate.c index 782f2ec620..24eb70d619 100644 --- a/target/xtensa/translate.c +++ b/target/xtensa/translate.c @@ -1620,6 +1620,12 @@ static void translate_depbits(DisasContext *dc, const OpcodeArg arg[], arg[2].imm, arg[3].imm); } +static void translate_diwbuip(DisasContext *dc, const OpcodeArg arg[], + const uint32_t par[]) +{ + tcg_gen_addi_i32(arg[0].out, arg[0].in, dc->config->dcache_line_bytes); +} + static bool test_ill_entry(DisasContext *dc, const OpcodeArg arg[], const uint32_t par[]) { @@ -3098,6 +3104,10 @@ static const XtensaOpcodeOps core_ops[] = { .translate = translate_nop, .op_flags = XTENSA_OP_PRIVILEGED, }, { + .name = "diwbui.p", + .translate = translate_diwbuip, + .op_flags = XTENSA_OP_PRIVILEGED, + }, { .name = "dpfl", .translate = translate_dcache, .op_flags = XTENSA_OP_PRIVILEGED, |