diff options
| -rw-r--r-- | hw/ppc/ppc440_bamboo.c | 11 | ||||
| -rw-r--r-- | hw/ppc/ppc4xx_devs.c | 60 | ||||
| -rw-r--r-- | hw/ppc/sam460ex.c | 5 | ||||
| -rw-r--r-- | include/hw/ppc/ppc4xx.h | 9 |
4 files changed, 42 insertions, 43 deletions
diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index da777ef9c2..7e3bc0ec7f 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -158,7 +158,6 @@ static void main_cpu_reset(void *opaque) static void bamboo_init(MachineState *machine) { - ram_addr_t ram_size = machine->ram_size; const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; @@ -203,10 +202,8 @@ static void bamboo_init(MachineState *machine) /* SDRAM controller */ memset(ram_bases, 0, sizeof(ram_bases)); memset(ram_sizes, 0, sizeof(ram_sizes)); - ram_size = ppc4xx_sdram_adjust(ram_size, PPC440EP_SDRAM_NR_BANKS, - ram_memories, - ram_bases, ram_sizes, - ppc440ep_sdram_bank_sizes); + ppc4xx_sdram_banks(machine->ram_size, PPC440EP_SDRAM_NR_BANKS, ram_memories, + ram_bases, ram_sizes, ppc440ep_sdram_bank_sizes); /* XXX 440EP's ECC interrupts are on UIC1, but we've only created UIC0. */ ppc4xx_sdram_init(env, pic[14], PPC440EP_SDRAM_NR_BANKS, ram_memories, ram_bases, ram_sizes, 1); @@ -268,7 +265,7 @@ static void bamboo_init(MachineState *machine) /* Load initrd. */ if (initrd_filename) { initrd_size = load_image_targphys(initrd_filename, RAMDISK_ADDR, - ram_size - RAMDISK_ADDR); + machine->ram_size - RAMDISK_ADDR); if (initrd_size < 0) { error_report("could not load ram disk '%s' at %x", @@ -279,7 +276,7 @@ static void bamboo_init(MachineState *machine) /* If we're loading a kernel directly, we must load the device tree too. */ if (kernel_filename) { - if (bamboo_load_device_tree(FDT_ADDR, ram_size, RAMDISK_ADDR, + if (bamboo_load_device_tree(FDT_ADDR, machine->ram_size, RAMDISK_ADDR, initrd_size, kernel_cmdline) < 0) { error_report("couldn't load device tree"); exit(1); diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index c2e50138aa..d89008a2a4 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -668,21 +668,22 @@ void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, /* Fill in consecutive SDRAM banks with 'ram_size' bytes of memory. * - * sdram_bank_sizes[] must be 0-terminated. + * sdram_bank_sizes[] must be in descending order, that is sizes[i] > sizes[i+1] + * and must be 0-terminated. * * The 4xx SDRAM controller supports a small number of banks, and each bank * must be one of a small set of sizes. The number of banks and the supported * sizes varies by SoC. */ -ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, - MemoryRegion ram_memories[], - hwaddr ram_bases[], - hwaddr ram_sizes[], - const ram_addr_t sdram_bank_sizes[]) +void ppc4xx_sdram_banks(ram_addr_t ram_size, int nr_banks, + MemoryRegion ram_memories[], + hwaddr ram_bases[], hwaddr ram_sizes[], + const ram_addr_t sdram_bank_sizes[]) { MemoryRegion *ram = g_malloc0(sizeof(*ram)); ram_addr_t size_left = ram_size; ram_addr_t base = 0; ram_addr_t bank_size; + int last_bank = 0; int i; int j; @@ -690,7 +691,12 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, for (j = 0; sdram_bank_sizes[j] != 0; j++) { bank_size = sdram_bank_sizes[j]; if (bank_size <= size_left) { + ram_bases[i] = base; + ram_sizes[i] = bank_size; + base += bank_size; size_left -= bank_size; + last_bank = i; + break; } } if (!size_left) { @@ -699,34 +705,32 @@ ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, } } - ram_size -= size_left; if (size_left) { - error_report("Truncating memory to %" PRId64 " MiB to fit SDRAM" - " controller limits", ram_size / MiB); + ram_addr_t used_size = ram_size - size_left; + GString *s = g_string_new(NULL); + + for (i = 0; sdram_bank_sizes[i]; i++) { + g_string_append_printf(s, "%" PRIi64 "%s", + sdram_bank_sizes[i] / MiB, + sdram_bank_sizes[i + 1] ? " ," : ""); + } + error_report("Max %d banks of %s MB DIMM/bank supported", + nr_banks, s->str); + error_report("Possible valid RAM size: %" PRIi64, + used_size ? used_size / MiB : sdram_bank_sizes[i - 1] / MiB); + + g_string_free(s, true); + exit(EXIT_FAILURE); } memory_region_allocate_system_memory(ram, NULL, "ppc4xx.sdram", ram_size); - size_left = ram_size; - for (i = 0; i < nr_banks && size_left; i++) { - for (j = 0; sdram_bank_sizes[j] != 0; j++) { - bank_size = sdram_bank_sizes[j]; - - if (bank_size <= size_left) { - char name[32]; - snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); - memory_region_init_alias(&ram_memories[i], NULL, name, ram, - base, bank_size); - ram_bases[i] = base; - ram_sizes[i] = bank_size; - base += bank_size; - size_left -= bank_size; - break; - } - } + for (i = 0; i <= last_bank; i++) { + char name[32]; + snprintf(name, sizeof(name), "ppc4xx.sdram%d", i); + memory_region_init_alias(&ram_memories[i], NULL, name, ram, + ram_bases[i], ram_sizes[i]); } - - return ram_size; } /*****************************************************************************/ diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 89bc70eb94..17d40bd672 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -324,9 +324,8 @@ static void sam460ex_init(MachineState *machine) /* SDRAM controller */ /* put all RAM on first bank because board has one slot * and firmware only checks that */ - machine->ram_size = ppc4xx_sdram_adjust(machine->ram_size, 1, - ram_memories, ram_bases, ram_sizes, - ppc460ex_sdram_bank_sizes); + ppc4xx_sdram_banks(machine->ram_size, 1, ram_memories, ram_bases, ram_sizes, + ppc460ex_sdram_bank_sizes); /* FIXME: does 460EX have ECC interrupts? */ ppc440_sdram_init(env, SDRAM_NR_BANKS, ram_memories, diff --git a/include/hw/ppc/ppc4xx.h b/include/hw/ppc/ppc4xx.h index 7d82259051..b8c8f324b4 100644 --- a/include/hw/ppc/ppc4xx.h +++ b/include/hw/ppc/ppc4xx.h @@ -42,11 +42,10 @@ enum { qemu_irq *ppcuic_init (CPUPPCState *env, qemu_irq *irqs, uint32_t dcr_base, int has_ssr, int has_vr); -ram_addr_t ppc4xx_sdram_adjust(ram_addr_t ram_size, int nr_banks, - MemoryRegion ram_memories[], - hwaddr ram_bases[], - hwaddr ram_sizes[], - const ram_addr_t sdram_bank_sizes[]); +void ppc4xx_sdram_banks(ram_addr_t ram_size, int nr_banks, + MemoryRegion ram_memories[], + hwaddr ram_bases[], hwaddr ram_sizes[], + const ram_addr_t sdram_bank_sizes[]); void ppc4xx_sdram_init (CPUPPCState *env, qemu_irq irq, int nbanks, MemoryRegion ram_memories[], |