diff options
44 files changed, 5408 insertions, 1547 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 180695f5d3..19792cfb2d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -205,21 +205,24 @@ F: disas/microblaze.c MIPS M: Aurelien Jarno <aurelien@aurel32.net> M: Aleksandar Markovic <amarkovic@wavecomp.com> +R: Aleksandar Rikalo <arikalo@wavecomp.com> R: Stefan Markovic <smarkovic@wavecomp.com> S: Maintained F: target/mips/ +F: default-configs/*mips* +F: disas/mips.c +F: disas/nanomips.cpp +F: disas/nanomips.h +F: hw/intc/mips_gic.c F: hw/mips/ F: hw/misc/mips_* -F: hw/intc/mips_gic.c F: hw/timer/mips_gictimer.c +F: include/hw/intc/mips_gic.h F: include/hw/mips/ F: include/hw/misc/mips_* -F: include/hw/intc/mips_gic.h F: include/hw/timer/mips_gictimer.h F: tests/tcg/mips/ -F: disas/mips.c -F: disas/nanomips.h -F: disas/nanomips.cpp +K: ^Subject:.*(?i)mips Moxie M: Anthony Green <green@moxielogic.com> @@ -262,11 +265,12 @@ M: Alistair Francis <Alistair.Francis@wdc.com> M: Sagar Karandikar <sagark@eecs.berkeley.edu> M: Bastian Koppelmann <kbastian@mail.uni-paderborn.de> L: qemu-riscv@nongnu.org -S: Maintained +S: Supported F: target/riscv/ F: hw/riscv/ F: include/hw/riscv/ -F: disas/riscv.c +F: linux-user/host/riscv32/ +F: linux-user/host/riscv64/ S390 M: Richard Henderson <rth@twiddle.net> @@ -360,6 +364,7 @@ F: target/arm/kvm.c MIPS M: James Hogan <jhogan@kernel.org> +R: Aleksandar Rikalo <arikalo@wavecomp.com> R: Stefan Markovic <smarkovic@wavecomp.com> S: Maintained F: target/mips/kvm.c @@ -869,6 +874,7 @@ MIPS Machines ------------- Jazz M: Hervé Poussineau <hpoussin@reactos.org> +R: Aleksandar Rikalo <arikalo@wavecomp.com> R: Stefan Markovic <smarkovic@wavecomp.com> S: Maintained F: hw/mips/mips_jazz.c @@ -877,12 +883,14 @@ F: hw/dma/rc4030.c Malta M: Aurelien Jarno <aurelien@aurel32.net> +R: Aleksandar Rikalo <arikalo@wavecomp.com> R: Stefan Markovic <smarkovic@wavecomp.com> S: Maintained F: hw/mips/mips_malta.c Mipssim M: Aleksandar Markovic <amarkovic@wavecomp.com> +R: Aleksandar Rikalo <arikalo@wavecomp.com> R: Stefan Markovic <smarkovic@wavecomp.com> S: Odd Fixes F: hw/mips/mips_mipssim.c @@ -890,12 +898,14 @@ F: hw/net/mipsnet.c R4000 M: Aurelien Jarno <aurelien@aurel32.net> +R: Aleksandar Rikalo <arikalo@wavecomp.com> R: Stefan Markovic <smarkovic@wavecomp.com> S: Maintained F: hw/mips/mips_r4k.c Fulong 2E M: Aleksandar Markovic <amarkovic@wavecomp.com> +R: Aleksandar Rikalo <arikalo@wavecomp.com> R: Stefan Markovic <smarkovic@wavecomp.com> S: Odd Fixes F: hw/mips/mips_fulong2e.c @@ -905,6 +915,7 @@ F: include/hw/isa/vt82c686.h Boston M: Paul Burton <pburton@wavecomp.com> +R: Aleksandar Rikalo <arikalo@wavecomp.com> R: Stefan Markovic <smarkovic@wavecomp.com> S: Maintained F: hw/core/loader-fit.c @@ -2161,6 +2172,7 @@ F: disas/i386.c MIPS target M: Aurelien Jarno <aurelien@aurel32.net> +R: Aleksandar Rikalo <arikalo@wavecomp.com> R: Stefan Markovic <smarkovic@wavecomp.com> S: Maintained F: tcg/mips/ @@ -2172,6 +2184,15 @@ S: Odd Fixes F: tcg/ppc/ F: disas/ppc.c +RISC-V +M: Michael Clark <mjc@sifive.com> +M: Palmer Dabbelt <palmer@sifive.com> +M: Alistair Francis <Alistair.Francis@wdc.com> +L: qemu-riscv@nongnu.org +S: Maintained +F: tcg/riscv/ +F: disas/riscv.c + S390 target M: Richard Henderson <rth@twiddle.net> S: Maintained diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index cd75829cf2..941295ea49 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -571,6 +571,81 @@ int cpu_signal_handler(int host_signum, void *pinfo, return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); } +#elif defined(__riscv) + +int cpu_signal_handler(int host_signum, void *pinfo, + void *puc) +{ + siginfo_t *info = pinfo; + ucontext_t *uc = puc; + greg_t pc = uc->uc_mcontext.__gregs[REG_PC]; + uint32_t insn = *(uint32_t *)pc; + int is_write = 0; + + /* Detect store by reading the instruction at the program + counter. Note: we currently only generate 32-bit + instructions so we thus only detect 32-bit stores */ + switch (((insn >> 0) & 0b11)) { + case 3: + switch (((insn >> 2) & 0b11111)) { + case 8: + switch (((insn >> 12) & 0b111)) { + case 0: /* sb */ + case 1: /* sh */ + case 2: /* sw */ + case 3: /* sd */ + case 4: /* sq */ + is_write = 1; + break; + default: + break; + } + break; + case 9: + switch (((insn >> 12) & 0b111)) { + case 2: /* fsw */ + case 3: /* fsd */ + case 4: /* fsq */ + is_write = 1; + break; + default: + break; + } + break; + default: + break; + } + } + + /* Check for compressed instructions */ + switch (((insn >> 13) & 0b111)) { + case 7: + switch (insn & 0b11) { + case 0: /*c.sd */ + case 2: /* c.sdsp */ + is_write = 1; + break; + default: + break; + } + break; + case 6: + switch (insn & 0b11) { + case 0: /* c.sw */ + case 3: /* c.swsp */ + is_write = 1; + break; + default: + break; + } + break; + default: + break; + } + + return handle_cpu_signal(pc, info, is_write, &uc->uc_sigmask); +} + #else #error host CPU specific signal handler needed diff --git a/block/dmg.c b/block/dmg.c index 50e91aef6d..43497bf343 100644 --- a/block/dmg.c +++ b/block/dmg.c @@ -54,7 +54,7 @@ enum { UDBZ, ULFO, UDCM = 0x7ffffffe, /* Comments */ - UDLE /* Last Entry */ + UDLE = 0xffffffff /* Last Entry */ }; static int dmg_probe(const uint8_t *buf, int buf_size, const char *filename) @@ -130,7 +130,8 @@ static void update_max_chunk_size(BDRVDMGState *s, uint32_t chunk, case UDRW: /* copy */ uncompressed_sectors = DIV_ROUND_UP(s->lengths[chunk], 512); break; - case UDIG: /* zero */ + case UDZE: /* zero */ + case UDIG: /* ignore */ /* as the all-zeroes block may be large, it is treated specially: the * sector is not copied from a large buffer, a simple memset is used * instead. Therefore uncompressed_sectors does not need to be set. */ @@ -199,8 +200,9 @@ typedef struct DmgHeaderState { static bool dmg_is_known_block_type(uint32_t entry_type) { switch (entry_type) { + case UDZE: /* zeros */ case UDRW: /* uncompressed */ - case UDIG: /* zeroes */ + case UDIG: /* ignore */ case UDZO: /* zlib */ return true; case UDBZ: /* bzip2 */ @@ -265,9 +267,10 @@ static int dmg_read_mish_block(BDRVDMGState *s, DmgHeaderState *ds, /* sector count */ s->sectorcounts[i] = buff_read_uint64(buffer, offset + 0x10); - /* all-zeroes sector (type 2) does not need to be "uncompressed" and can - * therefore be unbounded. */ - if (s->types[i] != 2 && s->sectorcounts[i] > DMG_SECTORCOUNTS_MAX) { + /* all-zeroes sector (type UDZE and UDIG) does not need to be + * "uncompressed" and can therefore be unbounded. */ + if (s->types[i] != UDZE && s->types[i] != UDIG + && s->sectorcounts[i] > DMG_SECTORCOUNTS_MAX) { error_report("sector count %" PRIu64 " for chunk %" PRIu32 " is larger than max (%u)", s->sectorcounts[i], i, DMG_SECTORCOUNTS_MAX); @@ -572,16 +575,20 @@ static inline uint32_t search_chunk(BDRVDMGState *s, uint64_t sector_num) { /* binary search */ uint32_t chunk1 = 0, chunk2 = s->n_chunks, chunk3; - while (chunk1 != chunk2) { + while (chunk1 <= chunk2) { chunk3 = (chunk1 + chunk2) / 2; if (s->sectors[chunk3] > sector_num) { - chunk2 = chunk3; + if (chunk3 == 0) { + goto err; + } + chunk2 = chunk3 - 1; } else if (s->sectors[chunk3] + s->sectorcounts[chunk3] > sector_num) { return chunk3; } else { - chunk1 = chunk3; + chunk1 = chunk3 + 1; } } +err: return s->n_chunks; /* error */ } @@ -671,7 +678,8 @@ static inline int dmg_read_chunk(BlockDriverState *bs, uint64_t sector_num) return -1; } break; - case UDIG: /* zero */ + case UDZE: /* zeros */ + case UDIG: /* ignore */ /* see dmg_read, it is treated specially. No buffer needs to be * pre-filled, the zeroes can be set directly. */ break; @@ -706,7 +714,8 @@ dmg_co_preadv(BlockDriverState *bs, uint64_t offset, uint64_t bytes, /* Special case: current chunk is all zeroes. Do not perform a memcpy as * s->uncompressed_chunk may be too small to cover the large all-zeroes * section. dmg_read_chunk is called to find s->current_chunk */ - if (s->types[s->current_chunk] == 2) { /* all zeroes block entry */ + if (s->types[s->current_chunk] == UDZE + || s->types[s->current_chunk] == UDIG) { /* all zeroes block entry */ qemu_iovec_memset(qiov, i * 512, 0, 512); continue; } diff --git a/configure b/configure index 224d3071ac..79375affc1 100755 --- a/configure +++ b/configure @@ -710,6 +710,12 @@ elif check_define __s390__ ; then else cpu="s390" fi +elif check_define __riscv ; then + if check_define _LP64 ; then + cpu="riscv64" + else + cpu="riscv32" + fi elif check_define __arm__ ; then cpu="arm" elif check_define __aarch64__ ; then @@ -722,7 +728,7 @@ ARCH= # Normalise host CPU name and set ARCH. # Note that this case should only have supported host CPUs, not guests. case "$cpu" in - ppc|ppc64|s390|s390x|sparc64|x32) + ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64) cpu="$cpu" supported_cpu="yes" eval "cross_cc_${cpu}=\$host_cc" @@ -6937,6 +6943,8 @@ elif test "$ARCH" = "x86_64" -o "$ARCH" = "x32" ; then QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/i386 $QEMU_INCLUDES" elif test "$ARCH" = "ppc64" ; then QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/ppc $QEMU_INCLUDES" +elif test "$ARCH" = "riscv32" -o "$ARCH" = "riscv64" ; then + QEMU_INCLUDES="-I\$(SRC_PATH)/tcg/riscv $QEMU_INCLUDES" else QEMU_INCLUDES="-iquote \$(SRC_PATH)/tcg/\$(ARCH) $QEMU_INCLUDES" fi @@ -7433,7 +7441,7 @@ for i in $ARCH $TARGET_BASE_ARCH ; do ppc*) disas_config "PPC" ;; - riscv) + riscv*) disas_config "RISCV" ;; s390*) diff --git a/default-configs/riscv32-softmmu.mak b/default-configs/riscv32-softmmu.mak index 7937c69e22..dbc9398284 100644 --- a/default-configs/riscv32-softmmu.mak +++ b/default-configs/riscv32-softmmu.mak @@ -1,7 +1,13 @@ # Default configuration for riscv-softmmu +include pci.mak + CONFIG_SERIAL=y CONFIG_VIRTIO_MMIO=y -include virtio.mak CONFIG_CADENCE=y + +CONFIG_PCI_GENERIC=y + +CONFIG_VGA=y +CONFIG_VGA_PCI=y diff --git a/default-configs/riscv64-softmmu.mak b/default-configs/riscv64-softmmu.mak index 7937c69e22..dbc9398284 100644 --- a/default-configs/riscv64-softmmu.mak +++ b/default-configs/riscv64-softmmu.mak @@ -1,7 +1,13 @@ # Default configuration for riscv-softmmu +include pci.mak + CONFIG_SERIAL=y CONFIG_VIRTIO_MMIO=y -include virtio.mak CONFIG_CADENCE=y + +CONFIG_PCI_GENERIC=y + +CONFIG_VGA=y +CONFIG_VGA_PCI=y diff --git a/disas.c b/disas.c index f9c517b358..d9aa713a40 100644 --- a/disas.c +++ b/disas.c @@ -522,8 +522,14 @@ void disas(FILE *out, void *code, unsigned long size) # ifdef _ARCH_PPC64 s.info.cap_mode = CS_MODE_64; # endif -#elif defined(__riscv__) - print_insn = print_insn_riscv; +#elif defined(__riscv) && defined(CONFIG_RISCV_DIS) +#if defined(_ILP32) || (__riscv_xlen == 32) + print_insn = print_insn_riscv32; +#elif defined(_LP64) + print_insn = print_insn_riscv64; +#else +#error unsupported RISC-V ABI +#endif #elif defined(__aarch64__) && defined(CONFIG_ARM_A64_DIS) print_insn = print_insn_arm_a64; s.info.cap_arch = CS_ARCH_ARM64; diff --git a/disas/microblaze.c b/disas/microblaze.c index 598ecbc89d..c23605043a 100644 --- a/disas/microblaze.c +++ b/disas/microblaze.c @@ -176,7 +176,6 @@ enum microblaze_instr_type { #define REG_TLBSX 36869 /* MMU: TLB Search Index reg */ /* alternate names for gen purpose regs */ -#define REG_SP 1 /* stack pointer */ #define REG_ROSDP 2 /* read-only small data pointer */ #define REG_RWSDP 13 /* read-write small data pointer */ diff --git a/disas/nanomips.cpp b/disas/nanomips.cpp index 1238c2ff33..17f4c22d4f 100644 --- a/disas/nanomips.cpp +++ b/disas/nanomips.cpp @@ -1,13 +1,13 @@ /* * Source file for nanoMIPS disassembler component of QEMU * - * Copyright (C) 2018 Wave Computing + * Copyright (C) 2018 Wave Computing, Inc. * Copyright (C) 2018 Matthew Fortune <matthew.fortune@mips.com> - * Copyright (C) 2018 Aleksandar Markovic <aleksandar.markovic@wavecomp.com> + * Copyright (C) 2018 Aleksandar Markovic <amarkovic@wavecomp.com> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or + * the Free Software Foundation, either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -17,6 +17,14 @@ * * You should have received a copy of the GNU General Public License * along with this program. If not, see <https://www.gnu.org/licenses/>. + * + */ + +/* + * Documentation used while implementing this component: + * + * [1] "MIPS® Architecture Base: nanoMIPS32(tm) Instruction Set Technical + * Reference Manual", Revision 01.01, April 27, 2018 */ extern "C" { @@ -258,7 +266,7 @@ namespace img std::string to_string(img::address a) { char buffer[256]; - sprintf(buffer, "0x%08llx", a); + sprintf(buffer, "0x%" PRIx64, a); return buffer; } @@ -284,69 +292,265 @@ uint64 NMD::renumber_registers(uint64 index, uint64 *register_list, } throw std::runtime_error(img::format( - "Invalid register mapping index %d, size of list = %d", + "Invalid register mapping index %" PRIu64 + ", size of list = %zu", index, register_list_size)); } /* - * these functions should be decode functions but the json does not have - * decode sections so they are based on the encode, the equivalent decode - * functions need writing eventually. + * NMD::decode_gpr_gpr4() - decoder for 'gpr4' gpr encoding type + * + * Map a 4-bit code to the 5-bit register space according to this pattern: + * + * 1 0 + * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * | | | | | | | | | | | | | | | | + * | | | | | | | | | | | | | | | | + * | | | | | | | | | | | └---------------┐ + * | | | | | | | | | | └---------------┐ | + * | | | | | | | | | └---------------┐ | | + * | | | | | | | | └---------------┐ | | | + * | | | | | | | | | | | | | | | | + * | | | | | | | | | | | | | | | | + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * 3 2 1 0 + * + * Used in handling following instructions: + * + * - ADDU[4X4] + * - LW[4X4] + * - MOVEP[REV] + * - MUL[4X4] + * - SW[4X4] */ -uint64 NMD::encode_gpr3(uint64 d) +uint64 NMD::decode_gpr_gpr4(uint64 d) { - static uint64 register_list[] = { 16, 17, 18, 19, 4, 5, 6, 7 }; + static uint64 register_list[] = { 8, 9, 10, 11, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; return renumber_registers(d, register_list, sizeof(register_list) / sizeof(register_list[0])); } -uint64 NMD::encode_gpr3_store(uint64 d) +/* + * NMD::decode_gpr_gpr4_zero() - decoder for 'gpr4.zero' gpr encoding type + * + * Map a 4-bit code to the 5-bit register space according to this pattern: + * + * 1 0 + * 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * | | | | | | | | | | | | | | | | + * | | | | | | | | | | | | └---------------------┐ + * | | | | | | | | | | | └---------------┐ | + * | | | | | | | | | | └---------------┐ | | + * | | | | | | | | | └---------------┐ | | | + * | | | | | | | | └---------------┐ | | | | + * | | | | | | | | | | | | | | | | + * | | | | | | | | | | | | | | | | + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * 3 2 1 0 + * + * This pattern is the same one used for 'gpr4' gpr encoding type, except for + * the input value 3, that is mapped to the output value 0 instead of 11. + * + * Used in handling following instructions: + * + * - MOVE.BALC + * - MOVEP + * - SW[4X4] + */ +uint64 NMD::decode_gpr_gpr4_zero(uint64 d) { - static uint64 register_list[] = { 0, 17, 18, 19, 4, 5, 6, 7 }; + static uint64 register_list[] = { 8, 9, 10, 0, 4, 5, 6, 7, + 16, 17, 18, 19, 20, 21, 22, 23 }; return renumber_registers(d, register_list, sizeof(register_list) / sizeof(register_list[0])); } -uint64 NMD::encode_rd1_from_rd(uint64 d) +/* + * NMD::decode_gpr_gpr3() - decoder for 'gpr3' gpr encoding type + * + * Map a 3-bit code to the 5-bit register space according to this pattern: + * + * 7 6 5 4 3 2 1 0 + * | | | | | | | | + * | | | | | | | | + * | | | └-----------------------┐ + * | | └-----------------------┐ | + * | └-----------------------┐ | | + * └-----------------------┐ | | | + * | | | | | | | | + * ┌-------┘ | | | | | | | + * | ┌-------┘ | | | | | | + * | | ┌-------┘ | | | | | + * | | | ┌-------┘ | | | | + * | | | | | | | | + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * 3 2 1 0 + * + * Used in handling following instructions: + * + * - ADDIU[R1.SP] + * - ADDIU[R2] + * - ADDU[16] + * - AND[16] + * - ANDI[16] + * - BEQC[16] + * - BEQZC[16] + * - BNEC[16] + * - BNEZC[16] + * - LB[16] + * - LBU[16] + * - LH[16] + * - LHU[16] + * - LI[16] + * - LW[16] + * - LW[GP16] + * - LWXS[16] + * - NOT[16] + * - OR[16] + * - SB[16] + * - SH[16] + * - SLL[16] + * - SRL[16] + * - SUBU[16] + * - SW[16] + * - XOR[16] + */ +uint64 NMD::decode_gpr_gpr3(uint64 d) { - static uint64 register_list[] = { 4, 5 }; + static uint64 register_list[] = { 16, 17, 18, 19, 4, 5, 6, 7 }; return renumber_registers(d, register_list, sizeof(register_list) / sizeof(register_list[0])); } -uint64 NMD::encode_gpr4_zero(uint64 d) +/* + * NMD::decode_gpr_gpr3_src_store() - decoder for 'gpr3.src.store' gpr encoding + * type + * + * Map a 3-bit code to the 5-bit register space according to this pattern: + * + * 7 6 5 4 3 2 1 0 + * | | | | | | | | + * | | | | | | | └-----------------------┐ + * | | | └-----------------------┐ | + * | | └-----------------------┐ | | + * | └-----------------------┐ | | | + * └-----------------------┐ | | | | + * | | | | | | | | + * ┌-------┘ | | | | | | | + * | ┌-------┘ | | | | | | + * | | ┌-------┘ | | | | | + * | | | | | | | | + * | | | | | | | | + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * 3 2 1 0 + * + * This pattern is the same one used for 'gpr3' gpr encoding type, except for + * the input value 0, that is mapped to the output value 0 instead of 16. + * + * Used in handling following instructions: + * + * - SB[16] + * - SH[16] + * - SW[16] + * - SW[GP16] + */ +uint64 NMD::decode_gpr_gpr3_src_store(uint64 d) { - static uint64 register_list[] = { 8, 9, 10, 0, 4, 5, 6, 7, - 16, 17, 18, 19, 20, 21, 22, 23 }; + static uint64 register_list[] = { 0, 17, 18, 19, 4, 5, 6, 7 }; return renumber_registers(d, register_list, sizeof(register_list) / sizeof(register_list[0])); } -uint64 NMD::encode_gpr4(uint64 d) +/* + * NMD::decode_gpr_gpr2_reg1() - decoder for 'gpr2.reg1' gpr encoding type + * + * Map a 2-bit code to the 5-bit register space according to this pattern: + * + * 3 2 1 0 + * | | | | + * | | | | + * | | | └-------------------┐ + * | | └-------------------┐ | + * | └-------------------┐ | | + * └-------------------┐ | | | + * | | | | + * | | | | + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * 3 2 1 0 + * + * Used in handling following instructions: + * + * - MOVEP + * - MOVEP[REV] + */ +uint64 NMD::decode_gpr_gpr2_reg1(uint64 d) { - static uint64 register_list[] = { 8, 9, 10, 11, 4, 5, 6, 7, - 16, 17, 18, 19, 20, 21, 22, 23 }; + static uint64 register_list[] = { 4, 5, 6, 7 }; return renumber_registers(d, register_list, sizeof(register_list) / sizeof(register_list[0])); } -uint64 NMD::encode_rd2_reg1(uint64 d) +/* + * NMD::decode_gpr_gpr2_reg2() - decoder for 'gpr2.reg2' gpr encoding type + * + * Map a 2-bit code to the 5-bit register space according to this pattern: + * + * 3 2 1 0 + * | | | | + * | | | | + * | | | └-----------------┐ + * | | └-----------------┐ | + * | └-----------------┐ | | + * └-----------------┐ | | | + * | | | | + * | | | | + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * 3 2 1 0 + * + * Used in handling following instructions: + * + * - MOVEP + * - MOVEP[REV] + */ +uint64 NMD::decode_gpr_gpr2_reg2(uint64 d) { - static uint64 register_list[] = { 4, 5, 6, 7 }; + static uint64 register_list[] = { 5, 6, 7, 8 }; return renumber_registers(d, register_list, sizeof(register_list) / sizeof(register_list[0])); } -uint64 NMD::encode_rd2_reg2(uint64 d) +/* + * NMD::decode_gpr_gpr1() - decoder for 'gpr1' gpr encoding type + * + * Map a 1-bit code to the 5-bit register space according to this pattern: + * + * 1 0 + * | | + * | | + * | └---------------------┐ + * └---------------------┐ | + * | | + * | | + * | | + * | | + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * 3 2 1 0 + * + * Used in handling following instruction: + * + * - MOVE.BALC + */ +uint64 NMD::decode_gpr_gpr1(uint64 d) { - static uint64 register_list[] = { 5, 6, 7, 8 }; + static uint64 register_list[] = { 4, 5 }; return renumber_registers(d, register_list, sizeof(register_list) / sizeof(register_list[0])); } @@ -379,14 +583,14 @@ int64 NMD::neg_copy(int64 d) /* strange wrapper around gpr3 */ uint64 NMD::encode_rs3_and_check_rs3_ge_rt3(uint64 d) { -return encode_gpr3(d); +return decode_gpr_gpr3(d); } /* strange wrapper around gpr3 */ uint64 NMD::encode_rs3_and_check_rs3_lt_rt3(uint64 d) { - return encode_gpr3(d); + return decode_gpr_gpr3(d); } @@ -501,7 +705,8 @@ std::string NMD::GPR(uint64 reg) return gpr_reg[reg]; } - throw std::runtime_error(img::format("Invalid GPR register index %d", reg)); + throw std::runtime_error(img::format("Invalid GPR register index %" PRIu64, + reg)); } @@ -518,7 +723,8 @@ std::string NMD::FPR(uint64 reg) return fpr_reg[reg]; } - throw std::runtime_error(img::format("Invalid FPR register index %d", reg)); + throw std::runtime_error(img::format("Invalid FPR register index %" PRIu64, + reg)); } @@ -532,26 +738,27 @@ std::string NMD::AC(uint64 reg) return ac_reg[reg]; } - throw std::runtime_error(img::format("Invalid AC register index %d", reg)); + throw std::runtime_error(img::format("Invalid AC register index %" PRIu64, + reg)); } std::string NMD::IMMEDIATE(uint64 value) { - return img::format("0x%x", value); + return img::format("0x%" PRIx64, value); } std::string NMD::IMMEDIATE(int64 value) { - return img::format("%d", value); + return img::format("%" PRId64, value); } std::string NMD::CPR(uint64 reg) { /* needs more work */ - return img::format("CP%d", reg); + return img::format("CP%" PRIu64, reg); } @@ -682,7 +889,7 @@ uint64 NMD::extract_shift3_2_1_0(uint64 instruction) } -uint64 NMD::extr_uil3il3bs9Fmsb11(uint64 instruction) +uint64 NMD::extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 3, 9) << 3; @@ -706,7 +913,7 @@ uint64 NMD::extract_rtz3_9_8_7(uint64 instruction) } -uint64 NMD::extr_uil1il1bs17Fmsb17(uint64 instruction) +uint64 NMD::extract_u_17_to_1__s1(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 1, 17) << 1; @@ -714,7 +921,7 @@ uint64 NMD::extr_uil1il1bs17Fmsb17(uint64 instruction) } -int64 NMD::extr_sil11il0bs10Tmsb9(uint64 instruction) +int64 NMD::extract_s__se9_20_19_18_17_16_15_14_13_12_11(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 11, 10); @@ -723,7 +930,7 @@ int64 NMD::extr_sil11il0bs10Tmsb9(uint64 instruction) } -int64 NMD::extr_sil0il11bs1_il1il1bs10Tmsb11(uint64 instruction) +int64 NMD::extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 1) << 11; @@ -766,7 +973,7 @@ uint64 NMD::extract_shift_4_3_2_1_0(uint64 instruction) } -uint64 NMD::extr_shiftxil7il1bs4Fmsb4(uint64 instruction) +uint64 NMD::extract_shiftx_10_9_8_7__s1(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 7, 4) << 1; @@ -790,7 +997,7 @@ uint64 NMD::extract_count3_14_13_12(uint64 instruction) } -int64 NMD::extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(uint64 instruction) +int64 NMD::extract_s__se31_0_11_to_2_20_to_12_s12(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 1) << 31; @@ -801,7 +1008,7 @@ int64 NMD::extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(uint64 instruction) } -int64 NMD::extr_sil0il7bs1_il1il1bs6Tmsb7(uint64 instruction) +int64 NMD::extract_s__se7_0_6_5_4_3_2_1_s1(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 1) << 7; @@ -835,7 +1042,7 @@ uint64 NMD::extract_rs_20_19_18_17_16(uint64 instruction) } -uint64 NMD::extr_uil1il1bs2Fmsb2(uint64 instruction) +uint64 NMD::extract_u_2_1__s1(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 1, 2) << 1; @@ -851,23 +1058,6 @@ uint64 NMD::extract_stripe_6(uint64 instruction) } -uint64 NMD::extr_xil17il0bs1Fmsb0(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 17, 1); - return value; -} - - -uint64 NMD::extr_xil2il0bs1_il15il0bs1Fmsb0(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 2, 1); - value |= extract_bits(instruction, 15, 1); - return value; -} - - uint64 NMD::extract_ac_13_12(uint64 instruction) { uint64 value = 0; @@ -892,7 +1082,7 @@ uint64 NMD::extract_rdl_25_24(uint64 instruction) } -int64 NMD::extr_sil0il10bs1_il1il1bs9Tmsb10(uint64 instruction) +int64 NMD::extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 1) << 10; @@ -918,14 +1108,6 @@ uint64 NMD::extract_shift_5_4_3_2_1_0(uint64 instruction) } -uint64 NMD::extr_xil10il0bs6Fmsb5(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 10, 6); - return value; -} - - uint64 NMD::extract_count_19_18_17_16(uint64 instruction) { uint64 value = 0; @@ -942,15 +1124,6 @@ uint64 NMD::extract_code_2_1_0(uint64 instruction) } -uint64 NMD::extr_xil10il0bs4_il22il0bs4Fmsb3(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 10, 4); - value |= extract_bits(instruction, 22, 4); - return value; -} - - uint64 NMD::extract_u_11_10_9_8_7_6_5_4_3_2_1_0(uint64 instruction) { uint64 value = 0; @@ -967,7 +1140,7 @@ uint64 NMD::extract_rs_4_3_2_1_0(uint64 instruction) } -uint64 NMD::extr_uil3il3bs18Fmsb20(uint64 instruction) +uint64 NMD::extract_u_20_to_3__s3(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 3, 18) << 3; @@ -975,15 +1148,7 @@ uint64 NMD::extr_uil3il3bs18Fmsb20(uint64 instruction) } -uint64 NMD::extr_xil12il0bs1Fmsb0(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 12, 1); - return value; -} - - -uint64 NMD::extr_uil0il2bs4Fmsb5(uint64 instruction) +uint64 NMD::extract_u_3_2_1_0__s2(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 0, 4) << 2; @@ -999,7 +1164,7 @@ uint64 NMD::extract_cofun_25_24_23(uint64 instruction) } -uint64 NMD::extr_uil0il2bs3Fmsb4(uint64 instruction) +uint64 NMD::extract_u_2_1_0__s2(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 0, 3) << 2; @@ -1007,14 +1172,6 @@ uint64 NMD::extr_uil0il2bs3Fmsb4(uint64 instruction) } -uint64 NMD::extr_xil10il0bs1Fmsb0(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 10, 1); - return value; -} - - uint64 NMD::extract_rd3_3_2_1(uint64 instruction) { uint64 value = 0; @@ -1047,22 +1204,6 @@ uint64 NMD::extract_ru_7_6_5_4_3(uint64 instruction) } -uint64 NMD::extr_xil21il0bs5Fmsb4(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 21, 5); - return value; -} - - -uint64 NMD::extr_xil9il0bs3Fmsb2(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 9, 3); - return value; -} - - uint64 NMD::extract_u_17_to_0(uint64 instruction) { uint64 value = 0; @@ -1071,15 +1212,6 @@ uint64 NMD::extract_u_17_to_0(uint64 instruction) } -uint64 NMD::extr_xil14il0bs1_il15il0bs1Fmsb0(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 14, 1); - value |= extract_bits(instruction, 15, 1); - return value; -} - - uint64 NMD::extract_rsz4_4_2_1_0(uint64 instruction) { uint64 value = 0; @@ -1089,15 +1221,7 @@ uint64 NMD::extract_rsz4_4_2_1_0(uint64 instruction) } -uint64 NMD::extr_xil24il0bs1Fmsb0(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 24, 1); - return value; -} - - -int64 NMD::extr_sil0il21bs1_il1il1bs20Tmsb21(uint64 instruction) +int64 NMD::extract_s__se21_0_20_to_1_s1(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 1) << 21; @@ -1140,7 +1264,7 @@ uint64 NMD::extract_rt_41_40_39_38_37(uint64 instruction) } -int64 NMD::extract_shift_21_20_19_18_17_16(uint64 instruction) +int64 NMD::extract_shift__se5_21_20_19_18_17_16(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 16, 6); @@ -1149,15 +1273,6 @@ int64 NMD::extract_shift_21_20_19_18_17_16(uint64 instruction) } -uint64 NMD::extr_xil6il0bs3_il10il0bs1Fmsb2(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 6, 3); - value |= extract_bits(instruction, 10, 1); - return value; -} - - uint64 NMD::extract_rd2_3_8(uint64 instruction) { uint64 value = 0; @@ -1167,14 +1282,6 @@ uint64 NMD::extract_rd2_3_8(uint64 instruction) } -uint64 NMD::extr_xil16il0bs5Fmsb4(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 16, 5); - return value; -} - - uint64 NMD::extract_code_17_to_0(uint64 instruction) { uint64 value = 0; @@ -1183,14 +1290,6 @@ uint64 NMD::extract_code_17_to_0(uint64 instruction) } -uint64 NMD::extr_xil0il0bs12Fmsb11(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 0, 12); - return value; -} - - uint64 NMD::extract_size_20_19_18_17_16(uint64 instruction) { uint64 value = 0; @@ -1199,7 +1298,7 @@ uint64 NMD::extract_size_20_19_18_17_16(uint64 instruction) } -int64 NMD::extr_sil2il2bs6_il15il8bs1Tmsb8(uint64 instruction) +int64 NMD::extract_s__se8_15_7_6_5_4_3_2_s2(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 2, 6) << 2; @@ -1217,7 +1316,7 @@ uint64 NMD::extract_u_15_to_0(uint64 instruction) } -uint64 NMD::extract_fs_15_14_13_12_11(uint64 instruction) +uint64 NMD::extract_fs_20_19_18_17_16(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 16, 5); @@ -1225,7 +1324,7 @@ uint64 NMD::extract_fs_15_14_13_12_11(uint64 instruction) } -int64 NMD::extr_sil0il0bs8_il15il8bs1Tmsb8(uint64 instruction) +int64 NMD::extract_s__se8_15_7_6_5_4_3_2_1_0(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 8); @@ -1259,15 +1358,6 @@ uint64 NMD::extract_hs_20_19_18_17_16(uint64 instruction) } -uint64 NMD::extr_xil10il0bs1_il14il0bs2Fmsb1(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 10, 1); - value |= extract_bits(instruction, 14, 2); - return value; -} - - uint64 NMD::extract_sel_13_12_11(uint64 instruction) { uint64 value = 0; @@ -1284,14 +1374,6 @@ uint64 NMD::extract_lsb_4_3_2_1_0(uint64 instruction) } -uint64 NMD::extr_xil14il0bs2Fmsb1(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 14, 2); - return value; -} - - uint64 NMD::extract_gp_2(uint64 instruction) { uint64 value = 0; @@ -1308,7 +1390,7 @@ uint64 NMD::extract_rt3_9_8_7(uint64 instruction) } -uint64 NMD::extract_ft_20_19_18_17_16(uint64 instruction) +uint64 NMD::extract_ft_25_24_23_22_21(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 21, 5); @@ -1332,14 +1414,6 @@ uint64 NMD::extract_cs_20_19_18_17_16(uint64 instruction) } -uint64 NMD::extr_xil16il0bs10Fmsb9(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 16, 10); - return value; -} - - uint64 NMD::extract_rt4_9_7_6_5(uint64 instruction) { uint64 value = 0; @@ -1357,7 +1431,7 @@ uint64 NMD::extract_msbt_10_9_8_7_6(uint64 instruction) } -uint64 NMD::extr_uil0il2bs6Fmsb7(uint64 instruction) +uint64 NMD::extract_u_5_4_3_2_1_0__s2(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 0, 6) << 2; @@ -1365,14 +1439,6 @@ uint64 NMD::extr_uil0il2bs6Fmsb7(uint64 instruction) } -uint64 NMD::extr_xil17il0bs9Fmsb8(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 17, 9); - return value; -} - - uint64 NMD::extract_sa_15_14_13(uint64 instruction) { uint64 value = 0; @@ -1381,7 +1447,7 @@ uint64 NMD::extract_sa_15_14_13(uint64 instruction) } -int64 NMD::extr_sil0il14bs1_il1il1bs13Tmsb14(uint64 instruction) +int64 NMD::extract_s__se14_0_13_to_1_s1(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 1) << 14; @@ -1399,7 +1465,7 @@ uint64 NMD::extract_rs3_6_5_4(uint64 instruction) } -uint64 NMD::extr_uil0il32bs32Fmsb63(uint64 instruction) +uint64 NMD::extract_u_31_to_0__s32(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 0, 32) << 32; @@ -1447,7 +1513,7 @@ uint64 NMD::extract_op_25_24_23_22_21(uint64 instruction) } -uint64 NMD::extr_uil0il2bs7Fmsb8(uint64 instruction) +uint64 NMD::extract_u_6_5_4_3_2_1_0__s2(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 0, 7) << 2; @@ -1463,15 +1529,6 @@ uint64 NMD::extract_bit_16_15_14_13_12_11(uint64 instruction) } -uint64 NMD::extr_xil10il0bs1_il11il0bs5Fmsb4(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 10, 1); - value |= extract_bits(instruction, 11, 5); - return value; -} - - uint64 NMD::extract_mask_20_19_18_17_16_15_14(uint64 instruction) { uint64 value = 0; @@ -1488,7 +1545,7 @@ uint64 NMD::extract_eu_3_2_1_0(uint64 instruction) } -uint64 NMD::extr_uil4il4bs4Fmsb7(uint64 instruction) +uint64 NMD::extract_u_7_6_5_4__s4(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 4, 4) << 4; @@ -1496,7 +1553,7 @@ uint64 NMD::extr_uil4il4bs4Fmsb7(uint64 instruction) } -int64 NMD::extr_sil3il3bs5_il15il8bs1Tmsb8(uint64 instruction) +int64 NMD::extract_s__se8_15_7_6_5_4_3_s3(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 3, 5) << 3; @@ -1514,7 +1571,7 @@ uint64 NMD::extract_ft_15_14_13_12_11(uint64 instruction) } -int64 NMD::extr_sil0il16bs16_il16il0bs16Tmsb31(uint64 instruction) +int64 NMD::extract_s__se31_15_to_0_31_to_16(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 16) << 16; @@ -1532,23 +1589,7 @@ uint64 NMD::extract_u_20_19_18_17_16_15_14_13(uint64 instruction) } -uint64 NMD::extr_xil15il0bs1Fmsb0(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 15, 1); - return value; -} - - -uint64 NMD::extr_xil11il0bs5Fmsb4(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 11, 5); - return value; -} - - -uint64 NMD::extr_uil2il2bs16Fmsb17(uint64 instruction) +uint64 NMD::extract_u_17_to_2__s2(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 2, 16) << 2; @@ -1556,7 +1597,7 @@ uint64 NMD::extr_uil2il2bs16Fmsb17(uint64 instruction) } -uint64 NMD::extract_rd_20_19_18_17_16(uint64 instruction) +uint64 NMD::extract_rd_15_14_13_12_11(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 11, 5); @@ -1580,7 +1621,7 @@ uint64 NMD::extract_code_1_0(uint64 instruction) } -int64 NMD::extr_sil0il25bs1_il1il1bs24Tmsb25(uint64 instruction) +int64 NMD::extract_s__se25_0_24_to_1_s1(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 1) << 25; @@ -1590,15 +1631,6 @@ int64 NMD::extr_sil0il25bs1_il1il1bs24Tmsb25(uint64 instruction) } -uint64 NMD::extr_xil0il0bs3_il4il0bs1Fmsb2(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 0, 3); - value |= extract_bits(instruction, 4, 1); - return value; -} - - uint64 NMD::extract_u_1_0(uint64 instruction) { uint64 value = 0; @@ -1607,7 +1639,7 @@ uint64 NMD::extract_u_1_0(uint64 instruction) } -uint64 NMD::extr_uil3il3bs1_il8il2bs1Fmsb3(uint64 instruction) +uint64 NMD::extract_u_3_8__s2(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 3, 1) << 3; @@ -1616,16 +1648,7 @@ uint64 NMD::extr_uil3il3bs1_il8il2bs1Fmsb3(uint64 instruction) } -uint64 NMD::extr_xil9il0bs3_il16il0bs5Fmsb4(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 9, 3); - value |= extract_bits(instruction, 16, 5); - return value; -} - - -uint64 NMD::extract_fd_10_9_8_7_6(uint64 instruction) +uint64 NMD::extract_fd_15_14_13_12_11(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 11, 5); @@ -1633,15 +1656,7 @@ uint64 NMD::extract_fd_10_9_8_7_6(uint64 instruction) } -uint64 NMD::extr_xil6il0bs3Fmsb2(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 6, 3); - return value; -} - - -uint64 NMD::extr_uil0il2bs5Fmsb6(uint64 instruction) +uint64 NMD::extract_u_4_3_2_1_0__s2(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 0, 5) << 2; @@ -1674,15 +1689,7 @@ uint64 NMD::extract_ct_25_24_23_22_21(uint64 instruction) } -uint64 NMD::extr_xil11il0bs1Fmsb0(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 11, 1); - return value; -} - - -uint64 NMD::extr_uil2il2bs19Fmsb20(uint64 instruction) +uint64 NMD::extract_u_20_to_2__s2(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 2, 19) << 2; @@ -1690,7 +1697,7 @@ uint64 NMD::extr_uil2il2bs19Fmsb20(uint64 instruction) } -int64 NMD::extract_s_4_2_1_0(uint64 instruction) +int64 NMD::extract_s__se3_4_2_1_0(uint64 instruction) { int64 value = 0; value |= extract_bits(instruction, 0, 3); @@ -1700,7 +1707,7 @@ int64 NMD::extract_s_4_2_1_0(uint64 instruction) } -uint64 NMD::extr_uil0il1bs4Fmsb4(uint64 instruction) +uint64 NMD::extract_u_3_2_1_0__s1(uint64 instruction) { uint64 value = 0; value |= extract_bits(instruction, 0, 4) << 1; @@ -1708,14 +1715,6 @@ uint64 NMD::extr_uil0il1bs4Fmsb4(uint64 instruction) } -uint64 NMD::extr_xil9il0bs2Fmsb1(uint64 instruction) -{ - uint64 value = 0; - value |= extract_bits(instruction, 9, 2); - return value; -} - - bool NMD::ADDIU_32__cond(uint64 instruction) { @@ -1742,7 +1741,7 @@ bool NMD::BEQC_16__cond(uint64 instruction) { uint64 rs3 = extract_rs3_6_5_4(instruction); uint64 rt3 = extract_rt3_9_8_7(instruction); - uint64 u = extr_uil0il1bs4Fmsb4(instruction); + uint64 u = extract_u_3_2_1_0__s1(instruction); return rs3 < rt3 && u != 0; } @@ -1751,7 +1750,7 @@ bool NMD::BNEC_16__cond(uint64 instruction) { uint64 rs3 = extract_rs3_6_5_4(instruction); uint64 rt3 = extract_rt3_9_8_7(instruction); - uint64 u = extr_uil0il1bs4Fmsb4(instruction); + uint64 u = extract_u_3_2_1_0__s1(instruction); return rs3 >= rt3 && u != 0; } @@ -1765,7 +1764,7 @@ bool NMD::MOVE_cond(uint64 instruction) bool NMD::P16_BR1_cond(uint64 instruction) { - uint64 u = extr_uil0il1bs4Fmsb4(instruction); + uint64 u = extract_u_3_2_1_0__s1(instruction); return u != 0; } @@ -1786,7 +1785,7 @@ bool NMD::PREFE_cond(uint64 instruction) bool NMD::SLTU_cond(uint64 instruction) { - uint64 rd = extract_rd_20_19_18_17_16(instruction); + uint64 rd = extract_rd_15_14_13_12_11(instruction); return rd != 0; } @@ -1804,8 +1803,8 @@ bool NMD::SLTU_cond(uint64 instruction) */ std::string NMD::ABS_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 fd_value = extract_ft_20_19_18_17_16(instruction); + uint64 fd_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string fs = FPR(copy(fs_value)); std::string fd = FPR(copy(fd_value)); @@ -1826,8 +1825,8 @@ std::string NMD::ABS_D(uint64 instruction) */ std::string NMD::ABS_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 fd_value = extract_ft_20_19_18_17_16(instruction); + uint64 fd_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string fs = FPR(copy(fs_value)); std::string fd = FPR(copy(fd_value)); @@ -1911,8 +1910,8 @@ std::string NMD::ABSQ_S_W(uint64 instruction) std::string NMD::ACLR(uint64 instruction) { uint64 bit_value = extract_bit_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string bit = IMMEDIATE(copy(bit_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -1934,8 +1933,8 @@ std::string NMD::ACLR(uint64 instruction) std::string NMD::ADD(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -1958,9 +1957,9 @@ std::string NMD::ADD(uint64 instruction) */ std::string NMD::ADD_D(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -1983,9 +1982,9 @@ std::string NMD::ADD_D(uint64 instruction) */ std::string NMD::ADD_S(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -2007,8 +2006,8 @@ std::string NMD::ADD_S(uint64 instruction) std::string NMD::ADDIU_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_15_to_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_15_to_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -2030,7 +2029,7 @@ std::string NMD::ADDIU_32_(uint64 instruction) std::string NMD::ADDIU_48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction); + int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -2051,7 +2050,7 @@ std::string NMD::ADDIU_48_(uint64 instruction) std::string NMD::ADDIU_GP48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction); + int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -2093,7 +2092,7 @@ std::string NMD::ADDIU_GP_B_(uint64 instruction) std::string NMD::ADDIU_GP_W_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil2il2bs19Fmsb20(instruction); + uint64 u_value = extract_u_20_to_2__s2(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -2114,8 +2113,8 @@ std::string NMD::ADDIU_GP_W_(uint64 instruction) std::string NMD::ADDIU_NEG_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -2136,10 +2135,10 @@ std::string NMD::ADDIU_NEG_(uint64 instruction) */ std::string NMD::ADDIU_R1_SP_(uint64 instruction) { - uint64 u_value = extr_uil0il2bs6Fmsb7(instruction); + uint64 u_value = extract_u_5_4_3_2_1_0__s2(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string u = IMMEDIATE(copy(u_value)); return img::format("ADDIU %s, $%d, %s", rt3, 29, u); @@ -2157,12 +2156,12 @@ std::string NMD::ADDIU_R1_SP_(uint64 instruction) */ std::string NMD::ADDIU_R2_(uint64 instruction) { - uint64 u_value = extr_uil0il2bs3Fmsb4(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_2_1_0__s2(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); std::string u = IMMEDIATE(copy(u_value)); return img::format("ADDIU %s, %s, %s", rt3, rs3, u); @@ -2180,7 +2179,7 @@ std::string NMD::ADDIU_R2_(uint64 instruction) std::string NMD::ADDIU_RS5_(uint64 instruction) { uint64 rt_value = extract_rt_9_8_7_6_5(instruction); - int64 s_value = extract_s_4_2_1_0(instruction); + int64 s_value = extract_s__se3_4_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -2202,7 +2201,7 @@ std::string NMD::ADDIU_RS5_(uint64 instruction) std::string NMD::ADDIUPC_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il21bs1_il1il1bs20Tmsb21(instruction); + int64 s_value = extract_s__se21_0_20_to_1_s1(instruction); std::string rt = GPR(copy(rt_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 4); @@ -2224,7 +2223,7 @@ std::string NMD::ADDIUPC_32_(uint64 instruction) std::string NMD::ADDIUPC_48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction); + int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); std::string rt = GPR(copy(rt_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 6); @@ -2246,8 +2245,8 @@ std::string NMD::ADDIUPC_48_(uint64 instruction) std::string NMD::ADDQ_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2270,8 +2269,8 @@ std::string NMD::ADDQ_PH(uint64 instruction) std::string NMD::ADDQ_S_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2294,8 +2293,8 @@ std::string NMD::ADDQ_S_PH(uint64 instruction) std::string NMD::ADDQ_S_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2319,8 +2318,8 @@ std::string NMD::ADDQ_S_W(uint64 instruction) std::string NMD::ADDQH_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2344,8 +2343,8 @@ std::string NMD::ADDQH_PH(uint64 instruction) std::string NMD::ADDQH_R_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2368,8 +2367,8 @@ std::string NMD::ADDQH_R_PH(uint64 instruction) std::string NMD::ADDQH_R_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2392,8 +2391,8 @@ std::string NMD::ADDQH_R_W(uint64 instruction) std::string NMD::ADDQH_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2416,8 +2415,8 @@ std::string NMD::ADDQH_W(uint64 instruction) std::string NMD::ADDSC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2442,9 +2441,9 @@ std::string NMD::ADDU_16_(uint64 instruction) uint64 rs3_value = extract_rs3_6_5_4(instruction); uint64 rd3_value = extract_rd3_3_2_1(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); - std::string rd3 = GPR(encode_gpr3(rd3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); + std::string rd3 = GPR(decode_gpr_gpr3(rd3_value)); return img::format("ADDU %s, %s, %s", rd3, rs3, rt3); } @@ -2463,8 +2462,8 @@ std::string NMD::ADDU_16_(uint64 instruction) std::string NMD::ADDU_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2486,11 +2485,11 @@ std::string NMD::ADDU_32_(uint64 instruction) */ std::string NMD::ADDU_4X4_(uint64 instruction) { - uint64 rs4_value = extract_rs4_4_2_1_0(instruction); uint64 rt4_value = extract_rt4_9_7_6_5(instruction); + uint64 rs4_value = extract_rs4_4_2_1_0(instruction); - std::string rs4 = GPR(encode_gpr4(rs4_value)); - std::string rt4 = GPR(encode_gpr4(rt4_value)); + std::string rs4 = GPR(decode_gpr_gpr4(rs4_value)); + std::string rt4 = GPR(decode_gpr_gpr4(rt4_value)); return img::format("ADDU %s, %s", rs4, rt4); } @@ -2509,8 +2508,8 @@ std::string NMD::ADDU_4X4_(uint64 instruction) std::string NMD::ADDU_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2533,8 +2532,8 @@ std::string NMD::ADDU_PH(uint64 instruction) std::string NMD::ADDU_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2557,8 +2556,8 @@ std::string NMD::ADDU_QB(uint64 instruction) std::string NMD::ADDU_S_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2581,8 +2580,8 @@ std::string NMD::ADDU_S_PH(uint64 instruction) std::string NMD::ADDU_S_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2606,8 +2605,8 @@ std::string NMD::ADDU_S_QB(uint64 instruction) std::string NMD::ADDUH_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2631,8 +2630,8 @@ std::string NMD::ADDUH_QB(uint64 instruction) std::string NMD::ADDUH_R_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2654,8 +2653,8 @@ std::string NMD::ADDUH_R_QB(uint64 instruction) std::string NMD::ADDWC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2678,7 +2677,7 @@ std::string NMD::ADDWC(uint64 instruction) std::string NMD::ALUIPC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(instruction); + int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 4); @@ -2701,8 +2700,8 @@ std::string NMD::AND_16_(uint64 instruction) uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("AND %s, %s", rs3, rt3); } @@ -2721,8 +2720,8 @@ std::string NMD::AND_16_(uint64 instruction) std::string NMD::AND_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -2747,8 +2746,8 @@ std::string NMD::ANDI_16_(uint64 instruction) uint64 rs3_value = extract_rs3_6_5_4(instruction); uint64 eu_value = extract_eu_3_2_1_0(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); std::string eu = IMMEDIATE(encode_eu_from_u_andi16(eu_value)); return img::format("ANDI %s, %s, %s", rt3, rs3, eu); @@ -2768,8 +2767,8 @@ std::string NMD::ANDI_16_(uint64 instruction) std::string NMD::ANDI_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -2792,8 +2791,8 @@ std::string NMD::ANDI_32_(uint64 instruction) std::string NMD::APPEND(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13_12_11(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -2816,8 +2815,8 @@ std::string NMD::APPEND(uint64 instruction) std::string NMD::ASET(uint64 instruction) { uint64 bit_value = extract_bit_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string bit = IMMEDIATE(copy(bit_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -2839,7 +2838,7 @@ std::string NMD::ASET(uint64 instruction) */ std::string NMD::BALC_16_(uint64 instruction) { - int64 s_value = extr_sil0il10bs1_il1il1bs9Tmsb10(instruction); + int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction); std::string s = ADDRESS(encode_s_from_address(s_value), 2); @@ -2859,7 +2858,7 @@ std::string NMD::BALC_16_(uint64 instruction) */ std::string NMD::BALC_32_(uint64 instruction) { - int64 s_value = extr_sil0il25bs1_il1il1bs24Tmsb25(instruction); + int64 s_value = extract_s__se25_0_24_to_1_s1(instruction); std::string s = ADDRESS(encode_s_from_address(s_value), 4); @@ -2903,7 +2902,7 @@ std::string NMD::BBEQZC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction); - int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction); + int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); std::string rt = GPR(copy(rt_value)); std::string bit = IMMEDIATE(copy(bit_value)); @@ -2927,7 +2926,7 @@ std::string NMD::BBNEZC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); uint64 bit_value = extract_bit_16_15_14_13_12_11(instruction); - int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction); + int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); std::string rt = GPR(copy(rt_value)); std::string bit = IMMEDIATE(copy(bit_value)); @@ -2949,7 +2948,7 @@ std::string NMD::BBNEZC(uint64 instruction) */ std::string NMD::BC_16_(uint64 instruction) { - int64 s_value = extr_sil0il10bs1_il1il1bs9Tmsb10(instruction); + int64 s_value = extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(instruction); std::string s = ADDRESS(encode_s_from_address(s_value), 2); @@ -2969,7 +2968,7 @@ std::string NMD::BC_16_(uint64 instruction) */ std::string NMD::BC_32_(uint64 instruction) { - int64 s_value = extr_sil0il25bs1_il1il1bs24Tmsb25(instruction); + int64 s_value = extract_s__se25_0_24_to_1_s1(instruction); std::string s = ADDRESS(encode_s_from_address(s_value), 4); @@ -2989,8 +2988,8 @@ std::string NMD::BC_32_(uint64 instruction) */ std::string NMD::BC1EQZC(uint64 instruction) { - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string ft = FPR(copy(ft_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 4); @@ -3011,8 +3010,8 @@ std::string NMD::BC1EQZC(uint64 instruction) */ std::string NMD::BC1NEZC(uint64 instruction) { - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string ft = FPR(copy(ft_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 4); @@ -3033,8 +3032,8 @@ std::string NMD::BC1NEZC(uint64 instruction) */ std::string NMD::BC2EQZC(uint64 instruction) { - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); uint64 ct_value = extract_ct_25_24_23_22_21(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string ct = CPR(copy(ct_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 4); @@ -3055,8 +3054,8 @@ std::string NMD::BC2EQZC(uint64 instruction) */ std::string NMD::BC2NEZC(uint64 instruction) { - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); uint64 ct_value = extract_ct_25_24_23_22_21(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string ct = CPR(copy(ct_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 4); @@ -3077,12 +3076,12 @@ std::string NMD::BC2NEZC(uint64 instruction) */ std::string NMD::BEQC_16_(uint64 instruction) { - uint64 u_value = extr_uil0il1bs4Fmsb4(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_3_2_1_0__s1(instruction); std::string rs3 = GPR(encode_rs3_and_check_rs3_lt_rt3(rs3_value)); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string u = ADDRESS(encode_u_from_address(u_value), 2); return img::format("BEQC %s, %s, %s", rs3, rt3, u); @@ -3102,8 +3101,8 @@ std::string NMD::BEQC_16_(uint64 instruction) std::string NMD::BEQC_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string rs = GPR(copy(rs_value)); std::string rt = GPR(copy(rt_value)); @@ -3126,8 +3125,8 @@ std::string NMD::BEQC_32_(uint64 instruction) std::string NMD::BEQIC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction); uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); + int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -3149,10 +3148,10 @@ std::string NMD::BEQIC(uint64 instruction) */ std::string NMD::BEQZC_16_(uint64 instruction) { - int64 s_value = extr_sil0il7bs1_il1il1bs6Tmsb7(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); + int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 2); return img::format("BEQZC %s, %s", rt3, s); @@ -3172,8 +3171,8 @@ std::string NMD::BEQZC_16_(uint64 instruction) std::string NMD::BGEC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string rs = GPR(copy(rs_value)); std::string rt = GPR(copy(rt_value)); @@ -3196,8 +3195,8 @@ std::string NMD::BGEC(uint64 instruction) std::string NMD::BGEIC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction); uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); + int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -3220,8 +3219,8 @@ std::string NMD::BGEIC(uint64 instruction) std::string NMD::BGEIUC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction); uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); + int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -3244,8 +3243,8 @@ std::string NMD::BGEIUC(uint64 instruction) std::string NMD::BGEUC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string rs = GPR(copy(rs_value)); std::string rt = GPR(copy(rt_value)); @@ -3268,8 +3267,8 @@ std::string NMD::BGEUC(uint64 instruction) std::string NMD::BLTC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string rs = GPR(copy(rs_value)); std::string rt = GPR(copy(rt_value)); @@ -3292,8 +3291,8 @@ std::string NMD::BLTC(uint64 instruction) std::string NMD::BLTIC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction); uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); + int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -3316,8 +3315,8 @@ std::string NMD::BLTIC(uint64 instruction) std::string NMD::BLTIUC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction); uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); + int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -3340,8 +3339,8 @@ std::string NMD::BLTIUC(uint64 instruction) std::string NMD::BLTUC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string rs = GPR(copy(rs_value)); std::string rt = GPR(copy(rt_value)); @@ -3363,12 +3362,12 @@ std::string NMD::BLTUC(uint64 instruction) */ std::string NMD::BNEC_16_(uint64 instruction) { - uint64 u_value = extr_uil0il1bs4Fmsb4(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_3_2_1_0__s1(instruction); std::string rs3 = GPR(encode_rs3_and_check_rs3_ge_rt3(rs3_value)); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string u = ADDRESS(encode_u_from_address(u_value), 2); return img::format("BNEC %s, %s, %s", rs3, rt3, u); @@ -3388,8 +3387,8 @@ std::string NMD::BNEC_16_(uint64 instruction) std::string NMD::BNEC_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string rs = GPR(copy(rs_value)); std::string rt = GPR(copy(rt_value)); @@ -3412,8 +3411,8 @@ std::string NMD::BNEC_32_(uint64 instruction) std::string NMD::BNEIC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il11bs1_il1il1bs10Tmsb11(instruction); uint64 u_value = extract_u_17_16_15_14_13_12_11(instruction); + int64 s_value = extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -3435,10 +3434,10 @@ std::string NMD::BNEIC(uint64 instruction) */ std::string NMD::BNEZC_16_(uint64 instruction) { - int64 s_value = extr_sil0il7bs1_il1il1bs6Tmsb7(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); + int64 s_value = extract_s__se7_0_6_5_4_3_2_1_s1(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 2); return img::format("BNEZC %s, %s", rt3, s); @@ -3457,7 +3456,7 @@ std::string NMD::BNEZC_16_(uint64 instruction) */ std::string NMD::BPOSGE32C(uint64 instruction) { - int64 s_value = extr_sil0il14bs1_il1il1bs13Tmsb14(instruction); + int64 s_value = extract_s__se14_0_13_to_1_s1(instruction); std::string s = ADDRESS(encode_s_from_address(s_value), 4); @@ -3537,9 +3536,9 @@ std::string NMD::BRSC(uint64 instruction) */ std::string NMD::CACHE(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 op_value = extract_op_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string op = IMMEDIATE(copy(op_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -3561,9 +3560,9 @@ std::string NMD::CACHE(uint64 instruction) */ std::string NMD::CACHEE(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 op_value = extract_op_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string op = IMMEDIATE(copy(op_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -3585,8 +3584,8 @@ std::string NMD::CACHEE(uint64 instruction) */ std::string NMD::CEIL_L_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -3607,8 +3606,8 @@ std::string NMD::CEIL_L_D(uint64 instruction) */ std::string NMD::CEIL_L_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -3629,8 +3628,8 @@ std::string NMD::CEIL_L_S(uint64 instruction) */ std::string NMD::CEIL_W_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -3651,8 +3650,8 @@ std::string NMD::CEIL_W_D(uint64 instruction) */ std::string NMD::CEIL_W_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -3673,8 +3672,8 @@ std::string NMD::CEIL_W_S(uint64 instruction) */ std::string NMD::CFC1(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -3695,8 +3694,8 @@ std::string NMD::CFC1(uint64 instruction) */ std::string NMD::CFC2(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -3717,8 +3716,8 @@ std::string NMD::CFC2(uint64 instruction) */ std::string NMD::CLASS_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -3739,8 +3738,8 @@ std::string NMD::CLASS_D(uint64 instruction) */ std::string NMD::CLASS_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -3805,9 +3804,9 @@ std::string NMD::CLZ(uint64 instruction) */ std::string NMD::CMP_AF_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -3829,9 +3828,9 @@ std::string NMD::CMP_AF_D(uint64 instruction) */ std::string NMD::CMP_AF_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -3853,9 +3852,9 @@ std::string NMD::CMP_AF_S(uint64 instruction) */ std::string NMD::CMP_EQ_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -3899,9 +3898,9 @@ std::string NMD::CMP_EQ_PH(uint64 instruction) */ std::string NMD::CMP_EQ_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -3923,9 +3922,9 @@ std::string NMD::CMP_EQ_S(uint64 instruction) */ std::string NMD::CMP_LE_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -3969,9 +3968,9 @@ std::string NMD::CMP_LE_PH(uint64 instruction) */ std::string NMD::CMP_LE_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -3993,9 +3992,9 @@ std::string NMD::CMP_LE_S(uint64 instruction) */ std::string NMD::CMP_LT_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4039,9 +4038,9 @@ std::string NMD::CMP_LT_PH(uint64 instruction) */ std::string NMD::CMP_LT_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4063,9 +4062,9 @@ std::string NMD::CMP_LT_S(uint64 instruction) */ std::string NMD::CMP_NE_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4087,9 +4086,9 @@ std::string NMD::CMP_NE_D(uint64 instruction) */ std::string NMD::CMP_NE_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4111,9 +4110,9 @@ std::string NMD::CMP_NE_S(uint64 instruction) */ std::string NMD::CMP_OR_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4135,9 +4134,9 @@ std::string NMD::CMP_OR_D(uint64 instruction) */ std::string NMD::CMP_OR_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4159,9 +4158,9 @@ std::string NMD::CMP_OR_S(uint64 instruction) */ std::string NMD::CMP_SAF_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4183,9 +4182,9 @@ std::string NMD::CMP_SAF_D(uint64 instruction) */ std::string NMD::CMP_SAF_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4207,9 +4206,9 @@ std::string NMD::CMP_SAF_S(uint64 instruction) */ std::string NMD::CMP_SEQ_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4231,9 +4230,9 @@ std::string NMD::CMP_SEQ_D(uint64 instruction) */ std::string NMD::CMP_SEQ_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4255,9 +4254,9 @@ std::string NMD::CMP_SEQ_S(uint64 instruction) */ std::string NMD::CMP_SLE_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4279,9 +4278,9 @@ std::string NMD::CMP_SLE_D(uint64 instruction) */ std::string NMD::CMP_SLE_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4303,9 +4302,9 @@ std::string NMD::CMP_SLE_S(uint64 instruction) */ std::string NMD::CMP_SLT_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4327,9 +4326,9 @@ std::string NMD::CMP_SLT_D(uint64 instruction) */ std::string NMD::CMP_SLT_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4351,9 +4350,9 @@ std::string NMD::CMP_SLT_S(uint64 instruction) */ std::string NMD::CMP_SNE_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4375,9 +4374,9 @@ std::string NMD::CMP_SNE_D(uint64 instruction) */ std::string NMD::CMP_SNE_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4399,9 +4398,9 @@ std::string NMD::CMP_SNE_S(uint64 instruction) */ std::string NMD::CMP_SOR_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4423,9 +4422,9 @@ std::string NMD::CMP_SOR_D(uint64 instruction) */ std::string NMD::CMP_SOR_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4447,9 +4446,9 @@ std::string NMD::CMP_SOR_S(uint64 instruction) */ std::string NMD::CMP_SUEQ_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4471,9 +4470,9 @@ std::string NMD::CMP_SUEQ_D(uint64 instruction) */ std::string NMD::CMP_SUEQ_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4495,9 +4494,9 @@ std::string NMD::CMP_SUEQ_S(uint64 instruction) */ std::string NMD::CMP_SULE_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4519,9 +4518,9 @@ std::string NMD::CMP_SULE_D(uint64 instruction) */ std::string NMD::CMP_SULE_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4543,9 +4542,9 @@ std::string NMD::CMP_SULE_S(uint64 instruction) */ std::string NMD::CMP_SULT_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4567,9 +4566,9 @@ std::string NMD::CMP_SULT_D(uint64 instruction) */ std::string NMD::CMP_SULT_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4591,9 +4590,9 @@ std::string NMD::CMP_SULT_S(uint64 instruction) */ std::string NMD::CMP_SUN_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4615,9 +4614,9 @@ std::string NMD::CMP_SUN_D(uint64 instruction) */ std::string NMD::CMP_SUNE_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4639,9 +4638,9 @@ std::string NMD::CMP_SUNE_D(uint64 instruction) */ std::string NMD::CMP_SUNE_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4663,9 +4662,9 @@ std::string NMD::CMP_SUNE_S(uint64 instruction) */ std::string NMD::CMP_SUN_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4687,9 +4686,9 @@ std::string NMD::CMP_SUN_S(uint64 instruction) */ std::string NMD::CMP_UEQ_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4711,9 +4710,9 @@ std::string NMD::CMP_UEQ_D(uint64 instruction) */ std::string NMD::CMP_UEQ_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4735,9 +4734,9 @@ std::string NMD::CMP_UEQ_S(uint64 instruction) */ std::string NMD::CMP_ULE_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4759,9 +4758,9 @@ std::string NMD::CMP_ULE_D(uint64 instruction) */ std::string NMD::CMP_ULE_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4783,9 +4782,9 @@ std::string NMD::CMP_ULE_S(uint64 instruction) */ std::string NMD::CMP_ULT_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4807,9 +4806,9 @@ std::string NMD::CMP_ULT_D(uint64 instruction) */ std::string NMD::CMP_ULT_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4831,9 +4830,9 @@ std::string NMD::CMP_ULT_S(uint64 instruction) */ std::string NMD::CMP_UN_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4855,9 +4854,9 @@ std::string NMD::CMP_UN_D(uint64 instruction) */ std::string NMD::CMP_UNE_D(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4879,9 +4878,9 @@ std::string NMD::CMP_UNE_D(uint64 instruction) */ std::string NMD::CMP_UNE_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4903,9 +4902,9 @@ std::string NMD::CMP_UNE_S(uint64 instruction) */ std::string NMD::CMP_UN_S(uint64 instruction) { - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -4928,8 +4927,8 @@ std::string NMD::CMP_UN_S(uint64 instruction) std::string NMD::CMPGDU_EQ_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -4952,8 +4951,8 @@ std::string NMD::CMPGDU_EQ_QB(uint64 instruction) std::string NMD::CMPGDU_LE_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -4976,8 +4975,8 @@ std::string NMD::CMPGDU_LE_QB(uint64 instruction) std::string NMD::CMPGDU_LT_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5000,8 +4999,8 @@ std::string NMD::CMPGDU_LT_QB(uint64 instruction) std::string NMD::CMPGU_EQ_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5024,8 +5023,8 @@ std::string NMD::CMPGU_EQ_QB(uint64 instruction) std::string NMD::CMPGU_LE_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5048,8 +5047,8 @@ std::string NMD::CMPGU_LE_QB(uint64 instruction) std::string NMD::CMPGU_LT_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5157,8 +5156,8 @@ std::string NMD::COP2_1(uint64 instruction) */ std::string NMD::CTC1(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -5179,8 +5178,8 @@ std::string NMD::CTC1(uint64 instruction) */ std::string NMD::CTC2(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -5201,8 +5200,8 @@ std::string NMD::CTC2(uint64 instruction) */ std::string NMD::CVT_D_L(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5223,8 +5222,8 @@ std::string NMD::CVT_D_L(uint64 instruction) */ std::string NMD::CVT_D_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5245,8 +5244,8 @@ std::string NMD::CVT_D_S(uint64 instruction) */ std::string NMD::CVT_D_W(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5267,8 +5266,8 @@ std::string NMD::CVT_D_W(uint64 instruction) */ std::string NMD::CVT_L_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5289,8 +5288,8 @@ std::string NMD::CVT_L_D(uint64 instruction) */ std::string NMD::CVT_L_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5311,8 +5310,8 @@ std::string NMD::CVT_L_S(uint64 instruction) */ std::string NMD::CVT_S_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5333,8 +5332,8 @@ std::string NMD::CVT_S_D(uint64 instruction) */ std::string NMD::CVT_S_L(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5355,8 +5354,8 @@ std::string NMD::CVT_S_L(uint64 instruction) */ std::string NMD::CVT_S_PL(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5377,8 +5376,8 @@ std::string NMD::CVT_S_PL(uint64 instruction) */ std::string NMD::CVT_S_PU(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5399,8 +5398,8 @@ std::string NMD::CVT_S_PU(uint64 instruction) */ std::string NMD::CVT_S_W(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5421,8 +5420,8 @@ std::string NMD::CVT_S_W(uint64 instruction) */ std::string NMD::CVT_W_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5443,8 +5442,8 @@ std::string NMD::CVT_W_D(uint64 instruction) */ std::string NMD::CVT_W_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -5466,7 +5465,7 @@ std::string NMD::CVT_W_S(uint64 instruction) std::string NMD::DADDIU_48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction); + int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -5488,8 +5487,8 @@ std::string NMD::DADDIU_48_(uint64 instruction) std::string NMD::DADDIU_NEG_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -5512,8 +5511,8 @@ std::string NMD::DADDIU_NEG_(uint64 instruction) std::string NMD::DADDIU_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -5536,8 +5535,8 @@ std::string NMD::DADDIU_U12_(uint64 instruction) std::string NMD::DADD(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5560,8 +5559,8 @@ std::string NMD::DADD(uint64 instruction) std::string NMD::DADDU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5628,8 +5627,8 @@ std::string NMD::DCLZ(uint64 instruction) std::string NMD::DDIV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5652,8 +5651,8 @@ std::string NMD::DDIV(uint64 instruction) std::string NMD::DDIVU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5694,9 +5693,9 @@ std::string NMD::DERET(uint64 instruction) std::string NMD::DEXTM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 rs_value = extract_rs_20_19_18_17_16(instruction); uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); - uint64 rs_value = extract_rs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -5720,9 +5719,9 @@ std::string NMD::DEXTM(uint64 instruction) std::string NMD::DEXT(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 rs_value = extract_rs_20_19_18_17_16(instruction); uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); - uint64 rs_value = extract_rs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -5746,9 +5745,9 @@ std::string NMD::DEXT(uint64 instruction) std::string NMD::DEXTU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 rs_value = extract_rs_20_19_18_17_16(instruction); uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); - uint64 rs_value = extract_rs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -5772,9 +5771,9 @@ std::string NMD::DEXTU(uint64 instruction) std::string NMD::DINSM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 rs_value = extract_rs_20_19_18_17_16(instruction); uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); - uint64 rs_value = extract_rs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -5800,9 +5799,9 @@ std::string NMD::DINSM(uint64 instruction) std::string NMD::DINS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 rs_value = extract_rs_20_19_18_17_16(instruction); uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); - uint64 rs_value = extract_rs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -5828,9 +5827,9 @@ std::string NMD::DINS(uint64 instruction) std::string NMD::DINSU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 rs_value = extract_rs_20_19_18_17_16(instruction); uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); - uint64 rs_value = extract_rs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -5876,8 +5875,8 @@ std::string NMD::DI(uint64 instruction) std::string NMD::DIV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5899,9 +5898,9 @@ std::string NMD::DIV(uint64 instruction) */ std::string NMD::DIV_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -5923,9 +5922,9 @@ std::string NMD::DIV_D(uint64 instruction) */ std::string NMD::DIV_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -5948,8 +5947,8 @@ std::string NMD::DIV_S(uint64 instruction) std::string NMD::DIVU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5972,9 +5971,9 @@ std::string NMD::DIVU(uint64 instruction) std::string NMD::DLSA(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); - uint64 u2_value = extract_u2_10_9(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); + uint64 u2_value = extract_u2_10_9(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -5998,7 +5997,7 @@ std::string NMD::DLSA(uint64 instruction) std::string NMD::DLUI_48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - uint64 u_value = extr_uil0il32bs32Fmsb63(instruction); + uint64 u_value = extract_u_31_to_0__s32(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -6044,7 +6043,7 @@ std::string NMD::DMFC0(uint64 instruction) std::string NMD::DMFC1(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string fs = FPR(copy(fs_value)); @@ -6065,8 +6064,8 @@ std::string NMD::DMFC1(uint64 instruction) */ std::string NMD::DMFC2(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -6112,8 +6111,8 @@ std::string NMD::DMFGC0(uint64 instruction) std::string NMD::DMOD(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -6136,8 +6135,8 @@ std::string NMD::DMOD(uint64 instruction) std::string NMD::DMODU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -6184,7 +6183,7 @@ std::string NMD::DMTC0(uint64 instruction) std::string NMD::DMTC1(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string fs = FPR(copy(fs_value)); @@ -6205,8 +6204,8 @@ std::string NMD::DMTC1(uint64 instruction) */ std::string NMD::DMTC2(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -6272,8 +6271,8 @@ std::string NMD::DMT(uint64 instruction) std::string NMD::DMUH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -6296,8 +6295,8 @@ std::string NMD::DMUH(uint64 instruction) std::string NMD::DMUHU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -6320,8 +6319,8 @@ std::string NMD::DMUHU(uint64 instruction) std::string NMD::DMUL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -6344,8 +6343,8 @@ std::string NMD::DMUL(uint64 instruction) std::string NMD::DMULU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -6368,8 +6367,8 @@ std::string NMD::DMULU(uint64 instruction) std::string NMD::DPA_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6392,8 +6391,8 @@ std::string NMD::DPA_W_PH(uint64 instruction) std::string NMD::DPAQ_SA_L_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6416,8 +6415,8 @@ std::string NMD::DPAQ_SA_L_W(uint64 instruction) std::string NMD::DPAQ_S_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6440,8 +6439,8 @@ std::string NMD::DPAQ_S_W_PH(uint64 instruction) std::string NMD::DPAQX_SA_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6464,8 +6463,8 @@ std::string NMD::DPAQX_SA_W_PH(uint64 instruction) std::string NMD::DPAQX_S_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6488,8 +6487,8 @@ std::string NMD::DPAQX_S_W_PH(uint64 instruction) std::string NMD::DPAU_H_QBL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6512,8 +6511,8 @@ std::string NMD::DPAU_H_QBL(uint64 instruction) std::string NMD::DPAU_H_QBR(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6536,8 +6535,8 @@ std::string NMD::DPAU_H_QBR(uint64 instruction) std::string NMD::DPAX_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6560,8 +6559,8 @@ std::string NMD::DPAX_W_PH(uint64 instruction) std::string NMD::DPS_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6584,8 +6583,8 @@ std::string NMD::DPS_W_PH(uint64 instruction) std::string NMD::DPSQ_SA_L_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6608,8 +6607,8 @@ std::string NMD::DPSQ_SA_L_W(uint64 instruction) std::string NMD::DPSQ_S_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6632,8 +6631,8 @@ std::string NMD::DPSQ_S_W_PH(uint64 instruction) std::string NMD::DPSQX_SA_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6656,8 +6655,8 @@ std::string NMD::DPSQX_SA_W_PH(uint64 instruction) std::string NMD::DPSQX_S_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6680,8 +6679,8 @@ std::string NMD::DPSQX_S_W_PH(uint64 instruction) std::string NMD::DPSU_H_QBL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6704,8 +6703,8 @@ std::string NMD::DPSU_H_QBL(uint64 instruction) std::string NMD::DPSU_H_QBR(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6728,8 +6727,8 @@ std::string NMD::DPSU_H_QBR(uint64 instruction) std::string NMD::DPSX_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -6752,8 +6751,8 @@ std::string NMD::DPSX_W_PH(uint64 instruction) std::string NMD::DROTR(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -6776,8 +6775,8 @@ std::string NMD::DROTR(uint64 instruction) std::string NMD::DROTR32(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -6800,8 +6799,8 @@ std::string NMD::DROTR32(uint64 instruction) std::string NMD::DROTRV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -6824,9 +6823,9 @@ std::string NMD::DROTRV(uint64 instruction) std::string NMD::DROTX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_5_4_3_2_1_0(instruction); - uint64 shiftx_value = extract_shiftx_11_10_9_8_7_6(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shiftx_value = extract_shiftx_11_10_9_8_7_6(instruction); + uint64 shift_value = extract_shift_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -6850,8 +6849,8 @@ std::string NMD::DROTX(uint64 instruction) std::string NMD::DSLL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -6874,8 +6873,8 @@ std::string NMD::DSLL(uint64 instruction) std::string NMD::DSLL32(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -6898,8 +6897,8 @@ std::string NMD::DSLL32(uint64 instruction) std::string NMD::DSLLV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -6922,8 +6921,8 @@ std::string NMD::DSLLV(uint64 instruction) std::string NMD::DSRA(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -6946,8 +6945,8 @@ std::string NMD::DSRA(uint64 instruction) std::string NMD::DSRA32(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -6970,8 +6969,8 @@ std::string NMD::DSRA32(uint64 instruction) std::string NMD::DSRAV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -6994,8 +6993,8 @@ std::string NMD::DSRAV(uint64 instruction) std::string NMD::DSRL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -7018,8 +7017,8 @@ std::string NMD::DSRL(uint64 instruction) std::string NMD::DSRL32(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -7042,8 +7041,8 @@ std::string NMD::DSRL32(uint64 instruction) std::string NMD::DSRLV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -7066,8 +7065,8 @@ std::string NMD::DSRLV(uint64 instruction) std::string NMD::DSUB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -7090,8 +7089,8 @@ std::string NMD::DSUB(uint64 instruction) std::string NMD::DSUBU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -7288,9 +7287,9 @@ std::string NMD::EVPE(uint64 instruction) std::string NMD::EXT(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 rs_value = extract_rs_20_19_18_17_16(instruction); uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); - uint64 rs_value = extract_rs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -7314,9 +7313,9 @@ std::string NMD::EXT(uint64 instruction) std::string NMD::EXTD(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_10_9_8_7_6(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); + uint64 shift_value = extract_shift_10_9_8_7_6(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -7340,9 +7339,9 @@ std::string NMD::EXTD(uint64 instruction) std::string NMD::EXTD32(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_10_9_8_7_6(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); + uint64 shift_value = extract_shift_10_9_8_7_6(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -7366,8 +7365,8 @@ std::string NMD::EXTD32(uint64 instruction) std::string NMD::EXTPDP(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 size_value = extract_size_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string ac = AC(copy(ac_value)); @@ -7390,8 +7389,8 @@ std::string NMD::EXTPDP(uint64 instruction) std::string NMD::EXTPDPV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string ac = AC(copy(ac_value)); @@ -7414,8 +7413,8 @@ std::string NMD::EXTPDPV(uint64 instruction) std::string NMD::EXTP(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 size_value = extract_size_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string ac = AC(copy(ac_value)); @@ -7438,8 +7437,8 @@ std::string NMD::EXTP(uint64 instruction) std::string NMD::EXTPV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string ac = AC(copy(ac_value)); @@ -7558,8 +7557,8 @@ std::string NMD::EXTR_W(uint64 instruction) std::string NMD::EXTRV_RS_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string ac = AC(copy(ac_value)); @@ -7582,8 +7581,8 @@ std::string NMD::EXTRV_RS_W(uint64 instruction) std::string NMD::EXTRV_R_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string ac = AC(copy(ac_value)); @@ -7606,8 +7605,8 @@ std::string NMD::EXTRV_R_W(uint64 instruction) std::string NMD::EXTRV_S_H(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string ac = AC(copy(ac_value)); @@ -7630,8 +7629,8 @@ std::string NMD::EXTRV_S_H(uint64 instruction) std::string NMD::EXTRV_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string ac = AC(copy(ac_value)); @@ -7655,9 +7654,9 @@ std::string NMD::EXTRV_W(uint64 instruction) std::string NMD::EXTW(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_10_9_8_7_6(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); + uint64 shift_value = extract_shift_10_9_8_7_6(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -7680,8 +7679,8 @@ std::string NMD::EXTW(uint64 instruction) */ std::string NMD::FLOOR_L_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -7702,8 +7701,8 @@ std::string NMD::FLOOR_L_D(uint64 instruction) */ std::string NMD::FLOOR_L_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -7724,8 +7723,8 @@ std::string NMD::FLOOR_L_S(uint64 instruction) */ std::string NMD::FLOOR_W_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -7746,8 +7745,8 @@ std::string NMD::FLOOR_W_D(uint64 instruction) */ std::string NMD::FLOOR_W_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -7769,8 +7768,8 @@ std::string NMD::FLOOR_W_S(uint64 instruction) std::string NMD::FORK(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -7833,9 +7832,9 @@ std::string NMD::HYPCALL_16_(uint64 instruction) std::string NMD::INS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 rs_value = extract_rs_20_19_18_17_16(instruction); uint64 msbd_value = extract_msbt_10_9_8_7_6(instruction); uint64 lsb_value = extract_lsb_4_3_2_1_0(instruction); - uint64 rs_value = extract_rs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -7984,13 +7983,13 @@ std::string NMD::JRC(uint64 instruction) */ std::string NMD::LB_16_(uint64 instruction) { - uint64 u_value = extract_u_1_0(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_1_0(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("LB %s, %s(%s)", rt3, u, rs3); } @@ -8031,8 +8030,8 @@ std::string NMD::LB_GP_(uint64 instruction) std::string NMD::LB_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8055,8 +8054,8 @@ std::string NMD::LB_S9_(uint64 instruction) std::string NMD::LB_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8079,8 +8078,8 @@ std::string NMD::LB_U12_(uint64 instruction) std::string NMD::LBE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8102,13 +8101,13 @@ std::string NMD::LBE(uint64 instruction) */ std::string NMD::LBU_16_(uint64 instruction) { - uint64 u_value = extract_u_1_0(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_1_0(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("LBU %s, %s(%s)", rt3, u, rs3); } @@ -8149,8 +8148,8 @@ std::string NMD::LBU_GP_(uint64 instruction) std::string NMD::LBU_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8173,8 +8172,8 @@ std::string NMD::LBU_S9_(uint64 instruction) std::string NMD::LBU_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8197,8 +8196,8 @@ std::string NMD::LBU_U12_(uint64 instruction) std::string NMD::LBUE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8221,8 +8220,8 @@ std::string NMD::LBUE(uint64 instruction) std::string NMD::LBUX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -8245,8 +8244,8 @@ std::string NMD::LBUX(uint64 instruction) std::string NMD::LBX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -8269,7 +8268,7 @@ std::string NMD::LBX(uint64 instruction) std::string NMD::LD_GP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil3il3bs18Fmsb20(instruction); + uint64 u_value = extract_u_20_to_3__s3(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8291,8 +8290,8 @@ std::string NMD::LD_GP_(uint64 instruction) std::string NMD::LD_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8315,8 +8314,8 @@ std::string NMD::LD_S9_(uint64 instruction) std::string NMD::LD_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8338,8 +8337,8 @@ std::string NMD::LD_U12_(uint64 instruction) */ std::string NMD::LDC1_GP_(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 u_value = extr_uil2il2bs16Fmsb17(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 u_value = extract_u_17_to_2__s2(instruction); std::string ft = FPR(copy(ft_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8360,9 +8359,9 @@ std::string NMD::LDC1_GP_(uint64 instruction) */ std::string NMD::LDC1_S9_(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string ft = FPR(copy(ft_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8384,9 +8383,9 @@ std::string NMD::LDC1_S9_(uint64 instruction) */ std::string NMD::LDC1_U12_(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string ft = FPR(copy(ft_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8409,8 +8408,8 @@ std::string NMD::LDC1_U12_(uint64 instruction) std::string NMD::LDC1XS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ft_value = extract_ft_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string rs = GPR(copy(rs_value)); @@ -8433,8 +8432,8 @@ std::string NMD::LDC1XS(uint64 instruction) std::string NMD::LDC1X(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ft_value = extract_ft_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string rs = GPR(copy(rs_value)); @@ -8456,9 +8455,9 @@ std::string NMD::LDC1X(uint64 instruction) */ std::string NMD::LDC2(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 ct_value = extract_ct_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string ct = CPR(copy(ct_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8481,9 +8480,9 @@ std::string NMD::LDC2(uint64 instruction) std::string NMD::LDM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 count3_value = extract_count3_14_13_12(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); + uint64 count3_value = extract_count3_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8507,7 +8506,7 @@ std::string NMD::LDM(uint64 instruction) std::string NMD::LDPC_48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction); + int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); std::string rt = GPR(copy(rt_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 6); @@ -8529,8 +8528,8 @@ std::string NMD::LDPC_48_(uint64 instruction) std::string NMD::LDX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -8553,8 +8552,8 @@ std::string NMD::LDX(uint64 instruction) std::string NMD::LDXS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -8576,13 +8575,13 @@ std::string NMD::LDXS(uint64 instruction) */ std::string NMD::LH_16_(uint64 instruction) { - uint64 u_value = extr_uil1il1bs2Fmsb2(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_2_1__s1(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("LH %s, %s(%s)", rt3, u, rs3); } @@ -8601,7 +8600,7 @@ std::string NMD::LH_16_(uint64 instruction) std::string NMD::LH_GP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil1il1bs17Fmsb17(instruction); + uint64 u_value = extract_u_17_to_1__s1(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8623,8 +8622,8 @@ std::string NMD::LH_GP_(uint64 instruction) std::string NMD::LH_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8647,8 +8646,8 @@ std::string NMD::LH_S9_(uint64 instruction) std::string NMD::LH_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8671,8 +8670,8 @@ std::string NMD::LH_U12_(uint64 instruction) std::string NMD::LHE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8694,13 +8693,13 @@ std::string NMD::LHE(uint64 instruction) */ std::string NMD::LHU_16_(uint64 instruction) { - uint64 u_value = extr_uil1il1bs2Fmsb2(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_2_1__s1(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("LHU %s, %s(%s)", rt3, u, rs3); } @@ -8719,7 +8718,7 @@ std::string NMD::LHU_16_(uint64 instruction) std::string NMD::LHU_GP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil1il1bs17Fmsb17(instruction); + uint64 u_value = extract_u_17_to_1__s1(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8741,8 +8740,8 @@ std::string NMD::LHU_GP_(uint64 instruction) std::string NMD::LHU_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8765,8 +8764,8 @@ std::string NMD::LHU_S9_(uint64 instruction) std::string NMD::LHU_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -8789,8 +8788,8 @@ std::string NMD::LHU_U12_(uint64 instruction) std::string NMD::LHUE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8813,8 +8812,8 @@ std::string NMD::LHUE(uint64 instruction) std::string NMD::LHUX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -8837,8 +8836,8 @@ std::string NMD::LHUX(uint64 instruction) std::string NMD::LHUXS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -8861,8 +8860,8 @@ std::string NMD::LHUXS(uint64 instruction) std::string NMD::LHXS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -8885,8 +8884,8 @@ std::string NMD::LHXS(uint64 instruction) std::string NMD::LHX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -8908,10 +8907,10 @@ std::string NMD::LHX(uint64 instruction) */ std::string NMD::LI_16_(uint64 instruction) { - uint64 eu_value = extract_eu_6_5_4_3_2_1_0(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); + uint64 eu_value = extract_eu_6_5_4_3_2_1_0(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string eu = IMMEDIATE(encode_eu_from_s_li16(eu_value)); return img::format("LI %s, %s", rt3, eu); @@ -8931,7 +8930,7 @@ std::string NMD::LI_16_(uint64 instruction) std::string NMD::LI_48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction); + int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8953,8 +8952,8 @@ std::string NMD::LI_48_(uint64 instruction) std::string NMD::LL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -8977,8 +8976,8 @@ std::string NMD::LL(uint64 instruction) std::string NMD::LLD(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil3il3bs5_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -9001,8 +9000,8 @@ std::string NMD::LLD(uint64 instruction) std::string NMD::LLDP(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ru_value = extract_ru_7_6_5_4_3(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ru_value = extract_ru_7_6_5_4_3(instruction); std::string rt = GPR(copy(rt_value)); std::string ru = GPR(copy(ru_value)); @@ -9025,8 +9024,8 @@ std::string NMD::LLDP(uint64 instruction) std::string NMD::LLE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -9049,8 +9048,8 @@ std::string NMD::LLE(uint64 instruction) std::string NMD::LLWP(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ru_value = extract_ru_7_6_5_4_3(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ru_value = extract_ru_7_6_5_4_3(instruction); std::string rt = GPR(copy(rt_value)); std::string ru = GPR(copy(ru_value)); @@ -9073,8 +9072,8 @@ std::string NMD::LLWP(uint64 instruction) std::string NMD::LLWPE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ru_value = extract_ru_7_6_5_4_3(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ru_value = extract_ru_7_6_5_4_3(instruction); std::string rt = GPR(copy(rt_value)); std::string ru = GPR(copy(ru_value)); @@ -9097,9 +9096,9 @@ std::string NMD::LLWPE(uint64 instruction) std::string NMD::LSA(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); - uint64 u2_value = extract_u2_10_9(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); + uint64 u2_value = extract_u2_10_9(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -9123,7 +9122,7 @@ std::string NMD::LSA(uint64 instruction) std::string NMD::LUI(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(instruction); + int64 s_value = extract_s__se31_0_11_to_2_20_to_12_s12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -9144,13 +9143,13 @@ std::string NMD::LUI(uint64 instruction) */ std::string NMD::LW_16_(uint64 instruction) { - uint64 u_value = extr_uil0il2bs4Fmsb5(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_3_2_1_0__s2(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("LW %s, %s(%s)", rt3, u, rs3); } @@ -9168,13 +9167,13 @@ std::string NMD::LW_16_(uint64 instruction) */ std::string NMD::LW_4X4_(uint64 instruction) { - uint64 rs4_value = extract_rs4_4_2_1_0(instruction); uint64 rt4_value = extract_rt4_9_7_6_5(instruction); - uint64 u_value = extr_uil3il3bs1_il8il2bs1Fmsb3(instruction); + uint64 rs4_value = extract_rs4_4_2_1_0(instruction); + uint64 u_value = extract_u_3_8__s2(instruction); - std::string rt4 = GPR(encode_gpr4(rt4_value)); + std::string rt4 = GPR(decode_gpr_gpr4(rt4_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs4 = GPR(encode_gpr4(rs4_value)); + std::string rs4 = GPR(decode_gpr_gpr4(rs4_value)); return img::format("LW %s, %s(%s)", rt4, u, rs4); } @@ -9193,7 +9192,7 @@ std::string NMD::LW_4X4_(uint64 instruction) std::string NMD::LW_GP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil2il2bs19Fmsb20(instruction); + uint64 u_value = extract_u_20_to_2__s2(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -9214,10 +9213,10 @@ std::string NMD::LW_GP_(uint64 instruction) */ std::string NMD::LW_GP16_(uint64 instruction) { - uint64 u_value = extr_uil0il2bs7Fmsb8(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); + uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); std::string u = IMMEDIATE(copy(u_value)); return img::format("LW %s, %s($%d)", rt3, u, 28); @@ -9237,8 +9236,8 @@ std::string NMD::LW_GP16_(uint64 instruction) std::string NMD::LW_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -9261,7 +9260,7 @@ std::string NMD::LW_S9_(uint64 instruction) std::string NMD::LW_SP_(uint64 instruction) { uint64 rt_value = extract_rt_9_8_7_6_5(instruction); - uint64 u_value = extr_uil0il2bs5Fmsb6(instruction); + uint64 u_value = extract_u_4_3_2_1_0__s2(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -9283,8 +9282,8 @@ std::string NMD::LW_SP_(uint64 instruction) std::string NMD::LW_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -9306,8 +9305,8 @@ std::string NMD::LW_U12_(uint64 instruction) */ std::string NMD::LWC1_GP_(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 u_value = extr_uil2il2bs16Fmsb17(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 u_value = extract_u_17_to_2__s2(instruction); std::string ft = FPR(copy(ft_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -9328,9 +9327,9 @@ std::string NMD::LWC1_GP_(uint64 instruction) */ std::string NMD::LWC1_S9_(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string ft = FPR(copy(ft_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -9352,9 +9351,9 @@ std::string NMD::LWC1_S9_(uint64 instruction) */ std::string NMD::LWC1_U12_(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string ft = FPR(copy(ft_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -9377,8 +9376,8 @@ std::string NMD::LWC1_U12_(uint64 instruction) std::string NMD::LWC1X(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ft_value = extract_ft_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string rs = GPR(copy(rs_value)); @@ -9401,8 +9400,8 @@ std::string NMD::LWC1X(uint64 instruction) std::string NMD::LWC1XS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ft_value = extract_ft_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string rs = GPR(copy(rs_value)); @@ -9424,9 +9423,9 @@ std::string NMD::LWC1XS(uint64 instruction) */ std::string NMD::LWC2(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 ct_value = extract_ct_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string ct = CPR(copy(ct_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -9449,8 +9448,8 @@ std::string NMD::LWC2(uint64 instruction) std::string NMD::LWE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -9473,9 +9472,9 @@ std::string NMD::LWE(uint64 instruction) std::string NMD::LWM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 count3_value = extract_count3_14_13_12(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); + uint64 count3_value = extract_count3_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -9499,7 +9498,7 @@ std::string NMD::LWM(uint64 instruction) std::string NMD::LWPC_48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction); + int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); std::string rt = GPR(copy(rt_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 6); @@ -9521,7 +9520,7 @@ std::string NMD::LWPC_48_(uint64 instruction) std::string NMD::LWU_GP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil2il2bs16Fmsb17(instruction); + uint64 u_value = extract_u_17_to_2__s2(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -9543,8 +9542,8 @@ std::string NMD::LWU_GP_(uint64 instruction) std::string NMD::LWU_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -9567,8 +9566,8 @@ std::string NMD::LWU_S9_(uint64 instruction) std::string NMD::LWU_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -9591,8 +9590,8 @@ std::string NMD::LWU_U12_(uint64 instruction) std::string NMD::LWUX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -9615,8 +9614,8 @@ std::string NMD::LWUX(uint64 instruction) std::string NMD::LWUXS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -9639,8 +9638,8 @@ std::string NMD::LWUXS(uint64 instruction) std::string NMD::LWX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -9662,13 +9661,13 @@ std::string NMD::LWX(uint64 instruction) */ std::string NMD::LWXS_16_(uint64 instruction) { - uint64 rd3_value = extract_rd3_3_2_1(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 rd3_value = extract_rd3_3_2_1(instruction); - std::string rd3 = GPR(encode_gpr3(rd3_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); - std::string rt3 = IMMEDIATE(encode_gpr3(rt3_value)); + std::string rd3 = GPR(decode_gpr_gpr3(rd3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); + std::string rt3 = IMMEDIATE(decode_gpr_gpr3(rt3_value)); return img::format("LWXS %s, %s(%s)", rd3, rs3, rt3); } @@ -9687,8 +9686,8 @@ std::string NMD::LWXS_16_(uint64 instruction) std::string NMD::LWXS_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -9711,8 +9710,8 @@ std::string NMD::LWXS_32_(uint64 instruction) std::string NMD::MADD_DSP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -9734,9 +9733,9 @@ std::string NMD::MADD_DSP_(uint64 instruction) */ std::string NMD::MADDF_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -9758,9 +9757,9 @@ std::string NMD::MADDF_D(uint64 instruction) */ std::string NMD::MADDF_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -9783,8 +9782,8 @@ std::string NMD::MADDF_S(uint64 instruction) std::string NMD::MADDU_DSP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -9807,8 +9806,8 @@ std::string NMD::MADDU_DSP_(uint64 instruction) std::string NMD::MAQ_S_W_PHL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -9831,8 +9830,8 @@ std::string NMD::MAQ_S_W_PHL(uint64 instruction) std::string NMD::MAQ_S_W_PHR(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -9855,8 +9854,8 @@ std::string NMD::MAQ_S_W_PHR(uint64 instruction) std::string NMD::MAQ_SA_W_PHL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -9879,8 +9878,8 @@ std::string NMD::MAQ_SA_W_PHL(uint64 instruction) std::string NMD::MAQ_SA_W_PHR(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -9902,9 +9901,9 @@ std::string NMD::MAQ_SA_W_PHR(uint64 instruction) */ std::string NMD::MAX_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -9926,9 +9925,9 @@ std::string NMD::MAX_D(uint64 instruction) */ std::string NMD::MAX_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -9950,9 +9949,9 @@ std::string NMD::MAX_S(uint64 instruction) */ std::string NMD::MAXA_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -9974,9 +9973,9 @@ std::string NMD::MAXA_D(uint64 instruction) */ std::string NMD::MAXA_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -10023,7 +10022,7 @@ std::string NMD::MFC0(uint64 instruction) std::string NMD::MFC1(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string fs = FPR(copy(fs_value)); @@ -10044,8 +10043,8 @@ std::string NMD::MFC1(uint64 instruction) */ std::string NMD::MFC2(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -10115,7 +10114,7 @@ std::string NMD::MFHC0(uint64 instruction) std::string NMD::MFHC1(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string fs = FPR(copy(fs_value)); @@ -10136,8 +10135,8 @@ std::string NMD::MFHC1(uint64 instruction) */ std::string NMD::MFHC2(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -10278,9 +10277,9 @@ std::string NMD::MFTR(uint64 instruction) */ std::string NMD::MIN_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -10302,9 +10301,9 @@ std::string NMD::MIN_D(uint64 instruction) */ std::string NMD::MIN_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -10326,9 +10325,9 @@ std::string NMD::MIN_S(uint64 instruction) */ std::string NMD::MINA_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -10350,9 +10349,9 @@ std::string NMD::MINA_D(uint64 instruction) */ std::string NMD::MINA_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -10375,8 +10374,8 @@ std::string NMD::MINA_S(uint64 instruction) std::string NMD::MOD(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -10399,8 +10398,8 @@ std::string NMD::MOD(uint64 instruction) std::string NMD::MODSUB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -10423,8 +10422,8 @@ std::string NMD::MODSUB(uint64 instruction) std::string NMD::MODU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -10446,8 +10445,8 @@ std::string NMD::MODU(uint64 instruction) */ std::string NMD::MOV_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -10468,8 +10467,8 @@ std::string NMD::MOV_D(uint64 instruction) */ std::string NMD::MOV_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -10490,12 +10489,12 @@ std::string NMD::MOV_S(uint64 instruction) */ std::string NMD::MOVE_BALC(uint64 instruction) { - uint64 rd1_value = extract_rdl_25_24(instruction); - int64 s_value = extr_sil0il21bs1_il1il1bs20Tmsb21(instruction); uint64 rtz4_value = extract_rtz4_27_26_25_23_22_21(instruction); + uint64 rd1_value = extract_rdl_25_24(instruction); + int64 s_value = extract_s__se21_0_20_to_1_s1(instruction); - std::string rd1 = GPR(encode_rd1_from_rd(rd1_value)); - std::string rtz4 = GPR(encode_gpr4_zero(rtz4_value)); + std::string rd1 = GPR(decode_gpr_gpr1(rd1_value)); + std::string rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 4); return img::format("MOVE.BALC %s, %s, %s", rd1, rtz4, s); @@ -10514,15 +10513,15 @@ std::string NMD::MOVE_BALC(uint64 instruction) */ std::string NMD::MOVEP(uint64 instruction) { - uint64 rsz4_value = extract_rsz4_4_2_1_0(instruction); uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction); uint64 rd2_value = extract_rd2_3_8(instruction); + uint64 rsz4_value = extract_rsz4_4_2_1_0(instruction); - std::string rd2 = GPR(encode_rd2_reg1(rd2_value)); - std::string re2 = GPR(encode_rd2_reg2(rd2_value)); + std::string rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value)); + std::string re2 = GPR(decode_gpr_gpr2_reg2(rd2_value)); /* !!!!!!!!!! - no conversion function */ - std::string rsz4 = GPR(encode_gpr4_zero(rsz4_value)); - std::string rtz4 = GPR(encode_gpr4_zero(rtz4_value)); + std::string rsz4 = GPR(decode_gpr_gpr4_zero(rsz4_value)); + std::string rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value)); return img::format("MOVEP %s, %s, %s, %s", rd2, re2, rsz4, rtz4); /* hand edited */ @@ -10541,14 +10540,14 @@ std::string NMD::MOVEP(uint64 instruction) */ std::string NMD::MOVEP_REV_(uint64 instruction) { - uint64 rs4_value = extract_rs4_4_2_1_0(instruction); uint64 rt4_value = extract_rt4_9_7_6_5(instruction); uint64 rd2_value = extract_rd2_3_8(instruction); + uint64 rs4_value = extract_rs4_4_2_1_0(instruction); - std::string rs4 = GPR(encode_gpr4(rs4_value)); - std::string rt4 = GPR(encode_gpr4(rt4_value)); - std::string rd2 = GPR(encode_rd2_reg1(rd2_value)); - std::string rs2 = GPR(encode_rd2_reg2(rd2_value)); + std::string rs4 = GPR(decode_gpr_gpr4(rs4_value)); + std::string rt4 = GPR(decode_gpr_gpr4(rt4_value)); + std::string rd2 = GPR(decode_gpr_gpr2_reg1(rd2_value)); + std::string rs2 = GPR(decode_gpr_gpr2_reg2(rd2_value)); /* !!!!!!!!!! - no conversion function */ return img::format("MOVEP %s, %s, %s, %s", rs4, rt4, rd2, rs2); @@ -10591,8 +10590,8 @@ std::string NMD::MOVE(uint64 instruction) std::string NMD::MOVN(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -10615,8 +10614,8 @@ std::string NMD::MOVN(uint64 instruction) std::string NMD::MOVZ(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -10639,8 +10638,8 @@ std::string NMD::MOVZ(uint64 instruction) std::string NMD::MSUB_DSP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -10662,9 +10661,9 @@ std::string NMD::MSUB_DSP_(uint64 instruction) */ std::string NMD::MSUBF_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -10686,9 +10685,9 @@ std::string NMD::MSUBF_D(uint64 instruction) */ std::string NMD::MSUBF_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -10711,8 +10710,8 @@ std::string NMD::MSUBF_S(uint64 instruction) std::string NMD::MSUBU_DSP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -10759,7 +10758,7 @@ std::string NMD::MTC0(uint64 instruction) std::string NMD::MTC1(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string fs = FPR(copy(fs_value)); @@ -10780,8 +10779,8 @@ std::string NMD::MTC1(uint64 instruction) */ std::string NMD::MTC2(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -10851,7 +10850,7 @@ std::string NMD::MTHC0(uint64 instruction) std::string NMD::MTHC1(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string fs = FPR(copy(fs_value)); @@ -10872,8 +10871,8 @@ std::string NMD::MTHC1(uint64 instruction) */ std::string NMD::MTHC2(uint64 instruction) { - uint64 cs_value = extract_cs_20_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); + uint64 cs_value = extract_cs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); std::string cs = CPR(copy(cs_value)); @@ -10918,8 +10917,8 @@ std::string NMD::MTHGC0(uint64 instruction) */ std::string NMD::MTHI_DSP_(uint64 instruction) { - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rs = GPR(copy(rs_value)); std::string ac = AC(copy(ac_value)); @@ -10940,8 +10939,8 @@ std::string NMD::MTHI_DSP_(uint64 instruction) */ std::string NMD::MTHLIP(uint64 instruction) { - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rs = GPR(copy(rs_value)); std::string ac = AC(copy(ac_value)); @@ -10988,8 +10987,8 @@ std::string NMD::MTHTR(uint64 instruction) */ std::string NMD::MTLO_DSP_(uint64 instruction) { - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string rs = GPR(copy(rs_value)); std::string ac = AC(copy(ac_value)); @@ -11037,8 +11036,8 @@ std::string NMD::MTTR(uint64 instruction) std::string NMD::MUH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11061,8 +11060,8 @@ std::string NMD::MUH(uint64 instruction) std::string NMD::MUHU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11085,8 +11084,8 @@ std::string NMD::MUHU(uint64 instruction) std::string NMD::MUL_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11108,11 +11107,11 @@ std::string NMD::MUL_32_(uint64 instruction) */ std::string NMD::MUL_4X4_(uint64 instruction) { - uint64 rs4_value = extract_rs4_4_2_1_0(instruction); uint64 rt4_value = extract_rt4_9_7_6_5(instruction); + uint64 rs4_value = extract_rs4_4_2_1_0(instruction); - std::string rs4 = GPR(encode_gpr4(rs4_value)); - std::string rt4 = GPR(encode_gpr4(rt4_value)); + std::string rs4 = GPR(decode_gpr_gpr4(rs4_value)); + std::string rt4 = GPR(decode_gpr_gpr4(rt4_value)); return img::format("MUL %s, %s", rs4, rt4); } @@ -11130,9 +11129,9 @@ std::string NMD::MUL_4X4_(uint64 instruction) */ std::string NMD::MUL_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -11155,8 +11154,8 @@ std::string NMD::MUL_D(uint64 instruction) std::string NMD::MUL_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11179,8 +11178,8 @@ std::string NMD::MUL_PH(uint64 instruction) std::string NMD::MUL_S_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11202,9 +11201,9 @@ std::string NMD::MUL_S_PH(uint64 instruction) */ std::string NMD::MUL_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -11227,8 +11226,8 @@ std::string NMD::MUL_S(uint64 instruction) std::string NMD::MULEQ_S_W_PHL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11251,8 +11250,8 @@ std::string NMD::MULEQ_S_W_PHL(uint64 instruction) std::string NMD::MULEQ_S_W_PHR(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11275,8 +11274,8 @@ std::string NMD::MULEQ_S_W_PHR(uint64 instruction) std::string NMD::MULEU_S_PH_QBL(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11299,8 +11298,8 @@ std::string NMD::MULEU_S_PH_QBL(uint64 instruction) std::string NMD::MULEU_S_PH_QBR(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11323,8 +11322,8 @@ std::string NMD::MULEU_S_PH_QBR(uint64 instruction) std::string NMD::MULQ_RS_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11347,8 +11346,8 @@ std::string NMD::MULQ_RS_PH(uint64 instruction) std::string NMD::MULQ_RS_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11371,8 +11370,8 @@ std::string NMD::MULQ_RS_W(uint64 instruction) std::string NMD::MULQ_S_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11395,8 +11394,8 @@ std::string NMD::MULQ_S_PH(uint64 instruction) std::string NMD::MULQ_S_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11419,8 +11418,8 @@ std::string NMD::MULQ_S_W(uint64 instruction) std::string NMD::MULSA_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -11443,8 +11442,8 @@ std::string NMD::MULSA_W_PH(uint64 instruction) std::string NMD::MULSAQ_S_W_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -11467,8 +11466,8 @@ std::string NMD::MULSAQ_S_W_PH(uint64 instruction) std::string NMD::MULT_DSP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -11491,8 +11490,8 @@ std::string NMD::MULT_DSP_(uint64 instruction) std::string NMD::MULTU_DSP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ac_value = extract_ac_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ac_value = extract_ac_13_12(instruction); std::string ac = AC(copy(ac_value)); std::string rs = GPR(copy(rs_value)); @@ -11515,8 +11514,8 @@ std::string NMD::MULTU_DSP_(uint64 instruction) std::string NMD::MULU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11538,8 +11537,8 @@ std::string NMD::MULU(uint64 instruction) */ std::string NMD::NEG_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -11560,8 +11559,8 @@ std::string NMD::NEG_D(uint64 instruction) */ std::string NMD::NEG_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -11619,8 +11618,8 @@ std::string NMD::NOP_32_(uint64 instruction) std::string NMD::NOR(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11645,8 +11644,8 @@ std::string NMD::NOT_16_(uint64 instruction) uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("NOT %s, %s", rt3, rs3); } @@ -11667,8 +11666,8 @@ std::string NMD::OR_16_(uint64 instruction) uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); - std::string rs3 = GPR(encode_gpr3(rs3_value)); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); return img::format("OR %s, %s", rs3, rt3); } @@ -11687,8 +11686,8 @@ std::string NMD::OR_16_(uint64 instruction) std::string NMD::OR_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11711,8 +11710,8 @@ std::string NMD::OR_32_(uint64 instruction) std::string NMD::ORI(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -11735,8 +11734,8 @@ std::string NMD::ORI(uint64 instruction) std::string NMD::PACKRL_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11777,8 +11776,8 @@ std::string NMD::PAUSE(uint64 instruction) std::string NMD::PICK_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -11801,8 +11800,8 @@ std::string NMD::PICK_PH(uint64 instruction) std::string NMD::PICK_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -12045,8 +12044,8 @@ std::string NMD::PRECEU_PH_QBR(uint64 instruction) std::string NMD::PRECR_QB_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -12069,8 +12068,8 @@ std::string NMD::PRECR_QB_PH(uint64 instruction) std::string NMD::PRECR_SRA_PH_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13_12_11(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -12093,8 +12092,8 @@ std::string NMD::PRECR_SRA_PH_W(uint64 instruction) std::string NMD::PRECR_SRA_R_PH_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13_12_11(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -12117,8 +12116,8 @@ std::string NMD::PRECR_SRA_R_PH_W(uint64 instruction) std::string NMD::PRECRQ_PH_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -12141,8 +12140,8 @@ std::string NMD::PRECRQ_PH_W(uint64 instruction) std::string NMD::PRECRQ_QB_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -12165,8 +12164,8 @@ std::string NMD::PRECRQ_QB_PH(uint64 instruction) std::string NMD::PRECRQ_RS_PH_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -12189,8 +12188,8 @@ std::string NMD::PRECRQ_RS_PH_W(uint64 instruction) std::string NMD::PRECRQU_S_QB_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -12212,9 +12211,9 @@ std::string NMD::PRECRQU_S_QB_PH(uint64 instruction) */ std::string NMD::PREF_S9_(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 hint_value = extract_hint_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string hint = IMMEDIATE(copy(hint_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -12237,8 +12236,8 @@ std::string NMD::PREF_S9_(uint64 instruction) std::string NMD::PREF_U12_(uint64 instruction) { uint64 hint_value = extract_hint_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string hint = IMMEDIATE(copy(hint_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -12260,9 +12259,9 @@ std::string NMD::PREF_U12_(uint64 instruction) */ std::string NMD::PREFE(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 hint_value = extract_hint_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string hint = IMMEDIATE(copy(hint_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -12285,8 +12284,8 @@ std::string NMD::PREFE(uint64 instruction) std::string NMD::PREPEND(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13_12_11(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -12398,8 +12397,8 @@ std::string NMD::RDPGPR(uint64 instruction) */ std::string NMD::RECIP_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12420,8 +12419,8 @@ std::string NMD::RECIP_D(uint64 instruction) */ std::string NMD::RECIP_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12443,7 +12442,7 @@ std::string NMD::RECIP_S(uint64 instruction) std::string NMD::REPL_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil11il0bs10Tmsb9(instruction); + int64 s_value = extract_s__se9_20_19_18_17_16_15_14_13_12_11(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -12530,9 +12529,9 @@ std::string NMD::REPLV_QB(uint64 instruction) */ std::string NMD::RESTORE_32_(uint64 instruction) { - uint64 count_value = extract_count_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil3il3bs9Fmsb11(instruction); + uint64 count_value = extract_count_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); uint64 gp_value = extract_gp_2(instruction); std::string u = IMMEDIATE(copy(u_value)); @@ -12553,9 +12552,9 @@ std::string NMD::RESTORE_32_(uint64 instruction) */ std::string NMD::RESTORE_JRC_16_(uint64 instruction) { - uint64 count_value = extract_count_3_2_1_0(instruction); uint64 rt1_value = extract_rtl_11(instruction); - uint64 u_value = extr_uil4il4bs4Fmsb7(instruction); + uint64 u_value = extract_u_7_6_5_4__s4(instruction); + uint64 count_value = extract_count_3_2_1_0(instruction); std::string u = IMMEDIATE(copy(u_value)); return img::format("RESTORE.JRC %s%s", u, @@ -12575,9 +12574,9 @@ std::string NMD::RESTORE_JRC_16_(uint64 instruction) */ std::string NMD::RESTORE_JRC_32_(uint64 instruction) { - uint64 count_value = extract_count_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil3il3bs9Fmsb11(instruction); + uint64 count_value = extract_count_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); uint64 gp_value = extract_gp_2(instruction); std::string u = IMMEDIATE(copy(u_value)); @@ -12599,7 +12598,7 @@ std::string NMD::RESTORE_JRC_32_(uint64 instruction) std::string NMD::RESTOREF(uint64 instruction) { uint64 count_value = extract_count_19_18_17_16(instruction); - uint64 u_value = extr_uil3il3bs9Fmsb11(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); std::string u = IMMEDIATE(copy(u_value)); std::string count = IMMEDIATE(copy(count_value)); @@ -12620,8 +12619,8 @@ std::string NMD::RESTOREF(uint64 instruction) */ std::string NMD::RINT_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12642,8 +12641,8 @@ std::string NMD::RINT_D(uint64 instruction) */ std::string NMD::RINT_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12665,8 +12664,8 @@ std::string NMD::RINT_S(uint64 instruction) std::string NMD::ROTR(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -12689,8 +12688,8 @@ std::string NMD::ROTR(uint64 instruction) std::string NMD::ROTRV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -12713,10 +12712,10 @@ std::string NMD::ROTRV(uint64 instruction) std::string NMD::ROTX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); - uint64 shiftx_value = extr_shiftxil7il1bs4Fmsb4(instruction); - uint64 stripe_value = extract_stripe_6(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shiftx_value = extract_shiftx_10_9_8_7__s1(instruction); + uint64 stripe_value = extract_stripe_6(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -12741,8 +12740,8 @@ std::string NMD::ROTX(uint64 instruction) */ std::string NMD::ROUND_L_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12763,8 +12762,8 @@ std::string NMD::ROUND_L_D(uint64 instruction) */ std::string NMD::ROUND_L_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12785,8 +12784,8 @@ std::string NMD::ROUND_L_S(uint64 instruction) */ std::string NMD::ROUND_W_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12807,8 +12806,8 @@ std::string NMD::ROUND_W_D(uint64 instruction) */ std::string NMD::ROUND_W_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12829,8 +12828,8 @@ std::string NMD::ROUND_W_S(uint64 instruction) */ std::string NMD::RSQRT_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12851,8 +12850,8 @@ std::string NMD::RSQRT_D(uint64 instruction) */ std::string NMD::RSQRT_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -12873,9 +12872,9 @@ std::string NMD::RSQRT_S(uint64 instruction) */ std::string NMD::SAVE_16_(uint64 instruction) { - uint64 count_value = extract_count_3_2_1_0(instruction); uint64 rt1_value = extract_rtl_11(instruction); - uint64 u_value = extr_uil4il4bs4Fmsb7(instruction); + uint64 u_value = extract_u_7_6_5_4__s4(instruction); + uint64 count_value = extract_count_3_2_1_0(instruction); std::string u = IMMEDIATE(copy(u_value)); return img::format("SAVE %s%s", u, @@ -12897,7 +12896,7 @@ std::string NMD::SAVE_32_(uint64 instruction) { uint64 count_value = extract_count_19_18_17_16(instruction); uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil3il3bs9Fmsb11(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); uint64 gp_value = extract_gp_2(instruction); std::string u = IMMEDIATE(copy(u_value)); @@ -12919,7 +12918,7 @@ std::string NMD::SAVE_32_(uint64 instruction) std::string NMD::SAVEF(uint64 instruction) { uint64 count_value = extract_count_19_18_17_16(instruction); - uint64 u_value = extr_uil3il3bs9Fmsb11(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3__s3(instruction); std::string u = IMMEDIATE(copy(u_value)); std::string count = IMMEDIATE(copy(count_value)); @@ -12941,12 +12940,12 @@ std::string NMD::SAVEF(uint64 instruction) std::string NMD::SB_16_(uint64 instruction) { uint64 rtz3_value = extract_rtz3_9_8_7(instruction); - uint64 u_value = extract_u_1_0(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_1_0(instruction); - std::string rtz3 = GPR(encode_gpr3_store(rtz3_value)); + std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("SB %s, %s(%s)", rtz3, u, rs3); } @@ -12987,8 +12986,8 @@ std::string NMD::SB_GP_(uint64 instruction) std::string NMD::SB_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13011,8 +13010,8 @@ std::string NMD::SB_S9_(uint64 instruction) std::string NMD::SB_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -13035,8 +13034,8 @@ std::string NMD::SB_U12_(uint64 instruction) std::string NMD::SBE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13059,8 +13058,8 @@ std::string NMD::SBE(uint64 instruction) std::string NMD::SBX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -13083,8 +13082,8 @@ std::string NMD::SBX(uint64 instruction) std::string NMD::SC(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13107,8 +13106,8 @@ std::string NMD::SC(uint64 instruction) std::string NMD::SCD(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil3il3bs5_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_s3(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13131,8 +13130,8 @@ std::string NMD::SCD(uint64 instruction) std::string NMD::SCDP(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ru_value = extract_ru_7_6_5_4_3(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ru_value = extract_ru_7_6_5_4_3(instruction); std::string rt = GPR(copy(rt_value)); std::string ru = GPR(copy(ru_value)); @@ -13155,8 +13154,8 @@ std::string NMD::SCDP(uint64 instruction) std::string NMD::SCE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil2il2bs6_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_s2(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13179,8 +13178,8 @@ std::string NMD::SCE(uint64 instruction) std::string NMD::SCWP(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ru_value = extract_ru_7_6_5_4_3(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ru_value = extract_ru_7_6_5_4_3(instruction); std::string rt = GPR(copy(rt_value)); std::string ru = GPR(copy(ru_value)); @@ -13203,8 +13202,8 @@ std::string NMD::SCWP(uint64 instruction) std::string NMD::SCWPE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ru_value = extract_ru_7_6_5_4_3(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ru_value = extract_ru_7_6_5_4_3(instruction); std::string rt = GPR(copy(rt_value)); std::string ru = GPR(copy(ru_value)); @@ -13227,7 +13226,7 @@ std::string NMD::SCWPE(uint64 instruction) std::string NMD::SD_GP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil3il3bs18Fmsb20(instruction); + uint64 u_value = extract_u_20_to_3__s3(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -13249,8 +13248,8 @@ std::string NMD::SD_GP_(uint64 instruction) std::string NMD::SD_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13273,8 +13272,8 @@ std::string NMD::SD_S9_(uint64 instruction) std::string NMD::SD_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -13336,8 +13335,8 @@ std::string NMD::SDBBP_32_(uint64 instruction) */ std::string NMD::SDC1_GP_(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 u_value = extr_uil2il2bs16Fmsb17(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 u_value = extract_u_17_to_2__s2(instruction); std::string ft = FPR(copy(ft_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -13358,9 +13357,9 @@ std::string NMD::SDC1_GP_(uint64 instruction) */ std::string NMD::SDC1_S9_(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string ft = FPR(copy(ft_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13382,9 +13381,9 @@ std::string NMD::SDC1_S9_(uint64 instruction) */ std::string NMD::SDC1_U12_(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string ft = FPR(copy(ft_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -13407,8 +13406,8 @@ std::string NMD::SDC1_U12_(uint64 instruction) std::string NMD::SDC1X(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ft_value = extract_ft_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string rs = GPR(copy(rs_value)); @@ -13431,8 +13430,8 @@ std::string NMD::SDC1X(uint64 instruction) std::string NMD::SDC1XS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ft_value = extract_ft_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string rs = GPR(copy(rs_value)); @@ -13455,8 +13454,8 @@ std::string NMD::SDC1XS(uint64 instruction) std::string NMD::SDC2(uint64 instruction) { uint64 cs_value = extract_cs_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string cs = CPR(copy(cs_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13479,9 +13478,9 @@ std::string NMD::SDC2(uint64 instruction) std::string NMD::SDM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 count3_value = extract_count3_14_13_12(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); + uint64 count3_value = extract_count3_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13505,7 +13504,7 @@ std::string NMD::SDM(uint64 instruction) std::string NMD::SDPC_48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction); + int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); std::string rt = GPR(copy(rt_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 6); @@ -13527,8 +13526,8 @@ std::string NMD::SDPC_48_(uint64 instruction) std::string NMD::SDXS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -13551,8 +13550,8 @@ std::string NMD::SDXS(uint64 instruction) std::string NMD::SDX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -13618,9 +13617,9 @@ std::string NMD::SEH(uint64 instruction) */ std::string NMD::SEL_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -13642,9 +13641,9 @@ std::string NMD::SEL_D(uint64 instruction) */ std::string NMD::SEL_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -13666,9 +13665,9 @@ std::string NMD::SEL_S(uint64 instruction) */ std::string NMD::SELEQZ_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -13690,9 +13689,9 @@ std::string NMD::SELEQZ_D(uint64 instruction) */ std::string NMD::SELEQZ_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -13714,9 +13713,9 @@ std::string NMD::SELEQZ_S(uint64 instruction) */ std::string NMD::SELNEZ_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -13738,9 +13737,9 @@ std::string NMD::SELNEZ_D(uint64 instruction) */ std::string NMD::SELNEZ_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -13763,8 +13762,8 @@ std::string NMD::SELNEZ_S(uint64 instruction) std::string NMD::SEQI(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -13787,12 +13786,12 @@ std::string NMD::SEQI(uint64 instruction) std::string NMD::SH_16_(uint64 instruction) { uint64 rtz3_value = extract_rtz3_9_8_7(instruction); - uint64 u_value = extr_uil1il1bs2Fmsb2(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_2_1__s1(instruction); - std::string rtz3 = GPR(encode_gpr3_store(rtz3_value)); + std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("SH %s, %s(%s)", rtz3, u, rs3); } @@ -13811,7 +13810,7 @@ std::string NMD::SH_16_(uint64 instruction) std::string NMD::SH_GP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil1il1bs17Fmsb17(instruction); + uint64 u_value = extract_u_17_to_1__s1(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -13833,8 +13832,8 @@ std::string NMD::SH_GP_(uint64 instruction) std::string NMD::SH_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13857,8 +13856,8 @@ std::string NMD::SH_S9_(uint64 instruction) std::string NMD::SH_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -13881,8 +13880,8 @@ std::string NMD::SH_U12_(uint64 instruction) std::string NMD::SHE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -13904,7 +13903,7 @@ std::string NMD::SHE(uint64 instruction) */ std::string NMD::SHILO(uint64 instruction) { - int64 shift_value = extract_shift_21_20_19_18_17_16(instruction); + int64 shift_value = extract_shift__se5_21_20_19_18_17_16(instruction); uint64 ac_value = extract_ac_13_12(instruction); std::string shift = IMMEDIATE(copy(shift_value)); @@ -14021,8 +14020,8 @@ std::string NMD::SHLL_S_PH(uint64 instruction) std::string NMD::SHLL_S_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13_12_11(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14045,8 +14044,8 @@ std::string NMD::SHLL_S_W(uint64 instruction) std::string NMD::SHLLV_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14069,8 +14068,8 @@ std::string NMD::SHLLV_PH(uint64 instruction) std::string NMD::SHLLV_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14093,8 +14092,8 @@ std::string NMD::SHLLV_QB(uint64 instruction) std::string NMD::SHLLV_S_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14117,8 +14116,8 @@ std::string NMD::SHLLV_S_PH(uint64 instruction) std::string NMD::SHLLV_S_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14141,8 +14140,8 @@ std::string NMD::SHLLV_S_W(uint64 instruction) std::string NMD::SHRA_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14165,8 +14164,8 @@ std::string NMD::SHRA_PH(uint64 instruction) std::string NMD::SHRA_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14189,8 +14188,8 @@ std::string NMD::SHRA_QB(uint64 instruction) std::string NMD::SHRA_R_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14213,8 +14212,8 @@ std::string NMD::SHRA_R_PH(uint64 instruction) std::string NMD::SHRA_R_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14237,8 +14236,8 @@ std::string NMD::SHRA_R_QB(uint64 instruction) std::string NMD::SHRA_R_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13_12_11(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14261,8 +14260,8 @@ std::string NMD::SHRA_R_W(uint64 instruction) std::string NMD::SHRAV_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14285,8 +14284,8 @@ std::string NMD::SHRAV_PH(uint64 instruction) std::string NMD::SHRAV_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14309,8 +14308,8 @@ std::string NMD::SHRAV_QB(uint64 instruction) std::string NMD::SHRAV_R_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14333,8 +14332,8 @@ std::string NMD::SHRAV_R_PH(uint64 instruction) std::string NMD::SHRAV_R_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14357,8 +14356,8 @@ std::string NMD::SHRAV_R_QB(uint64 instruction) std::string NMD::SHRAV_R_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14381,8 +14380,8 @@ std::string NMD::SHRAV_R_W(uint64 instruction) std::string NMD::SHRL_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13_12(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14405,8 +14404,8 @@ std::string NMD::SHRL_PH(uint64 instruction) std::string NMD::SHRL_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 sa_value = extract_sa_15_14_13(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 sa_value = extract_sa_15_14_13(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14429,8 +14428,8 @@ std::string NMD::SHRL_QB(uint64 instruction) std::string NMD::SHRLV_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14453,8 +14452,8 @@ std::string NMD::SHRLV_PH(uint64 instruction) std::string NMD::SHRLV_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rt = GPR(copy(rt_value)); @@ -14477,8 +14476,8 @@ std::string NMD::SHRLV_QB(uint64 instruction) std::string NMD::SHX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -14501,8 +14500,8 @@ std::string NMD::SHX(uint64 instruction) std::string NMD::SHXS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -14544,12 +14543,12 @@ std::string NMD::SIGRIE(uint64 instruction) */ std::string NMD::SLL_16_(uint64 instruction) { - uint64 shift3_value = extract_shift3_2_1_0(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 shift3_value = extract_shift3_2_1_0(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value)); return img::format("SLL %s, %s, %s", rt3, rs3, shift3); @@ -14569,8 +14568,8 @@ std::string NMD::SLL_16_(uint64 instruction) std::string NMD::SLL_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14593,8 +14592,8 @@ std::string NMD::SLL_32_(uint64 instruction) std::string NMD::SLLV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -14617,8 +14616,8 @@ std::string NMD::SLLV(uint64 instruction) std::string NMD::SLT(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -14641,8 +14640,8 @@ std::string NMD::SLT(uint64 instruction) std::string NMD::SLTI(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14665,8 +14664,8 @@ std::string NMD::SLTI(uint64 instruction) std::string NMD::SLTIU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14689,8 +14688,8 @@ std::string NMD::SLTIU(uint64 instruction) std::string NMD::SLTU(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -14713,8 +14712,8 @@ std::string NMD::SLTU(uint64 instruction) std::string NMD::SOV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -14756,8 +14755,8 @@ std::string NMD::SPECIAL2(uint64 instruction) */ std::string NMD::SQRT_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -14778,8 +14777,8 @@ std::string NMD::SQRT_D(uint64 instruction) */ std::string NMD::SQRT_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -14825,8 +14824,8 @@ std::string NMD::SRA(uint64 instruction) std::string NMD::SRAV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -14848,12 +14847,12 @@ std::string NMD::SRAV(uint64 instruction) */ std::string NMD::SRL_16_(uint64 instruction) { - uint64 shift3_value = extract_shift3_2_1_0(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 shift3_value = extract_shift3_2_1_0(instruction); - std::string rt3 = GPR(encode_gpr3(rt3_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); std::string shift3 = IMMEDIATE(encode_shift3_from_shift(shift3_value)); return img::format("SRL %s, %s, %s", rt3, rs3, shift3); @@ -14873,8 +14872,8 @@ std::string NMD::SRL_16_(uint64 instruction) std::string NMD::SRL_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 shift_value = extract_shift_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 shift_value = extract_shift_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); @@ -14897,8 +14896,8 @@ std::string NMD::SRL_32_(uint64 instruction) std::string NMD::SRLV(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -14921,8 +14920,8 @@ std::string NMD::SRLV(uint64 instruction) std::string NMD::SUB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -14944,9 +14943,9 @@ std::string NMD::SUB(uint64 instruction) */ std::string NMD::SUB_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -14968,9 +14967,9 @@ std::string NMD::SUB_D(uint64 instruction) */ std::string NMD::SUB_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 fd_value = extract_fd_10_9_8_7_6(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); + uint64 fd_value = extract_fd_15_14_13_12_11(instruction); std::string fd = FPR(copy(fd_value)); std::string fs = FPR(copy(fs_value)); @@ -14993,8 +14992,8 @@ std::string NMD::SUB_S(uint64 instruction) std::string NMD::SUBQ_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15018,8 +15017,8 @@ std::string NMD::SUBQ_PH(uint64 instruction) std::string NMD::SUBQ_S_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15043,8 +15042,8 @@ std::string NMD::SUBQ_S_PH(uint64 instruction) std::string NMD::SUBQ_S_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15068,8 +15067,8 @@ std::string NMD::SUBQ_S_W(uint64 instruction) std::string NMD::SUBQH_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15093,8 +15092,8 @@ std::string NMD::SUBQH_PH(uint64 instruction) std::string NMD::SUBQH_R_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15118,8 +15117,8 @@ std::string NMD::SUBQH_R_PH(uint64 instruction) std::string NMD::SUBQH_R_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15143,8 +15142,8 @@ std::string NMD::SUBQH_R_W(uint64 instruction) std::string NMD::SUBQH_W(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15166,13 +15165,13 @@ std::string NMD::SUBQH_W(uint64 instruction) */ std::string NMD::SUBU_16_(uint64 instruction) { - uint64 rd3_value = extract_rd3_3_2_1(instruction); uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 rd3_value = extract_rd3_3_2_1(instruction); - std::string rd3 = GPR(encode_gpr3(rd3_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rd3 = GPR(decode_gpr_gpr3(rd3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); return img::format("SUBU %s, %s, %s", rd3, rs3, rt3); } @@ -15191,8 +15190,8 @@ std::string NMD::SUBU_16_(uint64 instruction) std::string NMD::SUBU_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15215,8 +15214,8 @@ std::string NMD::SUBU_32_(uint64 instruction) std::string NMD::SUBU_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15239,8 +15238,8 @@ std::string NMD::SUBU_PH(uint64 instruction) std::string NMD::SUBU_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15263,8 +15262,8 @@ std::string NMD::SUBU_QB(uint64 instruction) std::string NMD::SUBU_S_PH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15287,8 +15286,8 @@ std::string NMD::SUBU_S_PH(uint64 instruction) std::string NMD::SUBU_S_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15312,8 +15311,8 @@ std::string NMD::SUBU_S_QB(uint64 instruction) std::string NMD::SUBUH_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15337,8 +15336,8 @@ std::string NMD::SUBUH_QB(uint64 instruction) std::string NMD::SUBUH_R_QB(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15361,12 +15360,12 @@ std::string NMD::SUBUH_R_QB(uint64 instruction) std::string NMD::SW_16_(uint64 instruction) { uint64 rtz3_value = extract_rtz3_9_8_7(instruction); - uint64 u_value = extr_uil0il2bs4Fmsb5(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); + uint64 u_value = extract_u_3_2_1_0__s2(instruction); - std::string rtz3 = GPR(encode_gpr3_store(rtz3_value)); + std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs3 = GPR(encode_gpr3(rs3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); return img::format("SW %s, %s(%s)", rtz3, u, rs3); } @@ -15384,13 +15383,13 @@ std::string NMD::SW_16_(uint64 instruction) */ std::string NMD::SW_4X4_(uint64 instruction) { - uint64 rs4_value = extract_rs4_4_2_1_0(instruction); uint64 rtz4_value = extract_rtz4_9_7_6_5(instruction); - uint64 u_value = extr_uil3il3bs1_il8il2bs1Fmsb3(instruction); + uint64 rs4_value = extract_rs4_4_2_1_0(instruction); + uint64 u_value = extract_u_3_8__s2(instruction); - std::string rtz4 = GPR(encode_gpr4_zero(rtz4_value)); + std::string rtz4 = GPR(decode_gpr_gpr4_zero(rtz4_value)); std::string u = IMMEDIATE(copy(u_value)); - std::string rs4 = GPR(encode_gpr4(rs4_value)); + std::string rs4 = GPR(decode_gpr_gpr4(rs4_value)); return img::format("SW %s, %s(%s)", rtz4, u, rs4); } @@ -15408,10 +15407,10 @@ std::string NMD::SW_4X4_(uint64 instruction) */ std::string NMD::SW_GP16_(uint64 instruction) { + uint64 u_value = extract_u_6_5_4_3_2_1_0__s2(instruction); uint64 rtz3_value = extract_rtz3_9_8_7(instruction); - uint64 u_value = extr_uil0il2bs7Fmsb8(instruction); - std::string rtz3 = GPR(encode_gpr3_store(rtz3_value)); + std::string rtz3 = GPR(decode_gpr_gpr3_src_store(rtz3_value)); std::string u = IMMEDIATE(copy(u_value)); return img::format("SW %s, %s($%d)", rtz3, u, 28); @@ -15431,7 +15430,7 @@ std::string NMD::SW_GP16_(uint64 instruction) std::string NMD::SW_GP_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extr_uil2il2bs19Fmsb20(instruction); + uint64 u_value = extract_u_20_to_2__s2(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -15453,7 +15452,7 @@ std::string NMD::SW_GP_(uint64 instruction) std::string NMD::SW_S9_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); std::string rt = GPR(copy(rt_value)); @@ -15477,7 +15476,7 @@ std::string NMD::SW_S9_(uint64 instruction) std::string NMD::SW_SP_(uint64 instruction) { uint64 rt_value = extract_rt_9_8_7_6_5(instruction); - uint64 u_value = extr_uil0il2bs5Fmsb6(instruction); + uint64 u_value = extract_u_4_3_2_1_0__s2(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -15499,8 +15498,8 @@ std::string NMD::SW_SP_(uint64 instruction) std::string NMD::SW_U12_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -15522,8 +15521,8 @@ std::string NMD::SW_U12_(uint64 instruction) */ std::string NMD::SWC1_GP_(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 u_value = extr_uil2il2bs16Fmsb17(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 u_value = extract_u_17_to_2__s2(instruction); std::string ft = FPR(copy(ft_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -15544,9 +15543,9 @@ std::string NMD::SWC1_GP_(uint64 instruction) */ std::string NMD::SWC1_S9_(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string ft = FPR(copy(ft_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -15568,9 +15567,9 @@ std::string NMD::SWC1_S9_(uint64 instruction) */ std::string NMD::SWC1_U12_(uint64 instruction) { - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string ft = FPR(copy(ft_value)); std::string u = IMMEDIATE(copy(u_value)); @@ -15593,8 +15592,8 @@ std::string NMD::SWC1_U12_(uint64 instruction) std::string NMD::SWC1X(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ft_value = extract_ft_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string rs = GPR(copy(rs_value)); @@ -15617,8 +15616,8 @@ std::string NMD::SWC1X(uint64 instruction) std::string NMD::SWC1XS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 ft_value = extract_ft_15_14_13_12_11(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_15_14_13_12_11(instruction); std::string ft = FPR(copy(ft_value)); std::string rs = GPR(copy(rs_value)); @@ -15641,8 +15640,8 @@ std::string NMD::SWC1XS(uint64 instruction) std::string NMD::SWC2(uint64 instruction) { uint64 cs_value = extract_cs_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string cs = CPR(copy(cs_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -15665,8 +15664,8 @@ std::string NMD::SWC2(uint64 instruction) std::string NMD::SWE(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -15689,9 +15688,9 @@ std::string NMD::SWE(uint64 instruction) std::string NMD::SWM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 count3_value = extract_count3_14_13_12(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); + uint64 count3_value = extract_count3_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -15715,7 +15714,7 @@ std::string NMD::SWM(uint64 instruction) std::string NMD::SWPC_48_(uint64 instruction) { uint64 rt_value = extract_rt_41_40_39_38_37(instruction); - int64 s_value = extr_sil0il16bs16_il16il0bs16Tmsb31(instruction); + int64 s_value = extract_s__se31_15_to_0_31_to_16(instruction); std::string rt = GPR(copy(rt_value)); std::string s = ADDRESS(encode_s_from_address(s_value), 6); @@ -15737,8 +15736,8 @@ std::string NMD::SWPC_48_(uint64 instruction) std::string NMD::SWX(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15761,8 +15760,8 @@ std::string NMD::SWX(uint64 instruction) std::string NMD::SWXS(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -15804,8 +15803,8 @@ std::string NMD::SYNC(uint64 instruction) */ std::string NMD::SYNCI(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string s = IMMEDIATE(copy(s_value)); std::string rs = GPR(copy(rs_value)); @@ -15826,8 +15825,8 @@ std::string NMD::SYNCI(uint64 instruction) */ std::string NMD::SYNCIE(uint64 instruction) { - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string s = IMMEDIATE(copy(s_value)); std::string rs = GPR(copy(rs_value)); @@ -16146,8 +16145,8 @@ std::string NMD::TNE(uint64 instruction) */ std::string NMD::TRUNC_L_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -16168,8 +16167,8 @@ std::string NMD::TRUNC_L_D(uint64 instruction) */ std::string NMD::TRUNC_L_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -16190,8 +16189,8 @@ std::string NMD::TRUNC_L_S(uint64 instruction) */ std::string NMD::TRUNC_W_D(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -16212,8 +16211,8 @@ std::string NMD::TRUNC_W_D(uint64 instruction) */ std::string NMD::TRUNC_W_S(uint64 instruction) { - uint64 fs_value = extract_fs_15_14_13_12_11(instruction); - uint64 ft_value = extract_ft_20_19_18_17_16(instruction); + uint64 ft_value = extract_ft_25_24_23_22_21(instruction); + uint64 fs_value = extract_fs_20_19_18_17_16(instruction); std::string ft = FPR(copy(ft_value)); std::string fs = FPR(copy(fs_value)); @@ -16235,9 +16234,9 @@ std::string NMD::TRUNC_W_S(uint64 instruction) std::string NMD::UALDM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 count3_value = extract_count3_14_13_12(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); + uint64 count3_value = extract_count3_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -16261,8 +16260,8 @@ std::string NMD::UALDM(uint64 instruction) std::string NMD::UALH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -16285,9 +16284,9 @@ std::string NMD::UALH(uint64 instruction) std::string NMD::UALWM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 count3_value = extract_count3_14_13_12(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); + uint64 count3_value = extract_count3_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -16311,9 +16310,9 @@ std::string NMD::UALWM(uint64 instruction) std::string NMD::UASDM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 count3_value = extract_count3_14_13_12(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); + uint64 count3_value = extract_count3_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -16337,8 +16336,8 @@ std::string NMD::UASDM(uint64 instruction) std::string NMD::UASH(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -16361,9 +16360,9 @@ std::string NMD::UASH(uint64 instruction) std::string NMD::UASWM(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 count3_value = extract_count3_14_13_12(instruction); - int64 s_value = extr_sil0il0bs8_il15il8bs1Tmsb8(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + int64 s_value = extract_s__se8_15_7_6_5_4_3_2_1_0(instruction); + uint64 count3_value = extract_count3_14_13_12(instruction); std::string rt = GPR(copy(rt_value)); std::string s = IMMEDIATE(copy(s_value)); @@ -16470,8 +16469,8 @@ std::string NMD::XOR_16_(uint64 instruction) uint64 rt3_value = extract_rt3_9_8_7(instruction); uint64 rs3_value = extract_rs3_6_5_4(instruction); - std::string rs3 = GPR(encode_gpr3(rs3_value)); - std::string rt3 = GPR(encode_gpr3(rt3_value)); + std::string rs3 = GPR(decode_gpr_gpr3(rs3_value)); + std::string rt3 = GPR(decode_gpr_gpr3(rt3_value)); return img::format("XOR %s, %s", rs3, rt3); } @@ -16490,8 +16489,8 @@ std::string NMD::XOR_16_(uint64 instruction) std::string NMD::XOR_32_(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 rd_value = extract_rd_20_19_18_17_16(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 rd_value = extract_rd_15_14_13_12_11(instruction); std::string rd = GPR(copy(rd_value)); std::string rs = GPR(copy(rs_value)); @@ -16514,8 +16513,8 @@ std::string NMD::XOR_32_(uint64 instruction) std::string NMD::XORI(uint64 instruction) { uint64 rt_value = extract_rt_25_24_23_22_21(instruction); - uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); uint64 rs_value = extract_rs_20_19_18_17_16(instruction); + uint64 u_value = extract_u_11_10_9_8_7_6_5_4_3_2_1_0(instruction); std::string rt = GPR(copy(rt_value)); std::string rs = GPR(copy(rs_value)); diff --git a/disas/nanomips.h b/disas/nanomips.h index 84cc9a6dfc..6482edafe3 100644 --- a/disas/nanomips.h +++ b/disas/nanomips.h @@ -1,13 +1,13 @@ /* * Header file for nanoMIPS disassembler component of QEMU * - * Copyright (C) 2018 Wave Computing + * Copyright (C) 2018 Wave Computing, Inc. * Copyright (C) 2018 Matthew Fortune <matthew.fortune@mips.com> - * Copyright (C) 2018 Aleksandar Markovic <aleksandar.markovic@wavecomp.com> + * Copyright (C) 2018 Aleksandar Markovic <amarkovic@wavecomp.com> * * This program is free software: you can redistribute it and/or modify * it under the terms of the GNU General Public License as published by - * the Free Software Foundation, either version 3 of the License, or + * the Free Software Foundation, either version 2 of the License, or * (at your option) any later version. * * This program is distributed in the hope that it will be useful, @@ -17,6 +17,7 @@ * * You should have received a copy of the GNU General Public License * along with this program. If not, see <https://www.gnu.org/licenses/>. + * */ #ifndef NANOMIPS_DISASSEMBLER_H @@ -24,14 +25,14 @@ #include <string> -typedef unsigned short uint16; -typedef unsigned int uint32; -typedef long long int64; -typedef unsigned long long uint64; +typedef int64_t int64; +typedef uint64_t uint64; +typedef uint32_t uint32; +typedef uint16_t uint16; namespace img { - typedef unsigned long long address; + typedef uint64_t address; } @@ -104,13 +105,14 @@ private: uint64 renumber_registers(uint64 index, uint64 *register_list, size_t register_list_size); - uint64 encode_gpr3(uint64 d); - uint64 encode_gpr3_store(uint64 d); - uint64 encode_rd1_from_rd(uint64 d); - uint64 encode_gpr4_zero(uint64 d); - uint64 encode_gpr4(uint64 d); - uint64 encode_rd2_reg1(uint64 d); - uint64 encode_rd2_reg2(uint64 d); + + uint64 decode_gpr_gpr4(uint64 d); + uint64 decode_gpr_gpr4_zero(uint64 d); + uint64 decode_gpr_gpr3(uint64 d); + uint64 decode_gpr_gpr3_src_store(uint64 d); + uint64 decode_gpr_gpr2_reg1(uint64 d); + uint64 decode_gpr_gpr2_reg2(uint64 d); + uint64 decode_gpr_gpr1(uint64 d); uint64 copy(uint64 d); int64 copy(int64 d); @@ -142,20 +144,20 @@ private: std::string CPR(uint64 reg); std::string ADDRESS(uint64 value, int instruction_size); - int64 extract_s_4_2_1_0(uint64 instruction); - int64 extr_sil0il0bs8_il15il8bs1Tmsb8(uint64 instruction); - int64 extr_sil0il10bs1_il1il1bs9Tmsb10(uint64 instruction); - int64 extr_sil0il11bs1_il1il1bs10Tmsb11(uint64 instruction); - int64 extr_sil0il14bs1_il1il1bs13Tmsb14(uint64 instruction); - int64 extr_sil0il16bs16_il16il0bs16Tmsb31(uint64 instruction); - int64 extr_sil0il21bs1_il1il1bs20Tmsb21(uint64 instruction); - int64 extr_sil0il25bs1_il1il1bs24Tmsb25(uint64 instruction); - int64 extr_sil0il31bs1_il2il21bs10_il12il12bs9Tmsb31(uint64 instruction); - int64 extr_sil0il7bs1_il1il1bs6Tmsb7(uint64 instruction); - int64 extr_sil11il0bs10Tmsb9(uint64 instruction); - int64 extract_shift_21_20_19_18_17_16(uint64 instruction); - int64 extr_sil2il2bs6_il15il8bs1Tmsb8(uint64 instruction); - int64 extr_sil3il3bs5_il15il8bs1Tmsb8(uint64 instruction); + int64 extract_s__se3_4_2_1_0(uint64 instruction); + int64 extract_s__se7_0_6_5_4_3_2_1_s1(uint64 instruction); + int64 extract_s__se8_15_7_6_5_4_3_s3(uint64 instruction); + int64 extract_s__se8_15_7_6_5_4_3_2_s2(uint64 instruction); + int64 extract_s__se8_15_7_6_5_4_3_2_1_0(uint64 instruction); + int64 extract_s__se9_20_19_18_17_16_15_14_13_12_11(uint64 instruction); + int64 extract_s__se10_0_9_8_7_6_5_4_3_2_1_s1(uint64 instruction); + int64 extract_s__se11_0_10_9_8_7_6_5_4_3_2_1_0_s1(uint64 instruction); + int64 extract_s__se14_0_13_to_1_s1(uint64 instruction); + int64 extract_s__se21_0_20_to_1_s1(uint64 instruction); + int64 extract_s__se25_0_24_to_1_s1(uint64 instruction); + int64 extract_s__se31_15_to_0_31_to_16(uint64 instruction); + int64 extract_s__se31_0_11_to_2_20_to_12_s12(uint64 instruction); + int64 extract_shift__se5_21_20_19_18_17_16(uint64 instruction); uint64 extract_ac_13_12(uint64 instruction); uint64 extract_bit_16_15_14_13_12_11(uint64 instruction); @@ -175,10 +177,10 @@ private: uint64 extract_ct_25_24_23_22_21(uint64 instruction); uint64 extract_eu_3_2_1_0(uint64 instruction); uint64 extract_eu_6_5_4_3_2_1_0(uint64 instruction); - uint64 extract_fd_10_9_8_7_6(uint64 instruction); - uint64 extract_fs_15_14_13_12_11(uint64 instruction); + uint64 extract_fd_15_14_13_12_11(uint64 instruction); + uint64 extract_fs_20_19_18_17_16(uint64 instruction); uint64 extract_ft_15_14_13_12_11(uint64 instruction); - uint64 extract_ft_20_19_18_17_16(uint64 instruction); + uint64 extract_ft_25_24_23_22_21(uint64 instruction); uint64 extract_gp_2(uint64 instruction); uint64 extract_hint_25_24_23_22_21(uint64 instruction); uint64 extract_hs_20_19_18_17_16(uint64 instruction); @@ -190,7 +192,7 @@ private: uint64 extract_rdl_25_24(uint64 instruction); uint64 extract_rd2_3_8(uint64 instruction); uint64 extract_rd3_3_2_1(uint64 instruction); - uint64 extract_rd_20_19_18_17_16(uint64 instruction); + uint64 extract_rd_15_14_13_12_11(uint64 instruction); uint64 extract_rs3_6_5_4(uint64 instruction); uint64 extract_rs4_4_2_1_0(uint64 instruction); uint64 extract_rs_4_3_2_1_0(uint64 instruction); @@ -217,7 +219,7 @@ private: uint64 extract_shift_20_19_18_17_16(uint64 instruction); uint64 extract_shift_10_9_8_7_6(uint64 instruction); uint64 extract_shiftx_11_10_9_8_7_6(uint64 instruction); - uint64 extr_shiftxil7il1bs4Fmsb4(uint64 instruction); + uint64 extract_shiftx_10_9_8_7__s1(uint64 instruction); uint64 extract_size_20_19_18_17_16(uint64 instruction); uint64 extract_stripe_6(uint64 instruction); uint64 extract_stype_20_19_18_17_16(uint64 instruction); @@ -226,49 +228,24 @@ private: uint64 extract_u_15_to_0(uint64 instruction); uint64 extract_u_17_to_0(uint64 instruction); uint64 extract_u_1_0(uint64 instruction); - uint64 extr_uil0il1bs4Fmsb4(uint64 instruction); - uint64 extr_uil0il2bs3Fmsb4(uint64 instruction); - uint64 extr_uil0il2bs4Fmsb5(uint64 instruction); - uint64 extr_uil0il2bs5Fmsb6(uint64 instruction); - uint64 extr_uil0il2bs6Fmsb7(uint64 instruction); - uint64 extr_uil0il2bs7Fmsb8(uint64 instruction); - uint64 extr_uil0il32bs32Fmsb63(uint64 instruction); + uint64 extract_u_3_2_1_0__s1(uint64 instruction); + uint64 extract_u_2_1_0__s2(uint64 instruction); + uint64 extract_u_3_2_1_0__s2(uint64 instruction); + uint64 extract_u_4_3_2_1_0__s2(uint64 instruction); + uint64 extract_u_5_4_3_2_1_0__s2(uint64 instruction); + uint64 extract_u_6_5_4_3_2_1_0__s2(uint64 instruction); + uint64 extract_u_31_to_0__s32(uint64 instruction); uint64 extract_u_10(uint64 instruction); uint64 extract_u_17_16_15_14_13_12_11(uint64 instruction); uint64 extract_u_20_19_18_17_16_15_14_13(uint64 instruction); - uint64 extr_uil1il1bs17Fmsb17(uint64 instruction); - uint64 extr_uil1il1bs2Fmsb2(uint64 instruction); - uint64 extr_uil2il2bs16Fmsb17(uint64 instruction); - uint64 extr_uil2il2bs19Fmsb20(uint64 instruction); - uint64 extr_uil3il3bs18Fmsb20(uint64 instruction); - uint64 extr_uil3il3bs1_il8il2bs1Fmsb3(uint64 instruction); - uint64 extr_uil3il3bs9Fmsb11(uint64 instruction); - uint64 extr_uil4il4bs4Fmsb7(uint64 instruction); - uint64 extr_xil0il0bs12Fmsb11(uint64 instruction); - uint64 extr_xil0il0bs3_il4il0bs1Fmsb2(uint64 instruction); - uint64 extr_xil10il0bs1Fmsb0(uint64 instruction); - uint64 extr_xil10il0bs1_il11il0bs5Fmsb4(uint64 instruction); - uint64 extr_xil10il0bs1_il14il0bs2Fmsb1(uint64 instruction); - uint64 extr_xil10il0bs4_il22il0bs4Fmsb3(uint64 instruction); - uint64 extr_xil10il0bs6Fmsb5(uint64 instruction); - uint64 extr_xil11il0bs1Fmsb0(uint64 instruction); - uint64 extr_xil11il0bs5Fmsb4(uint64 instruction); - uint64 extr_xil12il0bs1Fmsb0(uint64 instruction); - uint64 extr_xil14il0bs1_il15il0bs1Fmsb0(uint64 instruction); - uint64 extr_xil14il0bs2Fmsb1(uint64 instruction); - uint64 extr_xil15il0bs1Fmsb0(uint64 instruction); - uint64 extr_xil16il0bs10Fmsb9(uint64 instruction); - uint64 extr_xil16il0bs5Fmsb4(uint64 instruction); - uint64 extr_xil17il0bs1Fmsb0(uint64 instruction); - uint64 extr_xil17il0bs9Fmsb8(uint64 instruction); - uint64 extr_xil21il0bs5Fmsb4(uint64 instruction); - uint64 extr_xil24il0bs1Fmsb0(uint64 instruction); - uint64 extr_xil2il0bs1_il15il0bs1Fmsb0(uint64 instruction); - uint64 extr_xil6il0bs3Fmsb2(uint64 instruction); - uint64 extr_xil6il0bs3_il10il0bs1Fmsb2(uint64 instruction); - uint64 extr_xil9il0bs2Fmsb1(uint64 instruction); - uint64 extr_xil9il0bs3Fmsb2(uint64 instruction); - uint64 extr_xil9il0bs3_il16il0bs5Fmsb4(uint64 instruction); + uint64 extract_u_17_to_1__s1(uint64 instruction); + uint64 extract_u_2_1__s1(uint64 instruction); + uint64 extract_u_17_to_2__s2(uint64 instruction); + uint64 extract_u_20_to_2__s2(uint64 instruction); + uint64 extract_u_20_to_3__s3(uint64 instruction); + uint64 extract_u_3_8__s2(uint64 instruction); + uint64 extract_u_11_10_9_8_7_6_5_4_3__s3(uint64 instruction); + uint64 extract_u_7_6_5_4__s4(uint64 instruction); bool ADDIU_32__cond(uint64 instruction); bool ADDIU_RS5__cond(uint64 instruction); diff --git a/hw/nvram/fw_cfg.c b/hw/nvram/fw_cfg.c index 3cb726ff68..de58c7be46 100644 --- a/hw/nvram/fw_cfg.c +++ b/hw/nvram/fw_cfg.c @@ -68,15 +68,14 @@ static char *read_splashfile(char *filename, gsize *file_sizep, int *file_typep) { GError *err = NULL; - gboolean res; gchar *content; int file_type; unsigned int filehead; int bmp_bpp; - res = g_file_get_contents(filename, &content, file_sizep, &err); - if (res == FALSE) { - error_report("failed to read splash file '%s'", filename); + if (!g_file_get_contents(filename, &content, file_sizep, &err)) { + error_report("failed to read splash file '%s': %s", + filename, err->message); g_error_free(err); return NULL; } @@ -118,47 +117,39 @@ error: static void fw_cfg_bootsplash(FWCfgState *s) { - int boot_splash_time = -1; const char *boot_splash_filename = NULL; - char *p; + const char *boot_splash_time = NULL; + uint8_t qemu_extra_params_fw[2]; char *filename, *file_data; gsize file_size; int file_type; - const char *temp; /* get user configuration */ QemuOptsList *plist = qemu_find_opts("boot-opts"); QemuOpts *opts = QTAILQ_FIRST(&plist->head); - if (opts != NULL) { - temp = qemu_opt_get(opts, "splash"); - if (temp != NULL) { - boot_splash_filename = temp; - } - temp = qemu_opt_get(opts, "splash-time"); - if (temp != NULL) { - p = (char *)temp; - boot_splash_time = strtol(p, &p, 10); - } - } + boot_splash_filename = qemu_opt_get(opts, "splash"); + boot_splash_time = qemu_opt_get(opts, "splash-time"); /* insert splash time if user configurated */ - if (boot_splash_time >= 0) { + if (boot_splash_time) { + int64_t bst_val = qemu_opt_get_number(opts, "splash-time", -1); /* validate the input */ - if (boot_splash_time > 0xffff) { - error_report("splash time is big than 65535, force it to 65535."); - boot_splash_time = 0xffff; + if (bst_val < 0 || bst_val > 0xffff) { + error_report("splash-time is invalid," + "it should be a value between 0 and 65535"); + exit(1); } /* use little endian format */ - qemu_extra_params_fw[0] = (uint8_t)(boot_splash_time & 0xff); - qemu_extra_params_fw[1] = (uint8_t)((boot_splash_time >> 8) & 0xff); + qemu_extra_params_fw[0] = (uint8_t)(bst_val & 0xff); + qemu_extra_params_fw[1] = (uint8_t)((bst_val >> 8) & 0xff); fw_cfg_add_file(s, "etc/boot-menu-wait", qemu_extra_params_fw, 2); } /* insert splash file if user configurated */ - if (boot_splash_filename != NULL) { + if (boot_splash_filename) { filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, boot_splash_filename); if (filename == NULL) { - error_report("failed to find file '%s'.", boot_splash_filename); + error_report("failed to find file '%s'", boot_splash_filename); return; } @@ -186,26 +177,25 @@ static void fw_cfg_bootsplash(FWCfgState *s) static void fw_cfg_reboot(FWCfgState *s) { - int reboot_timeout = -1; - char *p; - const char *temp; + const char *reboot_timeout = NULL; + int64_t rt_val = -1; /* get user configuration */ QemuOptsList *plist = qemu_find_opts("boot-opts"); QemuOpts *opts = QTAILQ_FIRST(&plist->head); - if (opts != NULL) { - temp = qemu_opt_get(opts, "reboot-timeout"); - if (temp != NULL) { - p = (char *)temp; - reboot_timeout = strtol(p, &p, 10); + reboot_timeout = qemu_opt_get(opts, "reboot-timeout"); + + if (reboot_timeout) { + rt_val = qemu_opt_get_number(opts, "reboot-timeout", -1); + /* validate the input */ + if (rt_val < 0 || rt_val > 0xffff) { + error_report("reboot timeout is invalid," + "it should be a value between 0 and 65535"); + exit(1); } } - /* validate the input */ - if (reboot_timeout > 0xffff) { - error_report("reboot timeout is larger than 65535, force it to 65535."); - reboot_timeout = 0xffff; - } - fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&reboot_timeout, 4), 4); + + fw_cfg_add_file(s, "etc/boot-fail-wait", g_memdup(&rt_val, 4), 4); } static void fw_cfg_write(FWCfgState *s, uint8_t value) diff --git a/hw/riscv/sifive_clint.c b/hw/riscv/sifive_clint.c index 0d2fd52487..d4c159e937 100644 --- a/hw/riscv/sifive_clint.c +++ b/hw/riscv/sifive_clint.c @@ -146,15 +146,15 @@ static void sifive_clint_write(void *opaque, hwaddr addr, uint64_t value, error_report("clint: invalid timecmp hartid: %zu", hartid); } else if ((addr & 0x7) == 0) { /* timecmp_lo */ - uint64_t timecmp = env->timecmp; + uint64_t timecmp_hi = env->timecmp >> 32; sifive_clint_write_timecmp(RISCV_CPU(cpu), - timecmp << 32 | (value & 0xFFFFFFFF)); + timecmp_hi << 32 | (value & 0xFFFFFFFF)); return; } else if ((addr & 0x7) == 4) { /* timecmp_hi */ - uint64_t timecmp = env->timecmp; + uint64_t timecmp_lo = env->timecmp; sifive_clint_write_timecmp(RISCV_CPU(cpu), - value << 32 | (timecmp & 0xFFFFFFFF)); + value << 32 | (timecmp_lo & 0xFFFFFFFF)); } else { error_report("clint: invalid timecmp write: %08x", (uint32_t)addr); } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index cb513cc3bb..5d9d65ff29 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -192,9 +192,8 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); - /* sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, - serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), - SIFIVE_E_UART1_IRQ)); */ + sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, + serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 9cf9a1f986..d12ec3fc9a 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -214,7 +214,7 @@ static uint64_t sifive_plic_read(void *opaque, hwaddr addr, unsigned size) } else if (addr >= plic->pending_base && /* 1 bit per source */ addr < plic->pending_base + (plic->num_sources >> 3)) { - uint32_t word = (addr - plic->priority_base) >> 2; + uint32_t word = (addr - plic->pending_base) >> 2; if (RISCV_DEBUG_PLIC) { qemu_log("plic: read pending: word=%d value=%d\n", word, plic->pending[word]); diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index ef07df2442..3bd3b67507 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -85,7 +85,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, int cpu; uint32_t *cells; char *nodename; - uint32_t plic_phandle; + char ethclk_names[] = "pclk\0hclk\0tx_clk"; + uint32_t plic_phandle, ethclk_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -197,6 +198,17 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(cells); g_free(nodename); + nodename = g_strdup_printf("/soc/ethclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_GEM_CLOCK_FREQ); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", 3); + qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", 3); + ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); + g_free(nodename); + nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); @@ -208,6 +220,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + ethclk_phandle, ethclk_phandle, ethclk_phandle); + qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, + sizeof(ethclk_names)); qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1); qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0); g_free(nodename); @@ -225,6 +241,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_CLOCK_FREQ / 2); qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); qemu_fdt_setprop_cells(fdt, nodename, "interrupts", 1); @@ -350,9 +368,8 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_PLIC].size); sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ)); - /* sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, - serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), - SIFIVE_U_UART1_IRQ)); */ + sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base, + serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ)); sifive_clint_create(memmap[SIFIVE_U_CLINT].base, memmap[SIFIVE_U_CLINT].size, smp_cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index b0c3798cf2..456a3d3697 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -28,12 +28,26 @@ * Not yet implemented: * * Transmit FIFO using "qemu/fifo8.h" - * SIFIVE_UART_IE_TXWM interrupts - * SIFIVE_UART_IE_RXWM interrupts must honor fifo watermark - * Rx FIFO watermark interrupt trigger threshold - * Tx FIFO watermark interrupt trigger threshold. */ +/* Returns the state of the IP (interrupt pending) register */ +static uint64_t uart_ip(SiFiveUARTState *s) +{ + uint64_t ret = 0; + + uint64_t txcnt = SIFIVE_UART_GET_TXCNT(s->txctrl); + uint64_t rxcnt = SIFIVE_UART_GET_RXCNT(s->rxctrl); + + if (txcnt != 0) { + ret |= SIFIVE_UART_IP_TXWM; + } + if (s->rx_fifo_len > rxcnt) { + ret |= SIFIVE_UART_IP_RXWM; + } + + return ret; +} + static void update_irq(SiFiveUARTState *s) { int cond = 0; @@ -69,7 +83,7 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) case SIFIVE_UART_IE: return s->ie; case SIFIVE_UART_IP: - return s->rx_fifo_len ? SIFIVE_UART_IP_RXWM : 0; + return uart_ip(s); case SIFIVE_UART_TXCTRL: return s->txctrl; case SIFIVE_UART_RXCTRL: diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 2b38f89070..e7f0716fb6 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -39,6 +39,8 @@ #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "exec/address-spaces.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/gpex.h" #include "elf.h" #include <libfdt.h> @@ -47,14 +49,17 @@ static const struct MemmapEntry { hwaddr base; hwaddr size; } virt_memmap[] = { - [VIRT_DEBUG] = { 0x0, 0x100 }, - [VIRT_MROM] = { 0x1000, 0x11000 }, - [VIRT_TEST] = { 0x100000, 0x1000 }, - [VIRT_CLINT] = { 0x2000000, 0x10000 }, - [VIRT_PLIC] = { 0xc000000, 0x4000000 }, - [VIRT_UART0] = { 0x10000000, 0x100 }, - [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, - [VIRT_DRAM] = { 0x80000000, 0x0 }, + [VIRT_DEBUG] = { 0x0, 0x100 }, + [VIRT_MROM] = { 0x1000, 0x11000 }, + [VIRT_TEST] = { 0x100000, 0x1000 }, + [VIRT_CLINT] = { 0x2000000, 0x10000 }, + [VIRT_PLIC] = { 0xc000000, 0x4000000 }, + [VIRT_UART0] = { 0x10000000, 0x100 }, + [VIRT_VIRTIO] = { 0x10001000, 0x1000 }, + [VIRT_DRAM] = { 0x80000000, 0x0 }, + [VIRT_PCIE_MMIO] = { 0x40000000, 0x40000000 }, + [VIRT_PCIE_PIO] = { 0x03000000, 0x00010000 }, + [VIRT_PCIE_ECAM] = { 0x30000000, 0x10000000 }, }; static uint64_t load_kernel(const char *kernel_filename) @@ -98,6 +103,51 @@ static hwaddr load_initrd(const char *filename, uint64_t mem_size, return *start + size; } +static void create_pcie_irq_map(void *fdt, char *nodename, + uint32_t plic_phandle) +{ + int pin, dev; + uint32_t + full_irq_map[GPEX_NUM_IRQS * GPEX_NUM_IRQS * FDT_INT_MAP_WIDTH] = {}; + uint32_t *irq_map = full_irq_map; + + /* This code creates a standard swizzle of interrupts such that + * each device's first interrupt is based on it's PCI_SLOT number. + * (See pci_swizzle_map_irq_fn()) + * + * We only need one entry per interrupt in the table (not one per + * possible slot) seeing the interrupt-map-mask will allow the table + * to wrap to any number of devices. + */ + for (dev = 0; dev < GPEX_NUM_IRQS; dev++) { + int devfn = dev * 0x8; + + for (pin = 0; pin < GPEX_NUM_IRQS; pin++) { + int irq_nr = PCIE_IRQ + ((pin + PCI_SLOT(devfn)) % GPEX_NUM_IRQS); + int i = 0; + + irq_map[i] = cpu_to_be32(devfn << 8); + + i += FDT_PCI_ADDR_CELLS; + irq_map[i] = cpu_to_be32(pin + 1); + + i += FDT_PCI_INT_CELLS; + irq_map[i++] = cpu_to_be32(plic_phandle); + + i += FDT_PLIC_ADDR_CELLS; + irq_map[i] = cpu_to_be32(irq_nr); + + irq_map += FDT_INT_MAP_WIDTH; + } + } + + qemu_fdt_setprop(fdt, nodename, "interrupt-map", + full_irq_map, sizeof(full_irq_map)); + + qemu_fdt_setprop_cells(fdt, nodename, "interrupt-map-mask", + 0x1800, 0, 0, 0x7); +} + static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { @@ -203,7 +253,10 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, nodename = g_strdup_printf("/soc/interrupt-controller@%lx", (long)memmap[VIRT_PLIC].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1); + qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", + FDT_PLIC_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", + FDT_PLIC_INT_CELLS); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", @@ -233,6 +286,33 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, g_free(nodename); } + nodename = g_strdup_printf("/soc/pci@%lx", + (long) memmap[VIRT_PCIE_ECAM].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", + FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", + FDT_PCI_INT_CELLS); + qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "pci-host-ecam-generic"); + qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); + qemu_fdt_setprop_cell(fdt, nodename, "linux,pci-domain", 0); + qemu_fdt_setprop_cells(fdt, nodename, "bus-range", 0, + memmap[VIRT_PCIE_ECAM].base / + PCIE_MMCFG_SIZE_MIN - 1); + qemu_fdt_setprop(fdt, nodename, "dma-coherent", NULL, 0); + qemu_fdt_setprop_cells(fdt, nodename, "reg", 0, memmap[VIRT_PCIE_ECAM].base, + 0, memmap[VIRT_PCIE_ECAM].size); + qemu_fdt_setprop_sized_cells(fdt, nodename, "ranges", + 1, FDT_PCI_RANGE_IOPORT, 2, 0, + 2, memmap[VIRT_PCIE_PIO].base, 2, memmap[VIRT_PCIE_PIO].size, + 1, FDT_PCI_RANGE_MMIO, + 2, memmap[VIRT_PCIE_MMIO].base, + 2, memmap[VIRT_PCIE_MMIO].base, 2, memmap[VIRT_PCIE_MMIO].size); + create_pcie_irq_map(fdt, nodename, plic_phandle); + g_free(nodename); + nodename = g_strdup_printf("/test@%lx", (long)memmap[VIRT_TEST].base); qemu_fdt_add_subnode(fdt, nodename); @@ -263,6 +343,47 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, return fdt; } + +static inline DeviceState *gpex_pcie_init(MemoryRegion *sys_mem, + hwaddr ecam_base, hwaddr ecam_size, + hwaddr mmio_base, hwaddr mmio_size, + hwaddr pio_base, + DeviceState *plic, bool link_up) +{ + DeviceState *dev; + MemoryRegion *ecam_alias, *ecam_reg; + MemoryRegion *mmio_alias, *mmio_reg; + qemu_irq irq; + int i; + + dev = qdev_create(NULL, TYPE_GPEX_HOST); + + qdev_init_nofail(dev); + + ecam_alias = g_new0(MemoryRegion, 1); + ecam_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 0); + memory_region_init_alias(ecam_alias, OBJECT(dev), "pcie-ecam", + ecam_reg, 0, ecam_size); + memory_region_add_subregion(get_system_memory(), ecam_base, ecam_alias); + + mmio_alias = g_new0(MemoryRegion, 1); + mmio_reg = sysbus_mmio_get_region(SYS_BUS_DEVICE(dev), 1); + memory_region_init_alias(mmio_alias, OBJECT(dev), "pcie-mmio", + mmio_reg, mmio_base, mmio_size); + memory_region_add_subregion(get_system_memory(), mmio_base, mmio_alias); + + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 2, pio_base); + + for (i = 0; i < GPEX_NUM_IRQS; i++) { + irq = qdev_get_gpio_in(plic, PCIE_IRQ + i); + + sysbus_connect_irq(SYS_BUS_DEVICE(dev), i, irq); + gpex_set_irq_num(GPEX_HOST(dev), i, PCIE_IRQ + i); + } + + return dev; +} + static void riscv_virt_board_init(MachineState *machine) { const struct MemmapEntry *memmap = virt_memmap; @@ -385,6 +506,14 @@ static void riscv_virt_board_init(MachineState *machine) qdev_get_gpio_in(DEVICE(s->plic), VIRTIO_IRQ + i)); } + gpex_pcie_init(system_memory, + memmap[VIRT_PCIE_ECAM].base, + memmap[VIRT_PCIE_ECAM].size, + memmap[VIRT_PCIE_MMIO].base, + memmap[VIRT_PCIE_MMIO].size, + memmap[VIRT_PCIE_PIO].base, + DEVICE(s->plic), true); + serial_mm_init(system_memory, memmap[VIRT_UART0].base, 0, qdev_get_gpio_in(DEVICE(s->plic), UART0_IRQ), 399193, serial_hd(0), DEVICE_LITTLE_ENDIAN); diff --git a/include/elf.h b/include/elf.h index c151164b63..0ac7911b7b 100644 --- a/include/elf.h +++ b/include/elf.h @@ -1338,6 +1338,61 @@ typedef struct { #define R_IA64_DTPREL64LSB 0xb7 /* @dtprel(sym + add), data8 LSB */ #define R_IA64_LTOFF_DTPREL22 0xba /* @ltoff(@dtprel(s+a)), imm22 */ +/* RISC-V relocations. */ +#define R_RISCV_NONE 0 +#define R_RISCV_32 1 +#define R_RISCV_64 2 +#define R_RISCV_RELATIVE 3 +#define R_RISCV_COPY 4 +#define R_RISCV_JUMP_SLOT 5 +#define R_RISCV_TLS_DTPMOD32 6 +#define R_RISCV_TLS_DTPMOD64 7 +#define R_RISCV_TLS_DTPREL32 8 +#define R_RISCV_TLS_DTPREL64 9 +#define R_RISCV_TLS_TPREL32 10 +#define R_RISCV_TLS_TPREL64 11 +#define R_RISCV_BRANCH 16 +#define R_RISCV_JAL 17 +#define R_RISCV_CALL 18 +#define R_RISCV_CALL_PLT 19 +#define R_RISCV_GOT_HI20 20 +#define R_RISCV_TLS_GOT_HI20 21 +#define R_RISCV_TLS_GD_HI20 22 +#define R_RISCV_PCREL_HI20 23 +#define R_RISCV_PCREL_LO12_I 24 +#define R_RISCV_PCREL_LO12_S 25 +#define R_RISCV_HI20 26 +#define R_RISCV_LO12_I 27 +#define R_RISCV_LO12_S 28 +#define R_RISCV_TPREL_HI20 29 +#define R_RISCV_TPREL_LO12_I 30 +#define R_RISCV_TPREL_LO12_S 31 +#define R_RISCV_TPREL_ADD 32 +#define R_RISCV_ADD8 33 +#define R_RISCV_ADD16 34 +#define R_RISCV_ADD32 35 +#define R_RISCV_ADD64 36 +#define R_RISCV_SUB8 37 +#define R_RISCV_SUB16 38 +#define R_RISCV_SUB32 39 +#define R_RISCV_SUB64 40 +#define R_RISCV_GNU_VTINHERIT 41 +#define R_RISCV_GNU_VTENTRY 42 +#define R_RISCV_ALIGN 43 +#define R_RISCV_RVC_BRANCH 44 +#define R_RISCV_RVC_JUMP 45 +#define R_RISCV_RVC_LUI 46 +#define R_RISCV_GPREL_I 47 +#define R_RISCV_GPREL_S 48 +#define R_RISCV_TPREL_I 49 +#define R_RISCV_TPREL_S 50 +#define R_RISCV_RELAX 51 +#define R_RISCV_SUB6 52 +#define R_RISCV_SET6 53 +#define R_RISCV_SET8 54 +#define R_RISCV_SET16 55 +#define R_RISCV_SET32 56 + typedef struct elf32_rel { Elf32_Addr r_offset; Elf32_Word r_info; diff --git a/include/exec/helper-head.h b/include/exec/helper-head.h index 276dd5afce..ab4f8b6623 100644 --- a/include/exec/helper-head.h +++ b/include/exec/helper-head.h @@ -108,6 +108,19 @@ #define dh_is_signed_env dh_is_signed_ptr #define dh_is_signed(t) dh_is_signed_##t +#define dh_callflag_i32 0 +#define dh_callflag_s32 0 +#define dh_callflag_int 0 +#define dh_callflag_i64 0 +#define dh_callflag_s64 0 +#define dh_callflag_f16 0 +#define dh_callflag_f32 0 +#define dh_callflag_f64 0 +#define dh_callflag_ptr 0 +#define dh_callflag_void 0 +#define dh_callflag_noreturn TCG_CALL_NO_RETURN +#define dh_callflag(t) glue(dh_callflag_, dh_alias(t)) + #define dh_sizemask(t, n) \ ((dh_is_64bit(t) << (n*2)) | (dh_is_signed(t) << (n*2+1))) diff --git a/include/exec/helper-tcg.h b/include/exec/helper-tcg.h index b3bdb0c399..268e0f804b 100644 --- a/include/exec/helper-tcg.h +++ b/include/exec/helper-tcg.h @@ -11,36 +11,43 @@ #define str(s) #s #define DEF_HELPER_FLAGS_0(NAME, FLAGS, ret) \ - { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ + { .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) }, #define DEF_HELPER_FLAGS_1(NAME, FLAGS, ret, t1) \ - { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ + { .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) }, #define DEF_HELPER_FLAGS_2(NAME, FLAGS, ret, t1, t2) \ - { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ + { .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) }, #define DEF_HELPER_FLAGS_3(NAME, FLAGS, ret, t1, t2, t3) \ - { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ + { .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) }, #define DEF_HELPER_FLAGS_4(NAME, FLAGS, ret, t1, t2, t3, t4) \ - { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ + { .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) }, #define DEF_HELPER_FLAGS_5(NAME, FLAGS, ret, t1, t2, t3, t4, t5) \ - { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ + { .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) }, #define DEF_HELPER_FLAGS_6(NAME, FLAGS, ret, t1, t2, t3, t4, t5, t6) \ - { .func = HELPER(NAME), .name = str(NAME), .flags = FLAGS, \ + { .func = HELPER(NAME), .name = str(NAME), \ + .flags = FLAGS | dh_callflag(ret), \ .sizemask = dh_sizemask(ret, 0) | dh_sizemask(t1, 1) \ | dh_sizemask(t2, 2) | dh_sizemask(t3, 3) | dh_sizemask(t4, 4) \ | dh_sizemask(t5, 5) | dh_sizemask(t6, 6) }, diff --git a/include/exec/poison.h b/include/exec/poison.h index 32d53789f8..ecdc83c147 100644 --- a/include/exec/poison.h +++ b/include/exec/poison.h @@ -79,6 +79,7 @@ #pragma GCC poison CONFIG_MOXIE_DIS #pragma GCC poison CONFIG_NIOS2_DIS #pragma GCC poison CONFIG_PPC_DIS +#pragma GCC poison CONFIG_RISCV_DIS #pragma GCC poison CONFIG_S390_DIS #pragma GCC poison CONFIG_SH4_DIS #pragma GCC poison CONFIG_SPARC_DIS diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index e8b4d9ffa3..be13cc1304 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -63,7 +63,8 @@ enum { }; enum { - SIFIVE_U_CLOCK_FREQ = 1000000000 + SIFIVE_U_CLOCK_FREQ = 1000000000, + SIFIVE_U_GEM_CLOCK_FREQ = 125000000 }; #define SIFIVE_U_PLIC_HART_CONFIG "MS" diff --git a/include/hw/riscv/sifive_uart.h b/include/hw/riscv/sifive_uart.h index 504f18a60f..c8dc1c57fd 100644 --- a/include/hw/riscv/sifive_uart.h +++ b/include/hw/riscv/sifive_uart.h @@ -43,6 +43,9 @@ enum { SIFIVE_UART_IP_RXWM = 2 /* Receive watermark interrupt pending */ }; +#define SIFIVE_UART_GET_TXCNT(txctrl) ((txctrl >> 16) & 0x7) +#define SIFIVE_UART_GET_RXCNT(rxctrl) ((rxctrl >> 16) & 0x7) + #define TYPE_SIFIVE_UART "riscv.sifive.uart" #define SIFIVE_UART(obj) \ diff --git a/include/hw/riscv/virt.h b/include/hw/riscv/virt.h index 91163d6cbf..f12deaebd6 100644 --- a/include/hw/riscv/virt.h +++ b/include/hw/riscv/virt.h @@ -38,14 +38,18 @@ enum { VIRT_PLIC, VIRT_UART0, VIRT_VIRTIO, - VIRT_DRAM + VIRT_DRAM, + VIRT_PCIE_MMIO, + VIRT_PCIE_PIO, + VIRT_PCIE_ECAM }; enum { UART0_IRQ = 10, VIRTIO_IRQ = 1, /* 1 to 8 */ VIRTIO_COUNT = 8, - VIRTIO_NDEV = 10 + PCIE_IRQ = 0x20, /* 32 to 35 */ + VIRTIO_NDEV = 0x35 /* Arbitrary maximum number of interrupts */ }; enum { @@ -62,6 +66,13 @@ enum { #define VIRT_PLIC_CONTEXT_BASE 0x200000 #define VIRT_PLIC_CONTEXT_STRIDE 0x1000 +#define FDT_PCI_ADDR_CELLS 3 +#define FDT_PCI_INT_CELLS 1 +#define FDT_PLIC_ADDR_CELLS 0 +#define FDT_PLIC_INT_CELLS 1 +#define FDT_INT_MAP_WIDTH (FDT_PCI_ADDR_CELLS + FDT_PCI_INT_CELLS + 1 + \ + FDT_PLIC_ADDR_CELLS + FDT_PLIC_INT_CELLS) + #if defined(TARGET_RISCV32) #define VIRT_CPU TYPE_RISCV_CPU_RV32GCSU_V1_10_0 #elif defined(TARGET_RISCV64) diff --git a/include/qemu/atomic.h b/include/qemu/atomic.h index f6993a8fb1..a6ac188188 100644 --- a/include/qemu/atomic.h +++ b/include/qemu/atomic.h @@ -99,9 +99,10 @@ * those few cases by hand. * * Note that x32 is fully detected with __x86_64__ + _ILP32, and that for - * Sparc we always force the use of sparcv9 in configure. + * Sparc we always force the use of sparcv9 in configure. MIPS n32 (ILP32) & + * n64 (LP64) ABIs are both detected using __mips64. */ -#if defined(__x86_64__) || defined(__sparc__) +#if defined(__x86_64__) || defined(__sparc__) || defined(__mips64) # define ATOMIC_REG_SIZE 8 #else # define ATOMIC_REG_SIZE sizeof(void *) diff --git a/include/sysemu/sysemu.h b/include/sysemu/sysemu.h index e0d15da937..85877b7e43 100644 --- a/include/sysemu/sysemu.h +++ b/include/sysemu/sysemu.h @@ -116,7 +116,6 @@ extern uint8_t *boot_splash_filedata; extern size_t boot_splash_filedata_size; extern bool enable_mlock; extern bool enable_cpu_pm; -extern uint8_t qemu_extra_params_fw[2]; extern QEMUClockType rtc_clock; extern const char *mem_path; extern int mem_prealloc; diff --git a/linux-user/host/riscv32/hostdep.h b/linux-user/host/riscv32/hostdep.h new file mode 100644 index 0000000000..adf9edbf2d --- /dev/null +++ b/linux-user/host/riscv32/hostdep.h @@ -0,0 +1,11 @@ +/* + * hostdep.h : things which are dependent on the host architecture + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef RISCV32_HOSTDEP_H +#define RISCV32_HOSTDEP_H + +#endif diff --git a/linux-user/host/riscv64/hostdep.h b/linux-user/host/riscv64/hostdep.h new file mode 100644 index 0000000000..865f0fb9ff --- /dev/null +++ b/linux-user/host/riscv64/hostdep.h @@ -0,0 +1,34 @@ +/* + * hostdep.h : things which are dependent on the host architecture + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef RISCV64_HOSTDEP_H +#define RISCV64_HOSTDEP_H + +/* We have a safe-syscall.inc.S */ +#define HAVE_SAFE_SYSCALL + +#ifndef __ASSEMBLER__ + +/* These are defined by the safe-syscall.inc.S file */ +extern char safe_syscall_start[]; +extern char safe_syscall_end[]; + +/* Adjust the signal context to rewind out of safe-syscall if we're in it */ +static inline void rewind_if_in_safe_syscall(void *puc) +{ + ucontext_t *uc = puc; + unsigned long *pcreg = &uc->uc_mcontext.__gregs[REG_PC]; + + if (*pcreg > (uintptr_t)safe_syscall_start + && *pcreg < (uintptr_t)safe_syscall_end) { + *pcreg = (uintptr_t)safe_syscall_start; + } +} + +#endif /* __ASSEMBLER__ */ + +#endif diff --git a/linux-user/host/riscv64/safe-syscall.inc.S b/linux-user/host/riscv64/safe-syscall.inc.S new file mode 100644 index 0000000000..9ca3fbfd1e --- /dev/null +++ b/linux-user/host/riscv64/safe-syscall.inc.S @@ -0,0 +1,77 @@ +/* + * safe-syscall.inc.S : host-specific assembly fragment + * to handle signals occurring at the same time as system calls. + * This is intended to be included by linux-user/safe-syscall.S + * + * Written by Richard Henderson <rth@twiddle.net> + * Copyright (C) 2018 Linaro, Inc. + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + + .global safe_syscall_base + .global safe_syscall_start + .global safe_syscall_end + .type safe_syscall_base, @function + .type safe_syscall_start, @function + .type safe_syscall_end, @function + + /* + * This is the entry point for making a system call. The calling + * convention here is that of a C varargs function with the + * first argument an 'int *' to the signal_pending flag, the + * second one the system call number (as a 'long'), and all further + * arguments being syscall arguments (also 'long'). + * We return a long which is the syscall's return value, which + * may be negative-errno on failure. Conversion to the + * -1-and-errno-set convention is done by the calling wrapper. + */ +safe_syscall_base: + .cfi_startproc + /* + * The syscall calling convention is nearly the same as C: + * we enter with a0 == *signal_pending + * a1 == syscall number + * a2 ... a7 == syscall arguments + * and return the result in a0 + * and the syscall instruction needs + * a7 == syscall number + * a0 ... a5 == syscall arguments + * and returns the result in a0 + * Shuffle everything around appropriately. + */ + mv t0, a0 /* signal_pending pointer */ + mv t1, a1 /* syscall number */ + mv a0, a2 /* syscall arguments */ + mv a1, a3 + mv a2, a4 + mv a3, a5 + mv a4, a6 + mv a5, a7 + mv a7, t1 + + /* + * This next sequence of code works in conjunction with the + * rewind_if_safe_syscall_function(). If a signal is taken + * and the interrupted PC is anywhere between 'safe_syscall_start' + * and 'safe_syscall_end' then we rewind it to 'safe_syscall_start'. + * The code sequence must therefore be able to cope with this, and + * the syscall instruction must be the final one in the sequence. + */ +safe_syscall_start: + /* If signal_pending is non-zero, don't do the call */ + lw t1, 0(t0) + bnez t1, 0f + scall +safe_syscall_end: + /* code path for having successfully executed the syscall */ + ret + +0: + /* code path when we didn't execute the syscall */ + li a0, -TARGET_ERESTARTSYS + ret + .cfi_endproc + + .size safe_syscall_base, .-safe_syscall_base diff --git a/target/mips/translate.c b/target/mips/translate.c index e9c23a594b..2636e8c022 100644 --- a/target/mips/translate.c +++ b/target/mips/translate.c @@ -1399,10 +1399,12 @@ enum { /* - * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET - * ============================================ * - * MXU (full name: MIPS eXtension/enhanced Unit) is an SIMD extension of MIPS32 + * AN OVERVIEW OF MXU EXTENSION INSTRUCTION SET + * ============================================ + * + * + * MXU (full name: MIPS eXtension/enhanced Unit) is a SIMD extension of MIPS32 * instructions set. It is designed to fit the needs of signal, graphical and * video processing applications. MXU instruction set is used in Xburst family * of microprocessors by Ingenic. @@ -1410,39 +1412,31 @@ enum { * MXU unit contains 17 registers called X0-X16. X0 is always zero, and X16 is * the control register. * - * The notation used in MXU assembler mnemonics - * -------------------------------------------- * - * Registers: + * The notation used in MXU assembler mnemonics + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * Register operands: * * XRa, XRb, XRc, XRd - MXU registers * Rb, Rc, Rd, Rs, Rt - general purpose MIPS registers * - * Subfields: + * Non-register operands: * - * aptn1 - 1-bit accumulate add/subtract pattern - * aptn2 - 2-bit accumulate add/subtract pattern - * eptn2 - 2-bit execute add/subtract pattern - * optn2 - 2-bit operand pattern - * optn3 - 3-bit operand pattern - * sft4 - 4-bit shift amount - * strd2 - 2-bit stride amount + * aptn1 - 1-bit accumulate add/subtract pattern + * aptn2 - 2-bit accumulate add/subtract pattern + * eptn2 - 2-bit execute add/subtract pattern + * optn2 - 2-bit operand pattern + * optn3 - 3-bit operand pattern + * sft4 - 4-bit shift amount + * strd2 - 2-bit stride amount * * Prefixes: * - * <Operation parallel level><Operand size> - * S 32 - * D 16 - * Q 8 - * - * Suffixes: - * - * E - Expand results - * F - Fixed point multiplication - * L - Low part result - * R - Doing rounding - * V - Variable instead of immediate - * W - Combine above L and V + * Level of parallelism: Operand size: + * S - single operation at a time 32 - word + * D - two operations in parallel 16 - half word + * Q - four operations in parallel 8 - byte * * Operations: * @@ -1486,6 +1480,19 @@ enum { * SCOP - Calculate x’s scope (-1, means x<0; 0, means x==0; 1, means x>0) * XOR - Logical bitwise 'exclusive or' operation * + * Suffixes: + * + * E - Expand results + * F - Fixed point multiplication + * L - Low part result + * R - Doing rounding + * V - Variable instead of immediate + * W - Combine above L and V + * + * + * The list of MXU instructions grouped by functionality + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * * Load/Store instructions Multiplication instructions * ----------------------- --------------------------- * @@ -1563,6 +1570,13 @@ enum { * Q16SAT XRa, XRb, XRc S32I2M XRa, Rb * * + * The opcode organization of MXU instructions + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * The bits 31..26 of all MXU instructions are equal to 0x1C (also referred + * as opcode SPECIAL2 in the base MIPS ISA). The organization and meaning of + * other bits up to the instruction level is as follows: + * * bits * 05..00 * @@ -1663,12 +1677,21 @@ enum { * │ 20..18 * ├─ 100111 ─ OPC_MXU__POOL16 ─┬─ 000 ─ OPC_MXU_D32SARW * │ ├─ 001 ─ OPC_MXU_S32ALN - * ├─ 101000 ─ OPC_MXU_LXB ├─ 010 ─ OPC_MXU_S32ALNI - * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_S32NOR - * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_S32AND - * ├─ 101011 ─ OPC_MXU_S16STD ├─ 101 ─ OPC_MXU_S32OR - * ├─ 101100 ─ OPC_MXU_S16LDI ├─ 110 ─ OPC_MXU_S32XOR - * ├─ 101101 ─ OPC_MXU_S16SDI └─ 111 ─ OPC_MXU_S32LUI + * │ ├─ 010 ─ OPC_MXU_S32ALNI + * │ ├─ 011 ─ OPC_MXU_S32LUI + * │ ├─ 100 ─ OPC_MXU_S32NOR + * │ ├─ 101 ─ OPC_MXU_S32AND + * │ ├─ 110 ─ OPC_MXU_S32OR + * │ └─ 111 ─ OPC_MXU_S32XOR + * │ + * │ 7..5 + * ├─ 101000 ─ OPC_MXU__POOL17 ─┬─ 000 ─ OPC_MXU_LXB + * │ ├─ 001 ─ OPC_MXU_LXH + * ├─ 101001 ─ <not assigned> ├─ 011 ─ OPC_MXU_LXW + * ├─ 101010 ─ OPC_MXU_S16LDD ├─ 100 ─ OPC_MXU_LXBU + * ├─ 101011 ─ OPC_MXU_S16STD └─ 101 ─ OPC_MXU_LXHU + * ├─ 101100 ─ OPC_MXU_S16LDI + * ├─ 101101 ─ OPC_MXU_S16SDI * ├─ 101110 ─ OPC_MXU_S32M2I * ├─ 101111 ─ OPC_MXU_S32I2M * ├─ 110000 ─ OPC_MXU_D32SLL @@ -1678,23 +1701,23 @@ enum { * ├─ 110100 ─ OPC_MXU_Q16SLL ├─ 010 ─ OPC_MXU_D32SARV * ├─ 110101 ─ OPC_MXU_Q16SLR ├─ 011 ─ OPC_MXU_Q16SLLV * │ ├─ 100 ─ OPC_MXU_Q16SLRV - * ├─ 110110 ─ OPC_MXU__POOL17 ─┴─ 101 ─ OPC_MXU_Q16SARV + * ├─ 110110 ─ OPC_MXU__POOL18 ─┴─ 101 ─ OPC_MXU_Q16SARV * │ * ├─ 110111 ─ OPC_MXU_Q16SAR * │ 23..22 - * ├─ 111000 ─ OPC_MXU__POOL18 ─┬─ 00 ─ OPC_MXU_Q8MUL + * ├─ 111000 ─ OPC_MXU__POOL19 ─┬─ 00 ─ OPC_MXU_Q8MUL * │ └─ 01 ─ OPC_MXU_Q8MULSU * │ * │ 20..18 - * ├─ 111001 ─ OPC_MXU__POOL19 ─┬─ 000 ─ OPC_MXU_Q8MOVZ + * ├─ 111001 ─ OPC_MXU__POOL20 ─┬─ 000 ─ OPC_MXU_Q8MOVZ * │ ├─ 001 ─ OPC_MXU_Q8MOVN * │ ├─ 010 ─ OPC_MXU_D16MOVZ * │ ├─ 011 ─ OPC_MXU_D16MOVN * │ ├─ 100 ─ OPC_MXU_S32MOVZ - * │ └─ 101 ─ OPC_MXU_S32MOV + * │ └─ 101 ─ OPC_MXU_S32MOVN * │ * │ 23..22 - * ├─ 111010 ─ OPC_MXU__POOL20 ─┬─ 00 ─ OPC_MXU_Q8MAC + * ├─ 111010 ─ OPC_MXU__POOL21 ─┬─ 00 ─ OPC_MXU_Q8MAC * │ └─ 10 ─ OPC_MXU_Q8MACSU * ├─ 111011 ─ OPC_MXU_Q16SCOP * ├─ 111100 ─ OPC_MXU_Q8MADL @@ -1703,10 +1726,10 @@ enum { * └─ 111111 ─ <not assigned> (overlaps with SDBBP) * * - * Compiled after: + * Compiled after: * * "XBurst® Instruction Set Architecture MIPS eXtension/enhanced Unit - * Programming Manual", Ingenic Semiconductor Co, Ltd., 2017 + * Programming Manual", Ingenic Semiconductor Co, Ltd., revision June 2, 2017 */ enum { @@ -1750,7 +1773,7 @@ enum { OPC_MXU_S8SDI = 0x25, OPC_MXU__POOL15 = 0x26, OPC_MXU__POOL16 = 0x27, - OPC_MXU_LXB = 0x28, + OPC_MXU__POOL17 = 0x28, /* not assigned 0x29 */ OPC_MXU_S16LDD = 0x2A, OPC_MXU_S16STD = 0x2B, @@ -1764,11 +1787,11 @@ enum { OPC_MXU_D32SAR = 0x33, OPC_MXU_Q16SLL = 0x34, OPC_MXU_Q16SLR = 0x35, - OPC_MXU__POOL17 = 0x36, + OPC_MXU__POOL18 = 0x36, OPC_MXU_Q16SAR = 0x37, - OPC_MXU__POOL18 = 0x38, - OPC_MXU__POOL19 = 0x39, - OPC_MXU__POOL20 = 0x3A, + OPC_MXU__POOL19 = 0x38, + OPC_MXU__POOL20 = 0x39, + OPC_MXU__POOL21 = 0x3A, OPC_MXU_Q16SCOP = 0x3B, OPC_MXU_Q8MADL = 0x3C, OPC_MXU_S32SFL = 0x3D, @@ -1930,17 +1953,28 @@ enum { OPC_MXU_D32SARW = 0x00, OPC_MXU_S32ALN = 0x01, OPC_MXU_S32ALNI = 0x02, - OPC_MXU_S32NOR = 0x03, - OPC_MXU_S32AND = 0x04, - OPC_MXU_S32OR = 0x05, - OPC_MXU_S32XOR = 0x06, - OPC_MXU_S32LUI = 0x07, + OPC_MXU_S32LUI = 0x03, + OPC_MXU_S32NOR = 0x04, + OPC_MXU_S32AND = 0x05, + OPC_MXU_S32OR = 0x06, + OPC_MXU_S32XOR = 0x07, }; /* * MXU pool 17 */ enum { + OPC_MXU_LXB = 0x00, + OPC_MXU_LXH = 0x01, + OPC_MXU_LXW = 0x03, + OPC_MXU_LXBU = 0x04, + OPC_MXU_LXHU = 0x05, +}; + +/* + * MXU pool 18 + */ +enum { OPC_MXU_D32SLLV = 0x00, OPC_MXU_D32SLRV = 0x01, OPC_MXU_D32SARV = 0x03, @@ -1950,7 +1984,7 @@ enum { }; /* - * MXU pool 18 + * MXU pool 19 */ enum { OPC_MXU_Q8MUL = 0x00, @@ -1958,7 +1992,7 @@ enum { }; /* - * MXU pool 19 + * MXU pool 20 */ enum { OPC_MXU_Q8MOVZ = 0x00, @@ -1970,7 +2004,7 @@ enum { }; /* - * MXU pool 20 + * MXU pool 21 */ enum { OPC_MXU_Q8MAC = 0x00, @@ -2421,9 +2455,11 @@ static TCGv_i32 fpu_fcr0, fpu_fcr31; static TCGv_i64 fpu_f64[32]; static TCGv_i64 msa_wr_d[64]; +#if !defined(TARGET_MIPS64) /* MXU registers */ static TCGv mxu_gpr[NUMBER_OF_MXU_REGISTERS - 1]; static TCGv mxu_CR; +#endif #include "exec/gen-icount.h" @@ -2547,10 +2583,12 @@ static const char * const msaregnames[] = { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; +#if !defined(TARGET_MIPS64) static const char * const mxuregnames[] = { "XR1", "XR2", "XR3", "XR4", "XR5", "XR6", "XR7", "XR8", "XR9", "XR10", "XR11", "XR12", "XR13", "XR14", "XR15", "MXU_CR", }; +#endif #define LOG_DISAS(...) \ do { \ @@ -2633,6 +2671,7 @@ static inline void gen_store_srsgpr (int from, int to) } } +#if !defined(TARGET_MIPS64) /* MXU General purpose registers moves. */ static inline void gen_load_mxu_gpr(TCGv t, unsigned int reg) { @@ -2661,6 +2700,7 @@ static inline void gen_store_mxu_cr(TCGv t) /* TODO: Add handling of RW rules for MXU_CR. */ tcg_gen_mov_tl(mxu_CR, t); } +#endif /* Tests */ @@ -4993,8 +5033,8 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, } /* - * These MULT and MULTU instructions implemented in for example the - * Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core + * These MULT[U] and MADD[U] instructions implemented in for example + * the Toshiba/Sony R5900 and the Toshiba TX19, TX39 and TX79 core * architectures are special three-operand variants with the syntax * * MULT[U][1] rd, rs, rt @@ -5003,6 +5043,14 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, * * (rd, LO, HI) <- rs * rt * + * and + * + * MADD[U][1] rd, rs, rt + * + * such that + * + * (rd, LO, HI) <- (LO, HI) + rs * rt + * * where the low-order 32-bits of the result is placed into both the * GPR rd and the special register LO. The high-order 32-bits of the * result is placed into the special register HI. @@ -5059,8 +5107,54 @@ static void gen_mul_txx9(DisasContext *ctx, uint32_t opc, tcg_temp_free_i32(t3); } break; + case MMI_OPC_MADD1: + acc = 1; + /* Fall through */ + case MMI_OPC_MADD: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext_tl_i64(t2, t0); + tcg_gen_ext_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); + if (rd) { + gen_move_low32(cpu_gpr[rd], t2); + } + tcg_temp_free_i64(t2); + } + break; + case MMI_OPC_MADDU1: + acc = 1; + /* Fall through */ + case MMI_OPC_MADDU: + { + TCGv_i64 t2 = tcg_temp_new_i64(); + TCGv_i64 t3 = tcg_temp_new_i64(); + + tcg_gen_ext32u_tl(t0, t0); + tcg_gen_ext32u_tl(t1, t1); + tcg_gen_extu_tl_i64(t2, t0); + tcg_gen_extu_tl_i64(t3, t1); + tcg_gen_mul_i64(t2, t2, t3); + tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); + tcg_gen_add_i64(t2, t2, t3); + tcg_temp_free_i64(t3); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); + if (rd) { + gen_move_low32(cpu_gpr[rd], t2); + } + tcg_temp_free_i64(t2); + } + break; default: - MIPS_INVAL("mul TXx9"); + MIPS_INVAL("mul/madd TXx9"); generate_exception_end(ctx, EXCP_RI); goto out; } @@ -24201,6 +24295,8 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) } +#if !defined(TARGET_MIPS64) + /* MXU accumulate add/subtract 1-bit pattern 'aptn1' */ #define MXU_APTN1_A 0 #define MXU_APTN1_S 1 @@ -24218,6 +24314,11 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) #define MXU_EPTN2_SS 3 /* MXU operand getting pattern 'optn2' */ +#define MXU_OPTN2_PTN0 0 +#define MXU_OPTN2_PTN1 1 +#define MXU_OPTN2_PTN2 2 +#define MXU_OPTN2_PTN3 3 +/* alternative naming scheme for 'optn2' */ #define MXU_OPTN2_WW 0 #define MXU_OPTN2_LW 1 #define MXU_OPTN2_HW 2 @@ -24611,6 +24712,641 @@ static void gen_mxu_s32ldd_s32lddr(DisasContext *ctx) /* + * MXU instruction category: logic + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32NOR S32AND S32OR S32XOR + */ + +/* + * S32NOR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'nor' operation + * applied to the content of XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32NOR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad = extract32(ctx->opcode, 21, 5); + XRc = extract32(ctx->opcode, 14, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRa = extract32(ctx->opcode, 6, 4); + + if (unlikely(pad != 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa == 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb == 0) && (XRc == 0))) { + /* both operands zero registers -> just set destination to all 1s */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0xFFFFFFFF); + } else if (unlikely(XRb == 0)) { + /* XRb zero register -> just set destination to the negation of XRc */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc == 0)) { + /* XRa zero register -> just set destination to the negation of XRb */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb == XRc)) { + /* both operands same -> just set destination to the negation of XRb */ + tcg_gen_not_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_nor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]); + } +} + +/* + * S32AND XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'and' operation + * applied to the content of XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32AND(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad = extract32(ctx->opcode, 21, 5); + XRc = extract32(ctx->opcode, 14, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRa = extract32(ctx->opcode, 6, 4); + + if (unlikely(pad != 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa == 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb == 0) || (XRc == 0))) { + /* one of operands zero register -> just set destination to all 0s */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb == XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_and_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]); + } +} + +/* + * S32OR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'or' operation + * applied to the content of XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32OR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad = extract32(ctx->opcode, 21, 5); + XRc = extract32(ctx->opcode, 14, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRa = extract32(ctx->opcode, 6, 4); + + if (unlikely(pad != 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa == 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb == 0) && (XRc == 0))) { + /* both operands zero registers -> just set destination to all 0s */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb == 0)) { + /* XRb zero register -> just set destination to the content of XRc */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc == 0)) { + /* XRc zero register -> just set destination to the content of XRb */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb == XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]); + } +} + +/* + * S32XOR XRa, XRb, XRc + * Update XRa with the result of logical bitwise 'xor' operation + * applied to the content of XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32XOR(DisasContext *ctx) +{ + uint32_t pad, XRc, XRb, XRa; + + pad = extract32(ctx->opcode, 21, 5); + XRc = extract32(ctx->opcode, 14, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRa = extract32(ctx->opcode, 6, 4); + + if (unlikely(pad != 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa == 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb == 0) && (XRc == 0))) { + /* both operands zero registers -> just set destination to all 0s */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb == 0)) { + /* XRb zero register -> just set destination to the content of XRc */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } else if (unlikely(XRc == 0)) { + /* XRc zero register -> just set destination to the content of XRb */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else if (unlikely(XRb == XRc)) { + /* both operands same -> just set destination to all 0s */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else { + /* the most general case */ + tcg_gen_xor_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], mxu_gpr[XRc - 1]); + } +} + + +/* + * MXU instruction category max/min + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32MAX D16MAX Q8MAX + * S32MIN D16MIN Q8MIN + */ + +/* + * S32MAX XRa, XRb, XRc + * Update XRa with the maximum of signed 32-bit integers contained + * in XRb and XRc. + * + * S32MIN XRa, XRb, XRc + * Update XRa with the minimum of signed 32-bit integers contained + * in XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_S32MAX_S32MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad = extract32(ctx->opcode, 21, 5); + opc = extract32(ctx->opcode, 18, 3); + XRc = extract32(ctx->opcode, 14, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRa = extract32(ctx->opcode, 6, 4); + + if (unlikely(pad != 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa == 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb == 0) && (XRc == 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely((XRb == 0) || (XRc == 0))) { + /* exactly one operand is zero register - find which one is not...*/ + uint32_t XRx = XRb ? XRb : XRc; + /* ...and do max/min operation with one operand 0 */ + if (opc == OPC_MXU_S32MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRx - 1], 0); + } + } else if (unlikely(XRb == XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + if (opc == OPC_MXU_S32MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], + mxu_gpr[XRc - 1]); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], + mxu_gpr[XRc - 1]); + } + } +} + +/* + * D16MAX + * Update XRa with the 16-bit-wise maximums of signed integers + * contained in XRb and XRc. + * + * D16MIN + * Update XRa with the 16-bit-wise minimums of signed integers + * contained in XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_D16MAX_D16MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad = extract32(ctx->opcode, 21, 5); + opc = extract32(ctx->opcode, 18, 3); + XRc = extract32(ctx->opcode, 14, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRa = extract32(ctx->opcode, 6, 4); + + if (unlikely(pad != 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRc == 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb == 0) && (XRa == 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRc - 1], 0); + } else if (unlikely((XRb == 0) || (XRa == 0))) { + /* exactly one operand is zero register - find which one is not...*/ + uint32_t XRx = XRb ? XRb : XRc; + /* ...and do half-word-wise max/min with one operand 0 */ + TCGv_i32 t0 = tcg_temp_new(); + TCGv_i32 t1 = tcg_const_i32(0); + + /* the left half-word first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFFFF0000); + if (opc == OPC_MXU_D16MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* the right half-word */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0x0000FFFF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc == OPC_MXU_D16MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting half-words to its original position */ + tcg_gen_shri_i32(t0, t0, 16); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } else if (unlikely(XRb == XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + TCGv_i32 t0 = tcg_temp_new(); + TCGv_i32 t1 = tcg_temp_new(); + + /* the left half-word first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFFFF0000); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); + if (opc == OPC_MXU_D16MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* the right half-word */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0x0000FFFF); + /* move half-words to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 16); + tcg_gen_shli_i32(t1, t1, 16); + /* t0 will be max/min of t0 and t1 */ + if (opc == OPC_MXU_D16MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting half-words to its original position */ + tcg_gen_shri_i32(t0, t0, 16); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } +} + +/* + * Q8MAX + * Update XRa with the 8-bit-wise maximums of signed integers + * contained in XRb and XRc. + * + * Q8MIN + * Update XRa with the 8-bit-wise minimums of signed integers + * contained in XRb and XRc. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0| opc | XRc | XRb | XRa |MXU__POOL00| + * +-----------+---------+-----+-------+-------+-------+-----------+ + */ +static void gen_mxu_Q8MAX_Q8MIN(DisasContext *ctx) +{ + uint32_t pad, opc, XRc, XRb, XRa; + + pad = extract32(ctx->opcode, 21, 5); + opc = extract32(ctx->opcode, 18, 3); + XRc = extract32(ctx->opcode, 14, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRa = extract32(ctx->opcode, 6, 4); + + if (unlikely(pad != 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa == 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb == 0) && (XRc == 0))) { + /* both operands zero registers -> just set destination to zero */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely((XRb == 0) || (XRc == 0))) { + /* exactly one operand is zero register - make it be the first...*/ + uint32_t XRx = XRb ? XRb : XRc; + /* ...and do byte-wise max/min with one operand 0 */ + TCGv_i32 t0 = tcg_temp_new(); + TCGv_i32 t1 = tcg_const_i32(0); + int32_t i; + + /* the leftmost byte (byte 3) first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF000000); + if (opc == OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* bytes 2, 1, 0 */ + for (i = 2; i >= 0; i--) { + /* extract the byte */ + tcg_gen_andi_i32(t0, mxu_gpr[XRx - 1], 0xFF << (8 * i)); + /* move the byte to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); + /* t0 will be max/min of t0 and t1 */ + if (opc == OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + } + + tcg_temp_free(t1); + tcg_temp_free(t0); + } else if (unlikely(XRb == XRc)) { + /* both operands same -> just set destination to one of them */ + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } else { + /* the most general case */ + TCGv_i32 t0 = tcg_temp_new(); + TCGv_i32 t1 = tcg_temp_new(); + int32_t i; + + /* the leftmost bytes (bytes 3) first */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF000000); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); + if (opc == OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(mxu_gpr[XRa - 1], t0, t1); + } else { + tcg_gen_smin_i32(mxu_gpr[XRa - 1], t0, t1); + } + + /* bytes 2, 1, 0 */ + for (i = 2; i >= 0; i--) { + /* extract corresponding bytes */ + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0xFF << (8 * i)); + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF << (8 * i)); + /* move the bytes to the leftmost position */ + tcg_gen_shli_i32(t0, t0, 8 * (3 - i)); + tcg_gen_shli_i32(t1, t1, 8 * (3 - i)); + /* t0 will be max/min of t0 and t1 */ + if (opc == OPC_MXU_Q8MAX) { + tcg_gen_smax_i32(t0, t0, t1); + } else { + tcg_gen_smin_i32(t0, t0, t1); + } + /* return resulting byte to its original position */ + tcg_gen_shri_i32(t0, t0, 8 * (3 - i)); + /* finaly update the destination */ + tcg_gen_or_i32(mxu_gpr[XRa - 1], mxu_gpr[XRa - 1], t0); + } + + tcg_temp_free(t1); + tcg_temp_free(t0); + } +} + + +/* + * MXU instruction category: align + * ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~ + * + * S32ALN S32ALNI + */ + +/* + * S32ALNI XRc, XRb, XRa, optn3 + * Arrange bytes from XRb and XRc according to one of five sets of + * rules determined by optn3, and place the result in XRa. + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+-----+---+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |optn3|0 0|x x x| XRc | XRb | XRa |MXU__POOL16| + * +-----------+-----+---+-----+-------+-------+-------+-----------+ + * + */ +static void gen_mxu_S32ALNI(DisasContext *ctx) +{ + uint32_t optn3, pad, XRc, XRb, XRa; + + optn3 = extract32(ctx->opcode, 23, 3); + pad = extract32(ctx->opcode, 21, 2); + XRc = extract32(ctx->opcode, 14, 4); + XRb = extract32(ctx->opcode, 10, 4); + XRa = extract32(ctx->opcode, 6, 4); + + if (unlikely(pad != 0)) { + /* opcode padding incorrect -> do nothing */ + } else if (unlikely(XRa == 0)) { + /* destination is zero register -> do nothing */ + } else if (unlikely((XRb == 0) && (XRc == 0))) { + /* both operands zero registers -> just set destination to all 0s */ + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + } else if (unlikely(XRb == 0)) { + /* XRb zero register -> just appropriatelly shift XRc into XRa */ + switch (optn3) { + case MXU_OPTN3_PTN0: + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1], + 8 * (4 - optn3)); + break; + case MXU_OPTN3_PTN4: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + break; + } + } else if (unlikely(XRc == 0)) { + /* XRc zero register -> just appropriatelly shift XRb into XRa */ + switch (optn3) { + case MXU_OPTN3_PTN0: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_shri_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3); + break; + case MXU_OPTN3_PTN4: + tcg_gen_movi_i32(mxu_gpr[XRa - 1], 0); + break; + } + } else if (unlikely(XRb == XRc)) { + /* both operands same -> just rotation or moving from any of them */ + switch (optn3) { + case MXU_OPTN3_PTN0: + case MXU_OPTN3_PTN4: + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + break; + case MXU_OPTN3_PTN1: + case MXU_OPTN3_PTN2: + case MXU_OPTN3_PTN3: + tcg_gen_rotli_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1], 8 * optn3); + break; + } + } else { + /* the most general case */ + switch (optn3) { + case MXU_OPTN3_PTN0: + { + /* */ + /* XRb XRc */ + /* +---------------+ */ + /* | A B C D | E F G H */ + /* +-------+-------+ */ + /* | */ + /* XRa */ + /* */ + + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRb - 1]); + } + break; + case MXU_OPTN3_PTN1: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A | B C D E | F G H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 = tcg_temp_new(); + TCGv_i32 t1 = tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x00FFFFFF); + tcg_gen_shli_i32(t0, t0, 8); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFF000000); + tcg_gen_shri_i32(t1, t1, 24); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN2: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A B | C D E F | G H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 = tcg_temp_new(); + TCGv_i32 t1 = tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x0000FFFF); + tcg_gen_shli_i32(t0, t0, 16); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFF0000); + tcg_gen_shri_i32(t1, t1, 16); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN3: + { + /* */ + /* XRb XRc */ + /* +-------------------+ */ + /* A B C | D E F G | H */ + /* +---------+---------+ */ + /* | */ + /* XRa */ + /* */ + + TCGv_i32 t0 = tcg_temp_new(); + TCGv_i32 t1 = tcg_temp_new(); + + tcg_gen_andi_i32(t0, mxu_gpr[XRb - 1], 0x000000FF); + tcg_gen_shli_i32(t0, t0, 24); + + tcg_gen_andi_i32(t1, mxu_gpr[XRc - 1], 0xFFFFFF00); + tcg_gen_shri_i32(t1, t1, 8); + + tcg_gen_or_i32(mxu_gpr[XRa - 1], t0, t1); + + tcg_temp_free(t1); + tcg_temp_free(t0); + } + break; + case MXU_OPTN3_PTN4: + { + /* */ + /* XRb XRc */ + /* +---------------+ */ + /* A B C D | E F G H | */ + /* +-------+-------+ */ + /* | */ + /* XRa */ + /* */ + + tcg_gen_mov_i32(mxu_gpr[XRa - 1], mxu_gpr[XRc - 1]); + } + break; + } + } +} + + +/* * Decoding engine for MXU * ======================= */ @@ -24631,34 +25367,16 @@ static void decode_opc_mxu__pool00(CPUMIPSState *env, DisasContext *ctx) switch (opcode) { case OPC_MXU_S32MAX: - /* TODO: Implement emulation of S32MAX instruction. */ - MIPS_INVAL("OPC_MXU_S32MAX"); - generate_exception_end(ctx, EXCP_RI); - break; case OPC_MXU_S32MIN: - /* TODO: Implement emulation of S32MIN instruction. */ - MIPS_INVAL("OPC_MXU_S32MIN"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32MAX_S32MIN(ctx); break; case OPC_MXU_D16MAX: - /* TODO: Implement emulation of D16MAX instruction. */ - MIPS_INVAL("OPC_MXU_D16MAX"); - generate_exception_end(ctx, EXCP_RI); - break; case OPC_MXU_D16MIN: - /* TODO: Implement emulation of D16MIN instruction. */ - MIPS_INVAL("OPC_MXU_D16MIN"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_D16MAX_D16MIN(ctx); break; case OPC_MXU_Q8MAX: - /* TODO: Implement emulation of Q8MAX instruction. */ - MIPS_INVAL("OPC_MXU_Q8MAX"); - generate_exception_end(ctx, EXCP_RI); - break; case OPC_MXU_Q8MIN: - /* TODO: Implement emulation of Q8MIN instruction. */ - MIPS_INVAL("OPC_MXU_Q8MIN"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_Q8MAX_Q8MIN(ctx); break; case OPC_MXU_Q8SLT: /* TODO: Implement emulation of Q8SLT instruction. */ @@ -25261,18 +25979,18 @@ static void decode_opc_mxu__pool15(CPUMIPSState *env, DisasContext *ctx) * | SPECIAL2 | s3 |0 0|x x x| XRc | XRb | XRa |MXU__POOL16| * +-----------+-----+---+-----+-------+-------+-------+-----------+ * - * S32NOR, S32AND, S32OR, S32XOR: - * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 - * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL16| - * +-----------+---------+-----+-------+-------+-------+-----------+ - * * S32LUI: * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-----------+-----+---+-----+-------+---------------+-----------+ * | SPECIAL2 |optn3|0 0|x x x| XRc | s8 |MXU__POOL16| * +-----------+-----+---+-----+-------+---------------+-----------+ * + * S32NOR, S32AND, S32OR, S32XOR: + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+-----+-------+-------+-------+-----------+ + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL16| + * +-----------+---------+-----+-------+-------+-------+-----------+ + * */ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) { @@ -25290,33 +26008,70 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) generate_exception_end(ctx, EXCP_RI); break; case OPC_MXU_S32ALNI: - /* TODO: Implement emulation of S32ALNI instruction. */ - MIPS_INVAL("OPC_MXU_S32ALNI"); + gen_mxu_S32ALNI(ctx); + break; + case OPC_MXU_S32LUI: + /* TODO: Implement emulation of S32LUI instruction. */ + MIPS_INVAL("OPC_MXU_S32LUI"); generate_exception_end(ctx, EXCP_RI); break; case OPC_MXU_S32NOR: - /* TODO: Implement emulation of S32NOR instruction. */ - MIPS_INVAL("OPC_MXU_S32NOR"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32NOR(ctx); break; case OPC_MXU_S32AND: - /* TODO: Implement emulation of S32AND instruction. */ - MIPS_INVAL("OPC_MXU_S32AND"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32AND(ctx); break; case OPC_MXU_S32OR: - /* TODO: Implement emulation of S32OR instruction. */ - MIPS_INVAL("OPC_MXU_S32OR"); - generate_exception_end(ctx, EXCP_RI); + gen_mxu_S32OR(ctx); break; case OPC_MXU_S32XOR: - /* TODO: Implement emulation of S32XOR instruction. */ - MIPS_INVAL("OPC_MXU_S32XOR"); + gen_mxu_S32XOR(ctx); + break; + default: + MIPS_INVAL("decode_opc_mxu"); generate_exception_end(ctx, EXCP_RI); break; - case OPC_MXU_S32LUI: - /* TODO: Implement emulation of S32LUI instruction. */ - MIPS_INVAL("OPC_MXU_S32LUI"); + } +} + +/* + * + * Decode MXU pool17 + * + * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 + * +-----------+---------+---------+---+---------+-----+-----------+ + * | SPECIAL2 | rs | rt |0 0| rd |x x x|MXU__POOL15| + * +-----------+---------+---------+---+---------+-----+-----------+ + * + */ +static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx) +{ + uint32_t opcode = extract32(ctx->opcode, 6, 2); + + switch (opcode) { + case OPC_MXU_LXW: + /* TODO: Implement emulation of LXW instruction. */ + MIPS_INVAL("OPC_MXU_LXW"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_LXH: + /* TODO: Implement emulation of LXH instruction. */ + MIPS_INVAL("OPC_MXU_LXH"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_LXHU: + /* TODO: Implement emulation of LXHU instruction. */ + MIPS_INVAL("OPC_MXU_LXHU"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_LXB: + /* TODO: Implement emulation of LXB instruction. */ + MIPS_INVAL("OPC_MXU_LXB"); + generate_exception_end(ctx, EXCP_RI); + break; + case OPC_MXU_LXBU: + /* TODO: Implement emulation of LXBU instruction. */ + MIPS_INVAL("OPC_MXU_LXBU"); generate_exception_end(ctx, EXCP_RI); break; default: @@ -25325,18 +26080,17 @@ static void decode_opc_mxu__pool16(CPUMIPSState *env, DisasContext *ctx) break; } } - /* * - * Decode MXU pool17 + * Decode MXU pool18 * * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL17| + * | SPECIAL2 | rb |x x x| XRd | XRa |0 0 0 0|MXU__POOL18| * +-----------+---------+-----+-------+-------+-------+-----------+ * */ -static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode = extract32(ctx->opcode, 18, 3); @@ -25380,15 +26134,15 @@ static void decode_opc_mxu__pool17(CPUMIPSState *env, DisasContext *ctx) /* * - * Decode MXU pool18 + * Decode MXU pool19 * * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL18| + * | SPECIAL2 |0 0|x x| XRd | XRc | XRb | XRa |MXU__POOL19| * +-----------+---+---+-------+-------+-------+-------+-----------+ * */ -static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode = extract32(ctx->opcode, 22, 2); @@ -25406,15 +26160,15 @@ static void decode_opc_mxu__pool18(CPUMIPSState *env, DisasContext *ctx) /* * - * Decode MXU pool19 + * Decode MXU pool20 * * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-----------+---------+-----+-------+-------+-------+-----------+ - * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL19| + * | SPECIAL2 |0 0 0 0 0|x x x| XRc | XRb | XRa |MXU__POOL20| * +-----------+---------+-----+-------+-------+-------+-----------+ * */ -static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode = extract32(ctx->opcode, 18, 3); @@ -25458,15 +26212,15 @@ static void decode_opc_mxu__pool19(CPUMIPSState *env, DisasContext *ctx) /* * - * Decode MXU pool20 + * Decode MXU pool21 * * 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0 * +-----------+---+---+-------+-------+-------+-------+-----------+ - * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL20| + * | SPECIAL2 |an2|x x| XRd | XRc | XRb | XRa |MXU__POOL21| * +-----------+---+---+-------+-------+-------+-------+-----------+ * */ -static void decode_opc_mxu__pool20(CPUMIPSState *env, DisasContext *ctx) +static void decode_opc_mxu__pool21(CPUMIPSState *env, DisasContext *ctx) { uint32_t opcode = extract32(ctx->opcode, 22, 2); @@ -25669,10 +26423,8 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) case OPC_MXU__POOL16: decode_opc_mxu__pool16(env, ctx); break; - case OPC_MXU_LXB: - /* TODO: Implement emulation of LXB instruction. */ - MIPS_INVAL("OPC_MXU_LXB"); - generate_exception_end(ctx, EXCP_RI); + case OPC_MXU__POOL17: + decode_opc_mxu__pool17(env, ctx); break; case OPC_MXU_S16LDD: /* TODO: Implement emulation of S16LDD instruction. */ @@ -25724,23 +26476,23 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) MIPS_INVAL("OPC_MXU_Q16SLR"); generate_exception_end(ctx, EXCP_RI); break; - case OPC_MXU__POOL17: - decode_opc_mxu__pool17(env, ctx); + case OPC_MXU__POOL18: + decode_opc_mxu__pool18(env, ctx); break; case OPC_MXU_Q16SAR: /* TODO: Implement emulation of Q16SAR instruction. */ MIPS_INVAL("OPC_MXU_Q16SAR"); generate_exception_end(ctx, EXCP_RI); break; - case OPC_MXU__POOL18: - decode_opc_mxu__pool18(env, ctx); - break; case OPC_MXU__POOL19: decode_opc_mxu__pool19(env, ctx); break; case OPC_MXU__POOL20: decode_opc_mxu__pool20(env, ctx); break; + case OPC_MXU__POOL21: + decode_opc_mxu__pool21(env, ctx); + break; case OPC_MXU_Q16SCOP: /* TODO: Implement emulation of Q16SCOP instruction. */ MIPS_INVAL("OPC_MXU_Q16SCOP"); @@ -25771,6 +26523,8 @@ static void decode_opc_mxu(CPUMIPSState *env, DisasContext *ctx) } } +#endif /* !defined(TARGET_MIPS64) */ + static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) { @@ -26620,6 +27374,10 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) break; case MMI_OPC_MULT1: case MMI_OPC_MULTU1: + case MMI_OPC_MADD: + case MMI_OPC_MADDU: + case MMI_OPC_MADD1: + case MMI_OPC_MADDU1: gen_mul_txx9(ctx, opc, rd, rs, rt); break; case MMI_OPC_DIV1: @@ -26634,11 +27392,7 @@ static void decode_mmi(CPUMIPSState *env, DisasContext *ctx) case MMI_OPC_MFHI1: gen_HILO1_tx79(ctx, opc, rd); break; - case MMI_OPC_MADD: /* TODO: MMI_OPC_MADD */ - case MMI_OPC_MADDU: /* TODO: MMI_OPC_MADDU */ case MMI_OPC_PLZCW: /* TODO: MMI_OPC_PLZCW */ - case MMI_OPC_MADD1: /* TODO: MMI_OPC_MADD1 */ - case MMI_OPC_MADDU1: /* TODO: MMI_OPC_MADDU1 */ case MMI_OPC_PMFHL: /* TODO: MMI_OPC_PMFHL */ case MMI_OPC_PMTHL: /* TODO: MMI_OPC_PMTHL */ case MMI_OPC_PSLLH: /* TODO: MMI_OPC_PSLLH */ @@ -28015,8 +28769,10 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) case OPC_SPECIAL2: if ((ctx->insn_flags & INSN_R5900) && (ctx->insn_flags & ASE_MMI)) { decode_mmi(env, ctx); +#if !defined(TARGET_MIPS64) } else if (ctx->insn_flags & ASE_MXU) { decode_opc_mxu(env, ctx); +#endif } else { decode_opc_special2_legacy(env, ctx); } @@ -29025,7 +29781,7 @@ void mips_tcg_init(void) fpu_fcr31 = tcg_global_mem_new_i32(cpu_env, offsetof(CPUMIPSState, active_fpu.fcr31), "fcr31"); - +#if !defined(TARGET_MIPS64) for (i = 0; i < NUMBER_OF_MXU_REGISTERS - 1; i++) { mxu_gpr[i] = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, @@ -29036,6 +29792,7 @@ void mips_tcg_init(void) mxu_CR = tcg_global_mem_new(cpu_env, offsetof(CPUMIPSState, active_tc.mxu_cr), mxuregnames[NUMBER_OF_MXU_REGISTERS - 1]); +#endif } #include "translate_init.inc.c" diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index a025a0a3ba..5e8a2cb2ba 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -330,8 +330,8 @@ static void riscv_cpu_class_init(ObjectClass *c, void *data) CPUClass *cc = CPU_CLASS(c); DeviceClass *dc = DEVICE_CLASS(c); - mcc->parent_realize = dc->realize; - dc->realize = riscv_cpu_realize; + device_class_set_parent_realize(dc, riscv_cpu_realize, + &mcc->parent_realize); mcc->parent_reset = cc->reset; cc->reset = riscv_cpu_reset; diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index 86f9f4730c..0234c2d528 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -445,11 +445,13 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (RISCV_DEBUG_INTERRUPT) { int log_cause = cs->exception_index & RISCV_EXCP_INT_MASK; if (cs->exception_index & RISCV_EXCP_INT_FLAG) { - qemu_log_mask(LOG_TRACE, "core 0: trap %s, epc 0x" TARGET_FMT_lx, - riscv_intr_names[log_cause], env->pc); + qemu_log_mask(LOG_TRACE, "core " + TARGET_FMT_ld ": trap %s, epc 0x" TARGET_FMT_lx "\n", + env->mhartid, riscv_intr_names[log_cause], env->pc); } else { - qemu_log_mask(LOG_TRACE, "core 0: intr %s, epc 0x" TARGET_FMT_lx, - riscv_excp_names[log_cause], env->pc); + qemu_log_mask(LOG_TRACE, "core " + TARGET_FMT_ld ": intr %s, epc 0x" TARGET_FMT_lx "\n", + env->mhartid, riscv_excp_names[log_cause], env->pc); } } @@ -511,8 +513,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (hasbadaddr) { if (RISCV_DEBUG_INTERRUPT) { - qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld - ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); + qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x" + TARGET_FMT_lx "\n", env->mhartid, env->badaddr); } env->sbadaddr = env->badaddr; } else { @@ -536,8 +538,8 @@ void riscv_cpu_do_interrupt(CPUState *cs) if (hasbadaddr) { if (RISCV_DEBUG_INTERRUPT) { - qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld - ": badaddr 0x" TARGET_FMT_lx, env->mhartid, env->badaddr); + qemu_log_mask(LOG_TRACE, "core " TARGET_FMT_ld ": badaddr 0x" + TARGET_FMT_lx "\n", env->mhartid, env->badaddr); } env->mbadaddr = env->badaddr; } else { diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 03abd8fe5e..15a5366616 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -138,7 +138,7 @@ static void pmp_decode_napot(target_ulong a, target_ulong *sa, target_ulong *ea) return; } else { target_ulong t1 = ctz64(~a); - target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 3; + target_ulong base = (a & ~(((target_ulong)1 << t1) - 1)) << 2; target_ulong range = ((target_ulong)1 << (t1 + 3)) - 1; *sa = base; *ea = base + range; diff --git a/tcg/riscv/tcg-target.h b/tcg/riscv/tcg-target.h new file mode 100644 index 0000000000..60918cacb4 --- /dev/null +++ b/tcg/riscv/tcg-target.h @@ -0,0 +1,177 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2018 SiFive, Inc + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#ifndef RISCV_TCG_TARGET_H +#define RISCV_TCG_TARGET_H + +#if __riscv_xlen == 32 +# define TCG_TARGET_REG_BITS 32 +#elif __riscv_xlen == 64 +# define TCG_TARGET_REG_BITS 64 +#endif + +#define TCG_TARGET_INSN_UNIT_SIZE 4 +#define TCG_TARGET_TLB_DISPLACEMENT_BITS 20 +#define TCG_TARGET_NB_REGS 32 + +typedef enum { + TCG_REG_ZERO, + TCG_REG_RA, + TCG_REG_SP, + TCG_REG_GP, + TCG_REG_TP, + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_S0, + TCG_REG_S1, + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + TCG_REG_S9, + TCG_REG_S10, + TCG_REG_S11, + TCG_REG_T3, + TCG_REG_T4, + TCG_REG_T5, + TCG_REG_T6, + + /* aliases */ + TCG_AREG0 = TCG_REG_S0, + TCG_GUEST_BASE_REG = TCG_REG_S1, + TCG_REG_TMP0 = TCG_REG_T6, + TCG_REG_TMP1 = TCG_REG_T5, + TCG_REG_TMP2 = TCG_REG_T4, +} TCGReg; + +/* used for function call generation */ +#define TCG_REG_CALL_STACK TCG_REG_SP +#define TCG_TARGET_STACK_ALIGN 16 +#define TCG_TARGET_CALL_ALIGN_ARGS 1 +#define TCG_TARGET_CALL_STACK_OFFSET 0 + +/* optional instructions */ +#define TCG_TARGET_HAS_goto_ptr 1 +#define TCG_TARGET_HAS_movcond_i32 0 +#define TCG_TARGET_HAS_div_i32 1 +#define TCG_TARGET_HAS_rem_i32 1 +#define TCG_TARGET_HAS_div2_i32 0 +#define TCG_TARGET_HAS_rot_i32 0 +#define TCG_TARGET_HAS_deposit_i32 0 +#define TCG_TARGET_HAS_extract_i32 0 +#define TCG_TARGET_HAS_sextract_i32 0 +#define TCG_TARGET_HAS_add2_i32 1 +#define TCG_TARGET_HAS_sub2_i32 1 +#define TCG_TARGET_HAS_mulu2_i32 0 +#define TCG_TARGET_HAS_muls2_i32 0 +#define TCG_TARGET_HAS_muluh_i32 (TCG_TARGET_REG_BITS == 32) +#define TCG_TARGET_HAS_mulsh_i32 (TCG_TARGET_REG_BITS == 32) +#define TCG_TARGET_HAS_ext8s_i32 1 +#define TCG_TARGET_HAS_ext16s_i32 1 +#define TCG_TARGET_HAS_ext8u_i32 1 +#define TCG_TARGET_HAS_ext16u_i32 1 +#define TCG_TARGET_HAS_bswap16_i32 0 +#define TCG_TARGET_HAS_bswap32_i32 0 +#define TCG_TARGET_HAS_not_i32 1 +#define TCG_TARGET_HAS_neg_i32 1 +#define TCG_TARGET_HAS_andc_i32 0 +#define TCG_TARGET_HAS_orc_i32 0 +#define TCG_TARGET_HAS_eqv_i32 0 +#define TCG_TARGET_HAS_nand_i32 0 +#define TCG_TARGET_HAS_nor_i32 0 +#define TCG_TARGET_HAS_clz_i32 0 +#define TCG_TARGET_HAS_ctz_i32 0 +#define TCG_TARGET_HAS_ctpop_i32 0 +#define TCG_TARGET_HAS_direct_jump 0 +#define TCG_TARGET_HAS_brcond2 1 +#define TCG_TARGET_HAS_setcond2 1 + +#if TCG_TARGET_REG_BITS == 64 +#define TCG_TARGET_HAS_movcond_i64 0 +#define TCG_TARGET_HAS_div_i64 1 +#define TCG_TARGET_HAS_rem_i64 1 +#define TCG_TARGET_HAS_div2_i64 0 +#define TCG_TARGET_HAS_rot_i64 0 +#define TCG_TARGET_HAS_deposit_i64 0 +#define TCG_TARGET_HAS_extract_i64 0 +#define TCG_TARGET_HAS_sextract_i64 0 +#define TCG_TARGET_HAS_extrl_i64_i32 1 +#define TCG_TARGET_HAS_extrh_i64_i32 1 +#define TCG_TARGET_HAS_ext8s_i64 1 +#define TCG_TARGET_HAS_ext16s_i64 1 +#define TCG_TARGET_HAS_ext32s_i64 1 +#define TCG_TARGET_HAS_ext8u_i64 1 +#define TCG_TARGET_HAS_ext16u_i64 1 +#define TCG_TARGET_HAS_ext32u_i64 1 +#define TCG_TARGET_HAS_bswap16_i64 0 +#define TCG_TARGET_HAS_bswap32_i64 0 +#define TCG_TARGET_HAS_bswap64_i64 0 +#define TCG_TARGET_HAS_not_i64 1 +#define TCG_TARGET_HAS_neg_i64 1 +#define TCG_TARGET_HAS_andc_i64 0 +#define TCG_TARGET_HAS_orc_i64 0 +#define TCG_TARGET_HAS_eqv_i64 0 +#define TCG_TARGET_HAS_nand_i64 0 +#define TCG_TARGET_HAS_nor_i64 0 +#define TCG_TARGET_HAS_clz_i64 0 +#define TCG_TARGET_HAS_ctz_i64 0 +#define TCG_TARGET_HAS_ctpop_i64 0 +#define TCG_TARGET_HAS_add2_i64 1 +#define TCG_TARGET_HAS_sub2_i64 1 +#define TCG_TARGET_HAS_mulu2_i64 0 +#define TCG_TARGET_HAS_muls2_i64 0 +#define TCG_TARGET_HAS_muluh_i64 1 +#define TCG_TARGET_HAS_mulsh_i64 1 +#endif + +static inline void flush_icache_range(uintptr_t start, uintptr_t stop) +{ + __builtin___clear_cache((char *)start, (char *)stop); +} + +/* not defined -- call should be eliminated at compile time */ +void tb_target_set_jmp_target(uintptr_t, uintptr_t, uintptr_t); + +#define TCG_TARGET_DEFAULT_MO (0) + +#ifdef CONFIG_SOFTMMU +#define TCG_TARGET_NEED_LDST_LABELS +#endif +#define TCG_TARGET_NEED_POOL_LABELS + +#define TCG_TARGET_HAS_MEMORY_BSWAP 0 + +#endif diff --git a/tcg/riscv/tcg-target.inc.c b/tcg/riscv/tcg-target.inc.c new file mode 100644 index 0000000000..6cf8de32b5 --- /dev/null +++ b/tcg/riscv/tcg-target.inc.c @@ -0,0 +1,1949 @@ +/* + * Tiny Code Generator for QEMU + * + * Copyright (c) 2018 SiFive, Inc + * Copyright (c) 2008-2009 Arnaud Patard <arnaud.patard@rtp-net.org> + * Copyright (c) 2009 Aurelien Jarno <aurelien@aurel32.net> + * Copyright (c) 2008 Fabrice Bellard + * + * Based on i386/tcg-target.c and mips/tcg-target.c + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "tcg-pool.inc.c" + +#ifdef CONFIG_DEBUG_TCG +static const char * const tcg_target_reg_names[TCG_TARGET_NB_REGS] = { + "zero", + "ra", + "sp", + "gp", + "tp", + "t0", + "t1", + "t2", + "s0", + "s1", + "a0", + "a1", + "a2", + "a3", + "a4", + "a5", + "a6", + "a7", + "s2", + "s3", + "s4", + "s5", + "s6", + "s7", + "s8", + "s9", + "s10", + "s11", + "t3", + "t4", + "t5", + "t6" +}; +#endif + +static const int tcg_target_reg_alloc_order[] = { + /* Call saved registers */ + /* TCG_REG_S0 reservered for TCG_AREG0 */ + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + TCG_REG_S9, + TCG_REG_S10, + TCG_REG_S11, + + /* Call clobbered registers */ + TCG_REG_T0, + TCG_REG_T1, + TCG_REG_T2, + TCG_REG_T3, + TCG_REG_T4, + TCG_REG_T5, + TCG_REG_T6, + + /* Argument registers */ + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, +}; + +static const int tcg_target_call_iarg_regs[] = { + TCG_REG_A0, + TCG_REG_A1, + TCG_REG_A2, + TCG_REG_A3, + TCG_REG_A4, + TCG_REG_A5, + TCG_REG_A6, + TCG_REG_A7, +}; + +static const int tcg_target_call_oarg_regs[] = { + TCG_REG_A0, + TCG_REG_A1, +}; + +#define TCG_CT_CONST_ZERO 0x100 +#define TCG_CT_CONST_S12 0x200 +#define TCG_CT_CONST_N12 0x400 +#define TCG_CT_CONST_M12 0x800 + +static inline tcg_target_long sextreg(tcg_target_long val, int pos, int len) +{ + if (TCG_TARGET_REG_BITS == 32) { + return sextract32(val, pos, len); + } else { + return sextract64(val, pos, len); + } +} + +/* parse target specific constraints */ +static const char *target_parse_constraint(TCGArgConstraint *ct, + const char *ct_str, TCGType type) +{ + switch (*ct_str++) { + case 'r': + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + break; + case 'L': + /* qemu_ld/qemu_st constraint */ + ct->ct |= TCG_CT_REG; + ct->u.regs = 0xffffffff; + /* qemu_ld/qemu_st uses TCG_REG_TMP0 */ +#if defined(CONFIG_SOFTMMU) + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[0]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[1]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[2]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[3]); + tcg_regset_reset_reg(ct->u.regs, tcg_target_call_iarg_regs[4]); +#endif + break; + case 'I': + ct->ct |= TCG_CT_CONST_S12; + break; + case 'N': + ct->ct |= TCG_CT_CONST_N12; + break; + case 'M': + ct->ct |= TCG_CT_CONST_M12; + break; + case 'Z': + /* we can use a zero immediate as a zero register argument. */ + ct->ct |= TCG_CT_CONST_ZERO; + break; + default: + return NULL; + } + return ct_str; +} + +/* test if a constant matches the constraint */ +static int tcg_target_const_match(tcg_target_long val, TCGType type, + const TCGArgConstraint *arg_ct) +{ + int ct = arg_ct->ct; + if (ct & TCG_CT_CONST) { + return 1; + } + if ((ct & TCG_CT_CONST_ZERO) && val == 0) { + return 1; + } + if ((ct & TCG_CT_CONST_S12) && val == sextreg(val, 0, 12)) { + return 1; + } + if ((ct & TCG_CT_CONST_N12) && -val == sextreg(-val, 0, 12)) { + return 1; + } + if ((ct & TCG_CT_CONST_M12) && val >= -0xfff && val <= 0xfff) { + return 1; + } + return 0; +} + +/* + * RISC-V Base ISA opcodes (IM) + */ + +typedef enum { + OPC_ADD = 0x33, + OPC_ADDI = 0x13, + OPC_AND = 0x7033, + OPC_ANDI = 0x7013, + OPC_AUIPC = 0x17, + OPC_BEQ = 0x63, + OPC_BGE = 0x5063, + OPC_BGEU = 0x7063, + OPC_BLT = 0x4063, + OPC_BLTU = 0x6063, + OPC_BNE = 0x1063, + OPC_DIV = 0x2004033, + OPC_DIVU = 0x2005033, + OPC_JAL = 0x6f, + OPC_JALR = 0x67, + OPC_LB = 0x3, + OPC_LBU = 0x4003, + OPC_LD = 0x3003, + OPC_LH = 0x1003, + OPC_LHU = 0x5003, + OPC_LUI = 0x37, + OPC_LW = 0x2003, + OPC_LWU = 0x6003, + OPC_MUL = 0x2000033, + OPC_MULH = 0x2001033, + OPC_MULHSU = 0x2002033, + OPC_MULHU = 0x2003033, + OPC_OR = 0x6033, + OPC_ORI = 0x6013, + OPC_REM = 0x2006033, + OPC_REMU = 0x2007033, + OPC_SB = 0x23, + OPC_SD = 0x3023, + OPC_SH = 0x1023, + OPC_SLL = 0x1033, + OPC_SLLI = 0x1013, + OPC_SLT = 0x2033, + OPC_SLTI = 0x2013, + OPC_SLTIU = 0x3013, + OPC_SLTU = 0x3033, + OPC_SRA = 0x40005033, + OPC_SRAI = 0x40005013, + OPC_SRL = 0x5033, + OPC_SRLI = 0x5013, + OPC_SUB = 0x40000033, + OPC_SW = 0x2023, + OPC_XOR = 0x4033, + OPC_XORI = 0x4013, + +#if TCG_TARGET_REG_BITS == 64 + OPC_ADDIW = 0x1b, + OPC_ADDW = 0x3b, + OPC_DIVUW = 0x200503b, + OPC_DIVW = 0x200403b, + OPC_MULW = 0x200003b, + OPC_REMUW = 0x200703b, + OPC_REMW = 0x200603b, + OPC_SLLIW = 0x101b, + OPC_SLLW = 0x103b, + OPC_SRAIW = 0x4000501b, + OPC_SRAW = 0x4000503b, + OPC_SRLIW = 0x501b, + OPC_SRLW = 0x503b, + OPC_SUBW = 0x4000003b, +#else + /* Simplify code throughout by defining aliases for RV32. */ + OPC_ADDIW = OPC_ADDI, + OPC_ADDW = OPC_ADD, + OPC_DIVUW = OPC_DIVU, + OPC_DIVW = OPC_DIV, + OPC_MULW = OPC_MUL, + OPC_REMUW = OPC_REMU, + OPC_REMW = OPC_REM, + OPC_SLLIW = OPC_SLLI, + OPC_SLLW = OPC_SLL, + OPC_SRAIW = OPC_SRAI, + OPC_SRAW = OPC_SRA, + OPC_SRLIW = OPC_SRLI, + OPC_SRLW = OPC_SRL, + OPC_SUBW = OPC_SUB, +#endif + + OPC_FENCE = 0x0000000f, +} RISCVInsn; + +/* + * RISC-V immediate and instruction encoders (excludes 16-bit RVC) + */ + +/* Type-R */ + +static int32_t encode_r(RISCVInsn opc, TCGReg rd, TCGReg rs1, TCGReg rs2) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20; +} + +/* Type-I */ + +static int32_t encode_imm12(uint32_t imm) +{ + return (imm & 0xfff) << 20; +} + +static int32_t encode_i(RISCVInsn opc, TCGReg rd, TCGReg rs1, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | (rs1 & 0x1f) << 15 | encode_imm12(imm); +} + +/* Type-S */ + +static int32_t encode_simm12(uint32_t imm) +{ + int32_t ret = 0; + + ret |= (imm & 0xFE0) << 20; + ret |= (imm & 0x1F) << 7; + + return ret; +} + +static int32_t encode_s(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_simm12(imm); +} + +/* Type-SB */ + +static int32_t encode_sbimm12(uint32_t imm) +{ + int32_t ret = 0; + + ret |= (imm & 0x1000) << 19; + ret |= (imm & 0x7e0) << 20; + ret |= (imm & 0x1e) << 7; + ret |= (imm & 0x800) >> 4; + + return ret; +} + +static int32_t encode_sb(RISCVInsn opc, TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + return opc | (rs1 & 0x1f) << 15 | (rs2 & 0x1f) << 20 | encode_sbimm12(imm); +} + +/* Type-U */ + +static int32_t encode_uimm20(uint32_t imm) +{ + return imm & 0xfffff000; +} + +static int32_t encode_u(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_uimm20(imm); +} + +/* Type-UJ */ + +static int32_t encode_ujimm20(uint32_t imm) +{ + int32_t ret = 0; + + ret |= (imm & 0x0007fe) << (21 - 1); + ret |= (imm & 0x000800) << (20 - 11); + ret |= (imm & 0x0ff000) << (12 - 12); + ret |= (imm & 0x100000) << (31 - 20); + + return ret; +} + +static int32_t encode_uj(RISCVInsn opc, TCGReg rd, uint32_t imm) +{ + return opc | (rd & 0x1f) << 7 | encode_ujimm20(imm); +} + +/* + * RISC-V instruction emitters + */ + +static void tcg_out_opc_reg(TCGContext *s, RISCVInsn opc, + TCGReg rd, TCGReg rs1, TCGReg rs2) +{ + tcg_out32(s, encode_r(opc, rd, rs1, rs2)); +} + +static void tcg_out_opc_imm(TCGContext *s, RISCVInsn opc, + TCGReg rd, TCGReg rs1, TCGArg imm) +{ + tcg_out32(s, encode_i(opc, rd, rs1, imm)); +} + +static void tcg_out_opc_store(TCGContext *s, RISCVInsn opc, + TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + tcg_out32(s, encode_s(opc, rs1, rs2, imm)); +} + +static void tcg_out_opc_branch(TCGContext *s, RISCVInsn opc, + TCGReg rs1, TCGReg rs2, uint32_t imm) +{ + tcg_out32(s, encode_sb(opc, rs1, rs2, imm)); +} + +static void tcg_out_opc_upper(TCGContext *s, RISCVInsn opc, + TCGReg rd, uint32_t imm) +{ + tcg_out32(s, encode_u(opc, rd, imm)); +} + +static void tcg_out_opc_jump(TCGContext *s, RISCVInsn opc, + TCGReg rd, uint32_t imm) +{ + tcg_out32(s, encode_uj(opc, rd, imm)); +} + +static void tcg_out_nop_fill(tcg_insn_unit *p, int count) +{ + int i; + for (i = 0; i < count; ++i) { + p[i] = encode_i(OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); + } +} + +/* + * Relocations + */ + +static bool reloc_sbimm12(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + + if (offset == sextreg(offset, 1, 12) << 1) { + code_ptr[0] |= encode_sbimm12(offset); + return true; + } + + return false; +} + +static bool reloc_jimm20(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + + if (offset == sextreg(offset, 1, 20) << 1) { + code_ptr[0] |= encode_ujimm20(offset); + return true; + } + + return false; +} + +static bool reloc_call(tcg_insn_unit *code_ptr, tcg_insn_unit *target) +{ + intptr_t offset = (intptr_t)target - (intptr_t)code_ptr; + int32_t lo = sextreg(offset, 0, 12); + int32_t hi = offset - lo; + + if (offset == hi + lo) { + code_ptr[0] |= encode_uimm20(hi); + code_ptr[1] |= encode_imm12(lo); + return true; + } + + return false; +} + +static bool patch_reloc(tcg_insn_unit *code_ptr, int type, + intptr_t value, intptr_t addend) +{ + uint32_t insn = *code_ptr; + intptr_t diff; + bool short_jmp; + + tcg_debug_assert(addend == 0); + + switch (type) { + case R_RISCV_BRANCH: + diff = value - (uintptr_t)code_ptr; + short_jmp = diff == sextreg(diff, 0, 12); + if (short_jmp) { + return reloc_sbimm12(code_ptr, (tcg_insn_unit *)value); + } else { + /* Invert the condition */ + insn = insn ^ (1 << 12); + /* Clear the offset */ + insn &= 0x01fff07f; + /* Set the offset to the PC + 8 */ + insn |= encode_sbimm12(8); + + /* Move forward */ + code_ptr[0] = insn; + + /* Overwrite the NOP with jal x0,value */ + diff = value - (uintptr_t)(code_ptr + 1); + insn = encode_uj(OPC_JAL, TCG_REG_ZERO, diff); + code_ptr[1] = insn; + + return true; + } + break; + case R_RISCV_JAL: + return reloc_jimm20(code_ptr, (tcg_insn_unit *)value); + break; + case R_RISCV_CALL: + return reloc_call(code_ptr, (tcg_insn_unit *)value); + break; + default: + tcg_abort(); + } +} + +/* + * TCG intrinsics + */ + +static void tcg_out_mov(TCGContext *s, TCGType type, TCGReg ret, TCGReg arg) +{ + if (ret == arg) { + return; + } + switch (type) { + case TCG_TYPE_I32: + case TCG_TYPE_I64: + tcg_out_opc_imm(s, OPC_ADDI, ret, arg, 0); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_movi(TCGContext *s, TCGType type, TCGReg rd, + tcg_target_long val) +{ + tcg_target_long lo, hi, tmp; + int shift, ret; + + if (TCG_TARGET_REG_BITS == 64 && type == TCG_TYPE_I32) { + val = (int32_t)val; + } + + lo = sextreg(val, 0, 12); + if (val == lo) { + tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, lo); + return; + } + + hi = val - lo; + if (TCG_TARGET_REG_BITS == 32 || val == (int32_t)val) { + tcg_out_opc_upper(s, OPC_LUI, rd, hi); + if (lo != 0) { + tcg_out_opc_imm(s, OPC_ADDIW, rd, rd, lo); + } + return; + } + + /* We can only be here if TCG_TARGET_REG_BITS != 32 */ + tmp = tcg_pcrel_diff(s, (void *)val); + if (tmp == (int32_t)tmp) { + tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); + tcg_out_opc_imm(s, OPC_ADDI, rd, rd, 0); + ret = reloc_call(s->code_ptr - 2, (tcg_insn_unit *)val); + tcg_debug_assert(ret == true); + return; + } + + /* Look for a single 20-bit section. */ + shift = ctz64(val); + tmp = val >> shift; + if (tmp == sextreg(tmp, 0, 20)) { + tcg_out_opc_upper(s, OPC_LUI, rd, tmp << 12); + if (shift > 12) { + tcg_out_opc_imm(s, OPC_SLLI, rd, rd, shift - 12); + } else { + tcg_out_opc_imm(s, OPC_SRAI, rd, rd, 12 - shift); + } + return; + } + + /* Look for a few high zero bits, with lots of bits set in the middle. */ + shift = clz64(val); + tmp = val << shift; + if (tmp == sextreg(tmp, 12, 20) << 12) { + tcg_out_opc_upper(s, OPC_LUI, rd, tmp); + tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); + return; + } else if (tmp == sextreg(tmp, 0, 12)) { + tcg_out_opc_imm(s, OPC_ADDI, rd, TCG_REG_ZERO, tmp); + tcg_out_opc_imm(s, OPC_SRLI, rd, rd, shift); + return; + } + + /* Drop into the constant pool. */ + new_pool_label(s, val, R_RISCV_CALL, s->code_ptr, 0); + tcg_out_opc_upper(s, OPC_AUIPC, rd, 0); + tcg_out_opc_imm(s, OPC_LD, rd, rd, 0); +} + +static void tcg_out_ext8u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_ANDI, ret, arg, 0xff); +} + +static void tcg_out_ext16u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); + tcg_out_opc_imm(s, OPC_SRLIW, ret, ret, 16); +} + +static void tcg_out_ext32u(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_SLLI, ret, arg, 32); + tcg_out_opc_imm(s, OPC_SRLI, ret, ret, 32); +} + +static void tcg_out_ext8s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 24); + tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 24); +} + +static void tcg_out_ext16s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_SLLIW, ret, arg, 16); + tcg_out_opc_imm(s, OPC_SRAIW, ret, ret, 16); +} + +static void tcg_out_ext32s(TCGContext *s, TCGReg ret, TCGReg arg) +{ + tcg_out_opc_imm(s, OPC_ADDIW, ret, arg, 0); +} + +static void tcg_out_ldst(TCGContext *s, RISCVInsn opc, TCGReg data, + TCGReg addr, intptr_t offset) +{ + intptr_t imm12 = sextreg(offset, 0, 12); + + if (offset != imm12) { + intptr_t diff = offset - (uintptr_t)s->code_ptr; + + if (addr == TCG_REG_ZERO && diff == (int32_t)diff) { + imm12 = sextreg(diff, 0, 12); + tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP2, diff - imm12); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP2, offset - imm12); + if (addr != TCG_REG_ZERO) { + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, TCG_REG_TMP2, addr); + } + } + addr = TCG_REG_TMP2; + } + + switch (opc) { + case OPC_SB: + case OPC_SH: + case OPC_SW: + case OPC_SD: + tcg_out_opc_store(s, opc, addr, data, imm12); + break; + case OPC_LB: + case OPC_LBU: + case OPC_LH: + case OPC_LHU: + case OPC_LW: + case OPC_LWU: + case OPC_LD: + tcg_out_opc_imm(s, opc, data, addr, imm12); + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_ld(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); + tcg_out_ldst(s, is32bit ? OPC_LW : OPC_LD, arg, arg1, arg2); +} + +static void tcg_out_st(TCGContext *s, TCGType type, TCGReg arg, + TCGReg arg1, intptr_t arg2) +{ + bool is32bit = (TCG_TARGET_REG_BITS == 32 || type == TCG_TYPE_I32); + tcg_out_ldst(s, is32bit ? OPC_SW : OPC_SD, arg, arg1, arg2); +} + +static bool tcg_out_sti(TCGContext *s, TCGType type, TCGArg val, + TCGReg base, intptr_t ofs) +{ + if (val == 0) { + tcg_out_st(s, type, TCG_REG_ZERO, base, ofs); + return true; + } + return false; +} + +static void tcg_out_addsub2(TCGContext *s, + TCGReg rl, TCGReg rh, + TCGReg al, TCGReg ah, + TCGArg bl, TCGArg bh, + bool cbl, bool cbh, bool is_sub, bool is32bit) +{ + const RISCVInsn opc_add = is32bit ? OPC_ADDW : OPC_ADD; + const RISCVInsn opc_addi = is32bit ? OPC_ADDIW : OPC_ADDI; + const RISCVInsn opc_sub = is32bit ? OPC_SUBW : OPC_SUB; + TCGReg th = TCG_REG_TMP1; + + /* If we have a negative constant such that negating it would + make the high part zero, we can (usually) eliminate one insn. */ + if (cbl && cbh && bh == -1 && bl != 0) { + bl = -bl; + bh = 0; + is_sub = !is_sub; + } + + /* By operating on the high part first, we get to use the final + carry operation to move back from the temporary. */ + if (!cbh) { + tcg_out_opc_reg(s, (is_sub ? opc_sub : opc_add), th, ah, bh); + } else if (bh != 0 || ah == rl) { + tcg_out_opc_imm(s, opc_addi, th, ah, (is_sub ? -bh : bh)); + } else { + th = ah; + } + + /* Note that tcg optimization should eliminate the bl == 0 case. */ + if (is_sub) { + if (cbl) { + tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, al, bl); + tcg_out_opc_imm(s, opc_addi, rl, al, -bl); + } else { + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, al, bl); + tcg_out_opc_reg(s, opc_sub, rl, al, bl); + } + tcg_out_opc_reg(s, opc_sub, rh, th, TCG_REG_TMP0); + } else { + if (cbl) { + tcg_out_opc_imm(s, opc_addi, rl, al, bl); + tcg_out_opc_imm(s, OPC_SLTIU, TCG_REG_TMP0, rl, bl); + } else if (rl == al && rl == bl) { + tcg_out_opc_imm(s, OPC_SLTI, TCG_REG_TMP0, al, 0); + tcg_out_opc_reg(s, opc_addi, rl, al, bl); + } else { + tcg_out_opc_reg(s, opc_add, rl, al, bl); + tcg_out_opc_reg(s, OPC_SLTU, TCG_REG_TMP0, + rl, (rl == bl ? al : bl)); + } + tcg_out_opc_reg(s, opc_add, rh, th, TCG_REG_TMP0); + } +} + +static const struct { + RISCVInsn op; + bool swap; +} tcg_brcond_to_riscv[] = { + [TCG_COND_EQ] = { OPC_BEQ, false }, + [TCG_COND_NE] = { OPC_BNE, false }, + [TCG_COND_LT] = { OPC_BLT, false }, + [TCG_COND_GE] = { OPC_BGE, false }, + [TCG_COND_LE] = { OPC_BGE, true }, + [TCG_COND_GT] = { OPC_BLT, true }, + [TCG_COND_LTU] = { OPC_BLTU, false }, + [TCG_COND_GEU] = { OPC_BGEU, false }, + [TCG_COND_LEU] = { OPC_BGEU, true }, + [TCG_COND_GTU] = { OPC_BLTU, true } +}; + +static void tcg_out_brcond(TCGContext *s, TCGCond cond, TCGReg arg1, + TCGReg arg2, TCGLabel *l) +{ + RISCVInsn op = tcg_brcond_to_riscv[cond].op; + + tcg_debug_assert(op != 0); + + if (tcg_brcond_to_riscv[cond].swap) { + TCGReg t = arg1; + arg1 = arg2; + arg2 = t; + } + + if (l->has_value) { + intptr_t diff = tcg_pcrel_diff(s, l->u.value_ptr); + if (diff == sextreg(diff, 0, 12)) { + tcg_out_opc_branch(s, op, arg1, arg2, diff); + } else { + /* Invert the conditional branch. */ + tcg_out_opc_branch(s, op ^ (1 << 12), arg1, arg2, 8); + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, diff - 4); + } + } else { + tcg_out_reloc(s, s->code_ptr, R_RISCV_BRANCH, l, 0); + tcg_out_opc_branch(s, op, arg1, arg2, 0); + /* NOP to allow patching later */ + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); + } +} + +static void tcg_out_setcond(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg arg1, TCGReg arg2) +{ + switch (cond) { + case TCG_COND_EQ: + tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_SLTIU, ret, ret, 1); + break; + case TCG_COND_NE: + tcg_out_opc_reg(s, OPC_SUB, ret, arg1, arg2); + tcg_out_opc_reg(s, OPC_SLTU, ret, TCG_REG_ZERO, ret); + break; + case TCG_COND_LT: + tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); + break; + case TCG_COND_GE: + tcg_out_opc_reg(s, OPC_SLT, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_LE: + tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_GT: + tcg_out_opc_reg(s, OPC_SLT, ret, arg2, arg1); + break; + case TCG_COND_LTU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); + break; + case TCG_COND_GEU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg1, arg2); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_LEU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); + tcg_out_opc_imm(s, OPC_XORI, ret, ret, 1); + break; + case TCG_COND_GTU: + tcg_out_opc_reg(s, OPC_SLTU, ret, arg2, arg1); + break; + default: + g_assert_not_reached(); + break; + } +} + +static void tcg_out_brcond2(TCGContext *s, TCGCond cond, TCGReg al, TCGReg ah, + TCGReg bl, TCGReg bh, TCGLabel *l) +{ + /* todo */ + g_assert_not_reached(); +} + +static void tcg_out_setcond2(TCGContext *s, TCGCond cond, TCGReg ret, + TCGReg al, TCGReg ah, TCGReg bl, TCGReg bh) +{ + /* todo */ + g_assert_not_reached(); +} + +static inline void tcg_out_goto(TCGContext *s, tcg_insn_unit *target) +{ + ptrdiff_t offset = tcg_pcrel_diff(s, target); + tcg_debug_assert(offset == sextreg(offset, 1, 20) << 1); + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, offset); +} + +static void tcg_out_call_int(TCGContext *s, tcg_insn_unit *arg, bool tail) +{ + TCGReg link = tail ? TCG_REG_ZERO : TCG_REG_RA; + ptrdiff_t offset = tcg_pcrel_diff(s, arg); + int ret; + + if (offset == sextreg(offset, 1, 20) << 1) { + /* short jump: -2097150 to 2097152 */ + tcg_out_opc_jump(s, OPC_JAL, link, offset); + } else if (TCG_TARGET_REG_BITS == 32 || + offset == sextreg(offset, 1, 31) << 1) { + /* long jump: -2147483646 to 2147483648 */ + tcg_out_opc_upper(s, OPC_AUIPC, TCG_REG_TMP0, 0); + tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, 0); + ret = reloc_call(s->code_ptr - 2, arg);\ + tcg_debug_assert(ret == true); + } else if (TCG_TARGET_REG_BITS == 64) { + /* far jump: 64-bit */ + tcg_target_long imm = sextreg((tcg_target_long)arg, 0, 12); + tcg_target_long base = (tcg_target_long)arg - imm; + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_TMP0, base); + tcg_out_opc_imm(s, OPC_JALR, link, TCG_REG_TMP0, imm); + } else { + g_assert_not_reached(); + } +} + +static void tcg_out_call(TCGContext *s, tcg_insn_unit *arg) +{ + tcg_out_call_int(s, arg, false); +} + +static void tcg_out_mb(TCGContext *s, TCGArg a0) +{ + tcg_insn_unit insn = OPC_FENCE; + + if (a0 & TCG_MO_LD_LD) { + insn |= 0x02200000; + } + if (a0 & TCG_MO_ST_LD) { + insn |= 0x01200000; + } + if (a0 & TCG_MO_LD_ST) { + insn |= 0x02100000; + } + if (a0 & TCG_MO_ST_ST) { + insn |= 0x02200000; + } + tcg_out32(s, insn); +} + +/* + * Load/store and TLB + */ + +#if defined(CONFIG_SOFTMMU) +#include "tcg-ldst.inc.c" + +/* helper signature: helper_ret_ld_mmu(CPUState *env, target_ulong addr, + * TCGMemOpIdx oi, uintptr_t ra) + */ +static void * const qemu_ld_helpers[16] = { + [MO_UB] = helper_ret_ldub_mmu, + [MO_SB] = helper_ret_ldsb_mmu, + [MO_LEUW] = helper_le_lduw_mmu, + [MO_LESW] = helper_le_ldsw_mmu, + [MO_LEUL] = helper_le_ldul_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_LESL] = helper_le_ldsl_mmu, +#endif + [MO_LEQ] = helper_le_ldq_mmu, + [MO_BEUW] = helper_be_lduw_mmu, + [MO_BESW] = helper_be_ldsw_mmu, + [MO_BEUL] = helper_be_ldul_mmu, +#if TCG_TARGET_REG_BITS == 64 + [MO_BESL] = helper_be_ldsl_mmu, +#endif + [MO_BEQ] = helper_be_ldq_mmu, +}; + +/* helper signature: helper_ret_st_mmu(CPUState *env, target_ulong addr, + * uintxx_t val, TCGMemOpIdx oi, + * uintptr_t ra) + */ +static void * const qemu_st_helpers[16] = { + [MO_UB] = helper_ret_stb_mmu, + [MO_LEUW] = helper_le_stw_mmu, + [MO_LEUL] = helper_le_stl_mmu, + [MO_LEQ] = helper_le_stq_mmu, + [MO_BEUW] = helper_be_stw_mmu, + [MO_BEUL] = helper_be_stl_mmu, + [MO_BEQ] = helper_be_stq_mmu, +}; + +static void tcg_out_tlb_load(TCGContext *s, TCGReg addrl, + TCGReg addrh, TCGMemOpIdx oi, + tcg_insn_unit **label_ptr, bool is_load) +{ + TCGMemOp opc = get_memop(oi); + unsigned s_bits = opc & MO_SIZE; + unsigned a_bits = get_alignment_bits(opc); + target_ulong mask; + int mem_index = get_mmuidx(oi); + int cmp_off + = (is_load + ? offsetof(CPUArchState, tlb_table[mem_index][0].addr_read) + : offsetof(CPUArchState, tlb_table[mem_index][0].addr_write)); + int add_off = offsetof(CPUArchState, tlb_table[mem_index][0].addend); + RISCVInsn load_cmp_op = (TARGET_LONG_BITS == 64 ? OPC_LD : + TCG_TARGET_REG_BITS == 64 ? OPC_LWU : OPC_LW); + RISCVInsn load_add_op = TCG_TARGET_REG_BITS == 64 ? OPC_LD : OPC_LW; + TCGReg base = TCG_AREG0; + + /* We don't support oversize guests */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + g_assert_not_reached(); + } + + /* We don't support unaligned accesses. */ + if (a_bits < s_bits) { + a_bits = s_bits; + } + mask = (target_ulong)TARGET_PAGE_MASK | ((1 << a_bits) - 1); + + + /* Compensate for very large offsets. */ + if (add_off >= 0x1000) { + int adj; + base = TCG_REG_TMP2; + if (cmp_off <= 2 * 0xfff) { + adj = 0xfff; + tcg_out_opc_imm(s, OPC_ADDI, base, TCG_AREG0, adj); + } else { + adj = cmp_off - sextreg(cmp_off, 0, 12); + tcg_debug_assert(add_off - adj >= -0x1000 + && add_off - adj < 0x1000); + + tcg_out_opc_upper(s, OPC_LUI, base, adj); + tcg_out_opc_reg(s, OPC_ADD, base, base, TCG_AREG0); + } + add_off -= adj; + cmp_off -= adj; + } + + /* Extract the page index. */ + if (CPU_TLB_BITS + CPU_TLB_ENTRY_BITS < 12) { + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP0, addrl, + TARGET_PAGE_BITS - CPU_TLB_ENTRY_BITS); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP0, TCG_REG_TMP0, + MAKE_64BIT_MASK(CPU_TLB_ENTRY_BITS, CPU_TLB_BITS)); + } else if (TARGET_PAGE_BITS >= 12) { + tcg_out_opc_upper(s, OPC_LUI, TCG_REG_TMP0, + MAKE_64BIT_MASK(TARGET_PAGE_BITS, CPU_TLB_BITS)); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP0, TCG_REG_TMP0, addrl); + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP0, TCG_REG_TMP0, + CPU_TLB_BITS - CPU_TLB_ENTRY_BITS); + } else { + tcg_out_opc_imm(s, OPC_SRLI, TCG_REG_TMP0, addrl, TARGET_PAGE_BITS); + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP0, TCG_REG_TMP0, + MAKE_64BIT_MASK(0, CPU_TLB_BITS)); + tcg_out_opc_imm(s, OPC_SLLI, TCG_REG_TMP0, TCG_REG_TMP0, + CPU_TLB_ENTRY_BITS); + } + + /* Add that to the base address to index the tlb. */ + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP2, base, TCG_REG_TMP0); + base = TCG_REG_TMP2; + + /* Load the tlb comparator and the addend. */ + tcg_out_ldst(s, load_cmp_op, TCG_REG_TMP0, base, cmp_off); + tcg_out_ldst(s, load_add_op, TCG_REG_TMP2, base, add_off); + + /* Clear the non-page, non-alignment bits from the address. */ + if (mask == sextreg(mask, 0, 12)) { + tcg_out_opc_imm(s, OPC_ANDI, TCG_REG_TMP1, addrl, mask); + } else { + tcg_out_movi(s, TCG_TYPE_REG, TCG_REG_TMP1, mask); + tcg_out_opc_reg(s, OPC_AND, TCG_REG_TMP1, TCG_REG_TMP1, addrl); + } + + /* Compare masked address with the TLB entry. */ + label_ptr[0] = s->code_ptr; + tcg_out_opc_branch(s, OPC_BNE, TCG_REG_TMP0, TCG_REG_TMP1, 0); + /* NOP to allow patching later */ + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_ZERO, TCG_REG_ZERO, 0); + /* TODO: Move this out of line + * see: + * https://lists.nongnu.org/archive/html/qemu-devel/2018-11/msg02234.html + */ + + /* TLB Hit - translate address using addend. */ + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, TCG_REG_TMP0, addrl); + addrl = TCG_REG_TMP0; + } + tcg_out_opc_reg(s, OPC_ADD, TCG_REG_TMP0, TCG_REG_TMP2, addrl); +} + +static void add_qemu_ldst_label(TCGContext *s, int is_ld, TCGMemOpIdx oi, + TCGType ext, + TCGReg datalo, TCGReg datahi, + TCGReg addrlo, TCGReg addrhi, + void *raddr, tcg_insn_unit **label_ptr) +{ + TCGLabelQemuLdst *label = new_ldst_label(s); + + label->is_ld = is_ld; + label->oi = oi; + label->type = ext; + label->datalo_reg = datalo; + label->datahi_reg = datahi; + label->addrlo_reg = addrlo; + label->addrhi_reg = addrhi; + label->raddr = raddr; + label->label_ptr[0] = label_ptr[0]; +} + +static void tcg_out_qemu_ld_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + TCGMemOp opc = get_memop(oi); + TCGReg a0 = tcg_target_call_iarg_regs[0]; + TCGReg a1 = tcg_target_call_iarg_regs[1]; + TCGReg a2 = tcg_target_call_iarg_regs[2]; + TCGReg a3 = tcg_target_call_iarg_regs[3]; + + /* We don't support oversize guests */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + g_assert_not_reached(); + } + + /* resolve label address */ + patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0); + + /* call load helper */ + tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); + tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); + tcg_out_movi(s, TCG_TYPE_PTR, a2, oi); + tcg_out_movi(s, TCG_TYPE_PTR, a3, (tcg_target_long)l->raddr); + + tcg_out_call(s, qemu_ld_helpers[opc & (MO_BSWAP | MO_SSIZE)]); + tcg_out_mov(s, (opc & MO_SIZE) == MO_64, l->datalo_reg, a0); + + tcg_out_goto(s, l->raddr); +} + +static void tcg_out_qemu_st_slow_path(TCGContext *s, TCGLabelQemuLdst *l) +{ + TCGMemOpIdx oi = l->oi; + TCGMemOp opc = get_memop(oi); + TCGMemOp s_bits = opc & MO_SIZE; + TCGReg a0 = tcg_target_call_iarg_regs[0]; + TCGReg a1 = tcg_target_call_iarg_regs[1]; + TCGReg a2 = tcg_target_call_iarg_regs[2]; + TCGReg a3 = tcg_target_call_iarg_regs[3]; + TCGReg a4 = tcg_target_call_iarg_regs[4]; + + /* We don't support oversize guests */ + if (TCG_TARGET_REG_BITS < TARGET_LONG_BITS) { + g_assert_not_reached(); + } + + /* resolve label address */ + patch_reloc(l->label_ptr[0], R_RISCV_BRANCH, (intptr_t) s->code_ptr, 0); + + /* call store helper */ + tcg_out_mov(s, TCG_TYPE_PTR, a0, TCG_AREG0); + tcg_out_mov(s, TCG_TYPE_PTR, a1, l->addrlo_reg); + tcg_out_mov(s, TCG_TYPE_PTR, a2, l->datalo_reg); + switch (s_bits) { + case MO_8: + tcg_out_ext8u(s, a2, a2); + break; + case MO_16: + tcg_out_ext16u(s, a2, a2); + break; + default: + break; + } + tcg_out_movi(s, TCG_TYPE_PTR, a3, oi); + tcg_out_movi(s, TCG_TYPE_PTR, a4, (tcg_target_long)l->raddr); + + tcg_out_call(s, qemu_st_helpers[opc & (MO_BSWAP | MO_SSIZE)]); + + tcg_out_goto(s, l->raddr); +} +#endif /* CONFIG_SOFTMMU */ + +static void tcg_out_qemu_ld_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, TCGMemOp opc, bool is_64) +{ + const TCGMemOp bswap = opc & MO_BSWAP; + + /* We don't yet handle byteswapping, assert */ + g_assert(!bswap); + + switch (opc & (MO_SSIZE)) { + case MO_UB: + tcg_out_opc_imm(s, OPC_LBU, lo, base, 0); + break; + case MO_SB: + tcg_out_opc_imm(s, OPC_LB, lo, base, 0); + break; + case MO_UW: + tcg_out_opc_imm(s, OPC_LHU, lo, base, 0); + break; + case MO_SW: + tcg_out_opc_imm(s, OPC_LH, lo, base, 0); + break; + case MO_UL: + if (TCG_TARGET_REG_BITS == 64 && is_64) { + tcg_out_opc_imm(s, OPC_LWU, lo, base, 0); + break; + } + /* FALLTHRU */ + case MO_SL: + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + break; + case MO_Q: + /* Prefer to load from offset 0 first, but allow for overlap. */ + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_imm(s, OPC_LD, lo, base, 0); + } else if (lo != base) { + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + tcg_out_opc_imm(s, OPC_LW, hi, base, 4); + } else { + tcg_out_opc_imm(s, OPC_LW, hi, base, 4); + tcg_out_opc_imm(s, OPC_LW, lo, base, 0); + } + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_ld(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + TCGMemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 1); + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); + add_qemu_ldst_label(s, 1, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + + if (guest_base == 0) { + tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_ld_direct(s, data_regl, data_regh, base, opc, is_64); +#endif +} + +static void tcg_out_qemu_st_direct(TCGContext *s, TCGReg lo, TCGReg hi, + TCGReg base, TCGMemOp opc) +{ + const TCGMemOp bswap = opc & MO_BSWAP; + + /* We don't yet handle byteswapping, assert */ + g_assert(!bswap); + + switch (opc & (MO_SSIZE)) { + case MO_8: + tcg_out_opc_store(s, OPC_SB, base, lo, 0); + break; + case MO_16: + tcg_out_opc_store(s, OPC_SH, base, lo, 0); + break; + case MO_32: + tcg_out_opc_store(s, OPC_SW, base, lo, 0); + break; + case MO_64: + if (TCG_TARGET_REG_BITS == 64) { + tcg_out_opc_store(s, OPC_SD, base, lo, 0); + } else { + tcg_out_opc_store(s, OPC_SW, base, lo, 0); + tcg_out_opc_store(s, OPC_SW, base, hi, 4); + } + break; + default: + g_assert_not_reached(); + } +} + +static void tcg_out_qemu_st(TCGContext *s, const TCGArg *args, bool is_64) +{ + TCGReg addr_regl, addr_regh __attribute__((unused)); + TCGReg data_regl, data_regh; + TCGMemOpIdx oi; + TCGMemOp opc; +#if defined(CONFIG_SOFTMMU) + tcg_insn_unit *label_ptr[1]; +#endif + TCGReg base = TCG_REG_TMP0; + + data_regl = *args++; + data_regh = (TCG_TARGET_REG_BITS == 32 && is_64 ? *args++ : 0); + addr_regl = *args++; + addr_regh = (TCG_TARGET_REG_BITS < TARGET_LONG_BITS ? *args++ : 0); + oi = *args++; + opc = get_memop(oi); + +#if defined(CONFIG_SOFTMMU) + tcg_out_tlb_load(s, addr_regl, addr_regh, oi, label_ptr, 0); + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); + add_qemu_ldst_label(s, 0, oi, + (is_64 ? TCG_TYPE_I64 : TCG_TYPE_I32), + data_regl, data_regh, addr_regl, addr_regh, + s->code_ptr, label_ptr); +#else + if (TCG_TARGET_REG_BITS > TARGET_LONG_BITS) { + tcg_out_ext32u(s, base, addr_regl); + addr_regl = base; + } + + if (guest_base == 0) { + tcg_out_opc_reg(s, OPC_ADD, base, addr_regl, TCG_REG_ZERO); + } else { + tcg_out_opc_reg(s, OPC_ADD, base, TCG_GUEST_BASE_REG, addr_regl); + } + tcg_out_qemu_st_direct(s, data_regl, data_regh, base, opc); +#endif +} + +static tcg_insn_unit *tb_ret_addr; + +static void tcg_out_op(TCGContext *s, TCGOpcode opc, + const TCGArg *args, const int *const_args) +{ + TCGArg a0 = args[0]; + TCGArg a1 = args[1]; + TCGArg a2 = args[2]; + int c2 = const_args[2]; + + switch (opc) { + case INDEX_op_exit_tb: + /* Reuse the zeroing that exists for goto_ptr. */ + if (a0 == 0) { + tcg_out_call_int(s, s->code_gen_epilogue, true); + } else { + tcg_out_movi(s, TCG_TYPE_PTR, TCG_REG_A0, a0); + tcg_out_call_int(s, tb_ret_addr, true); + } + break; + + case INDEX_op_goto_tb: + assert(s->tb_jmp_insn_offset == 0); + /* indirect jump method */ + tcg_out_ld(s, TCG_TYPE_PTR, TCG_REG_TMP0, TCG_REG_ZERO, + (uintptr_t)(s->tb_jmp_target_addr + a0)); + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_TMP0, 0); + set_jmp_reset_offset(s, a0); + break; + + case INDEX_op_goto_ptr: + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, a0, 0); + break; + + case INDEX_op_br: + tcg_out_reloc(s, s->code_ptr, R_RISCV_JAL, arg_label(a0), 0); + tcg_out_opc_jump(s, OPC_JAL, TCG_REG_ZERO, 0); + break; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8u_i64: + tcg_out_ldst(s, OPC_LBU, a0, a1, a2); + break; + case INDEX_op_ld8s_i32: + case INDEX_op_ld8s_i64: + tcg_out_ldst(s, OPC_LB, a0, a1, a2); + break; + case INDEX_op_ld16u_i32: + case INDEX_op_ld16u_i64: + tcg_out_ldst(s, OPC_LHU, a0, a1, a2); + break; + case INDEX_op_ld16s_i32: + case INDEX_op_ld16s_i64: + tcg_out_ldst(s, OPC_LH, a0, a1, a2); + break; + case INDEX_op_ld32u_i64: + tcg_out_ldst(s, OPC_LWU, a0, a1, a2); + break; + case INDEX_op_ld_i32: + case INDEX_op_ld32s_i64: + tcg_out_ldst(s, OPC_LW, a0, a1, a2); + break; + case INDEX_op_ld_i64: + tcg_out_ldst(s, OPC_LD, a0, a1, a2); + break; + + case INDEX_op_st8_i32: + case INDEX_op_st8_i64: + tcg_out_ldst(s, OPC_SB, a0, a1, a2); + break; + case INDEX_op_st16_i32: + case INDEX_op_st16_i64: + tcg_out_ldst(s, OPC_SH, a0, a1, a2); + break; + case INDEX_op_st_i32: + case INDEX_op_st32_i64: + tcg_out_ldst(s, OPC_SW, a0, a1, a2); + break; + case INDEX_op_st_i64: + tcg_out_ldst(s, OPC_SD, a0, a1, a2); + break; + + case INDEX_op_add_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_ADDW, a0, a1, a2); + } + break; + case INDEX_op_add_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_ADDI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_ADD, a0, a1, a2); + } + break; + + case INDEX_op_sub_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_ADDIW, a0, a1, -a2); + } else { + tcg_out_opc_reg(s, OPC_SUBW, a0, a1, a2); + } + break; + case INDEX_op_sub_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_ADDI, a0, a1, -a2); + } else { + tcg_out_opc_reg(s, OPC_SUB, a0, a1, a2); + } + break; + + case INDEX_op_and_i32: + case INDEX_op_and_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_ANDI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_AND, a0, a1, a2); + } + break; + + case INDEX_op_or_i32: + case INDEX_op_or_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_ORI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_OR, a0, a1, a2); + } + break; + + case INDEX_op_xor_i32: + case INDEX_op_xor_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_XORI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_XOR, a0, a1, a2); + } + break; + + case INDEX_op_not_i32: + case INDEX_op_not_i64: + tcg_out_opc_imm(s, OPC_XORI, a0, a1, -1); + break; + + case INDEX_op_neg_i32: + tcg_out_opc_reg(s, OPC_SUBW, a0, TCG_REG_ZERO, a1); + break; + case INDEX_op_neg_i64: + tcg_out_opc_reg(s, OPC_SUB, a0, TCG_REG_ZERO, a1); + break; + + case INDEX_op_mul_i32: + tcg_out_opc_reg(s, OPC_MULW, a0, a1, a2); + break; + case INDEX_op_mul_i64: + tcg_out_opc_reg(s, OPC_MUL, a0, a1, a2); + break; + + case INDEX_op_div_i32: + tcg_out_opc_reg(s, OPC_DIVW, a0, a1, a2); + break; + case INDEX_op_div_i64: + tcg_out_opc_reg(s, OPC_DIV, a0, a1, a2); + break; + + case INDEX_op_divu_i32: + tcg_out_opc_reg(s, OPC_DIVUW, a0, a1, a2); + break; + case INDEX_op_divu_i64: + tcg_out_opc_reg(s, OPC_DIVU, a0, a1, a2); + break; + + case INDEX_op_rem_i32: + tcg_out_opc_reg(s, OPC_REMW, a0, a1, a2); + break; + case INDEX_op_rem_i64: + tcg_out_opc_reg(s, OPC_REM, a0, a1, a2); + break; + + case INDEX_op_remu_i32: + tcg_out_opc_reg(s, OPC_REMUW, a0, a1, a2); + break; + case INDEX_op_remu_i64: + tcg_out_opc_reg(s, OPC_REMU, a0, a1, a2); + break; + + case INDEX_op_shl_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_SLLIW, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SLLW, a0, a1, a2); + } + break; + case INDEX_op_shl_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_SLLI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SLL, a0, a1, a2); + } + break; + + case INDEX_op_shr_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_SRLIW, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SRLW, a0, a1, a2); + } + break; + case INDEX_op_shr_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_SRLI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SRL, a0, a1, a2); + } + break; + + case INDEX_op_sar_i32: + if (c2) { + tcg_out_opc_imm(s, OPC_SRAIW, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SRAW, a0, a1, a2); + } + break; + case INDEX_op_sar_i64: + if (c2) { + tcg_out_opc_imm(s, OPC_SRAI, a0, a1, a2); + } else { + tcg_out_opc_reg(s, OPC_SRA, a0, a1, a2); + } + break; + + case INDEX_op_add2_i32: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], false, true); + break; + case INDEX_op_add2_i64: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], false, false); + break; + case INDEX_op_sub2_i32: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], true, true); + break; + case INDEX_op_sub2_i64: + tcg_out_addsub2(s, a0, a1, a2, args[3], args[4], args[5], + const_args[4], const_args[5], true, false); + break; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + tcg_out_brcond(s, a2, a0, a1, arg_label(args[3])); + break; + case INDEX_op_brcond2_i32: + tcg_out_brcond2(s, args[4], a0, a1, a2, args[3], arg_label(args[5])); + break; + + case INDEX_op_setcond_i32: + case INDEX_op_setcond_i64: + tcg_out_setcond(s, args[3], a0, a1, a2); + break; + case INDEX_op_setcond2_i32: + tcg_out_setcond2(s, args[5], a0, a1, a2, args[3], args[4]); + break; + + case INDEX_op_qemu_ld_i32: + tcg_out_qemu_ld(s, args, false); + break; + case INDEX_op_qemu_ld_i64: + tcg_out_qemu_ld(s, args, true); + break; + case INDEX_op_qemu_st_i32: + tcg_out_qemu_st(s, args, false); + break; + case INDEX_op_qemu_st_i64: + tcg_out_qemu_st(s, args, true); + break; + + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + tcg_out_ext8u(s, a0, a1); + break; + + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + tcg_out_ext16u(s, a0, a1); + break; + + case INDEX_op_ext32u_i64: + case INDEX_op_extu_i32_i64: + tcg_out_ext32u(s, a0, a1); + break; + + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + tcg_out_ext8s(s, a0, a1); + break; + + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + tcg_out_ext16s(s, a0, a1); + break; + + case INDEX_op_ext32s_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_ext_i32_i64: + tcg_out_ext32s(s, a0, a1); + break; + + case INDEX_op_extrh_i64_i32: + tcg_out_opc_imm(s, OPC_SRAI, a0, a1, 32); + break; + + case INDEX_op_mulsh_i32: + case INDEX_op_mulsh_i64: + tcg_out_opc_reg(s, OPC_MULH, a0, a1, a2); + break; + + case INDEX_op_muluh_i32: + case INDEX_op_muluh_i64: + tcg_out_opc_reg(s, OPC_MULHU, a0, a1, a2); + break; + + case INDEX_op_mb: + tcg_out_mb(s, a0); + break; + + case INDEX_op_mov_i32: /* Always emitted via tcg_out_mov. */ + case INDEX_op_mov_i64: + case INDEX_op_movi_i32: /* Always emitted via tcg_out_movi. */ + case INDEX_op_movi_i64: + case INDEX_op_call: /* Always emitted via tcg_out_call. */ + default: + g_assert_not_reached(); + } +} + +static const TCGTargetOpDef *tcg_target_op_def(TCGOpcode op) +{ + static const TCGTargetOpDef r + = { .args_ct_str = { "r" } }; + static const TCGTargetOpDef r_r + = { .args_ct_str = { "r", "r" } }; + static const TCGTargetOpDef rZ_r + = { .args_ct_str = { "rZ", "r" } }; + static const TCGTargetOpDef rZ_rZ + = { .args_ct_str = { "rZ", "rZ" } }; + static const TCGTargetOpDef rZ_rZ_rZ_rZ + = { .args_ct_str = { "rZ", "rZ", "rZ", "rZ" } }; + static const TCGTargetOpDef r_r_ri + = { .args_ct_str = { "r", "r", "ri" } }; + static const TCGTargetOpDef r_r_rI + = { .args_ct_str = { "r", "r", "rI" } }; + static const TCGTargetOpDef r_rZ_rN + = { .args_ct_str = { "r", "rZ", "rN" } }; + static const TCGTargetOpDef r_rZ_rZ + = { .args_ct_str = { "r", "rZ", "rZ" } }; + static const TCGTargetOpDef r_rZ_rZ_rZ_rZ + = { .args_ct_str = { "r", "rZ", "rZ", "rZ", "rZ" } }; + static const TCGTargetOpDef r_L + = { .args_ct_str = { "r", "L" } }; + static const TCGTargetOpDef r_r_L + = { .args_ct_str = { "r", "r", "L" } }; + static const TCGTargetOpDef r_L_L + = { .args_ct_str = { "r", "L", "L" } }; + static const TCGTargetOpDef r_r_L_L + = { .args_ct_str = { "r", "r", "L", "L" } }; + static const TCGTargetOpDef LZ_L + = { .args_ct_str = { "LZ", "L" } }; + static const TCGTargetOpDef LZ_L_L + = { .args_ct_str = { "LZ", "L", "L" } }; + static const TCGTargetOpDef LZ_LZ_L + = { .args_ct_str = { "LZ", "LZ", "L" } }; + static const TCGTargetOpDef LZ_LZ_L_L + = { .args_ct_str = { "LZ", "LZ", "L", "L" } }; + static const TCGTargetOpDef r_r_rZ_rZ_rM_rM + = { .args_ct_str = { "r", "r", "rZ", "rZ", "rM", "rM" } }; + + switch (op) { + case INDEX_op_goto_ptr: + return &r; + + case INDEX_op_ld8u_i32: + case INDEX_op_ld8s_i32: + case INDEX_op_ld16u_i32: + case INDEX_op_ld16s_i32: + case INDEX_op_ld_i32: + case INDEX_op_not_i32: + case INDEX_op_neg_i32: + case INDEX_op_ld8u_i64: + case INDEX_op_ld8s_i64: + case INDEX_op_ld16u_i64: + case INDEX_op_ld16s_i64: + case INDEX_op_ld32s_i64: + case INDEX_op_ld32u_i64: + case INDEX_op_ld_i64: + case INDEX_op_not_i64: + case INDEX_op_neg_i64: + case INDEX_op_ext8u_i32: + case INDEX_op_ext8u_i64: + case INDEX_op_ext16u_i32: + case INDEX_op_ext16u_i64: + case INDEX_op_ext32u_i64: + case INDEX_op_extu_i32_i64: + case INDEX_op_ext8s_i32: + case INDEX_op_ext8s_i64: + case INDEX_op_ext16s_i32: + case INDEX_op_ext16s_i64: + case INDEX_op_ext32s_i64: + case INDEX_op_extrl_i64_i32: + case INDEX_op_extrh_i64_i32: + case INDEX_op_ext_i32_i64: + return &r_r; + + case INDEX_op_st8_i32: + case INDEX_op_st16_i32: + case INDEX_op_st_i32: + case INDEX_op_st8_i64: + case INDEX_op_st16_i64: + case INDEX_op_st32_i64: + case INDEX_op_st_i64: + return &rZ_r; + + case INDEX_op_add_i32: + case INDEX_op_and_i32: + case INDEX_op_or_i32: + case INDEX_op_xor_i32: + case INDEX_op_add_i64: + case INDEX_op_and_i64: + case INDEX_op_or_i64: + case INDEX_op_xor_i64: + return &r_r_rI; + + case INDEX_op_sub_i32: + case INDEX_op_sub_i64: + return &r_rZ_rN; + + case INDEX_op_mul_i32: + case INDEX_op_mulsh_i32: + case INDEX_op_muluh_i32: + case INDEX_op_div_i32: + case INDEX_op_divu_i32: + case INDEX_op_rem_i32: + case INDEX_op_remu_i32: + case INDEX_op_setcond_i32: + case INDEX_op_mul_i64: + case INDEX_op_mulsh_i64: + case INDEX_op_muluh_i64: + case INDEX_op_div_i64: + case INDEX_op_divu_i64: + case INDEX_op_rem_i64: + case INDEX_op_remu_i64: + case INDEX_op_setcond_i64: + return &r_rZ_rZ; + + case INDEX_op_shl_i32: + case INDEX_op_shr_i32: + case INDEX_op_sar_i32: + case INDEX_op_shl_i64: + case INDEX_op_shr_i64: + case INDEX_op_sar_i64: + return &r_r_ri; + + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + return &rZ_rZ; + + case INDEX_op_add2_i32: + case INDEX_op_add2_i64: + case INDEX_op_sub2_i32: + case INDEX_op_sub2_i64: + return &r_r_rZ_rZ_rM_rM; + + case INDEX_op_brcond2_i32: + return &rZ_rZ_rZ_rZ; + + case INDEX_op_setcond2_i32: + return &r_rZ_rZ_rZ_rZ; + + case INDEX_op_qemu_ld_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_L : &r_L_L; + case INDEX_op_qemu_st_i32: + return TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_L : &LZ_L_L; + case INDEX_op_qemu_ld_i64: + return TCG_TARGET_REG_BITS == 64 ? &r_L + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &r_r_L + : &r_r_L_L; + case INDEX_op_qemu_st_i64: + return TCG_TARGET_REG_BITS == 64 ? &LZ_L + : TARGET_LONG_BITS <= TCG_TARGET_REG_BITS ? &LZ_LZ_L + : &LZ_LZ_L_L; + + default: + return NULL; + } +} + +static const int tcg_target_callee_save_regs[] = { + TCG_REG_S0, /* used for the global env (TCG_AREG0) */ + TCG_REG_S1, + TCG_REG_S2, + TCG_REG_S3, + TCG_REG_S4, + TCG_REG_S5, + TCG_REG_S6, + TCG_REG_S7, + TCG_REG_S8, + TCG_REG_S9, + TCG_REG_S10, + TCG_REG_S11, + TCG_REG_RA, /* should be last for ABI compliance */ +}; + +/* Stack frame parameters. */ +#define REG_SIZE (TCG_TARGET_REG_BITS / 8) +#define SAVE_SIZE ((int)ARRAY_SIZE(tcg_target_callee_save_regs) * REG_SIZE) +#define TEMP_SIZE (CPU_TEMP_BUF_NLONGS * (int)sizeof(long)) +#define FRAME_SIZE ((TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE + SAVE_SIZE \ + + TCG_TARGET_STACK_ALIGN - 1) \ + & -TCG_TARGET_STACK_ALIGN) +#define SAVE_OFS (TCG_STATIC_CALL_ARGS_SIZE + TEMP_SIZE) + +/* We're expecting to be able to use an immediate for frame allocation. */ +QEMU_BUILD_BUG_ON(FRAME_SIZE > 0x7ff); + +/* Generate global QEMU prologue and epilogue code */ +static void tcg_target_qemu_prologue(TCGContext *s) +{ + int i; + + tcg_set_frame(s, TCG_REG_SP, TCG_STATIC_CALL_ARGS_SIZE, TEMP_SIZE); + + /* TB prologue */ + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, -FRAME_SIZE); + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_st(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + +#if !defined(CONFIG_SOFTMMU) + tcg_out_movi(s, TCG_TYPE_PTR, TCG_GUEST_BASE_REG, guest_base); + tcg_regset_set_reg(s->reserved_regs, TCG_GUEST_BASE_REG); +#endif + + /* Call generated code */ + tcg_out_mov(s, TCG_TYPE_PTR, TCG_AREG0, tcg_target_call_iarg_regs[0]); + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, tcg_target_call_iarg_regs[1], 0); + + /* Return path for goto_ptr. Set return value to 0 */ + s->code_gen_epilogue = s->code_ptr; + tcg_out_mov(s, TCG_TYPE_REG, TCG_REG_A0, TCG_REG_ZERO); + + /* TB epilogue */ + tb_ret_addr = s->code_ptr; + for (i = 0; i < ARRAY_SIZE(tcg_target_callee_save_regs); i++) { + tcg_out_ld(s, TCG_TYPE_REG, tcg_target_callee_save_regs[i], + TCG_REG_SP, SAVE_OFS + i * REG_SIZE); + } + + tcg_out_opc_imm(s, OPC_ADDI, TCG_REG_SP, TCG_REG_SP, FRAME_SIZE); + tcg_out_opc_imm(s, OPC_JALR, TCG_REG_ZERO, TCG_REG_RA, 0); +} + +static void tcg_target_init(TCGContext *s) +{ + tcg_target_available_regs[TCG_TYPE_I32] = 0xffffffff; + if (TCG_TARGET_REG_BITS == 64) { + tcg_target_available_regs[TCG_TYPE_I64] = 0xffffffff; + } + + tcg_target_call_clobber_regs = -1u; + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S0); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S1); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S2); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S3); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S4); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S5); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S6); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S7); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S8); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S9); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S10); + tcg_regset_reset_reg(tcg_target_call_clobber_regs, TCG_REG_S11); + + s->reserved_regs = 0; + tcg_regset_set_reg(s->reserved_regs, TCG_REG_ZERO); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP0); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP1); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TMP2); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_SP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_GP); + tcg_regset_set_reg(s->reserved_regs, TCG_REG_TP); +} + +typedef struct { + DebugFrameHeader h; + uint8_t fde_def_cfa[4]; + uint8_t fde_reg_ofs[ARRAY_SIZE(tcg_target_callee_save_regs) * 2]; +} DebugFrame; + +#define ELF_HOST_MACHINE EM_RISCV + +static const DebugFrame debug_frame = { + .h.cie.len = sizeof(DebugFrameCIE) - 4, /* length after .len member */ + .h.cie.id = -1, + .h.cie.version = 1, + .h.cie.code_align = 1, + .h.cie.data_align = -(TCG_TARGET_REG_BITS / 8) & 0x7f, /* sleb128 */ + .h.cie.return_column = TCG_REG_RA, + + /* Total FDE size does not include the "len" member. */ + .h.fde.len = sizeof(DebugFrame) - offsetof(DebugFrame, h.fde.cie_offset), + + .fde_def_cfa = { + 12, TCG_REG_SP, /* DW_CFA_def_cfa sp, ... */ + (FRAME_SIZE & 0x7f) | 0x80, /* ... uleb128 FRAME_SIZE */ + (FRAME_SIZE >> 7) + }, + .fde_reg_ofs = { + 0x80 + 9, 12, /* DW_CFA_offset, s1, -96 */ + 0x80 + 18, 11, /* DW_CFA_offset, s2, -88 */ + 0x80 + 19, 10, /* DW_CFA_offset, s3, -80 */ + 0x80 + 20, 9, /* DW_CFA_offset, s4, -72 */ + 0x80 + 21, 8, /* DW_CFA_offset, s5, -64 */ + 0x80 + 22, 7, /* DW_CFA_offset, s6, -56 */ + 0x80 + 23, 6, /* DW_CFA_offset, s7, -48 */ + 0x80 + 24, 5, /* DW_CFA_offset, s8, -40 */ + 0x80 + 25, 4, /* DW_CFA_offset, s9, -32 */ + 0x80 + 26, 3, /* DW_CFA_offset, s10, -24 */ + 0x80 + 27, 2, /* DW_CFA_offset, s11, -16 */ + 0x80 + 1 , 1, /* DW_CFA_offset, ra, -8 */ + } +}; + +void tcg_register_jit(void *buf, size_t buf_size) +{ + tcg_register_jit_int(buf, buf_size, &debug_frame, sizeof(debug_frame)); +} diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 38652db32c..1bd7ef24af 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -240,6 +240,7 @@ void tcg_gen_brcond_i32(TCGCond cond, TCGv_i32 arg1, TCGv_i32 arg2, TCGLabel *l) if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { + l->refs++; tcg_gen_op4ii_i32(INDEX_op_brcond_i32, arg1, arg2, cond, label_arg(l)); } } @@ -1405,6 +1406,7 @@ void tcg_gen_brcond_i64(TCGCond cond, TCGv_i64 arg1, TCGv_i64 arg2, TCGLabel *l) if (cond == TCG_COND_ALWAYS) { tcg_gen_br(l); } else if (cond != TCG_COND_NEVER) { + l->refs++; if (TCG_TARGET_REG_BITS == 32) { tcg_gen_op6ii_i32(INDEX_op_brcond2_i32, TCGV_LOW(arg1), TCGV_HIGH(arg1), TCGV_LOW(arg2), diff --git a/tcg/tcg-op.h b/tcg/tcg-op.h index db4e9188f4..7007ec0d4d 100644 --- a/tcg/tcg-op.h +++ b/tcg/tcg-op.h @@ -260,6 +260,7 @@ static inline void gen_set_label(TCGLabel *l) static inline void tcg_gen_br(TCGLabel *l) { + l->refs++; tcg_gen_op1(INDEX_op_br, label_arg(l)); } diff --git a/tcg/tcg-opc.h b/tcg/tcg-opc.h index e3a43aabb6..7a8a3edb5b 100644 --- a/tcg/tcg-opc.h +++ b/tcg/tcg-opc.h @@ -191,9 +191,10 @@ DEF(mulsh_i64, 1, 2, 0, IMPL64 | IMPL(TCG_TARGET_HAS_mulsh_i64)) /* QEMU specific */ DEF(insn_start, 0, 0, TLADDR_ARGS * TARGET_INSN_START_WORDS, TCG_OPF_NOT_PRESENT) -DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_END) -DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_END) -DEF(goto_ptr, 0, 1, 0, TCG_OPF_BB_END | IMPL(TCG_TARGET_HAS_goto_ptr)) +DEF(exit_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) +DEF(goto_tb, 0, 0, 1, TCG_OPF_BB_EXIT | TCG_OPF_BB_END) +DEF(goto_ptr, 0, 1, 0, + TCG_OPF_BB_EXIT | TCG_OPF_BB_END | IMPL(TCG_TARGET_HAS_goto_ptr)) DEF(qemu_ld_i32, 1, TLADDR_ARGS, 1, TCG_OPF_CALL_CLOBBER | TCG_OPF_SIDE_EFFECTS) diff --git a/tcg/tcg.c b/tcg/tcg.c index 963cb37892..c54b119020 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -1887,7 +1887,21 @@ static const char * const alignment_name[(MO_AMASK >> MO_ASHIFT) + 1] = { [MO_ALIGN_64 >> MO_ASHIFT] = "al64+", }; -void tcg_dump_ops(TCGContext *s) +static inline bool tcg_regset_single(TCGRegSet d) +{ + return (d & (d - 1)) == 0; +} + +static inline TCGReg tcg_regset_first(TCGRegSet d) +{ + if (TCG_TARGET_NB_REGS <= 32) { + return ctz32(d); + } else { + return ctz64(d); + } +} + +static void tcg_dump_ops(TCGContext *s, bool have_prefs) { char buf[128]; TCGOp *op; @@ -1902,6 +1916,7 @@ void tcg_dump_ops(TCGContext *s) def = &tcg_op_defs[c]; if (c == INDEX_op_insn_start) { + nb_oargs = 0; col += qemu_log("\n ----"); for (i = 0; i < TARGET_INSN_START_WORDS; ++i) { @@ -2021,12 +2036,15 @@ void tcg_dump_ops(TCGContext *s) col += qemu_log("%s$0x%" TCG_PRIlx, k ? "," : "", op->args[k]); } } - if (op->life) { - unsigned life = op->life; - for (; col < 48; ++col) { + if (have_prefs || op->life) { + for (; col < 40; ++col) { putc(' ', qemu_logfile); } + } + + if (op->life) { + unsigned life = op->life; if (life & (SYNC_ARG * 3)) { qemu_log(" sync:"); @@ -2046,6 +2064,33 @@ void tcg_dump_ops(TCGContext *s) } } } + + if (have_prefs) { + for (i = 0; i < nb_oargs; ++i) { + TCGRegSet set = op->output_pref[i]; + + if (i == 0) { + qemu_log(" pref="); + } else { + qemu_log(","); + } + if (set == 0) { + qemu_log("none"); + } else if (set == MAKE_64BIT_MASK(0, TCG_TARGET_NB_REGS)) { + qemu_log("all"); +#ifdef CONFIG_DEBUG_TCG + } else if (tcg_regset_single(set)) { + TCGReg reg = tcg_regset_first(set); + qemu_log("%s", tcg_target_reg_names[reg]); +#endif + } else if (TCG_TARGET_NB_REGS <= 32) { + qemu_log("%#x", (uint32_t)set); + } else { + qemu_log("%#" PRIx64, (uint64_t)set); + } + } + } + qemu_log("\n"); } } @@ -2171,6 +2216,26 @@ static void process_op_defs(TCGContext *s) void tcg_op_remove(TCGContext *s, TCGOp *op) { + TCGLabel *label; + + switch (op->opc) { + case INDEX_op_br: + label = arg_label(op->args[0]); + label->refs--; + break; + case INDEX_op_brcond_i32: + case INDEX_op_brcond_i64: + label = arg_label(op->args[3]); + label->refs--; + break; + case INDEX_op_brcond2_i32: + label = arg_label(op->args[5]); + label->refs--; + break; + default: + break; + } + QTAILQ_REMOVE(&s->ops, op, link); QTAILQ_INSERT_TAIL(&s->free_ops, op, link); s->nb_ops--; @@ -2219,43 +2284,181 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *old_op, TCGOpcode opc) return new_op; } +/* Reachable analysis : remove unreachable code. */ +static void reachable_code_pass(TCGContext *s) +{ + TCGOp *op, *op_next; + bool dead = false; + + QTAILQ_FOREACH_SAFE(op, &s->ops, link, op_next) { + bool remove = dead; + TCGLabel *label; + int call_flags; + + switch (op->opc) { + case INDEX_op_set_label: + label = arg_label(op->args[0]); + if (label->refs == 0) { + /* + * While there is an occasional backward branch, virtually + * all branches generated by the translators are forward. + * Which means that generally we will have already removed + * all references to the label that will be, and there is + * little to be gained by iterating. + */ + remove = true; + } else { + /* Once we see a label, insns become live again. */ + dead = false; + remove = false; + + /* + * Optimization can fold conditional branches to unconditional. + * If we find a label with one reference which is preceded by + * an unconditional branch to it, remove both. This needed to + * wait until the dead code in between them was removed. + */ + if (label->refs == 1) { + TCGOp *op_prev = QTAILQ_PREV(op, TCGOpHead, link); + if (op_prev->opc == INDEX_op_br && + label == arg_label(op_prev->args[0])) { + tcg_op_remove(s, op_prev); + remove = true; + } + } + } + break; + + case INDEX_op_br: + case INDEX_op_exit_tb: + case INDEX_op_goto_ptr: + /* Unconditional branches; everything following is dead. */ + dead = true; + break; + + case INDEX_op_call: + /* Notice noreturn helper calls, raising exceptions. */ + call_flags = op->args[TCGOP_CALLO(op) + TCGOP_CALLI(op) + 1]; + if (call_flags & TCG_CALL_NO_RETURN) { + dead = true; + } + break; + + case INDEX_op_insn_start: + /* Never remove -- we need to keep these for unwind. */ + remove = false; + break; + + default: + break; + } + + if (remove) { + tcg_op_remove(s, op); + } + } +} + #define TS_DEAD 1 #define TS_MEM 2 #define IS_DEAD_ARG(n) (arg_life & (DEAD_ARG << (n))) #define NEED_SYNC_ARG(n) (arg_life & (SYNC_ARG << (n))) +/* For liveness_pass_1, the register preferences for a given temp. */ +static inline TCGRegSet *la_temp_pref(TCGTemp *ts) +{ + return ts->state_ptr; +} + +/* For liveness_pass_1, reset the preferences for a given temp to the + * maximal regset for its type. + */ +static inline void la_reset_pref(TCGTemp *ts) +{ + *la_temp_pref(ts) + = (ts->state == TS_DEAD ? 0 : tcg_target_available_regs[ts->type]); +} + /* liveness analysis: end of function: all temps are dead, and globals should be in memory. */ -static void tcg_la_func_end(TCGContext *s) +static void la_func_end(TCGContext *s, int ng, int nt) { - int ng = s->nb_globals; - int nt = s->nb_temps; int i; for (i = 0; i < ng; ++i) { s->temps[i].state = TS_DEAD | TS_MEM; + la_reset_pref(&s->temps[i]); } for (i = ng; i < nt; ++i) { s->temps[i].state = TS_DEAD; + la_reset_pref(&s->temps[i]); } } /* liveness analysis: end of basic block: all temps are dead, globals and local temps should be in memory. */ -static void tcg_la_bb_end(TCGContext *s) +static void la_bb_end(TCGContext *s, int ng, int nt) { - int ng = s->nb_globals; - int nt = s->nb_temps; int i; for (i = 0; i < ng; ++i) { s->temps[i].state = TS_DEAD | TS_MEM; + la_reset_pref(&s->temps[i]); } for (i = ng; i < nt; ++i) { s->temps[i].state = (s->temps[i].temp_local ? TS_DEAD | TS_MEM : TS_DEAD); + la_reset_pref(&s->temps[i]); + } +} + +/* liveness analysis: sync globals back to memory. */ +static void la_global_sync(TCGContext *s, int ng) +{ + int i; + + for (i = 0; i < ng; ++i) { + int state = s->temps[i].state; + s->temps[i].state = state | TS_MEM; + if (state == TS_DEAD) { + /* If the global was previously dead, reset prefs. */ + la_reset_pref(&s->temps[i]); + } + } +} + +/* liveness analysis: sync globals back to memory and kill. */ +static void la_global_kill(TCGContext *s, int ng) +{ + int i; + + for (i = 0; i < ng; i++) { + s->temps[i].state = TS_DEAD | TS_MEM; + la_reset_pref(&s->temps[i]); + } +} + +/* liveness analysis: note live globals crossing calls. */ +static void la_cross_call(TCGContext *s, int nt) +{ + TCGRegSet mask = ~tcg_target_call_clobber_regs; + int i; + + for (i = 0; i < nt; i++) { + TCGTemp *ts = &s->temps[i]; + if (!(ts->state & TS_DEAD)) { + TCGRegSet *pset = la_temp_pref(ts); + TCGRegSet set = *pset; + + set &= mask; + /* If the combination is not possible, restart. */ + if (set == 0) { + set = tcg_target_available_regs[ts->type] & mask; + } + *pset = set; + } } } @@ -2265,16 +2468,25 @@ static void tcg_la_bb_end(TCGContext *s) static void liveness_pass_1(TCGContext *s) { int nb_globals = s->nb_globals; + int nb_temps = s->nb_temps; TCGOp *op, *op_prev; + TCGRegSet *prefs; + int i; + + prefs = tcg_malloc(sizeof(TCGRegSet) * nb_temps); + for (i = 0; i < nb_temps; ++i) { + s->temps[i].state_ptr = prefs + i; + } - tcg_la_func_end(s); + /* ??? Should be redundant with the exit_tb that ends the TB. */ + la_func_end(s, nb_globals, nb_temps); QTAILQ_FOREACH_REVERSE_SAFE(op, &s->ops, TCGOpHead, link, op_prev) { - int i, nb_iargs, nb_oargs; + int nb_iargs, nb_oargs; TCGOpcode opc_new, opc_new2; bool have_opc_new2; TCGLifeData arg_life = 0; - TCGTemp *arg_ts; + TCGTemp *ts; TCGOpcode opc = op->opc; const TCGOpDef *def = &tcg_op_defs[opc]; @@ -2282,6 +2494,7 @@ static void liveness_pass_1(TCGContext *s) case INDEX_op_call: { int call_flags; + int nb_call_regs; nb_oargs = TCGOP_CALLO(op); nb_iargs = TCGOP_CALLI(op); @@ -2290,53 +2503,74 @@ static void liveness_pass_1(TCGContext *s) /* pure functions can be removed if their result is unused */ if (call_flags & TCG_CALL_NO_SIDE_EFFECTS) { for (i = 0; i < nb_oargs; i++) { - arg_ts = arg_temp(op->args[i]); - if (arg_ts->state != TS_DEAD) { + ts = arg_temp(op->args[i]); + if (ts->state != TS_DEAD) { goto do_not_remove_call; } } goto do_remove; - } else { - do_not_remove_call: + } + do_not_remove_call: - /* output args are dead */ - for (i = 0; i < nb_oargs; i++) { - arg_ts = arg_temp(op->args[i]); - if (arg_ts->state & TS_DEAD) { - arg_life |= DEAD_ARG << i; - } - if (arg_ts->state & TS_MEM) { - arg_life |= SYNC_ARG << i; - } - arg_ts->state = TS_DEAD; + /* Output args are dead. */ + for (i = 0; i < nb_oargs; i++) { + ts = arg_temp(op->args[i]); + if (ts->state & TS_DEAD) { + arg_life |= DEAD_ARG << i; } + if (ts->state & TS_MEM) { + arg_life |= SYNC_ARG << i; + } + ts->state = TS_DEAD; + la_reset_pref(ts); - if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | - TCG_CALL_NO_READ_GLOBALS))) { - /* globals should go back to memory */ - for (i = 0; i < nb_globals; i++) { - s->temps[i].state = TS_DEAD | TS_MEM; - } - } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { - /* globals should be synced to memory */ - for (i = 0; i < nb_globals; i++) { - s->temps[i].state |= TS_MEM; - } + /* Not used -- it will be tcg_target_call_oarg_regs[i]. */ + op->output_pref[i] = 0; + } + + if (!(call_flags & (TCG_CALL_NO_WRITE_GLOBALS | + TCG_CALL_NO_READ_GLOBALS))) { + la_global_kill(s, nb_globals); + } else if (!(call_flags & TCG_CALL_NO_READ_GLOBALS)) { + la_global_sync(s, nb_globals); + } + + /* Record arguments that die in this helper. */ + for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { + ts = arg_temp(op->args[i]); + if (ts && ts->state & TS_DEAD) { + arg_life |= DEAD_ARG << i; } + } - /* record arguments that die in this helper */ - for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg_ts = arg_temp(op->args[i]); - if (arg_ts && arg_ts->state & TS_DEAD) { - arg_life |= DEAD_ARG << i; - } + /* For all live registers, remove call-clobbered prefs. */ + la_cross_call(s, nb_temps); + + nb_call_regs = ARRAY_SIZE(tcg_target_call_iarg_regs); + + /* Input arguments are live for preceding opcodes. */ + for (i = 0; i < nb_iargs; i++) { + ts = arg_temp(op->args[i + nb_oargs]); + if (ts && ts->state & TS_DEAD) { + /* For those arguments that die, and will be allocated + * in registers, clear the register set for that arg, + * to be filled in below. For args that will be on + * the stack, reset to any available reg. + */ + *la_temp_pref(ts) + = (i < nb_call_regs ? 0 : + tcg_target_available_regs[ts->type]); + ts->state &= ~TS_DEAD; } - /* input arguments are live for preceding opcodes */ - for (i = nb_oargs; i < nb_iargs + nb_oargs; i++) { - arg_ts = arg_temp(op->args[i]); - if (arg_ts) { - arg_ts->state &= ~TS_DEAD; - } + } + + /* For each input argument, add its input register to prefs. + If a temp is used once, this produces a single set bit. */ + for (i = 0; i < MIN(nb_call_regs, nb_iargs); i++) { + ts = arg_temp(op->args[i + nb_oargs]); + if (ts) { + tcg_regset_set_reg(*la_temp_pref(ts), + tcg_target_call_iarg_regs[i]); } } } @@ -2345,7 +2579,9 @@ static void liveness_pass_1(TCGContext *s) break; case INDEX_op_discard: /* mark the temporary as dead */ - arg_temp(op->args[0])->state = TS_DEAD; + ts = arg_temp(op->args[0]); + ts->state = TS_DEAD; + la_reset_pref(ts); break; case INDEX_op_add2_i32: @@ -2440,43 +2676,96 @@ static void liveness_pass_1(TCGContext *s) goto do_not_remove; } } - do_remove: - tcg_op_remove(s, op); - } else { - do_not_remove: - /* output args are dead */ - for (i = 0; i < nb_oargs; i++) { - arg_ts = arg_temp(op->args[i]); - if (arg_ts->state & TS_DEAD) { - arg_life |= DEAD_ARG << i; - } - if (arg_ts->state & TS_MEM) { - arg_life |= SYNC_ARG << i; - } - arg_ts->state = TS_DEAD; + goto do_remove; + } + goto do_not_remove; + + do_remove: + tcg_op_remove(s, op); + break; + + do_not_remove: + for (i = 0; i < nb_oargs; i++) { + ts = arg_temp(op->args[i]); + + /* Remember the preference of the uses that followed. */ + op->output_pref[i] = *la_temp_pref(ts); + + /* Output args are dead. */ + if (ts->state & TS_DEAD) { + arg_life |= DEAD_ARG << i; + } + if (ts->state & TS_MEM) { + arg_life |= SYNC_ARG << i; } + ts->state = TS_DEAD; + la_reset_pref(ts); + } - /* if end of basic block, update */ - if (def->flags & TCG_OPF_BB_END) { - tcg_la_bb_end(s); - } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { - /* globals should be synced to memory */ - for (i = 0; i < nb_globals; i++) { - s->temps[i].state |= TS_MEM; - } + /* If end of basic block, update. */ + if (def->flags & TCG_OPF_BB_EXIT) { + la_func_end(s, nb_globals, nb_temps); + } else if (def->flags & TCG_OPF_BB_END) { + la_bb_end(s, nb_globals, nb_temps); + } else if (def->flags & TCG_OPF_SIDE_EFFECTS) { + la_global_sync(s, nb_globals); + if (def->flags & TCG_OPF_CALL_CLOBBER) { + la_cross_call(s, nb_temps); } + } - /* record arguments that die in this opcode */ - for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { - arg_ts = arg_temp(op->args[i]); - if (arg_ts->state & TS_DEAD) { - arg_life |= DEAD_ARG << i; - } + /* Record arguments that die in this opcode. */ + for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { + ts = arg_temp(op->args[i]); + if (ts->state & TS_DEAD) { + arg_life |= DEAD_ARG << i; + } + } + + /* Input arguments are live for preceding opcodes. */ + for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { + ts = arg_temp(op->args[i]); + if (ts->state & TS_DEAD) { + /* For operands that were dead, initially allow + all regs for the type. */ + *la_temp_pref(ts) = tcg_target_available_regs[ts->type]; + ts->state &= ~TS_DEAD; + } + } + + /* Incorporate constraints for this operand. */ + switch (opc) { + case INDEX_op_mov_i32: + case INDEX_op_mov_i64: + /* Note that these are TCG_OPF_NOT_PRESENT and do not + have proper constraints. That said, special case + moves to propagate preferences backward. */ + if (IS_DEAD_ARG(1)) { + *la_temp_pref(arg_temp(op->args[0])) + = *la_temp_pref(arg_temp(op->args[1])); } - /* input arguments are live for preceding opcodes */ + break; + + default: for (i = nb_oargs; i < nb_oargs + nb_iargs; i++) { - arg_temp(op->args[i])->state &= ~TS_DEAD; + const TCGArgConstraint *ct = &def->args_ct[i]; + TCGRegSet set, *pset; + + ts = arg_temp(op->args[i]); + pset = la_temp_pref(ts); + set = *pset; + + set &= ct->u.regs; + if (ct->ct & TCG_CT_IALIAS) { + set &= op->output_pref[ct->alias_index]; + } + /* If the combination is not possible, restart. */ + if (set == 0) { + set = ct->u.regs; + } + *pset = set; } + break; } break; } @@ -2727,7 +3016,7 @@ static void temp_allocate_frame(TCGContext *s, TCGTemp *ts) s->current_frame_offset += sizeof(tcg_target_long); } -static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet); +static void temp_load(TCGContext *, TCGTemp *, TCGRegSet, TCGRegSet, TCGRegSet); /* Mark a temporary as free or dead. If 'free_or_dead' is negative, mark it free; otherwise mark it dead. */ @@ -2755,8 +3044,8 @@ static inline void temp_dead(TCGContext *s, TCGTemp *ts) registers needs to be allocated to store a constant. If 'free_or_dead' is non-zero, subsequently release the temporary; if it is positive, the temp is dead; if it is negative, the temp is free. */ -static void temp_sync(TCGContext *s, TCGTemp *ts, - TCGRegSet allocated_regs, int free_or_dead) +static void temp_sync(TCGContext *s, TCGTemp *ts, TCGRegSet allocated_regs, + TCGRegSet preferred_regs, int free_or_dead) { if (ts->fixed_reg) { return; @@ -2776,7 +3065,7 @@ static void temp_sync(TCGContext *s, TCGTemp *ts, break; } temp_load(s, ts, tcg_target_available_regs[ts->type], - allocated_regs); + allocated_regs, preferred_regs); /* fallthrough */ case TEMP_VAL_REG: @@ -2803,35 +3092,76 @@ static void tcg_reg_free(TCGContext *s, TCGReg reg, TCGRegSet allocated_regs) { TCGTemp *ts = s->reg_to_temp[reg]; if (ts != NULL) { - temp_sync(s, ts, allocated_regs, -1); + temp_sync(s, ts, allocated_regs, 0, -1); } } -/* Allocate a register belonging to reg1 & ~reg2 */ -static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs, - TCGRegSet allocated_regs, bool rev) +/** + * tcg_reg_alloc: + * @required_regs: Set of registers in which we must allocate. + * @allocated_regs: Set of registers which must be avoided. + * @preferred_regs: Set of registers we should prefer. + * @rev: True if we search the registers in "indirect" order. + * + * The allocated register must be in @required_regs & ~@allocated_regs, + * but if we can put it in @preferred_regs we may save a move later. + */ +static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet required_regs, + TCGRegSet allocated_regs, + TCGRegSet preferred_regs, bool rev) { - int i, n = ARRAY_SIZE(tcg_target_reg_alloc_order); + int i, j, f, n = ARRAY_SIZE(tcg_target_reg_alloc_order); + TCGRegSet reg_ct[2]; const int *order; - TCGReg reg; - TCGRegSet reg_ct; - reg_ct = desired_regs & ~allocated_regs; + reg_ct[1] = required_regs & ~allocated_regs; + tcg_debug_assert(reg_ct[1] != 0); + reg_ct[0] = reg_ct[1] & preferred_regs; + + /* Skip the preferred_regs option if it cannot be satisfied, + or if the preference made no difference. */ + f = reg_ct[0] == 0 || reg_ct[0] == reg_ct[1]; + order = rev ? indirect_reg_alloc_order : tcg_target_reg_alloc_order; - /* first try free registers */ - for(i = 0; i < n; i++) { - reg = order[i]; - if (tcg_regset_test_reg(reg_ct, reg) && s->reg_to_temp[reg] == NULL) - return reg; + /* Try free registers, preferences first. */ + for (j = f; j < 2; j++) { + TCGRegSet set = reg_ct[j]; + + if (tcg_regset_single(set)) { + /* One register in the set. */ + TCGReg reg = tcg_regset_first(set); + if (s->reg_to_temp[reg] == NULL) { + return reg; + } + } else { + for (i = 0; i < n; i++) { + TCGReg reg = order[i]; + if (s->reg_to_temp[reg] == NULL && + tcg_regset_test_reg(set, reg)) { + return reg; + } + } + } } - /* XXX: do better spill choice */ - for(i = 0; i < n; i++) { - reg = order[i]; - if (tcg_regset_test_reg(reg_ct, reg)) { + /* We must spill something. */ + for (j = f; j < 2; j++) { + TCGRegSet set = reg_ct[j]; + + if (tcg_regset_single(set)) { + /* One register in the set. */ + TCGReg reg = tcg_regset_first(set); tcg_reg_free(s, reg, allocated_regs); return reg; + } else { + for (i = 0; i < n; i++) { + TCGReg reg = order[i]; + if (tcg_regset_test_reg(set, reg)) { + tcg_reg_free(s, reg, allocated_regs); + return reg; + } + } } } @@ -2841,7 +3171,7 @@ static TCGReg tcg_reg_alloc(TCGContext *s, TCGRegSet desired_regs, /* Make sure the temporary is in a register. If needed, allocate the register from DESIRED while avoiding ALLOCATED. */ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, - TCGRegSet allocated_regs) + TCGRegSet allocated_regs, TCGRegSet preferred_regs) { TCGReg reg; @@ -2849,12 +3179,14 @@ static void temp_load(TCGContext *s, TCGTemp *ts, TCGRegSet desired_regs, case TEMP_VAL_REG: return; case TEMP_VAL_CONST: - reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); + reg = tcg_reg_alloc(s, desired_regs, allocated_regs, + preferred_regs, ts->indirect_base); tcg_out_movi(s, ts->type, reg, ts->val); ts->mem_coherent = 0; break; case TEMP_VAL_MEM: - reg = tcg_reg_alloc(s, desired_regs, allocated_regs, ts->indirect_base); + reg = tcg_reg_alloc(s, desired_regs, allocated_regs, + preferred_regs, ts->indirect_base); tcg_out_ld(s, ts->type, reg, ts->mem_base->reg, ts->mem_offset); ts->mem_coherent = 1; break; @@ -2924,7 +3256,8 @@ static void tcg_reg_alloc_bb_end(TCGContext *s, TCGRegSet allocated_regs) } static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, - tcg_target_ulong val, TCGLifeData arg_life) + tcg_target_ulong val, TCGLifeData arg_life, + TCGRegSet preferred_regs) { if (ots->fixed_reg) { /* For fixed registers, we do not do any constant propagation. */ @@ -2940,7 +3273,7 @@ static void tcg_reg_alloc_do_movi(TCGContext *s, TCGTemp *ots, ots->val = val; ots->mem_coherent = 0; if (NEED_SYNC_ARG(0)) { - temp_sync(s, ots, s->reserved_regs, IS_DEAD_ARG(0)); + temp_sync(s, ots, s->reserved_regs, preferred_regs, IS_DEAD_ARG(0)); } else if (IS_DEAD_ARG(0)) { temp_dead(s, ots); } @@ -2951,17 +3284,18 @@ static void tcg_reg_alloc_movi(TCGContext *s, const TCGOp *op) TCGTemp *ots = arg_temp(op->args[0]); tcg_target_ulong val = op->args[1]; - tcg_reg_alloc_do_movi(s, ots, val, op->life); + tcg_reg_alloc_do_movi(s, ots, val, op->life, op->output_pref[0]); } static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) { const TCGLifeData arg_life = op->life; - TCGRegSet allocated_regs; + TCGRegSet allocated_regs, preferred_regs; TCGTemp *ts, *ots; TCGType otype, itype; allocated_regs = s->reserved_regs; + preferred_regs = op->output_pref[0]; ots = arg_temp(op->args[0]); ts = arg_temp(op->args[1]); @@ -2975,7 +3309,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) if (IS_DEAD_ARG(1)) { temp_dead(s, ts); } - tcg_reg_alloc_do_movi(s, ots, val, arg_life); + tcg_reg_alloc_do_movi(s, ots, val, arg_life, preferred_regs); return; } @@ -2984,7 +3318,8 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) the SOURCE value into its own register first, that way we don't have to reload SOURCE the next time it is used. */ if (ts->val_type == TEMP_VAL_MEM) { - temp_load(s, ts, tcg_target_available_regs[itype], allocated_regs); + temp_load(s, ts, tcg_target_available_regs[itype], + allocated_regs, preferred_regs); } tcg_debug_assert(ts->val_type == TEMP_VAL_REG); @@ -3014,7 +3349,8 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) input one. */ tcg_regset_set_reg(allocated_regs, ts->reg); ots->reg = tcg_reg_alloc(s, tcg_target_available_regs[otype], - allocated_regs, ots->indirect_base); + allocated_regs, preferred_regs, + ots->indirect_base); } tcg_out_mov(s, otype, ots->reg, ts->reg); } @@ -3022,7 +3358,7 @@ static void tcg_reg_alloc_mov(TCGContext *s, const TCGOp *op) ots->mem_coherent = 0; s->reg_to_temp[ots->reg] = ots; if (NEED_SYNC_ARG(0)) { - temp_sync(s, ots, allocated_regs, 0); + temp_sync(s, ots, allocated_regs, 0, 0); } } } @@ -3054,6 +3390,8 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* satisfy input constraints */ for (k = 0; k < nb_iargs; k++) { + TCGRegSet i_preferred_regs, o_preferred_regs; + i = def->sorted_args[nb_oargs + k]; arg = op->args[i]; arg_ct = &def->args_ct[i]; @@ -3064,17 +3402,18 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) /* constant is OK for instruction */ const_args[i] = 1; new_args[i] = ts->val; - goto iarg_end; + continue; } - temp_load(s, ts, arg_ct->u.regs, i_allocated_regs); - + i_preferred_regs = o_preferred_regs = 0; if (arg_ct->ct & TCG_CT_IALIAS) { + o_preferred_regs = op->output_pref[arg_ct->alias_index]; if (ts->fixed_reg) { /* if fixed register, we must allocate a new register if the alias is not the same register */ - if (arg != op->args[arg_ct->alias_index]) + if (arg != op->args[arg_ct->alias_index]) { goto allocate_in_reg; + } } else { /* if the input is aliased to an output and if it is not dead after the instruction, we must allocate @@ -3082,33 +3421,42 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) if (!IS_DEAD_ARG(i)) { goto allocate_in_reg; } + /* check if the current register has already been allocated for another input aliased to an output */ - int k2, i2; - for (k2 = 0 ; k2 < k ; k2++) { - i2 = def->sorted_args[nb_oargs + k2]; - if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && - (new_args[i2] == ts->reg)) { - goto allocate_in_reg; + if (ts->val_type == TEMP_VAL_REG) { + int k2, i2; + reg = ts->reg; + for (k2 = 0 ; k2 < k ; k2++) { + i2 = def->sorted_args[nb_oargs + k2]; + if ((def->args_ct[i2].ct & TCG_CT_IALIAS) && + reg == new_args[i2]) { + goto allocate_in_reg; + } } } + i_preferred_regs = o_preferred_regs; } } + + temp_load(s, ts, arg_ct->u.regs, i_allocated_regs, i_preferred_regs); reg = ts->reg; + if (tcg_regset_test_reg(arg_ct->u.regs, reg)) { /* nothing to do : the constraint is satisfied */ } else { allocate_in_reg: /* allocate a new register matching the constraint and move the temporary register into it */ + temp_load(s, ts, tcg_target_available_regs[ts->type], + i_allocated_regs, 0); reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs, - ts->indirect_base); + o_preferred_regs, ts->indirect_base); tcg_out_mov(s, ts->type, reg, ts->reg); } new_args[i] = reg; const_args[i] = 0; tcg_regset_set_reg(i_allocated_regs, reg); - iarg_end: ; } /* mark dead temporaries and free the associated registers */ @@ -3147,7 +3495,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) } else if (arg_ct->ct & TCG_CT_NEWREG) { reg = tcg_reg_alloc(s, arg_ct->u.regs, i_allocated_regs | o_allocated_regs, - ts->indirect_base); + op->output_pref[k], ts->indirect_base); } else { /* if fixed register, we try to use it */ reg = ts->reg; @@ -3156,7 +3504,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) goto oarg_end; } reg = tcg_reg_alloc(s, arg_ct->u.regs, o_allocated_regs, - ts->indirect_base); + op->output_pref[k], ts->indirect_base); } tcg_regset_set_reg(o_allocated_regs, reg); /* if a fixed register is used, then a move will be done afterwards */ @@ -3192,7 +3540,7 @@ static void tcg_reg_alloc_op(TCGContext *s, const TCGOp *op) tcg_out_mov(s, ts->type, ts->reg, reg); } if (NEED_SYNC_ARG(i)) { - temp_sync(s, ts, o_allocated_regs, IS_DEAD_ARG(i)); + temp_sync(s, ts, o_allocated_regs, 0, IS_DEAD_ARG(i)); } else if (IS_DEAD_ARG(i)) { temp_dead(s, ts); } @@ -3248,7 +3596,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) if (arg != TCG_CALL_DUMMY_ARG) { ts = arg_temp(arg); temp_load(s, ts, tcg_target_available_regs[ts->type], - s->reserved_regs); + s->reserved_regs, 0); tcg_out_st(s, ts->type, ts->reg, TCG_REG_CALL_STACK, stack_offset); } #ifndef TCG_TARGET_STACK_GROWSUP @@ -3263,17 +3611,18 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) if (arg != TCG_CALL_DUMMY_ARG) { ts = arg_temp(arg); reg = tcg_target_call_iarg_regs[i]; - tcg_reg_free(s, reg, allocated_regs); if (ts->val_type == TEMP_VAL_REG) { if (ts->reg != reg) { + tcg_reg_free(s, reg, allocated_regs); tcg_out_mov(s, ts->type, reg, ts->reg); } } else { TCGRegSet arg_set = 0; + tcg_reg_free(s, reg, allocated_regs); tcg_regset_set_reg(arg_set, reg); - temp_load(s, ts, arg_set, allocated_regs); + temp_load(s, ts, arg_set, allocated_regs, 0); } tcg_regset_set_reg(allocated_regs, reg); @@ -3326,7 +3675,7 @@ static void tcg_reg_alloc_call(TCGContext *s, TCGOp *op) ts->mem_coherent = 0; s->reg_to_temp[reg] = ts; if (NEED_SYNC_ARG(i)) { - temp_sync(s, ts, allocated_regs, IS_DEAD_ARG(i)); + temp_sync(s, ts, allocated_regs, 0, IS_DEAD_ARG(i)); } else if (IS_DEAD_ARG(i)) { temp_dead(s, ts); } @@ -3476,7 +3825,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) && qemu_log_in_addr_range(tb->pc))) { qemu_log_lock(); qemu_log("OP:\n"); - tcg_dump_ops(s); + tcg_dump_ops(s, false); qemu_log("\n"); qemu_log_unlock(); } @@ -3495,6 +3844,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) atomic_set(&prof->la_time, prof->la_time - profile_getclock()); #endif + reachable_code_pass(s); liveness_pass_1(s); if (s->nb_indirects > 0) { @@ -3503,7 +3853,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) && qemu_log_in_addr_range(tb->pc))) { qemu_log_lock(); qemu_log("OP before indirect lowering:\n"); - tcg_dump_ops(s); + tcg_dump_ops(s, false); qemu_log("\n"); qemu_log_unlock(); } @@ -3524,7 +3874,7 @@ int tcg_gen_code(TCGContext *s, TranslationBlock *tb) && qemu_log_in_addr_range(tb->pc))) { qemu_log_lock(); qemu_log("OP after optimization and liveness analysis:\n"); - tcg_dump_ops(s); + tcg_dump_ops(s, true); qemu_log("\n"); qemu_log_unlock(); } diff --git a/tcg/tcg.h b/tcg/tcg.h index ade692fdf5..3a629991ca 100644 --- a/tcg/tcg.h +++ b/tcg/tcg.h @@ -244,7 +244,8 @@ typedef struct TCGRelocation { typedef struct TCGLabel { unsigned has_value : 1; - unsigned id : 31; + unsigned id : 15; + unsigned refs : 16; union { uintptr_t value; tcg_insn_unit *value_ptr; @@ -462,11 +463,13 @@ typedef TCGv_ptr TCGv_env; /* call flags */ /* Helper does not read globals (either directly or through an exception). It implies TCG_CALL_NO_WRITE_GLOBALS. */ -#define TCG_CALL_NO_READ_GLOBALS 0x0010 +#define TCG_CALL_NO_READ_GLOBALS 0x0001 /* Helper does not write globals */ -#define TCG_CALL_NO_WRITE_GLOBALS 0x0020 +#define TCG_CALL_NO_WRITE_GLOBALS 0x0002 /* Helper can be safely suppressed if the return value is not used. */ -#define TCG_CALL_NO_SIDE_EFFECTS 0x0040 +#define TCG_CALL_NO_SIDE_EFFECTS 0x0004 +/* Helper is QEMU_NORETURN. */ +#define TCG_CALL_NO_RETURN 0x0008 /* convenience version of most used call flags */ #define TCG_CALL_NO_RWG TCG_CALL_NO_READ_GLOBALS @@ -616,6 +619,9 @@ typedef struct TCGOp { /* Arguments for the opcode. */ TCGArg args[MAX_OPC_PARAM]; + + /* Register preferences for the output(s). */ + TCGRegSet output_pref[2]; } TCGOp; #define TCGOP_CALLI(X) (X)->param1 @@ -1024,20 +1030,22 @@ typedef struct TCGArgConstraint { /* Bits for TCGOpDef->flags, 8 bits available. */ enum { + /* Instruction exits the translation block. */ + TCG_OPF_BB_EXIT = 0x01, /* Instruction defines the end of a basic block. */ - TCG_OPF_BB_END = 0x01, + TCG_OPF_BB_END = 0x02, /* Instruction clobbers call registers and potentially update globals. */ - TCG_OPF_CALL_CLOBBER = 0x02, + TCG_OPF_CALL_CLOBBER = 0x04, /* Instruction has side effects: it cannot be removed if its outputs are not used, and might trigger exceptions. */ - TCG_OPF_SIDE_EFFECTS = 0x04, + TCG_OPF_SIDE_EFFECTS = 0x08, /* Instruction operands are 64-bits (otherwise 32-bits). */ - TCG_OPF_64BIT = 0x08, + TCG_OPF_64BIT = 0x10, /* Instruction is optional and not implemented by the host, or insn is generic and should not be implemened by the host. */ - TCG_OPF_NOT_PRESENT = 0x10, + TCG_OPF_NOT_PRESENT = 0x20, /* Instruction operands are vectors. */ - TCG_OPF_VECTOR = 0x20, + TCG_OPF_VECTOR = 0x40, }; typedef struct TCGOpDef { @@ -1076,9 +1084,6 @@ TCGOp *tcg_op_insert_after(TCGContext *s, TCGOp *op, TCGOpcode opc); void tcg_optimize(TCGContext *s); -/* only used for debugging purposes */ -void tcg_dump_ops(TCGContext *s); - TCGv_i32 tcg_const_i32(int32_t val); TCGv_i64 tcg_const_i64(int64_t val); TCGv_i32 tcg_const_local_i32(int32_t val); diff --git a/tests/tcg/mips/mipsr5900/Makefile b/tests/tcg/mips/mipsr5900/Makefile index a1c388bc3c..27ee5d5f54 100644 --- a/tests/tcg/mips/mipsr5900/Makefile +++ b/tests/tcg/mips/mipsr5900/Makefile @@ -10,6 +10,8 @@ CFLAGS = -Wall -mabi=32 -march=r5900 -static TESTCASES = div1.tst TESTCASES += divu1.tst +TESTCASES += madd.tst +TESTCASES += maddu.tst TESTCASES += mflohi1.tst TESTCASES += mtlohi1.tst TESTCASES += mult.tst diff --git a/tests/tcg/mips/mipsr5900/madd.c b/tests/tcg/mips/mipsr5900/madd.c new file mode 100644 index 0000000000..f6f215e1c3 --- /dev/null +++ b/tests/tcg/mips/mipsr5900/madd.c @@ -0,0 +1,78 @@ +/* + * Test R5900-specific three-operand MADD and MADD1. + */ + +#include <stdio.h> +#include <inttypes.h> +#include <assert.h> + +int64_t madd(int64_t a, int32_t rs, int32_t rt) +{ + int32_t lo = a; + int32_t hi = a >> 32; + int32_t rd; + int64_t r; + + __asm__ __volatile__ ( + " mtlo %5\n" + " mthi %6\n" + " madd %0, %3, %4\n" + " mflo %1\n" + " mfhi %2\n" + : "=r" (rd), "=r" (lo), "=r" (hi) + : "r" (rs), "r" (rt), "r" (lo), "r" (hi)); + r = ((int64_t)hi << 32) | (uint32_t)lo; + + assert(a + (int64_t)rs * rt == r); + assert(rd == lo); + + return r; +} + +int64_t madd1(int64_t a, int32_t rs, int32_t rt) +{ + int32_t lo = a; + int32_t hi = a >> 32; + int32_t rd; + int64_t r; + + __asm__ __volatile__ ( + " mtlo1 %5\n" + " mthi1 %6\n" + " madd1 %0, %3, %4\n" + " mflo1 %1\n" + " mfhi1 %2\n" + : "=r" (rd), "=r" (lo), "=r" (hi) + : "r" (rs), "r" (rt), "r" (lo), "r" (hi)); + r = ((int64_t)hi << 32) | (uint32_t)lo; + + assert(a + (int64_t)rs * rt == r); + assert(rd == lo); + + return r; +} + +static int64_t madd_variants(int64_t a, int32_t rs, int32_t rt) +{ + int64_t rd = madd(a, rs, rt); + int64_t rd1 = madd1(a, rs, rt); + + assert(rd == rd1); + + return rd; +} + +static void verify_madd(int64_t a, int32_t rs, int32_t rt, int64_t expected) +{ + assert(madd_variants(a, rs, rt) == expected); + assert(madd_variants(a, -rs, rt) == a + a - expected); + assert(madd_variants(a, rs, -rt) == a + a - expected); + assert(madd_variants(a, -rs, -rt) == expected); +} + +int main() +{ + verify_madd(13, 17, 19, 336); + + return 0; +} diff --git a/tests/tcg/mips/mipsr5900/maddu.c b/tests/tcg/mips/mipsr5900/maddu.c new file mode 100644 index 0000000000..30936fb2b4 --- /dev/null +++ b/tests/tcg/mips/mipsr5900/maddu.c @@ -0,0 +1,70 @@ +/* + * Test R5900-specific three-operand MADDU and MADDU1. + */ + +#include <stdio.h> +#include <inttypes.h> +#include <assert.h> + +uint64_t maddu(uint64_t a, uint32_t rs, uint32_t rt) +{ + uint32_t lo = a; + uint32_t hi = a >> 32; + uint32_t rd; + uint64_t r; + + __asm__ __volatile__ ( + " mtlo %5\n" + " mthi %6\n" + " maddu %0, %3, %4\n" + " mflo %1\n" + " mfhi %2\n" + : "=r" (rd), "=r" (lo), "=r" (hi) + : "r" (rs), "r" (rt), "r" (lo), "r" (hi)); + r = ((uint64_t)hi << 32) | (uint32_t)lo; + + assert(a + (uint64_t)rs * rt == r); + assert(rd == lo); + + return r; +} + +uint64_t maddu1(uint64_t a, uint32_t rs, uint32_t rt) +{ + uint32_t lo = a; + uint32_t hi = a >> 32; + uint32_t rd; + uint64_t r; + + __asm__ __volatile__ ( + " mtlo1 %5\n" + " mthi1 %6\n" + " maddu1 %0, %3, %4\n" + " mflo1 %1\n" + " mfhi1 %2\n" + : "=r" (rd), "=r" (lo), "=r" (hi) + : "r" (rs), "r" (rt), "r" (lo), "r" (hi)); + r = ((uint64_t)hi << 32) | (uint32_t)lo; + + assert(a + (uint64_t)rs * rt == r); + assert(rd == lo); + + return r; +} + +static int64_t maddu_variants(int64_t a, int32_t rs, int32_t rt) +{ + int64_t rd = maddu(a, rs, rt); + int64_t rd1 = maddu1(a, rs, rt); + + assert(rd == rd1); + + return rd; +} + +int main() +{ + assert(maddu_variants(13, 17, 19) == 336); + + return 0; +} diff --git a/vl.c b/vl.c index 8353d3c718..0db5ad0246 100644 --- a/vl.c +++ b/vl.c @@ -191,7 +191,6 @@ int boot_menu; bool boot_strict; uint8_t *boot_splash_filedata; size_t boot_splash_filedata_size; -uint8_t qemu_extra_params_fw[2]; bool wakeup_suspend_enabled; int icount_align_option; @@ -338,10 +337,10 @@ static QemuOptsList qemu_boot_opts = { .type = QEMU_OPT_STRING, }, { .name = "splash-time", - .type = QEMU_OPT_STRING, + .type = QEMU_OPT_NUMBER, }, { .name = "reboot-timeout", - .type = QEMU_OPT_STRING, + .type = QEMU_OPT_NUMBER, }, { .name = "strict", .type = QEMU_OPT_BOOL, |