diff options
76 files changed, 709 insertions, 1220 deletions
diff --git a/MAINTAINERS b/MAINTAINERS index 2f4e8cf954..71c652be98 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -903,6 +903,14 @@ M: Alexander Graf <agraf@suse.de> S: Maintained F: device_tree.[ch] +Error reporting +M: Markus Armbruster <armbru@redhat.com> +S: Supported +F: include/qapi/error.h +F: include/qemu/error-report.h +F: util/error.c +F: util/qemu-error.c + GDB stub L: qemu-devel@nongnu.org S: Odd Fixes diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index c6eab6de30..40334d7561 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -229,7 +229,7 @@ qemu_irq *armv7m_init(MemoryRegion *system_memory, int mem_size, int num_irq, /* Hack to map an additional page of ram at the top of the address space. This stops qemu complaining about executing code outside RAM when returning from an exception. */ - memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000, &error_abort); + memory_region_init_ram(hack, NULL, "armv7m.hack", 0x1000, &error_fatal); vmstate_register_ram_global(hack); memory_region_add_subregion(system_memory, 0xfffff000, hack); diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index c55fab8131..d934980efa 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -259,7 +259,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, /* Internal ROM */ memory_region_init_ram(&s->irom_mem, NULL, "exynos4210.irom", - EXYNOS4210_IROM_SIZE, &error_abort); + EXYNOS4210_IROM_SIZE, &error_fatal); vmstate_register_ram_global(&s->irom_mem); memory_region_set_readonly(&s->irom_mem, true); memory_region_add_subregion(system_mem, EXYNOS4210_IROM_BASE_ADDR, @@ -275,7 +275,7 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, /* Internal RAM */ memory_region_init_ram(&s->iram_mem, NULL, "exynos4210.iram", - EXYNOS4210_IRAM_SIZE, &error_abort); + EXYNOS4210_IRAM_SIZE, &error_fatal); vmstate_register_ram_global(&s->iram_mem); memory_region_add_subregion(system_mem, EXYNOS4210_IRAM_BASE_ADDR, &s->iram_mem); @@ -284,14 +284,14 @@ Exynos4210State *exynos4210_init(MemoryRegion *system_mem, mem_size = ram_size; if (mem_size > EXYNOS4210_DRAM_MAX_SIZE) { memory_region_init_ram(&s->dram1_mem, NULL, "exynos4210.dram1", - mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_abort); + mem_size - EXYNOS4210_DRAM_MAX_SIZE, &error_fatal); vmstate_register_ram_global(&s->dram1_mem); memory_region_add_subregion(system_mem, EXYNOS4210_DRAM1_BASE_ADDR, &s->dram1_mem); mem_size = EXYNOS4210_DRAM_MAX_SIZE; } memory_region_init_ram(&s->dram0_mem, NULL, "exynos4210.dram0", mem_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->dram0_mem); memory_region_add_subregion(system_mem, EXYNOS4210_DRAM0_BASE_ADDR, &s->dram0_mem); diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index f8353a7874..960bc39430 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -281,7 +281,7 @@ static void calxeda_init(MachineState *machine, enum cxmachines machine_id) sysram = g_new(MemoryRegion, 1); memory_region_init_ram(sysram, NULL, "highbank.sysram", 0x8000, - &error_abort); + &error_fatal); memory_region_add_subregion(sysmem, 0xfff88000, sysram); if (bios_name != NULL) { sysboot_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); diff --git a/hw/arm/integratorcp.c b/hw/arm/integratorcp.c index 0fbbf997ea..d87d36ff57 100644 --- a/hw/arm/integratorcp.c +++ b/hw/arm/integratorcp.c @@ -266,7 +266,7 @@ static int integratorcm_init(SysBusDevice *dev) s->cm_refcnt_offset = muldiv64(qemu_clock_get_ns(QEMU_CLOCK_VIRTUAL), 24, 1000); memory_region_init_ram(&s->flash, OBJECT(s), "integrator.flash", 0x100000, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->flash); memory_region_init_io(&s->iomem, OBJECT(s), &integratorcm_ops, s, diff --git a/hw/arm/mainstone.c b/hw/arm/mainstone.c index 0da02a67ec..03e9fa5a84 100644 --- a/hw/arm/mainstone.c +++ b/hw/arm/mainstone.c @@ -124,7 +124,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem, /* Setup CPU & memory */ mpu = pxa270_init(address_space_mem, mainstone_binfo.ram_size, cpu_model); memory_region_init_ram(rom, NULL, "mainstone.rom", MAINSTONE_ROM, - &error_abort); + &error_fatal); vmstate_register_ram_global(rom); memory_region_set_readonly(rom, true); memory_region_add_subregion(address_space_mem, 0, rom); diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 42f66b33e1..5cff3d4117 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -1599,7 +1599,7 @@ static void musicpal_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0, ram); memory_region_init_ram(sram, NULL, "musicpal.sram", MP_SRAM_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(sram); memory_region_add_subregion(address_space_mem, MP_SRAM_BASE, sram); diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 8873f9427c..6b1c076598 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -3872,7 +3872,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, s->sdram_size); memory_region_add_subregion(system_memory, OMAP_EMIFF_BASE, &s->emiff_ram); memory_region_init_ram(&s->imif_ram, NULL, "omap1.sram", s->sram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->imif_ram); memory_region_add_subregion(system_memory, OMAP_IMIF_BASE, &s->imif_ram); diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index 1ee2d610f7..98ee19f861 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -2271,7 +2271,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, s->sdram_size); memory_region_add_subregion(sysmem, OMAP2_Q2_BASE, &s->sdram); memory_region_init_ram(&s->sram, NULL, "omap2.sram", s->sram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->sram); memory_region_add_subregion(sysmem, OMAP2_SRAM_BASE, &s->sram); diff --git a/hw/arm/omap_sx1.c b/hw/arm/omap_sx1.c index 4b0f7f9c42..4de88f31b1 100644 --- a/hw/arm/omap_sx1.c +++ b/hw/arm/omap_sx1.c @@ -122,7 +122,7 @@ static void sx1_init(MachineState *machine, const int version) /* External Flash (EMIFS) */ memory_region_init_ram(flash, NULL, "omap_sx1.flash0-0", flash_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(flash); memory_region_set_readonly(flash, true); memory_region_add_subregion(address_space, OMAP_CS0_BASE, flash); @@ -166,7 +166,7 @@ static void sx1_init(MachineState *machine, const int version) (dinfo = drive_get(IF_PFLASH, 0, fl_idx)) != NULL) { MemoryRegion *flash_1 = g_new(MemoryRegion, 1); memory_region_init_ram(flash_1, NULL, "omap_sx1.flash1-0", flash1_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(flash_1); memory_region_set_readonly(flash_1, true); memory_region_add_subregion(address_space, OMAP_CS1_BASE, flash_1); diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 7f1cfb8f6a..1f84dbff18 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -213,7 +213,7 @@ static void palmte_init(MachineState *machine) /* External Flash (EMIFS) */ memory_region_init_ram(flash, NULL, "palmte.flash", flash_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(flash); memory_region_set_readonly(flash, true); memory_region_add_subregion(address_space_mem, OMAP_CS0_BASE, flash); diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index ec56b6172e..164260a9b6 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -2078,11 +2078,11 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, /* SDRAM & Internal Memory Storage */ memory_region_init_ram(&s->sdram, NULL, "pxa270.sdram", sdram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->sdram); memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); memory_region_init_ram(&s->internal, NULL, "pxa270.internal", 0x40000, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->internal); memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, &s->internal); @@ -2212,11 +2212,11 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) /* SDRAM & Internal Memory Storage */ memory_region_init_ram(&s->sdram, NULL, "pxa255.sdram", sdram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->sdram); memory_region_add_subregion(address_space, PXA2XX_SDRAM_BASE, &s->sdram); memory_region_init_ram(&s->internal, NULL, "pxa255.internal", - PXA2XX_INTERNAL_SIZE, &error_abort); + PXA2XX_INTERNAL_SIZE, &error_fatal); vmstate_register_ram_global(&s->internal); memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, &s->internal); diff --git a/hw/arm/realview.c b/hw/arm/realview.c index ef2788d3eb..23779ec274 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -151,13 +151,13 @@ static void realview_init(MachineState *machine, low_ram_size = ram_size - 0x20000000; ram_size = 0x20000000; memory_region_init_ram(ram_lo, NULL, "realview.lowmem", low_ram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(ram_lo); memory_region_add_subregion(sysmem, 0x20000000, ram_lo); } memory_region_init_ram(ram_hi, NULL, "realview.highmem", ram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(ram_hi); low_ram_size = ram_size; if (low_ram_size > 0x10000000) @@ -353,7 +353,7 @@ static void realview_init(MachineState *machine, BootROM happens to be in ROM/flash or in memory that isn't clobbered until after Linux boots the secondary CPUs. */ memory_region_init_ram(ram_hack, NULL, "realview.hack", 0x1000, - &error_abort); + &error_fatal); vmstate_register_ram_global(ram_hack); memory_region_add_subregion(sysmem, SMP_BOOT_ADDR, ram_hack); diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index fdb1010386..6c2cbcb203 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -913,7 +913,7 @@ static void spitz_common_init(MachineState *machine, sl_flash_register(mpu, (model == spitz) ? FLASH_128M : FLASH_1024M); - memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM, &error_abort); + memory_region_init_ram(rom, NULL, "spitz.rom", SPITZ_ROM, &error_fatal); vmstate_register_ram_global(rom); memory_region_set_readonly(rom, true); memory_region_add_subregion(address_space_mem, 0, rom); diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index ca4628b0fc..a76f051704 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -1231,13 +1231,13 @@ static void stellaris_init(const char *kernel_filename, const char *cpu_model, /* Flash programming is done via the SCU, so pretend it is ROM. */ memory_region_init_ram(flash, NULL, "stellaris.flash", flash_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(flash); memory_region_set_readonly(flash, true); memory_region_add_subregion(system_memory, 0, flash); memory_region_init_ram(sram, NULL, "stellaris.sram", sram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(sram); memory_region_add_subregion(system_memory, 0x20000000, sram); diff --git a/hw/arm/stm32f205_soc.c b/hw/arm/stm32f205_soc.c index 0f3bdc77b6..4d26a7ed91 100644 --- a/hw/arm/stm32f205_soc.c +++ b/hw/arm/stm32f205_soc.c @@ -71,7 +71,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) MemoryRegion *flash_alias = g_new(MemoryRegion, 1); memory_region_init_ram(flash, NULL, "STM32F205.flash", FLASH_SIZE, - &error_abort); + &error_fatal); memory_region_init_alias(flash_alias, NULL, "STM32F205.flash.alias", flash, 0, FLASH_SIZE); @@ -84,7 +84,7 @@ static void stm32f205_soc_realize(DeviceState *dev_soc, Error **errp) memory_region_add_subregion(system_memory, 0, flash_alias); memory_region_init_ram(sram, NULL, "STM32F205.sram", SRAM_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(sram); memory_region_add_subregion(system_memory, SRAM_BASE_ADDRESS, sram); diff --git a/hw/arm/tosa.c b/hw/arm/tosa.c index 73572ebe01..2c216e9c5d 100644 --- a/hw/arm/tosa.c +++ b/hw/arm/tosa.c @@ -227,7 +227,7 @@ static void tosa_init(MachineState *machine) mpu = pxa255_init(address_space_mem, tosa_binfo.ram_size); - memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM, &error_abort); + memory_region_init_ram(rom, NULL, "tosa.rom", TOSA_ROM, &error_fatal); vmstate_register_ram_global(rom); memory_region_set_readonly(rom, true); memory_region_add_subregion(address_space_mem, 0, rom); diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 0f8bf1ca5c..da8301a294 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -391,7 +391,7 @@ static void a15_daughterboard_init(const VexpressMachineState *vms, /* 0x2b0a0000: PL341 dynamic memory controller: not modelled */ /* 0x2e000000: system SRAM */ memory_region_init_ram(sram, NULL, "vexpress.a15sram", 0x10000, - &error_abort); + &error_fatal); vmstate_register_ram_global(sram); memory_region_add_subregion(sysmem, 0x2e000000, sram); @@ -671,13 +671,13 @@ static void vexpress_common_init(MachineState *machine) sram_size = 0x2000000; memory_region_init_ram(sram, NULL, "vexpress.sram", sram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(sram); memory_region_add_subregion(sysmem, map[VE_SRAM], sram); vram_size = 0x800000; memory_region_init_ram(vram, NULL, "vexpress.vram", vram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(vram); memory_region_add_subregion(sysmem, map[VE_VIDEORAM], vram); diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index a4e7b5c637..37dc0b0865 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -167,7 +167,7 @@ static void zynq_init(MachineState *machine) /* 256K of on-chip memory */ memory_region_init_ram(ocm_ram, NULL, "zynq.ocm_ram", 256 << 10, - &error_abort); + &error_fatal); vmstate_register_ram_global(ocm_ram); memory_region_add_subregion(address_space_mem, 0xFFFC0000, ocm_ram); diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 21855420dd..a9097f9b72 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -113,7 +113,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp) char *ocm_name = g_strdup_printf("zynqmp.ocm_ram_bank_%d", i); memory_region_init_ram(&s->ocm_ram[i], NULL, ocm_name, - XLNX_ZYNQMP_OCM_RAM_SIZE, &error_abort); + XLNX_ZYNQMP_OCM_RAM_SIZE, &error_fatal); vmstate_register_ram_global(&s->ocm_ram[i]); memory_region_add_subregion(get_system_memory(), XLNX_ZYNQMP_OCM_RAM_0_ADDRESS + diff --git a/hw/block/onenand.c b/hw/block/onenand.c index 1b2c893756..58eff508bf 100644 --- a/hw/block/onenand.c +++ b/hw/block/onenand.c @@ -786,7 +786,7 @@ static int onenand_initfn(SysBusDevice *sbd) s->otp = memset(g_malloc((64 + 2) << PAGE_SHIFT), 0xff, (64 + 2) << PAGE_SHIFT); memory_region_init_ram(&s->ram, OBJECT(s), "onenand.ram", - 0xc000 << s->shift, &error_abort); + 0xc000 << s->shift, &error_fatal); vmstate_register_ram_global(&s->ram); ram = memory_region_get_ram_ptr(&s->ram); s->boot[0] = ram + (0x0000 << s->shift); diff --git a/hw/core/loader.c b/hw/core/loader.c index a96a74e579..eb67f05ee2 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -740,7 +740,7 @@ static void *rom_set_mr(Rom *rom, Object *owner, const char *name) memory_region_init_resizeable_ram(rom->mr, owner, name, rom->datasize, rom->romsize, fw_cfg_resized, - &error_abort); + &error_fatal); memory_region_set_readonly(rom->mr, true); vmstate_register_ram_global(rom->mr); diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c index 2e8c2c74fb..d9484493b5 100644 --- a/hw/cris/axis_dev88.c +++ b/hw/cris/axis_dev88.c @@ -277,7 +277,7 @@ void axisdev88_init(MachineState *machine) /* The ETRAX-FS has 128Kb on chip ram, the docs refer to it as the internal memory. */ memory_region_init_ram(phys_intmem, NULL, "axisdev88.chipram", INTMEM_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(phys_intmem); memory_region_add_subregion(address_space_mem, 0x38000000, phys_intmem); diff --git a/hw/display/cg3.c b/hw/display/cg3.c index 34dcbc3119..d2a0d97320 100644 --- a/hw/display/cg3.c +++ b/hw/display/cg3.c @@ -281,7 +281,7 @@ static void cg3_initfn(Object *obj) CG3State *s = CG3(obj); memory_region_init_ram(&s->rom, NULL, "cg3.prom", FCODE_MAX_ROM_SIZE, - &error_abort); + &error_fatal); memory_region_set_readonly(&s->rom, true); sysbus_init_mmio(sbd, &s->rom); @@ -310,7 +310,7 @@ static void cg3_realizefn(DeviceState *dev, Error **errp) } memory_region_init_ram(&s->vram_mem, NULL, "cg3.vram", s->vram_size, - &error_abort); + &error_fatal); memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); vmstate_register_ram_global(&s->vram_mem); sysbus_init_mmio(sbd, &s->vram_mem); diff --git a/hw/display/qxl.c b/hw/display/qxl.c index 2288238d00..9c961dae93 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -1970,14 +1970,14 @@ static void qxl_realize_common(PCIQXLDevice *qxl, Error **errp) qxl->rom_size = qxl_rom_size(); memory_region_init_ram(&qxl->rom_bar, OBJECT(qxl), "qxl.vrom", - qxl->rom_size, &error_abort); + qxl->rom_size, &error_fatal); vmstate_register_ram(&qxl->rom_bar, &qxl->pci.qdev); init_qxl_rom(qxl); init_qxl_ram(qxl); qxl->guest_surfaces.cmds = g_new0(QXLPHYSICAL, qxl->ssd.num_surfaces); memory_region_init_ram(&qxl->vram_bar, OBJECT(qxl), "qxl.vram", - qxl->vram_size, &error_abort); + qxl->vram_size, &error_fatal); vmstate_register_ram(&qxl->vram_bar, &qxl->pci.qdev); memory_region_init_alias(&qxl->vram32_bar, OBJECT(qxl), "qxl.vram32", &qxl->vram_bar, 0, qxl->vram32_size); @@ -2079,7 +2079,7 @@ static void qxl_realize_secondary(PCIDevice *dev, Error **errp) qxl->id = device_id++; qxl_init_ramsize(qxl); memory_region_init_ram(&qxl->vga.vram, OBJECT(dev), "qxl.vgavram", - qxl->vga.vram_size, &error_abort); + qxl->vga.vram_size, &error_fatal); vmstate_register_ram(&qxl->vga.vram, &qxl->pci.qdev); qxl->vga.vram_ptr = memory_region_get_ram_ptr(&qxl->vga.vram); qxl->vga.con = graphic_console_init(DEVICE(dev), 0, &qxl_ops, qxl); diff --git a/hw/display/sm501.c b/hw/display/sm501.c index 15a5ba8000..3c3f97824b 100644 --- a/hw/display/sm501.c +++ b/hw/display/sm501.c @@ -1411,7 +1411,7 @@ void sm501_init(MemoryRegion *address_space_mem, uint32_t base, /* allocate local memory */ memory_region_init_ram(&s->local_mem_region, NULL, "sm501.local", - local_mem_bytes, &error_abort); + local_mem_bytes, &error_fatal); vmstate_register_ram_global(&s->local_mem_region); memory_region_set_log(&s->local_mem_region, true, DIRTY_MEMORY_VGA); s->local_mem = memory_region_get_ram_ptr(&s->local_mem_region); diff --git a/hw/display/tc6393xb.c b/hw/display/tc6393xb.c index f5f3f3e69d..516af1a5c3 100644 --- a/hw/display/tc6393xb.c +++ b/hw/display/tc6393xb.c @@ -584,7 +584,7 @@ TC6393xbState *tc6393xb_init(MemoryRegion *sysmem, uint32_t base, qemu_irq irq) memory_region_add_subregion(sysmem, base, &s->iomem); memory_region_init_ram(&s->vram, NULL, "tc6393xb.vram", 0x100000, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->vram); s->vram_ptr = memory_region_get_ram_ptr(&s->vram); memory_region_add_subregion(sysmem, base + 0x100000, &s->vram); diff --git a/hw/display/tcx.c b/hw/display/tcx.c index 6acdc2d282..463580094a 100644 --- a/hw/display/tcx.c +++ b/hw/display/tcx.c @@ -945,7 +945,7 @@ static void tcx_initfn(Object *obj) TCXState *s = TCX(obj); memory_region_init_ram(&s->rom, NULL, "tcx.prom", FCODE_MAX_ROM_SIZE, - &error_abort); + &error_fatal); memory_region_set_readonly(&s->rom, true); sysbus_init_mmio(sbd, &s->rom); @@ -1007,7 +1007,7 @@ static void tcx_realizefn(DeviceState *dev, Error **errp) char *fcode_filename; memory_region_init_ram(&s->vram_mem, OBJECT(s), "tcx.vram", - s->vram_size * (1 + 4 + 4), &error_abort); + s->vram_size * (1 + 4 + 4), &error_fatal); vmstate_register_ram_global(&s->vram_mem); memory_region_set_log(&s->vram_mem, true, DIRTY_MEMORY_VGA); vram_base = memory_region_get_ram_ptr(&s->vram_mem); diff --git a/hw/display/vga.c b/hw/display/vga.c index b35d523e65..9f6839488b 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -2139,7 +2139,7 @@ void vga_common_init(VGACommonState *s, Object *obj, bool global_vmstate) s->is_vbe_vmstate = 1; memory_region_init_ram(&s->vram, obj, "vga.vram", s->vram_size, - &error_abort); + &error_fatal); vmstate_register_ram(&s->vram, global_vmstate ? NULL : DEVICE(obj)); xen_register_framebuffer(&s->vram); s->vram_ptr = memory_region_get_ram_ptr(&s->vram); diff --git a/hw/display/vmware_vga.c b/hw/display/vmware_vga.c index 7f397d3c2e..8e9350981c 100644 --- a/hw/display/vmware_vga.c +++ b/hw/display/vmware_vga.c @@ -1244,7 +1244,7 @@ static void vmsvga_init(DeviceState *dev, struct vmsvga_state_s *s, s->fifo_size = SVGA_FIFO_SIZE; memory_region_init_ram(&s->fifo_ram, NULL, "vmsvga.fifo", s->fifo_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->fifo_ram); s->fifo_ptr = memory_region_get_ram_ptr(&s->fifo_ram); diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 56aecced7b..461c128d23 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -1400,7 +1400,7 @@ FWCfgState *pc_memory_init(PCMachineState *pcms, option_rom_mr = g_malloc(sizeof(*option_rom_mr)); memory_region_init_ram(option_rom_mr, NULL, "pc.rom", PC_ROM_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(option_rom_mr); memory_region_add_subregion_overlap(rom_memory, PC_ROM_MIN_VGA, diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index 662d99768e..579461fa1e 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -56,7 +56,7 @@ static void pc_isa_bios_init(MemoryRegion *rom_memory, isa_bios_size = MIN(flash_size, 128 * 1024); isa_bios = g_malloc(sizeof(*isa_bios)); memory_region_init_ram(isa_bios, NULL, "isa-bios", isa_bios_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(isa_bios); memory_region_add_subregion_overlap(rom_memory, 0x100000 - isa_bios_size, @@ -193,7 +193,7 @@ static void old_pc_system_rom_init(MemoryRegion *rom_memory, bool isapc_ram_fw) goto bios_error; } bios = g_malloc(sizeof(*bios)); - memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_abort); + memory_region_init_ram(bios, NULL, "pc.bios", bios_size, &error_fatal); vmstate_register_ram_global(bios); if (!isapc_ram_fw) { memory_region_set_readonly(bios, true); diff --git a/hw/input/milkymist-softusb.c b/hw/input/milkymist-softusb.c index 7b0f4db88d..8a02d35ca1 100644 --- a/hw/input/milkymist-softusb.c +++ b/hw/input/milkymist-softusb.c @@ -255,12 +255,12 @@ static int milkymist_softusb_init(SysBusDevice *dev) /* register pmem and dmem */ memory_region_init_ram(&s->pmem, OBJECT(s), "milkymist-softusb.pmem", - s->pmem_size, &error_abort); + s->pmem_size, &error_fatal); vmstate_register_ram_global(&s->pmem); s->pmem_ptr = memory_region_get_ram_ptr(&s->pmem); sysbus_init_mmio(dev, &s->pmem); memory_region_init_ram(&s->dmem, OBJECT(s), "milkymist-softusb.dmem", - s->dmem_size, &error_abort); + s->dmem_size, &error_fatal); vmstate_register_ram_global(&s->dmem); s->dmem_ptr = memory_region_get_ram_ptr(&s->dmem); sysbus_init_mmio(dev, &s->dmem); diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c index f63ab2b94d..b18dc7f7ea 100644 --- a/hw/m68k/an5206.c +++ b/hw/m68k/an5206.c @@ -54,7 +54,7 @@ static void an5206_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0, ram); /* Internal SRAM. */ - memory_region_init_ram(sram, NULL, "an5206.sram", 512, &error_abort); + memory_region_init_ram(sram, NULL, "an5206.sram", 512, &error_fatal); vmstate_register_ram_global(sram); memory_region_add_subregion(address_space_mem, AN5206_RAMBAR_ADDR, sram); diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 326a42d27e..c38ffb8be3 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -222,7 +222,7 @@ static void mcf5208evb_init(MachineState *machine) memory_region_add_subregion(address_space_mem, 0x40000000, ram); /* Internal SRAM. */ - memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384, &error_abort); + memory_region_init_ram(sram, NULL, "mcf5208.sram", 16384, &error_fatal); vmstate_register_ram_global(sram); memory_region_add_subregion(address_space_mem, 0x80000000, sram); diff --git a/hw/microblaze/petalogix_ml605_mmu.c b/hw/microblaze/petalogix_ml605_mmu.c index ed84a37e66..d75b053c3c 100644 --- a/hw/microblaze/petalogix_ml605_mmu.c +++ b/hw/microblaze/petalogix_ml605_mmu.c @@ -92,12 +92,12 @@ petalogix_ml605_init(MachineState *machine) /* Attach emulated BRAM through the LMB. */ memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_ml605.lmb_bram", - LMB_BRAM_SIZE, &error_abort); + LMB_BRAM_SIZE, &error_fatal); vmstate_register_ram_global(phys_lmb_bram); memory_region_add_subregion(address_space_mem, 0x00000000, phys_lmb_bram); memory_region_init_ram(phys_ram, NULL, "petalogix_ml605.ram", ram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(phys_ram); memory_region_add_subregion(address_space_mem, MEMORY_BASEADDR, phys_ram); diff --git a/hw/microblaze/petalogix_s3adsp1800_mmu.c b/hw/microblaze/petalogix_s3adsp1800_mmu.c index 0c2140c3f8..701b435368 100644 --- a/hw/microblaze/petalogix_s3adsp1800_mmu.c +++ b/hw/microblaze/petalogix_s3adsp1800_mmu.c @@ -71,12 +71,12 @@ petalogix_s3adsp1800_init(MachineState *machine) /* Attach emulated BRAM through the LMB. */ memory_region_init_ram(phys_lmb_bram, NULL, "petalogix_s3adsp1800.lmb_bram", LMB_BRAM_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(phys_lmb_bram); memory_region_add_subregion(sysmem, 0x00000000, phys_lmb_bram); memory_region_init_ram(phys_ram, NULL, "petalogix_s3adsp1800.ram", - ram_size, &error_abort); + ram_size, &error_fatal); vmstate_register_ram_global(phys_ram); memory_region_add_subregion(sysmem, ddr_base, phys_ram); diff --git a/hw/mips/cputimer.c b/hw/mips/cputimer.c index 577c9aeab8..ba9264b415 100644 --- a/hw/mips/cputimer.c +++ b/hw/mips/cputimer.c @@ -30,13 +30,21 @@ /* XXX: do not use a global */ uint32_t cpu_mips_get_random (CPUMIPSState *env) { - static uint32_t lfsr = 1; + static uint32_t seed = 1; static uint32_t prev_idx = 0; uint32_t idx; + uint32_t nb_rand_tlb = env->tlb->nb_tlb - env->CP0_Wired; + + if (nb_rand_tlb == 1) { + return env->tlb->nb_tlb - 1; + } + /* Don't return same value twice, so get another value */ do { - lfsr = (lfsr >> 1) ^ (-(lfsr & 1u) & 0xd0000001u); - idx = lfsr % (env->tlb->nb_tlb - env->CP0_Wired) + env->CP0_Wired; + /* Use a simple algorithm of Linear Congruential Generator + * from ISO/IEC 9899 standard. */ + seed = 1103515245 * seed + 12345; + idx = (seed >> 16) % nb_rand_tlb + env->CP0_Wired; } while (idx == prev_idx); prev_idx = idx; return idx; diff --git a/hw/mips/mips_fulong2e.c b/hw/mips/mips_fulong2e.c index 6d2ea30bb0..b8a11e49e9 100644 --- a/hw/mips/mips_fulong2e.c +++ b/hw/mips/mips_fulong2e.c @@ -294,7 +294,7 @@ static void mips_fulong2e_init(MachineState *machine) /* allocate RAM */ memory_region_allocate_system_memory(ram, NULL, "fulong2e.ram", ram_size); memory_region_init_ram(bios, NULL, "fulong2e.bios", bios_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(bios); memory_region_set_readonly(bios, true); diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 3906016ac4..f944c4c705 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -174,7 +174,7 @@ static void mips_jazz_init(MachineState *machine, memory_region_add_subregion(address_space, 0, ram); memory_region_init_ram(bios, NULL, "mips_jazz.bios", MAGNUM_BIOS_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(bios); memory_region_set_readonly(bios, true); memory_region_init_alias(bios2, NULL, "mips_jazz.bios", bios, @@ -241,7 +241,7 @@ static void mips_jazz_init(MachineState *machine, /* Simple ROM, so user doesn't have to provide one */ MemoryRegion *rom_mr = g_new(MemoryRegion, 1); memory_region_init_ram(rom_mr, NULL, "g364fb.rom", 0x80000, - &error_abort); + &error_fatal); vmstate_register_ram_global(rom_mr); memory_region_set_readonly(rom_mr, true); uint8_t *rom = memory_region_get_ram_ptr(rom_mr); diff --git a/hw/mips/mips_malta.c b/hw/mips/mips_malta.c index 23b6fc36a5..1004e37548 100644 --- a/hw/mips/mips_malta.c +++ b/hw/mips/mips_malta.c @@ -1120,7 +1120,7 @@ void mips_malta_init(MachineState *machine) * regions are not executable. */ memory_region_init_ram(bios_copy, NULL, "bios.1fc", BIOS_SIZE, - &error_abort); + &error_fatal); if (!rom_copy(memory_region_get_ram_ptr(bios_copy), FLASH_ADDRESS, BIOS_SIZE)) { memcpy(memory_region_get_ram_ptr(bios_copy), diff --git a/hw/mips/mips_mipssim.c b/hw/mips/mips_mipssim.c index 61f74a6315..063151ffcc 100644 --- a/hw/mips/mips_mipssim.c +++ b/hw/mips/mips_mipssim.c @@ -174,7 +174,7 @@ mips_mipssim_init(MachineState *machine) memory_region_allocate_system_memory(ram, NULL, "mips_mipssim.ram", ram_size); memory_region_init_ram(bios, NULL, "mips_mipssim.bios", BIOS_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(bios); memory_region_set_readonly(bios, true); diff --git a/hw/mips/mips_r4k.c b/hw/mips/mips_r4k.c index 86b2c0bcb7..c9612271e9 100644 --- a/hw/mips/mips_r4k.c +++ b/hw/mips/mips_r4k.c @@ -233,7 +233,7 @@ void mips_r4k_init(MachineState *machine) if ((bios_size > 0) && (bios_size <= BIOS_SIZE)) { bios = g_new(MemoryRegion, 1); memory_region_init_ram(bios, NULL, "mips_r4k.bios", BIOS_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(bios); memory_region_set_readonly(bios, true); memory_region_add_subregion(get_system_memory(), 0x1fc00000, bios); diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c index 80bcc5b4f6..5e69e11514 100644 --- a/hw/moxie/moxiesim.c +++ b/hw/moxie/moxiesim.c @@ -123,11 +123,11 @@ static void moxiesim_init(MachineState *machine) qemu_register_reset(main_cpu_reset, cpu); /* Allocate RAM. */ - memory_region_init_ram(ram, NULL, "moxiesim.ram", ram_size, &error_abort); + memory_region_init_ram(ram, NULL, "moxiesim.ram", ram_size, &error_fatal); vmstate_register_ram_global(ram); memory_region_add_subregion(address_space_mem, ram_base, ram); - memory_region_init_ram(rom, NULL, "moxie.rom", 128*0x1000, &error_abort); + memory_region_init_ram(rom, NULL, "moxie.rom", 128*0x1000, &error_fatal); vmstate_register_ram_global(rom); memory_region_add_subregion(get_system_memory(), 0x1000, rom); diff --git a/hw/net/milkymist-minimac2.c b/hw/net/milkymist-minimac2.c index 5d1cf08517..6302b8bfab 100644 --- a/hw/net/milkymist-minimac2.c +++ b/hw/net/milkymist-minimac2.c @@ -463,7 +463,7 @@ static int milkymist_minimac2_init(SysBusDevice *sbd) /* register buffers memory */ memory_region_init_ram(&s->buffers, OBJECT(dev), "milkymist-minimac2.buffers", - buffers_size, &error_abort); + buffers_size, &error_fatal); vmstate_register_ram_global(&s->buffers); s->rx0_buf = memory_region_get_ram_ptr(&s->buffers); s->rx1_buf = s->rx0_buf + MINIMAC2_BUFFER_SIZE; diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 1da0657ddf..09285bd2e6 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -114,7 +114,7 @@ static void openrisc_sim_init(MachineState *machine) } ram = g_malloc(sizeof(*ram)); - memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_abort); + memory_region_init_ram(ram, NULL, "openrisc.ram", ram_size, &error_fatal); vmstate_register_ram_global(ram); memory_region_add_subregion(get_system_memory(), 0, ram); diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 988907bfa0..da88cb3352 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -302,7 +302,7 @@ static void raven_realize(PCIDevice *d, Error **errp) d->config[0x34] = 0x00; // capabilities_pointer memory_region_init_ram(&s->bios, OBJECT(s), "bios", BIOS_SIZE, - &error_abort); + &error_fatal); memory_region_set_readonly(&s->bios, true); memory_region_add_subregion(get_system_memory(), (uint32_t)(-BIOS_SIZE), &s->bios); diff --git a/hw/pci/pci.c b/hw/pci/pci.c index ccea628209..b0bf54061f 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -2081,7 +2081,7 @@ static void pci_add_option_rom(PCIDevice *pdev, bool is_default_rom, snprintf(name, sizeof(name), "%s.rom", object_get_typename(OBJECT(pdev))); } pdev->has_rom = true; - memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_abort); + memory_region_init_ram(&pdev->rom, OBJECT(pdev), name, size, &error_fatal); vmstate_register_ram(&pdev->rom, &pdev->qdev); ptr = memory_region_get_ram_ptr(&pdev->rom); load_image(path, ptr); diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index 77d5c819ef..3c82be2e18 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -207,7 +207,7 @@ static void ppc_core99_init(MachineState *machine) /* allocate and load BIOS */ memory_region_init_ram(bios, NULL, "ppc_core99.bios", BIOS_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(bios); if (bios_name == NULL) diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 06fdbaf588..1e4b55a5cf 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -135,7 +135,7 @@ static void ppc_heathrow_init(MachineState *machine) /* allocate and load BIOS */ memory_region_init_ram(bios, NULL, "ppc_heathrow.bios", BIOS_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(bios); if (bios_name == NULL) diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index ec6c4cbaf1..53897257f0 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -215,7 +215,8 @@ static void ref405ep_init(MachineState *machine) 33333333, &pic, kernel_filename == NULL ? 0 : 1); /* allocate SRAM */ sram_size = 512 * 1024; - memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, &error_abort); + memory_region_init_ram(sram, NULL, "ef405ep.sram", sram_size, + &error_fatal); vmstate_register_ram_global(sram); memory_region_add_subregion(sysmem, 0xFFF00000, sram); /* allocate and load BIOS */ @@ -250,7 +251,7 @@ static void ref405ep_init(MachineState *machine) #endif bios = g_new(MemoryRegion, 1); memory_region_init_ram(bios, NULL, "ef405ep.bios", BIOS_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(bios); if (bios_name == NULL) @@ -579,7 +580,7 @@ static void taihu_405ep_init(MachineState *machine) bios_name = BIOS_FILENAME; bios = g_new(MemoryRegion, 1); memory_region_init_ram(bios, NULL, "taihu_405ep.bios", BIOS_SIZE, - &error_abort); + &error_fatal); vmstate_register_ram_global(bios); filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, bios_name); if (filename) { diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index c77434ae05..10f5dda1b1 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -975,7 +975,7 @@ static void ppc405_ocm_init(CPUPPCState *env) ocm = g_malloc0(sizeof(ppc405_ocm_t)); /* XXX: Size is 4096 or 0x04000000 */ memory_region_init_ram(&ocm->isarc_ram, NULL, "ppc405.ocm", 4096, - &error_abort); + &error_fatal); vmstate_register_ram_global(&ocm->isarc_ram); memory_region_init_alias(&ocm->dsarc_ram, NULL, "ppc405.dsarc", &ocm->isarc_ram, 0, 4096); diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 27a8360207..0e30c0f124 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -106,7 +106,7 @@ void s390_memory_init(ram_addr_t mem_size) MemoryRegion *ram = g_new(MemoryRegion, 1); /* allocate RAM for core */ - memory_region_init_ram(ram, NULL, "s390.ram", mem_size, &error_abort); + memory_region_init_ram(ram, NULL, "s390.ram", mem_size, &error_fatal); vmstate_register_ram_global(ram); memory_region_add_subregion(sysmem, 0, ram); diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c index fd277e1bf0..a061b49f19 100644 --- a/hw/s390x/sclp.c +++ b/hw/s390x/sclp.c @@ -231,7 +231,8 @@ static void assign_storage(SCLPDevice *sclp, SCCB *sccb) this_subregion_size = mhd->standby_subregion_size; } - memory_region_init_ram(standby_ram, NULL, id, this_subregion_size, &error_abort); + memory_region_init_ram(standby_ram, NULL, id, this_subregion_size, + &error_fatal); /* This is a hack to make memory hotunplug work again. Once we have * subdevices, we have to unparent them when unassigning memory, * instead of doing it via the ref count of the MemoryRegion. */ diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 3b0b2ecfa4..481bd927bd 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -255,7 +255,7 @@ static void r2d_init(MachineState *machine) qemu_register_reset(main_cpu_reset, reset_info); /* Allocate memory space */ - memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_abort); + memory_region_init_ram(sdram, NULL, "r2d.sdram", SDRAM_SIZE, &error_fatal); vmstate_register_ram_global(sdram); memory_region_add_subregion(address_space_mem, SDRAM_BASE, sdram); /* Register peripherals */ diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c index f93f98e568..59bcc23d22 100644 --- a/hw/sh4/shix.c +++ b/hw/sh4/shix.c @@ -59,16 +59,16 @@ static void shix_init(MachineState *machine) } /* Allocate memory space */ - memory_region_init_ram(rom, NULL, "shix.rom", 0x4000, &error_abort); + memory_region_init_ram(rom, NULL, "shix.rom", 0x4000, &error_fatal); vmstate_register_ram_global(rom); memory_region_set_readonly(rom, true); memory_region_add_subregion(sysmem, 0x00000000, rom); memory_region_init_ram(&sdram[0], NULL, "shix.sdram1", 0x01000000, - &error_abort); + &error_fatal); vmstate_register_ram_global(&sdram[0]); memory_region_add_subregion(sysmem, 0x08000000, &sdram[0]); memory_region_init_ram(&sdram[1], NULL, "shix.sdram2", 0x01000000, - &error_abort); + &error_fatal); vmstate_register_ram_global(&sdram[1]); memory_region_add_subregion(sysmem, 0x0c000000, &sdram[1]); diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 7f5dcd6d85..dd01842f70 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -156,7 +156,7 @@ static void leon3_generic_hw_init(MachineState *machine) /* Allocate BIOS */ prom_size = 8 * 1024 * 1024; /* 8Mb */ - memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_abort); + memory_region_init_ram(prom, NULL, "Leon3.bios", prom_size, &error_fatal); vmstate_register_ram_global(prom); memory_region_set_readonly(prom, true); memory_region_add_subregion(address_space_mem, 0x00000000, prom); diff --git a/hw/sparc/sun4m.c b/hw/sparc/sun4m.c index b5db8b7a00..dfb04f93e9 100644 --- a/hw/sparc/sun4m.c +++ b/hw/sparc/sun4m.c @@ -641,7 +641,7 @@ static int idreg_init1(SysBusDevice *dev) IDRegState *s = MACIO_ID_REGISTER(dev); memory_region_init_ram(&s->mem, OBJECT(s), - "sun4m.idreg", sizeof(idreg_data), &error_abort); + "sun4m.idreg", sizeof(idreg_data), &error_fatal); vmstate_register_ram_global(&s->mem); memory_region_set_readonly(&s->mem, true); sysbus_init_mmio(dev, &s->mem); @@ -688,7 +688,7 @@ static int afx_init1(SysBusDevice *dev) { AFXState *s = TCX_AFX(dev); - memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_abort); + memory_region_init_ram(&s->mem, OBJECT(s), "sun4m.afx", 4, &error_fatal); vmstate_register_ram_global(&s->mem); sysbus_init_mmio(dev, &s->mem); return 0; @@ -763,7 +763,7 @@ static int prom_init1(SysBusDevice *dev) PROMState *s = OPENPROM(dev); memory_region_init_ram(&s->prom, OBJECT(s), "sun4m.prom", PROM_SIZE_MAX, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->prom); memory_region_set_readonly(&s->prom, true); sysbus_init_mmio(dev, &s->prom); diff --git a/hw/sparc64/sun4u.c b/hw/sparc64/sun4u.c index a887a86b7d..e746f47ed4 100644 --- a/hw/sparc64/sun4u.c +++ b/hw/sparc64/sun4u.c @@ -690,7 +690,7 @@ static int prom_init1(SysBusDevice *dev) PROMState *s = OPENPROM(dev); memory_region_init_ram(&s->prom, OBJECT(s), "sun4u.prom", PROM_SIZE_MAX, - &error_abort); + &error_fatal); vmstate_register_ram_global(&s->prom); memory_region_set_readonly(&s->prom, true); sysbus_init_mmio(dev, &s->prom); @@ -734,7 +734,7 @@ static int ram_init1(SysBusDevice *dev) RamDevice *d = SUN4U_RAM(dev); memory_region_init_ram(&d->ram, OBJECT(d), "sun4u.ram", d->size, - &error_abort); + &error_fatal); vmstate_register_ram_global(&d->ram); sysbus_init_mmio(dev, &d->ram); return 0; diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c index a059a20a30..ff4d2bd083 100644 --- a/hw/tricore/tricore_testboard.c +++ b/hw/tricore/tricore_testboard.c @@ -76,17 +76,23 @@ static void tricore_testboard_init(MachineState *machine, int board_id) exit(1); } env = &cpu->env; - memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram", 2*1024*1024, &error_abort); + memory_region_init_ram(ext_cram, NULL, "powerlink_ext_c.ram", 2*1024*1024, + &error_fatal); vmstate_register_ram_global(ext_cram); - memory_region_init_ram(ext_dram, NULL, "powerlink_ext_d.ram", 4*1024*1024, &error_abort); + memory_region_init_ram(ext_dram, NULL, "powerlink_ext_d.ram", 4*1024*1024, + &error_fatal); vmstate_register_ram_global(ext_dram); - memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48*1024, &error_abort); + memory_region_init_ram(int_cram, NULL, "powerlink_int_c.ram", 48*1024, + &error_fatal); vmstate_register_ram_global(int_cram); - memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48*1024, &error_abort); + memory_region_init_ram(int_dram, NULL, "powerlink_int_d.ram", 48*1024, + &error_fatal); vmstate_register_ram_global(int_dram); - memory_region_init_ram(pcp_data, NULL, "powerlink_pcp_data.ram", 16*1024, &error_abort); + memory_region_init_ram(pcp_data, NULL, "powerlink_pcp_data.ram", 16*1024, + &error_fatal); vmstate_register_ram_global(pcp_data); - memory_region_init_ram(pcp_text, NULL, "powerlink_pcp_text.ram", 32*1024, &error_abort); + memory_region_init_ram(pcp_text, NULL, "powerlink_pcp_text.ram", 32*1024, + &error_fatal); vmstate_register_ram_global(pcp_text); memory_region_add_subregion(sysmem, 0x80000000, ext_cram); diff --git a/hw/unicore32/puv3.c b/hw/unicore32/puv3.c index 703e29d6d3..3026d94316 100644 --- a/hw/unicore32/puv3.c +++ b/hw/unicore32/puv3.c @@ -75,7 +75,7 @@ static void puv3_board_init(CPUUniCore32State *env, ram_addr_t ram_size) /* SDRAM at address zero. */ memory_region_init_ram(ram_memory, NULL, "puv3.ram", ram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(ram_memory); memory_region_add_subregion(get_system_memory(), 0, ram_memory); } diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index 328d20975d..3a8140a6b5 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -79,12 +79,12 @@ static void xtensa_sim_init(MachineState *machine) } ram = g_malloc(sizeof(*ram)); - memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size, &error_abort); + memory_region_init_ram(ram, NULL, "xtensa.sram", ram_size, &error_fatal); vmstate_register_ram_global(ram); memory_region_add_subregion(get_system_memory(), 0, ram); rom = g_malloc(sizeof(*rom)); - memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000, &error_abort); + memory_region_init_ram(rom, NULL, "xtensa.rom", 0x1000, &error_fatal); vmstate_register_ram_global(rom); memory_region_add_subregion(get_system_memory(), 0xfe000000, rom); diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index ab4d0e4127..5030ec9f87 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -143,7 +143,8 @@ static void lx60_net_init(MemoryRegion *address_space, sysbus_mmio_get_region(s, 1)); ram = g_malloc(sizeof(*ram)); - memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384, &error_abort); + memory_region_init_ram(ram, OBJECT(s), "open_eth.ram", 16384, + &error_fatal); vmstate_register_ram_global(ram); memory_region_add_subregion(address_space, buffers, ram); } @@ -223,7 +224,7 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine) ram = g_malloc(sizeof(*ram)); memory_region_init_ram(ram, NULL, "lx60.dram", machine->ram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(ram); memory_region_add_subregion(system_memory, 0, ram); @@ -275,7 +276,7 @@ static void lx_init(const LxBoardDesc *board, MachineState *machine) rom = g_malloc(sizeof(*rom)); memory_region_init_ram(rom, NULL, "lx60.sram", board->sram_size, - &error_abort); + &error_fatal); vmstate_register_ram_global(rom); memory_region_add_subregion(system_memory, 0xfe000000, rom); diff --git a/include/qapi/error.h b/include/qapi/error.h index 426d5eaceb..c69dddbbf2 100644 --- a/include/qapi/error.h +++ b/include/qapi/error.h @@ -50,6 +50,9 @@ * Call a function aborting on errors: * foo(arg, &error_abort); * + * Call a function treating errors as fatal: + * foo(arg, &error_fatal); + * * Receive an error and pass it on to the caller: * Error *err = NULL; * foo(arg, &err); @@ -100,6 +103,7 @@ ErrorClass error_get_class(const Error *err); * If @errp is NULL, the error is ignored. Don't bother creating one * then. * If @errp is &error_abort, print a suitable message and abort(). + * If @errp is &error_fatal, print a suitable message and exit(1). * If @errp is anything else, *@errp must be NULL. * The new error's class is ERROR_CLASS_GENERIC_ERROR, and its * human-readable error message is made from printf-style @fmt, ... @@ -148,6 +152,8 @@ void error_setg_win32_internal(Error **errp, * error object. * Else, if @dst_errp is &error_abort, print a suitable message and * abort(). + * Else, if @dst_errp is &error_fatal, print a suitable message and + * exit(1). * Else, if @dst_errp already contains an error, ignore this one: free * the error object. * Else, move the error object from @local_err to *@dst_errp. @@ -155,6 +161,13 @@ void error_setg_win32_internal(Error **errp, */ void error_propagate(Error **dst_errp, Error *local_err); +/** + * Append a printf-style human-readable explanation to an existing error. + * May be called multiple times, and safe if @errp is NULL. + */ +void error_append_hint(Error **errp, const char *fmt, ...) + GCC_FMT_ATTR(2, 3); + /* * Convenience function to report open() failure. */ @@ -199,4 +212,9 @@ void error_set_internal(Error **errp, */ extern Error *error_abort; +/* + * Pass to error_setg() & friends to exit(1) on error. + */ +extern Error *error_fatal; + #endif diff --git a/memory.c b/memory.c index 0d8b2d96a9..ef87363067 100644 --- a/memory.c +++ b/memory.c @@ -1251,7 +1251,7 @@ void memory_region_init_ram_ptr(MemoryRegion *mr, /* qemu_ram_alloc_from_ptr cannot fail with ptr != NULL. */ assert(ptr != NULL); - mr->ram_addr = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_abort); + mr->ram_addr = qemu_ram_alloc_from_ptr(size, ptr, mr, &error_fatal); } void memory_region_set_skip_dump(MemoryRegion *mr) diff --git a/numa.c b/numa.c index eed8f5d97b..e9b18f54be 100644 --- a/numa.c +++ b/numa.c @@ -424,14 +424,14 @@ static void allocate_system_memory_nonnuma(MemoryRegion *mr, Object *owner, */ if (err) { error_report_err(err); - memory_region_init_ram(mr, owner, name, ram_size, &error_abort); + memory_region_init_ram(mr, owner, name, ram_size, &error_fatal); } #else fprintf(stderr, "-mem-path not supported on this host\n"); exit(1); #endif } else { - memory_region_init_ram(mr, owner, name, ram_size, &error_abort); + memory_region_init_ram(mr, owner, name, ram_size, &error_fatal); } vmstate_register_ram_global(mr); } diff --git a/qdev-monitor.c b/qdev-monitor.c index f9e2d6258d..0bf7f83a1d 100644 --- a/qdev-monitor.c +++ b/qdev-monitor.c @@ -289,37 +289,35 @@ static Object *qdev_get_peripheral_anon(void) return dev; } -#if 0 /* conversion from qerror_report() to error_set() broke their use */ -static void qbus_list_bus(DeviceState *dev) +static void qbus_list_bus(DeviceState *dev, Error **errp) { BusState *child; const char *sep = " "; - error_printf("child buses at \"%s\":", - dev->id ? dev->id : object_get_typename(OBJECT(dev))); + error_append_hint(errp, "child buses at \"%s\":", + dev->id ? dev->id : object_get_typename(OBJECT(dev))); QLIST_FOREACH(child, &dev->child_bus, sibling) { - error_printf("%s\"%s\"", sep, child->name); + error_append_hint(errp, "%s\"%s\"", sep, child->name); sep = ", "; } - error_printf("\n"); } -static void qbus_list_dev(BusState *bus) +static void qbus_list_dev(BusState *bus, Error **errp) { BusChild *kid; const char *sep = " "; - error_printf("devices at \"%s\":", bus->name); + error_append_hint(errp, "devices at \"%s\":", bus->name); QTAILQ_FOREACH(kid, &bus->children, sibling) { DeviceState *dev = kid->child; - error_printf("%s\"%s\"", sep, object_get_typename(OBJECT(dev))); - if (dev->id) - error_printf("/\"%s\"", dev->id); + error_append_hint(errp, "%s\"%s\"", sep, + object_get_typename(OBJECT(dev))); + if (dev->id) { + error_append_hint(errp, "/\"%s\"", dev->id); + } sep = ", "; } - error_printf("\n"); } -#endif static BusState *qbus_find_bus(DeviceState *dev, char *elem) { @@ -461,11 +459,7 @@ static BusState *qbus_find(const char *path, Error **errp) if (!dev) { error_set(errp, ERROR_CLASS_DEVICE_NOT_FOUND, "Device '%s' not found", elem); -#if 0 /* conversion from qerror_report() to error_set() broke this: */ - if (!monitor_cur_is_qmp()) { - qbus_list_dev(bus); - } -#endif + qbus_list_dev(bus, errp); return NULL; } @@ -483,11 +477,7 @@ static BusState *qbus_find(const char *path, Error **errp) if (dev->num_child_bus) { error_setg(errp, "Device '%s' has multiple child buses", elem); -#if 0 /* conversion from qerror_report() to error_set() broke this: */ - if (!monitor_cur_is_qmp()) { - qbus_list_bus(dev); - } -#endif + qbus_list_bus(dev, errp); } else { error_setg(errp, "Device '%s' has no child bus", elem); } @@ -503,11 +493,7 @@ static BusState *qbus_find(const char *path, Error **errp) bus = qbus_find_bus(dev, elem); if (!bus) { error_setg(errp, "Bus '%s' not found", elem); -#if 0 /* conversion from qerror_report() to error_set() broke this: */ - if (!monitor_cur_is_qmp()) { - qbus_list_bus(dev); - } -#endif + qbus_list_bus(dev, errp); return NULL; } } diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 2acc4b3d0a..ed7d86d779 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -1049,4 +1049,28 @@ static inline void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) } #endif +static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, + uint32_t exception, + int error_code, + uintptr_t pc) +{ + CPUState *cs = CPU(mips_env_get_cpu(env)); + + if (exception < EXCP_SC) { + qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", + __func__, exception, error_code); + } + cs->exception_index = exception; + env->error_code = error_code; + + cpu_loop_exit_restore(cs, pc); +} + +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, + uint32_t exception, + uintptr_t pc) +{ + do_raise_exception_err(env, exception, 0, pc); +} + #endif /* !defined (__MIPS_CPU_H__) */ diff --git a/target-mips/helper.h b/target-mips/helper.h index 2b28e875cf..d8cc766bdf 100644 --- a/target-mips/helper.h +++ b/target-mips/helper.h @@ -1,5 +1,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) DEF_HELPER_2(raise_exception, noreturn, env, i32) +DEF_HELPER_1(raise_exception_debug, noreturn, env) DEF_HELPER_1(do_semihosting, void, env) diff --git a/target-mips/msa_helper.c b/target-mips/msa_helper.c index a1cb48f2a9..5dd3da67a8 100644 --- a/target-mips/msa_helper.c +++ b/target-mips/msa_helper.c @@ -1352,7 +1352,7 @@ void helper_msa_ctcmsa(CPUMIPSState *env, target_ulong elm, uint32_t cd) /* check exception */ if ((GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED) & GET_FP_CAUSE(env->active_tc.msacsr)) { - helper_raise_exception(env, EXCP_MSAFPE); + do_raise_exception(env, EXCP_MSAFPE, GETPC()); } break; } @@ -1505,14 +1505,14 @@ static inline void clear_msacsr_cause(CPUMIPSState *env) SET_FP_CAUSE(env->active_tc.msacsr, 0); } -static inline void check_msacsr_cause(CPUMIPSState *env) +static inline void check_msacsr_cause(CPUMIPSState *env, uintptr_t retaddr) { if ((GET_FP_CAUSE(env->active_tc.msacsr) & (GET_FP_ENABLE(env->active_tc.msacsr) | FP_UNIMPLEMENTED)) == 0) { UPDATE_FP_FLAGS(env->active_tc.msacsr, GET_FP_CAUSE(env->active_tc.msacsr)); } else { - helper_raise_exception(env, EXCP_MSAFPE); + do_raise_exception(env, EXCP_MSAFPE, retaddr); } } @@ -1851,7 +1851,8 @@ static inline int32 float64_to_q32(float64 a, float_status *status) } while (0) static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -1873,13 +1874,14 @@ static inline void compare_af(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -1903,13 +1905,14 @@ static inline void compare_un(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -1931,13 +1934,14 @@ static inline void compare_eq(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -1959,13 +1963,14 @@ static inline void compare_ueq(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -1987,13 +1992,14 @@ static inline void compare_lt(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -2015,13 +2021,14 @@ static inline void compare_ult(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -2043,13 +2050,14 @@ static inline void compare_le(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -2071,13 +2079,14 @@ static inline void compare_ule(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -2099,13 +2108,14 @@ static inline void compare_or(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) { wr_t wx, *pwx = &wx; uint32_t i; @@ -2127,13 +2137,15 @@ static inline void compare_une(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws, - wr_t *pwt, uint32_t df, int quiet) { + wr_t *pwt, uint32_t df, int quiet, + uintptr_t retaddr) +{ wr_t wx, *pwx = &wx; uint32_t i; @@ -2154,7 +2166,7 @@ static inline void compare_ne(CPUMIPSState *env, wr_t *pwd, wr_t *pws, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, retaddr); msa_move_v(pwd, pwx); } @@ -2165,7 +2177,7 @@ void helper_msa_fcaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_af(env, pwd, pws, pwt, df, 1); + compare_af(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2174,7 +2186,7 @@ void helper_msa_fcun_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_un(env, pwd, pws, pwt, df, 1); + compare_un(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2183,7 +2195,7 @@ void helper_msa_fceq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_eq(env, pwd, pws, pwt, df, 1); + compare_eq(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2192,7 +2204,7 @@ void helper_msa_fcueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_ueq(env, pwd, pws, pwt, df, 1); + compare_ueq(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2201,7 +2213,7 @@ void helper_msa_fclt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_lt(env, pwd, pws, pwt, df, 1); + compare_lt(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2210,7 +2222,7 @@ void helper_msa_fcult_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_ult(env, pwd, pws, pwt, df, 1); + compare_ult(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2219,7 +2231,7 @@ void helper_msa_fcle_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_le(env, pwd, pws, pwt, df, 1); + compare_le(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2228,7 +2240,7 @@ void helper_msa_fcule_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_ule(env, pwd, pws, pwt, df, 1); + compare_ule(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2237,7 +2249,7 @@ void helper_msa_fsaf_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_af(env, pwd, pws, pwt, df, 0); + compare_af(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2246,7 +2258,7 @@ void helper_msa_fsun_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_un(env, pwd, pws, pwt, df, 0); + compare_un(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2255,7 +2267,7 @@ void helper_msa_fseq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_eq(env, pwd, pws, pwt, df, 0); + compare_eq(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2264,7 +2276,7 @@ void helper_msa_fsueq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_ueq(env, pwd, pws, pwt, df, 0); + compare_ueq(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2273,7 +2285,7 @@ void helper_msa_fslt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_lt(env, pwd, pws, pwt, df, 0); + compare_lt(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2282,7 +2294,7 @@ void helper_msa_fsult_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_ult(env, pwd, pws, pwt, df, 0); + compare_ult(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2291,7 +2303,7 @@ void helper_msa_fsle_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_le(env, pwd, pws, pwt, df, 0); + compare_le(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2300,7 +2312,7 @@ void helper_msa_fsule_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_ule(env, pwd, pws, pwt, df, 0); + compare_ule(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2309,7 +2321,7 @@ void helper_msa_fcor_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_or(env, pwd, pws, pwt, df, 1); + compare_or(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2318,7 +2330,7 @@ void helper_msa_fcune_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_une(env, pwd, pws, pwt, df, 1); + compare_une(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2327,7 +2339,7 @@ void helper_msa_fcne_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_ne(env, pwd, pws, pwt, df, 1); + compare_ne(env, pwd, pws, pwt, df, 1, GETPC()); } void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2336,7 +2348,7 @@ void helper_msa_fsor_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_or(env, pwd, pws, pwt, df, 0); + compare_or(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2345,7 +2357,7 @@ void helper_msa_fsune_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_une(env, pwd, pws, pwt, df, 0); + compare_une(env, pwd, pws, pwt, df, 0, GETPC()); } void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd, @@ -2354,7 +2366,7 @@ void helper_msa_fsne_df(CPUMIPSState *env, uint32_t df, uint32_t wd, wr_t *pwd = &(env->active_fpu.fpr[wd].wr); wr_t *pws = &(env->active_fpu.fpr[ws].wr); wr_t *pwt = &(env->active_fpu.fpr[wt].wr); - compare_ne(env, pwd, pws, pwt, df, 0); + compare_ne(env, pwd, pws, pwt, df, 0, GETPC()); } #define float16_is_zero(ARG) 0 @@ -2404,7 +2416,7 @@ void helper_msa_fadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2434,7 +2446,7 @@ void helper_msa_fsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2464,7 +2476,7 @@ void helper_msa_fmul_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2495,7 +2507,7 @@ void helper_msa_fdiv_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2542,7 +2554,7 @@ void helper_msa_fmadd_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2577,7 +2589,7 @@ void helper_msa_fmsub_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2614,7 +2626,7 @@ void helper_msa_fexp2_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2666,7 +2678,7 @@ void helper_msa_fexdo_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2712,7 +2724,7 @@ void helper_msa_ftq_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2791,7 +2803,7 @@ void helper_msa_fmin_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2822,7 +2834,7 @@ void helper_msa_fmin_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2865,7 +2877,7 @@ void helper_msa_fmax_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2896,7 +2908,7 @@ void helper_msa_fmax_a_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2958,7 +2970,7 @@ void helper_msa_ftrunc_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -2988,7 +3000,7 @@ void helper_msa_ftrunc_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3018,7 +3030,7 @@ void helper_msa_fsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3067,7 +3079,7 @@ void helper_msa_frsqrt_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3097,7 +3109,7 @@ void helper_msa_frcp_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3127,7 +3139,7 @@ void helper_msa_frint_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3181,7 +3193,7 @@ void helper_msa_flog2_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3216,7 +3228,7 @@ void helper_msa_fexupl_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3250,7 +3262,7 @@ void helper_msa_fexupr_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3331,7 +3343,7 @@ void helper_msa_ftint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3361,7 +3373,7 @@ void helper_msa_ftint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3397,7 +3409,7 @@ void helper_msa_ffint_s_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } @@ -3427,7 +3439,7 @@ void helper_msa_ffint_u_df(CPUMIPSState *env, uint32_t df, uint32_t wd, assert(0); } - check_msacsr_cause(env); + check_msacsr_cause(env, GETPC()); msa_move_v(pwd, pwx); } diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c index 1aa9e3c9e4..6739fff216 100644 --- a/target-mips/op_helper.c +++ b/target-mips/op_helper.c @@ -30,42 +30,23 @@ static inline void cpu_mips_tlb_flush (CPUMIPSState *env, int flush_global); /*****************************************************************************/ /* Exceptions processing helpers */ -static inline void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) +void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code) { - CPUState *cs = CPU(mips_env_get_cpu(env)); - - if (exception < EXCP_SC) { - qemu_log_mask(CPU_LOG_INT, "%s: %d %d\n", - __func__, exception, error_code); - } - cs->exception_index = exception; - env->error_code = error_code; - - if (pc) { - /* now we have a real cpu fault */ - cpu_restore_state(cs, pc); - } - - cpu_loop_exit(cs); + do_raise_exception_err(env, exception, error_code, 0); } -static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, - uint32_t exception, - uintptr_t pc) +void helper_raise_exception(CPUMIPSState *env, uint32_t exception) { - do_raise_exception_err(env, exception, 0, pc); + do_raise_exception(env, exception, GETPC()); } -void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, - int error_code) +void helper_raise_exception_debug(CPUMIPSState *env) { - do_raise_exception_err(env, exception, error_code, 0); + do_raise_exception(env, EXCP_DEBUG, 0); } -void helper_raise_exception(CPUMIPSState *env, uint32_t exception) +static void raise_exception(CPUMIPSState *env, uint32_t exception) { do_raise_exception(env, exception, 0); } @@ -73,21 +54,21 @@ void helper_raise_exception(CPUMIPSState *env, uint32_t exception) #if defined(CONFIG_USER_ONLY) #define HELPER_LD(name, insn, type) \ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ - int mem_idx) \ + int mem_idx, uintptr_t retaddr) \ { \ - return (type) cpu_##insn##_data(env, addr); \ + return (type) cpu_##insn##_data_ra(env, addr, retaddr); \ } #else #define HELPER_LD(name, insn, type) \ static inline type do_##name(CPUMIPSState *env, target_ulong addr, \ - int mem_idx) \ + int mem_idx, uintptr_t retaddr) \ { \ switch (mem_idx) \ { \ - case 0: return (type) cpu_##insn##_kernel(env, addr); break; \ - case 1: return (type) cpu_##insn##_super(env, addr); break; \ + case 0: return (type) cpu_##insn##_kernel_ra(env, addr, retaddr); \ + case 1: return (type) cpu_##insn##_super_ra(env, addr, retaddr); \ default: \ - case 2: return (type) cpu_##insn##_user(env, addr); break; \ + case 2: return (type) cpu_##insn##_user_ra(env, addr, retaddr); \ } \ } #endif @@ -100,21 +81,21 @@ HELPER_LD(ld, ldq, int64_t) #if defined(CONFIG_USER_ONLY) #define HELPER_ST(name, insn, type) \ static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ - type val, int mem_idx) \ + type val, int mem_idx, uintptr_t retaddr) \ { \ - cpu_##insn##_data(env, addr, val); \ + cpu_##insn##_data_ra(env, addr, val, retaddr); \ } #else #define HELPER_ST(name, insn, type) \ static inline void do_##name(CPUMIPSState *env, target_ulong addr, \ - type val, int mem_idx) \ + type val, int mem_idx, uintptr_t retaddr) \ { \ switch (mem_idx) \ { \ - case 0: cpu_##insn##_kernel(env, addr, val); break; \ - case 1: cpu_##insn##_super(env, addr, val); break; \ + case 0: cpu_##insn##_kernel_ra(env, addr, val, retaddr); break; \ + case 1: cpu_##insn##_super_ra(env, addr, val, retaddr); break; \ default: \ - case 2: cpu_##insn##_user(env, addr, val); break; \ + case 2: cpu_##insn##_user_ra(env, addr, val, retaddr); break; \ } \ } #endif @@ -293,14 +274,15 @@ target_ulong helper_bitswap(target_ulong rt) static inline hwaddr do_translate_address(CPUMIPSState *env, target_ulong address, - int rw) + int rw, uintptr_t retaddr) { hwaddr lladdr; + CPUState *cs = CPU(mips_env_get_cpu(env)); lladdr = cpu_mips_translate_address(env, address, rw); if (lladdr == -1LL) { - cpu_loop_exit(CPU(mips_env_get_cpu(env))); + cpu_loop_exit_restore(cs, retaddr); } else { return lladdr; } @@ -311,10 +293,10 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ { \ if (arg & almask) { \ env->CP0_BadVAddr = arg; \ - helper_raise_exception(env, EXCP_AdEL); \ + do_raise_exception(env, EXCP_AdEL, GETPC()); \ } \ - env->lladdr = do_translate_address(env, arg, 0); \ - env->llval = do_##insn(env, arg, mem_idx); \ + env->lladdr = do_translate_address(env, arg, 0, GETPC()); \ + env->llval = do_##insn(env, arg, mem_idx, GETPC()); \ return env->llval; \ } HELPER_LD_ATOMIC(ll, lw, 0x3) @@ -331,12 +313,12 @@ target_ulong helper_##name(CPUMIPSState *env, target_ulong arg1, \ \ if (arg2 & almask) { \ env->CP0_BadVAddr = arg2; \ - helper_raise_exception(env, EXCP_AdES); \ + do_raise_exception(env, EXCP_AdES, GETPC()); \ } \ - if (do_translate_address(env, arg2, 1) == env->lladdr) { \ - tmp = do_##ld_insn(env, arg2, mem_idx); \ + if (do_translate_address(env, arg2, 1, GETPC()) == env->lladdr) { \ + tmp = do_##ld_insn(env, arg2, mem_idx, GETPC()); \ if (tmp == env->llval) { \ - do_##st_insn(env, arg2, arg1, mem_idx); \ + do_##st_insn(env, arg2, arg1, mem_idx, GETPC()); \ return 1; \ } \ } \ @@ -360,31 +342,43 @@ HELPER_ST_ATOMIC(scd, ld, sd, 0x7) void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { - do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx); + do_sb(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); - if (GET_LMASK(arg2) <= 2) - do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx); + if (GET_LMASK(arg2) <= 2) { + do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), mem_idx, + GETPC()); + } - if (GET_LMASK(arg2) <= 1) - do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx); + if (GET_LMASK(arg2) <= 1) { + do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), mem_idx, + GETPC()); + } - if (GET_LMASK(arg2) == 0) - do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx); + if (GET_LMASK(arg2) == 0) { + do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, mem_idx, + GETPC()); + } } void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { - do_sb(env, arg2, (uint8_t)arg1, mem_idx); + do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - if (GET_LMASK(arg2) >= 1) - do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + if (GET_LMASK(arg2) >= 1) { + do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx, + GETPC()); + } - if (GET_LMASK(arg2) >= 2) - do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + if (GET_LMASK(arg2) >= 2) { + do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx, + GETPC()); + } - if (GET_LMASK(arg2) == 3) - do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); + if (GET_LMASK(arg2) == 3) { + do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx, + GETPC()); + } } #if defined(TARGET_MIPS64) @@ -400,55 +394,83 @@ void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { - do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx); + do_sb(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); - if (GET_LMASK64(arg2) <= 6) - do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx); + if (GET_LMASK64(arg2) <= 6) { + do_sb(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) <= 5) - do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx); + if (GET_LMASK64(arg2) <= 5) { + do_sb(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) <= 4) - do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx); + if (GET_LMASK64(arg2) <= 4) { + do_sb(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) <= 3) - do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx); + if (GET_LMASK64(arg2) <= 3) { + do_sb(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) <= 2) - do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx); + if (GET_LMASK64(arg2) <= 2) { + do_sb(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) <= 1) - do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx); + if (GET_LMASK64(arg2) <= 1) { + do_sb(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) <= 0) - do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx); + if (GET_LMASK64(arg2) <= 0) { + do_sb(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, mem_idx, + GETPC()); + } } void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, int mem_idx) { - do_sb(env, arg2, (uint8_t)arg1, mem_idx); + do_sb(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - if (GET_LMASK64(arg2) >= 1) - do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx); + if (GET_LMASK64(arg2) >= 1) { + do_sb(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) >= 2) - do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx); + if (GET_LMASK64(arg2) >= 2) { + do_sb(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) >= 3) - do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx); + if (GET_LMASK64(arg2) >= 3) { + do_sb(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) >= 4) - do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx); + if (GET_LMASK64(arg2) >= 4) { + do_sb(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) >= 5) - do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx); + if (GET_LMASK64(arg2) >= 5) { + do_sb(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) >= 6) - do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx); + if (GET_LMASK64(arg2) >= 6) { + do_sb(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), mem_idx, + GETPC()); + } - if (GET_LMASK64(arg2) == 7) - do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx); + if (GET_LMASK64(arg2) == 7) { + do_sb(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), mem_idx, + GETPC()); + } } #endif /* TARGET_MIPS64 */ @@ -465,13 +487,14 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, for (i = 0; i < base_reglist; i++) { env->active_tc.gpr[multiple_regs[i]] = - (target_long)do_lw(env, addr, mem_idx); + (target_long)do_lw(env, addr, mem_idx, GETPC()); addr += 4; } } if (do_r31) { - env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx); + env->active_tc.gpr[31] = (target_long)do_lw(env, addr, mem_idx, + GETPC()); } } @@ -485,13 +508,14 @@ void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, target_ulong i; for (i = 0; i < base_reglist; i++) { - do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); + do_sw(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx, + GETPC()); addr += 4; } } if (do_r31) { - do_sw(env, addr, env->active_tc.gpr[31], mem_idx); + do_sw(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); } } @@ -506,13 +530,14 @@ void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, target_ulong i; for (i = 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx); + env->active_tc.gpr[multiple_regs[i]] = do_ld(env, addr, mem_idx, + GETPC()); addr += 8; } } if (do_r31) { - env->active_tc.gpr[31] = do_ld(env, addr, mem_idx); + env->active_tc.gpr[31] = do_ld(env, addr, mem_idx, GETPC()); } } @@ -526,13 +551,14 @@ void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, target_ulong i; for (i = 0; i < base_reglist; i++) { - do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx); + do_sd(env, addr, env->active_tc.gpr[multiple_regs[i]], mem_idx, + GETPC()); addr += 8; } } if (do_r31) { - do_sd(env, addr, env->active_tc.gpr[31], mem_idx); + do_sd(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); } } #endif @@ -1792,13 +1818,13 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; - helper_raise_exception(env, EXCP_THREAD); + do_raise_exception(env, EXCP_THREAD, GETPC()); } } } else if (arg1 == 0) { if (0 /* TODO: TC underflow */) { env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); - helper_raise_exception(env, EXCP_THREAD); + do_raise_exception(env, EXCP_THREAD, GETPC()); } else { // TODO: Deallocate TC } @@ -1806,7 +1832,7 @@ target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) /* Yield qualifier inputs not implemented. */ env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; - helper_raise_exception(env, EXCP_THREAD); + do_raise_exception(env, EXCP_THREAD, GETPC()); } return env->CP0_YQMask; } @@ -2165,7 +2191,7 @@ target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) (env->CP0_HWREna & (1 << 0))) return env->CP0_EBase & 0x3ff; else - helper_raise_exception(env, EXCP_RI); + do_raise_exception(env, EXCP_RI, GETPC()); return 0; } @@ -2176,7 +2202,7 @@ target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) (env->CP0_HWREna & (1 << 1))) return env->SYNCI_Step; else - helper_raise_exception(env, EXCP_RI); + do_raise_exception(env, EXCP_RI, GETPC()); return 0; } @@ -2184,10 +2210,15 @@ target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) target_ulong helper_rdhwr_cc(CPUMIPSState *env) { if ((env->hflags & MIPS_HFLAG_CP0) || - (env->CP0_HWREna & (1 << 2))) + (env->CP0_HWREna & (1 << 2))) { +#ifdef CONFIG_USER_ONLY return env->CP0_Count; - else - helper_raise_exception(env, EXCP_RI); +#else + return (int32_t)cpu_mips_get_count(env); +#endif + } else { + do_raise_exception(env, EXCP_RI, GETPC()); + } return 0; } @@ -2198,7 +2229,7 @@ target_ulong helper_rdhwr_ccres(CPUMIPSState *env) (env->CP0_HWREna & (1 << 3))) return env->CCRes; else - helper_raise_exception(env, EXCP_RI); + do_raise_exception(env, EXCP_RI, GETPC()); return 0; } @@ -2235,7 +2266,9 @@ void helper_wait(CPUMIPSState *env) cs->halted = 1; cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); - helper_raise_exception(env, EXCP_HLT); + /* Last instruction in the block, PC was updated before + - no need to recover PC and icount */ + raise_exception(env, EXCP_HLT); } #if !defined(CONFIG_USER_ONLY) @@ -2296,9 +2329,9 @@ void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, } if (is_exec) { - helper_raise_exception(env, EXCP_IBE); + raise_exception(env, EXCP_IBE); } else { - helper_raise_exception(env, EXCP_DBE); + raise_exception(env, EXCP_DBE); } } #endif /* !CONFIG_USER_ONLY */ @@ -2333,7 +2366,7 @@ target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) arg1 = (int32_t) ((env->CP0_Status & (1 << CP0St_FR)) >> CP0St_FR); } else { - helper_raise_exception(env, EXCP_RI); + do_raise_exception(env, EXCP_RI, GETPC()); } } break; @@ -2376,7 +2409,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) env->CP0_Status &= ~(1 << CP0St_FR); compute_hflags(env); } else { - helper_raise_exception(env, EXCP_RI); + do_raise_exception(env, EXCP_RI, GETPC()); } break; case 4: @@ -2388,7 +2421,7 @@ void helper_ctc1(CPUMIPSState *env, target_ulong arg1, uint32_t fs, uint32_t rt) env->CP0_Status |= (1 << CP0St_FR); compute_hflags(env); } else { - helper_raise_exception(env, EXCP_RI); + do_raise_exception(env, EXCP_RI, GETPC()); } break; case 5: diff --git a/target-mips/translate.c b/target-mips/translate.c index 93cb4f2731..87d495975a 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -33,9 +33,7 @@ #include "trace-tcg.h" - #define MIPS_DEBUG_DISAS 0 -//#define MIPS_DEBUG_SIGN_EXTENSIONS /* MIPS major opcodes */ #define MASK_OP_MAJOR(op) (op & (0x3F << 26)) @@ -1482,26 +1480,23 @@ static const char * const msaregnames[] = { "w30.d0", "w30.d1", "w31.d0", "w31.d1", }; -#define MIPS_DEBUG(fmt, ...) \ +#define LOG_DISAS(...) \ do { \ if (MIPS_DEBUG_DISAS) { \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, \ - TARGET_FMT_lx ": %08x " fmt "\n", \ - ctx->pc, ctx->opcode , ## __VA_ARGS__); \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \ } \ } while (0) -#define LOG_DISAS(...) \ +#define MIPS_INVAL(op) \ do { \ if (MIPS_DEBUG_DISAS) { \ - qemu_log_mask(CPU_LOG_TB_IN_ASM, ## __VA_ARGS__); \ + qemu_log_mask(CPU_LOG_TB_IN_ASM, \ + TARGET_FMT_lx ": %08x Invalid %s %03x %03x %03x\n", \ + ctx->pc, ctx->opcode, op, ctx->opcode >> 26, \ + ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)); \ } \ } while (0) -#define MIPS_INVAL(op) \ - MIPS_DEBUG("Invalid %s %03x %03x %03x", op, ctx->opcode >> 26, \ - ctx->opcode & 0x3F, ((ctx->opcode >> 16) & 0x1F)) - /* General purpose registers moves. */ static inline void gen_load_gpr (TCGv t, int reg) { @@ -1615,14 +1610,19 @@ static inline void generate_exception_err(DisasContext *ctx, int excp, int err) gen_helper_raise_exception_err(cpu_env, texcp, terr); tcg_temp_free_i32(terr); tcg_temp_free_i32(texcp); + ctx->bstate = BS_EXCP; } static inline void generate_exception(DisasContext *ctx, int excp) { - save_cpu_state(ctx, 1); gen_helper_0e0i(raise_exception, excp); } +static inline void generate_exception_end(DisasContext *ctx, int excp) +{ + generate_exception_err(ctx, excp, 0); +} + /* Floating point register moves. */ static void gen_load_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) { @@ -1647,10 +1647,7 @@ static void gen_store_fpr32(DisasContext *ctx, TCGv_i32 t, int reg) static void gen_load_fpr32h(DisasContext *ctx, TCGv_i32 t, int reg) { if (ctx->hflags & MIPS_HFLAG_F64) { - TCGv_i64 t64 = tcg_temp_new_i64(); - tcg_gen_shri_i64(t64, fpu_f64[reg], 32); - tcg_gen_extrl_i64_i32(t, t64); - tcg_temp_free_i64(t64); + tcg_gen_extrh_i64_i32(t, fpu_f64[reg]); } else { gen_load_fpr32(ctx, t, reg | 1); } @@ -1725,12 +1722,23 @@ static target_long addr_add(DisasContext *ctx, target_long base, return sum; } +/* Sign-extract the low 32-bits to a target_long. */ static inline void gen_move_low32(TCGv ret, TCGv_i64 arg) { #if defined(TARGET_MIPS64) - tcg_gen_ext32s_tl(ret, arg); + tcg_gen_ext32s_i64(ret, arg); #else - tcg_gen_trunc_i64_tl(ret, arg); + tcg_gen_extrl_i64_i32(ret, arg); +#endif +} + +/* Sign-extract the high 32-bits to a target_long. */ +static inline void gen_move_high32(TCGv ret, TCGv_i64 arg) +{ +#if defined(TARGET_MIPS64) + tcg_gen_sari_i64(ret, arg, 32); +#else + tcg_gen_extrh_i64_i32(ret, arg); #endif } @@ -1753,7 +1761,7 @@ static inline void check_cp1_enabled(DisasContext *ctx) static inline void check_cop1x(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_COP1X))) - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } /* Verify that the processor is running with 64-bit floating-point @@ -1762,7 +1770,7 @@ static inline void check_cop1x(DisasContext *ctx) static inline void check_cp1_64bitmode(DisasContext *ctx) { if (unlikely(~ctx->hflags & (MIPS_HFLAG_F64 | MIPS_HFLAG_COP1X))) - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } /* @@ -1779,7 +1787,7 @@ static inline void check_cp1_64bitmode(DisasContext *ctx) static inline void check_cp1_registers(DisasContext *ctx, int regs) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_F64) && (regs & 1))) - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } /* Verify that the processor is running with DSP instructions enabled. @@ -1790,9 +1798,9 @@ static inline void check_dsp(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSP))) { if (ctx->insn_flags & ASE_DSP) { - generate_exception(ctx, EXCP_DSPDIS); + generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } } } @@ -1801,9 +1809,9 @@ static inline void check_dspr2(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_DSPR2))) { if (ctx->insn_flags & ASE_DSP) { - generate_exception(ctx, EXCP_DSPDIS); + generate_exception_end(ctx, EXCP_DSPDIS); } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } } } @@ -1813,7 +1821,7 @@ static inline void check_dspr2(DisasContext *ctx) static inline void check_insn(DisasContext *ctx, int flags) { if (unlikely(!(ctx->insn_flags & flags))) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } } @@ -1823,7 +1831,7 @@ static inline void check_insn(DisasContext *ctx, int flags) static inline void check_insn_opc_removed(DisasContext *ctx, int flags) { if (unlikely(ctx->insn_flags & flags)) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } } @@ -1843,7 +1851,7 @@ static inline void check_ps(DisasContext *ctx) static inline void check_mips_64(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_64))) - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } #endif @@ -2052,7 +2060,7 @@ static inline void op_st_##insn(TCGv arg1, TCGv arg2, int rt, DisasContext *ctx) tcg_gen_movi_tl(t0, rt | ((almask << 3) & 0x20)); \ tcg_gen_st_tl(t0, cpu_env, offsetof(CPUMIPSState, llreg)); \ tcg_gen_st_tl(arg1, cpu_env, offsetof(CPUMIPSState, llnewval)); \ - gen_helper_0e0i(raise_exception, EXCP_SC); \ + generate_exception_end(ctx, EXCP_SC); \ gen_set_label(l2); \ tcg_gen_movi_tl(t0, 0); \ gen_store_gpr(t0, rt); \ @@ -2105,14 +2113,12 @@ static target_ulong pc_relative_pc (DisasContext *ctx) static void gen_ld(DisasContext *ctx, uint32_t opc, int rt, int base, int16_t offset) { - const char *opn = "ld"; TCGv t0, t1, t2; if (rt == 0 && ctx->insn_flags & (INSN_LOONGSON2E | INSN_LOONGSON2F)) { /* Loongson CPU uses a load to zero register for prefetch. We emulate it as a NOP. On other CPU we must perform the actual memory access. */ - MIPS_DEBUG("NOP"); return; } @@ -2125,20 +2131,16 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); - opn = "lwu"; break; case OPC_LD: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); - opn = "ld"; break; case OPC_LLD: case R6_OPC_LLD: - save_cpu_state(ctx, 1); op_ld_lld(t0, t0, ctx); gen_store_gpr(t0, rt); - opn = "lld"; break; case OPC_LDL: t1 = tcg_temp_new(); @@ -2161,7 +2163,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); gen_store_gpr(t0, rt); - opn = "ldl"; break; case OPC_LDR: t1 = tcg_temp_new(); @@ -2185,7 +2186,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_gen_or_tl(t0, t0, t1); tcg_temp_free(t1); gen_store_gpr(t0, rt); - opn = "ldr"; break; case OPC_LDPC: t1 = tcg_const_tl(pc_relative_pc(ctx)); @@ -2193,7 +2193,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); gen_store_gpr(t0, rt); - opn = "ldpc"; break; #endif case OPC_LWPC: @@ -2202,35 +2201,29 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); gen_store_gpr(t0, rt); - opn = "lwpc"; break; case OPC_LW: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); - opn = "lw"; break; case OPC_LH: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); - opn = "lh"; break; case OPC_LHU: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEUW | ctx->default_tcg_memop_mask); gen_store_gpr(t0, rt); - opn = "lhu"; break; case OPC_LB: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_SB); gen_store_gpr(t0, rt); - opn = "lb"; break; case OPC_LBU: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB); gen_store_gpr(t0, rt); - opn = "lbu"; break; case OPC_LWL: t1 = tcg_temp_new(); @@ -2254,7 +2247,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); - opn = "lwl"; break; case OPC_LWR: t1 = tcg_temp_new(); @@ -2279,18 +2271,13 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, tcg_temp_free(t1); tcg_gen_ext32s_tl(t0, t0); gen_store_gpr(t0, rt); - opn = "lwr"; break; case OPC_LL: case R6_OPC_LL: - save_cpu_state(ctx, 1); op_ld_ll(t0, t0, ctx); gen_store_gpr(t0, rt); - opn = "ll"; break; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); tcg_temp_free(t0); } @@ -2298,7 +2285,6 @@ static void gen_ld(DisasContext *ctx, uint32_t opc, static void gen_st (DisasContext *ctx, uint32_t opc, int rt, int base, int16_t offset) { - const char *opn = "st"; TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -2309,46 +2295,32 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, case OPC_SD: tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ | ctx->default_tcg_memop_mask); - opn = "sd"; break; case OPC_SDL: - save_cpu_state(ctx, 1); gen_helper_0e2i(sdl, t1, t0, ctx->mem_idx); - opn = "sdl"; break; case OPC_SDR: - save_cpu_state(ctx, 1); gen_helper_0e2i(sdr, t1, t0, ctx->mem_idx); - opn = "sdr"; break; #endif case OPC_SW: tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL | ctx->default_tcg_memop_mask); - opn = "sw"; break; case OPC_SH: tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUW | ctx->default_tcg_memop_mask); - opn = "sh"; break; case OPC_SB: tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_8); - opn = "sb"; break; case OPC_SWL: - save_cpu_state(ctx, 1); gen_helper_0e2i(swl, t1, t0, ctx->mem_idx); - opn = "swl"; break; case OPC_SWR: - save_cpu_state(ctx, 1); gen_helper_0e2i(swr, t1, t0, ctx->mem_idx); - opn = "swr"; break; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); tcg_temp_free(t0); tcg_temp_free(t1); } @@ -2358,7 +2330,6 @@ static void gen_st (DisasContext *ctx, uint32_t opc, int rt, static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, int base, int16_t offset) { - const char *opn = "st_cond"; TCGv t0, t1; #ifdef CONFIG_USER_ONLY @@ -2374,20 +2345,14 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, #if defined(TARGET_MIPS64) case OPC_SCD: case R6_OPC_SCD: - save_cpu_state(ctx, 1); op_st_scd(t1, t0, rt, ctx); - opn = "scd"; break; #endif case OPC_SC: case R6_OPC_SC: - save_cpu_state(ctx, 1); op_st_sc(t1, t0, rt, ctx); - opn = "sc"; break; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %d(%s)", opn, regnames[rt], offset, regnames[base]); tcg_temp_free(t1); tcg_temp_free(t0); } @@ -2396,7 +2361,6 @@ static void gen_st_cond (DisasContext *ctx, uint32_t opc, int rt, static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, int base, int16_t offset) { - const char *opn = "flt_ldst"; TCGv t0 = tcg_temp_new(); gen_base_offset_addr(ctx, t0, base, offset); @@ -2411,7 +2375,6 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, gen_store_fpr32(ctx, fp0, ft); tcg_temp_free_i32(fp0); } - opn = "lwc1"; break; case OPC_SWC1: { @@ -2421,7 +2384,6 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, ctx->default_tcg_memop_mask); tcg_temp_free_i32(fp0); } - opn = "swc1"; break; case OPC_LDC1: { @@ -2431,7 +2393,6 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, gen_store_fpr64(ctx, fp0, ft); tcg_temp_free_i64(fp0); } - opn = "ldc1"; break; case OPC_SDC1: { @@ -2441,15 +2402,12 @@ static void gen_flt_ldst (DisasContext *ctx, uint32_t opc, int ft, ctx->default_tcg_memop_mask); tcg_temp_free_i64(fp0); } - opn = "sdc1"; break; default: - MIPS_INVAL(opn); - generate_exception(ctx, EXCP_RI); + MIPS_INVAL("flt_ldst"); + generate_exception_end(ctx, EXCP_RI); goto out; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %d(%s)", opn, fregnames[ft], offset, regnames[base]); out: tcg_temp_free(t0); } @@ -2477,12 +2435,10 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, int rt, int rs, int16_t imm) { target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ - const char *opn = "imm arith"; if (rt == 0 && opc != OPC_ADDI && opc != OPC_DADDI) { /* If no destination, treat it as a NOP. For addi, we must generate the overflow exception when needed. */ - MIPS_DEBUG("NOP"); return; } switch (opc) { @@ -2510,7 +2466,6 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rt); tcg_temp_free(t0); } - opn = "addi"; break; case OPC_ADDIU: if (rs != 0) { @@ -2519,7 +2474,6 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rt], uimm); } - opn = "addiu"; break; #if defined(TARGET_MIPS64) case OPC_DADDI: @@ -2544,7 +2498,6 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rt); tcg_temp_free(t0); } - opn = "daddi"; break; case OPC_DADDIU: if (rs != 0) { @@ -2552,12 +2505,9 @@ static void gen_arith_imm(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rt], uimm); } - opn = "daddiu"; break; #endif } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); } /* Logic with immediate operand */ @@ -2568,7 +2518,6 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc, if (rt == 0) { /* If no destination, treat it as a NOP. */ - MIPS_DEBUG("NOP"); return; } uimm = (uint16_t)imm; @@ -2578,39 +2527,30 @@ static void gen_logic_imm(DisasContext *ctx, uint32_t opc, tcg_gen_andi_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); else tcg_gen_movi_tl(cpu_gpr[rt], 0); - MIPS_DEBUG("andi %s, %s, " TARGET_FMT_lx, regnames[rt], - regnames[rs], uimm); break; case OPC_ORI: if (rs != 0) tcg_gen_ori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); else tcg_gen_movi_tl(cpu_gpr[rt], uimm); - MIPS_DEBUG("ori %s, %s, " TARGET_FMT_lx, regnames[rt], - regnames[rs], uimm); break; case OPC_XORI: if (likely(rs != 0)) tcg_gen_xori_tl(cpu_gpr[rt], cpu_gpr[rs], uimm); else tcg_gen_movi_tl(cpu_gpr[rt], uimm); - MIPS_DEBUG("xori %s, %s, " TARGET_FMT_lx, regnames[rt], - regnames[rs], uimm); break; case OPC_LUI: if (rs != 0 && (ctx->insn_flags & ISA_MIPS32R6)) { /* OPC_AUI */ tcg_gen_addi_tl(cpu_gpr[rt], cpu_gpr[rs], imm << 16); tcg_gen_ext32s_tl(cpu_gpr[rt], cpu_gpr[rt]); - MIPS_DEBUG("aui %s, %s, %04x", regnames[rt], regnames[rs], imm); } else { tcg_gen_movi_tl(cpu_gpr[rt], imm << 16); - MIPS_DEBUG("lui %s, " TARGET_FMT_lx, regnames[rt], uimm); } break; default: - MIPS_DEBUG("Unknown logical immediate opcode %08x", opc); break; } } @@ -2620,12 +2560,10 @@ static void gen_slt_imm(DisasContext *ctx, uint32_t opc, int rt, int rs, int16_t imm) { target_ulong uimm = (target_long)imm; /* Sign extend to 32/64 bits */ - const char *opn = "imm arith"; TCGv t0; if (rt == 0) { /* If no destination, treat it as a NOP. */ - MIPS_DEBUG("NOP"); return; } t0 = tcg_temp_new(); @@ -2633,15 +2571,11 @@ static void gen_slt_imm(DisasContext *ctx, uint32_t opc, switch (opc) { case OPC_SLTI: tcg_gen_setcondi_tl(TCG_COND_LT, cpu_gpr[rt], t0, uimm); - opn = "slti"; break; case OPC_SLTIU: tcg_gen_setcondi_tl(TCG_COND_LTU, cpu_gpr[rt], t0, uimm); - opn = "sltiu"; break; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); tcg_temp_free(t0); } @@ -2650,12 +2584,10 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc, int rt, int rs, int16_t imm) { target_ulong uimm = ((uint16_t)imm) & 0x1f; - const char *opn = "imm shift"; TCGv t0; if (rt == 0) { /* If no destination, treat it as a NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -2665,11 +2597,9 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc, case OPC_SLL: tcg_gen_shli_tl(t0, t0, uimm); tcg_gen_ext32s_tl(cpu_gpr[rt], t0); - opn = "sll"; break; case OPC_SRA: tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); - opn = "sra"; break; case OPC_SRL: if (uimm != 0) { @@ -2678,7 +2608,6 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc, } else { tcg_gen_ext32s_tl(cpu_gpr[rt], t0); } - opn = "srl"; break; case OPC_ROTR: if (uimm != 0) { @@ -2691,20 +2620,16 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc, } else { tcg_gen_ext32s_tl(cpu_gpr[rt], t0); } - opn = "rotr"; break; #if defined(TARGET_MIPS64) case OPC_DSLL: tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm); - opn = "dsll"; break; case OPC_DSRA: tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm); - opn = "dsra"; break; case OPC_DSRL: tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm); - opn = "dsrl"; break; case OPC_DROTR: if (uimm != 0) { @@ -2712,28 +2637,21 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc, } else { tcg_gen_mov_tl(cpu_gpr[rt], t0); } - opn = "drotr"; break; case OPC_DSLL32: tcg_gen_shli_tl(cpu_gpr[rt], t0, uimm + 32); - opn = "dsll32"; break; case OPC_DSRA32: tcg_gen_sari_tl(cpu_gpr[rt], t0, uimm + 32); - opn = "dsra32"; break; case OPC_DSRL32: tcg_gen_shri_tl(cpu_gpr[rt], t0, uimm + 32); - opn = "dsrl32"; break; case OPC_DROTR32: tcg_gen_rotri_tl(cpu_gpr[rt], t0, uimm + 32); - opn = "drotr32"; break; #endif } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, " TARGET_FMT_lx, opn, regnames[rt], regnames[rs], uimm); tcg_temp_free(t0); } @@ -2741,13 +2659,10 @@ static void gen_shift_imm(DisasContext *ctx, uint32_t opc, static void gen_arith(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { - const char *opn = "arith"; - if (rd == 0 && opc != OPC_ADD && opc != OPC_SUB && opc != OPC_DADD && opc != OPC_DSUB) { /* If no destination, treat it as a NOP. For add & sub, we must generate the overflow exception when needed. */ - MIPS_DEBUG("NOP"); return; } @@ -2775,7 +2690,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rd); tcg_temp_free(t0); } - opn = "add"; break; case OPC_ADDU: if (rs != 0 && rt != 0) { @@ -2788,7 +2702,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rd], 0); } - opn = "addu"; break; case OPC_SUB: { @@ -2813,7 +2726,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rd); tcg_temp_free(t0); } - opn = "sub"; break; case OPC_SUBU: if (rs != 0 && rt != 0) { @@ -2827,7 +2739,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rd], 0); } - opn = "subu"; break; #if defined(TARGET_MIPS64) case OPC_DADD: @@ -2852,7 +2763,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rd); tcg_temp_free(t0); } - opn = "dadd"; break; case OPC_DADDU: if (rs != 0 && rt != 0) { @@ -2864,7 +2774,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rd], 0); } - opn = "daddu"; break; case OPC_DSUB: { @@ -2888,7 +2797,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, gen_store_gpr(t0, rd); tcg_temp_free(t0); } - opn = "dsub"; break; case OPC_DSUBU: if (rs != 0 && rt != 0) { @@ -2900,7 +2808,6 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rd], 0); } - opn = "dsubu"; break; #endif case OPC_MUL: @@ -2910,23 +2817,18 @@ static void gen_arith(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rd], 0); } - opn = "mul"; break; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); } /* Conditional move */ static void gen_cond_move(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { - const char *opn = "cond move"; TCGv t0, t1, t2; if (rd == 0) { /* If no destination, treat it as a NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -2938,38 +2840,28 @@ static void gen_cond_move(DisasContext *ctx, uint32_t opc, switch (opc) { case OPC_MOVN: tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); - opn = "movn"; break; case OPC_MOVZ: tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, cpu_gpr[rd]); - opn = "movz"; break; case OPC_SELNEZ: tcg_gen_movcond_tl(TCG_COND_NE, cpu_gpr[rd], t0, t1, t2, t1); - opn = "selnez"; break; case OPC_SELEQZ: tcg_gen_movcond_tl(TCG_COND_EQ, cpu_gpr[rd], t0, t1, t2, t1); - opn = "seleqz"; break; } tcg_temp_free(t2); tcg_temp_free(t1); tcg_temp_free(t0); - - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); } /* Logic */ static void gen_logic(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { - const char *opn = "logic"; - if (rd == 0) { /* If no destination, treat it as a NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -2980,7 +2872,6 @@ static void gen_logic(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rd], 0); } - opn = "and"; break; case OPC_NOR: if (rs != 0 && rt != 0) { @@ -2992,7 +2883,6 @@ static void gen_logic(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rd], ~((target_ulong)0)); } - opn = "nor"; break; case OPC_OR: if (likely(rs != 0 && rt != 0)) { @@ -3004,7 +2894,6 @@ static void gen_logic(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rd], 0); } - opn = "or"; break; case OPC_XOR: if (likely(rs != 0 && rt != 0)) { @@ -3016,23 +2905,18 @@ static void gen_logic(DisasContext *ctx, uint32_t opc, } else { tcg_gen_movi_tl(cpu_gpr[rd], 0); } - opn = "xor"; break; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); } /* Set on lower than */ static void gen_slt(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { - const char *opn = "slt"; TCGv t0, t1; if (rd == 0) { /* If no destination, treat it as a NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -3043,15 +2927,11 @@ static void gen_slt(DisasContext *ctx, uint32_t opc, switch (opc) { case OPC_SLT: tcg_gen_setcond_tl(TCG_COND_LT, cpu_gpr[rd], t0, t1); - opn = "slt"; break; case OPC_SLTU: tcg_gen_setcond_tl(TCG_COND_LTU, cpu_gpr[rd], t0, t1); - opn = "sltu"; break; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); tcg_temp_free(t0); tcg_temp_free(t1); } @@ -3060,13 +2940,11 @@ static void gen_slt(DisasContext *ctx, uint32_t opc, static void gen_shift(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { - const char *opn = "shifts"; TCGv t0, t1; if (rd == 0) { /* If no destination, treat it as a NOP. For add & sub, we must generate the overflow exception when needed. */ - MIPS_DEBUG("NOP"); return; } @@ -3079,19 +2957,16 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, tcg_gen_andi_tl(t0, t0, 0x1f); tcg_gen_shl_tl(t0, t1, t0); tcg_gen_ext32s_tl(cpu_gpr[rd], t0); - opn = "sllv"; break; case OPC_SRAV: tcg_gen_andi_tl(t0, t0, 0x1f); tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); - opn = "srav"; break; case OPC_SRLV: tcg_gen_ext32u_tl(t1, t1); tcg_gen_andi_tl(t0, t0, 0x1f); tcg_gen_shr_tl(t0, t1, t0); tcg_gen_ext32s_tl(cpu_gpr[rd], t0); - opn = "srlv"; break; case OPC_ROTRV: { @@ -3105,34 +2980,27 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, tcg_gen_ext_i32_tl(cpu_gpr[rd], t2); tcg_temp_free_i32(t2); tcg_temp_free_i32(t3); - opn = "rotrv"; } break; #if defined(TARGET_MIPS64) case OPC_DSLLV: tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_shl_tl(cpu_gpr[rd], t1, t0); - opn = "dsllv"; break; case OPC_DSRAV: tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_sar_tl(cpu_gpr[rd], t1, t0); - opn = "dsrav"; break; case OPC_DSRLV: tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_shr_tl(cpu_gpr[rd], t1, t0); - opn = "dsrlv"; break; case OPC_DROTRV: tcg_gen_andi_tl(t0, t0, 0x3f); tcg_gen_rotr_tl(cpu_gpr[rd], t1, t0); - opn = "drotrv"; break; #endif } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); tcg_temp_free(t0); tcg_temp_free(t1); } @@ -3140,11 +3008,8 @@ static void gen_shift(DisasContext *ctx, uint32_t opc, /* Arithmetic on HI/LO registers */ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { - const char *opn = "hilo"; - if (reg == 0 && (opc == OPC_MFHI || opc == OPC_MFLO)) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -3162,7 +3027,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { tcg_gen_mov_tl(cpu_gpr[reg], cpu_HI[acc]); } - opn = "mfhi"; break; case OPC_MFLO: #if defined(TARGET_MIPS64) @@ -3173,7 +3037,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) { tcg_gen_mov_tl(cpu_gpr[reg], cpu_LO[acc]); } - opn = "mflo"; break; case OPC_MTHI: if (reg != 0) { @@ -3188,7 +3051,6 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) } else { tcg_gen_movi_tl(cpu_HI[acc], 0); } - opn = "mthi"; break; case OPC_MTLO: if (reg != 0) { @@ -3203,11 +3065,8 @@ static void gen_HILO(DisasContext *ctx, uint32_t opc, int acc, int reg) } else { tcg_gen_movi_tl(cpu_LO[acc], 0); } - opn = "mtlo"; break; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s", opn, regnames[reg]); } static inline void gen_r6_ld(target_long addr, int reg, int memidx, @@ -3275,7 +3134,7 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, #endif default: MIPS_INVAL("OPC_PCREL"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -3284,12 +3143,10 @@ static inline void gen_pcrel(DisasContext *ctx, int opc, target_ulong pc, static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) { - const char *opn = "r6 mul/div"; TCGv t0, t1; if (rd == 0) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -3318,7 +3175,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "div"; break; case R6_OPC_MOD: { @@ -3338,7 +3194,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "mod"; break; case R6_OPC_DIVU: { @@ -3352,7 +3207,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "divu"; break; case R6_OPC_MODU: { @@ -3366,7 +3220,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "modu"; break; case R6_OPC_MUL: { @@ -3379,7 +3232,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free_i32(t2); tcg_temp_free_i32(t3); } - opn = "mul"; break; case R6_OPC_MUH: { @@ -3392,7 +3244,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free_i32(t2); tcg_temp_free_i32(t3); } - opn = "muh"; break; case R6_OPC_MULU: { @@ -3405,7 +3256,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free_i32(t2); tcg_temp_free_i32(t3); } - opn = "mulu"; break; case R6_OPC_MUHU: { @@ -3418,7 +3268,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free_i32(t2); tcg_temp_free_i32(t3); } - opn = "muhu"; break; #if defined(TARGET_MIPS64) case R6_OPC_DDIV: @@ -3436,7 +3285,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "ddiv"; break; case R6_OPC_DMOD: { @@ -3453,7 +3301,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "dmod"; break; case R6_OPC_DDIVU: { @@ -3464,7 +3311,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "ddivu"; break; case R6_OPC_DMODU: { @@ -3475,11 +3321,9 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "dmodu"; break; case R6_OPC_DMUL: tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); - opn = "dmul"; break; case R6_OPC_DMUH: { @@ -3487,11 +3331,9 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_muls2_i64(t2, cpu_gpr[rd], t0, t1); tcg_temp_free(t2); } - opn = "dmuh"; break; case R6_OPC_DMULU: tcg_gen_mul_i64(cpu_gpr[rd], t0, t1); - opn = "dmulu"; break; case R6_OPC_DMUHU: { @@ -3499,16 +3341,13 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) tcg_gen_mulu2_i64(t2, cpu_gpr[rd], t0, t1); tcg_temp_free(t2); } - opn = "dmuhu"; break; #endif default: - MIPS_INVAL(opn); - generate_exception(ctx, EXCP_RI); + MIPS_INVAL("r6 mul/div"); + generate_exception_end(ctx, EXCP_RI); goto out; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]); out: tcg_temp_free(t0); tcg_temp_free(t1); @@ -3517,7 +3356,6 @@ static void gen_r6_muldiv(DisasContext *ctx, int opc, int rd, int rs, int rt) static void gen_muldiv(DisasContext *ctx, uint32_t opc, int acc, int rs, int rt) { - const char *opn = "mul/div"; TCGv t0, t1; t0 = tcg_temp_new(); @@ -3551,7 +3389,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "div"; break; case OPC_DIVU: { @@ -3567,7 +3404,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "divu"; break; case OPC_MULT: { @@ -3581,7 +3417,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_temp_free_i32(t2); tcg_temp_free_i32(t3); } - opn = "mult"; break; case OPC_MULTU: { @@ -3595,7 +3430,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_temp_free_i32(t2); tcg_temp_free_i32(t3); } - opn = "multu"; break; #if defined(TARGET_MIPS64) case OPC_DDIV: @@ -3614,7 +3448,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "ddiv"; break; case OPC_DDIVU: { @@ -3626,15 +3459,12 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_temp_free(t3); tcg_temp_free(t2); } - opn = "ddivu"; break; case OPC_DMULT: tcg_gen_muls2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); - opn = "dmult"; break; case OPC_DMULTU: tcg_gen_mulu2_i64(cpu_LO[acc], cpu_HI[acc], t0, t1); - opn = "dmultu"; break; #endif case OPC_MADD: @@ -3648,14 +3478,10 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); tcg_temp_free_i64(t3); - tcg_gen_trunc_i64_tl(t0, t2); - tcg_gen_shri_i64(t2, t2, 32); - tcg_gen_trunc_i64_tl(t1, t2); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[acc], t0); - tcg_gen_ext32s_tl(cpu_HI[acc], t1); } - opn = "madd"; break; case OPC_MADDU: { @@ -3670,14 +3496,10 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_add_i64(t2, t2, t3); tcg_temp_free_i64(t3); - tcg_gen_trunc_i64_tl(t0, t2); - tcg_gen_shri_i64(t2, t2, 32); - tcg_gen_trunc_i64_tl(t1, t2); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[acc], t0); - tcg_gen_ext32s_tl(cpu_HI[acc], t1); } - opn = "maddu"; break; case OPC_MSUB: { @@ -3690,14 +3512,10 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); tcg_temp_free_i64(t3); - tcg_gen_trunc_i64_tl(t0, t2); - tcg_gen_shri_i64(t2, t2, 32); - tcg_gen_trunc_i64_tl(t1, t2); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[acc], t0); - tcg_gen_ext32s_tl(cpu_HI[acc], t1); } - opn = "msub"; break; case OPC_MSUBU: { @@ -3712,22 +3530,16 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, tcg_gen_concat_tl_i64(t3, cpu_LO[acc], cpu_HI[acc]); tcg_gen_sub_i64(t2, t3, t2); tcg_temp_free_i64(t3); - tcg_gen_trunc_i64_tl(t0, t2); - tcg_gen_shri_i64(t2, t2, 32); - tcg_gen_trunc_i64_tl(t1, t2); + gen_move_low32(cpu_LO[acc], t2); + gen_move_high32(cpu_HI[acc], t2); tcg_temp_free_i64(t2); - tcg_gen_ext32s_tl(cpu_LO[acc], t0); - tcg_gen_ext32s_tl(cpu_HI[acc], t1); } - opn = "msubu"; break; default: - MIPS_INVAL(opn); - generate_exception(ctx, EXCP_RI); + MIPS_INVAL("mul/div"); + generate_exception_end(ctx, EXCP_RI); goto out; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s %s", opn, regnames[rs], regnames[rt]); out: tcg_temp_free(t0); tcg_temp_free(t1); @@ -3736,7 +3548,6 @@ static void gen_muldiv(DisasContext *ctx, uint32_t opc, static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { - const char *opn = "mul vr54xx"; TCGv t0 = tcg_temp_new(); TCGv t1 = tcg_temp_new(); @@ -3746,68 +3557,52 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, switch (opc) { case OPC_VR54XX_MULS: gen_helper_muls(t0, cpu_env, t0, t1); - opn = "muls"; break; case OPC_VR54XX_MULSU: gen_helper_mulsu(t0, cpu_env, t0, t1); - opn = "mulsu"; break; case OPC_VR54XX_MACC: gen_helper_macc(t0, cpu_env, t0, t1); - opn = "macc"; break; case OPC_VR54XX_MACCU: gen_helper_maccu(t0, cpu_env, t0, t1); - opn = "maccu"; break; case OPC_VR54XX_MSAC: gen_helper_msac(t0, cpu_env, t0, t1); - opn = "msac"; break; case OPC_VR54XX_MSACU: gen_helper_msacu(t0, cpu_env, t0, t1); - opn = "msacu"; break; case OPC_VR54XX_MULHI: gen_helper_mulhi(t0, cpu_env, t0, t1); - opn = "mulhi"; break; case OPC_VR54XX_MULHIU: gen_helper_mulhiu(t0, cpu_env, t0, t1); - opn = "mulhiu"; break; case OPC_VR54XX_MULSHI: gen_helper_mulshi(t0, cpu_env, t0, t1); - opn = "mulshi"; break; case OPC_VR54XX_MULSHIU: gen_helper_mulshiu(t0, cpu_env, t0, t1); - opn = "mulshiu"; break; case OPC_VR54XX_MACCHI: gen_helper_macchi(t0, cpu_env, t0, t1); - opn = "macchi"; break; case OPC_VR54XX_MACCHIU: gen_helper_macchiu(t0, cpu_env, t0, t1); - opn = "macchiu"; break; case OPC_VR54XX_MSACHI: gen_helper_msachi(t0, cpu_env, t0, t1); - opn = "msachi"; break; case OPC_VR54XX_MSACHIU: gen_helper_msachiu(t0, cpu_env, t0, t1); - opn = "msachiu"; break; default: MIPS_INVAL("mul vr54xx"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } gen_store_gpr(t0, rd); - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, %s", opn, regnames[rd], regnames[rs], regnames[rt]); out: tcg_temp_free(t0); @@ -3817,12 +3612,10 @@ static void gen_mul_vr54xx (DisasContext *ctx, uint32_t opc, static void gen_cl (DisasContext *ctx, uint32_t opc, int rd, int rs) { - const char *opn = "CLx"; TCGv t0; if (rd == 0) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } t0 = tcg_temp_new(); @@ -3831,28 +3624,22 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, case OPC_CLO: case R6_OPC_CLO: gen_helper_clo(cpu_gpr[rd], t0); - opn = "clo"; break; case OPC_CLZ: case R6_OPC_CLZ: gen_helper_clz(cpu_gpr[rd], t0); - opn = "clz"; break; #if defined(TARGET_MIPS64) case OPC_DCLO: case R6_OPC_DCLO: gen_helper_dclo(cpu_gpr[rd], t0); - opn = "dclo"; break; case OPC_DCLZ: case R6_OPC_DCLZ: gen_helper_dclz(cpu_gpr[rd], t0); - opn = "dclz"; break; #endif } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); tcg_temp_free(t0); } @@ -3860,12 +3647,10 @@ static void gen_cl (DisasContext *ctx, uint32_t opc, static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, int rd, int rs, int rt) { - const char *opn = "loongson"; TCGv t0, t1; if (rd == 0) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -3897,7 +3682,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, case OPC_MULT_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - opn = "mult.g"; break; case OPC_MULTU_G_2E: case OPC_MULTU_G_2F: @@ -3905,7 +3689,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_ext32u_tl(t1, t1); tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); - opn = "multu.g"; break; case OPC_DIV_G_2E: case OPC_DIV_G_2F: @@ -3928,7 +3711,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); gen_set_label(l3); } - opn = "div.g"; break; case OPC_DIVU_G_2E: case OPC_DIVU_G_2F: @@ -3945,7 +3727,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); gen_set_label(l2); } - opn = "divu.g"; break; case OPC_MOD_G_2E: case OPC_MOD_G_2F: @@ -3966,7 +3747,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); gen_set_label(l3); } - opn = "mod.g"; break; case OPC_MODU_G_2E: case OPC_MODU_G_2F: @@ -3983,18 +3763,15 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_ext32s_tl(cpu_gpr[rd], cpu_gpr[rd]); gen_set_label(l2); } - opn = "modu.g"; break; #if defined(TARGET_MIPS64) case OPC_DMULT_G_2E: case OPC_DMULT_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - opn = "dmult.g"; break; case OPC_DMULTU_G_2E: case OPC_DMULTU_G_2F: tcg_gen_mul_tl(cpu_gpr[rd], t0, t1); - opn = "dmultu.g"; break; case OPC_DDIV_G_2E: case OPC_DDIV_G_2F: @@ -4014,7 +3791,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_div_tl(cpu_gpr[rd], t0, t1); gen_set_label(l3); } - opn = "ddiv.g"; break; case OPC_DDIVU_G_2E: case OPC_DDIVU_G_2F: @@ -4028,7 +3804,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_divu_tl(cpu_gpr[rd], t0, t1); gen_set_label(l2); } - opn = "ddivu.g"; break; case OPC_DMOD_G_2E: case OPC_DMOD_G_2F: @@ -4046,7 +3821,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_rem_tl(cpu_gpr[rd], t0, t1); gen_set_label(l3); } - opn = "dmod.g"; break; case OPC_DMODU_G_2E: case OPC_DMODU_G_2F: @@ -4060,13 +3834,10 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, tcg_gen_remu_tl(cpu_gpr[rd], t0, t1); gen_set_label(l2); } - opn = "dmodu.g"; break; #endif } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s", opn, regnames[rd], regnames[rs]); tcg_temp_free(t0); tcg_temp_free(t1); } @@ -4074,7 +3845,6 @@ static void gen_loongson_integer(DisasContext *ctx, uint32_t opc, /* Loongson multimedia instructions */ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) { - const char *opn = "loongson_cp2"; uint32_t opc, shift_max; TCGv_i64 t0, t1; @@ -4097,11 +3867,11 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) gen_load_fpr64(ctx, t1, rt); #define LMI_HELPER(UP, LO) \ - case OPC_##UP: gen_helper_##LO(t0, t0, t1); opn = #LO; break + case OPC_##UP: gen_helper_##LO(t0, t0, t1); break #define LMI_HELPER_1(UP, LO) \ - case OPC_##UP: gen_helper_##LO(t0, t0); opn = #LO; break + case OPC_##UP: gen_helper_##LO(t0, t0); break #define LMI_DIRECT(UP, LO, OP) \ - case OPC_##UP: tcg_gen_##OP##_i64(t0, t0, t1); opn = #LO; break + case OPC_##UP: tcg_gen_##OP##_i64(t0, t0, t1); break switch (opc) { LMI_HELPER(PADDSH, paddsh); @@ -4172,19 +3942,15 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) case OPC_PINSRH_0: tcg_gen_deposit_i64(t0, t0, t1, 0, 16); - opn = "pinsrh_0"; break; case OPC_PINSRH_1: tcg_gen_deposit_i64(t0, t0, t1, 16, 16); - opn = "pinsrh_1"; break; case OPC_PINSRH_2: tcg_gen_deposit_i64(t0, t0, t1, 32, 16); - opn = "pinsrh_2"; break; case OPC_PINSRH_3: tcg_gen_deposit_i64(t0, t0, t1, 48, 16); - opn = "pinsrh_3"; break; case OPC_PEXTRH: @@ -4192,42 +3958,33 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) tcg_gen_shli_i64(t1, t1, 4); tcg_gen_shr_i64(t0, t0, t1); tcg_gen_ext16u_i64(t0, t0); - opn = "pextrh"; break; case OPC_ADDU_CP2: tcg_gen_add_i64(t0, t0, t1); tcg_gen_ext32s_i64(t0, t0); - opn = "addu"; break; case OPC_SUBU_CP2: tcg_gen_sub_i64(t0, t0, t1); tcg_gen_ext32s_i64(t0, t0); - opn = "addu"; break; case OPC_SLL_CP2: - opn = "sll"; shift_max = 32; goto do_shift; case OPC_SRL_CP2: - opn = "srl"; shift_max = 32; goto do_shift; case OPC_SRA_CP2: - opn = "sra"; shift_max = 32; goto do_shift; case OPC_DSLL_CP2: - opn = "dsll"; shift_max = 64; goto do_shift; case OPC_DSRL_CP2: - opn = "dsrl"; shift_max = 64; goto do_shift; case OPC_DSRA_CP2: - opn = "dsra"; shift_max = 64; goto do_shift; do_shift: @@ -4282,8 +4039,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(lab); - - opn = (opc == OPC_ADD_CP2 ? "add" : "dadd"); break; } @@ -4305,8 +4060,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) tcg_gen_brcondi_i64(TCG_COND_GE, t1, 0, lab); generate_exception(ctx, EXCP_OVERFLOW); gen_set_label(lab); - - opn = (opc == OPC_SUB_CP2 ? "sub" : "dsub"); break; } @@ -4314,7 +4067,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) tcg_gen_ext32u_i64(t0, t0); tcg_gen_ext32u_i64(t1, t1); tcg_gen_mul_i64(t0, t0, t1); - opn = "pmuluw"; break; case OPC_SEQU_CP2: @@ -4326,8 +4078,8 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) /* ??? Document is unclear: Set FCC[CC]. Does that mean the FD field is the CC field? */ default: - MIPS_INVAL(opn); - generate_exception(ctx, EXCP_RI); + MIPS_INVAL("loongson_cp2"); + generate_exception_end(ctx, EXCP_RI); return; } @@ -4336,9 +4088,6 @@ static void gen_loongson_multimedia(DisasContext *ctx, int rd, int rs, int rt) gen_store_fpr64(ctx, t0, rd); - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, %s", opn, - fregnames[rd], fregnames[rs], fregnames[rt]); tcg_temp_free_i64(t0); tcg_temp_free_i64(t1); } @@ -4390,7 +4139,7 @@ static void gen_trap (DisasContext *ctx, uint32_t opc, case OPC_TGEU: /* rs >= rs unsigned */ case OPC_TGEIU: /* r0 >= 0 unsigned */ /* Always trap */ - generate_exception(ctx, EXCP_TRAP); + generate_exception_end(ctx, EXCP_TRAP); break; case OPC_TLT: /* rs < rs */ case OPC_TLTI: /* r0 < 0 */ @@ -4450,7 +4199,7 @@ static inline void gen_goto_tb(DisasContext *ctx, int n, target_ulong dest) gen_save_pc(dest); if (ctx->singlestep_enabled) { save_cpu_state(ctx, 0); - gen_helper_0e0i(raise_exception, EXCP_DEBUG); + gen_helper_raise_exception_debug(cpu_env); } tcg_gen_exit_tb(0); } @@ -4473,7 +4222,7 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc); #endif - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } @@ -4533,14 +4282,14 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, /* Hint = 0 is JR/JALR, hint 16 is JR.HB/JALR.HB, the others are reserved. */ MIPS_INVAL("jump hint"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } gen_load_gpr(btarget, rs); break; default: MIPS_INVAL("branch/jump"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } if (bcond_compute == 0) { @@ -4554,20 +4303,17 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, case OPC_BLEZL: /* 0 <= 0 likely */ /* Always take */ ctx->hflags |= MIPS_HFLAG_B; - MIPS_DEBUG("balways"); break; case OPC_BGEZAL: /* 0 >= 0 */ case OPC_BGEZALL: /* 0 >= 0 likely */ /* Always take and link */ blink = 31; ctx->hflags |= MIPS_HFLAG_B; - MIPS_DEBUG("balways and link"); break; case OPC_BNE: /* rx != rx */ case OPC_BGTZ: /* 0 > 0 */ case OPC_BLTZ: /* 0 < 0 */ /* Treat as NOP. */ - MIPS_DEBUG("bnever (NOP)"); goto out; case OPC_BLTZAL: /* 0 < 0 */ /* Handle as an unconditional branch to get correct delay @@ -4575,24 +4321,20 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, blink = 31; btgt = ctx->pc + insn_bytes + delayslot_size; ctx->hflags |= MIPS_HFLAG_B; - MIPS_DEBUG("bnever and link"); break; case OPC_BLTZALL: /* 0 < 0 likely */ tcg_gen_movi_tl(cpu_gpr[31], ctx->pc + 8); /* Skip the instruction in the delay slot */ - MIPS_DEBUG("bnever, link and skip"); ctx->pc += 4; goto out; case OPC_BNEL: /* rx != rx likely */ case OPC_BGTZL: /* 0 > 0 likely */ case OPC_BLTZL: /* 0 < 0 likely */ /* Skip the instruction in the delay slot */ - MIPS_DEBUG("bnever and skip"); ctx->pc += 4; goto out; case OPC_J: ctx->hflags |= MIPS_HFLAG_B; - MIPS_DEBUG("j " TARGET_FMT_lx, btgt); break; case OPC_JALX: ctx->hflags |= MIPS_HFLAG_BX; @@ -4600,118 +4342,91 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, case OPC_JAL: blink = 31; ctx->hflags |= MIPS_HFLAG_B; - MIPS_DEBUG("jal " TARGET_FMT_lx, btgt); break; case OPC_JR: ctx->hflags |= MIPS_HFLAG_BR; - MIPS_DEBUG("jr %s", regnames[rs]); break; case OPC_JALR: blink = rt; ctx->hflags |= MIPS_HFLAG_BR; - MIPS_DEBUG("jalr %s, %s", regnames[rt], regnames[rs]); break; default: MIPS_INVAL("branch/jump"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } } else { switch (opc) { case OPC_BEQ: tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); - MIPS_DEBUG("beq %s, %s, " TARGET_FMT_lx, - regnames[rs], regnames[rt], btgt); goto not_likely; case OPC_BEQL: tcg_gen_setcond_tl(TCG_COND_EQ, bcond, t0, t1); - MIPS_DEBUG("beql %s, %s, " TARGET_FMT_lx, - regnames[rs], regnames[rt], btgt); goto likely; case OPC_BNE: tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); - MIPS_DEBUG("bne %s, %s, " TARGET_FMT_lx, - regnames[rs], regnames[rt], btgt); goto not_likely; case OPC_BNEL: tcg_gen_setcond_tl(TCG_COND_NE, bcond, t0, t1); - MIPS_DEBUG("bnel %s, %s, " TARGET_FMT_lx, - regnames[rs], regnames[rt], btgt); goto likely; case OPC_BGEZ: tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); - MIPS_DEBUG("bgez %s, " TARGET_FMT_lx, regnames[rs], btgt); goto not_likely; case OPC_BGEZL: tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); - MIPS_DEBUG("bgezl %s, " TARGET_FMT_lx, regnames[rs], btgt); goto likely; case OPC_BGEZAL: tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); - MIPS_DEBUG("bgezal %s, " TARGET_FMT_lx, regnames[rs], btgt); blink = 31; goto not_likely; case OPC_BGEZALL: tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 0); blink = 31; - MIPS_DEBUG("bgezall %s, " TARGET_FMT_lx, regnames[rs], btgt); goto likely; case OPC_BGTZ: tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); - MIPS_DEBUG("bgtz %s, " TARGET_FMT_lx, regnames[rs], btgt); goto not_likely; case OPC_BGTZL: tcg_gen_setcondi_tl(TCG_COND_GT, bcond, t0, 0); - MIPS_DEBUG("bgtzl %s, " TARGET_FMT_lx, regnames[rs], btgt); goto likely; case OPC_BLEZ: tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); - MIPS_DEBUG("blez %s, " TARGET_FMT_lx, regnames[rs], btgt); goto not_likely; case OPC_BLEZL: tcg_gen_setcondi_tl(TCG_COND_LE, bcond, t0, 0); - MIPS_DEBUG("blezl %s, " TARGET_FMT_lx, regnames[rs], btgt); goto likely; case OPC_BLTZ: tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); - MIPS_DEBUG("bltz %s, " TARGET_FMT_lx, regnames[rs], btgt); goto not_likely; case OPC_BLTZL: tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); - MIPS_DEBUG("bltzl %s, " TARGET_FMT_lx, regnames[rs], btgt); goto likely; case OPC_BPOSGE32: tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 32); - MIPS_DEBUG("bposge32 " TARGET_FMT_lx, btgt); goto not_likely; #if defined(TARGET_MIPS64) case OPC_BPOSGE64: tcg_gen_setcondi_tl(TCG_COND_GE, bcond, t0, 64); - MIPS_DEBUG("bposge64 " TARGET_FMT_lx, btgt); goto not_likely; #endif case OPC_BLTZAL: tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); blink = 31; - MIPS_DEBUG("bltzal %s, " TARGET_FMT_lx, regnames[rs], btgt); not_likely: ctx->hflags |= MIPS_HFLAG_BC; break; case OPC_BLTZALL: tcg_gen_setcondi_tl(TCG_COND_LT, bcond, t0, 0); blink = 31; - MIPS_DEBUG("bltzall %s, " TARGET_FMT_lx, regnames[rs], btgt); likely: ctx->hflags |= MIPS_HFLAG_BL; break; default: MIPS_INVAL("conditional branch/jump"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } } - MIPS_DEBUG("enter ds: link %d cond %02x target " TARGET_FMT_lx, - blink, ctx->hflags, btgt); ctx->btarget = btgt; @@ -4802,7 +4517,7 @@ static void gen_bitops (DisasContext *ctx, uint32_t opc, int rt, default: fail: MIPS_INVAL("bitops"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); tcg_temp_free(t0); tcg_temp_free(t1); return; @@ -4818,7 +4533,6 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) if (rd == 0) { /* If no destination, treat it as a NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -4875,7 +4589,7 @@ static void gen_bshfl (DisasContext *ctx, uint32_t op2, int rt, int rd) #endif default: MIPS_INVAL("bsfhl"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); tcg_temp_free(t0); return; } @@ -5048,12 +4762,6 @@ static inline void gen_mtc0_store32 (TCGv arg, target_ulong off) tcg_temp_free_i32(t0); } -static inline void gen_mtc0_store64 (TCGv arg, target_ulong off) -{ - tcg_gen_ext32s_tl(arg, arg); - tcg_gen_st_tl(arg, cpu_env, off); -} - static void gen_mfhc0(DisasContext *ctx, TCGv arg, int reg, int sel) { const char *rn = "invalid"; @@ -5912,12 +5620,14 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) break; case 5: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPESchedule)); + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPESchedule)); rn = "VPESchedule"; break; case 6: CP0_CHECK(ctx->insn_flags & ASE_MT); - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_VPEScheFBack)); + tcg_gen_st_tl(arg, cpu_env, + offsetof(CPUMIPSState, CP0_VPEScheFBack)); rn = "VPEScheFBack"; break; case 7: @@ -6167,7 +5877,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 14: switch (sel) { case 0: - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_EPC)); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EPC)); rn = "EPC"; break; default: @@ -6340,7 +6050,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) switch (sel) { case 0: /* EJTAG support */ - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_DEPC)); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_DEPC)); rn = "DEPC"; break; default: @@ -6443,7 +6153,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel) case 30: switch (sel) { case 0: - gen_mtc0_store64(arg, offsetof(CPUMIPSState, CP0_ErrorEPC)); + tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_ErrorEPC)); rn = "ErrorEPC"; break; default: @@ -7942,7 +7652,7 @@ static void gen_mftr(CPUMIPSState *env, DisasContext *ctx, int rt, int rd, die: tcg_temp_free(t0); LOG_DISAS("mftr (reg %d u %d sel %d h %d)\n", rt, u, sel, h); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, @@ -8123,7 +7833,6 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, break; case 3: /* XXX: For now we support only a single FPU context. */ - save_cpu_state(ctx, 1); { TCGv_i32 fs_tmp = tcg_const_i32(rd); @@ -8147,7 +7856,7 @@ static void gen_mttr(CPUMIPSState *env, DisasContext *ctx, int rd, int rt, die: tcg_temp_free(t0); LOG_DISAS("mttr (reg %d u %d sel %d h %d)\n", rd, u, sel, h); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, int rd) @@ -8276,7 +7985,6 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, case OPC_ERET: /* OPC_ERETNC */ if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { - MIPS_DEBUG("CTI in delay / forbidden slot"); goto die; } else { int bit_shift = (ctx->hflags & MIPS_HFLAG_M16) ? 16 : 6; @@ -8299,12 +8007,11 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, check_insn(ctx, ISA_MIPS32); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { - MIPS_DEBUG("CTI in delay / forbidden slot"); goto die; } if (!(ctx->hflags & MIPS_HFLAG_DM)) { MIPS_INVAL(opn); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } else { gen_helper_deret(cpu_env); ctx->bstate = BS_EXCP; @@ -8315,7 +8022,6 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, check_insn(ctx, ISA_MIPS3 | ISA_MIPS32); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { - MIPS_DEBUG("CTI in delay / forbidden slot"); goto die; } /* If we get an exception, we want to restart at next instruction */ @@ -8328,11 +8034,10 @@ static void gen_cp0 (CPUMIPSState *env, DisasContext *ctx, uint32_t opc, int rt, default: die: MIPS_INVAL(opn); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s %d", opn, regnames[rt], rd); } #endif /* !CONFIG_USER_ONLY */ @@ -8341,12 +8046,10 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, int32_t cc, int32_t offset) { target_ulong btarget; - const char *opn = "cp1 cond branch"; TCGv_i32 t0 = tcg_temp_new_i32(); if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { - MIPS_DEBUG("CTI in delay / forbidden slot"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } @@ -8361,26 +8064,22 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_not_i32(t0, t0); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); - opn = "bc1f"; goto not_likely; case OPC_BC1FL: tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_not_i32(t0, t0); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); - opn = "bc1fl"; goto likely; case OPC_BC1T: tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); - opn = "bc1t"; goto not_likely; case OPC_BC1TL: tcg_gen_shri_i32(t0, fpu_fcr31, get_fp_bit(cc)); tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); - opn = "bc1tl"; likely: ctx->hflags |= MIPS_HFLAG_BL; break; @@ -8394,7 +8093,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } - opn = "bc1any2f"; goto not_likely; case OPC_BC1TANY2: { @@ -8406,7 +8104,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } - opn = "bc1any2t"; goto not_likely; case OPC_BC1FANY4: { @@ -8422,7 +8119,6 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } - opn = "bc1any4f"; goto not_likely; case OPC_BC1TANY4: { @@ -8438,18 +8134,14 @@ static void gen_compute_branch1(DisasContext *ctx, uint32_t op, tcg_gen_andi_i32(t0, t0, 1); tcg_gen_extu_i32_tl(bcond, t0); } - opn = "bc1any4t"; not_likely: ctx->hflags |= MIPS_HFLAG_BC; break; default: - MIPS_INVAL(opn); - generate_exception (ctx, EXCP_RI); + MIPS_INVAL("cp1 cond branch"); + generate_exception_end(ctx, EXCP_RI); goto out; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn, - ctx->hflags, btarget); ctx->btarget = btarget; ctx->hflags |= MIPS_HFLAG_BDS32; out: @@ -8462,7 +8154,6 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, int delayslot_size) { target_ulong btarget; - const char *opn = "cp1 cond branch"; TCGv_i64 t0 = tcg_temp_new_i64(); if (ctx->hflags & MIPS_HFLAG_BMASK) { @@ -8470,7 +8161,7 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc); #endif - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } @@ -8482,25 +8173,20 @@ static void gen_compute_branch1_r6(DisasContext *ctx, uint32_t op, switch (op) { case OPC_BC1EQZ: tcg_gen_xori_i64(t0, t0, 1); - opn = "bc1eqz"; ctx->hflags |= MIPS_HFLAG_BC; break; case OPC_BC1NEZ: /* t0 already set */ - opn = "bc1nez"; ctx->hflags |= MIPS_HFLAG_BC; break; default: - MIPS_INVAL(opn); - generate_exception(ctx, EXCP_RI); + MIPS_INVAL("cp1 cond branch"); + generate_exception_end(ctx, EXCP_RI); goto out; } tcg_gen_trunc_i64_tl(bcond, t0); - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s: cond %02x target " TARGET_FMT_lx, opn, - ctx->hflags, btarget); ctx->btarget = btarget; switch (delayslot_size) { @@ -8731,7 +8417,6 @@ enum r6_f_cmp_op { }; static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) { - const char *opn = "cp1 move"; TCGv t0 = tcg_temp_new(); switch (opc) { @@ -8744,7 +8429,6 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) tcg_temp_free_i32(fp0); } gen_store_gpr(t0, rt); - opn = "mfc1"; break; case OPC_MTC1: gen_load_gpr(t0, rt); @@ -8755,16 +8439,14 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) gen_store_fpr32(ctx, fp0, fs); tcg_temp_free_i32(fp0); } - opn = "mtc1"; break; case OPC_CFC1: gen_helper_1e0i(cfc1, t0, fs); gen_store_gpr(t0, rt); - opn = "cfc1"; break; case OPC_CTC1: gen_load_gpr(t0, rt); - save_cpu_state(ctx, 1); + save_cpu_state(ctx, 0); { TCGv_i32 fs_tmp = tcg_const_i32(fs); @@ -8773,18 +8455,15 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) } /* Stop translation as we may have changed hflags */ ctx->bstate = BS_STOP; - opn = "ctc1"; break; #if defined(TARGET_MIPS64) case OPC_DMFC1: gen_load_fpr64(ctx, t0, fs); gen_store_gpr(t0, rt); - opn = "dmfc1"; break; case OPC_DMTC1: gen_load_gpr(t0, rt); gen_store_fpr64(ctx, t0, fs); - opn = "dmtc1"; break; #endif case OPC_MFHC1: @@ -8796,7 +8475,6 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) tcg_temp_free_i32(fp0); } gen_store_gpr(t0, rt); - opn = "mfhc1"; break; case OPC_MTHC1: gen_load_gpr(t0, rt); @@ -8807,15 +8485,12 @@ static void gen_cp1 (DisasContext *ctx, uint32_t opc, int rt, int fs) gen_store_fpr32h(ctx, fp0, fs); tcg_temp_free_i32(fp0); } - opn = "mthc1"; break; default: - MIPS_INVAL(opn); - generate_exception (ctx, EXCP_RI); + MIPS_INVAL("cp1 move"); + generate_exception_end(ctx, EXCP_RI); goto out; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s %s", opn, regnames[rt], fregnames[fs]); out: tcg_temp_free(t0); @@ -8945,7 +8620,7 @@ static void gen_sel_s(DisasContext *ctx, enum fopcode op1, int fd, int ft, break; default: MIPS_INVAL("gen_sel_s"); - generate_exception (ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -8982,7 +8657,7 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, break; default: MIPS_INVAL("gen_sel_d"); - generate_exception (ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -8996,44 +8671,6 @@ static void gen_sel_d(DisasContext *ctx, enum fopcode op1, int fd, int ft, static void gen_farith (DisasContext *ctx, enum fopcode op1, int ft, int fs, int fd, int cc) { - const char *opn = "farith"; - const char *condnames[] = { - "c.f", - "c.un", - "c.eq", - "c.ueq", - "c.olt", - "c.ult", - "c.ole", - "c.ule", - "c.sf", - "c.ngle", - "c.seq", - "c.ngl", - "c.lt", - "c.nge", - "c.le", - "c.ngt", - }; - const char *condnames_abs[] = { - "cabs.f", - "cabs.un", - "cabs.eq", - "cabs.ueq", - "cabs.olt", - "cabs.ult", - "cabs.ole", - "cabs.ule", - "cabs.sf", - "cabs.ngle", - "cabs.seq", - "cabs.ngl", - "cabs.lt", - "cabs.nge", - "cabs.le", - "cabs.ngt", - }; - enum { BINOP, CMPOP, OTHEROP } optype = OTHEROP; uint32_t func = ctx->opcode & 0x3f; switch (op1) { case OPC_ADD_S: @@ -9048,8 +8685,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "add.s"; - optype = BINOP; break; case OPC_SUB_S: { @@ -9063,8 +8698,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "sub.s"; - optype = BINOP; break; case OPC_MUL_S: { @@ -9078,8 +8711,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "mul.s"; - optype = BINOP; break; case OPC_DIV_S: { @@ -9093,8 +8724,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "div.s"; - optype = BINOP; break; case OPC_SQRT_S: { @@ -9105,7 +8734,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "sqrt.s"; break; case OPC_ABS_S: { @@ -9116,7 +8744,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "abs.s"; break; case OPC_MOV_S: { @@ -9126,7 +8753,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "mov.s"; break; case OPC_NEG_S: { @@ -9137,7 +8763,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "neg.s"; break; case OPC_ROUND_L_S: check_cp1_64bitmode(ctx); @@ -9151,7 +8776,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); } - opn = "round.l.s"; break; case OPC_TRUNC_L_S: check_cp1_64bitmode(ctx); @@ -9165,7 +8789,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); } - opn = "trunc.l.s"; break; case OPC_CEIL_L_S: check_cp1_64bitmode(ctx); @@ -9179,7 +8802,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); } - opn = "ceil.l.s"; break; case OPC_FLOOR_L_S: check_cp1_64bitmode(ctx); @@ -9193,7 +8815,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); } - opn = "floor.l.s"; break; case OPC_ROUND_W_S: { @@ -9204,7 +8825,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "round.w.s"; break; case OPC_TRUNC_W_S: { @@ -9215,7 +8835,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "trunc.w.s"; break; case OPC_CEIL_W_S: { @@ -9226,7 +8845,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "ceil.w.s"; break; case OPC_FLOOR_W_S: { @@ -9237,27 +8855,22 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "floor.w.s"; break; case OPC_SEL_S: check_insn(ctx, ISA_MIPS32R6); gen_sel_s(ctx, op1, fd, ft, fs); - opn = "sel.s"; break; case OPC_SELEQZ_S: check_insn(ctx, ISA_MIPS32R6); gen_sel_s(ctx, op1, fd, ft, fs); - opn = "seleqz.s"; break; case OPC_SELNEZ_S: check_insn(ctx, ISA_MIPS32R6); gen_sel_s(ctx, op1, fd, ft, fs); - opn = "selnez.s"; break; case OPC_MOVCF_S: check_insn_opc_removed(ctx, ISA_MIPS32R6); gen_movcf_s(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); - opn = "movcf.s"; break; case OPC_MOVZ_S: check_insn_opc_removed(ctx, ISA_MIPS32R6); @@ -9274,7 +8887,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp0); gen_set_label(l1); } - opn = "movz.s"; break; case OPC_MOVN_S: check_insn_opc_removed(ctx, ISA_MIPS32R6); @@ -9291,10 +8903,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_set_label(l1); } } - opn = "movn.s"; break; case OPC_RECIP_S: - check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(); @@ -9303,10 +8913,8 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "recip.s"; break; case OPC_RSQRT_S: - check_cop1x(ctx); { TCGv_i32 fp0 = tcg_temp_new_i32(); @@ -9315,7 +8923,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "rsqrt.s"; break; case OPC_MADDF_S: check_insn(ctx, ISA_MIPS32R6); @@ -9331,7 +8938,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp2); tcg_temp_free_i32(fp1); tcg_temp_free_i32(fp0); - opn = "maddf.s"; } break; case OPC_MSUBF_S: @@ -9348,7 +8954,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp2); tcg_temp_free_i32(fp1); tcg_temp_free_i32(fp0); - opn = "msubf.s"; } break; case OPC_RINT_S: @@ -9359,7 +8964,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_helper_float_rint_s(fp0, cpu_env, fp0); gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); - opn = "rint.s"; } break; case OPC_CLASS_S: @@ -9370,7 +8974,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_helper_float_class_s(fp0, fp0); gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); - opn = "class.s"; } break; case OPC_MIN_S: /* OPC_RECIP2_S */ @@ -9386,7 +8989,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp2); tcg_temp_free_i32(fp1); tcg_temp_free_i32(fp0); - opn = "min.s"; } else { /* OPC_RECIP2_S */ check_cp1_64bitmode(ctx); @@ -9401,7 +9003,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "recip2.s"; } break; case OPC_MINA_S: /* OPC_RECIP1_S */ @@ -9417,7 +9018,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp2); tcg_temp_free_i32(fp1); tcg_temp_free_i32(fp0); - opn = "mina.s"; } else { /* OPC_RECIP1_S */ check_cp1_64bitmode(ctx); @@ -9429,7 +9029,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "recip1.s"; } break; case OPC_MAX_S: /* OPC_RSQRT1_S */ @@ -9443,7 +9042,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp1, fd); tcg_temp_free_i32(fp1); tcg_temp_free_i32(fp0); - opn = "max.s"; } else { /* OPC_RSQRT1_S */ check_cp1_64bitmode(ctx); @@ -9455,7 +9053,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "rsqrt1.s"; } break; case OPC_MAXA_S: /* OPC_RSQRT2_S */ @@ -9469,7 +9066,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp1, fd); tcg_temp_free_i32(fp1); tcg_temp_free_i32(fp0); - opn = "maxa.s"; } else { /* OPC_RSQRT2_S */ check_cp1_64bitmode(ctx); @@ -9484,7 +9080,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "rsqrt2.s"; } break; case OPC_CVT_D_S: @@ -9499,7 +9094,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); } - opn = "cvt.d.s"; break; case OPC_CVT_W_S: { @@ -9510,7 +9104,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "cvt.w.s"; break; case OPC_CVT_L_S: check_cp1_64bitmode(ctx); @@ -9524,7 +9117,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); } - opn = "cvt.l.s"; break; case OPC_CVT_PS_S: check_ps(ctx); @@ -9541,7 +9133,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); } - opn = "cvt.ps.s"; break; case OPC_CMP_F_S: case OPC_CMP_UN_S: @@ -9562,12 +9153,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, check_insn_opc_removed(ctx, ISA_MIPS32R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_s(ctx, func-48, ft, fs, cc); - opn = condnames_abs[func-48]; } else { gen_cmp_s(ctx, func-48, ft, fs, cc); - opn = condnames[func-48]; } - optype = CMPOP; break; case OPC_ADD_D: check_cp1_registers(ctx, fs | ft | fd); @@ -9582,8 +9170,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "add.d"; - optype = BINOP; break; case OPC_SUB_D: check_cp1_registers(ctx, fs | ft | fd); @@ -9598,8 +9184,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "sub.d"; - optype = BINOP; break; case OPC_MUL_D: check_cp1_registers(ctx, fs | ft | fd); @@ -9614,8 +9198,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "mul.d"; - optype = BINOP; break; case OPC_DIV_D: check_cp1_registers(ctx, fs | ft | fd); @@ -9630,8 +9212,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "div.d"; - optype = BINOP; break; case OPC_SQRT_D: check_cp1_registers(ctx, fs | fd); @@ -9643,7 +9223,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "sqrt.d"; break; case OPC_ABS_D: check_cp1_registers(ctx, fs | fd); @@ -9655,7 +9234,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "abs.d"; break; case OPC_MOV_D: check_cp1_registers(ctx, fs | fd); @@ -9666,7 +9244,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "mov.d"; break; case OPC_NEG_D: check_cp1_registers(ctx, fs | fd); @@ -9678,7 +9255,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "neg.d"; break; case OPC_ROUND_L_D: check_cp1_64bitmode(ctx); @@ -9690,7 +9266,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "round.l.d"; break; case OPC_TRUNC_L_D: check_cp1_64bitmode(ctx); @@ -9702,7 +9277,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "trunc.l.d"; break; case OPC_CEIL_L_D: check_cp1_64bitmode(ctx); @@ -9714,7 +9288,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "ceil.l.d"; break; case OPC_FLOOR_L_D: check_cp1_64bitmode(ctx); @@ -9726,7 +9299,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "floor.l.d"; break; case OPC_ROUND_W_D: check_cp1_registers(ctx, fs); @@ -9740,7 +9312,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } - opn = "round.w.d"; break; case OPC_TRUNC_W_D: check_cp1_registers(ctx, fs); @@ -9754,7 +9325,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } - opn = "trunc.w.d"; break; case OPC_CEIL_W_D: check_cp1_registers(ctx, fs); @@ -9768,7 +9338,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } - opn = "ceil.w.d"; break; case OPC_FLOOR_W_D: check_cp1_registers(ctx, fs); @@ -9782,27 +9351,22 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } - opn = "floor.w.d"; break; case OPC_SEL_D: check_insn(ctx, ISA_MIPS32R6); gen_sel_d(ctx, op1, fd, ft, fs); - opn = "sel.d"; break; case OPC_SELEQZ_D: check_insn(ctx, ISA_MIPS32R6); gen_sel_d(ctx, op1, fd, ft, fs); - opn = "seleqz.d"; break; case OPC_SELNEZ_D: check_insn(ctx, ISA_MIPS32R6); gen_sel_d(ctx, op1, fd, ft, fs); - opn = "selnez.d"; break; case OPC_MOVCF_D: check_insn_opc_removed(ctx, ISA_MIPS32R6); gen_movcf_d(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); - opn = "movcf.d"; break; case OPC_MOVZ_D: check_insn_opc_removed(ctx, ISA_MIPS32R6); @@ -9819,7 +9383,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i64(fp0); gen_set_label(l1); } - opn = "movz.d"; break; case OPC_MOVN_D: check_insn_opc_removed(ctx, ISA_MIPS32R6); @@ -9836,10 +9399,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_set_label(l1); } } - opn = "movn.d"; break; case OPC_RECIP_D: - check_cp1_64bitmode(ctx); + check_cp1_registers(ctx, fs | fd); { TCGv_i64 fp0 = tcg_temp_new_i64(); @@ -9848,10 +9410,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "recip.d"; break; case OPC_RSQRT_D: - check_cp1_64bitmode(ctx); + check_cp1_registers(ctx, fs | fd); { TCGv_i64 fp0 = tcg_temp_new_i64(); @@ -9860,7 +9421,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "rsqrt.d"; break; case OPC_MADDF_D: check_insn(ctx, ISA_MIPS32R6); @@ -9876,7 +9436,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i64(fp2); tcg_temp_free_i64(fp1); tcg_temp_free_i64(fp0); - opn = "maddf.d"; } break; case OPC_MSUBF_D: @@ -9893,7 +9452,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i64(fp2); tcg_temp_free_i64(fp1); tcg_temp_free_i64(fp0); - opn = "msubf.d"; } break; case OPC_RINT_D: @@ -9904,7 +9462,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_helper_float_rint_d(fp0, cpu_env, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); - opn = "rint.d"; } break; case OPC_CLASS_D: @@ -9915,7 +9472,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_helper_float_class_d(fp0, fp0); gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); - opn = "class.d"; } break; case OPC_MIN_D: /* OPC_RECIP2_D */ @@ -9929,7 +9485,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp1, fd); tcg_temp_free_i64(fp1); tcg_temp_free_i64(fp0); - opn = "min.d"; } else { /* OPC_RECIP2_D */ check_cp1_64bitmode(ctx); @@ -9944,7 +9499,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "recip2.d"; } break; case OPC_MINA_D: /* OPC_RECIP1_D */ @@ -9958,7 +9512,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp1, fd); tcg_temp_free_i64(fp1); tcg_temp_free_i64(fp0); - opn = "mina.d"; } else { /* OPC_RECIP1_D */ check_cp1_64bitmode(ctx); @@ -9970,7 +9523,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "recip1.d"; } break; case OPC_MAX_D: /* OPC_RSQRT1_D */ @@ -9984,7 +9536,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp1, fd); tcg_temp_free_i64(fp1); tcg_temp_free_i64(fp0); - opn = "max.d"; } else { /* OPC_RSQRT1_D */ check_cp1_64bitmode(ctx); @@ -9996,7 +9547,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "rsqrt1.d"; } break; case OPC_MAXA_D: /* OPC_RSQRT2_D */ @@ -10010,7 +9560,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp1, fd); tcg_temp_free_i64(fp1); tcg_temp_free_i64(fp0); - opn = "maxa.d"; } else { /* OPC_RSQRT2_D */ check_cp1_64bitmode(ctx); @@ -10025,7 +9574,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "rsqrt2.d"; } break; case OPC_CMP_F_D: @@ -10047,12 +9595,9 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, check_insn_opc_removed(ctx, ISA_MIPS32R6); if (ctx->opcode & (1 << 6)) { gen_cmpabs_d(ctx, func-48, ft, fs, cc); - opn = condnames_abs[func-48]; } else { gen_cmp_d(ctx, func-48, ft, fs, cc); - opn = condnames[func-48]; } - optype = CMPOP; break; case OPC_CVT_S_D: check_cp1_registers(ctx, fs); @@ -10066,7 +9611,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } - opn = "cvt.s.d"; break; case OPC_CVT_W_D: check_cp1_registers(ctx, fs); @@ -10080,7 +9624,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } - opn = "cvt.w.d"; break; case OPC_CVT_L_D: check_cp1_64bitmode(ctx); @@ -10092,7 +9635,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "cvt.l.d"; break; case OPC_CVT_S_W: { @@ -10103,7 +9645,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "cvt.s.w"; break; case OPC_CVT_D_W: check_cp1_registers(ctx, fd); @@ -10117,7 +9658,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp64, fd); tcg_temp_free_i64(fp64); } - opn = "cvt.d.w"; break; case OPC_CVT_S_L: check_cp1_64bitmode(ctx); @@ -10131,7 +9671,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp32, fd); tcg_temp_free_i32(fp32); } - opn = "cvt.s.l"; break; case OPC_CVT_D_L: check_cp1_64bitmode(ctx); @@ -10143,7 +9682,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "cvt.d.l"; break; case OPC_CVT_PS_PW: check_ps(ctx); @@ -10155,7 +9693,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "cvt.ps.pw"; break; case OPC_ADD_PS: check_ps(ctx); @@ -10170,7 +9707,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "add.ps"; break; case OPC_SUB_PS: check_ps(ctx); @@ -10185,7 +9721,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "sub.ps"; break; case OPC_MUL_PS: check_ps(ctx); @@ -10200,7 +9735,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "mul.ps"; break; case OPC_ABS_PS: check_ps(ctx); @@ -10212,7 +9746,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "abs.ps"; break; case OPC_MOV_PS: check_ps(ctx); @@ -10223,7 +9756,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "mov.ps"; break; case OPC_NEG_PS: check_ps(ctx); @@ -10235,12 +9767,10 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "neg.ps"; break; case OPC_MOVCF_PS: check_ps(ctx); gen_movcf_ps(ctx, fs, fd, (ft >> 2) & 0x7, ft & 0x1); - opn = "movcf.ps"; break; case OPC_MOVZ_PS: check_ps(ctx); @@ -10256,7 +9786,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i64(fp0); gen_set_label(l1); } - opn = "movz.ps"; break; case OPC_MOVN_PS: check_ps(ctx); @@ -10273,7 +9802,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_set_label(l1); } } - opn = "movn.ps"; break; case OPC_ADDR_PS: check_ps(ctx); @@ -10288,7 +9816,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "addr.ps"; break; case OPC_MULR_PS: check_ps(ctx); @@ -10303,7 +9830,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "mulr.ps"; break; case OPC_RECIP2_PS: check_ps(ctx); @@ -10318,7 +9844,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "recip2.ps"; break; case OPC_RECIP1_PS: check_ps(ctx); @@ -10330,7 +9855,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "recip1.ps"; break; case OPC_RSQRT1_PS: check_ps(ctx); @@ -10342,7 +9866,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "rsqrt1.ps"; break; case OPC_RSQRT2_PS: check_ps(ctx); @@ -10357,7 +9880,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "rsqrt2.ps"; break; case OPC_CVT_S_PU: check_cp1_64bitmode(ctx); @@ -10369,7 +9891,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "cvt.s.pu"; break; case OPC_CVT_PW_PS: check_ps(ctx); @@ -10381,7 +9902,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "cvt.pw.ps"; break; case OPC_CVT_S_PL: check_cp1_64bitmode(ctx); @@ -10393,7 +9913,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "cvt.s.pl"; break; case OPC_PLL_PS: check_ps(ctx); @@ -10408,7 +9927,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } - opn = "pll.ps"; break; case OPC_PLU_PS: check_ps(ctx); @@ -10423,7 +9941,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } - opn = "plu.ps"; break; case OPC_PUL_PS: check_ps(ctx); @@ -10438,7 +9955,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } - opn = "pul.ps"; break; case OPC_PUU_PS: check_ps(ctx); @@ -10453,7 +9969,6 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, tcg_temp_free_i32(fp0); tcg_temp_free_i32(fp1); } - opn = "puu.ps"; break; case OPC_CMP_F_PS: case OPC_CMP_UN_PS: @@ -10473,38 +9988,21 @@ static void gen_farith (DisasContext *ctx, enum fopcode op1, case OPC_CMP_NGT_PS: if (ctx->opcode & (1 << 6)) { gen_cmpabs_ps(ctx, func-48, ft, fs, cc); - opn = condnames_abs[func-48]; } else { gen_cmp_ps(ctx, func-48, ft, fs, cc); - opn = condnames[func-48]; } - optype = CMPOP; break; default: - MIPS_INVAL(opn); - generate_exception (ctx, EXCP_RI); + MIPS_INVAL("farith"); + generate_exception_end(ctx, EXCP_RI); return; } - (void)opn; /* avoid a compiler warning */ - switch (optype) { - case BINOP: - MIPS_DEBUG("%s %s, %s, %s", opn, fregnames[fd], fregnames[fs], fregnames[ft]); - break; - case CMPOP: - MIPS_DEBUG("%s %s,%s", opn, fregnames[fs], fregnames[ft]); - break; - default: - MIPS_DEBUG("%s %s,%s", opn, fregnames[fd], fregnames[fs]); - break; - } } /* Coprocessor 3 (FPU) */ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, int fd, int fs, int base, int index) { - const char *opn = "extended float load/store"; - int store = 0; TCGv t0 = tcg_temp_new(); if (base == 0) { @@ -10527,7 +10025,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, gen_store_fpr32(ctx, fp0, fd); tcg_temp_free_i32(fp0); } - opn = "lwxc1"; break; case OPC_LDXC1: check_cop1x(ctx); @@ -10538,7 +10035,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "ldxc1"; break; case OPC_LUXC1: check_cp1_64bitmode(ctx); @@ -10550,7 +10046,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp0, fd); tcg_temp_free_i64(fp0); } - opn = "luxc1"; break; case OPC_SWXC1: check_cop1x(ctx); @@ -10560,8 +10055,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, tcg_gen_qemu_st_i32(fp0, t0, ctx->mem_idx, MO_TEUL); tcg_temp_free_i32(fp0); } - opn = "swxc1"; - store = 1; break; case OPC_SDXC1: check_cop1x(ctx); @@ -10572,8 +10065,6 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ); tcg_temp_free_i64(fp0); } - opn = "sdxc1"; - store = 1; break; case OPC_SUXC1: check_cp1_64bitmode(ctx); @@ -10584,21 +10075,14 @@ static void gen_flt3_ldst (DisasContext *ctx, uint32_t opc, tcg_gen_qemu_st_i64(fp0, t0, ctx->mem_idx, MO_TEQ); tcg_temp_free_i64(fp0); } - opn = "suxc1"; - store = 1; break; } tcg_temp_free(t0); - (void)opn; (void)store; /* avoid compiler warnings */ - MIPS_DEBUG("%s %s, %s(%s)", opn, fregnames[store ? fs : fd], - regnames[index], regnames[base]); } static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, int fd, int fr, int fs, int ft) { - const char *opn = "flt3_arith"; - switch (opc) { case OPC_ALNV_PS: check_ps(ctx); @@ -10636,7 +10120,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, tcg_temp_free_i32(fp); tcg_temp_free_i32(fph); } - opn = "alnv.ps"; break; case OPC_MADD_S: check_cop1x(ctx); @@ -10654,7 +10137,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr32(ctx, fp2, fd); tcg_temp_free_i32(fp2); } - opn = "madd.s"; break; case OPC_MADD_D: check_cop1x(ctx); @@ -10673,7 +10155,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } - opn = "madd.d"; break; case OPC_MADD_PS: check_ps(ctx); @@ -10691,7 +10172,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } - opn = "madd.ps"; break; case OPC_MSUB_S: check_cop1x(ctx); @@ -10709,7 +10189,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr32(ctx, fp2, fd); tcg_temp_free_i32(fp2); } - opn = "msub.s"; break; case OPC_MSUB_D: check_cop1x(ctx); @@ -10728,7 +10207,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } - opn = "msub.d"; break; case OPC_MSUB_PS: check_ps(ctx); @@ -10746,7 +10224,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } - opn = "msub.ps"; break; case OPC_NMADD_S: check_cop1x(ctx); @@ -10764,7 +10241,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr32(ctx, fp2, fd); tcg_temp_free_i32(fp2); } - opn = "nmadd.s"; break; case OPC_NMADD_D: check_cop1x(ctx); @@ -10783,7 +10259,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } - opn = "nmadd.d"; break; case OPC_NMADD_PS: check_ps(ctx); @@ -10801,7 +10276,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } - opn = "nmadd.ps"; break; case OPC_NMSUB_S: check_cop1x(ctx); @@ -10819,7 +10293,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr32(ctx, fp2, fd); tcg_temp_free_i32(fp2); } - opn = "nmsub.s"; break; case OPC_NMSUB_D: check_cop1x(ctx); @@ -10838,7 +10311,6 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } - opn = "nmsub.d"; break; case OPC_NMSUB_PS: check_ps(ctx); @@ -10856,16 +10328,12 @@ static void gen_flt3_arith (DisasContext *ctx, uint32_t opc, gen_store_fpr64(ctx, fp2, fd); tcg_temp_free_i64(fp2); } - opn = "nmsub.ps"; break; default: - MIPS_INVAL(opn); - generate_exception (ctx, EXCP_RI); + MIPS_INVAL("flt3_arith"); + generate_exception_end(ctx, EXCP_RI); return; } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s, %s, %s", opn, fregnames[fd], fregnames[fr], - fregnames[fs], fregnames[ft]); } static void gen_rdhwr(DisasContext *ctx, int rt, int rd) @@ -10881,22 +10349,18 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd) switch (rd) { case 0: - save_cpu_state(ctx, 1); gen_helper_rdhwr_cpunum(t0, cpu_env); gen_store_gpr(t0, rt); break; case 1: - save_cpu_state(ctx, 1); gen_helper_rdhwr_synci_step(t0, cpu_env); gen_store_gpr(t0, rt); break; case 2: - save_cpu_state(ctx, 1); gen_helper_rdhwr_cc(t0, cpu_env); gen_store_gpr(t0, rt); break; case 3: - save_cpu_state(ctx, 1); gen_helper_rdhwr_ccres(t0, cpu_env); gen_store_gpr(t0, rt); break; @@ -10913,13 +10377,13 @@ static void gen_rdhwr(DisasContext *ctx, int rt, int rd) offsetof(CPUMIPSState, active_tc.CP0_UserLocal)); gen_store_gpr(t0, rt); } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } break; #endif default: /* Invalid */ MIPS_INVAL("rdhwr"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } tcg_temp_free(t0); @@ -10947,12 +10411,10 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) /* FIXME: Need to clear can_do_io. */ switch (proc_hflags & MIPS_HFLAG_BMASK_BASE) { case MIPS_HFLAG_FBNSLOT: - MIPS_DEBUG("forbidden slot"); gen_goto_tb(ctx, 0, ctx->pc + insn_bytes); break; case MIPS_HFLAG_B: /* unconditional branch */ - MIPS_DEBUG("unconditional branch"); if (proc_hflags & MIPS_HFLAG_BX) { tcg_gen_xori_i32(hflags, hflags, MIPS_HFLAG_M16); } @@ -10960,12 +10422,10 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) break; case MIPS_HFLAG_BL: /* blikely taken case */ - MIPS_DEBUG("blikely branch taken"); gen_goto_tb(ctx, 0, ctx->btarget); break; case MIPS_HFLAG_BC: /* Conditional branch */ - MIPS_DEBUG("conditional branch"); { TCGLabel *l1 = gen_new_label(); @@ -10977,7 +10437,6 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) break; case MIPS_HFLAG_BR: /* unconditional branch to register */ - MIPS_DEBUG("branch to register"); if (ctx->insn_flags & (ASE_MIPS16 | ASE_MICROMIPS)) { TCGv t0 = tcg_temp_new(); TCGv_i32 t1 = tcg_temp_new_i32(); @@ -10996,7 +10455,7 @@ static void gen_branch(DisasContext *ctx, int insn_bytes) } if (ctx->singlestep_enabled) { save_cpu_state(ctx, 0); - gen_helper_0e0i(raise_exception, EXCP_DEBUG); + gen_helper_raise_exception_debug(cpu_env); } tcg_gen_exit_tb(0); break; @@ -11021,7 +10480,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, LOG_DISAS("Branch in delay / forbidden slot at PC 0x" TARGET_FMT_lx "\n", ctx->pc); #endif - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } @@ -11083,7 +10542,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } @@ -11104,7 +10563,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact branch/jump"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } @@ -11227,7 +10686,7 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, break; default: MIPS_INVAL("Compact conditional branch/jump"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto out; } @@ -11236,7 +10695,6 @@ static void gen_compute_compact_branch(DisasContext *ctx, uint32_t opc, gen_set_label(fs); ctx->hflags |= MIPS_HFLAG_FBNSLOT; - MIPS_DEBUG("Compact conditional branch"); } out: @@ -11402,7 +10860,7 @@ static void gen_mips16_save (DisasContext *ctx, args = 4; break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } @@ -11498,7 +10956,7 @@ static void gen_mips16_save (DisasContext *ctx, astatic = 4; break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } @@ -11604,7 +11062,7 @@ static void gen_mips16_restore (DisasContext *ctx, astatic = 4; break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } @@ -11635,7 +11093,7 @@ static void gen_addiupc (DisasContext *ctx, int rx, int imm, TCGv t0; if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } @@ -11684,7 +11142,7 @@ static void decode_i64_mips16 (DisasContext *ctx, check_insn(ctx, ISA_MIPS3); check_mips_64(ctx); if (extended && (ctx->hflags & MIPS_HFLAG_BMASK)) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } else { offset = extended ? offset : offset << 3; gen_ld(ctx, OPC_LDPC, ry, 0, offset); @@ -11759,7 +11217,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); #endif break; case 0x2: @@ -11787,7 +11245,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); #endif } else { gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); @@ -11839,7 +11297,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx) } break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -11902,7 +11360,7 @@ static int decode_extended_mips16_opc (CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -11983,7 +11441,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_shift_imm(ctx, OPC_DSLL, rx, ry, sa); #else - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); #endif break; case 0x2: @@ -12011,7 +11469,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_arith_imm(ctx, OPC_DADDIU, ry, rx, imm); #else - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); #endif } else { gen_arith_imm(ctx, OPC_ADDIU, ry, rx, imm); @@ -12095,7 +11553,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) gen_arith(ctx, OPC_ADDU, ry, reg32, 0); break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -12185,7 +11643,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); goto done; } @@ -12224,7 +11682,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) * when in debug mode... */ check_insn(ctx, ISA_MIPS32); - generate_exception(ctx, EXCP_DBp); + generate_exception_end(ctx, EXCP_DBp); } break; case RR_SLT: @@ -12234,7 +11692,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) gen_slt(ctx, OPC_SLTU, 24, rx, ry); break; case RR_BREAK: - generate_exception(ctx, EXCP_BREAK); + generate_exception_end(ctx, EXCP_BREAK); break; case RR_SLLV: gen_shift(ctx, OPC_SLLV, ry, rx, ry); @@ -12301,7 +11759,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -12365,7 +11823,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -12380,7 +11838,7 @@ static int decode_mips16_opc (CPUMIPSState *env, DisasContext *ctx) break; #endif default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -13027,12 +12485,11 @@ static void gen_andi16(DisasContext *ctx) static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, int base, int16_t offset) { - const char *opn = "ldst_multiple"; TCGv t0, t1; TCGv_i32 t2; if (ctx->hflags & MIPS_HFLAG_BMASK) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } @@ -13047,25 +12504,19 @@ static void gen_ldst_multiple (DisasContext *ctx, uint32_t opc, int reglist, switch (opc) { case LWM32: gen_helper_lwm(cpu_env, t0, t1, t2); - opn = "lwm"; break; case SWM32: gen_helper_swm(cpu_env, t0, t1, t2); - opn = "swm"; break; #ifdef TARGET_MIPS64 case LDM: gen_helper_ldm(cpu_env, t0, t1, t2); - opn = "ldm"; break; case SDM: gen_helper_sdm(cpu_env, t0, t1, t2); - opn = "sdm"; break; #endif } - (void)opn; - MIPS_DEBUG("%s, %x, %d(%s)", opn, reglist, offset, regnames[base]); tcg_temp_free(t0); tcg_temp_free(t1); tcg_temp_free_i32(t2); @@ -13162,7 +12613,7 @@ static void gen_pool16c_insn(DisasContext *ctx) gen_HILO(ctx, OPC_MFLO, 0, uMIPS_RS5(ctx->opcode)); break; case BREAK16: - generate_exception(ctx, EXCP_BREAK); + generate_exception_end(ctx, EXCP_BREAK); break; case SDBBP16: if (is_uhi(extract32(ctx->opcode, 0, 4))) { @@ -13172,7 +12623,7 @@ static void gen_pool16c_insn(DisasContext *ctx) * when in debug mode... */ check_insn(ctx, ISA_MIPS32); - generate_exception(ctx, EXCP_DBp); + generate_exception_end(ctx, EXCP_DBp); } break; case JRADDIUSP + 0: @@ -13186,7 +12637,7 @@ static void gen_pool16c_insn(DisasContext *ctx) } break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -13322,11 +12773,10 @@ static void gen_ldxs (DisasContext *ctx, int base, int index, int rd) static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, int base, int16_t offset) { - const char *opn = "ldst_pair"; TCGv t0, t1; if (ctx->hflags & MIPS_HFLAG_BMASK || rd == 31) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } @@ -13338,7 +12788,7 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, switch (opc) { case LWP: if (rd == base) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); @@ -13347,7 +12797,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, gen_op_addr_add(ctx, t0, t0, t1); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TESL); gen_store_gpr(t1, rd+1); - opn = "lwp"; break; case SWP: gen_load_gpr(t1, rd); @@ -13356,12 +12805,11 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd+1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEUL); - opn = "swp"; break; #ifdef TARGET_MIPS64 case LDP: if (rd == base) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ); @@ -13370,7 +12818,6 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, gen_op_addr_add(ctx, t0, t0, t1); tcg_gen_qemu_ld_tl(t1, t0, ctx->mem_idx, MO_TEQ); gen_store_gpr(t1, rd+1); - opn = "ldp"; break; case SDP: gen_load_gpr(t1, rd); @@ -13379,12 +12826,9 @@ static void gen_ldst_pair (DisasContext *ctx, uint32_t opc, int rd, gen_op_addr_add(ctx, t0, t0, t1); gen_load_gpr(t1, rd+1); tcg_gen_qemu_st_tl(t1, t0, ctx->mem_idx, MO_TEQ); - opn = "sdp"; break; #endif } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s, %s, %d(%s)", opn, regnames[rd], offset, regnames[base]); tcg_temp_free(t0); tcg_temp_free(t1); } @@ -13666,8 +13110,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) /* NOP */ break; case SYSCALL: - generate_exception(ctx, EXCP_SYSCALL); - ctx->bstate = BS_STOP; + generate_exception_end(ctx, EXCP_SYSCALL); break; case SDBBP: if (is_uhi(extract32(ctx->opcode, 16, 10))) { @@ -13675,9 +13118,9 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) } else { check_insn(ctx, ISA_MIPS32); if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } else { - generate_exception(ctx, EXCP_DBp); + generate_exception_end(ctx, EXCP_DBp); } } break; @@ -13725,7 +13168,7 @@ static void gen_pool32axf (CPUMIPSState *env, DisasContext *ctx, int rt, int rs) default: pool32axf_invalid: MIPS_INVAL("pool32axf"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -13993,7 +13436,7 @@ static void gen_pool32fxf(DisasContext *ctx, int rt, int rs) break; default: MIPS_INVAL("pool32fxf"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -14190,12 +13633,12 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_pool32axf(env, ctx, rt, rs); break; case 0x07: - generate_exception(ctx, EXCP_BREAK); + generate_exception_end(ctx, EXCP_BREAK); break; default: pool32a_invalid: MIPS_INVAL("pool32a"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -14235,7 +13678,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("pool32b"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -14715,7 +14158,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) default: pool32f_invalid: MIPS_INVAL("pool32f"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } else { @@ -14871,7 +14314,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) /* Fall through */ default: MIPS_INVAL("pool32i"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -14960,7 +14403,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("pool32c"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -15238,7 +14681,7 @@ static void decode_micromips32_opc(CPUMIPSState *env, DisasContext *ctx) gen_st(ctx, mips32_op, rt, rs, imm); break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -15250,8 +14693,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) /* make sure instructions are on a halfword boundary */ if (ctx->pc & 0x1) { env->CP0_BadVAddr = ctx->pc; - generate_exception(ctx, EXCP_AdEL); - ctx->bstate = BS_STOP; + generate_exception_end(ctx, EXCP_AdEL); return 2; } @@ -15270,9 +14712,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) case 7: /* LB32, LH32, LWC132, LDC132, LW32 */ if (ctx->hflags & MIPS_HFLAG_BDS16) { - generate_exception(ctx, EXCP_RI); - /* Just stop translation; the user is confused. */ - ctx->bstate = BS_STOP; + generate_exception_end(ctx, EXCP_RI); return 2; } break; @@ -15283,9 +14723,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) case 3: /* MOVE16, ANDI16, POOL16D, POOL16E, BEQZ16, BNEZ16, B16, LI16 */ if (ctx->hflags & MIPS_HFLAG_BDS32) { - generate_exception(ctx, EXCP_RI); - /* Just stop translation; the user is confused. */ - ctx->bstate = BS_STOP; + generate_exception_end(ctx, EXCP_RI); return 2; } break; @@ -15357,7 +14795,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) case POOL16F: check_insn_opc_removed(ctx, ISA_MIPS32R6); if (ctx->opcode & 1) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } else { /* MOVEP */ int enc_dest = uMIPS_RD(ctx->opcode); @@ -15495,7 +14933,7 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) case RES_29: case RES_31: case RES_39: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; default: decode_micromips32_opc(env, ctx); @@ -15517,7 +14955,6 @@ static int decode_micromips_opc (CPUMIPSState *env, DisasContext *ctx) static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc, int rd, int base, int offset) { - const char *opn = "ldx"; TCGv t0; check_dsp(ctx); @@ -15535,42 +14972,33 @@ static void gen_mipsdsp_ld(DisasContext *ctx, uint32_t opc, case OPC_LBUX: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_UB); gen_store_gpr(t0, rd); - opn = "lbux"; break; case OPC_LHX: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESW); gen_store_gpr(t0, rd); - opn = "lhx"; break; case OPC_LWX: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TESL); gen_store_gpr(t0, rd); - opn = "lwx"; break; #if defined(TARGET_MIPS64) case OPC_LDX: tcg_gen_qemu_ld_tl(t0, t0, ctx->mem_idx, MO_TEQ); gen_store_gpr(t0, rd); - opn = "ldx"; break; #endif } - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s %s, %s(%s)", opn, - regnames[rd], regnames[offset], regnames[base]); tcg_temp_free(t0); } static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, int ret, int v1, int v2) { - const char *opn = "mipsdsp arith"; TCGv v1_t; TCGv v2_t; if (ret == 0) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -16010,23 +15438,18 @@ static void gen_mipsdsp_arith(DisasContext *ctx, uint32_t op1, uint32_t op2, tcg_temp_free(v1_t); tcg_temp_free(v2_t); - - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s", opn); } static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, int ret, int v1, int v2) { uint32_t op2; - const char *opn = "mipsdsp shift"; TCGv t0; TCGv v1_t; TCGv v2_t; if (ret == 0) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -16133,7 +15556,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, break; default: /* Invalid */ MIPS_INVAL("MASK SHLL.QB"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -16248,7 +15671,7 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, break; default: /* Invalid */ MIPS_INVAL("MASK SHLL.OB"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -16258,21 +15681,17 @@ static void gen_mipsdsp_shift(DisasContext *ctx, uint32_t opc, tcg_temp_free(t0); tcg_temp_free(v1_t); tcg_temp_free(v2_t); - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s", opn); } static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, int ret, int v1, int v2, int check_ret) { - const char *opn = "mipsdsp multiply"; TCGv_i32 t0; TCGv v1_t; TCGv v2_t; if ((ret == 0) && (check_ret == 1)) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -16570,23 +15989,17 @@ static void gen_mipsdsp_multiply(DisasContext *ctx, uint32_t op1, uint32_t op2, tcg_temp_free_i32(t0); tcg_temp_free(v1_t); tcg_temp_free(v2_t); - - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s", opn); - } static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, int ret, int val) { - const char *opn = "mipsdsp Bit/ Manipulation"; int16_t imm; TCGv t0; TCGv val_t; if (ret == 0) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -16714,23 +16127,18 @@ static void gen_mipsdsp_bitinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, } tcg_temp_free(t0); tcg_temp_free(val_t); - - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s", opn); } static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, uint32_t op1, uint32_t op2, int ret, int v1, int v2, int check_ret) { - const char *opn = "mipsdsp add compare pick"; TCGv t1; TCGv v1_t; TCGv v2_t; if ((ret == 0) && (check_ret == 1)) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -16905,22 +16313,17 @@ static void gen_mipsdsp_add_cmp_pick(DisasContext *ctx, tcg_temp_free(t1); tcg_temp_free(v1_t); tcg_temp_free(v2_t); - - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s", opn); } static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, uint32_t op1, int rt, int rs, int sa) { - const char *opn = "mipsdsp append/dappend"; TCGv t0; check_dspr2(ctx); if (rt == 0) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -16957,7 +16360,7 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, break; default: /* Invalid */ MIPS_INVAL("MASK APPEND"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -16991,22 +16394,19 @@ static void gen_mipsdsp_append(CPUMIPSState *env, DisasContext *ctx, break; default: /* Invalid */ MIPS_INVAL("MASK DAPPEND"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; #endif } tcg_temp_free(t0); - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s", opn); } static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, int ret, int v1, int v2, int check_ret) { - const char *opn = "mipsdsp accumulator"; TCGv t0; TCGv t1; TCGv v1_t; @@ -17015,7 +16415,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, if ((ret == 0) && (check_ret == 1)) { /* Treat as NOP. */ - MIPS_DEBUG("NOP"); return; } @@ -17227,9 +16626,6 @@ static void gen_mipsdsp_accinsn(DisasContext *ctx, uint32_t op1, uint32_t op2, tcg_temp_free(t1); tcg_temp_free(v1_t); tcg_temp_free(v2_t); - - (void)opn; /* avoid a compiler warning */ - MIPS_DEBUG("%s", opn); } /* End MIPSDSP functions. */ @@ -17264,7 +16660,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("special_r6 muldiv"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17279,7 +16675,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) We need additionally to check other fields */ gen_cl(ctx, op1, rd, rs); } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } break; case R6_OPC_SDBBP: @@ -17287,9 +16683,9 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) gen_helper_do_semihosting(cpu_env); } else { if (ctx->hflags & MIPS_HFLAG_SBRI) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } else { - generate_exception(ctx, EXCP_DBp); + generate_exception_end(ctx, EXCP_DBp); } } break; @@ -17306,7 +16702,7 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) check_mips_64(ctx); gen_cl(ctx, op1, rd, rs); } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } break; case OPC_DMULT ... OPC_DDIVU: @@ -17325,14 +16721,14 @@ static void decode_opc_special_r6(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("special_r6 muldiv"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; #endif default: /* Invalid */ MIPS_INVAL("special_r6"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -17400,16 +16796,16 @@ static void decode_opc_special_legacy(CPUMIPSState *env, DisasContext *ctx) case OPC_SPIM: #ifdef MIPS_STRICT_STANDARD MIPS_INVAL("SPIM"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); #else /* Implemented as RI exception for now. */ MIPS_INVAL("spim (unofficial)"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); #endif break; default: /* Invalid */ MIPS_INVAL("special_legacy"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -17431,8 +16827,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) rs == 0 && rt == 0) { /* PAUSE */ if ((ctx->insn_flags & ISA_MIPS32R6) && (ctx->hflags & MIPS_HFLAG_BMASK)) { - MIPS_DEBUG("CTI in delay / forbidden slot"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -17452,7 +16847,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17475,7 +16870,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift(ctx, op1, rd, rs, rt); break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17505,18 +16900,17 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) /* Pmon entry point, also R4010 selsl */ #ifdef MIPS_STRICT_STANDARD MIPS_INVAL("PMON / selsl"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); #else gen_helper_0e0i(pmon, sa); #endif } break; case OPC_SYSCALL: - generate_exception(ctx, EXCP_SYSCALL); - ctx->bstate = BS_STOP; + generate_exception_end(ctx, EXCP_SYSCALL); break; case OPC_BREAK: - generate_exception(ctx, EXCP_BREAK); + generate_exception_end(ctx, EXCP_BREAK); break; case OPC_SYNC: check_insn(ctx, ISA_MIPS2); @@ -17547,7 +16941,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17565,7 +16959,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift_imm(ctx, op1, rd, rt, sa); break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17594,7 +16988,7 @@ static void decode_opc_special(CPUMIPSState *env, DisasContext *ctx) gen_shift(ctx, op1, rd, rs, rt); break; default: - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17657,7 +17051,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) * when in debug mode... */ check_insn(ctx, ISA_MIPS32); - generate_exception(ctx, EXCP_DBp); + generate_exception_end(ctx, EXCP_DBp); } break; #if defined(TARGET_MIPS64) @@ -17679,7 +17073,7 @@ static void decode_opc_special2_legacy(CPUMIPSState *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special2_legacy"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -17701,7 +17095,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) case R6_OPC_PREF: if (rt >= 24) { /* hint codes 24-31 are reserved and signal RI */ - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } /* Treat as NOP. */ break; @@ -17760,7 +17154,7 @@ static void decode_opc_special3_r6(CPUMIPSState *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special3_r6"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -17806,13 +17200,13 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MASK ADDUH.QB"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } else if (ctx->insn_flags & INSN_LOONGSON2E) { gen_loongson_integer(ctx, op1, rd, rs, rt); } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } break; case OPC_LX_DSP: @@ -17828,7 +17222,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK LX"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17859,7 +17253,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MASK ABSQ_S.PH"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17896,7 +17290,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.QB"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -17936,7 +17330,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK CMPU.EQ.QB"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17972,7 +17366,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK DPAW.PH"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -17985,7 +17379,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) TCGv t0, t1; if (rt == 0) { - MIPS_DEBUG("NOP"); break; } @@ -18003,7 +17396,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) } default: /* Invalid */ MIPS_INVAL("MASK INSV"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -18038,7 +17431,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK EXTR.W"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -18081,7 +17474,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ABSQ_S.QH"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -18120,7 +17513,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK ADDU.OB"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -18165,7 +17558,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK CMPU_EQ.OB"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -18202,7 +17595,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK EXTR.W"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -18241,7 +17634,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("MASK DPAQ.W.QH"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -18253,7 +17646,6 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) TCGv t0, t1; if (rt == 0) { - MIPS_DEBUG("NOP"); break; } check_dsp(ctx); @@ -18272,7 +17664,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) } default: /* Invalid */ MIPS_INVAL("MASK DINSV"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -18282,7 +17674,7 @@ static void decode_opc_special3_legacy(CPUMIPSState *env, DisasContext *ctx) #endif default: /* Invalid */ MIPS_INVAL("special3_legacy"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -18363,7 +17755,6 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) { TCGv t0 = tcg_temp_new(); - save_cpu_state(ctx, 1); gen_load_gpr(t0, rs); gen_helper_yield(t0, cpu_env, t0); gen_store_gpr(t0, rd); @@ -18384,16 +17775,16 @@ static inline int check_msa_access(DisasContext *ctx) { if (unlikely((ctx->hflags & MIPS_HFLAG_FPU) && !(ctx->hflags & MIPS_HFLAG_F64))) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return 0; } if (unlikely(!(ctx->hflags & MIPS_HFLAG_MSA))) { if (ctx->insn_flags & ASE_MSA) { - generate_exception(ctx, EXCP_MSADIS); + generate_exception_end(ctx, EXCP_MSADIS); return 0; } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return 0; } } @@ -18450,8 +17841,7 @@ static void gen_msa_branch(CPUMIPSState *env, DisasContext *ctx, uint32_t op1) check_msa_access(ctx); if (ctx->insn_flags & ISA_MIPS32R6 && ctx->hflags & MIPS_HFLAG_BMASK) { - MIPS_DEBUG("CTI in delay / forbidden slot"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } switch (op1) { @@ -18526,7 +17916,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx) { uint8_t df = (ctx->opcode >> 24) & 0x3; if (df == DF_DOUBLE) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } else { TCGv_i32 tdf = tcg_const_i32(df); gen_helper_msa_shf_df(cpu_env, tdf, twd, tws, ti8); @@ -18536,7 +17926,7 @@ static void gen_msa_i8(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -18608,7 +17998,7 @@ static void gen_msa_i5(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -18644,7 +18034,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx) m = dfm & 0x7; df = DF_BYTE; } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } @@ -18692,7 +18082,7 @@ static void gen_msa_bit(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -18887,7 +18277,8 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) case OPC_HSUB_S_df: case OPC_HSUB_U_df: if (df == DF_BYTE) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); + break; } switch (MASK_MSA_3R(ctx->opcode)) { case OPC_DOTP_S_df: @@ -18924,7 +18315,7 @@ static void gen_msa_3r(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } tcg_temp_free_i32(twd); @@ -18956,7 +18347,7 @@ static void gen_msa_elm_3e(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -18993,7 +18384,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ if (df == DF_DOUBLE) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } #endif @@ -19011,7 +18402,7 @@ static void gen_msa_elm_df(CPUMIPSState *env, DisasContext *ctx, uint32_t df, break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } tcg_temp_free_i32(twd); tcg_temp_free_i32(tws); @@ -19041,7 +18432,7 @@ static void gen_msa_elm(CPUMIPSState *env, DisasContext *ctx) gen_msa_elm_3e(env, ctx); return; } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); return; } @@ -19196,7 +18587,7 @@ static void gen_msa_3rf(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -19224,7 +18615,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx) #if !defined(TARGET_MIPS64) /* Double format valid only for MIPS64 */ if (df == DF_DOUBLE) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } #endif @@ -19241,7 +18632,7 @@ static void gen_msa_2r(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -19356,7 +18747,7 @@ static void gen_msa_vec_v(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -19385,7 +18776,7 @@ static void gen_msa_vec(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -19483,7 +18874,7 @@ static void gen_msa(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("MSA instruction"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } @@ -19500,7 +18891,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (ctx->pc & 0x3) { env->CP0_BadVAddr = ctx->pc; generate_exception_err(ctx, EXCP_AdEL, EXCP_INST_NOTAVAIL); - ctx->bstate = BS_STOP; return; } @@ -19508,7 +18898,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if ((ctx->hflags & MIPS_HFLAG_BMASK_BASE) == MIPS_HFLAG_BL) { TCGLabel *l1 = gen_new_label(); - MIPS_DEBUG("blikely condition (" TARGET_FMT_lx ")", ctx->pc + 4); tcg_gen_brcondi_tl(TCG_COND_NE, bcond, 0, l1); tcg_gen_movi_i32(hflags, ctx->hflags & ~MIPS_HFLAG_BMASK); gen_goto_tb(ctx, 1, ctx->pc + 4); @@ -19556,7 +18945,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) /* OPC_NAL, OPC_BAL */ gen_compute_branch(ctx, op1, 4, 0, -1, imm << 2, 4); } else { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } } else { gen_compute_branch(ctx, op1, 4, rs, -1, imm << 2, 4); @@ -19588,7 +18977,6 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (rs != 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 32); } - MIPS_DEBUG("dahi %s, %04x", regnames[rs], imm); break; case OPC_DATI: check_insn(ctx, ISA_MIPS32R6); @@ -19596,12 +18984,11 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) if (rs != 0) { tcg_gen_addi_tl(cpu_gpr[rs], cpu_gpr[rs], (int64_t)imm << 48); } - MIPS_DEBUG("dati %s, %04x", regnames[rs], imm); break; #endif default: /* Invalid */ MIPS_INVAL("regimm"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -19676,7 +19063,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("mfmc0"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } tcg_temp_free(t0); @@ -19693,7 +19080,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("cp0"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -19728,7 +19115,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) case OPC_BLEZC: /* OPC_BGEZC, OPC_BGEC, OPC_BLEZL */ if (ctx->insn_flags & ISA_MIPS32R6) { if (rt == 0) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } /* OPC_BLEZC, OPC_BGEZC, OPC_BGEC */ @@ -19741,7 +19128,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) case OPC_BGTZC: /* OPC_BLTZC, OPC_BLTC, OPC_BGTZL */ if (ctx->insn_flags & ISA_MIPS32R6) { if (rt == 0) { - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } /* OPC_BGTZC, OPC_BLTZC, OPC_BLTC */ @@ -19971,7 +19358,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("cp1"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } break; @@ -20053,7 +19440,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: MIPS_INVAL("cp3"); - generate_exception (ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } else { @@ -20109,7 +19496,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) gen_compute_compact_branch(ctx, op, rs, rt, imm << 2); } else { MIPS_INVAL("major opcode"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); } break; #endif @@ -20118,15 +19505,16 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) #if defined(TARGET_MIPS64) /* OPC_DAUI */ check_mips_64(ctx); - if (rt != 0) { + if (rs == 0) { + generate_exception(ctx, EXCP_RI); + } else if (rt != 0) { TCGv t0 = tcg_temp_new(); gen_load_gpr(t0, rs); tcg_gen_addi_tl(cpu_gpr[rt], t0, imm << 16); tcg_temp_free(t0); } - MIPS_DEBUG("daui %s, %s, %04x", regnames[rt], regnames[rs], imm); #else - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); MIPS_INVAL("major opcode"); #endif } else { @@ -20146,7 +19534,7 @@ static void decode_opc(CPUMIPSState *env, DisasContext *ctx) break; default: /* Invalid */ MIPS_INVAL("major opcode"); - generate_exception(ctx, EXCP_RI); + generate_exception_end(ctx, EXCP_RI); break; } } @@ -20212,7 +19600,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, if (bp->pc == ctx.pc) { save_cpu_state(&ctx, 1); ctx.bstate = BS_BRANCH; - gen_helper_0e0i(raise_exception, EXCP_DEBUG); + gen_helper_raise_exception_debug(cpu_env); /* Include the breakpoint location or the tb won't * be flushed when it must be. */ ctx.pc += 4; @@ -20249,8 +19637,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, ctx.opcode = cpu_lduw_code(env, ctx.pc); insn_bytes = decode_mips16_opc(env, &ctx); } else { - generate_exception(&ctx, EXCP_RI); - ctx.bstate = BS_STOP; + generate_exception_end(&ctx, EXCP_RI); break; } @@ -20302,7 +19689,7 @@ gen_intermediate_code_internal(MIPSCPU *cpu, TranslationBlock *tb, } if (cs->singlestep_enabled && ctx.bstate != BS_BRANCH) { save_cpu_state(&ctx, ctx.bstate != BS_EXCP); - gen_helper_0e0i(raise_exception, EXCP_DEBUG); + gen_helper_raise_exception_debug(cpu_env); } else { switch (ctx.bstate) { case BS_STOP: @@ -20392,40 +19779,6 @@ static void fpu_dump_state(CPUMIPSState *env, FILE *f, fprintf_function fpu_fpri #undef printfpr } -#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) -/* Debug help: The architecture requires 32bit code to maintain proper - sign-extended values on 64bit machines. */ - -#define SIGN_EXT_P(val) ((((val) & ~0x7fffffff) == 0) || (((val) & ~0x7fffffff) == ~0x7fffffff)) - -static void -cpu_mips_check_sign_extensions (CPUMIPSState *env, FILE *f, - fprintf_function cpu_fprintf, - int flags) -{ - int i; - - if (!SIGN_EXT_P(env->active_tc.PC)) - cpu_fprintf(f, "BROKEN: pc=0x" TARGET_FMT_lx "\n", env->active_tc.PC); - if (!SIGN_EXT_P(env->active_tc.HI[0])) - cpu_fprintf(f, "BROKEN: HI=0x" TARGET_FMT_lx "\n", env->active_tc.HI[0]); - if (!SIGN_EXT_P(env->active_tc.LO[0])) - cpu_fprintf(f, "BROKEN: LO=0x" TARGET_FMT_lx "\n", env->active_tc.LO[0]); - if (!SIGN_EXT_P(env->btarget)) - cpu_fprintf(f, "BROKEN: btarget=0x" TARGET_FMT_lx "\n", env->btarget); - - for (i = 0; i < 32; i++) { - if (!SIGN_EXT_P(env->active_tc.gpr[i])) - cpu_fprintf(f, "BROKEN: %s=0x" TARGET_FMT_lx "\n", regnames[i], env->active_tc.gpr[i]); - } - - if (!SIGN_EXT_P(env->CP0_EPC)) - cpu_fprintf(f, "BROKEN: EPC=0x" TARGET_FMT_lx "\n", env->CP0_EPC); - if (!SIGN_EXT_P(env->lladdr)) - cpu_fprintf(f, "BROKEN: LLAddr=0x" TARGET_FMT_lx "\n", env->lladdr); -} -#endif - void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -20457,9 +19810,6 @@ void mips_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, env->CP0_Config4, env->CP0_Config5); if (env->hflags & MIPS_HFLAG_FPU) fpu_dump_state(env, f, cpu_fprintf, flags); -#if defined(TARGET_MIPS64) && defined(MIPS_DEBUG_SIGN_EXTENSIONS) - cpu_mips_check_sign_extensions(env, f, cpu_fprintf, flags); -#endif } void mips_tcg_init(void) diff --git a/util/error.c b/util/error.c index cdb726ce81..8b86490ba1 100644 --- a/util/error.c +++ b/util/error.c @@ -2,9 +2,11 @@ * QEMU Error Objects * * Copyright IBM, Corp. 2011 + * Copyright (C) 2011-2015 Red Hat, Inc. * * Authors: * Anthony Liguori <aliguori@us.ibm.com> + * Markus Armbruster <armbru@redhat.com>, * * This work is licensed under the terms of the GNU LGPL, version 2. See * the COPYING.LIB file in the top-level directory. @@ -20,16 +22,24 @@ struct Error ErrorClass err_class; const char *src, *func; int line; + GString *hint; }; Error *error_abort; +Error *error_fatal; -static void error_do_abort(Error *err) +static void error_handle_fatal(Error **errp, Error *err) { - fprintf(stderr, "Unexpected error in %s() at %s:%d:\n", - err->func, err->src, err->line); - error_report_err(err); - abort(); + if (errp == &error_abort) { + fprintf(stderr, "Unexpected error in %s() at %s:%d:\n", + err->func, err->src, err->line); + error_report_err(err); + abort(); + } + if (errp == &error_fatal) { + error_report_err(err); + exit(1); + } } static void error_setv(Error **errp, @@ -51,10 +61,7 @@ static void error_setv(Error **errp, err->line = line; err->func = func; - if (errp == &error_abort) { - error_do_abort(err); - } - + error_handle_fatal(errp, err); *errp = err; errno = saved_errno; @@ -115,6 +122,28 @@ void error_setg_file_open_internal(Error **errp, "Could not open '%s'", filename); } +void error_append_hint(Error **errp, const char *fmt, ...) +{ + va_list ap; + int saved_errno = errno; + Error *err; + + if (!errp) { + return; + } + err = *errp; + assert(err && errp != &error_abort); + + if (!err->hint) { + err->hint = g_string_new(NULL); + } + va_start(ap, fmt); + g_string_append_vprintf(err->hint, fmt, ap); + va_end(ap); + + errno = saved_errno; +} + #ifdef _WIN32 void error_setg_win32_internal(Error **errp, @@ -151,6 +180,12 @@ Error *error_copy(const Error *err) err_new = g_malloc0(sizeof(*err)); err_new->msg = g_strdup(err->msg); err_new->err_class = err->err_class; + err_new->src = err->src; + err_new->line = err->line; + err_new->func = err->func; + if (err->hint) { + err_new->hint = g_string_new(err->hint->str); + } return err_new; } @@ -168,6 +203,9 @@ const char *error_get_pretty(Error *err) void error_report_err(Error *err) { error_report("%s", error_get_pretty(err)); + if (err->hint) { + error_printf_unless_qmp("%s\n", err->hint->str); + } error_free(err); } @@ -175,17 +213,22 @@ void error_free(Error *err) { if (err) { g_free(err->msg); + if (err->hint) { + g_string_free(err->hint, true); + } g_free(err); } } void error_propagate(Error **dst_errp, Error *local_err) { - if (local_err && dst_errp == &error_abort) { - error_do_abort(local_err); - } else if (dst_errp && !*dst_errp) { + if (!local_err) { + return; + } + error_handle_fatal(dst_errp, local_err); + if (dst_errp && !*dst_errp) { *dst_errp = local_err; - } else if (local_err) { + } else { error_free(local_err); } } diff --git a/util/qemu-error.c b/util/qemu-error.c index 77ea6c6145..c1574bb348 100644 --- a/util/qemu-error.c +++ b/util/qemu-error.c @@ -210,7 +210,7 @@ void error_vreport(const char *fmt, va_list ap) GTimeVal tv; gchar *timestr; - if (enable_timestamp_msg) { + if (enable_timestamp_msg && !cur_mon) { g_get_current_time(&tv); timestr = g_time_val_to_iso8601(&tv); error_printf("%s ", timestr); diff --git a/util/qemu-option.c b/util/qemu-option.c index b1fb57c0fc..a50eceae4a 100644 --- a/util/qemu-option.c +++ b/util/qemu-option.c @@ -205,10 +205,8 @@ void parse_option_size(const char *name, const char *value, break; default: error_setg(errp, QERR_INVALID_PARAMETER_VALUE, name, "a size"); -#if 0 /* conversion from qerror_report() to error_set() broke this: */ - error_printf_unless_qmp("You may use k, M, G or T suffixes for " - "kilobytes, megabytes, gigabytes and terabytes.\n"); -#endif + error_append_hint(errp, "You may use k, M, G or T suffixes for " + "kilobytes, megabytes, gigabytes and terabytes."); return; } } else { @@ -648,9 +646,8 @@ QemuOpts *qemu_opts_create(QemuOptsList *list, const char *id, if (!id_wellformed(id)) { error_setg(errp, QERR_INVALID_PARAMETER_VALUE, "id", "an identifier"); -#if 0 /* conversion from qerror_report() to error_set() broke this: */ - error_printf_unless_qmp("Identifiers consist of letters, digits, '-', '.', '_', starting with a letter.\n"); -#endif + error_append_hint(errp, "Identifiers consist of letters, digits, " + "'-', '.', '_', starting with a letter."); return NULL; } opts = qemu_opts_find(list, id); diff --git a/xen-hvm.c b/xen-hvm.c index 5ea621e7b7..3d78a0c529 100644 --- a/xen-hvm.c +++ b/xen-hvm.c @@ -213,7 +213,7 @@ static void xen_ram_init(PCMachineState *pcms, block_len = (1ULL << 32) + pcms->above_4g_mem_size; } memory_region_init_ram(&ram_memory, NULL, "xen.ram", block_len, - &error_abort); + &error_fatal); *ram_memory_p = &ram_memory; vmstate_register_ram_global(&ram_memory); |