diff options
305 files changed, 6461 insertions, 2672 deletions
diff --git a/.shippable.yml b/.shippable.yml index f74a3de3ff..bbc6f88510 100644 --- a/.shippable.yml +++ b/.shippable.yml @@ -27,6 +27,8 @@ env: TARGET_LIST=ppc64-softmmu,ppc64-linux-user,ppc64abi32-linux-user build: pre_ci: + # usually host ARCH is set by configure + - echo "ARCH=$(uname -m)" > config-host.mak - make docker-image-${IMAGE} V=1 pre_ci_boot: image_name: qemu diff --git a/.travis.yml b/.travis.yml index 106f9b5d01..d0b9e099b9 100644 --- a/.travis.yml +++ b/.travis.yml @@ -5,7 +5,18 @@ dist: xenial language: c compiler: - gcc -cache: ccache +cache: + # There is one cache per branch and compiler version. + # characteristics of each job are used to identify the cache: + # - OS name (currently, linux, osx, or windows) + # - OS distribution (for Linux, xenial, trusty, or precise) + # - macOS image name (e.g., xcode7.2) + # - Names and values of visible environment variables set in .travis.yml or Settings panel + timeout: 1200 + ccache: true + pip: true + directories: + - $HOME/avocado/data/cache addons: @@ -15,6 +26,7 @@ addons: - libaio-dev - libattr1-dev - libbrlapi-dev + - libcap-dev - libcap-ng-dev - libgcc-4.8-dev - libgnutls-dev @@ -40,6 +52,7 @@ addons: - gcovr homebrew: packages: + - ccache - glib - pixman - gnu-sed @@ -65,6 +78,9 @@ env: - TEST_CMD="make check -j3 V=1" # This is broadly a list of "mainline" softmmu targets which have support across the major distros - MAIN_SOFTMMU_TARGETS="aarch64-softmmu,arm-softmmu,i386-softmmu,mips-softmmu,mips64-softmmu,ppc64-softmmu,riscv64-softmmu,s390x-softmmu,x86_64-softmmu" + - CCACHE_SLOPPINESS="include_file_ctime,include_file_mtime" + - CCACHE_MAXSIZE=1G + git: # we want to do this ourselves @@ -72,25 +88,32 @@ git: before_script: + - if [ "$TRAVIS_OS_NAME" == "osx" ] ; then export PATH="/usr/local/opt/ccache/libexec:$PATH" ; fi + - command -v ccache && ccache --zero-stats - mkdir -p ${BUILD_DIR} && cd ${BUILD_DIR} - ${SRC_DIR}/configure ${BASE_CONFIG} ${CONFIG} || { cat config.log && exit 1; } script: - make -j3 && travis_retry ${TEST_CMD} +after_script: + - command -v ccache && ccache --show-stats matrix: include: - env: - CONFIG="--disable-system --static" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" # we split the system builds as it takes a while to build them all - env: - CONFIG="--disable-user --target-list=${MAIN_SOFTMMU_TARGETS}" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" - env: - CONFIG="--disable-user --target-list-exclude=${MAIN_SOFTMMU_TARGETS}" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" # Just build tools and run minimal unit and softfloat checks @@ -98,14 +121,18 @@ matrix: - BASE_CONFIG="--enable-tools" - CONFIG="--disable-user --disable-system" - TEST_CMD="make check-unit check-softfloat -j3" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" + - env: - CONFIG="--enable-debug --enable-debug-tcg --disable-user" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-debug" # TCG debug can be run just on it's own and is mostly agnostic to user/softmmu distinctions - env: - CONFIG="--enable-debug-tcg --disable-system" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-debug" - env: @@ -115,6 +142,7 @@ matrix: # Module builds are mostly of interest to major distros - env: - CONFIG="--enable-modules --target-list=${MAIN_SOFTMMU_TARGETS}" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" # Alternate coroutines implementations are only really of interest to KVM users @@ -134,6 +162,7 @@ matrix: - BUILD_DIR="out-of-tree/build/dir" SRC_DIR="../../.." - BASE_CONFIG="--enable-tools --enable-docs" - CONFIG="--target-list=x86_64-softmmu,aarch64-linux-user" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" addons: apt: packages: @@ -145,11 +174,13 @@ matrix: # Test with Clang for compile portability (Travis uses clang-5.0) - env: - CONFIG="--disable-system" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-clang-default" compiler: clang - env: - CONFIG="--disable-user --target-list=${MAIN_SOFTMMU_TARGETS}" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-clang-default" compiler: clang @@ -162,6 +193,7 @@ matrix: - env: - CONFIG="--disable-user --target-list-exclude=${MAIN_SOFTMMU_TARGETS}" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-clang-default" compiler: clang @@ -175,6 +207,7 @@ matrix: # We manually include builds which we disable "make check" for - env: - CONFIG="--without-default-devices --disable-user" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" - TEST_CMD="" @@ -218,6 +251,7 @@ matrix: # Python builds - env: - CONFIG="--target-list=x86_64-softmmu" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" language: python python: - "3.4" @@ -225,6 +259,7 @@ matrix: - env: - CONFIG="--target-list=x86_64-softmmu" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" language: python python: - "3.6" @@ -296,8 +331,11 @@ matrix: - env: - CONFIG="--disable-system" - TEST_CMD="make -j3 check-tcg V=1" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" + # Run check-tcg against softmmu targets - env: - CONFIG="--target-list=xtensa-softmmu,arm-softmmu,aarch64-softmmu,alpha-softmmu" - TEST_CMD="make -j3 check-tcg V=1" + - CACHE_NAME="${TRAVIS_BRANCH}-linux-gcc-default" diff --git a/MAINTAINERS b/MAINTAINERS index 50eaf005f4..1c56d45b16 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -1554,7 +1554,8 @@ F: include/hw/virtio/virtio-input.h F: contrib/vhost-user-input/* virtio-serial -M: Amit Shah <amit@kernel.org> +M: Laurent Vivier <lvivier@redhat.com> +R: Amit Shah <amit@kernel.org> S: Supported F: hw/char/virtio-serial-bus.c F: hw/char/virtio-console.c @@ -1563,7 +1564,8 @@ F: tests/virtio-console-test.c F: tests/virtio-serial-test.c virtio-rng -M: Amit Shah <amit@kernel.org> +M: Laurent Vivier <lvivier@redhat.com> +R: Amit Shah <amit@kernel.org> S: Supported F: hw/virtio/virtio-rng.c F: include/hw/virtio/virtio-rng.h @@ -2040,7 +2042,7 @@ QEMU Guest Agent M: Michael Roth <mdroth@linux.vnet.ibm.com> S: Maintained F: qga/ -F: qemu-ga.texi +F: docs/interop/qemu-ga.rst F: scripts/qemu-guest-agent/ F: tests/test-qga.c F: docs/interop/qemu-ga-ref.texi diff --git a/Makefile b/Makefile index ae17a83067..111082ce54 100644 --- a/Makefile +++ b/Makefile @@ -325,7 +325,7 @@ endif endif ifdef BUILD_DOCS -DOCS=qemu-doc.html qemu-doc.txt qemu.1 qemu-img.1 qemu-nbd.8 qemu-ga.8 +DOCS=qemu-doc.html qemu-doc.txt qemu.1 qemu-img.1 qemu-nbd.8 docs/interop/qemu-ga.8 DOCS+=docs/interop/qemu-qmp-ref.html docs/interop/qemu-qmp-ref.txt docs/interop/qemu-qmp-ref.7 DOCS+=docs/interop/qemu-ga-ref.html docs/interop/qemu-ga-ref.txt docs/interop/qemu-ga-ref.7 DOCS+=docs/qemu-block-drivers.7 @@ -717,6 +717,7 @@ endef distclean: clean rm -f config-host.mak config-host.h* config-host.ld $(DOCS) qemu-options.texi qemu-img-cmds.texi qemu-monitor.texi qemu-monitor-info.texi + rm -f tests/tcg/config-*.mak rm -f config-all-devices.mak config-all-disas.mak config.status rm -f $(SUBDIR_DEVICES_MAK) rm -f po/*.mo tests/qemu-iotests/common.env @@ -782,10 +783,11 @@ DESCS= endif # Note that we manually filter-out the non-Sphinx documentation which -# is currently built into the docs/interop directory in the build tree. +# is currently built into the docs/interop directory in the build tree, +# and also any sphinx-built manpages. define install-manual = for d in $$(cd $(MANUAL_BUILDDIR) && find $1 -type d); do $(INSTALL_DIR) "$(DESTDIR)$(qemu_docdir)/$$d"; done -for f in $$(cd $(MANUAL_BUILDDIR) && find $1 -type f -a '!' '(' -name 'qemu-*-qapi.*' -o -name 'qemu-*-ref.*' ')' ); do $(INSTALL_DATA) "$(MANUAL_BUILDDIR)/$$f" "$(DESTDIR)$(qemu_docdir)/$$f"; done +for f in $$(cd $(MANUAL_BUILDDIR) && find $1 -type f -a '!' '(' -name '*.[0-9]' -o -name 'qemu-*-qapi.*' -o -name 'qemu-*-ref.*' ')' ); do $(INSTALL_DATA) "$(MANUAL_BUILDDIR)/$$f" "$(DESTDIR)$(qemu_docdir)/$$f"; done endef # Note that we deliberately do not install the "devel" manual: it is @@ -817,7 +819,7 @@ ifdef CONFIG_TRACE_SYSTEMTAP $(INSTALL_DATA) scripts/qemu-trace-stap.1 "$(DESTDIR)$(mandir)/man1" endif ifneq (,$(findstring qemu-ga,$(TOOLS))) - $(INSTALL_DATA) qemu-ga.8 "$(DESTDIR)$(mandir)/man8" + $(INSTALL_DATA) docs/interop/qemu-ga.8 "$(DESTDIR)$(mandir)/man8" $(INSTALL_DATA) docs/interop/qemu-ga-ref.html "$(DESTDIR)$(qemu_docdir)" $(INSTALL_DATA) docs/interop/qemu-ga-ref.txt "$(DESTDIR)$(qemu_docdir)" $(INSTALL_DATA) docs/interop/qemu-ga-ref.7 "$(DESTDIR)$(mandir)/man7" @@ -976,18 +978,22 @@ docs/version.texi: $(SRC_PATH)/VERSION config-host.mak sphinxdocs: $(MANUAL_BUILDDIR)/devel/index.html $(MANUAL_BUILDDIR)/interop/index.html $(MANUAL_BUILDDIR)/specs/index.html # Canned command to build a single manual -build-manual = $(call quiet-command,sphinx-build $(if $(V),,-q) -W -n -b html -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1") +# Arguments: $1 = manual name, $2 = Sphinx builder ('html' or 'man') +build-manual = $(call quiet-command,CONFDIR="$(qemu_confdir)" sphinx-build $(if $(V),,-q) -W -n -b $2 -D version=$(VERSION) -D release="$(FULL_VERSION)" -d .doctrees/$1 $(SRC_PATH)/docs/$1 $(MANUAL_BUILDDIR)/$1 ,"SPHINX","$(MANUAL_BUILDDIR)/$1") # We assume all RST files in the manual's directory are used in it manual-deps = $(wildcard $(SRC_PATH)/docs/$1/*.rst) $(SRC_PATH)/docs/$1/conf.py $(SRC_PATH)/docs/conf.py $(MANUAL_BUILDDIR)/devel/index.html: $(call manual-deps,devel) - $(call build-manual,devel) + $(call build-manual,devel,html) $(MANUAL_BUILDDIR)/interop/index.html: $(call manual-deps,interop) - $(call build-manual,interop) + $(call build-manual,interop,html) $(MANUAL_BUILDDIR)/specs/index.html: $(call manual-deps,specs) - $(call build-manual,specs) + $(call build-manual,specs,html) + +$(MANUAL_BUILDDIR)/interop/qemu-ga.8: $(call manual-deps,interop) + $(call build-manual,interop,man) qemu-options.texi: $(SRC_PATH)/qemu-options.hx $(SRC_PATH)/scripts/hxtool $(call quiet-command,sh $(SRC_PATH)/scripts/hxtool -t < $< > $@,"GEN","$@") @@ -1012,7 +1018,6 @@ qemu.1: qemu-option-trace.texi qemu-img.1: qemu-img.texi qemu-option-trace.texi qemu-img-cmds.texi fsdev/virtfs-proxy-helper.1: fsdev/virtfs-proxy-helper.texi qemu-nbd.8: qemu-nbd.texi qemu-option-trace.texi -qemu-ga.8: qemu-ga.texi docs/qemu-block-drivers.7: docs/qemu-block-drivers.texi docs/qemu-cpu-models.7: docs/qemu-cpu-models.texi scripts/qemu-trace-stap.1: scripts/qemu-trace-stap.texi @@ -1025,7 +1030,7 @@ txt: qemu-doc.txt docs/interop/qemu-qmp-ref.txt docs/interop/qemu-ga-ref.txt qemu-doc.html qemu-doc.info qemu-doc.pdf qemu-doc.txt: \ qemu-img.texi qemu-nbd.texi qemu-options.texi \ qemu-tech.texi qemu-option-trace.texi \ - qemu-deprecated.texi qemu-monitor.texi qemu-img-cmds.texi qemu-ga.texi \ + qemu-deprecated.texi qemu-monitor.texi qemu-img-cmds.texi \ qemu-monitor-info.texi docs/qemu-block-drivers.texi \ docs/qemu-cpu-models.texi docs/security.texi diff --git a/Makefile.objs b/Makefile.objs index 6a143dcd57..abcbd89654 100644 --- a/Makefile.objs +++ b/Makefile.objs @@ -203,6 +203,7 @@ trace-events-subdirs += target/riscv trace-events-subdirs += target/s390x trace-events-subdirs += target/sparc trace-events-subdirs += util +trace-events-subdirs += hw/core trace-events-files = $(SRC_PATH)/trace-events $(trace-events-subdirs:%=$(SRC_PATH)/%/trace-events) diff --git a/Makefile.target b/Makefile.target index 933b27453a..5e916230c4 100644 --- a/Makefile.target +++ b/Makefile.target @@ -39,9 +39,6 @@ endif PROGS=$(QEMU_PROG) $(QEMU_PROGW) STPFILES= -# Makefile Tests -include $(SRC_PATH)/tests/tcg/Makefile.include - config-target.h: config-target.h-timestamp config-target.h-timestamp: config-target.mak diff --git a/accel/tcg/atomic_template.h b/accel/tcg/atomic_template.h index df9c838817..287433d809 100644 --- a/accel/tcg/atomic_template.h +++ b/accel/tcg/atomic_template.h @@ -149,7 +149,7 @@ ABI_TYPE ATOMIC_NAME(xchg)(CPUArchState *env, target_ulong addr, #define GEN_ATOMIC_HELPER(X) \ ABI_TYPE ATOMIC_NAME(X)(CPUArchState *env, target_ulong addr, \ - ABI_TYPE val EXTRA_ARGS) \ + ABI_TYPE val EXTRA_ARGS) \ { \ ATOMIC_MMU_DECLS; \ DATA_TYPE *haddr = ATOMIC_MMU_LOOKUP; \ diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c index ecc15e3eb0..be64020746 100644 --- a/backends/hostmem-file.c +++ b/backends/hostmem-file.c @@ -58,28 +58,6 @@ file_backend_memory_alloc(HostMemoryBackend *backend, Error **errp) return; } - /* - * Verify pmem file size since starting a guest with an incorrect size - * leads to confusing failures inside the guest. - */ - if (fb->is_pmem) { - Error *local_err = NULL; - uint64_t size; - - size = qemu_get_pmem_size(fb->mem_path, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - if (size && backend->size > size) { - error_setg(errp, "size property %" PRIu64 " is larger than " - "pmem file \"%s\" size %" PRIu64, backend->size, - fb->mem_path, size); - return; - } - } - backend->force_prealloc = mem_prealloc; name = host_memory_backend_get_name(backend); memory_region_init_ram_from_file(&backend->mr, OBJECT(backend), diff --git a/backends/vhost-user.c b/backends/vhost-user.c index 0a13506c98..2bf3406525 100644 --- a/backends/vhost-user.c +++ b/backends/vhost-user.c @@ -46,7 +46,7 @@ vhost_user_backend_dev_init(VhostUserBackend *b, VirtIODevice *vdev, b->vdev = vdev; b->dev.nvqs = nvqs; - b->dev.vqs = g_new(struct vhost_virtqueue, nvqs); + b->dev.vqs = g_new0(struct vhost_virtqueue, nvqs); ret = vhost_dev_init(&b->dev, &b->vhost_user, VHOST_BACKEND_TYPE_USER, 0); if (ret < 0) { diff --git a/block/backup.c b/block/backup.c index 03637aeb11..763f0d7ff6 100644 --- a/block/backup.c +++ b/block/backup.c @@ -425,21 +425,6 @@ void backup_do_checkpoint(BlockJob *job, Error **errp) bdrv_set_dirty_bitmap(backup_job->copy_bitmap, 0, backup_job->len); } -static void backup_drain(BlockJob *job) -{ - BackupBlockJob *s = container_of(job, BackupBlockJob, common); - - /* Need to keep a reference in case blk_drain triggers execution - * of backup_complete... - */ - if (s->target) { - BlockBackend *target = s->target; - blk_ref(target); - blk_drain(target); - blk_unref(target); - } -} - static BlockErrorAction backup_error_action(BackupBlockJob *job, bool read, int error) { @@ -588,13 +573,11 @@ static const BlockJobDriver backup_job_driver = { .job_type = JOB_TYPE_BACKUP, .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = backup_run, .commit = backup_commit, .abort = backup_abort, .clean = backup_clean, - }, - .drain = backup_drain, + } }; static int64_t backup_calculate_cluster_size(BlockDriverState *target, diff --git a/block/bochs.c b/block/bochs.c index 962f18592d..32bb83b268 100644 --- a/block/bochs.c +++ b/block/bochs.c @@ -248,8 +248,8 @@ bochs_co_preadv(BlockDriverState *bs, uint64_t offset, uint64_t bytes, QEMUIOVector local_qiov; int ret; - assert((offset & (BDRV_SECTOR_SIZE - 1)) == 0); - assert((bytes & (BDRV_SECTOR_SIZE - 1)) == 0); + assert(QEMU_IS_ALIGNED(offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(bytes, BDRV_SECTOR_SIZE)); qemu_iovec_init(&local_qiov, qiov->niov); qemu_co_mutex_lock(&s->lock); diff --git a/block/cloop.c b/block/cloop.c index 384c9735bb..4de94876d4 100644 --- a/block/cloop.c +++ b/block/cloop.c @@ -253,8 +253,8 @@ cloop_co_preadv(BlockDriverState *bs, uint64_t offset, uint64_t bytes, int nb_sectors = bytes >> BDRV_SECTOR_BITS; int ret, i; - assert((offset & (BDRV_SECTOR_SIZE - 1)) == 0); - assert((bytes & (BDRV_SECTOR_SIZE - 1)) == 0); + assert(QEMU_IS_ALIGNED(offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(bytes, BDRV_SECTOR_SIZE)); qemu_co_mutex_lock(&s->lock); diff --git a/block/commit.c b/block/commit.c index 408ae15389..bc8454463d 100644 --- a/block/commit.c +++ b/block/commit.c @@ -216,7 +216,6 @@ static const BlockJobDriver commit_job_driver = { .job_type = JOB_TYPE_COMMIT, .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = commit_run, .prepare = commit_prepare, .abort = commit_abort, diff --git a/block/create.c b/block/create.c index 1bd00ed5f8..89812669df 100644 --- a/block/create.c +++ b/block/create.c @@ -64,9 +64,13 @@ void qmp_blockdev_create(const char *job_id, BlockdevCreateOptions *options, const char *fmt = BlockdevDriver_str(options->driver); BlockDriver *drv = bdrv_find_format(fmt); + if (!drv) { + error_setg(errp, "Block driver '%s' not found or not supported", fmt); + return; + } + /* If the driver is in the schema, we know that it exists. But it may not * be whitelisted. */ - assert(drv); if (bdrv_uses_whitelist() && !bdrv_is_whitelisted(drv, false)) { error_setg(errp, "Driver is not whitelisted"); return; diff --git a/block/curl.c b/block/curl.c index d4c8e94f3e..f86299378e 100644 --- a/block/curl.c +++ b/block/curl.c @@ -80,6 +80,7 @@ static CURLMcode __curl_multi_socket_action(CURLM *multi_handle, #define CURL_BLOCK_OPT_TIMEOUT_DEFAULT 5 struct BDRVCURLState; +struct CURLState; static bool libcurl_initialized; @@ -97,6 +98,7 @@ typedef struct CURLAIOCB { typedef struct CURLSocket { int fd; + struct CURLState *state; QLIST_ENTRY(CURLSocket) next; } CURLSocket; @@ -137,7 +139,6 @@ typedef struct BDRVCURLState { static void curl_clean_state(CURLState *s); static void curl_multi_do(void *arg); -static void curl_multi_read(void *arg); #ifdef NEED_CURL_TIMER_CALLBACK /* Called from curl_multi_do_locked, with s->mutex held. */ @@ -170,33 +171,29 @@ static int curl_sock_cb(CURL *curl, curl_socket_t fd, int action, QLIST_FOREACH(socket, &state->sockets, next) { if (socket->fd == fd) { - if (action == CURL_POLL_REMOVE) { - QLIST_REMOVE(socket, next); - g_free(socket); - } break; } } if (!socket) { socket = g_new0(CURLSocket, 1); socket->fd = fd; + socket->state = state; QLIST_INSERT_HEAD(&state->sockets, socket, next); } - socket = NULL; trace_curl_sock_cb(action, (int)fd); switch (action) { case CURL_POLL_IN: aio_set_fd_handler(s->aio_context, fd, false, - curl_multi_read, NULL, NULL, state); + curl_multi_do, NULL, NULL, socket); break; case CURL_POLL_OUT: aio_set_fd_handler(s->aio_context, fd, false, - NULL, curl_multi_do, NULL, state); + NULL, curl_multi_do, NULL, socket); break; case CURL_POLL_INOUT: aio_set_fd_handler(s->aio_context, fd, false, - curl_multi_read, curl_multi_do, NULL, state); + curl_multi_do, curl_multi_do, NULL, socket); break; case CURL_POLL_REMOVE: aio_set_fd_handler(s->aio_context, fd, false, @@ -204,6 +201,11 @@ static int curl_sock_cb(CURL *curl, curl_socket_t fd, int action, break; } + if (action == CURL_POLL_REMOVE) { + QLIST_REMOVE(socket, next); + g_free(socket); + } + return 0; } @@ -227,7 +229,6 @@ static size_t curl_read_cb(void *ptr, size_t size, size_t nmemb, void *opaque) { CURLState *s = ((CURLState*)opaque); size_t realsize = size * nmemb; - int i; trace_curl_read_cb(realsize); @@ -243,32 +244,6 @@ static size_t curl_read_cb(void *ptr, size_t size, size_t nmemb, void *opaque) memcpy(s->orig_buf + s->buf_off, ptr, realsize); s->buf_off += realsize; - for(i=0; i<CURL_NUM_ACB; i++) { - CURLAIOCB *acb = s->acb[i]; - - if (!acb) - continue; - - if ((s->buf_off >= acb->end)) { - size_t request_length = acb->bytes; - - qemu_iovec_from_buf(acb->qiov, 0, s->orig_buf + acb->start, - acb->end - acb->start); - - if (acb->end - acb->start < request_length) { - size_t offset = acb->end - acb->start; - qemu_iovec_memset(acb->qiov, offset, 0, - request_length - offset); - } - - acb->ret = 0; - s->acb[i] = NULL; - qemu_mutex_unlock(&s->s->mutex); - aio_co_wake(acb->co); - qemu_mutex_lock(&s->s->mutex); - } - } - read_end: /* curl will error out if we do not return this value */ return size * nmemb; @@ -349,13 +324,14 @@ static void curl_multi_check_completion(BDRVCURLState *s) break; if (msg->msg == CURLMSG_DONE) { + int i; CURLState *state = NULL; + bool error = msg->data.result != CURLE_OK; + curl_easy_getinfo(msg->easy_handle, CURLINFO_PRIVATE, (char **)&state); - /* ACBs for successful messages get completed in curl_read_cb */ - if (msg->data.result != CURLE_OK) { - int i; + if (error) { static int errcount = 100; /* Don't lose the original error message from curl, since @@ -367,20 +343,35 @@ static void curl_multi_check_completion(BDRVCURLState *s) error_report("curl: further errors suppressed"); } } + } - for (i = 0; i < CURL_NUM_ACB; i++) { - CURLAIOCB *acb = state->acb[i]; + for (i = 0; i < CURL_NUM_ACB; i++) { + CURLAIOCB *acb = state->acb[i]; - if (acb == NULL) { - continue; - } + if (acb == NULL) { + continue; + } + + if (!error) { + /* Assert that we have read all data */ + assert(state->buf_off >= acb->end); + + qemu_iovec_from_buf(acb->qiov, 0, + state->orig_buf + acb->start, + acb->end - acb->start); - acb->ret = -EIO; - state->acb[i] = NULL; - qemu_mutex_unlock(&s->mutex); - aio_co_wake(acb->co); - qemu_mutex_lock(&s->mutex); + if (acb->end - acb->start < acb->bytes) { + size_t offset = acb->end - acb->start; + qemu_iovec_memset(acb->qiov, offset, 0, + acb->bytes - offset); + } } + + acb->ret = error ? -EIO : 0; + state->acb[i] = NULL; + qemu_mutex_unlock(&s->mutex); + aio_co_wake(acb->co); + qemu_mutex_lock(&s->mutex); } curl_clean_state(state); @@ -390,42 +381,30 @@ static void curl_multi_check_completion(BDRVCURLState *s) } /* Called with s->mutex held. */ -static void curl_multi_do_locked(CURLState *s) +static void curl_multi_do_locked(CURLSocket *socket) { - CURLSocket *socket, *next_socket; + BDRVCURLState *s = socket->state->s; int running; int r; - if (!s->s->multi) { + if (!s->multi) { return; } - /* Need to use _SAFE because curl_multi_socket_action() may trigger - * curl_sock_cb() which might modify this list */ - QLIST_FOREACH_SAFE(socket, &s->sockets, next, next_socket) { - do { - r = curl_multi_socket_action(s->s->multi, socket->fd, 0, &running); - } while (r == CURLM_CALL_MULTI_PERFORM); - } + do { + r = curl_multi_socket_action(s->multi, socket->fd, 0, &running); + } while (r == CURLM_CALL_MULTI_PERFORM); } static void curl_multi_do(void *arg) { - CURLState *s = (CURLState *)arg; + CURLSocket *socket = arg; + BDRVCURLState *s = socket->state->s; - qemu_mutex_lock(&s->s->mutex); - curl_multi_do_locked(s); - qemu_mutex_unlock(&s->s->mutex); -} - -static void curl_multi_read(void *arg) -{ - CURLState *s = (CURLState *)arg; - - qemu_mutex_lock(&s->s->mutex); - curl_multi_do_locked(s); - curl_multi_check_completion(s->s); - qemu_mutex_unlock(&s->s->mutex); + qemu_mutex_lock(&s->mutex); + curl_multi_do_locked(socket); + curl_multi_check_completion(s); + qemu_mutex_unlock(&s->mutex); } static void curl_multi_timeout_do(void *arg) @@ -903,7 +882,13 @@ static void curl_setup_preadv(BlockDriverState *bs, CURLAIOCB *acb) trace_curl_setup_preadv(acb->bytes, start, state->range); curl_easy_setopt(state->curl, CURLOPT_RANGE, state->range); - curl_multi_add_handle(s->multi, state->curl); + if (curl_multi_add_handle(s->multi, state->curl) != CURLM_OK) { + state->acb[0] = NULL; + acb->ret = -EIO; + + curl_clean_state(state); + goto out; + } /* Tell curl it needs to kick things off */ curl_multi_socket_action(s->multi, CURL_SOCKET_TIMEOUT, 0, &running); diff --git a/block/dmg.c b/block/dmg.c index 45f6b28f17..4a045f2b3e 100644 --- a/block/dmg.c +++ b/block/dmg.c @@ -697,8 +697,8 @@ dmg_co_preadv(BlockDriverState *bs, uint64_t offset, uint64_t bytes, int nb_sectors = bytes >> BDRV_SECTOR_BITS; int ret, i; - assert((offset & (BDRV_SECTOR_SIZE - 1)) == 0); - assert((bytes & (BDRV_SECTOR_SIZE - 1)) == 0); + assert(QEMU_IS_ALIGNED(offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(bytes, BDRV_SECTOR_SIZE)); qemu_co_mutex_lock(&s->lock); diff --git a/block/file-posix.c b/block/file-posix.c index 87c5a4ccbd..f12c06de2d 100644 --- a/block/file-posix.c +++ b/block/file-posix.c @@ -1459,59 +1459,6 @@ out: } } -#ifdef CONFIG_XFS -static int xfs_write_zeroes(BDRVRawState *s, int64_t offset, uint64_t bytes) -{ - int64_t len; - struct xfs_flock64 fl; - int err; - - len = lseek(s->fd, 0, SEEK_END); - if (len < 0) { - return -errno; - } - - if (offset + bytes > len) { - /* XFS_IOC_ZERO_RANGE does not increase the file length */ - if (ftruncate(s->fd, offset + bytes) < 0) { - return -errno; - } - } - - memset(&fl, 0, sizeof(fl)); - fl.l_whence = SEEK_SET; - fl.l_start = offset; - fl.l_len = bytes; - - if (xfsctl(NULL, s->fd, XFS_IOC_ZERO_RANGE, &fl) < 0) { - err = errno; - trace_file_xfs_write_zeroes(strerror(errno)); - return -err; - } - - return 0; -} - -static int xfs_discard(BDRVRawState *s, int64_t offset, uint64_t bytes) -{ - struct xfs_flock64 fl; - int err; - - memset(&fl, 0, sizeof(fl)); - fl.l_whence = SEEK_SET; - fl.l_start = offset; - fl.l_len = bytes; - - if (xfsctl(NULL, s->fd, XFS_IOC_UNRESVSP64, &fl) < 0) { - err = errno; - trace_file_xfs_discard(strerror(errno)); - return -err; - } - - return 0; -} -#endif - static int translate_err(int err) { if (err == -ENODEV || err == -ENOSYS || err == -EOPNOTSUPP || @@ -1555,22 +1502,20 @@ static ssize_t handle_aiocb_write_zeroes_block(RawPosixAIOData *aiocb) } while (errno == EINTR); ret = translate_err(-errno); + if (ret == -ENOTSUP) { + s->has_write_zeroes = false; + } } #endif - if (ret == -ENOTSUP) { - s->has_write_zeroes = false; - } return ret; } static int handle_aiocb_write_zeroes(void *opaque) { RawPosixAIOData *aiocb = opaque; -#if defined(CONFIG_FALLOCATE) || defined(CONFIG_XFS) - BDRVRawState *s = aiocb->bs->opaque; -#endif #ifdef CONFIG_FALLOCATE + BDRVRawState *s = aiocb->bs->opaque; int64_t len; #endif @@ -1578,12 +1523,6 @@ static int handle_aiocb_write_zeroes(void *opaque) return handle_aiocb_write_zeroes_block(aiocb); } -#ifdef CONFIG_XFS - if (s->is_xfs) { - return xfs_write_zeroes(s, aiocb->aio_offset, aiocb->aio_nbytes); - } -#endif - #ifdef CONFIG_FALLOCATE_ZERO_RANGE if (s->has_write_zeroes) { int ret = do_fallocate(s->fd, FALLOC_FL_ZERO_RANGE, @@ -1653,14 +1592,6 @@ static int handle_aiocb_write_zeroes_unmap(void *opaque) } #endif -#ifdef CONFIG_XFS - if (s->is_xfs) { - /* xfs_discard() guarantees that the discarded area reads as all-zero - * afterwards, so we can use it here. */ - return xfs_discard(s, aiocb->aio_offset, aiocb->aio_nbytes); - } -#endif - /* If we couldn't manage to unmap while guaranteed that the area reads as * all-zero afterwards, just write zeroes without unmapping */ ret = handle_aiocb_write_zeroes(aiocb); @@ -1737,12 +1668,6 @@ static int handle_aiocb_discard(void *opaque) ret = -errno; #endif } else { -#ifdef CONFIG_XFS - if (s->is_xfs) { - return xfs_discard(s, aiocb->aio_offset, aiocb->aio_nbytes); - } -#endif - #ifdef CONFIG_FALLOCATE_PUNCH_HOLE ret = do_fallocate(s->fd, FALLOC_FL_PUNCH_HOLE | FALLOC_FL_KEEP_SIZE, aiocb->aio_offset, aiocb->aio_nbytes); diff --git a/block/io.c b/block/io.c index 16a598fd08..f8c3596131 100644 --- a/block/io.c +++ b/block/io.c @@ -1097,8 +1097,8 @@ static int coroutine_fn bdrv_driver_preadv(BlockDriverState *bs, sector_num = offset >> BDRV_SECTOR_BITS; nb_sectors = bytes >> BDRV_SECTOR_BITS; - assert((offset & (BDRV_SECTOR_SIZE - 1)) == 0); - assert((bytes & (BDRV_SECTOR_SIZE - 1)) == 0); + assert(QEMU_IS_ALIGNED(offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(bytes, BDRV_SECTOR_SIZE)); assert(bytes <= BDRV_REQUEST_MAX_BYTES); assert(drv->bdrv_co_readv); @@ -1171,8 +1171,8 @@ static int coroutine_fn bdrv_driver_pwritev(BlockDriverState *bs, sector_num = offset >> BDRV_SECTOR_BITS; nb_sectors = bytes >> BDRV_SECTOR_BITS; - assert((offset & (BDRV_SECTOR_SIZE - 1)) == 0); - assert((bytes & (BDRV_SECTOR_SIZE - 1)) == 0); + assert(QEMU_IS_ALIGNED(offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(bytes, BDRV_SECTOR_SIZE)); assert(bytes <= BDRV_REQUEST_MAX_BYTES); assert(drv->bdrv_co_writev); diff --git a/block/mirror.c b/block/mirror.c index 853e2c7510..fe984efb90 100644 --- a/block/mirror.c +++ b/block/mirror.c @@ -646,14 +646,11 @@ static int mirror_exit_common(Job *job) bdrv_ref(mirror_top_bs); bdrv_ref(target_bs); - /* Remove target parent that still uses BLK_PERM_WRITE/RESIZE before + /* + * Remove target parent that still uses BLK_PERM_WRITE/RESIZE before * inserting target_bs at s->to_replace, where we might not be able to get * these permissions. - * - * Note that blk_unref() alone doesn't necessarily drop permissions because - * we might be running nested inside mirror_drain(), which takes an extra - * reference, so use an explicit blk_set_perm() first. */ - blk_set_perm(s->target, 0, BLK_PERM_ALL, &error_abort); + */ blk_unref(s->target); s->target = NULL; @@ -1149,28 +1146,12 @@ static bool mirror_drained_poll(BlockJob *job) return !!s->in_flight; } -static void mirror_drain(BlockJob *job) -{ - MirrorBlockJob *s = container_of(job, MirrorBlockJob, common); - - /* Need to keep a reference in case blk_drain triggers execution - * of mirror_complete... - */ - if (s->target) { - BlockBackend *target = s->target; - blk_ref(target); - blk_drain(target); - blk_unref(target); - } -} - static const BlockJobDriver mirror_job_driver = { .job_driver = { .instance_size = sizeof(MirrorBlockJob), .job_type = JOB_TYPE_MIRROR, .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = mirror_run, .prepare = mirror_prepare, .abort = mirror_abort, @@ -1178,7 +1159,6 @@ static const BlockJobDriver mirror_job_driver = { .complete = mirror_complete, }, .drained_poll = mirror_drained_poll, - .drain = mirror_drain, }; static const BlockJobDriver commit_active_job_driver = { @@ -1187,7 +1167,6 @@ static const BlockJobDriver commit_active_job_driver = { .job_type = JOB_TYPE_COMMIT, .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = mirror_run, .prepare = mirror_prepare, .abort = mirror_abort, @@ -1195,7 +1174,6 @@ static const BlockJobDriver commit_active_job_driver = { .complete = mirror_complete, }, .drained_poll = mirror_drained_poll, - .drain = mirror_drain, }; static void coroutine_fn diff --git a/block/nfs.c b/block/nfs.c index 0ec50953e4..f39acfdb28 100644 --- a/block/nfs.c +++ b/block/nfs.c @@ -390,12 +390,17 @@ static void nfs_attach_aio_context(BlockDriverState *bs, static void nfs_client_close(NFSClient *client) { if (client->context) { + qemu_mutex_lock(&client->mutex); + aio_set_fd_handler(client->aio_context, nfs_get_fd(client->context), + false, NULL, NULL, NULL, NULL); + qemu_mutex_unlock(&client->mutex); if (client->fh) { nfs_close(client->context, client->fh); client->fh = NULL; } - aio_set_fd_handler(client->aio_context, nfs_get_fd(client->context), - false, NULL, NULL, NULL, NULL); +#ifdef LIBNFS_FEATURE_UMOUNT + nfs_umount(client->context); +#endif nfs_destroy_context(client->context); client->context = NULL; } diff --git a/block/qcow2-cluster.c b/block/qcow2-cluster.c index f09cc992af..8d5fa1539c 100644 --- a/block/qcow2-cluster.c +++ b/block/qcow2-cluster.c @@ -462,27 +462,6 @@ static int coroutine_fn do_perform_cow_read(BlockDriverState *bs, return 0; } -static bool coroutine_fn do_perform_cow_encrypt(BlockDriverState *bs, - uint64_t src_cluster_offset, - uint64_t cluster_offset, - unsigned offset_in_cluster, - uint8_t *buffer, - unsigned bytes) -{ - if (bytes && bs->encrypted) { - BDRVQcow2State *s = bs->opaque; - assert((offset_in_cluster & ~BDRV_SECTOR_MASK) == 0); - assert((bytes & ~BDRV_SECTOR_MASK) == 0); - assert(s->crypto); - if (qcow2_co_encrypt(bs, cluster_offset, - src_cluster_offset + offset_in_cluster, - buffer, bytes) < 0) { - return false; - } - } - return true; -} - static int coroutine_fn do_perform_cow_write(BlockDriverState *bs, uint64_t cluster_offset, unsigned offset_in_cluster, @@ -890,12 +869,19 @@ static int perform_cow(BlockDriverState *bs, QCowL2Meta *m) /* Encrypt the data if necessary before writing it */ if (bs->encrypted) { - if (!do_perform_cow_encrypt(bs, m->offset, m->alloc_offset, - start->offset, start_buffer, - start->nb_bytes) || - !do_perform_cow_encrypt(bs, m->offset, m->alloc_offset, - end->offset, end_buffer, end->nb_bytes)) { - ret = -EIO; + ret = qcow2_co_encrypt(bs, + m->alloc_offset + start->offset, + m->offset + start->offset, + start_buffer, start->nb_bytes); + if (ret < 0) { + goto fail; + } + + ret = qcow2_co_encrypt(bs, + m->alloc_offset + end->offset, + m->offset + end->offset, + end_buffer, end->nb_bytes); + if (ret < 0) { goto fail; } } @@ -1351,13 +1337,7 @@ static int handle_alloc(BlockDriverState *bs, uint64_t guest_offset, } entry = be64_to_cpu(l2_slice[l2_index]); - - /* For the moment, overwrite compressed clusters one by one */ - if (entry & QCOW_OFLAG_COMPRESSED) { - nb_clusters = 1; - } else { - nb_clusters = count_cow_clusters(bs, nb_clusters, l2_slice, l2_index); - } + nb_clusters = count_cow_clusters(bs, nb_clusters, l2_slice, l2_index); /* This function is only called when there were no non-COW clusters, so if * we can't find any unallocated or COW clusters either, something is diff --git a/block/qcow2-threads.c b/block/qcow2-threads.c index 3b1e63fe41..8f5a0d1ebe 100644 --- a/block/qcow2-threads.c +++ b/block/qcow2-threads.c @@ -234,35 +234,70 @@ static int qcow2_encdec_pool_func(void *opaque) } static int coroutine_fn -qcow2_co_encdec(BlockDriverState *bs, uint64_t file_cluster_offset, - uint64_t offset, void *buf, size_t len, Qcow2EncDecFunc func) +qcow2_co_encdec(BlockDriverState *bs, uint64_t host_offset, + uint64_t guest_offset, void *buf, size_t len, + Qcow2EncDecFunc func) { BDRVQcow2State *s = bs->opaque; Qcow2EncDecData arg = { .block = s->crypto, - .offset = s->crypt_physical_offset ? - file_cluster_offset + offset_into_cluster(s, offset) : - offset, + .offset = s->crypt_physical_offset ? host_offset : guest_offset, .buf = buf, .len = len, .func = func, }; - return qcow2_co_process(bs, qcow2_encdec_pool_func, &arg); + assert(QEMU_IS_ALIGNED(guest_offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(host_offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(len, BDRV_SECTOR_SIZE)); + assert(s->crypto); + + return len == 0 ? 0 : qcow2_co_process(bs, qcow2_encdec_pool_func, &arg); } +/* + * qcow2_co_encrypt() + * + * Encrypts one or more contiguous aligned sectors + * + * @host_offset - underlying storage offset of the first sector of the + * data to be encrypted + * + * @guest_offset - guest (virtual) offset of the first sector of the + * data to be encrypted + * + * @buf - buffer with the data to encrypt, that after encryption + * will be written to the underlying storage device at + * @host_offset + * + * @len - length of the buffer (must be a BDRV_SECTOR_SIZE multiple) + * + * Depending on the encryption method, @host_offset and/or @guest_offset + * may be used for generating the initialization vector for + * encryption. + * + * Note that while the whole range must be aligned on sectors, it + * does not have to be aligned on clusters and can also cross cluster + * boundaries + */ int coroutine_fn -qcow2_co_encrypt(BlockDriverState *bs, uint64_t file_cluster_offset, - uint64_t offset, void *buf, size_t len) +qcow2_co_encrypt(BlockDriverState *bs, uint64_t host_offset, + uint64_t guest_offset, void *buf, size_t len) { - return qcow2_co_encdec(bs, file_cluster_offset, offset, buf, len, - qcrypto_block_encrypt); + return qcow2_co_encdec(bs, host_offset, guest_offset, buf, len, + qcrypto_block_encrypt); } +/* + * qcow2_co_decrypt() + * + * Decrypts one or more contiguous aligned sectors + * Similar to qcow2_co_encrypt + */ int coroutine_fn -qcow2_co_decrypt(BlockDriverState *bs, uint64_t file_cluster_offset, - uint64_t offset, void *buf, size_t len) +qcow2_co_decrypt(BlockDriverState *bs, uint64_t host_offset, + uint64_t guest_offset, void *buf, size_t len) { - return qcow2_co_encdec(bs, file_cluster_offset, offset, buf, len, - qcrypto_block_decrypt); + return qcow2_co_encdec(bs, host_offset, guest_offset, buf, len, + qcrypto_block_decrypt); } diff --git a/block/qcow2.c b/block/qcow2.c index 0882ff6e92..4d16393e61 100644 --- a/block/qcow2.c +++ b/block/qcow2.c @@ -828,7 +828,11 @@ static void read_cache_sizes(BlockDriverState *bs, QemuOpts *opts, bool l2_cache_entry_size_set; int min_refcount_cache = MIN_REFCOUNT_CACHE_SIZE * s->cluster_size; uint64_t virtual_disk_size = bs->total_sectors * BDRV_SECTOR_SIZE; - uint64_t max_l2_cache = virtual_disk_size / (s->cluster_size / 8); + uint64_t max_l2_entries = DIV_ROUND_UP(virtual_disk_size, s->cluster_size); + /* An L2 table is always one cluster in size so the max cache size + * should be a multiple of the cluster size. */ + uint64_t max_l2_cache = ROUND_UP(max_l2_entries * sizeof(uint64_t), + s->cluster_size); combined_cache_size_set = qemu_opt_get(opts, QCOW2_OPT_CACHE_SIZE); l2_cache_size_set = qemu_opt_get(opts, QCOW2_OPT_L2_CACHE_SIZE); @@ -2063,9 +2067,10 @@ static coroutine_fn int qcow2_co_preadv_part(BlockDriverState *bs, goto fail; } - assert((offset & (BDRV_SECTOR_SIZE - 1)) == 0); - assert((cur_bytes & (BDRV_SECTOR_SIZE - 1)) == 0); - if (qcow2_co_decrypt(bs, cluster_offset, offset, + assert(QEMU_IS_ALIGNED(offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(cur_bytes, BDRV_SECTOR_SIZE)); + if (qcow2_co_decrypt(bs, cluster_offset + offset_in_cluster, + offset, cluster_data, cur_bytes) < 0) { ret = -EIO; goto fail; @@ -2284,7 +2289,7 @@ static coroutine_fn int qcow2_co_pwritev_part( qemu_iovec_to_buf(qiov, qiov_offset + bytes_done, cluster_data, cur_bytes); - if (qcow2_co_encrypt(bs, cluster_offset, offset, + if (qcow2_co_encrypt(bs, cluster_offset + offset_in_cluster, offset, cluster_data, cur_bytes) < 0) { ret = -EIO; goto out_unlocked; diff --git a/block/qcow2.h b/block/qcow2.h index 998bcdaef1..a488d761ff 100644 --- a/block/qcow2.h +++ b/block/qcow2.h @@ -758,10 +758,10 @@ ssize_t coroutine_fn qcow2_co_decompress(BlockDriverState *bs, void *dest, size_t dest_size, const void *src, size_t src_size); int coroutine_fn -qcow2_co_encrypt(BlockDriverState *bs, uint64_t file_cluster_offset, - uint64_t offset, void *buf, size_t len); +qcow2_co_encrypt(BlockDriverState *bs, uint64_t host_offset, + uint64_t guest_offset, void *buf, size_t len); int coroutine_fn -qcow2_co_decrypt(BlockDriverState *bs, uint64_t file_cluster_offset, - uint64_t offset, void *buf, size_t len); +qcow2_co_decrypt(BlockDriverState *bs, uint64_t host_offset, + uint64_t guest_offset, void *buf, size_t len); #endif diff --git a/block/stream.c b/block/stream.c index 0d3a6ac7c3..5562ccbf57 100644 --- a/block/stream.c +++ b/block/stream.c @@ -212,7 +212,6 @@ static const BlockJobDriver stream_job_driver = { .abort = stream_abort, .clean = stream_clean, .user_resume = block_job_user_resume, - .drain = block_job_drain, }, }; diff --git a/block/vpc.c b/block/vpc.c index b25aab0425..5cd3890780 100644 --- a/block/vpc.c +++ b/block/vpc.c @@ -885,6 +885,7 @@ static int create_dynamic_disk(BlockBackend *blk, uint8_t *buf, goto fail; } + ret = 0; fail: return ret; } @@ -908,7 +909,7 @@ static int create_fixed_disk(BlockBackend *blk, uint8_t *buf, return ret; } - return ret; + return 0; } static int calculate_rounded_image_size(BlockdevCreateOptionsVpc *vpc_opts, diff --git a/block/vvfat.c b/block/vvfat.c index f6c28805dd..019b8f1341 100644 --- a/block/vvfat.c +++ b/block/vvfat.c @@ -1547,8 +1547,8 @@ vvfat_co_preadv(BlockDriverState *bs, uint64_t offset, uint64_t bytes, int nb_sectors = bytes >> BDRV_SECTOR_BITS; void *buf; - assert((offset & (BDRV_SECTOR_SIZE - 1)) == 0); - assert((bytes & (BDRV_SECTOR_SIZE - 1)) == 0); + assert(QEMU_IS_ALIGNED(offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(bytes, BDRV_SECTOR_SIZE)); buf = g_try_malloc(bytes); if (bytes && buf == NULL) { @@ -3082,8 +3082,8 @@ vvfat_co_pwritev(BlockDriverState *bs, uint64_t offset, uint64_t bytes, int nb_sectors = bytes >> BDRV_SECTOR_BITS; void *buf; - assert((offset & (BDRV_SECTOR_SIZE - 1)) == 0); - assert((bytes & (BDRV_SECTOR_SIZE - 1)) == 0); + assert(QEMU_IS_ALIGNED(offset, BDRV_SECTOR_SIZE)); + assert(QEMU_IS_ALIGNED(bytes, BDRV_SECTOR_SIZE)); buf = g_try_malloc(bytes); if (bytes && buf == NULL) { diff --git a/blockjob.c b/blockjob.c index 6e32d1a0c0..c6e20e2fcd 100644 --- a/blockjob.c +++ b/blockjob.c @@ -90,18 +90,6 @@ void block_job_free(Job *job) error_free(bjob->blocker); } -void block_job_drain(Job *job) -{ - BlockJob *bjob = container_of(job, BlockJob, job); - const JobDriver *drv = job->driver; - BlockJobDriver *bjdrv = container_of(drv, BlockJobDriver, job_driver); - - blk_drain(bjob->blk); - if (bjdrv->drain) { - bjdrv->drain(bjob); - } -} - static char *child_job_get_parent_desc(BdrvChild *c) { BlockJob *job = c->opaque; @@ -187,14 +175,23 @@ static const BdrvChildRole child_job = { void block_job_remove_all_bdrv(BlockJob *job) { - GSList *l; - for (l = job->nodes; l; l = l->next) { + /* + * bdrv_root_unref_child() may reach child_job_[can_]set_aio_ctx(), + * which will also traverse job->nodes, so consume the list one by + * one to make sure that such a concurrent access does not attempt + * to process an already freed BdrvChild. + */ + while (job->nodes) { + GSList *l = job->nodes; BdrvChild *c = l->data; + + job->nodes = l->next; + bdrv_op_unblock_all(c->bs, job->blocker); bdrv_root_unref_child(c); + + g_slist_free_1(l); } - g_slist_free(job->nodes); - job->nodes = NULL; } bool block_job_has_bdrv(BlockJob *job, BlockDriverState *bs) @@ -422,7 +419,6 @@ void *block_job_create(const char *job_id, const BlockJobDriver *driver, assert(is_block_job(&job->job)); assert(job->job.driver->free == &block_job_free); assert(job->job.driver->user_resume == &block_job_user_resume); - assert(job->job.driver->drain == &block_job_drain); job->blk = blk; diff --git a/configure b/configure index 95134c0180..30aad233d1 100755 --- a/configure +++ b/configure @@ -495,27 +495,10 @@ qed="yes" parallels="yes" sheepdog="yes" libxml2="" -docker="no" debug_mutex="no" libpmem="" default_devices="yes" -# cross compilers defaults, can be overridden with --cross-cc-ARCH -cross_cc_aarch64="aarch64-linux-gnu-gcc" -cross_cc_aarch64_be="$cross_cc_aarch64" -cross_cc_cflags_aarch64_be="-mbig-endian" -cross_cc_arm="arm-linux-gnueabihf-gcc" -cross_cc_cflags_armeb="-mbig-endian" -cross_cc_i386="i386-pc-linux-gnu-gcc" -cross_cc_cflags_i386="" -cross_cc_ppc="powerpc-linux-gnu-gcc" -cross_cc_cflags_ppc="-m32" -cross_cc_ppc64="powerpc-linux-gnu-gcc" -cross_cc_cflags_ppc64="-m64" -cross_cc_ppc64le="powerpc64le-linux-gnu-gcc" - -enabled_cross_compilers="" - supported_cpu="no" supported_os="no" bogus_os="no" @@ -548,9 +531,12 @@ for opt do ;; --cross-cc-cflags-*) cc_arch=${opt#--cross-cc-flags-}; cc_arch=${cc_arch%%=*} eval "cross_cc_cflags_${cc_arch}=\$optarg" + cross_cc_vars="$cross_cc_vars cross_cc_cflags_${cc_arch}" ;; --cross-cc-*) cc_arch=${opt#--cross-cc-}; cc_arch=${cc_arch%%=*} + cc_archs="$cc_archs $cc_arch" eval "cross_cc_${cc_arch}=\$optarg" + cross_cc_vars="$cross_cc_vars cross_cc_${cc_arch}" ;; esac done @@ -745,42 +731,34 @@ ARCH= case "$cpu" in ppc|ppc64|s390|s390x|sparc64|x32|riscv32|riscv64) supported_cpu="yes" - eval "cross_cc_${cpu}=\$host_cc" ;; ppc64le) ARCH="ppc64" supported_cpu="yes" - cross_cc_ppc64le=$host_cc ;; i386|i486|i586|i686|i86pc|BePC) cpu="i386" supported_cpu="yes" - cross_cc_i386=$host_cc ;; x86_64|amd64) cpu="x86_64" supported_cpu="yes" - cross_cc_x86_64=$host_cc ;; armv*b|armv*l|arm) cpu="arm" supported_cpu="yes" - cross_cc_arm=$host_cc ;; aarch64) cpu="aarch64" supported_cpu="yes" - cross_cc_aarch64=$host_cc ;; mips*) cpu="mips" supported_cpu="yes" - cross_cc_mips=$host_cc ;; sparc|sun4[cdmuv]) cpu="sparc" supported_cpu="yes" - cross_cc_sparc=$host_cc ;; *) # This will result in either an error or falling back to TCI later @@ -1555,44 +1533,30 @@ case "$cpu" in ppc) CPU_CFLAGS="-m32" LDFLAGS="-m32 $LDFLAGS" - cross_cc_ppc=$cc - cross_cc_cflags_ppc="$CPU_CFLAGS" ;; ppc64) CPU_CFLAGS="-m64" LDFLAGS="-m64 $LDFLAGS" - cross_cc_ppc64=$cc - cross_cc_cflags_ppc64="$CPU_CFLAGS" ;; sparc) CPU_CFLAGS="-m32 -mv8plus -mcpu=ultrasparc" LDFLAGS="-m32 -mv8plus $LDFLAGS" - cross_cc_sparc=$cc - cross_cc_cflags_sparc="$CPU_CFLAGS" ;; sparc64) CPU_CFLAGS="-m64 -mcpu=ultrasparc" LDFLAGS="-m64 $LDFLAGS" - cross_cc_sparc64=$cc - cross_cc_cflags_sparc64="$CPU_CFLAGS" ;; s390) CPU_CFLAGS="-m31" LDFLAGS="-m31 $LDFLAGS" - cross_cc_s390=$cc - cross_cc_cflags_s390="$CPU_CFLAGS" ;; s390x) CPU_CFLAGS="-m64" LDFLAGS="-m64 $LDFLAGS" - cross_cc_s390x=$cc - cross_cc_cflags_s390x="$CPU_CFLAGS" ;; i386) CPU_CFLAGS="-m32" LDFLAGS="-m32 $LDFLAGS" - cross_cc_i386=$cc - cross_cc_cflags_i386="$CPU_CFLAGS" ;; x86_64) # ??? Only extremely old AMD cpus do not have cmpxchg16b. @@ -1600,18 +1564,16 @@ case "$cpu" in # runtime and generate the fallback to serial emulation. CPU_CFLAGS="-m64 -mcx16" LDFLAGS="-m64 $LDFLAGS" - cross_cc_x86_64=$cc - cross_cc_cflags_x86_64="$CPU_CFLAGS" ;; x32) CPU_CFLAGS="-mx32" LDFLAGS="-mx32 $LDFLAGS" - cross_cc_i386=$cc - cross_cc_cflags_i386="$CPU_CFLAGS" ;; # No special flags required for other host CPUs esac +eval "cross_cc_${cpu}=\$host_cc" +cross_cc_vars="$cross_cc_vars cross_cc_${cpu}" QEMU_CFLAGS="$CPU_CFLAGS $QEMU_CFLAGS" # For user-mode emulation the host arch has to be one we explicitly @@ -2059,6 +2021,12 @@ static THREAD int tls_var; int main(void) { return tls_var; } EOF + # check we support --no-pie first... + if compile_prog "-Werror -fno-pie" "-no-pie"; then + CFLAGS_NOPIE="-fno-pie" + LDFLAGS_NOPIE="-nopie" + fi + if compile_prog "-fPIE -DPIE" "-pie"; then QEMU_CFLAGS="-fPIE -DPIE $QEMU_CFLAGS" LDFLAGS="-pie $LDFLAGS" @@ -2074,11 +2042,6 @@ EOF pie="no" fi fi - - if compile_prog "-Werror -fno-pie" "-nopie"; then - CFLAGS_NOPIE="-fno-pie" - LDFLAGS_NOPIE="-nopie" - fi fi ########################################## @@ -5894,17 +5857,6 @@ EOF fi ########################################## -# Docker and cross-compiler support -# -# This is specifically for building test -# cases for foreign architectures, not -# cross-compiling QEMU itself. - -if has "docker"; then - docker=$($python $source_path/tests/docker/docker.py probe) -fi - -########################################## # check for libpmem if test "$libpmem" != "no"; then @@ -6474,7 +6426,6 @@ echo "qed support $qed" echo "parallels support $parallels" echo "sheepdog support $sheepdog" echo "capstone $capstone" -echo "docker $docker" echo "libpmem support $libpmem" echo "libudev $libudev" echo "default devices $default_devices" @@ -7384,10 +7335,6 @@ if test "$gcov" = "yes" ; then echo "GCOV=$gcov_tool" >> $config_host_mak fi -if test "$docker" != "no"; then - echo "HAVE_USER_DOCKER=y" >> $config_host_mak -fi - if test "$libudev" != "no"; then echo "CONFIG_LIBUDEV=y" >> $config_host_mak echo "LIBUDEV_LIBS=$libudev_libs" >> $config_host_mak @@ -7461,10 +7408,6 @@ case "$target" in ;; esac -target_compiler="" -target_compiler_static="" -target_compiler_cflags="" - mkdir -p $target_dir echo "# Automatically generated by configure - do not modify" > $config_target_mak @@ -7481,26 +7424,20 @@ case "$target_name" in i386) mttcg="yes" gdb_xml_files="i386-32bit.xml" - target_compiler=$cross_cc_i386 - target_compiler_cflags=$cross_cc_ccflags_i386 ;; x86_64) TARGET_BASE_ARCH=i386 mttcg="yes" gdb_xml_files="i386-64bit.xml" - target_compiler=$cross_cc_x86_64 ;; alpha) mttcg="yes" - target_compiler=$cross_cc_alpha ;; arm|armeb) TARGET_ARCH=arm bflt="yes" mttcg="yes" gdb_xml_files="arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" - target_compiler=$cross_cc_arm - eval "target_compiler_cflags=\$cross_cc_cflags_${target_name}" ;; aarch64|aarch64_be) TARGET_ARCH=aarch64 @@ -7508,41 +7445,32 @@ case "$target_name" in bflt="yes" mttcg="yes" gdb_xml_files="aarch64-core.xml aarch64-fpu.xml arm-core.xml arm-vfp.xml arm-vfp3.xml arm-neon.xml" - target_compiler=$cross_cc_aarch64 - eval "target_compiler_cflags=\$cross_cc_cflags_${target_name}" ;; cris) - target_compiler=$cross_cc_cris ;; hppa) mttcg="yes" - target_compiler=$cross_cc_hppa ;; lm32) - target_compiler=$cross_cc_lm32 ;; m68k) bflt="yes" gdb_xml_files="cf-core.xml cf-fp.xml m68k-fp.xml" - target_compiler=$cross_cc_m68k ;; microblaze|microblazeel) TARGET_ARCH=microblaze bflt="yes" echo "TARGET_ABI32=y" >> $config_target_mak - target_compiler=$cross_cc_microblaze ;; mips|mipsel) mttcg="yes" TARGET_ARCH=mips - target_compiler=$cross_cc_mips echo "TARGET_ABI_MIPSO32=y" >> $config_target_mak ;; mipsn32|mipsn32el) mttcg="yes" TARGET_ARCH=mips64 TARGET_BASE_ARCH=mips - target_compiler=$cross_cc_mipsn32 echo "TARGET_ABI_MIPSN32=y" >> $config_target_mak echo "TARGET_ABI32=y" >> $config_target_mak ;; @@ -7550,32 +7478,24 @@ case "$target_name" in mttcg="yes" TARGET_ARCH=mips64 TARGET_BASE_ARCH=mips - target_compiler=$cross_cc_mips64 echo "TARGET_ABI_MIPSN64=y" >> $config_target_mak ;; moxie) - target_compiler=$cross_cc_moxie ;; nios2) - target_compiler=$cross_cc_nios2 ;; or1k) - target_compiler=$cross_cc_or1k TARGET_ARCH=openrisc TARGET_BASE_ARCH=openrisc ;; ppc) gdb_xml_files="power-core.xml power-fpu.xml power-altivec.xml power-spe.xml" - target_compiler=$cross_cc_ppc - target_compiler_cflags="$cross_cc_cflags_ppc" ;; ppc64) TARGET_BASE_ARCH=ppc TARGET_ABI_DIR=ppc mttcg=yes gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml" - target_compiler=$cross_cc_ppc64 - target_compiler_cflags="$cross_cc_cflags_ppc64" ;; ppc64le) TARGET_ARCH=ppc64 @@ -7583,7 +7503,6 @@ case "$target_name" in TARGET_ABI_DIR=ppc mttcg=yes gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml" - target_compiler=$cross_cc_ppc64le ;; ppc64abi32) TARGET_ARCH=ppc64 @@ -7591,60 +7510,48 @@ case "$target_name" in TARGET_ABI_DIR=ppc echo "TARGET_ABI32=y" >> $config_target_mak gdb_xml_files="power64-core.xml power-fpu.xml power-altivec.xml power-spe.xml power-vsx.xml" - target_compiler=$cross_cc_ppc64abi32 ;; riscv32) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes gdb_xml_files="riscv-32bit-cpu.xml riscv-32bit-fpu.xml riscv-32bit-csr.xml" - target_compiler=$cross_cc_riscv32 ;; riscv64) TARGET_BASE_ARCH=riscv TARGET_ABI_DIR=riscv mttcg=yes gdb_xml_files="riscv-64bit-cpu.xml riscv-64bit-fpu.xml riscv-64bit-csr.xml" - target_compiler=$cross_cc_riscv64 ;; sh4|sh4eb) TARGET_ARCH=sh4 bflt="yes" - target_compiler=$cross_cc_sh4 ;; sparc) - target_compiler=$cross_cc_sparc ;; sparc64) TARGET_BASE_ARCH=sparc - target_compiler=$cross_cc_sparc64 ;; sparc32plus) TARGET_ARCH=sparc64 TARGET_BASE_ARCH=sparc TARGET_ABI_DIR=sparc - target_compiler=$cross_cc_sparc32plus echo "TARGET_ABI32=y" >> $config_target_mak ;; s390x) mttcg=yes gdb_xml_files="s390x-core64.xml s390-acr.xml s390-fpr.xml s390-vx.xml s390-cr.xml s390-virt.xml s390-gs.xml" - target_compiler=$cross_cc_s390x ;; tilegx) - target_compiler=$cross_cc_tilegx ;; tricore) - target_compiler=$cross_cc_tricore ;; unicore32) - target_compiler=$cross_cc_unicore32 ;; xtensa|xtensaeb) TARGET_ARCH=xtensa bflt="yes" mttcg="yes" - target_compiler=$cross_cc_xtensa ;; *) error_exit "Unsupported target CPU" @@ -7655,27 +7562,6 @@ if [ "$TARGET_BASE_ARCH" = "" ]; then TARGET_BASE_ARCH=$TARGET_ARCH fi -# Do we have a cross compiler for this target? -if has $target_compiler; then - - write_c_skeleton - - if ! do_compiler "$target_compiler" $target_compiler_cflags -o $TMPE $TMPC -static ; then - # For host systems we might get away with building without -static - if ! do_compiler "$target_compiler" $target_compiler_cflags -o $TMPE $TMPC ; then - target_compiler="" - else - enabled_cross_compilers="${enabled_cross_compilers} '${target_compiler}'" - target_compiler_static="n" - fi - else - enabled_cross_compilers="${enabled_cross_compilers} '${target_compiler}'" - target_compiler_static="y" - fi -else - target_compiler="" -fi - symlink "$source_path/Makefile.target" "$target_dir/Makefile" upper() { @@ -7752,18 +7638,6 @@ if test "$target_bsd_user" = "yes" ; then echo "CONFIG_BSD_USER=y" >> $config_target_mak fi -if test -n "$target_compiler"; then - echo "CROSS_CC_GUEST=\"$target_compiler\"" >> $config_target_mak - - if test -n "$target_compiler_static"; then - echo "CROSS_CC_GUEST_STATIC=$target_compiler_static" >> $config_target_mak - fi - - if test -n "$target_compiler_cflags"; then - echo "CROSS_CC_GUEST_CFLAGS=$target_compiler_cflags" >> $config_target_mak - fi -fi - # generate QEMU_CFLAGS/LDFLAGS for targets @@ -7894,11 +7768,6 @@ done # for target in $targets echo "PIXMAN_CFLAGS=$pixman_cflags" >> $config_host_mak echo "PIXMAN_LIBS=$pixman_libs" >> $config_host_mak -if test -n "$enabled_cross_compilers"; then - echo - echo "NOTE: cross-compilers enabled: $enabled_cross_compilers" -fi - if [ "$fdt" = "git" ]; then echo "config-host.h: dtc/all" >> $config_host_mak fi @@ -7927,15 +7796,14 @@ fi # so the build tree will be missing the link back to the new file, and # tests might fail. Prefer to keep the relevant files in their own # directory and symlink the directory instead. -DIRS="tests tests/tcg tests/tcg/cris tests/tcg/lm32 tests/libqos tests/qapi-schema tests/tcg/xtensa tests/qemu-iotests tests/vm" +DIRS="tests tests/tcg tests/tcg/lm32 tests/libqos tests/qapi-schema tests/qemu-iotests tests/vm" DIRS="$DIRS tests/fp tests/qgraph" DIRS="$DIRS docs docs/interop fsdev scsi" DIRS="$DIRS pc-bios/optionrom pc-bios/spapr-rtas pc-bios/s390-ccw" DIRS="$DIRS roms/seabios roms/vgabios" -LINKS="Makefile tests/tcg/Makefile" -LINKS="$LINKS tests/tcg/cris/Makefile tests/tcg/cris/.gdbinit" -LINKS="$LINKS tests/tcg/lm32/Makefile tests/tcg/xtensa/Makefile po/Makefile" -LINKS="$LINKS tests/fp/Makefile" +LINKS="Makefile" +LINKS="$LINKS tests/tcg/lm32/Makefile po/Makefile" +LINKS="$LINKS tests/tcg/Makefile.target tests/fp/Makefile" LINKS="$LINKS pc-bios/optionrom/Makefile pc-bios/keymaps" LINKS="$LINKS pc-bios/spapr-rtas/Makefile" LINKS="$LINKS pc-bios/s390-ccw/Makefile" @@ -7965,6 +7833,12 @@ for f in $LINKS ; do fi done +(for i in $cross_cc_vars; do + export $i +done +export target_list source_path +$source_path/tests/tcg/configure.sh) + # temporary config to build submodules for rom in seabios vgabios ; do config_mak=roms/$rom/config.mak diff --git a/cpus.c b/cpus.c index 85cd451a86..d2c61ff155 100644 --- a/cpus.c +++ b/cpus.c @@ -77,6 +77,8 @@ #endif /* CONFIG_LINUX */ +static QemuMutex qemu_global_mutex; + int64_t max_delay; int64_t max_advance; @@ -782,7 +784,7 @@ static void cpu_throttle_thread(CPUState *cpu, run_on_cpu_data opaque) { double pct; double throttle_ratio; - long sleeptime_ns; + int64_t sleeptime_ns, endtime_ns; if (!cpu_throttle_get_percentage()) { return; @@ -790,11 +792,20 @@ static void cpu_throttle_thread(CPUState *cpu, run_on_cpu_data opaque) pct = (double)cpu_throttle_get_percentage()/100; throttle_ratio = pct / (1 - pct); - sleeptime_ns = (long)(throttle_ratio * CPU_THROTTLE_TIMESLICE_NS); - - qemu_mutex_unlock_iothread(); - g_usleep(sleeptime_ns / 1000); /* Convert ns to us for usleep call */ - qemu_mutex_lock_iothread(); + /* Add 1ns to fix double's rounding error (like 0.9999999...) */ + sleeptime_ns = (int64_t)(throttle_ratio * CPU_THROTTLE_TIMESLICE_NS + 1); + endtime_ns = qemu_clock_get_ns(QEMU_CLOCK_REALTIME) + sleeptime_ns; + while (sleeptime_ns > 0 && !cpu->stop) { + if (sleeptime_ns > SCALE_MS) { + qemu_cond_timedwait(cpu->halt_cond, &qemu_global_mutex, + sleeptime_ns / SCALE_MS); + } else { + qemu_mutex_unlock_iothread(); + g_usleep(sleeptime_ns / SCALE_US); + qemu_mutex_lock_iothread(); + } + sleeptime_ns = endtime_ns - qemu_clock_get_ns(QEMU_CLOCK_REALTIME); + } atomic_set(&cpu->throttle_thread_scheduled, 0); } @@ -1172,8 +1183,6 @@ static void qemu_init_sigbus(void) } #endif /* !CONFIG_LINUX */ -static QemuMutex qemu_global_mutex; - static QemuThread io_thread; /* cpu creation */ diff --git a/default-configs/i386-softmmu.mak b/default-configs/i386-softmmu.mak index cd5ea391e8..ba3fb3ff50 100644 --- a/default-configs/i386-softmmu.mak +++ b/default-configs/i386-softmmu.mak @@ -25,4 +25,3 @@ CONFIG_ISAPC=y CONFIG_I440FX=y CONFIG_Q35=y -CONFIG_ACPI_PCI=y diff --git a/docs/conf.py b/docs/conf.py index e46b299b71..b7edb0666b 100644 --- a/docs/conf.py +++ b/docs/conf.py @@ -115,6 +115,14 @@ todo_include_todos = False # with "option::" in the document being processed. Turn that off. suppress_warnings = ["ref.option"] +# The rst_epilog fragment is effectively included in every rST file. +# We use it to define substitutions based on build config that +# can then be used in the documentation. The fallback if the +# environment variable is not set is for the benefit of readthedocs +# style document building; our Makefile always sets the variable. +confdir = os.getenv('CONFDIR', "/etc/qemu") +rst_epilog = ".. |CONFDIR| replace:: ``" + confdir + "``\n" + # -- Options for HTML output ---------------------------------------------- # The theme to use for HTML and HTML Help pages. See the documentation for @@ -192,14 +200,8 @@ latex_documents = [ # -- Options for manual page output --------------------------------------- - -# One entry per manual page. List of tuples -# (source start file, name, description, authors, manual section). -man_pages = [ - (master_doc, 'qemu', u'QEMU Documentation', - [author], 1) -] - +# Individual manual/conf.py can override this to create man pages +man_pages = [] # -- Options for Texinfo output ------------------------------------------- diff --git a/docs/devel/migration.rst b/docs/devel/migration.rst index f7668ae389..e88918f763 100644 --- a/docs/devel/migration.rst +++ b/docs/devel/migration.rst @@ -183,8 +183,7 @@ another to load the state back. .. code:: c - int register_savevm_live(DeviceState *dev, - const char *idstr, + int register_savevm_live(const char *idstr, int instance_id, int version_id, SaveVMHandlers *ops, diff --git a/docs/devel/tracing.txt b/docs/devel/tracing.txt index 76e492a489..8231bbf5d1 100644 --- a/docs/devel/tracing.txt +++ b/docs/devel/tracing.txt @@ -112,6 +112,8 @@ Trace events should use types as follows: Format strings should reflect the types defined in the trace event. Take special care to use PRId64 and PRIu64 for int64_t and uint64_t types, respectively. This ensures portability between 32- and 64-bit platforms. +Format strings must not end with a newline character. It is the responsibility +of backends to adapt line ending for proper logging. Each event declaration will start with the event name, then its arguments, finally a format string for pretty-printing. For example: diff --git a/docs/interop/conf.py b/docs/interop/conf.py index cf3c69d4a7..e87b8c22be 100644 --- a/docs/interop/conf.py +++ b/docs/interop/conf.py @@ -13,3 +13,10 @@ exec(compile(open(parent_config, "rb").read(), parent_config, 'exec')) # This slightly misuses the 'description', but is the best way to get # the manual title to appear in the sidebar. html_theme_options['description'] = u'System Emulation Management and Interoperability Guide' + +# One entry per manual page. List of tuples +# (source start file, name, description, authors, manual section). +man_pages = [ + ('qemu-ga', 'qemu-ga', u'QEMU Guest Agent', + ['Michael Roth <mdroth@linux.vnet.ibm.com>'], 8) +] diff --git a/docs/interop/index.rst b/docs/interop/index.rst index b4bfcab417..3e33fb5933 100644 --- a/docs/interop/index.rst +++ b/docs/interop/index.rst @@ -15,5 +15,6 @@ Contents: bitmaps live-block-operations pr-helper + qemu-ga vhost-user vhost-user-gpu diff --git a/docs/interop/qemu-ga.rst b/docs/interop/qemu-ga.rst new file mode 100644 index 0000000000..1313a4ae1c --- /dev/null +++ b/docs/interop/qemu-ga.rst @@ -0,0 +1,133 @@ +QEMU Guest Agent +================ + +Synopsis +-------- + +**qemu-ga** [*OPTIONS*] + +Description +----------- + +The QEMU Guest Agent is a daemon intended to be run within virtual +machines. It allows the hypervisor host to perform various operations +in the guest, such as: + +- get information from the guest +- set the guest's system time +- read/write a file +- sync and freeze the filesystems +- suspend the guest +- reconfigure guest local processors +- set user's password +- ... + +qemu-ga will read a system configuration file on startup (located at +|CONFDIR|\ ``/qemu-ga.conf`` by default), then parse remaining +configuration options on the command line. For the same key, the last +option wins, but the lists accumulate (see below for configuration +file format). + +Options +------- + +.. program:: qemu-ga + +.. option:: -m, --method=METHOD + + Transport method: one of ``unix-listen``, ``virtio-serial``, or + ``isa-serial`` (``virtio-serial`` is the default). + +.. option:: -p, --path=PATH + + Device/socket path (the default for virtio-serial is + ``/dev/virtio-ports/org.qemu.guest_agent.0``, + the default for isa-serial is ``/dev/ttyS0``) + +.. option:: -l, --logfile=PATH + + Set log file path (default is stderr). + +.. option:: -f, --pidfile=PATH + + Specify pid file (default is ``/var/run/qemu-ga.pid``). + +.. option:: -F, --fsfreeze-hook=PATH + + Enable fsfreeze hook. Accepts an optional argument that specifies + script to run on freeze/thaw. Script will be called with + 'freeze'/'thaw' arguments accordingly (default is + |CONFDIR|\ ``/fsfreeze-hook``). If using -F with an argument, do + not follow -F with a space (for example: + ``-F/var/run/fsfreezehook.sh``). + +.. option:: -t, --statedir=PATH + + Specify the directory to store state information (absolute paths only, + default is ``/var/run``). + +.. option:: -v, --verbose + + Log extra debugging information. + +.. option:: -V, --version + + Print version information and exit. + +.. option:: -d, --daemon + + Daemonize after startup (detach from terminal). + +.. option:: -b, --blacklist=LIST + + Comma-separated list of RPCs to disable (no spaces, ``?`` to list + available RPCs). + +.. option:: -D, --dump-conf + + Dump the configuration in a format compatible with ``qemu-ga.conf`` + and exit. + +.. option:: -h, --help + + Display this help and exit. + +Files +----- + + +The syntax of the ``qemu-ga.conf`` configuration file follows the +Desktop Entry Specification, here is a quick summary: it consists of +groups of key-value pairs, interspersed with comments. + +:: + + # qemu-ga configuration sample + [general] + daemonize = 0 + pidfile = /var/run/qemu-ga.pid + verbose = 0 + method = virtio-serial + path = /dev/virtio-ports/org.qemu.guest_agent.0 + statedir = /var/run + +The list of keys follows the command line options: + +============= =========== +Key Key type +============= =========== +daemon boolean +method string +path string +logfile string +pidfile string +fsfreeze-hook string +statedir string +verbose boolean +blacklist string list +============= =========== + +See also +-------- + +:manpage:`qemu(1)` diff --git a/docs/nvdimm.txt b/docs/nvdimm.txt index b531cacd35..362e99109e 100644 --- a/docs/nvdimm.txt +++ b/docs/nvdimm.txt @@ -171,6 +171,35 @@ guest software that this vNVDIMM device contains a region that cannot accept persistent writes. In result, for example, the guest Linux NVDIMM driver, marks such vNVDIMM device as read-only. +Backend File Setup Example +-------------------------- + +Here are two examples showing how to setup these persistent backends on +linux using the tool ndctl [3]. + +A. DAX device + +Use the following command to set up /dev/dax0.0 so that the entirety of +namespace0.0 can be exposed as an emulated NVDIMM to the guest: + + ndctl create-namespace -f -e namespace0.0 -m devdax + +The /dev/dax0.0 could be used directly in "mem-path" option. + +B. DAX file + +Individual files on a DAX host file system can be exposed as emulated +NVDIMMS. First an fsdax block device is created, partitioned, and then +mounted with the "dax" mount option: + + ndctl create-namespace -f -e namespace0.0 -m fsdax + (partition /dev/pmem0 with name pmem0p1) + mount -o dax /dev/pmem0p1 /mnt + (create or copy a disk image file with qemu-img(1), cp(1), or dd(1) + in /mnt) + +Then the new file in /mnt could be used in "mem-path" option. + NVDIMM Persistence ------------------ @@ -212,3 +241,5 @@ References https://www.snia.org/sites/default/files/technical_work/final/NVMProgrammingModel_v1.2.pdf [2] Persistent Memory Development Kit (PMDK), formerly known as NVML project, home page: http://pmem.io/pmdk/ +[3] ndctl-create-namespace - provision or reconfigure a namespace + http://pmem.io/ndctl/ndctl-create-namespace.html diff --git a/docs/virtio-pmem.rst b/docs/virtio-pmem.rst new file mode 100644 index 0000000000..e77881b26f --- /dev/null +++ b/docs/virtio-pmem.rst @@ -0,0 +1,75 @@ + +======================== +QEMU virtio pmem +======================== + + This document explains the setup and usage of the virtio pmem device + which is available since QEMU v4.1.0. + + The virtio pmem device is a paravirtualized persistent memory device + on regular (i.e non-NVDIMM) storage. + +Usecase +-------- + + Virtio pmem allows to bypass the guest page cache and directly use + host page cache. This reduces guest memory footprint as the host can + make efficient memory reclaim decisions under memory pressure. + +o How does virtio-pmem compare to the nvdimm emulation supported by QEMU? + + NVDIMM emulation on regular (i.e. non-NVDIMM) host storage does not + persist the guest writes as there are no defined semantics in the device + specification. The virtio pmem device provides guest write persistence + on non-NVDIMM host storage. + +virtio pmem usage +----------------- + + A virtio pmem device backed by a memory-backend-file can be created on + the QEMU command line as in the following example: + + -object memory-backend-file,id=mem1,share,mem-path=./virtio_pmem.img,size=4G + -device virtio-pmem-pci,memdev=mem1,id=nv1 + + where: + - "object memory-backend-file,id=mem1,share,mem-path=<image>, size=<image size>" + creates a backend file with the specified size. + + - "device virtio-pmem-pci,id=nvdimm1,memdev=mem1" creates a virtio pmem + pci device whose storage is provided by above memory backend device. + + Multiple virtio pmem devices can be created if multiple pairs of "-object" + and "-device" are provided. + +Hotplug +------- + +Virtio pmem devices can be hotplugged via the QEMU monitor. First, the +memory backing has to be added via 'object_add'; afterwards, the virtio +pmem device can be added via 'device_add'. + +For example, the following commands add another 4GB virtio pmem device to +the guest: + + (qemu) object_add memory-backend-file,id=mem2,share=on,mem-path=virtio_pmem2.img,size=4G + (qemu) device_add virtio-pmem-pci,id=virtio_pmem2,memdev=mem2 + +Guest Data Persistence +---------------------- + + Guest data persistence on non-NVDIMM requires guest userspace applications + to perform fsync/msync. This is different from a real nvdimm backend where + no additional fsync/msync is required. This is to persist guest writes in + host backing file which otherwise remains in host page cache and there is + risk of losing the data in case of power failure. + + With virtio pmem device, MAP_SYNC mmap flag is not supported. This provides + a hint to application to perform fsync for write persistence. + +Limitations +------------ +- Real nvdimm device backend is not supported. +- virtio pmem hotunplug is not supported. +- ACPI NVDIMM features like regions/namespaces are not supported. +- ndctl command is not supported. diff --git a/exec.c b/exec.c index 235d6bc883..8b998974f8 100644 --- a/exec.c +++ b/exec.c @@ -227,8 +227,7 @@ static void phys_map_node_reserve(PhysPageMap *map, unsigned nodes) { static unsigned alloc_hint = 16; if (map->nodes_nb + nodes > map->nodes_nb_alloc) { - map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, alloc_hint); - map->nodes_nb_alloc = MAX(map->nodes_nb_alloc, map->nodes_nb + nodes); + map->nodes_nb_alloc = MAX(alloc_hint, map->nodes_nb + nodes); map->nodes = g_renew(Node, map->nodes, map->nodes_nb_alloc); alloc_hint = map->nodes_nb_alloc; } @@ -255,7 +254,7 @@ static uint32_t phys_map_node_alloc(PhysPageMap *map, bool leaf) } static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, - hwaddr *index, hwaddr *nb, uint16_t leaf, + hwaddr *index, uint64_t *nb, uint16_t leaf, int level) { PhysPageEntry *p; @@ -281,7 +280,7 @@ static void phys_page_set_level(PhysPageMap *map, PhysPageEntry *lp, } static void phys_page_set(AddressSpaceDispatch *d, - hwaddr index, hwaddr nb, + hwaddr index, uint64_t nb, uint16_t leaf) { /* Wildly overreserve - it doesn't matter much. */ @@ -325,7 +324,8 @@ static void phys_page_compact(PhysPageEntry *lp, Node *nodes) assert(valid_ptr < P_L2_SIZE); /* Don't compress if it won't fit in the # of bits we have. */ - if (lp->skip + p[valid_ptr].skip >= (1 << 3)) { + if (P_L2_LEVELS >= (1 << 6) && + lp->skip + p[valid_ptr].skip >= (1 << 6)) { return; } @@ -1492,8 +1492,8 @@ hwaddr memory_region_section_get_iotlb(CPUState *cpu, #if !defined(CONFIG_USER_ONLY) -static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, - uint16_t section); +static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end, + uint16_t section); static subpage_t *subpage_init(FlatView *fv, hwaddr base); static void *(*phys_mem_alloc)(size_t size, uint64_t *align, bool shared) = @@ -1791,7 +1791,39 @@ long qemu_maxrampagesize(void) #ifdef CONFIG_POSIX static int64_t get_file_size(int fd) { - int64_t size = lseek(fd, 0, SEEK_END); + int64_t size; +#if defined(__linux__) + struct stat st; + + if (fstat(fd, &st) < 0) { + return -errno; + } + + /* Special handling for devdax character devices */ + if (S_ISCHR(st.st_mode)) { + g_autofree char *subsystem_path = NULL; + g_autofree char *subsystem = NULL; + + subsystem_path = g_strdup_printf("/sys/dev/char/%d:%d/subsystem", + major(st.st_rdev), minor(st.st_rdev)); + subsystem = g_file_read_link(subsystem_path, NULL); + + if (subsystem && g_str_has_suffix(subsystem, "/dax")) { + g_autofree char *size_path = NULL; + g_autofree char *size_str = NULL; + + size_path = g_strdup_printf("/sys/dev/char/%d:%d/size", + major(st.st_rdev), minor(st.st_rdev)); + + if (g_file_get_contents(size_path, &size_str, NULL, NULL)) { + return g_ascii_strtoll(size_str, NULL, 0); + } + } + } +#endif /* defined(__linux__) */ + + /* st.st_size may be zero for special files yet lseek(2) works */ + size = lseek(fd, 0, SEEK_END); if (size < 0) { return -errno; } @@ -2914,8 +2946,8 @@ static const MemoryRegionOps subpage_ops = { .endianness = DEVICE_NATIVE_ENDIAN, }; -static int subpage_register (subpage_t *mmio, uint32_t start, uint32_t end, - uint16_t section) +static int subpage_register(subpage_t *mmio, uint32_t start, uint32_t end, + uint16_t section) { int idx, eidx; @@ -2938,6 +2970,7 @@ static subpage_t *subpage_init(FlatView *fv, hwaddr base) { subpage_t *mmio; + /* mmio->sub_section is set to PHYS_SECTION_UNASSIGNED with g_malloc0 */ mmio = g_malloc0(sizeof(subpage_t) + TARGET_PAGE_SIZE * sizeof(uint16_t)); mmio->fv = fv; mmio->base = base; @@ -2948,7 +2981,6 @@ static subpage_t *subpage_init(FlatView *fv, hwaddr base) printf("%s: %p base " TARGET_FMT_plx " len %08x\n", __func__, mmio, base, TARGET_PAGE_SIZE); #endif - subpage_register(mmio, 0, TARGET_PAGE_SIZE-1, PHYS_SECTION_UNASSIGNED); return mmio; } diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx index c59444c461..257ee7d7a3 100644 --- a/hmp-commands-info.hx +++ b/hmp-commands-info.hx @@ -249,7 +249,7 @@ STEXI Show virtual to physical memory mappings. ETEXI -#if defined(TARGET_I386) +#if defined(TARGET_I386) || defined(TARGET_RISCV) { .name = "mem", .args_type = "", diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index 13e208c78c..aa72be309d 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -190,6 +190,8 @@ static void aspeed_board_init(MachineState *machine, &error_abort); object_property_set_int(OBJECT(&bmc->soc), machine->smp.cpus, "num-cpus", &error_abort); + object_property_set_link(OBJECT(&bmc->soc), OBJECT(&bmc->ram_container), + "dram", &error_abort); if (machine->kernel_filename) { /* * When booting with a -kernel command line there is no u-boot diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 9ee8104832..cf1d0cf921 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -112,43 +112,13 @@ static const int aspeed_soc_ast2400_irqmap[] = { #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap -static const char *aspeed_soc_ast2400_typenames[] = { "aspeed.smc.spi" }; -static const char *aspeed_soc_ast2500_typenames[] = { - "aspeed.smc.ast2500-spi1", "aspeed.smc.ast2500-spi2" }; - static const AspeedSoCInfo aspeed_socs[] = { { - .name = "ast2400-a0", - .cpu_type = ARM_CPU_TYPE_NAME("arm926"), - .silicon_rev = AST2400_A0_SILICON_REV, - .sram_size = 0x8000, - .spis_num = 1, - .fmc_typename = "aspeed.smc.fmc", - .spi_typename = aspeed_soc_ast2400_typenames, - .wdts_num = 2, - .irqmap = aspeed_soc_ast2400_irqmap, - .memmap = aspeed_soc_ast2400_memmap, - .num_cpus = 1, - }, { .name = "ast2400-a1", .cpu_type = ARM_CPU_TYPE_NAME("arm926"), .silicon_rev = AST2400_A1_SILICON_REV, .sram_size = 0x8000, .spis_num = 1, - .fmc_typename = "aspeed.smc.fmc", - .spi_typename = aspeed_soc_ast2400_typenames, - .wdts_num = 2, - .irqmap = aspeed_soc_ast2400_irqmap, - .memmap = aspeed_soc_ast2400_memmap, - .num_cpus = 1, - }, { - .name = "ast2400", - .cpu_type = ARM_CPU_TYPE_NAME("arm926"), - .silicon_rev = AST2400_A0_SILICON_REV, - .sram_size = 0x8000, - .spis_num = 1, - .fmc_typename = "aspeed.smc.fmc", - .spi_typename = aspeed_soc_ast2400_typenames, .wdts_num = 2, .irqmap = aspeed_soc_ast2400_irqmap, .memmap = aspeed_soc_ast2400_memmap, @@ -159,8 +129,6 @@ static const AspeedSoCInfo aspeed_socs[] = { .silicon_rev = AST2500_A1_SILICON_REV, .sram_size = 0x9000, .spis_num = 2, - .fmc_typename = "aspeed.smc.ast2500-fmc", - .spi_typename = aspeed_soc_ast2500_typenames, .wdts_num = 3, .irqmap = aspeed_soc_ast2500_irqmap, .memmap = aspeed_soc_ast2500_memmap, @@ -180,6 +148,12 @@ static void aspeed_soc_init(Object *obj) AspeedSoCState *s = ASPEED_SOC(obj); AspeedSoCClass *sc = ASPEED_SOC_GET_CLASS(s); int i; + char socname[8]; + char typename[64]; + + if (sscanf(sc->info->name, "%7s", socname) != 1) { + g_assert_not_reached(); + } for (i = 0; i < sc->info->num_cpus; i++) { object_initialize_child(obj, "cpu[*]", OBJECT(&s->cpu[i]), @@ -187,8 +161,9 @@ static void aspeed_soc_init(Object *obj) &error_abort, NULL); } + snprintf(typename, sizeof(typename), "aspeed.scu-%s", socname); sysbus_init_child_obj(obj, "scu", OBJECT(&s->scu), sizeof(s->scu), - TYPE_ASPEED_SCU); + typename); qdev_prop_set_uint32(DEVICE(&s->scu), "silicon-rev", sc->info->silicon_rev); object_property_add_alias(obj, "hw-strap1", OBJECT(&s->scu), @@ -212,14 +187,18 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "i2c", OBJECT(&s->i2c), sizeof(s->i2c), TYPE_ASPEED_I2C); + snprintf(typename, sizeof(typename), "aspeed.fmc-%s", socname); sysbus_init_child_obj(obj, "fmc", OBJECT(&s->fmc), sizeof(s->fmc), - sc->info->fmc_typename); + typename); object_property_add_alias(obj, "num-cs", OBJECT(&s->fmc), "num-cs", &error_abort); + object_property_add_alias(obj, "dram", OBJECT(&s->fmc), "dram", + &error_abort); for (i = 0; i < sc->info->spis_num; i++) { + snprintf(typename, sizeof(typename), "aspeed.spi%d-%s", i + 1, socname); sysbus_init_child_obj(obj, "spi[*]", OBJECT(&s->spi[i]), - sizeof(s->spi[i]), sc->info->spi_typename[i]); + sizeof(s->spi[i]), typename); } sysbus_init_child_obj(obj, "sdmc", OBJECT(&s->sdmc), sizeof(s->sdmc), @@ -247,6 +226,10 @@ static void aspeed_soc_init(Object *obj) sysbus_init_child_obj(obj, "xdma", OBJECT(&s->xdma), sizeof(s->xdma), TYPE_ASPEED_XDMA); + + snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); + sysbus_init_child_obj(obj, "gpio", OBJECT(&s->gpio), sizeof(s->gpio), + typename); } static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -426,6 +409,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) sc->info->memmap[ASPEED_XDMA]); sysbus_connect_irq(SYS_BUS_DEVICE(&s->xdma), 0, aspeed_soc_get_irq(s, ASPEED_XDMA)); + + /* GPIO */ + object_property_set_bool(OBJECT(&s->gpio), true, "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, sc->info->memmap[ASPEED_GPIO]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->gpio), 0, + aspeed_soc_get_irq(s, ASPEED_GPIO)); } static Property aspeed_soc_properties[] = { DEFINE_PROP_UINT32("num-cpus", AspeedSoCState, num_cpus, 0), diff --git a/hw/block/dataplane/virtio-blk.c b/hw/block/dataplane/virtio-blk.c index 9299a1a7c2..119906a5fe 100644 --- a/hw/block/dataplane/virtio-blk.c +++ b/hw/block/dataplane/virtio-blk.c @@ -298,6 +298,9 @@ void virtio_blk_data_plane_stop(VirtIODevice *vdev) virtio_bus_cleanup_host_notifier(VIRTIO_BUS(qbus), i); } + qemu_bh_cancel(s->bh); + notify_guest_bh(s); /* final chance to notify guest */ + /* Clean up guest notifier (irq) */ k->set_guest_notifiers(qbus->parent, nvqs, false); diff --git a/hw/block/vhost-user-blk.c b/hw/block/vhost-user-blk.c index 0b8c5dfeab..63da9bb619 100644 --- a/hw/block/vhost-user-blk.c +++ b/hw/block/vhost-user-blk.c @@ -421,7 +421,7 @@ static void vhost_user_blk_device_realize(DeviceState *dev, Error **errp) } s->inflight = g_new0(struct vhost_inflight, 1); - s->vqs = g_new(struct vhost_virtqueue, s->num_queues); + s->vqs = g_new0(struct vhost_virtqueue, s->num_queues); s->watch = 0; s->connected = false; diff --git a/hw/core/loader.c b/hw/core/loader.c index 32f7cc7c33..0d60219364 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -45,6 +45,7 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "qapi/error.h" +#include "trace.h" #include "hw/hw.h" #include "disas/disas.h" #include "migration/vmstate.h" @@ -338,6 +339,8 @@ const char *load_elf_strerror(int error) return "The image is from incompatible architecture"; case ELF_LOAD_WRONG_ENDIAN: return "The image has incorrect endianness"; + case ELF_LOAD_TOO_BIG: + return "The image segments are too big to load"; default: return "Unknown error"; } @@ -1149,6 +1152,8 @@ static void rom_reset(void *unused) * CPU definitely fetches its instructions from the just written data. */ cpu_flush_icache_range(rom->addr, rom->datasize); + + trace_loader_write_rom(rom->name, rom->addr, rom->datasize, rom->isrom); } } diff --git a/hw/core/qdev.c b/hw/core/qdev.c index 60d66c2f39..cbad6c1d55 100644 --- a/hw/core/qdev.c +++ b/hw/core/qdev.c @@ -237,6 +237,23 @@ HotplugHandler *qdev_get_machine_hotplug_handler(DeviceState *dev) return NULL; } +bool qdev_hotplug_allowed(DeviceState *dev, Error **errp) +{ + MachineState *machine; + MachineClass *mc; + Object *m_obj = qdev_get_machine(); + + if (object_dynamic_cast(m_obj, TYPE_MACHINE)) { + machine = MACHINE(m_obj); + mc = MACHINE_GET_CLASS(machine); + if (mc->hotplug_allowed) { + return mc->hotplug_allowed(machine, dev, errp); + } + } + + return true; +} + HotplugHandler *qdev_get_bus_hotplug_handler(DeviceState *dev) { if (dev->parent_bus) { diff --git a/hw/core/trace-events b/hw/core/trace-events new file mode 100644 index 0000000000..fe47a9c8cb --- /dev/null +++ b/hw/core/trace-events @@ -0,0 +1,2 @@ +# loader.c +loader_write_rom(const char *name, uint64_t gpa, uint64_t size, bool isrom) "%s: @0x%"PRIx64" size=0x%"PRIx64" ROM=%d" diff --git a/hw/display/ati.c b/hw/display/ati.c index 8f940eee22..db3b254316 100644 --- a/hw/display/ati.c +++ b/hw/display/ati.c @@ -19,6 +19,7 @@ #include "qemu/osdep.h" #include "ati_int.h" #include "ati_regs.h" +#include "vga-access.h" #include "hw/qdev-properties.h" #include "vga_regs.h" #include "qemu/log.h" @@ -135,19 +136,19 @@ static void ati_vga_switch_mode(ATIVGAState *s) static void ati_cursor_define(ATIVGAState *s) { uint8_t data[1024]; - uint8_t *src; + uint32_t srcoff; int i, j, idx = 0; if ((s->regs.cur_offset & BIT(31)) || s->cursor_guest_mode) { return; /* Do not update cursor if locked or rendered by guest */ } /* FIXME handle cur_hv_offs correctly */ - src = s->vga.vram_ptr + s->regs.cur_offset - - (s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0xffff) * 16; + srcoff = s->regs.cur_offset - + (s->regs.cur_hv_offs >> 16) - (s->regs.cur_hv_offs & 0xffff) * 16; for (i = 0; i < 64; i++) { for (j = 0; j < 8; j++, idx++) { - data[idx] = src[i * 16 + j]; - data[512 + idx] = src[i * 16 + j + 8]; + data[idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j); + data[512 + idx] = vga_read_byte(&s->vga, srcoff + i * 16 + j + 8); } } if (!s->cursor) { @@ -189,7 +190,7 @@ static void ati_cursor_invalidate(VGACommonState *vga) static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y) { ATIVGAState *s = container_of(vga, ATIVGAState, vga); - uint8_t *src; + uint32_t srcoff; uint32_t *dp = (uint32_t *)d; int i, j, h; @@ -199,13 +200,13 @@ static void ati_cursor_draw_line(VGACommonState *vga, uint8_t *d, int scr_y) return; } /* FIXME handle cur_hv_offs correctly */ - src = s->vga.vram_ptr + s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16; + srcoff = s->cursor_offset + (scr_y - vga->hw_cursor_y) * 16; dp = &dp[vga->hw_cursor_x]; h = ((s->regs.crtc_h_total_disp >> 16) + 1) * 8; for (i = 0; i < 8; i++) { uint32_t color; - uint8_t abits = src[i]; - uint8_t xbits = src[i + 8]; + uint8_t abits = vga_read_byte(vga, srcoff + i); + uint8_t xbits = vga_read_byte(vga, srcoff + i + 8); for (j = 0; j < 8; j++, abits <<= 1, xbits <<= 1) { if (abits & BIT(7)) { if (xbits & BIT(7)) { diff --git a/hw/display/vga-access.h b/hw/display/vga-access.h new file mode 100644 index 0000000000..c0fbd9958b --- /dev/null +++ b/hw/display/vga-access.h @@ -0,0 +1,49 @@ +/* + * QEMU VGA Emulator templates + * + * Copyright (c) 2003 Fabrice Bellard + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +static inline uint8_t vga_read_byte(VGACommonState *vga, uint32_t addr) +{ + return vga->vram_ptr[addr & vga->vbe_size_mask]; +} + +static inline uint16_t vga_read_word_le(VGACommonState *vga, uint32_t addr) +{ + uint32_t offset = addr & vga->vbe_size_mask & ~1; + uint16_t *ptr = (uint16_t *)(vga->vram_ptr + offset); + return lduw_le_p(ptr); +} + +static inline uint16_t vga_read_word_be(VGACommonState *vga, uint32_t addr) +{ + uint32_t offset = addr & vga->vbe_size_mask & ~1; + uint16_t *ptr = (uint16_t *)(vga->vram_ptr + offset); + return lduw_be_p(ptr); +} + +static inline uint32_t vga_read_dword_le(VGACommonState *vga, uint32_t addr) +{ + uint32_t offset = addr & vga->vbe_size_mask & ~3; + uint32_t *ptr = (uint32_t *)(vga->vram_ptr + offset); + return ldl_le_p(ptr); +} diff --git a/hw/display/vga-helpers.h b/hw/display/vga-helpers.h index 5a752b3f9e..10e9cfd40a 100644 --- a/hw/display/vga-helpers.h +++ b/hw/display/vga-helpers.h @@ -95,32 +95,6 @@ static void vga_draw_glyph9(uint8_t *d, int linesize, } while (--h); } -static inline uint8_t vga_read_byte(VGACommonState *vga, uint32_t addr) -{ - return vga->vram_ptr[addr & vga->vbe_size_mask]; -} - -static inline uint16_t vga_read_word_le(VGACommonState *vga, uint32_t addr) -{ - uint32_t offset = addr & vga->vbe_size_mask & ~1; - uint16_t *ptr = (uint16_t *)(vga->vram_ptr + offset); - return lduw_le_p(ptr); -} - -static inline uint16_t vga_read_word_be(VGACommonState *vga, uint32_t addr) -{ - uint32_t offset = addr & vga->vbe_size_mask & ~1; - uint16_t *ptr = (uint16_t *)(vga->vram_ptr + offset); - return lduw_be_p(ptr); -} - -static inline uint32_t vga_read_dword_le(VGACommonState *vga, uint32_t addr) -{ - uint32_t offset = addr & vga->vbe_size_mask & ~3; - uint32_t *ptr = (uint32_t *)(vga->vram_ptr + offset); - return ldl_le_p(ptr); -} - /* * 4 color mode */ diff --git a/hw/display/vga.c b/hw/display/vga.c index 573d223d46..82ebe53610 100644 --- a/hw/display/vga.c +++ b/hw/display/vga.c @@ -1009,6 +1009,7 @@ void vga_mem_writeb(VGACommonState *s, hwaddr addr, uint32_t val) typedef void vga_draw_line_func(VGACommonState *s1, uint8_t *d, uint32_t srcaddr, int width); +#include "vga-access.h" #include "vga-helpers.h" /* return true if the palette was modified */ diff --git a/hw/gpio/Makefile.objs b/hw/gpio/Makefile.objs index e5da0cb54f..d305b3b24b 100644 --- a/hw/gpio/Makefile.objs +++ b/hw/gpio/Makefile.objs @@ -9,3 +9,4 @@ obj-$(CONFIG_OMAP) += omap_gpio.o obj-$(CONFIG_IMX) += imx_gpio.o obj-$(CONFIG_RASPI) += bcm2835_gpio.o obj-$(CONFIG_NRF51_SOC) += nrf51_gpio.o +obj-$(CONFIG_ASPEED_SOC) += aspeed_gpio.o diff --git a/hw/gpio/aspeed_gpio.c b/hw/gpio/aspeed_gpio.c new file mode 100644 index 0000000000..25fbfec3b8 --- /dev/null +++ b/hw/gpio/aspeed_gpio.c @@ -0,0 +1,884 @@ +/* + * ASPEED GPIO Controller + * + * Copyright (C) 2017-2019 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include <assert.h> + +#include "qemu/osdep.h" +#include "qemu/host-utils.h" +#include "qemu/log.h" +#include "hw/gpio/aspeed_gpio.h" +#include "include/hw/misc/aspeed_scu.h" +#include "qapi/error.h" +#include "qapi/visitor.h" +#include "hw/irq.h" +#include "migration/vmstate.h" + +#define GPIOS_PER_REG 32 +#define GPIOS_PER_SET GPIOS_PER_REG +#define GPIO_PIN_GAP_SIZE 4 +#define GPIOS_PER_GROUP 8 +#define GPIO_GROUP_SHIFT 3 + +/* GPIO Source Types */ +#define ASPEED_CMD_SRC_MASK 0x01010101 +#define ASPEED_SOURCE_ARM 0 +#define ASPEED_SOURCE_LPC 1 +#define ASPEED_SOURCE_COPROCESSOR 2 +#define ASPEED_SOURCE_RESERVED 3 + +/* GPIO Interrupt Triggers */ +/* + * For each set of gpios there are three sensitivity registers that control + * the interrupt trigger mode. + * + * | 2 | 1 | 0 | trigger mode + * ----------------------------- + * | 0 | 0 | 0 | falling-edge + * | 0 | 0 | 1 | rising-edge + * | 0 | 1 | 0 | level-low + * | 0 | 1 | 1 | level-high + * | 1 | X | X | dual-edge + */ +#define ASPEED_FALLING_EDGE 0 +#define ASPEED_RISING_EDGE 1 +#define ASPEED_LEVEL_LOW 2 +#define ASPEED_LEVEL_HIGH 3 +#define ASPEED_DUAL_EDGE 4 + +/* GPIO Register Address Offsets */ +#define GPIO_ABCD_DATA_VALUE (0x000 >> 2) +#define GPIO_ABCD_DIRECTION (0x004 >> 2) +#define GPIO_ABCD_INT_ENABLE (0x008 >> 2) +#define GPIO_ABCD_INT_SENS_0 (0x00C >> 2) +#define GPIO_ABCD_INT_SENS_1 (0x010 >> 2) +#define GPIO_ABCD_INT_SENS_2 (0x014 >> 2) +#define GPIO_ABCD_INT_STATUS (0x018 >> 2) +#define GPIO_ABCD_RESET_TOLERANT (0x01C >> 2) +#define GPIO_EFGH_DATA_VALUE (0x020 >> 2) +#define GPIO_EFGH_DIRECTION (0x024 >> 2) +#define GPIO_EFGH_INT_ENABLE (0x028 >> 2) +#define GPIO_EFGH_INT_SENS_0 (0x02C >> 2) +#define GPIO_EFGH_INT_SENS_1 (0x030 >> 2) +#define GPIO_EFGH_INT_SENS_2 (0x034 >> 2) +#define GPIO_EFGH_INT_STATUS (0x038 >> 2) +#define GPIO_EFGH_RESET_TOLERANT (0x03C >> 2) +#define GPIO_ABCD_DEBOUNCE_1 (0x040 >> 2) +#define GPIO_ABCD_DEBOUNCE_2 (0x044 >> 2) +#define GPIO_EFGH_DEBOUNCE_1 (0x048 >> 2) +#define GPIO_EFGH_DEBOUNCE_2 (0x04C >> 2) +#define GPIO_DEBOUNCE_TIME_1 (0x050 >> 2) +#define GPIO_DEBOUNCE_TIME_2 (0x054 >> 2) +#define GPIO_DEBOUNCE_TIME_3 (0x058 >> 2) +#define GPIO_ABCD_COMMAND_SRC_0 (0x060 >> 2) +#define GPIO_ABCD_COMMAND_SRC_1 (0x064 >> 2) +#define GPIO_EFGH_COMMAND_SRC_0 (0x068 >> 2) +#define GPIO_EFGH_COMMAND_SRC_1 (0x06C >> 2) +#define GPIO_IJKL_DATA_VALUE (0x070 >> 2) +#define GPIO_IJKL_DIRECTION (0x074 >> 2) +#define GPIO_MNOP_DATA_VALUE (0x078 >> 2) +#define GPIO_MNOP_DIRECTION (0x07C >> 2) +#define GPIO_QRST_DATA_VALUE (0x080 >> 2) +#define GPIO_QRST_DIRECTION (0x084 >> 2) +#define GPIO_UVWX_DATA_VALUE (0x088 >> 2) +#define GPIO_UVWX_DIRECTION (0x08C >> 2) +#define GPIO_IJKL_COMMAND_SRC_0 (0x090 >> 2) +#define GPIO_IJKL_COMMAND_SRC_1 (0x094 >> 2) +#define GPIO_IJKL_INT_ENABLE (0x098 >> 2) +#define GPIO_IJKL_INT_SENS_0 (0x09C >> 2) +#define GPIO_IJKL_INT_SENS_1 (0x0A0 >> 2) +#define GPIO_IJKL_INT_SENS_2 (0x0A4 >> 2) +#define GPIO_IJKL_INT_STATUS (0x0A8 >> 2) +#define GPIO_IJKL_RESET_TOLERANT (0x0AC >> 2) +#define GPIO_IJKL_DEBOUNCE_1 (0x0B0 >> 2) +#define GPIO_IJKL_DEBOUNCE_2 (0x0B4 >> 2) +#define GPIO_IJKL_INPUT_MASK (0x0B8 >> 2) +#define GPIO_ABCD_DATA_READ (0x0C0 >> 2) +#define GPIO_EFGH_DATA_READ (0x0C4 >> 2) +#define GPIO_IJKL_DATA_READ (0x0C8 >> 2) +#define GPIO_MNOP_DATA_READ (0x0CC >> 2) +#define GPIO_QRST_DATA_READ (0x0D0 >> 2) +#define GPIO_UVWX_DATA_READ (0x0D4 >> 2) +#define GPIO_YZAAAB_DATA_READ (0x0D8 >> 2) +#define GPIO_AC_DATA_READ (0x0DC >> 2) +#define GPIO_MNOP_COMMAND_SRC_0 (0x0E0 >> 2) +#define GPIO_MNOP_COMMAND_SRC_1 (0x0E4 >> 2) +#define GPIO_MNOP_INT_ENABLE (0x0E8 >> 2) +#define GPIO_MNOP_INT_SENS_0 (0x0EC >> 2) +#define GPIO_MNOP_INT_SENS_1 (0x0F0 >> 2) +#define GPIO_MNOP_INT_SENS_2 (0x0F4 >> 2) +#define GPIO_MNOP_INT_STATUS (0x0F8 >> 2) +#define GPIO_MNOP_RESET_TOLERANT (0x0FC >> 2) +#define GPIO_MNOP_DEBOUNCE_1 (0x100 >> 2) +#define GPIO_MNOP_DEBOUNCE_2 (0x104 >> 2) +#define GPIO_MNOP_INPUT_MASK (0x108 >> 2) +#define GPIO_QRST_COMMAND_SRC_0 (0x110 >> 2) +#define GPIO_QRST_COMMAND_SRC_1 (0x114 >> 2) +#define GPIO_QRST_INT_ENABLE (0x118 >> 2) +#define GPIO_QRST_INT_SENS_0 (0x11C >> 2) +#define GPIO_QRST_INT_SENS_1 (0x120 >> 2) +#define GPIO_QRST_INT_SENS_2 (0x124 >> 2) +#define GPIO_QRST_INT_STATUS (0x128 >> 2) +#define GPIO_QRST_RESET_TOLERANT (0x12C >> 2) +#define GPIO_QRST_DEBOUNCE_1 (0x130 >> 2) +#define GPIO_QRST_DEBOUNCE_2 (0x134 >> 2) +#define GPIO_QRST_INPUT_MASK (0x138 >> 2) +#define GPIO_UVWX_COMMAND_SRC_0 (0x140 >> 2) +#define GPIO_UVWX_COMMAND_SRC_1 (0x144 >> 2) +#define GPIO_UVWX_INT_ENABLE (0x148 >> 2) +#define GPIO_UVWX_INT_SENS_0 (0x14C >> 2) +#define GPIO_UVWX_INT_SENS_1 (0x150 >> 2) +#define GPIO_UVWX_INT_SENS_2 (0x154 >> 2) +#define GPIO_UVWX_INT_STATUS (0x158 >> 2) +#define GPIO_UVWX_RESET_TOLERANT (0x15C >> 2) +#define GPIO_UVWX_DEBOUNCE_1 (0x160 >> 2) +#define GPIO_UVWX_DEBOUNCE_2 (0x164 >> 2) +#define GPIO_UVWX_INPUT_MASK (0x168 >> 2) +#define GPIO_YZAAAB_COMMAND_SRC_0 (0x170 >> 2) +#define GPIO_YZAAAB_COMMAND_SRC_1 (0x174 >> 2) +#define GPIO_YZAAAB_INT_ENABLE (0x178 >> 2) +#define GPIO_YZAAAB_INT_SENS_0 (0x17C >> 2) +#define GPIO_YZAAAB_INT_SENS_1 (0x180 >> 2) +#define GPIO_YZAAAB_INT_SENS_2 (0x184 >> 2) +#define GPIO_YZAAAB_INT_STATUS (0x188 >> 2) +#define GPIO_YZAAAB_RESET_TOLERANT (0x18C >> 2) +#define GPIO_YZAAAB_DEBOUNCE_1 (0x190 >> 2) +#define GPIO_YZAAAB_DEBOUNCE_2 (0x194 >> 2) +#define GPIO_YZAAAB_INPUT_MASK (0x198 >> 2) +#define GPIO_AC_COMMAND_SRC_0 (0x1A0 >> 2) +#define GPIO_AC_COMMAND_SRC_1 (0x1A4 >> 2) +#define GPIO_AC_INT_ENABLE (0x1A8 >> 2) +#define GPIO_AC_INT_SENS_0 (0x1AC >> 2) +#define GPIO_AC_INT_SENS_1 (0x1B0 >> 2) +#define GPIO_AC_INT_SENS_2 (0x1B4 >> 2) +#define GPIO_AC_INT_STATUS (0x1B8 >> 2) +#define GPIO_AC_RESET_TOLERANT (0x1BC >> 2) +#define GPIO_AC_DEBOUNCE_1 (0x1C0 >> 2) +#define GPIO_AC_DEBOUNCE_2 (0x1C4 >> 2) +#define GPIO_AC_INPUT_MASK (0x1C8 >> 2) +#define GPIO_ABCD_INPUT_MASK (0x1D0 >> 2) +#define GPIO_EFGH_INPUT_MASK (0x1D4 >> 2) +#define GPIO_YZAAAB_DATA_VALUE (0x1E0 >> 2) +#define GPIO_YZAAAB_DIRECTION (0x1E4 >> 2) +#define GPIO_AC_DATA_VALUE (0x1E8 >> 2) +#define GPIO_AC_DIRECTION (0x1EC >> 2) +#define GPIO_3_6V_MEM_SIZE 0x1F0 +#define GPIO_3_6V_REG_ARRAY_SIZE (GPIO_3_6V_MEM_SIZE >> 2) + +static int aspeed_evaluate_irq(GPIOSets *regs, int gpio_prev_high, int gpio) +{ + uint32_t falling_edge = 0, rising_edge = 0; + uint32_t int_trigger = extract32(regs->int_sens_0, gpio, 1) + | extract32(regs->int_sens_1, gpio, 1) << 1 + | extract32(regs->int_sens_2, gpio, 1) << 2; + uint32_t gpio_curr_high = extract32(regs->data_value, gpio, 1); + uint32_t gpio_int_enabled = extract32(regs->int_enable, gpio, 1); + + if (!gpio_int_enabled) { + return 0; + } + + /* Detect edges */ + if (gpio_curr_high && !gpio_prev_high) { + rising_edge = 1; + } else if (!gpio_curr_high && gpio_prev_high) { + falling_edge = 1; + } + + if (((int_trigger == ASPEED_FALLING_EDGE) && falling_edge) || + ((int_trigger == ASPEED_RISING_EDGE) && rising_edge) || + ((int_trigger == ASPEED_LEVEL_LOW) && !gpio_curr_high) || + ((int_trigger == ASPEED_LEVEL_HIGH) && gpio_curr_high) || + ((int_trigger >= ASPEED_DUAL_EDGE) && (rising_edge || falling_edge))) + { + regs->int_status = deposit32(regs->int_status, gpio, 1, 1); + return 1; + } + return 0; +} + +#define nested_struct_index(ta, pa, m, tb, pb) \ + (pb - ((tb *)(((char *)pa) + offsetof(ta, m)))) + +static ptrdiff_t aspeed_gpio_set_idx(AspeedGPIOState *s, GPIOSets *regs) +{ + return nested_struct_index(AspeedGPIOState, s, sets, GPIOSets, regs); +} + +static void aspeed_gpio_update(AspeedGPIOState *s, GPIOSets *regs, + uint32_t value) +{ + uint32_t input_mask = regs->input_mask; + uint32_t direction = regs->direction; + uint32_t old = regs->data_value; + uint32_t new = value; + uint32_t diff; + int gpio; + + diff = old ^ new; + if (diff) { + for (gpio = 0; gpio < GPIOS_PER_REG; gpio++) { + uint32_t mask = 1 << gpio; + + /* If the gpio needs to be updated... */ + if (!(diff & mask)) { + continue; + } + + /* ...and we're output or not input-masked... */ + if (!(direction & mask) && (input_mask & mask)) { + continue; + } + + /* ...then update the state. */ + if (mask & new) { + regs->data_value |= mask; + } else { + regs->data_value &= ~mask; + } + + /* If the gpio is set to output... */ + if (direction & mask) { + /* ...trigger the line-state IRQ */ + ptrdiff_t set = aspeed_gpio_set_idx(s, regs); + size_t offset = set * GPIOS_PER_SET + gpio; + qemu_set_irq(s->gpios[offset], !!(new & mask)); + } else { + /* ...otherwise if we meet the line's current IRQ policy... */ + if (aspeed_evaluate_irq(regs, old & mask, gpio)) { + /* ...trigger the VIC IRQ */ + s->pending++; + } + } + } + } + qemu_set_irq(s->irq, !!(s->pending)); +} + +static uint32_t aspeed_adjust_pin(AspeedGPIOState *s, uint32_t pin) +{ + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + /* + * The 2500 has a 4 pin gap in group AB and the 2400 has a 4 pin + * gap in group Y (and only four pins in AB but this is the last group so + * it doesn't matter). + */ + if (agc->gap && pin >= agc->gap) { + pin += GPIO_PIN_GAP_SIZE; + } + + return pin; +} + +static bool aspeed_gpio_get_pin_level(AspeedGPIOState *s, uint32_t set_idx, + uint32_t pin) +{ + uint32_t reg_val; + uint32_t pin_mask = 1 << pin; + + reg_val = s->sets[set_idx].data_value; + + return !!(reg_val & pin_mask); +} + +static void aspeed_gpio_set_pin_level(AspeedGPIOState *s, uint32_t set_idx, + uint32_t pin, bool level) +{ + uint32_t value = s->sets[set_idx].data_value; + uint32_t pin_mask = 1 << pin; + + if (level) { + value |= pin_mask; + } else { + value &= !pin_mask; + } + + aspeed_gpio_update(s, &s->sets[set_idx], value); +} + +/* + * | src_1 | src_2 | source | + * |-----------------------------| + * | 0 | 0 | ARM | + * | 0 | 1 | LPC | + * | 1 | 0 | Coprocessor| + * | 1 | 1 | Reserved | + * + * Once the source of a set is programmed, corresponding bits in the + * data_value, direction, interrupt [enable, sens[0-2]], reset_tol and + * debounce registers can only be written by the source. + * + * Source is ARM by default + * only bits 24, 16, 8, and 0 can be set + * + * we don't currently have a model for the LPC or Coprocessor + */ +static uint32_t update_value_control_source(GPIOSets *regs, uint32_t old_value, + uint32_t value) +{ + int i; + int cmd_source; + + /* assume the source is always ARM for now */ + int source = ASPEED_SOURCE_ARM; + + uint32_t new_value = 0; + + /* for each group in set */ + for (i = 0; i < GPIOS_PER_REG; i += GPIOS_PER_GROUP) { + cmd_source = extract32(regs->cmd_source_0, i, 1) + | (extract32(regs->cmd_source_1, i, 1) << 1); + + if (source == cmd_source) { + new_value |= (0xff << i) & value; + } else { + new_value |= (0xff << i) & old_value; + } + } + return new_value; +} + +static const AspeedGPIOReg aspeed_3_6v_gpios[GPIO_3_6V_REG_ARRAY_SIZE] = { + /* Set ABCD */ + [GPIO_ABCD_DATA_VALUE] = { 0, gpio_reg_data_value }, + [GPIO_ABCD_DIRECTION] = { 0, gpio_reg_direction }, + [GPIO_ABCD_INT_ENABLE] = { 0, gpio_reg_int_enable }, + [GPIO_ABCD_INT_SENS_0] = { 0, gpio_reg_int_sens_0 }, + [GPIO_ABCD_INT_SENS_1] = { 0, gpio_reg_int_sens_1 }, + [GPIO_ABCD_INT_SENS_2] = { 0, gpio_reg_int_sens_2 }, + [GPIO_ABCD_INT_STATUS] = { 0, gpio_reg_int_status }, + [GPIO_ABCD_RESET_TOLERANT] = { 0, gpio_reg_reset_tolerant }, + [GPIO_ABCD_DEBOUNCE_1] = { 0, gpio_reg_debounce_1 }, + [GPIO_ABCD_DEBOUNCE_2] = { 0, gpio_reg_debounce_2 }, + [GPIO_ABCD_COMMAND_SRC_0] = { 0, gpio_reg_cmd_source_0 }, + [GPIO_ABCD_COMMAND_SRC_1] = { 0, gpio_reg_cmd_source_1 }, + [GPIO_ABCD_DATA_READ] = { 0, gpio_reg_data_read }, + [GPIO_ABCD_INPUT_MASK] = { 0, gpio_reg_input_mask }, + /* Set EFGH */ + [GPIO_EFGH_DATA_VALUE] = { 1, gpio_reg_data_value }, + [GPIO_EFGH_DIRECTION] = { 1, gpio_reg_direction }, + [GPIO_EFGH_INT_ENABLE] = { 1, gpio_reg_int_enable }, + [GPIO_EFGH_INT_SENS_0] = { 1, gpio_reg_int_sens_0 }, + [GPIO_EFGH_INT_SENS_1] = { 1, gpio_reg_int_sens_1 }, + [GPIO_EFGH_INT_SENS_2] = { 1, gpio_reg_int_sens_2 }, + [GPIO_EFGH_INT_STATUS] = { 1, gpio_reg_int_status }, + [GPIO_EFGH_RESET_TOLERANT] = { 1, gpio_reg_reset_tolerant }, + [GPIO_EFGH_DEBOUNCE_1] = { 1, gpio_reg_debounce_1 }, + [GPIO_EFGH_DEBOUNCE_2] = { 1, gpio_reg_debounce_2 }, + [GPIO_EFGH_COMMAND_SRC_0] = { 1, gpio_reg_cmd_source_0 }, + [GPIO_EFGH_COMMAND_SRC_1] = { 1, gpio_reg_cmd_source_1 }, + [GPIO_EFGH_DATA_READ] = { 1, gpio_reg_data_read }, + [GPIO_EFGH_INPUT_MASK] = { 1, gpio_reg_input_mask }, + /* Set IJKL */ + [GPIO_IJKL_DATA_VALUE] = { 2, gpio_reg_data_value }, + [GPIO_IJKL_DIRECTION] = { 2, gpio_reg_direction }, + [GPIO_IJKL_INT_ENABLE] = { 2, gpio_reg_int_enable }, + [GPIO_IJKL_INT_SENS_0] = { 2, gpio_reg_int_sens_0 }, + [GPIO_IJKL_INT_SENS_1] = { 2, gpio_reg_int_sens_1 }, + [GPIO_IJKL_INT_SENS_2] = { 2, gpio_reg_int_sens_2 }, + [GPIO_IJKL_INT_STATUS] = { 2, gpio_reg_int_status }, + [GPIO_IJKL_RESET_TOLERANT] = { 2, gpio_reg_reset_tolerant }, + [GPIO_IJKL_DEBOUNCE_1] = { 2, gpio_reg_debounce_1 }, + [GPIO_IJKL_DEBOUNCE_2] = { 2, gpio_reg_debounce_2 }, + [GPIO_IJKL_COMMAND_SRC_0] = { 2, gpio_reg_cmd_source_0 }, + [GPIO_IJKL_COMMAND_SRC_1] = { 2, gpio_reg_cmd_source_1 }, + [GPIO_IJKL_DATA_READ] = { 2, gpio_reg_data_read }, + [GPIO_IJKL_INPUT_MASK] = { 2, gpio_reg_input_mask }, + /* Set MNOP */ + [GPIO_MNOP_DATA_VALUE] = { 3, gpio_reg_data_value }, + [GPIO_MNOP_DIRECTION] = { 3, gpio_reg_direction }, + [GPIO_MNOP_INT_ENABLE] = { 3, gpio_reg_int_enable }, + [GPIO_MNOP_INT_SENS_0] = { 3, gpio_reg_int_sens_0 }, + [GPIO_MNOP_INT_SENS_1] = { 3, gpio_reg_int_sens_1 }, + [GPIO_MNOP_INT_SENS_2] = { 3, gpio_reg_int_sens_2 }, + [GPIO_MNOP_INT_STATUS] = { 3, gpio_reg_int_status }, + [GPIO_MNOP_RESET_TOLERANT] = { 3, gpio_reg_reset_tolerant }, + [GPIO_MNOP_DEBOUNCE_1] = { 3, gpio_reg_debounce_1 }, + [GPIO_MNOP_DEBOUNCE_2] = { 3, gpio_reg_debounce_2 }, + [GPIO_MNOP_COMMAND_SRC_0] = { 3, gpio_reg_cmd_source_0 }, + [GPIO_MNOP_COMMAND_SRC_1] = { 3, gpio_reg_cmd_source_1 }, + [GPIO_MNOP_DATA_READ] = { 3, gpio_reg_data_read }, + [GPIO_MNOP_INPUT_MASK] = { 3, gpio_reg_input_mask }, + /* Set QRST */ + [GPIO_QRST_DATA_VALUE] = { 4, gpio_reg_data_value }, + [GPIO_QRST_DIRECTION] = { 4, gpio_reg_direction }, + [GPIO_QRST_INT_ENABLE] = { 4, gpio_reg_int_enable }, + [GPIO_QRST_INT_SENS_0] = { 4, gpio_reg_int_sens_0 }, + [GPIO_QRST_INT_SENS_1] = { 4, gpio_reg_int_sens_1 }, + [GPIO_QRST_INT_SENS_2] = { 4, gpio_reg_int_sens_2 }, + [GPIO_QRST_INT_STATUS] = { 4, gpio_reg_int_status }, + [GPIO_QRST_RESET_TOLERANT] = { 4, gpio_reg_reset_tolerant }, + [GPIO_QRST_DEBOUNCE_1] = { 4, gpio_reg_debounce_1 }, + [GPIO_QRST_DEBOUNCE_2] = { 4, gpio_reg_debounce_2 }, + [GPIO_QRST_COMMAND_SRC_0] = { 4, gpio_reg_cmd_source_0 }, + [GPIO_QRST_COMMAND_SRC_1] = { 4, gpio_reg_cmd_source_1 }, + [GPIO_QRST_DATA_READ] = { 4, gpio_reg_data_read }, + [GPIO_QRST_INPUT_MASK] = { 4, gpio_reg_input_mask }, + /* Set UVWX */ + [GPIO_UVWX_DATA_VALUE] = { 5, gpio_reg_data_value }, + [GPIO_UVWX_DIRECTION] = { 5, gpio_reg_direction }, + [GPIO_UVWX_INT_ENABLE] = { 5, gpio_reg_int_enable }, + [GPIO_UVWX_INT_SENS_0] = { 5, gpio_reg_int_sens_0 }, + [GPIO_UVWX_INT_SENS_1] = { 5, gpio_reg_int_sens_1 }, + [GPIO_UVWX_INT_SENS_2] = { 5, gpio_reg_int_sens_2 }, + [GPIO_UVWX_INT_STATUS] = { 5, gpio_reg_int_status }, + [GPIO_UVWX_RESET_TOLERANT] = { 5, gpio_reg_reset_tolerant }, + [GPIO_UVWX_DEBOUNCE_1] = { 5, gpio_reg_debounce_1 }, + [GPIO_UVWX_DEBOUNCE_2] = { 5, gpio_reg_debounce_2 }, + [GPIO_UVWX_COMMAND_SRC_0] = { 5, gpio_reg_cmd_source_0 }, + [GPIO_UVWX_COMMAND_SRC_1] = { 5, gpio_reg_cmd_source_1 }, + [GPIO_UVWX_DATA_READ] = { 5, gpio_reg_data_read }, + [GPIO_UVWX_INPUT_MASK] = { 5, gpio_reg_input_mask }, + /* Set YZAAAB */ + [GPIO_YZAAAB_DATA_VALUE] = { 6, gpio_reg_data_value }, + [GPIO_YZAAAB_DIRECTION] = { 6, gpio_reg_direction }, + [GPIO_YZAAAB_INT_ENABLE] = { 6, gpio_reg_int_enable }, + [GPIO_YZAAAB_INT_SENS_0] = { 6, gpio_reg_int_sens_0 }, + [GPIO_YZAAAB_INT_SENS_1] = { 6, gpio_reg_int_sens_1 }, + [GPIO_YZAAAB_INT_SENS_2] = { 6, gpio_reg_int_sens_2 }, + [GPIO_YZAAAB_INT_STATUS] = { 6, gpio_reg_int_status }, + [GPIO_YZAAAB_RESET_TOLERANT] = { 6, gpio_reg_reset_tolerant }, + [GPIO_YZAAAB_DEBOUNCE_1] = { 6, gpio_reg_debounce_1 }, + [GPIO_YZAAAB_DEBOUNCE_2] = { 6, gpio_reg_debounce_2 }, + [GPIO_YZAAAB_COMMAND_SRC_0] = { 6, gpio_reg_cmd_source_0 }, + [GPIO_YZAAAB_COMMAND_SRC_1] = { 6, gpio_reg_cmd_source_1 }, + [GPIO_YZAAAB_DATA_READ] = { 6, gpio_reg_data_read }, + [GPIO_YZAAAB_INPUT_MASK] = { 6, gpio_reg_input_mask }, + /* Set AC (ast2500 only) */ + [GPIO_AC_DATA_VALUE] = { 7, gpio_reg_data_value }, + [GPIO_AC_DIRECTION] = { 7, gpio_reg_direction }, + [GPIO_AC_INT_ENABLE] = { 7, gpio_reg_int_enable }, + [GPIO_AC_INT_SENS_0] = { 7, gpio_reg_int_sens_0 }, + [GPIO_AC_INT_SENS_1] = { 7, gpio_reg_int_sens_1 }, + [GPIO_AC_INT_SENS_2] = { 7, gpio_reg_int_sens_2 }, + [GPIO_AC_INT_STATUS] = { 7, gpio_reg_int_status }, + [GPIO_AC_RESET_TOLERANT] = { 7, gpio_reg_reset_tolerant }, + [GPIO_AC_DEBOUNCE_1] = { 7, gpio_reg_debounce_1 }, + [GPIO_AC_DEBOUNCE_2] = { 7, gpio_reg_debounce_2 }, + [GPIO_AC_COMMAND_SRC_0] = { 7, gpio_reg_cmd_source_0 }, + [GPIO_AC_COMMAND_SRC_1] = { 7, gpio_reg_cmd_source_1 }, + [GPIO_AC_DATA_READ] = { 7, gpio_reg_data_read }, + [GPIO_AC_INPUT_MASK] = { 7, gpio_reg_input_mask }, +}; + +static uint64_t aspeed_gpio_read(void *opaque, hwaddr offset, uint32_t size) +{ + AspeedGPIOState *s = ASPEED_GPIO(opaque); + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + uint64_t idx = -1; + const AspeedGPIOReg *reg; + GPIOSets *set; + + idx = offset >> 2; + if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { + idx -= GPIO_DEBOUNCE_TIME_1; + return (uint64_t) s->debounce_regs[idx]; + } + + reg = &agc->reg_table[idx]; + if (reg->set_idx >= agc->nr_gpio_sets) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return 0; + } + + set = &s->sets[reg->set_idx]; + switch (reg->type) { + case gpio_reg_data_value: + return set->data_value; + case gpio_reg_direction: + return set->direction; + case gpio_reg_int_enable: + return set->int_enable; + case gpio_reg_int_sens_0: + return set->int_sens_0; + case gpio_reg_int_sens_1: + return set->int_sens_1; + case gpio_reg_int_sens_2: + return set->int_sens_2; + case gpio_reg_int_status: + return set->int_status; + case gpio_reg_reset_tolerant: + return set->reset_tol; + case gpio_reg_debounce_1: + return set->debounce_1; + case gpio_reg_debounce_2: + return set->debounce_2; + case gpio_reg_cmd_source_0: + return set->cmd_source_0; + case gpio_reg_cmd_source_1: + return set->cmd_source_1; + case gpio_reg_data_read: + return set->data_read; + case gpio_reg_input_mask: + return set->input_mask; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no getter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return 0; + }; +} + +static void aspeed_gpio_write(void *opaque, hwaddr offset, uint64_t data, + uint32_t size) +{ + AspeedGPIOState *s = ASPEED_GPIO(opaque); + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + const GPIOSetProperties *props; + uint64_t idx = -1; + const AspeedGPIOReg *reg; + GPIOSets *set; + uint32_t cleared; + + idx = offset >> 2; + if (idx >= GPIO_DEBOUNCE_TIME_1 && idx <= GPIO_DEBOUNCE_TIME_3) { + idx -= GPIO_DEBOUNCE_TIME_1; + s->debounce_regs[idx] = (uint32_t) data; + return; + } + + reg = &agc->reg_table[idx]; + if (reg->set_idx >= agc->nr_gpio_sets) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return; + } + + set = &s->sets[reg->set_idx]; + props = &agc->props[reg->set_idx]; + + switch (reg->type) { + case gpio_reg_data_value: + data &= props->output; + data = update_value_control_source(set, set->data_value, data); + set->data_read = data; + aspeed_gpio_update(s, set, data); + return; + case gpio_reg_direction: + /* + * where data is the value attempted to be written to the pin: + * pin type | input mask | output mask | expected value + * ------------------------------------------------------------ + * bidirectional | 1 | 1 | data + * input only | 1 | 0 | 0 + * output only | 0 | 1 | 1 + * no pin / gap | 0 | 0 | 0 + * + * which is captured by: + * data = ( data | ~input) & output; + */ + data = (data | ~props->input) & props->output; + set->direction = update_value_control_source(set, set->direction, data); + break; + case gpio_reg_int_enable: + set->int_enable = update_value_control_source(set, set->int_enable, + data); + break; + case gpio_reg_int_sens_0: + set->int_sens_0 = update_value_control_source(set, set->int_sens_0, + data); + break; + case gpio_reg_int_sens_1: + set->int_sens_1 = update_value_control_source(set, set->int_sens_1, + data); + break; + case gpio_reg_int_sens_2: + set->int_sens_2 = update_value_control_source(set, set->int_sens_2, + data); + break; + case gpio_reg_int_status: + cleared = ctpop32(data & set->int_status); + if (s->pending && cleared) { + assert(s->pending >= cleared); + s->pending -= cleared; + } + set->int_status &= ~data; + break; + case gpio_reg_reset_tolerant: + set->reset_tol = update_value_control_source(set, set->reset_tol, + data); + return; + case gpio_reg_debounce_1: + set->debounce_1 = update_value_control_source(set, set->debounce_1, + data); + return; + case gpio_reg_debounce_2: + set->debounce_2 = update_value_control_source(set, set->debounce_2, + data); + return; + case gpio_reg_cmd_source_0: + set->cmd_source_0 = data & ASPEED_CMD_SRC_MASK; + return; + case gpio_reg_cmd_source_1: + set->cmd_source_1 = data & ASPEED_CMD_SRC_MASK; + return; + case gpio_reg_data_read: + /* Read only register */ + return; + case gpio_reg_input_mask: + /* + * feeds into interrupt generation + * 0: read from data value reg will be updated + * 1: read from data value reg will not be updated + */ + set->input_mask = data & props->input; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: no setter for offset 0x%" + HWADDR_PRIx"\n", __func__, offset); + return; + } + aspeed_gpio_update(s, set, set->data_value); + return; +} + +static int get_set_idx(AspeedGPIOState *s, const char *group, int *group_idx) +{ + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + int set_idx, g_idx = *group_idx; + + for (set_idx = 0; set_idx < agc->nr_gpio_sets; set_idx++) { + const GPIOSetProperties *set_props = &agc->props[set_idx]; + for (g_idx = 0; g_idx < ASPEED_GROUPS_PER_SET; g_idx++) { + if (!strncmp(group, set_props->group_label[g_idx], strlen(group))) { + *group_idx = g_idx; + return set_idx; + } + } + } + return -1; +} + +static void aspeed_gpio_get_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + int pin = 0xfff; + bool level = true; + char group[3]; + AspeedGPIOState *s = ASPEED_GPIO(obj); + int set_idx, group_idx = 0; + + if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + set_idx = get_set_idx(s, group, &group_idx); + if (set_idx == -1) { + error_setg(errp, "%s: invalid group %s", __func__, group); + return; + } + pin = pin + group_idx * GPIOS_PER_GROUP; + level = aspeed_gpio_get_pin_level(s, set_idx, pin); + visit_type_bool(v, name, &level, errp); +} + +static void aspeed_gpio_set_pin(Object *obj, Visitor *v, const char *name, + void *opaque, Error **errp) +{ + Error *local_err = NULL; + bool level; + int pin = 0xfff; + char group[3]; + AspeedGPIOState *s = ASPEED_GPIO(obj); + int set_idx, group_idx = 0; + + visit_type_bool(v, name, &level, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } + if (sscanf(name, "gpio%2[A-Z]%1d", group, &pin) != 2) { + error_setg(errp, "%s: error reading %s", __func__, name); + return; + } + set_idx = get_set_idx(s, group, &group_idx); + if (set_idx == -1) { + error_setg(errp, "%s: invalid group %s", __func__, group); + return; + } + pin = pin + group_idx * GPIOS_PER_GROUP; + aspeed_gpio_set_pin_level(s, set_idx, pin, level); +} + +/****************** Setup functions ******************/ +static const GPIOSetProperties ast2400_set_props[] = { + [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, + [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, + [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, + [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, + [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, + [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, + [6] = {0x0000000f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, +}; + +static const GPIOSetProperties ast2500_set_props[] = { + [0] = {0xffffffff, 0xffffffff, {"A", "B", "C", "D"} }, + [1] = {0xffffffff, 0xffffffff, {"E", "F", "G", "H"} }, + [2] = {0xffffffff, 0xffffffff, {"I", "J", "K", "L"} }, + [3] = {0xffffffff, 0xffffffff, {"M", "N", "O", "P"} }, + [4] = {0xffffffff, 0xffffffff, {"Q", "R", "S", "T"} }, + [5] = {0xffffffff, 0x0000ffff, {"U", "V", "W", "X"} }, + [6] = {0xffffff0f, 0x0fffff0f, {"Y", "Z", "AA", "AB"} }, + [7] = {0x000000ff, 0x000000ff, {"AC"} }, +}; + +static const MemoryRegionOps aspeed_gpio_ops = { + .read = aspeed_gpio_read, + .write = aspeed_gpio_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid.min_access_size = 4, + .valid.max_access_size = 4, +}; + +static void aspeed_gpio_reset(DeviceState *dev) +{ + AspeedGPIOState *s = ASPEED_GPIO(dev); + + /* TODO: respect the reset tolerance registers */ + memset(s->sets, 0, sizeof(s->sets)); +} + +static void aspeed_gpio_realize(DeviceState *dev, Error **errp) +{ + AspeedGPIOState *s = ASPEED_GPIO(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + int pin; + + /* Interrupt parent line */ + sysbus_init_irq(sbd, &s->irq); + + /* Individual GPIOs */ + for (pin = 0; pin < agc->nr_gpio_pins; pin++) { + sysbus_init_irq(sbd, &s->gpios[pin]); + } + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_gpio_ops, s, + TYPE_ASPEED_GPIO, GPIO_3_6V_MEM_SIZE); + + sysbus_init_mmio(sbd, &s->iomem); +} + +static void aspeed_gpio_init(Object *obj) +{ + AspeedGPIOState *s = ASPEED_GPIO(obj); + AspeedGPIOClass *agc = ASPEED_GPIO_GET_CLASS(s); + int pin; + + for (pin = 0; pin < agc->nr_gpio_pins; pin++) { + char *name; + int set_idx = pin / GPIOS_PER_SET; + int pin_idx = aspeed_adjust_pin(s, pin) - (set_idx * GPIOS_PER_SET); + int group_idx = pin_idx >> GPIO_GROUP_SHIFT; + const GPIOSetProperties *props = &agc->props[set_idx]; + + name = g_strdup_printf("gpio%s%d", props->group_label[group_idx], + pin_idx % GPIOS_PER_GROUP); + object_property_add(obj, name, "bool", aspeed_gpio_get_pin, + aspeed_gpio_set_pin, NULL, NULL, NULL); + } +} + +static const VMStateDescription vmstate_gpio_regs = { + .name = TYPE_ASPEED_GPIO"/regs", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(data_value, GPIOSets), + VMSTATE_UINT32(data_read, GPIOSets), + VMSTATE_UINT32(direction, GPIOSets), + VMSTATE_UINT32(int_enable, GPIOSets), + VMSTATE_UINT32(int_sens_0, GPIOSets), + VMSTATE_UINT32(int_sens_1, GPIOSets), + VMSTATE_UINT32(int_sens_2, GPIOSets), + VMSTATE_UINT32(int_status, GPIOSets), + VMSTATE_UINT32(reset_tol, GPIOSets), + VMSTATE_UINT32(cmd_source_0, GPIOSets), + VMSTATE_UINT32(cmd_source_1, GPIOSets), + VMSTATE_UINT32(debounce_1, GPIOSets), + VMSTATE_UINT32(debounce_2, GPIOSets), + VMSTATE_UINT32(input_mask, GPIOSets), + VMSTATE_END_OF_LIST(), + } +}; + +static const VMStateDescription vmstate_aspeed_gpio = { + .name = TYPE_ASPEED_GPIO, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_STRUCT_ARRAY(sets, AspeedGPIOState, ASPEED_GPIO_MAX_NR_SETS, + 1, vmstate_gpio_regs, GPIOSets), + VMSTATE_UINT32_ARRAY(debounce_regs, AspeedGPIOState, + ASPEED_GPIO_NR_DEBOUNCE_REGS), + VMSTATE_END_OF_LIST(), + } +}; + +static void aspeed_gpio_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = aspeed_gpio_realize; + dc->reset = aspeed_gpio_reset; + dc->desc = "Aspeed GPIO Controller"; + dc->vmsd = &vmstate_aspeed_gpio; +} + +static void aspeed_gpio_ast2400_class_init(ObjectClass *klass, void *data) +{ + AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); + + agc->props = ast2400_set_props; + agc->nr_gpio_pins = 216; + agc->nr_gpio_sets = 7; + agc->gap = 196; + agc->reg_table = aspeed_3_6v_gpios; +} + +static void aspeed_gpio_2500_class_init(ObjectClass *klass, void *data) +{ + AspeedGPIOClass *agc = ASPEED_GPIO_CLASS(klass); + + agc->props = ast2500_set_props; + agc->nr_gpio_pins = 228; + agc->nr_gpio_sets = 8; + agc->gap = 220; + agc->reg_table = aspeed_3_6v_gpios; +} + +static const TypeInfo aspeed_gpio_info = { + .name = TYPE_ASPEED_GPIO, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AspeedGPIOState), + .class_size = sizeof(AspeedGPIOClass), + .class_init = aspeed_gpio_class_init, + .abstract = true, +}; + +static const TypeInfo aspeed_gpio_ast2400_info = { + .name = TYPE_ASPEED_GPIO "-ast2400", + .parent = TYPE_ASPEED_GPIO, + .class_init = aspeed_gpio_ast2400_class_init, + .instance_init = aspeed_gpio_init, +}; + +static const TypeInfo aspeed_gpio_ast2500_info = { + .name = TYPE_ASPEED_GPIO "-ast2500", + .parent = TYPE_ASPEED_GPIO, + .class_init = aspeed_gpio_2500_class_init, + .instance_init = aspeed_gpio_init, +}; + +static void aspeed_gpio_register_types(void) +{ + type_register_static(&aspeed_gpio_info); + type_register_static(&aspeed_gpio_ast2400_info); + type_register_static(&aspeed_gpio_ast2500_info); +} + +type_init(aspeed_gpio_register_types); diff --git a/hw/i386/Kconfig b/hw/i386/Kconfig index 6350438036..c7a9d6315c 100644 --- a/hw/i386/Kconfig +++ b/hw/i386/Kconfig @@ -29,6 +29,7 @@ config PC select MC146818RTC # For ACPI builder: select SERIAL_ISA + select ACPI_PCI select ACPI_VMGENID select VIRTIO_PMEM_SUPPORTED diff --git a/hw/i386/Makefile.objs b/hw/i386/Makefile.objs index 5d9c9efd5f..d3374e0831 100644 --- a/hw/i386/Makefile.objs +++ b/hw/i386/Makefile.objs @@ -1,5 +1,5 @@ obj-$(CONFIG_KVM) += kvm/ -obj-y += multiboot.o +obj-y += e820_memory_layout.o multiboot.o obj-y += pc.o obj-$(CONFIG_I440FX) += pc_piix.o obj-$(CONFIG_Q35) += pc_q35.o diff --git a/hw/i386/e820_memory_layout.c b/hw/i386/e820_memory_layout.c new file mode 100644 index 0000000000..bcf9eaf837 --- /dev/null +++ b/hw/i386/e820_memory_layout.c @@ -0,0 +1,59 @@ +/* + * QEMU BIOS e820 routines + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * SPDX-License-Identifier: MIT + */ + +#include "qemu/osdep.h" +#include "qemu/bswap.h" +#include "e820_memory_layout.h" + +static size_t e820_entries; +struct e820_table e820_reserve; +struct e820_entry *e820_table; + +int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) +{ + int index = le32_to_cpu(e820_reserve.count); + struct e820_entry *entry; + + if (type != E820_RAM) { + /* old FW_CFG_E820_TABLE entry -- reservations only */ + if (index >= E820_NR_ENTRIES) { + return -EBUSY; + } + entry = &e820_reserve.entry[index++]; + + entry->address = cpu_to_le64(address); + entry->length = cpu_to_le64(length); + entry->type = cpu_to_le32(type); + + e820_reserve.count = cpu_to_le32(index); + } + + /* new "etc/e820" file -- include ram too */ + e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); + e820_table[e820_entries].address = cpu_to_le64(address); + e820_table[e820_entries].length = cpu_to_le64(length); + e820_table[e820_entries].type = cpu_to_le32(type); + e820_entries++; + + return e820_entries; +} + +int e820_get_num_entries(void) +{ + return e820_entries; +} + +bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) +{ + if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { + *address = le64_to_cpu(e820_table[idx].address); + *length = le64_to_cpu(e820_table[idx].length); + return true; + } + return false; +} diff --git a/hw/i386/e820_memory_layout.h b/hw/i386/e820_memory_layout.h new file mode 100644 index 0000000000..2a0ceb8b9c --- /dev/null +++ b/hw/i386/e820_memory_layout.h @@ -0,0 +1,42 @@ +/* + * QEMU BIOS e820 routines + * + * Copyright (c) 2003-2004 Fabrice Bellard + * + * SPDX-License-Identifier: MIT + */ + +#ifndef HW_I386_E820_H +#define HW_I386_E820_H + +/* e820 types */ +#define E820_RAM 1 +#define E820_RESERVED 2 +#define E820_ACPI 3 +#define E820_NVS 4 +#define E820_UNUSABLE 5 + +#define E820_NR_ENTRIES 16 + +struct e820_entry { + uint64_t address; + uint64_t length; + uint32_t type; +} QEMU_PACKED __attribute((__aligned__(4))); + +struct e820_table { + uint32_t count; + struct e820_entry entry[E820_NR_ENTRIES]; +} QEMU_PACKED __attribute((__aligned__(4))); + +extern struct e820_table e820_reserve; +extern struct e820_entry *e820_table; + +int e820_add_entry(uint64_t address, uint64_t length, uint32_t type); +int e820_get_num_entries(void); +bool e820_get_entry(int index, uint32_t type, + uint64_t *address, uint64_t *length); + + + +#endif diff --git a/hw/i386/fw_cfg.c b/hw/i386/fw_cfg.c index 380a819230..39b6bc6052 100644 --- a/hw/i386/fw_cfg.c +++ b/hw/i386/fw_cfg.c @@ -13,8 +13,15 @@ */ #include "qemu/osdep.h" +#include "sysemu/numa.h" +#include "hw/acpi/acpi.h" +#include "hw/firmware/smbios.h" +#include "hw/i386/pc.h" #include "hw/i386/fw_cfg.h" +#include "hw/timer/hpet.h" #include "hw/nvram/fw_cfg.h" +#include "e820_memory_layout.h" +#include "kvm_i386.h" const char *fw_cfg_arch_key_name(uint16_t key) { @@ -36,3 +43,133 @@ const char *fw_cfg_arch_key_name(uint16_t key) } return NULL; } + +void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg) +{ + uint8_t *smbios_tables, *smbios_anchor; + size_t smbios_tables_len, smbios_anchor_len; + struct smbios_phys_mem_area *mem_array; + unsigned i, array_count; + X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); + + /* tell smbios about cpuid version and features */ + smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); + + smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len); + if (smbios_tables) { + fw_cfg_add_bytes(fw_cfg, FW_CFG_SMBIOS_ENTRIES, + smbios_tables, smbios_tables_len); + } + + /* build the array of physical mem area from e820 table */ + mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); + for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { + uint64_t addr, len; + + if (e820_get_entry(i, E820_RAM, &addr, &len)) { + mem_array[array_count].address = addr; + mem_array[array_count].length = len; + array_count++; + } + } + smbios_get_tables(ms, mem_array, array_count, + &smbios_tables, &smbios_tables_len, + &smbios_anchor, &smbios_anchor_len); + g_free(mem_array); + + if (smbios_anchor) { + fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-tables", + smbios_tables, smbios_tables_len); + fw_cfg_add_file(fw_cfg, "etc/smbios/smbios-anchor", + smbios_anchor, smbios_anchor_len); + } +} + +FWCfgState *fw_cfg_arch_create(MachineState *ms, + uint16_t boot_cpus, + uint16_t apic_id_limit) +{ + FWCfgState *fw_cfg; + uint64_t *numa_fw_cfg; + int i; + MachineClass *mc = MACHINE_GET_CLASS(ms); + const CPUArchIdList *cpus = mc->possible_cpu_arch_ids(ms); + int nb_numa_nodes = ms->numa_state->num_nodes; + + fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, + &address_space_memory); + fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, boot_cpus); + + /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: + * + * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for + * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, + * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface + * for CPU hotplug also uses APIC ID and not "CPU index". + * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", + * but the "limit to the APIC ID values SeaBIOS may see". + * + * So for compatibility reasons with old BIOSes we are stuck with + * "etc/max-cpus" actually being apic_id_limit + */ + fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, apic_id_limit); + fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); + fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, + acpi_tables, acpi_tables_len); + fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); + + fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, + &e820_reserve, sizeof(e820_reserve)); + fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, + sizeof(struct e820_entry) * e820_get_num_entries()); + + fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); + /* allocate memory for the NUMA channel: one (64bit) word for the number + * of nodes, one word for each VCPU->node and one word for each node to + * hold the amount of memory. + */ + numa_fw_cfg = g_new0(uint64_t, 1 + apic_id_limit + nb_numa_nodes); + numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); + for (i = 0; i < cpus->len; i++) { + unsigned int apic_id = cpus->cpus[i].arch_id; + assert(apic_id < apic_id_limit); + numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); + } + for (i = 0; i < nb_numa_nodes; i++) { + numa_fw_cfg[apic_id_limit + 1 + i] = + cpu_to_le64(ms->numa_state->nodes[i].node_mem); + } + fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, + (1 + apic_id_limit + nb_numa_nodes) * + sizeof(*numa_fw_cfg)); + + return fw_cfg; +} + +void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg) +{ + X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); + CPUX86State *env = &cpu->env; + uint32_t unused, ecx, edx; + uint64_t feature_control_bits = 0; + uint64_t *val; + + cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); + if (ecx & CPUID_EXT_VMX) { + feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; + } + + if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == + (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && + (env->mcg_cap & MCG_LMCE_P)) { + feature_control_bits |= FEATURE_CONTROL_LMCE; + } + + if (!feature_control_bits) { + return; + } + + val = g_malloc(sizeof(*val)); + *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); + fw_cfg_add_file(fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); +} diff --git a/hw/i386/fw_cfg.h b/hw/i386/fw_cfg.h index 17a4bc32f2..e0856a3769 100644 --- a/hw/i386/fw_cfg.h +++ b/hw/i386/fw_cfg.h @@ -9,6 +9,7 @@ #ifndef HW_I386_FW_CFG_H #define HW_I386_FW_CFG_H +#include "hw/boards.h" #include "hw/nvram/fw_cfg.h" #define FW_CFG_ACPI_TABLES (FW_CFG_ARCH_LOCAL + 0) @@ -17,4 +18,10 @@ #define FW_CFG_E820_TABLE (FW_CFG_ARCH_LOCAL + 3) #define FW_CFG_HPET (FW_CFG_ARCH_LOCAL + 4) +FWCfgState *fw_cfg_arch_create(MachineState *ms, + uint16_t boot_cpus, + uint16_t apic_id_limit); +void fw_cfg_build_smbios(MachineState *ms, FWCfgState *fw_cfg); +void fw_cfg_build_feature_control(MachineState *ms, FWCfgState *fw_cfg); + #endif diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 75ca6f9c70..f1de8fdb75 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -35,6 +35,7 @@ #include "hw/i386/x86-iommu.h" #include "hw/pci-host/q35.h" #include "sysemu/kvm.h" +#include "sysemu/sysemu.h" #include "hw/i386/apic_internal.h" #include "kvm_i386.h" #include "migration/vmstate.h" @@ -64,6 +65,13 @@ static void vtd_address_space_refresh_all(IntelIOMMUState *s); static void vtd_address_space_unmap(VTDAddressSpace *as, IOMMUNotifier *n); +static void vtd_panic_require_caching_mode(void) +{ + error_report("We need to set caching-mode=on for intel-iommu to enable " + "device assignment with IOMMU protection."); + exit(1); +} + static void vtd_define_quad(IntelIOMMUState *s, hwaddr addr, uint64_t val, uint64_t wmask, uint64_t w1cmask) { @@ -2928,12 +2936,6 @@ static void vtd_iommu_notify_flag_changed(IOMMUMemoryRegion *iommu, VTDAddressSpace *vtd_as = container_of(iommu, VTDAddressSpace, iommu); IntelIOMMUState *s = vtd_as->iommu_state; - if (!s->caching_mode && new & IOMMU_NOTIFIER_MAP) { - error_report("We need to set caching-mode=on for intel-iommu to enable " - "device assignment with IOMMU protection."); - exit(1); - } - /* Update per-address-space notifier flags */ vtd_as->notifier_flags = new; @@ -3699,6 +3701,32 @@ static bool vtd_decide_config(IntelIOMMUState *s, Error **errp) return true; } +static int vtd_machine_done_notify_one(Object *child, void *unused) +{ + IntelIOMMUState *iommu = INTEL_IOMMU_DEVICE(x86_iommu_get_default()); + + /* + * We hard-coded here because vfio-pci is the only special case + * here. Let's be more elegant in the future when we can, but so + * far there seems to be no better way. + */ + if (object_dynamic_cast(child, "vfio-pci") && !iommu->caching_mode) { + vtd_panic_require_caching_mode(); + } + + return 0; +} + +static void vtd_machine_done_hook(Notifier *notifier, void *unused) +{ + object_child_foreach_recursive(object_get_root(), + vtd_machine_done_notify_one, NULL); +} + +static Notifier vtd_machine_done_notify = { + .notify = vtd_machine_done_hook, +}; + static void vtd_realize(DeviceState *dev, Error **errp) { MachineState *ms = MACHINE(qdev_get_machine()); @@ -3744,6 +3772,7 @@ static void vtd_realize(DeviceState *dev, Error **errp) pci_setup_iommu(bus, vtd_host_dma_iommu, dev); /* Pseudo address space under root PCI bus. */ pcms->ioapic_as = vtd_host_dma_iommu(bus, s, Q35_PSEUDO_DEVFN_IOAPIC); + qemu_add_machine_init_done_notifier(&vtd_machine_done_notify); } static void vtd_class_init(ObjectClass *klass, void *data) diff --git a/hw/i386/pc.c b/hw/i386/pc.c index bad866fe44..bcda50efcc 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -87,6 +87,8 @@ #include "sysemu/replay.h" #include "qapi/qmp/qerror.h" #include "config-devices.h" +#include "e820_memory_layout.h" +#include "fw_cfg.h" /* debug PC/ISA interrupts */ //#define DEBUG_IRQ @@ -98,22 +100,6 @@ #define DPRINTF(fmt, ...) #endif -#define E820_NR_ENTRIES 16 - -struct e820_entry { - uint64_t address; - uint64_t length; - uint32_t type; -} QEMU_PACKED __attribute((__aligned__(4))); - -struct e820_table { - uint32_t count; - struct e820_entry entry[E820_NR_ENTRIES]; -} QEMU_PACKED __attribute((__aligned__(4))); - -static struct e820_table e820_reserve; -static struct e820_entry *e820_table; -static unsigned e820_entries; struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; /* Physical Address of PVH entry point read from kernel ELF NOTE */ @@ -880,50 +866,6 @@ static void handle_a20_line_change(void *opaque, int irq, int level) x86_cpu_set_a20(cpu, level); } -int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) -{ - int index = le32_to_cpu(e820_reserve.count); - struct e820_entry *entry; - - if (type != E820_RAM) { - /* old FW_CFG_E820_TABLE entry -- reservations only */ - if (index >= E820_NR_ENTRIES) { - return -EBUSY; - } - entry = &e820_reserve.entry[index++]; - - entry->address = cpu_to_le64(address); - entry->length = cpu_to_le64(length); - entry->type = cpu_to_le32(type); - - e820_reserve.count = cpu_to_le32(index); - } - - /* new "etc/e820" file -- include ram too */ - e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); - e820_table[e820_entries].address = cpu_to_le64(address); - e820_table[e820_entries].length = cpu_to_le64(length); - e820_table[e820_entries].type = cpu_to_le32(type); - e820_entries++; - - return e820_entries; -} - -int e820_get_num_entries(void) -{ - return e820_entries; -} - -bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) -{ - if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { - *address = le64_to_cpu(e820_table[idx].address); - *length = le64_to_cpu(e820_table[idx].length); - return true; - } - return false; -} - /* Calculates initial APIC ID for a specific CPU index * * Currently we need to be able to calculate the APIC ID from the CPU index @@ -953,108 +895,6 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, } } -static void pc_build_smbios(PCMachineState *pcms) -{ - uint8_t *smbios_tables, *smbios_anchor; - size_t smbios_tables_len, smbios_anchor_len; - struct smbios_phys_mem_area *mem_array; - unsigned i, array_count; - MachineState *ms = MACHINE(pcms); - X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); - - /* tell smbios about cpuid version and features */ - smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); - - smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len); - if (smbios_tables) { - fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, - smbios_tables, smbios_tables_len); - } - - /* build the array of physical mem area from e820 table */ - mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); - for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { - uint64_t addr, len; - - if (e820_get_entry(i, E820_RAM, &addr, &len)) { - mem_array[array_count].address = addr; - mem_array[array_count].length = len; - array_count++; - } - } - smbios_get_tables(ms, mem_array, array_count, - &smbios_tables, &smbios_tables_len, - &smbios_anchor, &smbios_anchor_len); - g_free(mem_array); - - if (smbios_anchor) { - fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", - smbios_tables, smbios_tables_len); - fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", - smbios_anchor, smbios_anchor_len); - } -} - -static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) -{ - FWCfgState *fw_cfg; - uint64_t *numa_fw_cfg; - int i; - const CPUArchIdList *cpus; - MachineClass *mc = MACHINE_GET_CLASS(pcms); - MachineState *ms = MACHINE(pcms); - int nb_numa_nodes = ms->numa_state->num_nodes; - - fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); - - /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: - * - * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for - * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, - * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface - * for CPU hotplug also uses APIC ID and not "CPU index". - * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", - * but the "limit to the APIC ID values SeaBIOS may see". - * - * So for compatibility reasons with old BIOSes we are stuck with - * "etc/max-cpus" actually being apic_id_limit - */ - fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); - fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); - fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, - acpi_tables, acpi_tables_len); - fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); - - fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, - &e820_reserve, sizeof(e820_reserve)); - fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, - sizeof(struct e820_entry) * e820_entries); - - fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); - /* allocate memory for the NUMA channel: one (64bit) word for the number - * of nodes, one word for each VCPU->node and one word for each node to - * hold the amount of memory. - */ - numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); - numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); - cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); - for (i = 0; i < cpus->len; i++) { - unsigned int apic_id = cpus->cpus[i].arch_id; - assert(apic_id < pcms->apic_id_limit); - numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); - } - for (i = 0; i < nb_numa_nodes; i++) { - numa_fw_cfg[pcms->apic_id_limit + 1 + i] = - cpu_to_le64(ms->numa_state->nodes[i].node_mem); - } - fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, - (1 + pcms->apic_id_limit + nb_numa_nodes) * - sizeof(*numa_fw_cfg)); - - return fw_cfg; -} - static long get_file_size(FILE *f) { long where, size; @@ -1672,7 +1512,7 @@ void pc_cpus_init(PCMachineState *pcms) * Limit for the APIC ID value, so that all * CPU APIC IDs are < pcms->apic_id_limit. * - * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). + * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). */ pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, ms->smp.max_cpus - 1) + 1; @@ -1682,35 +1522,6 @@ void pc_cpus_init(PCMachineState *pcms) } } -static void pc_build_feature_control_file(PCMachineState *pcms) -{ - MachineState *ms = MACHINE(pcms); - X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); - CPUX86State *env = &cpu->env; - uint32_t unused, ecx, edx; - uint64_t feature_control_bits = 0; - uint64_t *val; - - cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); - if (ecx & CPUID_EXT_VMX) { - feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; - } - - if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == - (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && - (env->mcg_cap & MCG_LMCE_P)) { - feature_control_bits |= FEATURE_CONTROL_LMCE; - } - - if (!feature_control_bits) { - return; - } - - val = g_malloc(sizeof(*val)); - *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); - fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); -} - static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) { if (cpus_count > 0xff) { @@ -1753,8 +1564,8 @@ void pc_machine_done(Notifier *notifier, void *data) acpi_setup(); if (pcms->fw_cfg) { - pc_build_smbios(pcms); - pc_build_feature_control_file(pcms); + fw_cfg_build_smbios(MACHINE(pcms), pcms->fw_cfg); + fw_cfg_build_feature_control(MACHINE(pcms), pcms->fw_cfg); /* update FW_CFG_NB_CPUS to account for -device added CPUs */ fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); } @@ -1831,6 +1642,7 @@ void pc_memory_init(PCMachineState *pcms, MemoryRegion *ram_below_4g, *ram_above_4g; FWCfgState *fw_cfg; MachineState *machine = MACHINE(pcms); + MachineClass *mc = MACHINE_GET_CLASS(machine); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); assert(machine->ram_size == pcms->below_4g_mem_size + @@ -1864,7 +1676,6 @@ void pc_memory_init(PCMachineState *pcms, if (!pcmc->has_reserved_memory && (machine->ram_slots || (machine->maxram_size > machine->ram_size))) { - MachineClass *mc = MACHINE_GET_CLASS(machine); error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", mc->name); @@ -1927,7 +1738,8 @@ void pc_memory_init(PCMachineState *pcms, option_rom_mr, 1); - fw_cfg = bochs_bios_init(&address_space_memory, pcms); + fw_cfg = fw_cfg_arch_create(machine, + pcms->boot_cpus, pcms->apic_id_limit); rom_set_fw(fw_cfg); @@ -2944,6 +2756,26 @@ static void x86_nmi(NMIState *n, int cpu_index, Error **errp) } } + +static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) +{ + X86IOMMUState *iommu = x86_iommu_get_default(); + IntelIOMMUState *intel_iommu; + + if (iommu && + object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && + object_dynamic_cast((Object *)dev, "vfio-pci")) { + intel_iommu = INTEL_IOMMU_DEVICE(iommu); + if (!intel_iommu->caching_mode) { + error_setg(errp, "Device assignment is not allowed without " + "enabling caching-mode=on for Intel IOMMU."); + return false; + } + } + + return true; +} + static void pc_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -2968,6 +2800,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) pcmc->pvh_enabled = true; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler = pc_get_hotplug_handler; + mc->hotplug_allowed = pc_hotplug_allowed; mc->cpu_index_to_instance_props = pc_cpu_index_to_props; mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; diff --git a/hw/mips/mips_jazz.c b/hw/mips/mips_jazz.c index 388c15c376..c967b97d80 100644 --- a/hw/mips/mips_jazz.c +++ b/hw/mips/mips_jazz.c @@ -111,16 +111,26 @@ static const MemoryRegionOps dma_dummy_ops = { #define MAGNUM_BIOS_SIZE_MAX 0x7e000 #define MAGNUM_BIOS_SIZE (BIOS_SIZE < MAGNUM_BIOS_SIZE_MAX ? BIOS_SIZE : MAGNUM_BIOS_SIZE_MAX) -static CPUUnassignedAccess real_do_unassigned_access; -static void mips_jazz_do_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, - int opaque, unsigned size) +static void (*real_do_transaction_failed)(CPUState *cpu, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, + uintptr_t retaddr); + +static void mips_jazz_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, + uintptr_t retaddr) { - if (!is_exec) { + if (access_type != MMU_INST_FETCH) { /* ignore invalid access (ie do not raise exception) */ return; } - (*real_do_unassigned_access)(cpu, addr, is_write, is_exec, opaque, size); + (*real_do_transaction_failed)(cs, physaddr, addr, size, access_type, + mmu_idx, attrs, response, retaddr); } static void mips_jazz_init(MachineState *machine, @@ -157,16 +167,25 @@ static void mips_jazz_init(MachineState *machine, env = &cpu->env; qemu_register_reset(main_cpu_reset, cpu); - /* Chipset returns 0 in invalid reads and do not raise data exceptions. + /* + * Chipset returns 0 in invalid reads and do not raise data exceptions. * However, we can't simply add a global memory region to catch - * everything, as memory core directly call unassigned_mem_read/write - * on some invalid accesses, which call do_unassigned_access on the - * CPU, which raise an exception. - * Handle that case by hijacking the do_unassigned_access method on - * the CPU, and do not raise exceptions for data access. */ + * everything, as this would make all accesses including instruction + * accesses be ignored and not raise exceptions. + * So instead we hijack the do_transaction_failed method on the CPU, and + * do not raise exceptions for data access. + * + * NOTE: this behaviour of raising exceptions for bad instruction + * fetches but not bad data accesses was added in commit 54e755588cf1e9 + * to restore behaviour broken by c658b94f6e8c206, but it is not clear + * whether the real hardware behaves this way. It is possible that + * real hardware ignores bad instruction fetches as well -- if so then + * we could replace this hijacking of CPU methods with a simple global + * memory region that catches all memory accesses, as we do on Malta. + */ cc = CPU_GET_CLASS(cpu); - real_do_unassigned_access = cc->do_unassigned_access; - cc->do_unassigned_access = mips_jazz_do_unassigned_access; + real_do_transaction_failed = cc->do_transaction_failed; + cc->do_transaction_failed = mips_jazz_do_transaction_failed; /* allocate RAM */ memory_region_allocate_system_memory(ram, NULL, "mips_jazz.ram", diff --git a/hw/misc/Makefile.objs b/hw/misc/Makefile.objs index e4aad707fb..a150680966 100644 --- a/hw/misc/Makefile.objs +++ b/hw/misc/Makefile.objs @@ -26,57 +26,57 @@ common-obj-$(CONFIG_PUV3) += puv3_pm.o common-obj-$(CONFIG_MACIO) += macio/ -obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o +common-obj-$(CONFIG_IVSHMEM_DEVICE) += ivshmem.o -obj-$(CONFIG_REALVIEW) += arm_sysctl.o -obj-$(CONFIG_NSERIES) += cbus.o -obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o -obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o exynos4210_rng.o -obj-$(CONFIG_IMX) += imx_ccm.o -obj-$(CONFIG_IMX) += imx31_ccm.o -obj-$(CONFIG_IMX) += imx25_ccm.o -obj-$(CONFIG_IMX) += imx6_ccm.o -obj-$(CONFIG_IMX) += imx6ul_ccm.o +common-obj-$(CONFIG_REALVIEW) += arm_sysctl.o +common-obj-$(CONFIG_NSERIES) += cbus.o +common-obj-$(CONFIG_ECCMEMCTL) += eccmemctl.o +common-obj-$(CONFIG_EXYNOS4) += exynos4210_pmu.o exynos4210_clk.o exynos4210_rng.o +common-obj-$(CONFIG_IMX) += imx_ccm.o +common-obj-$(CONFIG_IMX) += imx31_ccm.o +common-obj-$(CONFIG_IMX) += imx25_ccm.o +common-obj-$(CONFIG_IMX) += imx6_ccm.o +common-obj-$(CONFIG_IMX) += imx6ul_ccm.o obj-$(CONFIG_IMX) += imx6_src.o -obj-$(CONFIG_IMX) += imx7_ccm.o -obj-$(CONFIG_IMX) += imx2_wdt.o -obj-$(CONFIG_IMX) += imx7_snvs.o -obj-$(CONFIG_IMX) += imx7_gpr.o -obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o -obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o -obj-$(CONFIG_MAINSTONE) += mst_fpga.o -obj-$(CONFIG_OMAP) += omap_clk.o -obj-$(CONFIG_OMAP) += omap_gpmc.o -obj-$(CONFIG_OMAP) += omap_l4.o -obj-$(CONFIG_OMAP) += omap_sdrc.o -obj-$(CONFIG_OMAP) += omap_tap.o -obj-$(CONFIG_RASPI) += bcm2835_mbox.o -obj-$(CONFIG_RASPI) += bcm2835_property.o -obj-$(CONFIG_RASPI) += bcm2835_rng.o -obj-$(CONFIG_SLAVIO) += slavio_misc.o -obj-$(CONFIG_ZYNQ) += zynq_slcr.o -obj-$(CONFIG_ZYNQ) += zynq-xadc.o -obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o +common-obj-$(CONFIG_IMX) += imx7_ccm.o +common-obj-$(CONFIG_IMX) += imx2_wdt.o +common-obj-$(CONFIG_IMX) += imx7_snvs.o +common-obj-$(CONFIG_IMX) += imx7_gpr.o +common-obj-$(CONFIG_MILKYMIST) += milkymist-hpdmc.o +common-obj-$(CONFIG_MILKYMIST) += milkymist-pfpu.o +common-obj-$(CONFIG_MAINSTONE) += mst_fpga.o +common-obj-$(CONFIG_OMAP) += omap_clk.o +common-obj-$(CONFIG_OMAP) += omap_gpmc.o +common-obj-$(CONFIG_OMAP) += omap_l4.o +common-obj-$(CONFIG_OMAP) += omap_sdrc.o +common-obj-$(CONFIG_OMAP) += omap_tap.o +common-obj-$(CONFIG_RASPI) += bcm2835_mbox.o +common-obj-$(CONFIG_RASPI) += bcm2835_property.o +common-obj-$(CONFIG_RASPI) += bcm2835_rng.o +common-obj-$(CONFIG_SLAVIO) += slavio_misc.o +common-obj-$(CONFIG_ZYNQ) += zynq_slcr.o +common-obj-$(CONFIG_ZYNQ) += zynq-xadc.o +common-obj-$(CONFIG_STM32F2XX_SYSCFG) += stm32f2xx_syscfg.o obj-$(CONFIG_MIPS_CPS) += mips_cmgcr.o obj-$(CONFIG_MIPS_CPS) += mips_cpc.o obj-$(CONFIG_MIPS_ITU) += mips_itu.o -obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o -obj-$(CONFIG_MPS2_SCC) += mps2-scc.o +common-obj-$(CONFIG_MPS2_FPGAIO) += mps2-fpgaio.o +common-obj-$(CONFIG_MPS2_SCC) += mps2-scc.o -obj-$(CONFIG_TZ_MPC) += tz-mpc.o -obj-$(CONFIG_TZ_MSC) += tz-msc.o -obj-$(CONFIG_TZ_PPC) += tz-ppc.o -obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o +common-obj-$(CONFIG_TZ_MPC) += tz-mpc.o +common-obj-$(CONFIG_TZ_MSC) += tz-msc.o +common-obj-$(CONFIG_TZ_PPC) += tz-ppc.o +common-obj-$(CONFIG_IOTKIT_SECCTL) += iotkit-secctl.o obj-$(CONFIG_IOTKIT_SYSCTL) += iotkit-sysctl.o -obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o -obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o -obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o +common-obj-$(CONFIG_IOTKIT_SYSINFO) += iotkit-sysinfo.o +common-obj-$(CONFIG_ARMSSE_CPUID) += armsse-cpuid.o +common-obj-$(CONFIG_ARMSSE_MHU) += armsse-mhu.o -obj-$(CONFIG_PVPANIC) += pvpanic.o -obj-$(CONFIG_AUX) += auxbus.o -obj-$(CONFIG_ASPEED_SOC) += aspeed_xdma.o -obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o -obj-$(CONFIG_MSF2) += msf2-sysreg.o -obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o +common-obj-$(CONFIG_PVPANIC) += pvpanic.o +common-obj-$(CONFIG_AUX) += auxbus.o +common-obj-$(CONFIG_ASPEED_SOC) += aspeed_xdma.o +common-obj-$(CONFIG_ASPEED_SOC) += aspeed_scu.o aspeed_sdmc.o +common-obj-$(CONFIG_MSF2) += msf2-sysreg.o +common-obj-$(CONFIG_NRF51_SOC) += nrf51_rng.o -obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o +common-obj-$(CONFIG_GRLIB) += grlib_ahb_apb_pnp.o diff --git a/hw/misc/aspeed_scu.c b/hw/misc/aspeed_scu.c index 268cb24e56..620b25c204 100644 --- a/hw/misc/aspeed_scu.c +++ b/hw/misc/aspeed_scu.c @@ -164,25 +164,13 @@ static uint32_t aspeed_scu_get_random(void) return num; } -static void aspeed_scu_set_apb_freq(AspeedSCUState *s) +uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s) { - uint32_t apb_divider; + AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(s); + uint32_t hpll = asc->calc_hpll(s, s->regs[HPLL_PARAM]); - switch (s->silicon_rev) { - case AST2400_A0_SILICON_REV: - case AST2400_A1_SILICON_REV: - apb_divider = 2; - break; - case AST2500_A0_SILICON_REV: - case AST2500_A1_SILICON_REV: - apb_divider = 4; - break; - default: - g_assert_not_reached(); - } - - s->apb_freq = s->hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) - / apb_divider; + return hpll / (SCU_CLK_GET_PCLK_DIV(s->regs[CLK_SEL]) + 1) + / asc->apb_divider; } static uint64_t aspeed_scu_read(void *opaque, hwaddr offset, unsigned size) @@ -241,7 +229,6 @@ static void aspeed_scu_write(void *opaque, hwaddr offset, uint64_t data, return; case CLK_SEL: s->regs[reg] = data; - aspeed_scu_set_apb_freq(s); break; case HW_STRAP1: if (ASPEED_IS_AST2500(s->regs[SILICON_REV])) { @@ -303,11 +290,11 @@ static const uint32_t hpll_ast2400_freqs[][4] = { { 400, 375, 350, 425 }, /* 25MHz */ }; -static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s) +static uint32_t aspeed_2400_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) { - uint32_t hpll_reg = s->regs[HPLL_PARAM]; uint8_t freq_select; bool clk_25m_in; + uint32_t clkin = aspeed_scu_get_clkin(s); if (hpll_reg & SCU_AST2400_H_PLL_OFF) { return 0; @@ -324,7 +311,7 @@ static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s) multiplier = (2 - od) * ((n + 2) / (d + 1)); } - return s->clkin * multiplier; + return clkin * multiplier; } /* HW strapping */ @@ -334,10 +321,10 @@ static uint32_t aspeed_scu_calc_hpll_ast2400(AspeedSCUState *s) return hpll_ast2400_freqs[clk_25m_in][freq_select] * 1000000; } -static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s) +static uint32_t aspeed_2500_scu_calc_hpll(AspeedSCUState *s, uint32_t hpll_reg) { - uint32_t hpll_reg = s->regs[HPLL_PARAM]; uint32_t multiplier = 1; + uint32_t clkin = aspeed_scu_get_clkin(s); if (hpll_reg & SCU_H_PLL_OFF) { return 0; @@ -351,42 +338,19 @@ static uint32_t aspeed_scu_calc_hpll_ast2500(AspeedSCUState *s) multiplier = ((m + 1) / (n + 1)) / (p + 1); } - return s->clkin * multiplier; + return clkin * multiplier; } static void aspeed_scu_reset(DeviceState *dev) { AspeedSCUState *s = ASPEED_SCU(dev); - const uint32_t *reset; - uint32_t (*calc_hpll)(AspeedSCUState *s); - - switch (s->silicon_rev) { - case AST2400_A0_SILICON_REV: - case AST2400_A1_SILICON_REV: - reset = ast2400_a0_resets; - calc_hpll = aspeed_scu_calc_hpll_ast2400; - break; - case AST2500_A0_SILICON_REV: - case AST2500_A1_SILICON_REV: - reset = ast2500_a1_resets; - calc_hpll = aspeed_scu_calc_hpll_ast2500; - break; - default: - g_assert_not_reached(); - } + AspeedSCUClass *asc = ASPEED_SCU_GET_CLASS(dev); - memcpy(s->regs, reset, sizeof(s->regs)); + memcpy(s->regs, asc->resets, sizeof(s->regs)); s->regs[SILICON_REV] = s->silicon_rev; s->regs[HW_STRAP1] = s->hw_strap1; s->regs[HW_STRAP2] = s->hw_strap2; s->regs[PROT_KEY] = s->hw_prot_key; - - /* - * All registers are set. Now compute the frequencies of the main clocks - */ - s->clkin = aspeed_scu_get_clkin(s); - s->hpll = calc_hpll(s); - aspeed_scu_set_apb_freq(s); } static uint32_t aspeed_silicon_revs[] = { @@ -459,11 +423,51 @@ static const TypeInfo aspeed_scu_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(AspeedSCUState), .class_init = aspeed_scu_class_init, + .class_size = sizeof(AspeedSCUClass), + .abstract = true, +}; + +static void aspeed_2400_scu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); + + dc->desc = "ASPEED 2400 System Control Unit"; + asc->resets = ast2400_a0_resets; + asc->calc_hpll = aspeed_2400_scu_calc_hpll; + asc->apb_divider = 2; +} + +static const TypeInfo aspeed_2400_scu_info = { + .name = TYPE_ASPEED_2400_SCU, + .parent = TYPE_ASPEED_SCU, + .instance_size = sizeof(AspeedSCUState), + .class_init = aspeed_2400_scu_class_init, +}; + +static void aspeed_2500_scu_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedSCUClass *asc = ASPEED_SCU_CLASS(klass); + + dc->desc = "ASPEED 2500 System Control Unit"; + asc->resets = ast2500_a1_resets; + asc->calc_hpll = aspeed_2500_scu_calc_hpll; + asc->apb_divider = 4; +} + +static const TypeInfo aspeed_2500_scu_info = { + .name = TYPE_ASPEED_2500_SCU, + .parent = TYPE_ASPEED_SCU, + .instance_size = sizeof(AspeedSCUState), + .class_init = aspeed_2500_scu_class_init, }; static void aspeed_scu_register_types(void) { type_register_static(&aspeed_scu_info); + type_register_static(&aspeed_2400_scu_info); + type_register_static(&aspeed_2500_scu_info); } type_init(aspeed_scu_register_types); diff --git a/hw/misc/trace-events b/hw/misc/trace-events index c1ea1aa437..74276225f8 100644 --- a/hw/misc/trace-events +++ b/hw/misc/trace-events @@ -118,11 +118,11 @@ iotkit_secctl_ns_read(uint32_t offset, uint64_t data, unsigned size) "IoTKit Sec iotkit_secctl_ns_write(uint32_t offset, uint64_t data, unsigned size) "IoTKit SecCtl NS regs write: offset 0x%x data 0x%" PRIx64 " size %u" # imx6ul_ccm.c -ccm_entry(void) "\n" -ccm_freq(uint32_t freq) "freq = %d\n" -ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d\n" -ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 "\n" -ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 "\n" +ccm_entry(void) "" +ccm_freq(uint32_t freq) "freq = %d" +ccm_clock_freq(uint32_t clock, uint32_t freq) "(Clock = %d) = %d" +ccm_read_reg(const char *reg_name, uint32_t value) "reg[%s] <= 0x%" PRIx32 +ccm_write_reg(const char *reg_name, uint32_t value) "reg[%s] => 0x%" PRIx32 # iotkit-sysinfo.c iotkit_sysinfo_read(uint64_t offset, uint64_t data, unsigned size) "IoTKit SysInfo read: offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" diff --git a/hw/net/vmxnet3.c b/hw/net/vmxnet3.c index b07adeed9c..39ff6624c5 100644 --- a/hw/net/vmxnet3.c +++ b/hw/net/vmxnet3.c @@ -2242,13 +2242,10 @@ static void vmxnet3_instance_init(Object *obj) static void vmxnet3_pci_uninit(PCIDevice *pci_dev) { - DeviceState *dev = DEVICE(pci_dev); VMXNET3State *s = VMXNET3(pci_dev); VMW_CBPRN("Starting uninit..."); - unregister_savevm(dev, "vmxnet3-msix", s); - vmxnet3_net_uninit(s); vmxnet3_cleanup_msix(s); diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index 222a325056..08a2a5a770 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -3078,7 +3078,7 @@ static void spapr_machine_init(MachineState *machine) * interface, this is a legacy from the sPAPREnvironment structure * which predated MachineState but had a similar function */ vmstate_register(NULL, 0, &vmstate_spapr, spapr); - register_savevm_live(NULL, "spapr/htab", -1, 1, + register_savevm_live("spapr/htab", -1, 1, &savevm_htab_handlers, spapr); qbus_set_hotplug_handler(sysbus_get_default(), OBJECT(machine), diff --git a/hw/riscv/Kconfig b/hw/riscv/Kconfig index 8674211085..fb19b2df3a 100644 --- a/hw/riscv/Kconfig +++ b/hw/riscv/Kconfig @@ -12,12 +12,14 @@ config SIFIVE_E bool select HART select SIFIVE + select UNIMP config SIFIVE_U bool select CADENCE select HART select SIFIVE + select UNIMP config SPIKE bool diff --git a/hw/riscv/Makefile.objs b/hw/riscv/Makefile.objs index eb9d4f9ffc..fc3c6dd7c8 100644 --- a/hw/riscv/Makefile.objs +++ b/hw/riscv/Makefile.objs @@ -2,12 +2,14 @@ obj-y += boot.o obj-$(CONFIG_SPIKE) += riscv_htif.o obj-$(CONFIG_HART) += riscv_hart.o obj-$(CONFIG_SIFIVE_E) += sifive_e.o +obj-$(CONFIG_SIFIVE_E) += sifive_e_prci.o obj-$(CONFIG_SIFIVE) += sifive_clint.o obj-$(CONFIG_SIFIVE) += sifive_gpio.o -obj-$(CONFIG_SIFIVE) += sifive_prci.o obj-$(CONFIG_SIFIVE) += sifive_plic.o obj-$(CONFIG_SIFIVE) += sifive_test.o obj-$(CONFIG_SIFIVE_U) += sifive_u.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_otp.o +obj-$(CONFIG_SIFIVE_U) += sifive_u_prci.o obj-$(CONFIG_SIFIVE) += sifive_uart.o obj-$(CONFIG_SPIKE) += spike.o obj-$(CONFIG_RISCV_VIRT) += virt.o diff --git a/hw/riscv/boot.c b/hw/riscv/boot.c index 4c63b5cf8a..2e92fb0680 100644 --- a/hw/riscv/boot.c +++ b/hw/riscv/boot.c @@ -69,25 +69,33 @@ void riscv_find_and_load_firmware(MachineState *machine, * so then in the future we can make "-bios default" the default option * if no -bios option is set without breaking anything. */ - firmware_filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, - default_machine_firmware); - if (firmware_filename == NULL) { - error_report("Unable to load the default RISC-V firmware \"%s\"", - default_machine_firmware); - exit(1); - } + firmware_filename = riscv_find_firmware(default_machine_firmware); } else { firmware_filename = machine->firmware; + if (strcmp(firmware_filename, "none")) { + firmware_filename = riscv_find_firmware(firmware_filename); + } } if (strcmp(firmware_filename, "none")) { /* If not "none" load the firmware */ riscv_load_firmware(firmware_filename, firmware_load_addr); + g_free(firmware_filename); } +} - if (!strcmp(machine->firmware, "default")) { - g_free(firmware_filename); +char *riscv_find_firmware(const char *firmware_filename) +{ + char *filename; + + filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, firmware_filename); + if (filename == NULL) { + error_report("Unable to load the RISC-V firmware \"%s\"", + firmware_filename); + exit(1); } + + return filename; } target_ulong riscv_load_firmware(const char *firmware_filename, diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c index d0f3199968..5b98227db6 100644 --- a/hw/riscv/riscv_hart.c +++ b/hw/riscv/riscv_hart.c @@ -3,7 +3,7 @@ * * Copyright (c) 2017 SiFive, Inc. * - * Holds the state of a heterogenous array of RISC-V harts + * Holds the state of a homogeneous array of RISC-V harts * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -29,6 +29,7 @@ static Property riscv_harts_props[] = { DEFINE_PROP_UINT32("num-harts", RISCVHartArrayState, num_harts, 1), + DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0), DEFINE_PROP_STRING("cpu-type", RISCVHartArrayState, cpu_type), DEFINE_PROP_END_OF_LIST(), }; @@ -39,26 +40,33 @@ static void riscv_harts_cpu_reset(void *opaque) cpu_reset(CPU(cpu)); } +static void riscv_hart_realize(RISCVHartArrayState *s, int idx, + char *cpu_type, Error **errp) +{ + Error *err = NULL; + + object_initialize_child(OBJECT(s), "harts[*]", &s->harts[idx], + sizeof(RISCVCPU), cpu_type, + &error_abort, NULL); + s->harts[idx].env.mhartid = s->hartid_base + idx; + qemu_register_reset(riscv_harts_cpu_reset, &s->harts[idx]); + object_property_set_bool(OBJECT(&s->harts[idx]), true, + "realized", &err); + if (err) { + error_propagate(errp, err); + return; + } +} + static void riscv_harts_realize(DeviceState *dev, Error **errp) { RISCVHartArrayState *s = RISCV_HART_ARRAY(dev); - Error *err = NULL; int n; s->harts = g_new0(RISCVCPU, s->num_harts); for (n = 0; n < s->num_harts; n++) { - object_initialize_child(OBJECT(s), "harts[*]", &s->harts[n], - sizeof(RISCVCPU), s->cpu_type, - &error_abort, NULL); - s->harts[n].env.mhartid = n; - qemu_register_reset(riscv_harts_cpu_reset, &s->harts[n]); - object_property_set_bool(OBJECT(&s->harts[n]), true, - "realized", &err); - if (err) { - error_propagate(errp, err); - return; - } + riscv_hart_realize(s, n, s->cpu_type, errp); } } diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index 792d75a1a3..0f9d641a0e 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -36,13 +36,14 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "hw/char/serial.h" +#include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_clint.h" -#include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_uart.h" #include "hw/riscv/sifive_e.h" +#include "hw/riscv/sifive_e_prci.h" #include "hw/riscv/boot.h" #include "chardev/char.h" #include "sysemu/arch_init.h" @@ -74,14 +75,6 @@ static const struct MemmapEntry { [SIFIVE_E_DTIM] = { 0x80000000, 0x4000 } }; -static void sifive_mmio_emulate(MemoryRegion *parent, const char *name, - uintptr_t offset, uintptr_t length) -{ - MemoryRegion *mock_mmio = g_new(MemoryRegion, 1); - memory_region_init_ram(mock_mmio, NULL, name, length, &error_fatal); - memory_region_add_subregion(parent, offset, mock_mmio); -} - static void riscv_sifive_e_init(MachineState *machine) { const struct MemmapEntry *memmap = sifive_e_memmap; @@ -172,9 +165,9 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) sifive_clint_create(memmap[SIFIVE_E_CLINT].base, memmap[SIFIVE_E_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.aon", + create_unimplemented_device("riscv.sifive.e.aon", memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size); - sifive_prci_create(memmap[SIFIVE_E_PRCI].base); + sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base); /* GPIO */ @@ -199,19 +192,19 @@ static void riscv_sifive_e_soc_realize(DeviceState *dev, Error **errp) sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base, serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ)); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi0", + create_unimplemented_device("riscv.sifive.e.qspi0", memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm0", + create_unimplemented_device("riscv.sifive.e.pwm0", memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size); sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base, serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ)); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi1", + create_unimplemented_device("riscv.sifive.e.qspi1", memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm1", + create_unimplemented_device("riscv.sifive.e.pwm1", memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.qspi2", + create_unimplemented_device("riscv.sifive.e.qspi2", memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size); - sifive_mmio_emulate(sys_mem, "riscv.sifive.e.pwm2", + create_unimplemented_device("riscv.sifive.e.pwm2", memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size); /* Flash memory */ diff --git a/hw/riscv/sifive_e_prci.c b/hw/riscv/sifive_e_prci.c new file mode 100644 index 0000000000..a1c0d44f18 --- /dev/null +++ b/hw/riscv/sifive_e_prci.c @@ -0,0 +1,124 @@ +/* + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) + * + * Copyright (c) 2017 SiFive, Inc. + * + * Simple model of the PRCI to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/hw.h" +#include "hw/riscv/sifive_e_prci.h" + +static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveEPRCIState *s = opaque; + switch (addr) { + case SIFIVE_E_PRCI_HFROSCCFG: + return s->hfrosccfg; + case SIFIVE_E_PRCI_HFXOSCCFG: + return s->hfxosccfg; + case SIFIVE_E_PRCI_PLLCFG: + return s->pllcfg; + case SIFIVE_E_PRCI_PLLOUTDIV: + return s->plloutdiv; + } + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%x\n", + __func__, (int)addr); + return 0; +} + +static void sifive_e_prci_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveEPRCIState *s = opaque; + switch (addr) { + case SIFIVE_E_PRCI_HFROSCCFG: + s->hfrosccfg = (uint32_t) val64; + /* OSC stays ready */ + s->hfrosccfg |= SIFIVE_E_PRCI_HFROSCCFG_RDY; + break; + case SIFIVE_E_PRCI_HFXOSCCFG: + s->hfxosccfg = (uint32_t) val64; + /* OSC stays ready */ + s->hfxosccfg |= SIFIVE_E_PRCI_HFXOSCCFG_RDY; + break; + case SIFIVE_E_PRCI_PLLCFG: + s->pllcfg = (uint32_t) val64; + /* PLL stays locked */ + s->pllcfg |= SIFIVE_E_PRCI_PLLCFG_LOCK; + break; + case SIFIVE_E_PRCI_PLLOUTDIV: + s->plloutdiv = (uint32_t) val64; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)val64); + } +} + +static const MemoryRegionOps sifive_e_prci_ops = { + .read = sifive_e_prci_read, + .write = sifive_e_prci_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static void sifive_e_prci_init(Object *obj) +{ + SiFiveEPRCIState *s = SIFIVE_E_PRCI(obj); + + memory_region_init_io(&s->mmio, obj, &sifive_e_prci_ops, s, + TYPE_SIFIVE_E_PRCI, SIFIVE_E_PRCI_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); + + s->hfrosccfg = (SIFIVE_E_PRCI_HFROSCCFG_RDY | SIFIVE_E_PRCI_HFROSCCFG_EN); + s->hfxosccfg = (SIFIVE_E_PRCI_HFXOSCCFG_RDY | SIFIVE_E_PRCI_HFXOSCCFG_EN); + s->pllcfg = (SIFIVE_E_PRCI_PLLCFG_REFSEL | SIFIVE_E_PRCI_PLLCFG_BYPASS | + SIFIVE_E_PRCI_PLLCFG_LOCK); + s->plloutdiv = SIFIVE_E_PRCI_PLLOUTDIV_DIV1; +} + +static const TypeInfo sifive_e_prci_info = { + .name = TYPE_SIFIVE_E_PRCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveEPRCIState), + .instance_init = sifive_e_prci_init, +}; + +static void sifive_e_prci_register_types(void) +{ + type_register_static(&sifive_e_prci_info); +} + +type_init(sifive_e_prci_register_types) + + +/* + * Create PRCI device. + */ +DeviceState *sifive_e_prci_create(hwaddr addr) +{ + DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_E_PRCI); + qdev_init_nofail(dev); + sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); + return dev; +} diff --git a/hw/riscv/sifive_plic.c b/hw/riscv/sifive_plic.c index 64a1a10380..98e4304b66 100644 --- a/hw/riscv/sifive_plic.c +++ b/hw/riscv/sifive_plic.c @@ -162,18 +162,6 @@ static void sifive_plic_update(SiFivePLICState *plic) } } -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, true); - sifive_plic_update(plic); -} - -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq) -{ - sifive_plic_set_pending(plic, irq, false); - sifive_plic_update(plic); -} - static uint32_t sifive_plic_claim(SiFivePLICState *plic, uint32_t addrid) { int i, j; diff --git a/hw/riscv/sifive_prci.c b/hw/riscv/sifive_prci.c deleted file mode 100644 index 9837b6166f..0000000000 --- a/hw/riscv/sifive_prci.c +++ /dev/null @@ -1,125 +0,0 @@ -/* - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) - * - * Copyright (c) 2017 SiFive, Inc. - * - * Simple model of the PRCI to emulate register reads made by the SDK BSP - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#include "qemu/osdep.h" -#include "hw/hw.h" -#include "hw/sysbus.h" -#include "qemu/module.h" -#include "target/riscv/cpu.h" -#include "hw/hw.h" -#include "hw/riscv/sifive_prci.h" - -static uint64_t sifive_prci_read(void *opaque, hwaddr addr, unsigned int size) -{ - SiFivePRCIState *s = opaque; - switch (addr) { - case SIFIVE_PRCI_HFROSCCFG: - return s->hfrosccfg; - case SIFIVE_PRCI_HFXOSCCFG: - return s->hfxosccfg; - case SIFIVE_PRCI_PLLCFG: - return s->pllcfg; - case SIFIVE_PRCI_PLLOUTDIV: - return s->plloutdiv; - } - hw_error("%s: read: addr=0x%x\n", __func__, (int)addr); - return 0; -} - -static void sifive_prci_write(void *opaque, hwaddr addr, - uint64_t val64, unsigned int size) -{ - SiFivePRCIState *s = opaque; - switch (addr) { - case SIFIVE_PRCI_HFROSCCFG: - s->hfrosccfg = (uint32_t) val64; - /* OSC stays ready */ - s->hfrosccfg |= SIFIVE_PRCI_HFROSCCFG_RDY; - break; - case SIFIVE_PRCI_HFXOSCCFG: - s->hfxosccfg = (uint32_t) val64; - /* OSC stays ready */ - s->hfxosccfg |= SIFIVE_PRCI_HFXOSCCFG_RDY; - break; - case SIFIVE_PRCI_PLLCFG: - s->pllcfg = (uint32_t) val64; - /* PLL stays locked */ - s->pllcfg |= SIFIVE_PRCI_PLLCFG_LOCK; - break; - case SIFIVE_PRCI_PLLOUTDIV: - s->plloutdiv = (uint32_t) val64; - break; - default: - hw_error("%s: bad write: addr=0x%x v=0x%x\n", - __func__, (int)addr, (int)val64); - } -} - -static const MemoryRegionOps sifive_prci_ops = { - .read = sifive_prci_read, - .write = sifive_prci_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid = { - .min_access_size = 4, - .max_access_size = 4 - } -}; - -static void sifive_prci_init(Object *obj) -{ - SiFivePRCIState *s = SIFIVE_PRCI(obj); - - memory_region_init_io(&s->mmio, obj, &sifive_prci_ops, s, - TYPE_SIFIVE_PRCI, 0x8000); - sysbus_init_mmio(SYS_BUS_DEVICE(obj), &s->mmio); - - s->hfrosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); - s->hfxosccfg = (SIFIVE_PRCI_HFROSCCFG_RDY | SIFIVE_PRCI_HFROSCCFG_EN); - s->pllcfg = (SIFIVE_PRCI_PLLCFG_REFSEL | SIFIVE_PRCI_PLLCFG_BYPASS | - SIFIVE_PRCI_PLLCFG_LOCK); - s->plloutdiv = SIFIVE_PRCI_PLLOUTDIV_DIV1; - -} - -static const TypeInfo sifive_prci_info = { - .name = TYPE_SIFIVE_PRCI, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(SiFivePRCIState), - .instance_init = sifive_prci_init, -}; - -static void sifive_prci_register_types(void) -{ - type_register_static(&sifive_prci_info); -} - -type_init(sifive_prci_register_types) - - -/* - * Create PRCI device. - */ -DeviceState *sifive_prci_create(hwaddr addr) -{ - DeviceState *dev = qdev_create(NULL, TYPE_SIFIVE_PRCI); - qdev_init_nofail(dev); - sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, addr); - return dev; -} diff --git a/hw/riscv/sifive_test.c b/hw/riscv/sifive_test.c index afbb3aaf34..339195c6ff 100644 --- a/hw/riscv/sifive_test.c +++ b/hw/riscv/sifive_test.c @@ -19,10 +19,10 @@ */ #include "qemu/osdep.h" -#include "hw/hw.h" #include "hw/sysbus.h" +#include "qemu/log.h" #include "qemu/module.h" -#include "target/riscv/cpu.h" +#include "sysemu/runstate.h" #include "hw/hw.h" #include "hw/riscv/sifive_test.h" @@ -42,12 +42,15 @@ static void sifive_test_write(void *opaque, hwaddr addr, exit(code); case FINISHER_PASS: exit(0); + case FINISHER_RESET: + qemu_system_reset_request(SHUTDOWN_CAUSE_GUEST_RESET); + return; default: break; } } - hw_error("%s: write: addr=0x%x val=0x%016" PRIx64 "\n", - __func__, (int)addr, val64); + qemu_log_mask(LOG_GUEST_ERROR, "%s: write: addr=0x%x val=0x%016" PRIx64 "\n", + __func__, (int)addr, val64); } static const MemoryRegionOps sifive_test_ops = { diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 9910fa6708..9f8e84bf2e 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -3,14 +3,19 @@ * * Copyright (c) 2016-2017 Sagar Karandikar, sagark@eecs.berkeley.edu * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> * * Provides a board compatible with the SiFive Freedom U SDK: * * 0) UART * 1) CLINT (Core Level Interruptor) * 2) PLIC (Platform Level Interrupt Controller) + * 3) PRCI (Power, Reset, Clock, Interrupt) + * 4) OTP (One-Time Programmable) memory with stored serial number + * 5) GEM (Gigabit Ethernet Controller) and management block * - * This board currently uses a hardcoded devicetree that indicates one hart. + * This board currently generates devicetree dynamically that indicates at least + * two harts and up to five harts. * * This program is free software; you can redistribute it and/or modify it * under the terms and conditions of the GNU General Public License, @@ -33,15 +38,17 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "hw/char/serial.h" +#include "hw/cpu/cluster.h" +#include "hw/misc/unimp.h" #include "target/riscv/cpu.h" #include "hw/riscv/riscv_hart.h" #include "hw/riscv/sifive_plic.h" #include "hw/riscv/sifive_clint.h" #include "hw/riscv/sifive_uart.h" -#include "hw/riscv/sifive_prci.h" #include "hw/riscv/sifive_u.h" #include "hw/riscv/boot.h" #include "chardev/char.h" +#include "net/eth.h" #include "sysemu/arch_init.h" #include "sysemu/device_tree.h" #include "sysemu/sysemu.h" @@ -59,23 +66,29 @@ static const struct MemmapEntry { [SIFIVE_U_MROM] = { 0x1000, 0x11000 }, [SIFIVE_U_CLINT] = { 0x2000000, 0x10000 }, [SIFIVE_U_PLIC] = { 0xc000000, 0x4000000 }, - [SIFIVE_U_UART0] = { 0x10013000, 0x1000 }, - [SIFIVE_U_UART1] = { 0x10023000, 0x1000 }, + [SIFIVE_U_PRCI] = { 0x10000000, 0x1000 }, + [SIFIVE_U_UART0] = { 0x10010000, 0x1000 }, + [SIFIVE_U_UART1] = { 0x10011000, 0x1000 }, + [SIFIVE_U_OTP] = { 0x10070000, 0x1000 }, [SIFIVE_U_DRAM] = { 0x80000000, 0x0 }, - [SIFIVE_U_GEM] = { 0x100900FC, 0x2000 }, + [SIFIVE_U_GEM] = { 0x10090000, 0x2000 }, + [SIFIVE_U_GEM_MGMT] = { 0x100a0000, 0x1000 }, }; +#define OTP_SERIAL 1 #define GEM_REVISION 0x10070109 static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { + MachineState *ms = MACHINE(qdev_get_machine()); void *fdt; int cpu; uint32_t *cells; char *nodename; - char ethclk_names[] = "pclk\0hclk\0tx_clk"; - uint32_t plic_phandle, ethclk_phandle, phandle = 1; + char ethclk_names[] = "pclk\0hclk"; + uint32_t plic_phandle, prci_phandle, phandle = 1; + uint32_t hfclk_phandle, rtcclk_phandle, phy_phandle; fdt = s->fdt = create_device_tree(&s->fdt_size); if (!fdt) { @@ -83,8 +96,9 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, exit(1); } - qemu_fdt_setprop_string(fdt, "/", "model", "ucbbar,spike-bare,qemu"); - qemu_fdt_setprop_string(fdt, "/", "compatible", "ucbbar,spike-bare-dev"); + qemu_fdt_setprop_string(fdt, "/", "model", "SiFive HiFive Unleashed A00"); + qemu_fdt_setprop_string(fdt, "/", "compatible", + "sifive,hifive-unleashed-a00"); qemu_fdt_setprop_cell(fdt, "/", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/", "#address-cells", 0x2); @@ -94,6 +108,28 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/soc", "#size-cells", 0x2); qemu_fdt_setprop_cell(fdt, "/soc", "#address-cells", 0x2); + hfclk_phandle = phandle++; + nodename = g_strdup_printf("/hfclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", hfclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "hfclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_HFCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + + rtcclk_phandle = phandle++; + nodename = g_strdup_printf("/rtcclk"); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", rtcclk_phandle); + qemu_fdt_setprop_string(fdt, nodename, "clock-output-names", "rtcclk"); + qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", + SIFIVE_U_RTCCLK_FREQ); + qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); + g_free(nodename); + nodename = g_strdup_printf("/memory@%lx", (long)memmap[SIFIVE_U_DRAM].base); qemu_fdt_add_subnode(fdt, nodename); @@ -109,15 +145,21 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, "/cpus", "#size-cells", 0x0); qemu_fdt_setprop_cell(fdt, "/cpus", "#address-cells", 0x1); - for (cpu = s->soc.cpus.num_harts - 1; cpu >= 0; cpu--) { + for (cpu = ms->smp.cpus - 1; cpu >= 0; cpu--) { int cpu_phandle = phandle++; nodename = g_strdup_printf("/cpus/cpu@%d", cpu); char *intc = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); - char *isa = riscv_isa_string(&s->soc.cpus.harts[cpu]); + char *isa; qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", SIFIVE_U_CLOCK_FREQ); - qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + /* cpu 0 is the management hart that does not have mmu */ + if (cpu != 0) { + qemu_fdt_setprop_string(fdt, nodename, "mmu-type", "riscv,sv48"); + isa = riscv_isa_string(&s->soc.u_cpus.harts[cpu - 1]); + } else { + isa = riscv_isa_string(&s->soc.e_cpus.harts[0]); + } qemu_fdt_setprop_string(fdt, nodename, "riscv,isa", isa); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv"); qemu_fdt_setprop_string(fdt, nodename, "status", "okay"); @@ -125,7 +167,6 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); qemu_fdt_add_subnode(fdt, intc); qemu_fdt_setprop_cell(fdt, intc, "phandle", cpu_phandle); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", cpu_phandle); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -134,8 +175,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, g_free(nodename); } - cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); - for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { + cells = g_new0(uint32_t, ms->smp.cpus * 4); + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { nodename = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); @@ -153,20 +194,41 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, 0x0, memmap[SIFIVE_U_CLINT].base, 0x0, memmap[SIFIVE_U_CLINT].size); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); + cells, ms->smp.cpus * sizeof(uint32_t) * 4); g_free(cells); g_free(nodename); + prci_phandle = phandle++; + nodename = g_strdup_printf("/soc/clock-controller@%lx", + (long)memmap[SIFIVE_U_PRCI].base); + qemu_fdt_add_subnode(fdt, nodename); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + hfclk_phandle, rtcclk_phandle); + qemu_fdt_setprop_cells(fdt, nodename, "reg", + 0x0, memmap[SIFIVE_U_PRCI].base, + 0x0, memmap[SIFIVE_U_PRCI].size); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-prci"); + g_free(nodename); + plic_phandle = phandle++; - cells = g_new0(uint32_t, s->soc.cpus.num_harts * 4); - for (cpu = 0; cpu < s->soc.cpus.num_harts; cpu++) { + cells = g_new0(uint32_t, ms->smp.cpus * 4 - 2); + for (cpu = 0; cpu < ms->smp.cpus; cpu++) { nodename = g_strdup_printf("/cpus/cpu@%d/interrupt-controller", cpu); uint32_t intc_phandle = qemu_fdt_get_phandle(fdt, nodename); - cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); - cells[cpu * 4 + 1] = cpu_to_be32(IRQ_M_EXT); - cells[cpu * 4 + 2] = cpu_to_be32(intc_phandle); - cells[cpu * 4 + 3] = cpu_to_be32(IRQ_S_EXT); + /* cpu 0 is the management hart that does not have S-mode */ + if (cpu == 0) { + cells[0] = cpu_to_be32(intc_phandle); + cells[1] = cpu_to_be32(IRQ_M_EXT); + } else { + cells[cpu * 4 - 2] = cpu_to_be32(intc_phandle); + cells[cpu * 4 - 1] = cpu_to_be32(IRQ_M_EXT); + cells[cpu * 4 + 0] = cpu_to_be32(intc_phandle); + cells[cpu * 4 + 1] = cpu_to_be32(IRQ_S_EXT); + } g_free(nodename); } nodename = g_strdup_printf("/soc/interrupt-controller@%lx", @@ -176,73 +238,70 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); qemu_fdt_setprop(fdt, nodename, "interrupt-controller", NULL, 0); qemu_fdt_setprop(fdt, nodename, "interrupts-extended", - cells, s->soc.cpus.num_harts * sizeof(uint32_t) * 4); + cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t)); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_PLIC].base, 0x0, memmap[SIFIVE_U_PLIC].size); - qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); - qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35); - qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); - ethclk_phandle = phandle++; - nodename = g_strdup_printf("/soc/ethclk"); - qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "fixed-clock"); - qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x0); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_GEM_CLOCK_FREQ); - qemu_fdt_setprop_cell(fdt, nodename, "phandle", ethclk_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", ethclk_phandle); - ethclk_phandle = qemu_fdt_get_phandle(fdt, nodename); - g_free(nodename); - + phy_phandle = phandle++; nodename = g_strdup_printf("/soc/ethernet@%lx", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_string(fdt, nodename, "compatible", "cdns,macb"); + qemu_fdt_setprop_string(fdt, nodename, "compatible", + "sifive,fu540-c000-gem"); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_GEM].base, - 0x0, memmap[SIFIVE_U_GEM].size); + 0x0, memmap[SIFIVE_U_GEM].size, + 0x0, memmap[SIFIVE_U_GEM_MGMT].base, + 0x0, memmap[SIFIVE_U_GEM_MGMT].size); qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii"); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_GEM_IRQ); qemu_fdt_setprop_cells(fdt, nodename, "clocks", - ethclk_phandle, ethclk_phandle, ethclk_phandle); - qemu_fdt_setprop(fdt, nodename, "clocks-names", ethclk_names, + prci_phandle, PRCI_CLK_GEMGXLPLL, prci_phandle, PRCI_CLK_GEMGXLPLL); + qemu_fdt_setprop(fdt, nodename, "clock-names", ethclk_names, sizeof(ethclk_names)); - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", 1); - qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0); + qemu_fdt_setprop(fdt, nodename, "local-mac-address", + s->soc.gem.conf.macaddr.a, ETH_ALEN); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", 1); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0); g_free(nodename); nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0", (long)memmap[SIFIVE_U_GEM].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0); g_free(nodename); - nodename = g_strdup_printf("/soc/uart@%lx", + nodename = g_strdup_printf("/soc/serial@%lx", (long)memmap[SIFIVE_U_UART0].base); qemu_fdt_add_subnode(fdt, nodename); qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0"); qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[SIFIVE_U_UART0].base, 0x0, memmap[SIFIVE_U_UART0].size); - qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", - SIFIVE_U_CLOCK_FREQ / 2); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); + qemu_fdt_setprop_cells(fdt, nodename, "clocks", + prci_phandle, PRCI_CLK_TLCLK); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", SIFIVE_U_UART0_IRQ); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); if (cmdline) { qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } + + qemu_fdt_add_subnode(fdt, "/aliases"); + qemu_fdt_setprop_string(fdt, "/aliases", "serial0", nodename); + g_free(nodename); } @@ -275,7 +334,18 @@ static void riscv_sifive_u_init(MachineState *machine) memmap[SIFIVE_U_DRAM].base); if (machine->kernel_filename) { - riscv_load_kernel(machine->kernel_filename); + uint64_t kernel_entry = riscv_load_kernel(machine->kernel_filename); + + if (machine->initrd_filename) { + hwaddr start; + hwaddr end = riscv_load_initrd(machine->initrd_filename, + machine->ram_size, kernel_entry, + &start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", + "linux,initrd-start", start); + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", + end); + } } /* reset vector */ @@ -319,13 +389,37 @@ static void riscv_sifive_u_soc_init(Object *obj) MachineState *ms = MACHINE(qdev_get_machine()); SiFiveUSoCState *s = RISCV_U_SOC(obj); - object_initialize_child(obj, "cpus", &s->cpus, sizeof(s->cpus), - TYPE_RISCV_HART_ARRAY, &error_abort, NULL); - object_property_set_str(OBJECT(&s->cpus), SIFIVE_U_CPU, "cpu-type", - &error_abort); - object_property_set_int(OBJECT(&s->cpus), ms->smp.cpus, "num-harts", - &error_abort); - + object_initialize_child(obj, "e-cluster", &s->e_cluster, + sizeof(s->e_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->e_cluster), "cluster-id", 0); + + object_initialize_child(OBJECT(&s->e_cluster), "e-cpus", + &s->e_cpus, sizeof(s->e_cpus), + TYPE_RISCV_HART_ARRAY, &error_abort, + NULL); + qdev_prop_set_uint32(DEVICE(&s->e_cpus), "num-harts", 1); + qdev_prop_set_uint32(DEVICE(&s->e_cpus), "hartid-base", 0); + qdev_prop_set_string(DEVICE(&s->e_cpus), "cpu-type", SIFIVE_E_CPU); + + object_initialize_child(obj, "u-cluster", &s->u_cluster, + sizeof(s->u_cluster), TYPE_CPU_CLUSTER, + &error_abort, NULL); + qdev_prop_set_uint32(DEVICE(&s->u_cluster), "cluster-id", 1); + + object_initialize_child(OBJECT(&s->u_cluster), "u-cpus", + &s->u_cpus, sizeof(s->u_cpus), + TYPE_RISCV_HART_ARRAY, &error_abort, + NULL); + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "num-harts", ms->smp.cpus - 1); + qdev_prop_set_uint32(DEVICE(&s->u_cpus), "hartid-base", 1); + qdev_prop_set_string(DEVICE(&s->u_cpus), "cpu-type", SIFIVE_U_CPU); + + sysbus_init_child_obj(obj, "prci", &s->prci, sizeof(s->prci), + TYPE_SIFIVE_U_PRCI); + sysbus_init_child_obj(obj, "otp", &s->otp, sizeof(s->otp), + TYPE_SIFIVE_U_OTP); + qdev_prop_set_uint32(DEVICE(&s->otp), "serial", OTP_SERIAL); sysbus_init_child_obj(obj, "gem", &s->gem, sizeof(s->gem), TYPE_CADENCE_GEM); } @@ -344,7 +438,19 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) Error *err = NULL; NICInfo *nd = &nd_table[0]; - object_property_set_bool(OBJECT(&s->cpus), true, "realized", + object_property_set_bool(OBJECT(&s->e_cpus), true, "realized", + &error_abort); + object_property_set_bool(OBJECT(&s->u_cpus), true, "realized", + &error_abort); + /* + * The cluster must be realized after the RISC-V hart array container, + * as the container's CPU object is only created on realize, and the + * CPU must exist and have been parented into the cluster before the + * cluster is realized. + */ + object_property_set_bool(OBJECT(&s->e_cluster), true, "realized", + &error_abort); + object_property_set_bool(OBJECT(&s->u_cluster), true, "realized", &error_abort); /* boot rom */ @@ -359,10 +465,11 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) plic_hart_config = g_malloc0(plic_hart_config_len); for (i = 0; i < ms->smp.cpus; i++) { if (i != 0) { - strncat(plic_hart_config, ",", plic_hart_config_len); + strncat(plic_hart_config, "," SIFIVE_U_PLIC_HART_CONFIG, + plic_hart_config_len); + } else { + strncat(plic_hart_config, "M", plic_hart_config_len); } - strncat(plic_hart_config, SIFIVE_U_PLIC_HART_CONFIG, - plic_hart_config_len); plic_hart_config_len -= (strlen(SIFIVE_U_PLIC_HART_CONFIG) + 1); } @@ -386,6 +493,12 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) memmap[SIFIVE_U_CLINT].size, ms->smp.cpus, SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE); + object_property_set_bool(OBJECT(&s->prci), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base); + + object_property_set_bool(OBJECT(&s->otp), true, "realized", &err); + sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base); + for (i = 0; i < SIFIVE_U_PLIC_NUM_SOURCES; i++) { plic_gpios[i] = qdev_get_gpio_in(DEVICE(s->plic), i); } @@ -404,16 +517,18 @@ static void riscv_sifive_u_soc_realize(DeviceState *dev, Error **errp) sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base); sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0, plic_gpios[SIFIVE_U_GEM_IRQ]); + + create_unimplemented_device("riscv.sifive.u.gem-mgmt", + memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size); } static void riscv_sifive_u_machine_init(MachineClass *mc) { mc->desc = "RISC-V Board compatible with SiFive U SDK"; mc->init = riscv_sifive_u_init; - /* The real hardware has 5 CPUs, but one of them is a small embedded power - * management CPU. - */ - mc->max_cpus = 4; + mc->max_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + SIFIVE_U_COMPUTE_CPU_COUNT; + mc->min_cpus = SIFIVE_U_MANAGEMENT_CPU_COUNT + 1; + mc->default_cpus = mc->min_cpus; } DEFINE_MACHINE("sifive_u", riscv_sifive_u_machine_init) diff --git a/hw/riscv/sifive_u_otp.c b/hw/riscv/sifive_u_otp.c new file mode 100644 index 0000000000..ea0eee5678 --- /dev/null +++ b/hw/riscv/sifive_u_otp.c @@ -0,0 +1,191 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * Simple model of the OTP to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/qdev-properties.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/riscv/sifive_u_otp.h" + +static uint64_t sifive_u_otp_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + + switch (addr) { + case SIFIVE_U_OTP_PA: + return s->pa; + case SIFIVE_U_OTP_PAIO: + return s->paio; + case SIFIVE_U_OTP_PAS: + return s->pas; + case SIFIVE_U_OTP_PCE: + return s->pce; + case SIFIVE_U_OTP_PCLK: + return s->pclk; + case SIFIVE_U_OTP_PDIN: + return s->pdin; + case SIFIVE_U_OTP_PDOUT: + if ((s->pce & SIFIVE_U_OTP_PCE_EN) && + (s->pdstb & SIFIVE_U_OTP_PDSTB_EN) && + (s->ptrim & SIFIVE_U_OTP_PTRIM_EN)) { + return s->fuse[s->pa & SIFIVE_U_OTP_PA_MASK]; + } else { + return 0xff; + } + case SIFIVE_U_OTP_PDSTB: + return s->pdstb; + case SIFIVE_U_OTP_PPROG: + return s->pprog; + case SIFIVE_U_OTP_PTC: + return s->ptc; + case SIFIVE_U_OTP_PTM: + return s->ptm; + case SIFIVE_U_OTP_PTM_REP: + return s->ptm_rep; + case SIFIVE_U_OTP_PTR: + return s->ptr; + case SIFIVE_U_OTP_PTRIM: + return s->ptrim; + case SIFIVE_U_OTP_PWE: + return s->pwe; + } + + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n", + __func__, addr); + return 0; +} + +static void sifive_u_otp_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveUOTPState *s = opaque; + uint32_t val32 = (uint32_t)val64; + + switch (addr) { + case SIFIVE_U_OTP_PA: + s->pa = val32 & SIFIVE_U_OTP_PA_MASK; + break; + case SIFIVE_U_OTP_PAIO: + s->paio = val32; + break; + case SIFIVE_U_OTP_PAS: + s->pas = val32; + break; + case SIFIVE_U_OTP_PCE: + s->pce = val32; + break; + case SIFIVE_U_OTP_PCLK: + s->pclk = val32; + break; + case SIFIVE_U_OTP_PDIN: + s->pdin = val32; + break; + case SIFIVE_U_OTP_PDOUT: + /* read-only */ + break; + case SIFIVE_U_OTP_PDSTB: + s->pdstb = val32; + break; + case SIFIVE_U_OTP_PPROG: + s->pprog = val32; + break; + case SIFIVE_U_OTP_PTC: + s->ptc = val32; + break; + case SIFIVE_U_OTP_PTM: + s->ptm = val32; + break; + case SIFIVE_U_OTP_PTM_REP: + s->ptm_rep = val32; + break; + case SIFIVE_U_OTP_PTR: + s->ptr = val32; + break; + case SIFIVE_U_OTP_PTRIM: + s->ptrim = val32; + break; + case SIFIVE_U_OTP_PWE: + s->pwe = val32; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx + " v=0x%x\n", __func__, addr, val32); + } +} + +static const MemoryRegionOps sifive_u_otp_ops = { + .read = sifive_u_otp_read, + .write = sifive_u_otp_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static Property sifive_u_otp_properties[] = { + DEFINE_PROP_UINT32("serial", SiFiveUOTPState, serial, 0), + DEFINE_PROP_END_OF_LIST(), +}; + +static void sifive_u_otp_realize(DeviceState *dev, Error **errp) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_otp_ops, s, + TYPE_SIFIVE_U_OTP, SIFIVE_U_OTP_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); +} + +static void sifive_u_otp_reset(DeviceState *dev) +{ + SiFiveUOTPState *s = SIFIVE_U_OTP(dev); + + /* Initialize all fuses' initial value to 0xFFs */ + memset(s->fuse, 0xff, sizeof(s->fuse)); + + /* Make a valid content of serial number */ + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR] = s->serial; + s->fuse[SIFIVE_U_OTP_SERIAL_ADDR + 1] = ~(s->serial); +} + +static void sifive_u_otp_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->props = sifive_u_otp_properties; + dc->realize = sifive_u_otp_realize; + dc->reset = sifive_u_otp_reset; +} + +static const TypeInfo sifive_u_otp_info = { + .name = TYPE_SIFIVE_U_OTP, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveUOTPState), + .class_init = sifive_u_otp_class_init, +}; + +static void sifive_u_otp_register_types(void) +{ + type_register_static(&sifive_u_otp_info); +} + +type_init(sifive_u_otp_register_types) diff --git a/hw/riscv/sifive_u_prci.c b/hw/riscv/sifive_u_prci.c new file mode 100644 index 0000000000..4fa590c064 --- /dev/null +++ b/hw/riscv/sifive_u_prci.c @@ -0,0 +1,169 @@ +/* + * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * Simple model of the PRCI to emulate register reads made by the SDK BSP + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "hw/sysbus.h" +#include "qemu/log.h" +#include "qemu/module.h" +#include "hw/riscv/sifive_u_prci.h" + +static uint64_t sifive_u_prci_read(void *opaque, hwaddr addr, unsigned int size) +{ + SiFiveUPRCIState *s = opaque; + + switch (addr) { + case SIFIVE_U_PRCI_HFXOSCCFG: + return s->hfxosccfg; + case SIFIVE_U_PRCI_COREPLLCFG0: + return s->corepllcfg0; + case SIFIVE_U_PRCI_DDRPLLCFG0: + return s->ddrpllcfg0; + case SIFIVE_U_PRCI_DDRPLLCFG1: + return s->ddrpllcfg1; + case SIFIVE_U_PRCI_GEMGXLPLLCFG0: + return s->gemgxlpllcfg0; + case SIFIVE_U_PRCI_GEMGXLPLLCFG1: + return s->gemgxlpllcfg1; + case SIFIVE_U_PRCI_CORECLKSEL: + return s->coreclksel; + case SIFIVE_U_PRCI_DEVICESRESET: + return s->devicesreset; + case SIFIVE_U_PRCI_CLKMUXSTATUS: + return s->clkmuxstatus; + } + + qemu_log_mask(LOG_GUEST_ERROR, "%s: read: addr=0x%" HWADDR_PRIx "\n", + __func__, addr); + + return 0; +} + +static void sifive_u_prci_write(void *opaque, hwaddr addr, + uint64_t val64, unsigned int size) +{ + SiFiveUPRCIState *s = opaque; + uint32_t val32 = (uint32_t)val64; + + switch (addr) { + case SIFIVE_U_PRCI_HFXOSCCFG: + s->hfxosccfg = val32; + /* OSC stays ready */ + s->hfxosccfg |= SIFIVE_U_PRCI_HFXOSCCFG_RDY; + break; + case SIFIVE_U_PRCI_COREPLLCFG0: + s->corepllcfg0 = val32; + /* internal feedback */ + s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE; + /* PLL stays locked */ + s->corepllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK; + break; + case SIFIVE_U_PRCI_DDRPLLCFG0: + s->ddrpllcfg0 = val32; + /* internal feedback */ + s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE; + /* PLL stays locked */ + s->ddrpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK; + break; + case SIFIVE_U_PRCI_DDRPLLCFG1: + s->ddrpllcfg1 = val32; + break; + case SIFIVE_U_PRCI_GEMGXLPLLCFG0: + s->gemgxlpllcfg0 = val32; + /* internal feedback */ + s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_FSE; + /* PLL stays locked */ + s->gemgxlpllcfg0 |= SIFIVE_U_PRCI_PLLCFG0_LOCK; + break; + case SIFIVE_U_PRCI_GEMGXLPLLCFG1: + s->gemgxlpllcfg1 = val32; + break; + case SIFIVE_U_PRCI_CORECLKSEL: + s->coreclksel = val32; + break; + case SIFIVE_U_PRCI_DEVICESRESET: + s->devicesreset = val32; + break; + case SIFIVE_U_PRCI_CLKMUXSTATUS: + s->clkmuxstatus = val32; + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%" HWADDR_PRIx + " v=0x%x\n", __func__, addr, val32); + } +} + +static const MemoryRegionOps sifive_u_prci_ops = { + .read = sifive_u_prci_read, + .write = sifive_u_prci_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid = { + .min_access_size = 4, + .max_access_size = 4 + } +}; + +static void sifive_u_prci_realize(DeviceState *dev, Error **errp) +{ + SiFiveUPRCIState *s = SIFIVE_U_PRCI(dev); + + memory_region_init_io(&s->mmio, OBJECT(dev), &sifive_u_prci_ops, s, + TYPE_SIFIVE_U_PRCI, SIFIVE_U_PRCI_REG_SIZE); + sysbus_init_mmio(SYS_BUS_DEVICE(dev), &s->mmio); +} + +static void sifive_u_prci_reset(DeviceState *dev) +{ + SiFiveUPRCIState *s = SIFIVE_U_PRCI(dev); + + /* Initialize register to power-on-reset values */ + s->hfxosccfg = SIFIVE_U_PRCI_HFXOSCCFG_RDY | SIFIVE_U_PRCI_HFXOSCCFG_EN; + s->corepllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF | + SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE | + SIFIVE_U_PRCI_PLLCFG0_LOCK; + s->ddrpllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF | + SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE | + SIFIVE_U_PRCI_PLLCFG0_LOCK; + s->gemgxlpllcfg0 = SIFIVE_U_PRCI_PLLCFG0_DIVR | SIFIVE_U_PRCI_PLLCFG0_DIVF | + SIFIVE_U_PRCI_PLLCFG0_DIVQ | SIFIVE_U_PRCI_PLLCFG0_FSE | + SIFIVE_U_PRCI_PLLCFG0_LOCK; + s->coreclksel = SIFIVE_U_PRCI_CORECLKSEL_HFCLK; +} + +static void sifive_u_prci_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = sifive_u_prci_realize; + dc->reset = sifive_u_prci_reset; +} + +static const TypeInfo sifive_u_prci_info = { + .name = TYPE_SIFIVE_U_PRCI, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(SiFiveUPRCIState), + .class_init = sifive_u_prci_class_init, +}; + +static void sifive_u_prci_register_types(void) +{ + type_register_static(&sifive_u_prci_info); +} + +type_init(sifive_u_prci_register_types) diff --git a/hw/riscv/sifive_uart.c b/hw/riscv/sifive_uart.c index 9de42b1680..a403ae90f5 100644 --- a/hw/riscv/sifive_uart.c +++ b/hw/riscv/sifive_uart.c @@ -18,10 +18,10 @@ #include "qemu/osdep.h" #include "qapi/error.h" +#include "qemu/log.h" #include "hw/sysbus.h" #include "chardev/char.h" #include "chardev/char-fe.h" -#include "target/riscv/cpu.h" #include "hw/hw.h" #include "hw/irq.h" #include "hw/riscv/sifive_uart.h" @@ -95,8 +95,8 @@ uart_read(void *opaque, hwaddr addr, unsigned int size) return s->div; } - hw_error("%s: bad read: addr=0x%x\n", - __func__, (int)addr); + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad read: addr=0x%x\n", + __func__, (int)addr); return 0; } @@ -127,8 +127,8 @@ uart_write(void *opaque, hwaddr addr, s->div = val64; return; } - hw_error("%s: bad write: addr=0x%x v=0x%x\n", - __func__, (int)addr, (int)value); + qemu_log_mask(LOG_GUEST_ERROR, "%s: bad write: addr=0x%x v=0x%x\n", + __func__, (int)addr, (int)value); } static const MemoryRegionOps uart_ops = { diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index 7c04bd554f..d60415d190 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -112,7 +112,6 @@ static void create_fdt(SpikeState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); qemu_fdt_add_subnode(fdt, intc); qemu_fdt_setprop_cell(fdt, intc, "phandle", 1); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", 1); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 9bced28486..d36f5625ec 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -112,7 +112,7 @@ static void create_pcie_irq_map(void *fdt, char *nodename, 0x1800, 0, 0, 0x7); } -static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, +static void create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, uint64_t mem_size, const char *cmdline) { void *fdt; @@ -170,11 +170,9 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cell(fdt, nodename, "reg", cpu); qemu_fdt_setprop_string(fdt, nodename, "device_type", "cpu"); qemu_fdt_setprop_cell(fdt, nodename, "phandle", cpu_phandle); - qemu_fdt_setprop_cell(fdt, nodename, "linux,phandle", cpu_phandle); intc_phandle = phandle++; qemu_fdt_add_subnode(fdt, intc); qemu_fdt_setprop_cell(fdt, intc, "phandle", intc_phandle); - qemu_fdt_setprop_cell(fdt, intc, "linux,phandle", intc_phandle); qemu_fdt_setprop_string(fdt, intc, "compatible", "riscv,cpu-intc"); qemu_fdt_setprop(fdt, intc, "interrupt-controller", NULL, 0); qemu_fdt_setprop_cell(fdt, intc, "#interrupt-cells", 1); @@ -235,8 +233,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, nodename = g_strdup_printf("/soc/interrupt-controller@%lx", (long)memmap[VIRT_PLIC].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", - FDT_PLIC_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", + FDT_PLIC_ADDR_CELLS); qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", FDT_PLIC_INT_CELLS); qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0"); @@ -246,11 +244,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[VIRT_PLIC].base, 0x0, memmap[VIRT_PLIC].size); - qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control"); - qemu_fdt_setprop_cell(fdt, nodename, "riscv,max-priority", 7); qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", VIRTIO_NDEV); - qemu_fdt_setprop_cells(fdt, nodename, "phandle", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "linux,phandle", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle); plic_phandle = qemu_fdt_get_phandle(fdt, nodename); g_free(cells); g_free(nodename); @@ -263,19 +258,19 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[VIRT_VIRTIO].base + i * memmap[VIRT_VIRTIO].size, 0x0, memmap[VIRT_VIRTIO].size); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", VIRTIO_IRQ + i); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", VIRTIO_IRQ + i); g_free(nodename); } nodename = g_strdup_printf("/soc/pci@%lx", (long) memmap[VIRT_PCIE_ECAM].base); qemu_fdt_add_subnode(fdt, nodename); - qemu_fdt_setprop_cells(fdt, nodename, "#address-cells", - FDT_PCI_ADDR_CELLS); - qemu_fdt_setprop_cells(fdt, nodename, "#interrupt-cells", - FDT_PCI_INT_CELLS); - qemu_fdt_setprop_cells(fdt, nodename, "#size-cells", 0x2); + qemu_fdt_setprop_cell(fdt, nodename, "#address-cells", + FDT_PCI_ADDR_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", + FDT_PCI_INT_CELLS); + qemu_fdt_setprop_cell(fdt, nodename, "#size-cells", 0x2); qemu_fdt_setprop_string(fdt, nodename, "compatible", "pci-host-ecam-generic"); qemu_fdt_setprop_string(fdt, nodename, "device_type", "pci"); @@ -312,8 +307,8 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, 0x0, memmap[VIRT_UART0].base, 0x0, memmap[VIRT_UART0].size); qemu_fdt_setprop_cell(fdt, nodename, "clock-frequency", 3686400); - qemu_fdt_setprop_cells(fdt, nodename, "interrupt-parent", plic_phandle); - qemu_fdt_setprop_cells(fdt, nodename, "interrupts", UART0_IRQ); + qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle); + qemu_fdt_setprop_cell(fdt, nodename, "interrupts", UART0_IRQ); qemu_fdt_add_subnode(fdt, "/chosen"); qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename); @@ -321,8 +316,6 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_string(fdt, "/chosen", "bootargs", cmdline); } g_free(nodename); - - return fdt; } @@ -378,7 +371,6 @@ static void riscv_virt_board_init(MachineState *machine) size_t plic_hart_config_len; int i; unsigned int smp_cpus = machine->smp.cpus; - void *fdt; /* Initialize SOC */ object_initialize_child(OBJECT(machine), "soc", &s->soc, sizeof(s->soc), @@ -397,7 +389,7 @@ static void riscv_virt_board_init(MachineState *machine) main_mem); /* create device tree */ - fdt = create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); + create_fdt(s, memmap, machine->ram_size, machine->kernel_cmdline); /* boot rom */ memory_region_init_rom(mask_rom, NULL, "riscv_virt_board.mrom", @@ -416,9 +408,9 @@ static void riscv_virt_board_init(MachineState *machine) hwaddr end = riscv_load_initrd(machine->initrd_filename, machine->ram_size, kernel_entry, &start); - qemu_fdt_setprop_cell(fdt, "/chosen", + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-start", start); - qemu_fdt_setprop_cell(fdt, "/chosen", "linux,initrd-end", + qemu_fdt_setprop_cell(s->fdt, "/chosen", "linux,initrd-end", end); } } diff --git a/hw/s390x/s390-skeys.c b/hw/s390x/s390-skeys.c index d4807f7777..bd37f39120 100644 --- a/hw/s390x/s390-skeys.c +++ b/hw/s390x/s390-skeys.c @@ -389,7 +389,7 @@ static inline void s390_skeys_set_migration_enabled(Object *obj, bool value, ss->migration_enabled = value; if (ss->migration_enabled) { - register_savevm_live(NULL, TYPE_S390_SKEYS, 0, 1, + register_savevm_live(TYPE_S390_SKEYS, 0, 1, &savevm_s390_storage_keys, ss); } else { unregister_savevm(DEVICE(ss), TYPE_S390_SKEYS, ss); diff --git a/hw/s390x/s390-stattrib.c b/hw/s390x/s390-stattrib.c index eda5ca3bb6..bf5ac014c4 100644 --- a/hw/s390x/s390-stattrib.c +++ b/hw/s390x/s390-stattrib.c @@ -381,7 +381,7 @@ static void s390_stattrib_instance_init(Object *obj) { S390StAttribState *sas = S390_STATTRIB(obj); - register_savevm_live(NULL, TYPE_S390_STATTRIB, 0, 0, + register_savevm_live(TYPE_S390_STATTRIB, 0, 0, &savevm_s390_stattrib_handlers, sas); object_property_add_bool(obj, "migration-enabled", diff --git a/hw/s390x/tod.c b/hw/s390x/tod.c index 1bf0875afa..2499d6f656 100644 --- a/hw/s390x/tod.c +++ b/hw/s390x/tod.c @@ -101,7 +101,7 @@ static void s390_tod_realize(DeviceState *dev, Error **errp) S390TODState *td = S390_TOD(dev); /* Legacy migration interface */ - register_savevm_live(NULL, "todclock", 0, 1, &savevm_tod, td); + register_savevm_live("todclock", 0, 1, &savevm_tod, td); } static void s390_tod_class_init(ObjectClass *oc, void *data) diff --git a/hw/scsi/trace-events b/hw/scsi/trace-events index 452b5994e6..b0820052f8 100644 --- a/hw/scsi/trace-events +++ b/hw/scsi/trace-events @@ -28,7 +28,7 @@ mptsas_mmio_read(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x val mptsas_mmio_unhandled_read(void *dev, uint32_t addr) "dev %p addr 0x%08x" mptsas_mmio_unhandled_write(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%x" mptsas_mmio_write(void *dev, uint32_t addr, uint32_t val) "dev %p addr 0x%08x value 0x%x" -mptsas_process_message(void *dev, int msg, uint32_t ctx) "dev %p cmd %d context 0x%08x\n" +mptsas_process_message(void *dev, int msg, uint32_t ctx) "dev %p cmd %d context 0x%08x" mptsas_process_scsi_io_request(void *dev, int bus, int target, int lun, uint64_t len) "dev %p dev %d:%d:%d length %"PRIu64"" mptsas_reset(void *dev) "dev %p " mptsas_scsi_overflow(void *dev, uint32_t ctx, uint64_t req, uint64_t found) "dev %p context 0x%08x: %"PRIu64"/%"PRIu64"" diff --git a/hw/sd/trace-events b/hw/sd/trace-events index 52971dc033..efcff666a2 100644 --- a/hw/sd/trace-events +++ b/hw/sd/trace-events @@ -4,7 +4,7 @@ bcm2835_sdhost_read(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" bcm2835_sdhost_write(uint64_t offset, uint64_t data, unsigned size) "offset 0x%" PRIx64 " data 0x%" PRIx64 " size %u" bcm2835_sdhost_edm_change(const char *why, uint32_t edm) "(%s) EDM now 0x%x" -bcm2835_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x\n" +bcm2835_sdhost_update_irq(uint32_t irq) "IRQ bits 0x%x" # core.c sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg) "@%s CMD%02d arg 0x%08x" diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 9f3cff5fb6..9ffc7e0117 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -28,6 +28,8 @@ #include "qemu/log.h" #include "qemu/module.h" #include "qemu/error-report.h" +#include "qapi/error.h" +#include "exec/address-spaces.h" #include "hw/irq.h" #include "hw/qdev-properties.h" @@ -75,6 +77,10 @@ #define CTRL_CMD_MASK 0xff #define CTRL_DUMMY_HIGH_SHIFT 14 #define CTRL_AST2400_SPI_4BYTE (1 << 13) +#define CE_CTRL_CLOCK_FREQ_SHIFT 8 +#define CE_CTRL_CLOCK_FREQ_MASK 0xf +#define CE_CTRL_CLOCK_FREQ(div) \ + (((div) & CE_CTRL_CLOCK_FREQ_MASK) << CE_CTRL_CLOCK_FREQ_SHIFT) #define CTRL_DUMMY_LOW_SHIFT 6 /* 2 bits [7:6] */ #define CTRL_CE_STOP_ACTIVE (1 << 2) #define CTRL_CMD_MODE_MASK 0x3 @@ -110,10 +116,10 @@ #define DMA_CTRL_DELAY_SHIFT 8 #define DMA_CTRL_FREQ_MASK 0xf #define DMA_CTRL_FREQ_SHIFT 4 -#define DMA_CTRL_MODE (1 << 3) +#define DMA_CTRL_CALIB (1 << 3) #define DMA_CTRL_CKSUM (1 << 2) -#define DMA_CTRL_DIR (1 << 1) -#define DMA_CTRL_EN (1 << 0) +#define DMA_CTRL_WRITE (1 << 1) +#define DMA_CTRL_ENABLE (1 << 0) /* DMA Flash Side Address */ #define R_DMA_FLASH_ADDR (0x84 / 4) @@ -145,6 +151,24 @@ #define ASPEED_SOC_SPI_FLASH_BASE 0x30000000 #define ASPEED_SOC_SPI2_FLASH_BASE 0x38000000 +/* + * DMA DRAM addresses should be 4 bytes aligned and the valid address + * range is 0x40000000 - 0x5FFFFFFF (AST2400) + * 0x80000000 - 0xBFFFFFFF (AST2500) + * + * DMA flash addresses should be 4 bytes aligned and the valid address + * range is 0x20000000 - 0x2FFFFFFF. + * + * DMA length is from 4 bytes to 32MB + * 0: 4 bytes + * 0x7FFFFF: 32M bytes + */ +#define DMA_DRAM_ADDR(s, val) ((s)->sdram_base | \ + ((val) & (s)->ctrl->dma_dram_mask)) +#define DMA_FLASH_ADDR(s, val) ((s)->ctrl->flash_window_base | \ + ((val) & (s)->ctrl->dma_flash_mask)) +#define DMA_LENGTH(val) ((val) & 0x01FFFFFC) + /* Flash opcodes. */ #define SPI_OP_READ 0x03 /* Read data bytes (low frequency) */ @@ -190,7 +214,7 @@ static const AspeedSegments aspeed_segments_ast2500_spi2[] = { static const AspeedSMCController controllers[] = { { - .name = "aspeed.smc.smc", + .name = "aspeed.smc-ast2400", .r_conf = R_CONF, .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, @@ -203,7 +227,7 @@ static const AspeedSMCController controllers[] = { .has_dma = false, .nregs = ASPEED_SMC_R_SMC_MAX, }, { - .name = "aspeed.smc.fmc", + .name = "aspeed.fmc-ast2400", .r_conf = R_CONF, .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, @@ -214,9 +238,11 @@ static const AspeedSMCController controllers[] = { .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, .has_dma = true, + .dma_flash_mask = 0x0FFFFFFC, + .dma_dram_mask = 0x1FFFFFFC, .nregs = ASPEED_SMC_R_MAX, }, { - .name = "aspeed.smc.spi", + .name = "aspeed.spi1-ast2400", .r_conf = R_SPI_CONF, .r_ce_ctrl = 0xff, .r_ctrl0 = R_SPI_CTRL0, @@ -229,7 +255,7 @@ static const AspeedSMCController controllers[] = { .has_dma = false, .nregs = ASPEED_SMC_R_SPI_MAX, }, { - .name = "aspeed.smc.ast2500-fmc", + .name = "aspeed.fmc-ast2500", .r_conf = R_CONF, .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, @@ -240,9 +266,11 @@ static const AspeedSMCController controllers[] = { .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, .has_dma = true, + .dma_flash_mask = 0x0FFFFFFC, + .dma_dram_mask = 0x3FFFFFFC, .nregs = ASPEED_SMC_R_MAX, }, { - .name = "aspeed.smc.ast2500-spi1", + .name = "aspeed.spi1-ast2500", .r_conf = R_CONF, .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, @@ -255,7 +283,7 @@ static const AspeedSMCController controllers[] = { .has_dma = false, .nregs = ASPEED_SMC_R_MAX, }, { - .name = "aspeed.smc.ast2500-spi2", + .name = "aspeed.spi2-ast2500", .r_conf = R_CONF, .r_ce_ctrl = R_CE_CTRL, .r_ctrl0 = R_CTRL0, @@ -732,9 +760,6 @@ static void aspeed_smc_reset(DeviceState *d) memset(s->regs, 0, sizeof s->regs); - /* Pretend DMA is done (u-boot initialization) */ - s->regs[R_INTR_CTRL] = INTR_CTRL_DMA_STATUS; - /* Unselect all slaves */ for (i = 0; i < s->num_cs; ++i) { s->regs[s->r_ctrl0 + i] |= CTRL_CE_STOP_ACTIVE; @@ -775,6 +800,11 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr == s->r_ce_ctrl || addr == R_INTR_CTRL || addr == R_DUMMY_DATA || + (s->ctrl->has_dma && addr == R_DMA_CTRL) || + (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) || + (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) || + (s->ctrl->has_dma && addr == R_DMA_LEN) || + (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) || (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_slaves) || (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_slaves)) { return s->regs[addr]; @@ -785,6 +815,243 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) } } +static uint8_t aspeed_smc_hclk_divisor(uint8_t hclk_mask) +{ + /* HCLK/1 .. HCLK/16 */ + const uint8_t hclk_divisors[] = { + 15, 7, 14, 6, 13, 5, 12, 4, 11, 3, 10, 2, 9, 1, 8, 0 + }; + int i; + + for (i = 0; i < ARRAY_SIZE(hclk_divisors); i++) { + if (hclk_mask == hclk_divisors[i]) { + return i + 1; + } + } + + qemu_log_mask(LOG_GUEST_ERROR, "invalid HCLK mask %x", hclk_mask); + return 0; +} + +/* + * When doing calibration, the SPI clock rate in the CE0 Control + * Register and the read delay cycles in the Read Timing Compensation + * Register are set using bit[11:4] of the DMA Control Register. + */ +static void aspeed_smc_dma_calibration(AspeedSMCState *s) +{ + uint8_t delay = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; + uint8_t hclk_mask = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; + uint8_t hclk_div = aspeed_smc_hclk_divisor(hclk_mask); + uint32_t hclk_shift = (hclk_div - 1) << 2; + uint8_t cs; + + /* + * The Read Timing Compensation Register values apply to all CS on + * the SPI bus and only HCLK/1 - HCLK/5 can have tunable delays + */ + if (hclk_div && hclk_div < 6) { + s->regs[s->r_timings] &= ~(0xf << hclk_shift); + s->regs[s->r_timings] |= delay << hclk_shift; + } + + /* + * TODO: compute the CS from the DMA address and the segment + * registers. This is not really a problem for now because the + * Timing Register values apply to all CS and software uses CS0 to + * do calibration. + */ + cs = 0; + s->regs[s->r_ctrl0 + cs] &= + ~(CE_CTRL_CLOCK_FREQ_MASK << CE_CTRL_CLOCK_FREQ_SHIFT); + s->regs[s->r_ctrl0 + cs] |= CE_CTRL_CLOCK_FREQ(hclk_div); +} + +/* + * Emulate read errors in the DMA Checksum Register for high + * frequencies and optimistic settings of the Read Timing Compensation + * Register. This will help in tuning the SPI timing calibration + * algorithm. + */ +static bool aspeed_smc_inject_read_failure(AspeedSMCState *s) +{ + uint8_t delay = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_DELAY_SHIFT) & DMA_CTRL_DELAY_MASK; + uint8_t hclk_mask = + (s->regs[R_DMA_CTRL] >> DMA_CTRL_FREQ_SHIFT) & DMA_CTRL_FREQ_MASK; + + /* + * Typical values of a palmetto-bmc machine. + */ + switch (aspeed_smc_hclk_divisor(hclk_mask)) { + case 4 ... 16: + return false; + case 3: /* at least one HCLK cycle delay */ + return (delay & 0x7) < 1; + case 2: /* at least two HCLK cycle delay */ + return (delay & 0x7) < 2; + case 1: /* (> 100MHz) is above the max freq of the controller */ + return true; + default: + g_assert_not_reached(); + } +} + +/* + * Accumulate the result of the reads to provide a checksum that will + * be used to validate the read timing settings. + */ +static void aspeed_smc_dma_checksum(AspeedSMCState *s) +{ + MemTxResult result; + uint32_t data; + + if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: invalid direction for DMA checksum\n", __func__); + return; + } + + if (s->regs[R_DMA_CTRL] & DMA_CTRL_CALIB) { + aspeed_smc_dma_calibration(s); + } + + while (s->regs[R_DMA_LEN]) { + data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n", + __func__, s->regs[R_DMA_FLASH_ADDR]); + return; + } + + /* + * When the DMA is on-going, the DMA registers are updated + * with the current working addresses and length. + */ + s->regs[R_DMA_CHECKSUM] += data; + s->regs[R_DMA_FLASH_ADDR] += 4; + s->regs[R_DMA_LEN] -= 4; + } + + if (s->inject_failure && aspeed_smc_inject_read_failure(s)) { + s->regs[R_DMA_CHECKSUM] = 0xbadc0de; + } + +} + +static void aspeed_smc_dma_rw(AspeedSMCState *s) +{ + MemTxResult result; + uint32_t data; + + while (s->regs[R_DMA_LEN]) { + if (s->regs[R_DMA_CTRL] & DMA_CTRL_WRITE) { + data = address_space_ldl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM read failed @%08x\n", + __func__, s->regs[R_DMA_DRAM_ADDR]); + return; + } + + address_space_stl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], + data, MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash write failed @%08x\n", + __func__, s->regs[R_DMA_FLASH_ADDR]); + return; + } + } else { + data = address_space_ldl_le(&s->flash_as, s->regs[R_DMA_FLASH_ADDR], + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: Flash read failed @%08x\n", + __func__, s->regs[R_DMA_FLASH_ADDR]); + return; + } + + address_space_stl_le(&s->dram_as, s->regs[R_DMA_DRAM_ADDR], + data, MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DRAM write failed @%08x\n", + __func__, s->regs[R_DMA_DRAM_ADDR]); + return; + } + } + + /* + * When the DMA is on-going, the DMA registers are updated + * with the current working addresses and length. + */ + s->regs[R_DMA_FLASH_ADDR] += 4; + s->regs[R_DMA_DRAM_ADDR] += 4; + s->regs[R_DMA_LEN] -= 4; + s->regs[R_DMA_CHECKSUM] += data; + } +} + +static void aspeed_smc_dma_stop(AspeedSMCState *s) +{ + /* + * When the DMA is disabled, INTR_CTRL_DMA_STATUS=0 means the + * engine is idle + */ + s->regs[R_INTR_CTRL] &= ~INTR_CTRL_DMA_STATUS; + s->regs[R_DMA_CHECKSUM] = 0; + + /* + * Lower the DMA irq in any case. The IRQ control register could + * have been cleared before disabling the DMA. + */ + qemu_irq_lower(s->irq); +} + +/* + * When INTR_CTRL_DMA_STATUS=1, the DMA has completed and a new DMA + * can start even if the result of the previous was not collected. + */ +static bool aspeed_smc_dma_in_progress(AspeedSMCState *s) +{ + return s->regs[R_DMA_CTRL] & DMA_CTRL_ENABLE && + !(s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_STATUS); +} + +static void aspeed_smc_dma_done(AspeedSMCState *s) +{ + s->regs[R_INTR_CTRL] |= INTR_CTRL_DMA_STATUS; + if (s->regs[R_INTR_CTRL] & INTR_CTRL_DMA_EN) { + qemu_irq_raise(s->irq); + } +} + +static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl) +{ + if (!(dma_ctrl & DMA_CTRL_ENABLE)) { + s->regs[R_DMA_CTRL] = dma_ctrl; + + aspeed_smc_dma_stop(s); + return; + } + + if (aspeed_smc_dma_in_progress(s)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA in progress\n", __func__); + return; + } + + s->regs[R_DMA_CTRL] = dma_ctrl; + + if (s->regs[R_DMA_CTRL] & DMA_CTRL_CKSUM) { + aspeed_smc_dma_checksum(s); + } else { + aspeed_smc_dma_rw(s); + } + + aspeed_smc_dma_done(s); +} + static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { @@ -810,6 +1077,16 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, } } else if (addr == R_DUMMY_DATA) { s->regs[addr] = value & 0xff; + } else if (addr == R_INTR_CTRL) { + s->regs[addr] = value; + } else if (s->ctrl->has_dma && addr == R_DMA_CTRL) { + aspeed_smc_dma_ctrl(s, value); + } else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) { + s->regs[addr] = DMA_DRAM_ADDR(s, value); + } else if (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) { + s->regs[addr] = DMA_FLASH_ADDR(s, value); + } else if (s->ctrl->has_dma && addr == R_DMA_LEN) { + s->regs[addr] = DMA_LENGTH(value); } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", __func__, addr); @@ -824,6 +1101,28 @@ static const MemoryRegionOps aspeed_smc_ops = { .valid.unaligned = true, }; + +/* + * Initialize the custom address spaces for DMAs + */ +static void aspeed_smc_dma_setup(AspeedSMCState *s, Error **errp) +{ + char *name; + + if (!s->dram_mr) { + error_setg(errp, TYPE_ASPEED_SMC ": 'dram' link not set"); + return; + } + + name = g_strdup_printf("%s-dma-flash", s->ctrl->name); + address_space_init(&s->flash_as, &s->mmio_flash, name); + g_free(name); + + name = g_strdup_printf("%s-dma-dram", s->ctrl->name); + address_space_init(&s->dram_as, s->dram_mr, name); + g_free(name); +} + static void aspeed_smc_realize(DeviceState *dev, Error **errp) { SysBusDevice *sbd = SYS_BUS_DEVICE(dev); @@ -849,10 +1148,12 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) s->num_cs = s->ctrl->max_slaves; } + /* DMA irq. Keep it first for the initialization in the SoC */ + sysbus_init_irq(sbd, &s->irq); + s->spi = ssi_create_bus(dev, "spi"); /* Setup cs_lines for slaves */ - sysbus_init_irq(sbd, &s->irq); s->cs_lines = g_new0(qemu_irq, s->num_cs); ssi_auto_connect_slaves(dev, s->cs_lines, s->spi); @@ -899,6 +1200,11 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) memory_region_add_subregion(&s->mmio_flash, offset, &fl->mmio); offset += fl->size; } + + /* DMA support */ + if (s->ctrl->has_dma) { + aspeed_smc_dma_setup(s, errp); + } } static const VMStateDescription vmstate_aspeed_smc = { @@ -915,7 +1221,10 @@ static const VMStateDescription vmstate_aspeed_smc = { static Property aspeed_smc_properties[] = { DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), + DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0), + DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, + TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/timer/aspeed_timer.c b/hw/timer/aspeed_timer.c index 59c2bbeee6..2bda826882 100644 --- a/hw/timer/aspeed_timer.c +++ b/hw/timer/aspeed_timer.c @@ -93,7 +93,8 @@ static inline uint32_t calculate_rate(struct AspeedTimer *t) { AspeedTimerCtrlState *s = timer_to_ctrl(t); - return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ : s->scu->apb_freq; + return timer_external_clock(t) ? TIMER_CLOCK_EXT_HZ : + aspeed_scu_get_apb_freq(s->scu); } static inline uint32_t calculate_ticks(struct AspeedTimer *t, uint64_t now_ns) diff --git a/hw/virtio/virtio-mmio.c b/hw/virtio/virtio-mmio.c index eccc795f28..3d5ca0f667 100644 --- a/hw/virtio/virtio-mmio.c +++ b/hw/virtio/virtio-mmio.c @@ -50,14 +50,24 @@ OBJECT_CHECK(VirtIOMMIOProxy, (obj), TYPE_VIRTIO_MMIO) #define VIRT_MAGIC 0x74726976 /* 'virt' */ -#define VIRT_VERSION 1 +#define VIRT_VERSION 2 +#define VIRT_VERSION_LEGACY 1 #define VIRT_VENDOR 0x554D4551 /* 'QEMU' */ +typedef struct VirtIOMMIOQueue { + uint16_t num; + bool enabled; + uint32_t desc[2]; + uint32_t avail[2]; + uint32_t used[2]; +} VirtIOMMIOQueue; + typedef struct { /* Generic */ SysBusDevice parent_obj; MemoryRegion iomem; qemu_irq irq; + bool legacy; /* Guest accessible state needing migration and reset */ uint32_t host_features_sel; uint32_t guest_features_sel; @@ -65,6 +75,9 @@ typedef struct { /* virtio-bus */ VirtioBusState bus; bool format_transport_address; + /* Fields only used for non-legacy (v2) devices */ + uint32_t guest_features[2]; + VirtIOMMIOQueue vqs[VIRTIO_QUEUE_MAX]; } VirtIOMMIOProxy; static bool virtio_mmio_ioeventfd_enabled(DeviceState *d) @@ -118,7 +131,11 @@ static uint64_t virtio_mmio_read(void *opaque, hwaddr offset, unsigned size) case VIRTIO_MMIO_MAGIC_VALUE: return VIRT_MAGIC; case VIRTIO_MMIO_VERSION: - return VIRT_VERSION; + if (proxy->legacy) { + return VIRT_VERSION_LEGACY; + } else { + return VIRT_VERSION; + } case VIRTIO_MMIO_VENDOR_ID: return VIRT_VENDOR; default: @@ -149,28 +166,64 @@ static uint64_t virtio_mmio_read(void *opaque, hwaddr offset, unsigned size) case VIRTIO_MMIO_MAGIC_VALUE: return VIRT_MAGIC; case VIRTIO_MMIO_VERSION: - return VIRT_VERSION; + if (proxy->legacy) { + return VIRT_VERSION_LEGACY; + } else { + return VIRT_VERSION; + } case VIRTIO_MMIO_DEVICE_ID: return vdev->device_id; case VIRTIO_MMIO_VENDOR_ID: return VIRT_VENDOR; case VIRTIO_MMIO_DEVICE_FEATURES: - if (proxy->host_features_sel) { - return 0; + if (proxy->legacy) { + if (proxy->host_features_sel) { + return 0; + } else { + return vdev->host_features; + } + } else { + VirtioDeviceClass *vdc = VIRTIO_DEVICE_GET_CLASS(vdev); + return (vdev->host_features & ~vdc->legacy_features) + >> (32 * proxy->host_features_sel); } - return vdev->host_features; case VIRTIO_MMIO_QUEUE_NUM_MAX: if (!virtio_queue_get_num(vdev, vdev->queue_sel)) { return 0; } return VIRTQUEUE_MAX_SIZE; case VIRTIO_MMIO_QUEUE_PFN: + if (!proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from legacy register (0x%" + HWADDR_PRIx ") in non-legacy mode\n", + __func__, offset); + return 0; + } return virtio_queue_get_addr(vdev, vdev->queue_sel) >> proxy->guest_page_shift; + case VIRTIO_MMIO_QUEUE_READY: + if (proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from non-legacy register (0x%" + HWADDR_PRIx ") in legacy mode\n", + __func__, offset); + return 0; + } + return proxy->vqs[vdev->queue_sel].enabled; case VIRTIO_MMIO_INTERRUPT_STATUS: return atomic_read(&vdev->isr); case VIRTIO_MMIO_STATUS: return vdev->status; + case VIRTIO_MMIO_CONFIG_GENERATION: + if (proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: read from non-legacy register (0x%" + HWADDR_PRIx ") in legacy mode\n", + __func__, offset); + return 0; + } + return vdev->generation; case VIRTIO_MMIO_DEVICE_FEATURES_SEL: case VIRTIO_MMIO_DRIVER_FEATURES: case VIRTIO_MMIO_DRIVER_FEATURES_SEL: @@ -180,12 +233,20 @@ static uint64_t virtio_mmio_read(void *opaque, hwaddr offset, unsigned size) case VIRTIO_MMIO_QUEUE_ALIGN: case VIRTIO_MMIO_QUEUE_NOTIFY: case VIRTIO_MMIO_INTERRUPT_ACK: + case VIRTIO_MMIO_QUEUE_DESC_LOW: + case VIRTIO_MMIO_QUEUE_DESC_HIGH: + case VIRTIO_MMIO_QUEUE_AVAIL_LOW: + case VIRTIO_MMIO_QUEUE_AVAIL_HIGH: + case VIRTIO_MMIO_QUEUE_USED_LOW: + case VIRTIO_MMIO_QUEUE_USED_HIGH: qemu_log_mask(LOG_GUEST_ERROR, - "%s: read of write-only register\n", - __func__); + "%s: read of write-only register (0x%" HWADDR_PRIx ")\n", + __func__, offset); return 0; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: bad register offset\n", __func__); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad register offset (0x%" HWADDR_PRIx ")\n", + __func__, offset); return 0; } return 0; @@ -232,17 +293,41 @@ static void virtio_mmio_write(void *opaque, hwaddr offset, uint64_t value, } switch (offset) { case VIRTIO_MMIO_DEVICE_FEATURES_SEL: - proxy->host_features_sel = value; + if (value) { + proxy->host_features_sel = 1; + } else { + proxy->host_features_sel = 0; + } break; case VIRTIO_MMIO_DRIVER_FEATURES: - if (!proxy->guest_features_sel) { - virtio_set_features(vdev, value); + if (proxy->legacy) { + if (proxy->guest_features_sel) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: attempt to write guest features with " + "guest_features_sel > 0 in legacy mode\n", + __func__); + } else { + virtio_set_features(vdev, value); + } + } else { + proxy->guest_features[proxy->guest_features_sel] = value; } break; case VIRTIO_MMIO_DRIVER_FEATURES_SEL: - proxy->guest_features_sel = value; + if (value) { + proxy->guest_features_sel = 1; + } else { + proxy->guest_features_sel = 0; + } break; case VIRTIO_MMIO_GUEST_PAGE_SIZE: + if (!proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to legacy register (0x%" + HWADDR_PRIx ") in non-legacy mode\n", + __func__, offset); + return; + } proxy->guest_page_shift = ctz32(value); if (proxy->guest_page_shift > 31) { proxy->guest_page_shift = 0; @@ -256,15 +341,31 @@ static void virtio_mmio_write(void *opaque, hwaddr offset, uint64_t value, break; case VIRTIO_MMIO_QUEUE_NUM: trace_virtio_mmio_queue_write(value, VIRTQUEUE_MAX_SIZE); - virtio_queue_set_num(vdev, vdev->queue_sel, value); - /* Note: only call this function for legacy devices */ - virtio_queue_update_rings(vdev, vdev->queue_sel); + if (proxy->legacy) { + virtio_queue_set_num(vdev, vdev->queue_sel, value); + virtio_queue_update_rings(vdev, vdev->queue_sel); + } else { + proxy->vqs[vdev->queue_sel].num = value; + } break; case VIRTIO_MMIO_QUEUE_ALIGN: - /* Note: this is only valid for legacy devices */ + if (!proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to legacy register (0x%" + HWADDR_PRIx ") in non-legacy mode\n", + __func__, offset); + return; + } virtio_queue_set_align(vdev, vdev->queue_sel, value); break; case VIRTIO_MMIO_QUEUE_PFN: + if (!proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to legacy register (0x%" + HWADDR_PRIx ") in non-legacy mode\n", + __func__, offset); + return; + } if (value == 0) { virtio_reset(vdev); } else { @@ -272,6 +373,29 @@ static void virtio_mmio_write(void *opaque, hwaddr offset, uint64_t value, value << proxy->guest_page_shift); } break; + case VIRTIO_MMIO_QUEUE_READY: + if (proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to non-legacy register (0x%" + HWADDR_PRIx ") in legacy mode\n", + __func__, offset); + return; + } + if (value) { + virtio_queue_set_num(vdev, vdev->queue_sel, + proxy->vqs[vdev->queue_sel].num); + virtio_queue_set_rings(vdev, vdev->queue_sel, + ((uint64_t)proxy->vqs[vdev->queue_sel].desc[1]) << 32 | + proxy->vqs[vdev->queue_sel].desc[0], + ((uint64_t)proxy->vqs[vdev->queue_sel].avail[1]) << 32 | + proxy->vqs[vdev->queue_sel].avail[0], + ((uint64_t)proxy->vqs[vdev->queue_sel].used[1]) << 32 | + proxy->vqs[vdev->queue_sel].used[0]); + proxy->vqs[vdev->queue_sel].enabled = 1; + } else { + proxy->vqs[vdev->queue_sel].enabled = 0; + } + break; case VIRTIO_MMIO_QUEUE_NOTIFY: if (value < VIRTIO_QUEUE_MAX) { virtio_queue_notify(vdev, value); @@ -286,6 +410,12 @@ static void virtio_mmio_write(void *opaque, hwaddr offset, uint64_t value, virtio_mmio_stop_ioeventfd(proxy); } + if (!proxy->legacy && (value & VIRTIO_CONFIG_S_FEATURES_OK)) { + virtio_set_features(vdev, + ((uint64_t)proxy->guest_features[1]) << 32 | + proxy->guest_features[0]); + } + virtio_set_status(vdev, value & 0xff); if (value & VIRTIO_CONFIG_S_DRIVER_OK) { @@ -296,6 +426,66 @@ static void virtio_mmio_write(void *opaque, hwaddr offset, uint64_t value, virtio_reset(vdev); } break; + case VIRTIO_MMIO_QUEUE_DESC_LOW: + if (proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to non-legacy register (0x%" + HWADDR_PRIx ") in legacy mode\n", + __func__, offset); + return; + } + proxy->vqs[vdev->queue_sel].desc[0] = value; + break; + case VIRTIO_MMIO_QUEUE_DESC_HIGH: + if (proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to non-legacy register (0x%" + HWADDR_PRIx ") in legacy mode\n", + __func__, offset); + return; + } + proxy->vqs[vdev->queue_sel].desc[1] = value; + break; + case VIRTIO_MMIO_QUEUE_AVAIL_LOW: + if (proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to non-legacy register (0x%" + HWADDR_PRIx ") in legacy mode\n", + __func__, offset); + return; + } + proxy->vqs[vdev->queue_sel].avail[0] = value; + break; + case VIRTIO_MMIO_QUEUE_AVAIL_HIGH: + if (proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to non-legacy register (0x%" + HWADDR_PRIx ") in legacy mode\n", + __func__, offset); + return; + } + proxy->vqs[vdev->queue_sel].avail[1] = value; + break; + case VIRTIO_MMIO_QUEUE_USED_LOW: + if (proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to non-legacy register (0x%" + HWADDR_PRIx ") in legacy mode\n", + __func__, offset); + return; + } + proxy->vqs[vdev->queue_sel].used[0] = value; + break; + case VIRTIO_MMIO_QUEUE_USED_HIGH: + if (proxy->legacy) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: write to non-legacy register (0x%" + HWADDR_PRIx ") in legacy mode\n", + __func__, offset); + return; + } + proxy->vqs[vdev->queue_sel].used[1] = value; + break; case VIRTIO_MMIO_MAGIC_VALUE: case VIRTIO_MMIO_VERSION: case VIRTIO_MMIO_DEVICE_ID: @@ -303,22 +493,31 @@ static void virtio_mmio_write(void *opaque, hwaddr offset, uint64_t value, case VIRTIO_MMIO_DEVICE_FEATURES: case VIRTIO_MMIO_QUEUE_NUM_MAX: case VIRTIO_MMIO_INTERRUPT_STATUS: + case VIRTIO_MMIO_CONFIG_GENERATION: qemu_log_mask(LOG_GUEST_ERROR, - "%s: write to readonly register\n", - __func__); + "%s: write to read-only register (0x%" HWADDR_PRIx ")\n", + __func__, offset); break; default: - qemu_log_mask(LOG_GUEST_ERROR, "%s: bad register offset\n", __func__); + qemu_log_mask(LOG_GUEST_ERROR, + "%s: bad register offset (0x%" HWADDR_PRIx ")\n", + __func__, offset); } } -static const MemoryRegionOps virtio_mem_ops = { +static const MemoryRegionOps virtio_legacy_mem_ops = { .read = virtio_mmio_read, .write = virtio_mmio_write, .endianness = DEVICE_NATIVE_ENDIAN, }; +static const MemoryRegionOps virtio_mem_ops = { + .read = virtio_mmio_read, + .write = virtio_mmio_write, + .endianness = DEVICE_LITTLE_ENDIAN, +}; + static void virtio_mmio_update_irq(DeviceState *opaque, uint16_t vector) { VirtIOMMIOProxy *proxy = VIRTIO_MMIO(opaque); @@ -352,15 +551,90 @@ static void virtio_mmio_save_config(DeviceState *opaque, QEMUFile *f) qemu_put_be32(f, proxy->guest_page_shift); } +static const VMStateDescription vmstate_virtio_mmio_queue_state = { + .name = "virtio_mmio/queue_state", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT16(num, VirtIOMMIOQueue), + VMSTATE_BOOL(enabled, VirtIOMMIOQueue), + VMSTATE_UINT32_ARRAY(desc, VirtIOMMIOQueue, 2), + VMSTATE_UINT32_ARRAY(avail, VirtIOMMIOQueue, 2), + VMSTATE_UINT32_ARRAY(used, VirtIOMMIOQueue, 2), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_virtio_mmio_state_sub = { + .name = "virtio_mmio/state", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(guest_features, VirtIOMMIOProxy, 2), + VMSTATE_STRUCT_ARRAY(vqs, VirtIOMMIOProxy, VIRTIO_QUEUE_MAX, 0, + vmstate_virtio_mmio_queue_state, + VirtIOMMIOQueue), + VMSTATE_END_OF_LIST() + } +}; + +static const VMStateDescription vmstate_virtio_mmio = { + .name = "virtio_mmio", + .version_id = 1, + .minimum_version_id = 1, + .minimum_version_id_old = 1, + .fields = (VMStateField[]) { + VMSTATE_END_OF_LIST() + }, + .subsections = (const VMStateDescription * []) { + &vmstate_virtio_mmio_state_sub, + NULL + } +}; + +static void virtio_mmio_save_extra_state(DeviceState *opaque, QEMUFile *f) +{ + VirtIOMMIOProxy *proxy = VIRTIO_MMIO(opaque); + + vmstate_save_state(f, &vmstate_virtio_mmio, proxy, NULL); +} + +static int virtio_mmio_load_extra_state(DeviceState *opaque, QEMUFile *f) +{ + VirtIOMMIOProxy *proxy = VIRTIO_MMIO(opaque); + + return vmstate_load_state(f, &vmstate_virtio_mmio, proxy, 1); +} + +static bool virtio_mmio_has_extra_state(DeviceState *opaque) +{ + VirtIOMMIOProxy *proxy = VIRTIO_MMIO(opaque); + + return !proxy->legacy; +} + static void virtio_mmio_reset(DeviceState *d) { VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d); + int i; virtio_mmio_stop_ioeventfd(proxy); virtio_bus_reset(&proxy->bus); proxy->host_features_sel = 0; proxy->guest_features_sel = 0; proxy->guest_page_shift = 0; + + if (!proxy->legacy) { + proxy->guest_features[0] = proxy->guest_features[1] = 0; + + for (i = 0; i < VIRTIO_QUEUE_MAX; i++) { + proxy->vqs[i].enabled = 0; + proxy->vqs[i].num = 0; + proxy->vqs[i].desc[0] = proxy->vqs[i].desc[1] = 0; + proxy->vqs[i].avail[0] = proxy->vqs[i].avail[1] = 0; + proxy->vqs[i].used[0] = proxy->vqs[i].used[1] = 0; + } + } } static int virtio_mmio_set_guest_notifier(DeviceState *d, int n, bool assign, @@ -423,11 +697,22 @@ assign_error: return r; } +static void virtio_mmio_pre_plugged(DeviceState *d, Error **errp) +{ + VirtIOMMIOProxy *proxy = VIRTIO_MMIO(d); + VirtIODevice *vdev = virtio_bus_get_device(&proxy->bus); + + if (!proxy->legacy) { + virtio_add_feature(&vdev->host_features, VIRTIO_F_VERSION_1); + } +} + /* virtio-mmio device */ static Property virtio_mmio_properties[] = { DEFINE_PROP_BOOL("format_transport_address", VirtIOMMIOProxy, format_transport_address, true), + DEFINE_PROP_BOOL("force-legacy", VirtIOMMIOProxy, legacy, true), DEFINE_PROP_END_OF_LIST(), }; @@ -439,8 +724,15 @@ static void virtio_mmio_realizefn(DeviceState *d, Error **errp) qbus_create_inplace(&proxy->bus, sizeof(proxy->bus), TYPE_VIRTIO_MMIO_BUS, d, NULL); sysbus_init_irq(sbd, &proxy->irq); - memory_region_init_io(&proxy->iomem, OBJECT(d), &virtio_mem_ops, proxy, - TYPE_VIRTIO_MMIO, 0x200); + if (proxy->legacy) { + memory_region_init_io(&proxy->iomem, OBJECT(d), + &virtio_legacy_mem_ops, proxy, + TYPE_VIRTIO_MMIO, 0x200); + } else { + memory_region_init_io(&proxy->iomem, OBJECT(d), + &virtio_mem_ops, proxy, + TYPE_VIRTIO_MMIO, 0x200); + } sysbus_init_mmio(sbd, &proxy->iomem); } @@ -511,9 +803,13 @@ static void virtio_mmio_bus_class_init(ObjectClass *klass, void *data) k->notify = virtio_mmio_update_irq; k->save_config = virtio_mmio_save_config; k->load_config = virtio_mmio_load_config; + k->save_extra_state = virtio_mmio_save_extra_state; + k->load_extra_state = virtio_mmio_load_extra_state; + k->has_extra_state = virtio_mmio_has_extra_state; k->set_guest_notifiers = virtio_mmio_set_guest_notifiers; k->ioeventfd_enabled = virtio_mmio_ioeventfd_enabled; k->ioeventfd_assign = virtio_mmio_ioeventfd_assign; + k->pre_plugged = virtio_mmio_pre_plugged; k->has_variable_vring_alignment = true; bus_class->max_dev = 1; bus_class->get_dev_path = virtio_mmio_bus_get_dev_path; diff --git a/include/block/block.h b/include/block/block.h index 124ad40809..37c9de7446 100644 --- a/include/block/block.h +++ b/include/block/block.h @@ -143,7 +143,6 @@ typedef struct HDGeometry { #define BDRV_SECTOR_BITS 9 #define BDRV_SECTOR_SIZE (1ULL << BDRV_SECTOR_BITS) -#define BDRV_SECTOR_MASK ~(BDRV_SECTOR_SIZE - 1) #define BDRV_REQUEST_MAX_SECTORS MIN(SIZE_MAX >> BDRV_SECTOR_BITS, \ INT_MAX >> BDRV_SECTOR_BITS) @@ -195,7 +194,6 @@ typedef struct HDGeometry { #define BDRV_BLOCK_ALLOCATED 0x10 #define BDRV_BLOCK_EOF 0x20 #define BDRV_BLOCK_RECURSE 0x40 -#define BDRV_BLOCK_OFFSET_MASK BDRV_SECTOR_MASK typedef QSIMPLEQ_HEAD(BlockReopenQueue, BlockReopenQueueEntry) BlockReopenQueue; diff --git a/include/block/blockjob_int.h b/include/block/blockjob_int.h index e4a318dd15..e2824a36a8 100644 --- a/include/block/blockjob_int.h +++ b/include/block/blockjob_int.h @@ -52,17 +52,6 @@ struct BlockJobDriver { * besides job->blk to the new AioContext. */ void (*attached_aio_context)(BlockJob *job, AioContext *new_context); - - /* - * If the callback is not NULL, it will be invoked when the job has to be - * synchronously cancelled or completed; it should drain BlockDriverStates - * as required to ensure progress. - * - * Block jobs must use the default implementation for job_driver.drain, - * which will in turn call this callback after doing generic block job - * stuff. - */ - void (*drain)(BlockJob *job); }; /** @@ -108,14 +97,6 @@ void block_job_free(Job *job); void block_job_user_resume(Job *job); /** - * block_job_drain: - * Callback to be used for JobDriver.drain in all block jobs. Drains the main - * block node associated with the block jobs and calls BlockJobDriver.drain for - * job-specific actions. - */ -void block_job_drain(Job *job); - -/** * block_job_ratelimit_get_delay: * * Calculate and return delay for the next request in ns. See the documentation diff --git a/include/exec/memory.h b/include/exec/memory.h index 2dd810259d..a30245c25a 100644 --- a/include/exec/memory.h +++ b/include/exec/memory.h @@ -2201,8 +2201,25 @@ address_space_write_cached(MemoryRegionCache *cache, hwaddr addr, } } +#ifdef NEED_CPU_H /* enum device_endian to MemOp. */ -MemOp devend_memop(enum device_endian end); +static inline MemOp devend_memop(enum device_endian end) +{ + QEMU_BUILD_BUG_ON(DEVICE_HOST_ENDIAN != DEVICE_LITTLE_ENDIAN && + DEVICE_HOST_ENDIAN != DEVICE_BIG_ENDIAN); + +#if defined(HOST_WORDS_BIGENDIAN) != defined(TARGET_WORDS_BIGENDIAN) + /* Swap if non-host endianness or native (target) endianness */ + return (end == DEVICE_HOST_ENDIAN) ? 0 : MO_BSWAP; +#else + const int non_host_endianness = + DEVICE_LITTLE_ENDIAN ^ DEVICE_BIG_ENDIAN ^ DEVICE_HOST_ENDIAN; + + /* In this case, native (target) endianness needs no swap. */ + return (end == non_host_endianness) ? MO_BSWAP : 0; +#endif +} +#endif #endif diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 976fd6be93..ab5052b12c 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -23,6 +23,7 @@ #include "hw/watchdog/wdt_aspeed.h" #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" +#include "hw/gpio/aspeed_gpio.h" #define ASPEED_SPIS_NUM 2 #define ASPEED_WDTS_NUM 3 @@ -48,6 +49,7 @@ typedef struct AspeedSoCState { AspeedSDMCState sdmc; AspeedWDTState wdt[ASPEED_WDTS_NUM]; FTGMAC100State ftgmac100[ASPEED_MACS_NUM]; + AspeedGPIOState gpio; } AspeedSoCState; #define TYPE_ASPEED_SOC "aspeed-soc" @@ -59,8 +61,6 @@ typedef struct AspeedSoCInfo { uint32_t silicon_rev; uint64_t sram_size; int spis_num; - const char *fmc_typename; - const char **spi_typename; int wdts_num; const int *irqmap; const hwaddr *memmap; diff --git a/include/hw/boards.h b/include/hw/boards.h index 2289536e48..be18a5c032 100644 --- a/include/hw/boards.h +++ b/include/hw/boards.h @@ -166,6 +166,13 @@ typedef struct { * The function pointer to hook different machine specific functions for * parsing "smp-opts" from QemuOpts to MachineState::CpuTopology and more * machine specific topology fields, such as smp_dies for PCMachine. + * @hotplug_allowed: + * If the hook is provided, then it'll be called for each device + * hotplug to check whether the device hotplug is allowed. Return + * true to grant allowance or false to reject the hotplug. When + * false is returned, an error must be set to show the reason of + * the rejection. If the hook is not provided, all hotplug will be + * allowed. */ struct MachineClass { /*< private >*/ @@ -224,6 +231,8 @@ struct MachineClass { HotplugHandler *(*get_hotplug_handler)(MachineState *machine, DeviceState *dev); + bool (*hotplug_allowed)(MachineState *state, DeviceState *dev, + Error **errp); CpuInstanceProperties (*cpu_index_to_instance_props)(MachineState *machine, unsigned cpu_index); const CPUArchIdList *(*possible_cpu_arch_ids)(MachineState *machine); diff --git a/include/hw/elf_ops.h b/include/hw/elf_ops.h index 1496d7e753..e07d276df7 100644 --- a/include/hw/elf_ops.h +++ b/include/hw/elf_ops.h @@ -485,6 +485,11 @@ static int glue(load_elf, SZ)(const char *name, int fd, } } + if (mem_size > INT_MAX - total_size) { + ret = ELF_LOAD_TOO_BIG; + goto fail; + } + /* address_offset is hack for kernel images that are linked at the wrong physical address. */ if (translate_fn) { diff --git a/include/hw/gpio/aspeed_gpio.h b/include/hw/gpio/aspeed_gpio.h new file mode 100644 index 0000000000..a2deac046a --- /dev/null +++ b/include/hw/gpio/aspeed_gpio.h @@ -0,0 +1,100 @@ +/* + * ASPEED GPIO Controller + * + * Copyright (C) 2017-2018 IBM Corp. + * + * This code is licensed under the GPL version 2 or later. See + * the COPYING file in the top-level directory. + */ + +#ifndef ASPEED_GPIO_H +#define ASPEED_GPIO_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_GPIO "aspeed.gpio" +#define ASPEED_GPIO(obj) OBJECT_CHECK(AspeedGPIOState, (obj), TYPE_ASPEED_GPIO) +#define ASPEED_GPIO_CLASS(klass) \ + OBJECT_CLASS_CHECK(AspeedGPIOClass, (klass), TYPE_ASPEED_GPIO) +#define ASPEED_GPIO_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AspeedGPIOClass, (obj), TYPE_ASPEED_GPIO) + +#define ASPEED_GPIO_MAX_NR_SETS 8 +#define ASPEED_REGS_PER_BANK 14 +#define ASPEED_GPIO_MAX_NR_REGS (ASPEED_REGS_PER_BANK * ASPEED_GPIO_MAX_NR_SETS) +#define ASPEED_GPIO_NR_PINS 228 +#define ASPEED_GROUPS_PER_SET 4 +#define ASPEED_GPIO_NR_DEBOUNCE_REGS 3 +#define ASPEED_CHARS_PER_GROUP_LABEL 4 + +typedef struct GPIOSets GPIOSets; + +typedef struct GPIOSetProperties { + uint32_t input; + uint32_t output; + char group_label[ASPEED_GROUPS_PER_SET][ASPEED_CHARS_PER_GROUP_LABEL]; +} GPIOSetProperties; + +enum GPIORegType { + gpio_not_a_reg, + gpio_reg_data_value, + gpio_reg_direction, + gpio_reg_int_enable, + gpio_reg_int_sens_0, + gpio_reg_int_sens_1, + gpio_reg_int_sens_2, + gpio_reg_int_status, + gpio_reg_reset_tolerant, + gpio_reg_debounce_1, + gpio_reg_debounce_2, + gpio_reg_cmd_source_0, + gpio_reg_cmd_source_1, + gpio_reg_data_read, + gpio_reg_input_mask, +}; + +typedef struct AspeedGPIOReg { + uint16_t set_idx; + enum GPIORegType type; + } AspeedGPIOReg; + +typedef struct AspeedGPIOClass { + SysBusDevice parent_obj; + const GPIOSetProperties *props; + uint32_t nr_gpio_pins; + uint32_t nr_gpio_sets; + uint32_t gap; + const AspeedGPIOReg *reg_table; +} AspeedGPIOClass; + +typedef struct AspeedGPIOState { + /* <private> */ + SysBusDevice parent; + + /*< public >*/ + MemoryRegion iomem; + int pending; + qemu_irq irq; + qemu_irq gpios[ASPEED_GPIO_NR_PINS]; + +/* Parallel GPIO Registers */ + uint32_t debounce_regs[ASPEED_GPIO_NR_DEBOUNCE_REGS]; + struct GPIOSets { + uint32_t data_value; /* Reflects pin values */ + uint32_t data_read; /* Contains last value written to data value */ + uint32_t direction; + uint32_t int_enable; + uint32_t int_sens_0; + uint32_t int_sens_1; + uint32_t int_sens_2; + uint32_t int_status; + uint32_t reset_tol; + uint32_t cmd_source_0; + uint32_t cmd_source_1; + uint32_t debounce_1; + uint32_t debounce_2; + uint32_t input_mask; + } sets[ASPEED_GPIO_MAX_NR_SETS]; +} AspeedGPIOState; + +#endif /* _ASPEED_GPIO_H_ */ diff --git a/include/hw/i386/pc.h b/include/hw/i386/pc.h index 19a837889d..062feeb69e 100644 --- a/include/hw/i386/pc.h +++ b/include/hw/i386/pc.h @@ -291,17 +291,6 @@ void pc_system_firmware_init(PCMachineState *pcms, MemoryRegion *rom_memory); void pc_madt_cpu_entry(AcpiDeviceIf *adev, int uid, const CPUArchIdList *apic_ids, GArray *entry); -/* e820 types */ -#define E820_RAM 1 -#define E820_RESERVED 2 -#define E820_ACPI 3 -#define E820_NVS 4 -#define E820_UNUSABLE 5 - -int e820_add_entry(uint64_t, uint64_t, uint32_t); -int e820_get_num_entries(void); -bool e820_get_entry(int, uint32_t, uint64_t *, uint64_t *); - extern GlobalProperty pc_compat_4_1[]; extern const size_t pc_compat_4_1_len; diff --git a/include/hw/loader.h b/include/hw/loader.h index 07fd9286e7..48a96cd559 100644 --- a/include/hw/loader.h +++ b/include/hw/loader.h @@ -89,6 +89,7 @@ int load_image_gzipped(const char *filename, hwaddr addr, uint64_t max_sz); #define ELF_LOAD_NOT_ELF -2 #define ELF_LOAD_WRONG_ARCH -3 #define ELF_LOAD_WRONG_ENDIAN -4 +#define ELF_LOAD_TOO_BIG -5 const char *load_elf_strerror(int error); /** load_elf_ram_sym: diff --git a/include/hw/misc/aspeed_scu.h b/include/hw/misc/aspeed_scu.h index 38996adc59..239e94fe2c 100644 --- a/include/hw/misc/aspeed_scu.h +++ b/include/hw/misc/aspeed_scu.h @@ -15,6 +15,8 @@ #define TYPE_ASPEED_SCU "aspeed.scu" #define ASPEED_SCU(obj) OBJECT_CHECK(AspeedSCUState, (obj), TYPE_ASPEED_SCU) +#define TYPE_ASPEED_2400_SCU TYPE_ASPEED_SCU "-ast2400" +#define TYPE_ASPEED_2500_SCU TYPE_ASPEED_SCU "-ast2500" #define ASPEED_SCU_NR_REGS (0x1A8 >> 2) @@ -30,10 +32,6 @@ typedef struct AspeedSCUState { uint32_t hw_strap1; uint32_t hw_strap2; uint32_t hw_prot_key; - - uint32_t clkin; - uint32_t hpll; - uint32_t apb_freq; } AspeedSCUState; #define AST2400_A0_SILICON_REV 0x02000303U @@ -45,8 +43,23 @@ typedef struct AspeedSCUState { extern bool is_supported_silicon_rev(uint32_t silicon_rev); +#define ASPEED_SCU_CLASS(klass) \ + OBJECT_CLASS_CHECK(AspeedSCUClass, (klass), TYPE_ASPEED_SCU) +#define ASPEED_SCU_GET_CLASS(obj) \ + OBJECT_GET_CLASS(AspeedSCUClass, (obj), TYPE_ASPEED_SCU) + +typedef struct AspeedSCUClass { + SysBusDeviceClass parent_class; + + const uint32_t *resets; + uint32_t (*calc_hpll)(AspeedSCUState *s, uint32_t hpll_reg); + uint32_t apb_divider; +} AspeedSCUClass; + #define ASPEED_SCU_PROT_KEY 0x1688A8A8 +uint32_t aspeed_scu_get_apb_freq(AspeedSCUState *s); + /* * Extracted from Aspeed SDK v00.03.21. Fixes and extra definitions * were added. diff --git a/include/hw/qdev-core.h b/include/hw/qdev-core.h index de70b7a19a..aa123f88cb 100644 --- a/include/hw/qdev-core.h +++ b/include/hw/qdev-core.h @@ -280,6 +280,7 @@ void qdev_set_legacy_instance_id(DeviceState *dev, int alias_id, int required_for_version); HotplugHandler *qdev_get_bus_hotplug_handler(DeviceState *dev); HotplugHandler *qdev_get_machine_hotplug_handler(DeviceState *dev); +bool qdev_hotplug_allowed(DeviceState *dev, Error **errp); /** * qdev_get_hotplug_handler: Get handler responsible for device wiring * diff --git a/include/hw/riscv/boot.h b/include/hw/riscv/boot.h index 1f21c2bef1..66075d0e57 100644 --- a/include/hw/riscv/boot.h +++ b/include/hw/riscv/boot.h @@ -25,6 +25,7 @@ void riscv_find_and_load_firmware(MachineState *machine, const char *default_machine_firmware, hwaddr firmware_load_addr); +char *riscv_find_firmware(const char *firmware_filename); target_ulong riscv_load_firmware(const char *firmware_filename, hwaddr firmware_load_addr); target_ulong riscv_load_kernel(const char *kernel_filename); diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h index 3b52b50571..c75856fa73 100644 --- a/include/hw/riscv/riscv_hart.h +++ b/include/hw/riscv/riscv_hart.h @@ -35,6 +35,7 @@ typedef struct RISCVHartArrayState { /*< public >*/ uint32_t num_harts; + uint32_t hartid_base; char *cpu_type; RISCVCPU *harts; } RISCVHartArrayState; diff --git a/include/hw/riscv/sifive_cpu.h b/include/hw/riscv/sifive_cpu.h new file mode 100644 index 0000000000..136799633a --- /dev/null +++ b/include/hw/riscv/sifive_cpu.h @@ -0,0 +1,31 @@ +/* + * SiFive CPU types + * + * Copyright (c) 2017 SiFive, Inc. + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_CPU_H +#define HW_SIFIVE_CPU_H + +#if defined(TARGET_RISCV32) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 +#elif defined(TARGET_RISCV64) +#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 +#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 +#endif + +#endif /* HW_SIFIVE_CPU_H */ diff --git a/include/hw/riscv/sifive_e.h b/include/hw/riscv/sifive_e.h index 9c868dd7f9..25ce7aa9d5 100644 --- a/include/hw/riscv/sifive_e.h +++ b/include/hw/riscv/sifive_e.h @@ -20,6 +20,7 @@ #define HW_SIFIVE_E_H #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_cpu.h" #include "hw/riscv/sifive_gpio.h" #define TYPE_RISCV_E_SOC "riscv.sifive.e.soc" @@ -84,10 +85,4 @@ enum { #define SIFIVE_E_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_E_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E31 -#elif defined(TARGET_RISCV64) -#define SIFIVE_E_CPU TYPE_RISCV_CPU_SIFIVE_E51 -#endif - #endif diff --git a/include/hw/riscv/sifive_e_prci.h b/include/hw/riscv/sifive_e_prci.h new file mode 100644 index 0000000000..698b0b451c --- /dev/null +++ b/include/hw/riscv/sifive_e_prci.h @@ -0,0 +1,71 @@ +/* + * QEMU SiFive E PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2017 SiFive, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_E_PRCI_H +#define HW_SIFIVE_E_PRCI_H + +enum { + SIFIVE_E_PRCI_HFROSCCFG = 0x0, + SIFIVE_E_PRCI_HFXOSCCFG = 0x4, + SIFIVE_E_PRCI_PLLCFG = 0x8, + SIFIVE_E_PRCI_PLLOUTDIV = 0xC +}; + +enum { + SIFIVE_E_PRCI_HFROSCCFG_RDY = (1 << 31), + SIFIVE_E_PRCI_HFROSCCFG_EN = (1 << 30) +}; + +enum { + SIFIVE_E_PRCI_HFXOSCCFG_RDY = (1 << 31), + SIFIVE_E_PRCI_HFXOSCCFG_EN = (1 << 30) +}; + +enum { + SIFIVE_E_PRCI_PLLCFG_PLLSEL = (1 << 16), + SIFIVE_E_PRCI_PLLCFG_REFSEL = (1 << 17), + SIFIVE_E_PRCI_PLLCFG_BYPASS = (1 << 18), + SIFIVE_E_PRCI_PLLCFG_LOCK = (1 << 31) +}; + +enum { + SIFIVE_E_PRCI_PLLOUTDIV_DIV1 = (1 << 8) +}; + +#define SIFIVE_E_PRCI_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_E_PRCI "riscv.sifive.e.prci" + +#define SIFIVE_E_PRCI(obj) \ + OBJECT_CHECK(SiFiveEPRCIState, (obj), TYPE_SIFIVE_E_PRCI) + +typedef struct SiFiveEPRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t hfrosccfg; + uint32_t hfxosccfg; + uint32_t pllcfg; + uint32_t plloutdiv; +} SiFiveEPRCIState; + +DeviceState *sifive_e_prci_create(hwaddr addr); + +#endif diff --git a/include/hw/riscv/sifive_plic.h b/include/hw/riscv/sifive_plic.h index b0edba2884..4421e81249 100644 --- a/include/hw/riscv/sifive_plic.h +++ b/include/hw/riscv/sifive_plic.h @@ -69,9 +69,6 @@ typedef struct SiFivePLICState { uint32_t aperture_size; } SiFivePLICState; -void sifive_plic_raise_irq(SiFivePLICState *plic, uint32_t irq); -void sifive_plic_lower_irq(SiFivePLICState *plic, uint32_t irq); - DeviceState *sifive_plic_create(hwaddr addr, char *hart_config, uint32_t num_sources, uint32_t num_priorities, uint32_t priority_base, uint32_t pending_base, diff --git a/include/hw/riscv/sifive_prci.h b/include/hw/riscv/sifive_prci.h deleted file mode 100644 index 8b7de134f8..0000000000 --- a/include/hw/riscv/sifive_prci.h +++ /dev/null @@ -1,71 +0,0 @@ -/* - * QEMU SiFive PRCI (Power, Reset, Clock, Interrupt) interface - * - * Copyright (c) 2017 SiFive, Inc. - * - * This program is free software; you can redistribute it and/or modify it - * under the terms and conditions of the GNU General Public License, - * version 2 or later, as published by the Free Software Foundation. - * - * This program is distributed in the hope it will be useful, but WITHOUT - * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or - * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for - * more details. - * - * You should have received a copy of the GNU General Public License along with - * this program. If not, see <http://www.gnu.org/licenses/>. - */ - -#ifndef HW_SIFIVE_PRCI_H -#define HW_SIFIVE_PRCI_H - -#include "hw/sysbus.h" - -enum { - SIFIVE_PRCI_HFROSCCFG = 0x0, - SIFIVE_PRCI_HFXOSCCFG = 0x4, - SIFIVE_PRCI_PLLCFG = 0x8, - SIFIVE_PRCI_PLLOUTDIV = 0xC -}; - -enum { - SIFIVE_PRCI_HFROSCCFG_RDY = (1 << 31), - SIFIVE_PRCI_HFROSCCFG_EN = (1 << 30) -}; - -enum { - SIFIVE_PRCI_HFXOSCCFG_RDY = (1 << 31), - SIFIVE_PRCI_HFXOSCCFG_EN = (1 << 30) -}; - -enum { - SIFIVE_PRCI_PLLCFG_PLLSEL = (1 << 16), - SIFIVE_PRCI_PLLCFG_REFSEL = (1 << 17), - SIFIVE_PRCI_PLLCFG_BYPASS = (1 << 18), - SIFIVE_PRCI_PLLCFG_LOCK = (1 << 31) -}; - -enum { - SIFIVE_PRCI_PLLOUTDIV_DIV1 = (1 << 8) -}; - -#define TYPE_SIFIVE_PRCI "riscv.sifive.prci" - -#define SIFIVE_PRCI(obj) \ - OBJECT_CHECK(SiFivePRCIState, (obj), TYPE_SIFIVE_PRCI) - -typedef struct SiFivePRCIState { - /*< private >*/ - SysBusDevice parent_obj; - - /*< public >*/ - MemoryRegion mmio; - uint32_t hfrosccfg; - uint32_t hfxosccfg; - uint32_t pllcfg; - uint32_t plloutdiv; -} SiFivePRCIState; - -DeviceState *sifive_prci_create(hwaddr addr); - -#endif diff --git a/include/hw/riscv/sifive_test.h b/include/hw/riscv/sifive_test.h index 3a603a6ead..1ec416ac1b 100644 --- a/include/hw/riscv/sifive_test.h +++ b/include/hw/riscv/sifive_test.h @@ -36,7 +36,8 @@ typedef struct SiFiveTestState { enum { FINISHER_FAIL = 0x3333, - FINISHER_PASS = 0x5555 + FINISHER_PASS = 0x5555, + FINISHER_RESET = 0x7777 }; DeviceState *sifive_test_create(hwaddr addr); diff --git a/include/hw/riscv/sifive_u.h b/include/hw/riscv/sifive_u.h index be021ce256..e4df298c23 100644 --- a/include/hw/riscv/sifive_u.h +++ b/include/hw/riscv/sifive_u.h @@ -21,6 +21,9 @@ #include "hw/net/cadence_gem.h" #include "hw/riscv/riscv_hart.h" +#include "hw/riscv/sifive_cpu.h" +#include "hw/riscv/sifive_u_prci.h" +#include "hw/riscv/sifive_u_otp.h" #define TYPE_RISCV_U_SOC "riscv.sifive.u.soc" #define RISCV_U_SOC(obj) \ @@ -31,8 +34,13 @@ typedef struct SiFiveUSoCState { SysBusDevice parent_obj; /*< public >*/ - RISCVHartArrayState cpus; + CPUClusterState e_cluster; + CPUClusterState u_cluster; + RISCVHartArrayState e_cpus; + RISCVHartArrayState u_cpus; DeviceState *plic; + SiFiveUPRCIState prci; + SiFiveUOTPState otp; CadenceGEMState gem; } SiFiveUSoCState; @@ -51,23 +59,30 @@ enum { SIFIVE_U_MROM, SIFIVE_U_CLINT, SIFIVE_U_PLIC, + SIFIVE_U_PRCI, SIFIVE_U_UART0, SIFIVE_U_UART1, + SIFIVE_U_OTP, SIFIVE_U_DRAM, - SIFIVE_U_GEM + SIFIVE_U_GEM, + SIFIVE_U_GEM_MGMT }; enum { - SIFIVE_U_UART0_IRQ = 3, - SIFIVE_U_UART1_IRQ = 4, + SIFIVE_U_UART0_IRQ = 4, + SIFIVE_U_UART1_IRQ = 5, SIFIVE_U_GEM_IRQ = 0x35 }; enum { SIFIVE_U_CLOCK_FREQ = 1000000000, - SIFIVE_U_GEM_CLOCK_FREQ = 125000000 + SIFIVE_U_HFCLK_FREQ = 33333333, + SIFIVE_U_RTCCLK_FREQ = 1000000 }; +#define SIFIVE_U_MANAGEMENT_CPU_COUNT 1 +#define SIFIVE_U_COMPUTE_CPU_COUNT 4 + #define SIFIVE_U_PLIC_HART_CONFIG "MS" #define SIFIVE_U_PLIC_NUM_SOURCES 54 #define SIFIVE_U_PLIC_NUM_PRIORITIES 7 @@ -78,10 +93,4 @@ enum { #define SIFIVE_U_PLIC_CONTEXT_BASE 0x200000 #define SIFIVE_U_PLIC_CONTEXT_STRIDE 0x1000 -#if defined(TARGET_RISCV32) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U34 -#elif defined(TARGET_RISCV64) -#define SIFIVE_U_CPU TYPE_RISCV_CPU_SIFIVE_U54 -#endif - #endif diff --git a/include/hw/riscv/sifive_u_otp.h b/include/hw/riscv/sifive_u_otp.h new file mode 100644 index 0000000000..639297564a --- /dev/null +++ b/include/hw/riscv/sifive_u_otp.h @@ -0,0 +1,80 @@ +/* + * QEMU SiFive U OTP (One-Time Programmable) Memory interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_U_OTP_H +#define HW_SIFIVE_U_OTP_H + +#define SIFIVE_U_OTP_PA 0x00 +#define SIFIVE_U_OTP_PAIO 0x04 +#define SIFIVE_U_OTP_PAS 0x08 +#define SIFIVE_U_OTP_PCE 0x0C +#define SIFIVE_U_OTP_PCLK 0x10 +#define SIFIVE_U_OTP_PDIN 0x14 +#define SIFIVE_U_OTP_PDOUT 0x18 +#define SIFIVE_U_OTP_PDSTB 0x1C +#define SIFIVE_U_OTP_PPROG 0x20 +#define SIFIVE_U_OTP_PTC 0x24 +#define SIFIVE_U_OTP_PTM 0x28 +#define SIFIVE_U_OTP_PTM_REP 0x2C +#define SIFIVE_U_OTP_PTR 0x30 +#define SIFIVE_U_OTP_PTRIM 0x34 +#define SIFIVE_U_OTP_PWE 0x38 + +#define SIFIVE_U_OTP_PCE_EN (1 << 0) + +#define SIFIVE_U_OTP_PDSTB_EN (1 << 0) + +#define SIFIVE_U_OTP_PTRIM_EN (1 << 0) + +#define SIFIVE_U_OTP_PA_MASK 0xfff +#define SIFIVE_U_OTP_NUM_FUSES 0x1000 +#define SIFIVE_U_OTP_SERIAL_ADDR 0xfc + +#define SIFIVE_U_OTP_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_OTP "riscv.sifive.u.otp" + +#define SIFIVE_U_OTP(obj) \ + OBJECT_CHECK(SiFiveUOTPState, (obj), TYPE_SIFIVE_U_OTP) + +typedef struct SiFiveUOTPState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t pa; + uint32_t paio; + uint32_t pas; + uint32_t pce; + uint32_t pclk; + uint32_t pdin; + uint32_t pdstb; + uint32_t pprog; + uint32_t ptc; + uint32_t ptm; + uint32_t ptm_rep; + uint32_t ptr; + uint32_t ptrim; + uint32_t pwe; + uint32_t fuse[SIFIVE_U_OTP_NUM_FUSES]; + /* config */ + uint32_t serial; +} SiFiveUOTPState; + +#endif /* HW_SIFIVE_U_OTP_H */ diff --git a/include/hw/riscv/sifive_u_prci.h b/include/hw/riscv/sifive_u_prci.h new file mode 100644 index 0000000000..0a531fdadc --- /dev/null +++ b/include/hw/riscv/sifive_u_prci.h @@ -0,0 +1,91 @@ +/* + * QEMU SiFive U PRCI (Power, Reset, Clock, Interrupt) interface + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#ifndef HW_SIFIVE_U_PRCI_H +#define HW_SIFIVE_U_PRCI_H + +#define SIFIVE_U_PRCI_HFXOSCCFG 0x00 +#define SIFIVE_U_PRCI_COREPLLCFG0 0x04 +#define SIFIVE_U_PRCI_DDRPLLCFG0 0x0C +#define SIFIVE_U_PRCI_DDRPLLCFG1 0x10 +#define SIFIVE_U_PRCI_GEMGXLPLLCFG0 0x1C +#define SIFIVE_U_PRCI_GEMGXLPLLCFG1 0x20 +#define SIFIVE_U_PRCI_CORECLKSEL 0x24 +#define SIFIVE_U_PRCI_DEVICESRESET 0x28 +#define SIFIVE_U_PRCI_CLKMUXSTATUS 0x2C + +/* + * Current FU540-C000 manual says ready bit is at bit 29, but + * freedom-u540-c000-bootloader codes (ux00prci.h) says it is at bit 31. + * We have to trust the actual code that works. + * + * see https://github.com/sifive/freedom-u540-c000-bootloader + */ + +#define SIFIVE_U_PRCI_HFXOSCCFG_EN (1 << 30) +#define SIFIVE_U_PRCI_HFXOSCCFG_RDY (1 << 31) + +/* xxxPLLCFG0 register bits */ +#define SIFIVE_U_PRCI_PLLCFG0_DIVR (1 << 0) +#define SIFIVE_U_PRCI_PLLCFG0_DIVF (31 << 6) +#define SIFIVE_U_PRCI_PLLCFG0_DIVQ (3 << 15) +#define SIFIVE_U_PRCI_PLLCFG0_FSE (1 << 25) +#define SIFIVE_U_PRCI_PLLCFG0_LOCK (1 << 31) + +/* xxxPLLCFG1 register bits */ +#define SIFIVE_U_PRCI_PLLCFG1_CKE (1 << 24) + +/* coreclksel register bits */ +#define SIFIVE_U_PRCI_CORECLKSEL_HFCLK (1 << 0) + + +#define SIFIVE_U_PRCI_REG_SIZE 0x1000 + +#define TYPE_SIFIVE_U_PRCI "riscv.sifive.u.prci" + +#define SIFIVE_U_PRCI(obj) \ + OBJECT_CHECK(SiFiveUPRCIState, (obj), TYPE_SIFIVE_U_PRCI) + +typedef struct SiFiveUPRCIState { + /*< private >*/ + SysBusDevice parent_obj; + + /*< public >*/ + MemoryRegion mmio; + uint32_t hfxosccfg; + uint32_t corepllcfg0; + uint32_t ddrpllcfg0; + uint32_t ddrpllcfg1; + uint32_t gemgxlpllcfg0; + uint32_t gemgxlpllcfg1; + uint32_t coreclksel; + uint32_t devicesreset; + uint32_t clkmuxstatus; +} SiFiveUPRCIState; + +/* + * Clock indexes for use by Device Tree data and the PRCI driver. + * + * These values are from sifive-fu540-prci.h in the Linux kernel. + */ +#define PRCI_CLK_COREPLL 0 +#define PRCI_CLK_DDRPLL 1 +#define PRCI_CLK_GEMGXLPLL 2 +#define PRCI_CLK_TLCLK 3 + +#endif /* HW_SIFIVE_U_PRCI_H */ diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index aa07dac4fe..5176ff6bf9 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -46,6 +46,8 @@ typedef struct AspeedSMCController { hwaddr flash_window_base; uint32_t flash_window_size; bool has_dma; + hwaddr dma_flash_mask; + hwaddr dma_dram_mask; uint32_t nregs; } AspeedSMCController; @@ -86,6 +88,7 @@ typedef struct AspeedSMCState { uint32_t num_cs; qemu_irq *cs_lines; + bool inject_failure; SSIBus *spi; @@ -101,6 +104,10 @@ typedef struct AspeedSMCState { /* for DMA support */ uint64_t sdram_base; + AddressSpace flash_as; + MemoryRegion *dram_mr; + AddressSpace dram_as; + AspeedSMCFlash *flashes; uint8_t snoop_index; diff --git a/include/migration/register.h b/include/migration/register.h index 3d0b9833c6..a13359a08d 100644 --- a/include/migration/register.h +++ b/include/migration/register.h @@ -68,8 +68,7 @@ typedef struct SaveVMHandlers { int (*resume_prepare)(MigrationState *s, void *opaque); } SaveVMHandlers; -int register_savevm_live(DeviceState *dev, - const char *idstr, +int register_savevm_live(const char *idstr, int instance_id, int version_id, const SaveVMHandlers *ops, diff --git a/include/qemu/job.h b/include/qemu/job.h index 73c67d3175..bd59cd8944 100644 --- a/include/qemu/job.h +++ b/include/qemu/job.h @@ -220,13 +220,6 @@ struct JobDriver { */ void (*complete)(Job *job, Error **errp); - /* - * If the callback is not NULL, it will be invoked when the job has to be - * synchronously cancelled or completed; it should drain any activities - * as required to ensure progress. - */ - void (*drain)(Job *job); - /** * If the callback is not NULL, prepare will be invoked when all the jobs * belonging to the same transaction complete; or upon this job's completion @@ -470,12 +463,6 @@ bool job_user_paused(Job *job); */ void job_user_resume(Job *job, Error **errp); -/* - * Drain any activities as required to ensure progress. This can be called in a - * loop to synchronously complete a job. - */ -void job_drain(Job *job); - /** * Get the next element from the list of block jobs after @job, or the * first one if @job is %NULL. diff --git a/include/qemu/memfd.h b/include/qemu/memfd.h index d551c28b68..975b6bdb77 100644 --- a/include/qemu/memfd.h +++ b/include/qemu/memfd.h @@ -32,6 +32,10 @@ #define MFD_HUGE_SHIFT 26 #endif +#if defined CONFIG_LINUX && !defined CONFIG_MEMFD +int memfd_create(const char *name, unsigned int flags); +#endif + int qemu_memfd_create(const char *name, size_t size, bool hugetlb, uint64_t hugetlbsize, unsigned int seals, Error **errp); bool qemu_memfd_alloc_check(void); diff --git a/include/qemu/osdep.h b/include/qemu/osdep.h index af2b91f0b8..c7d242f476 100644 --- a/include/qemu/osdep.h +++ b/include/qemu/osdep.h @@ -571,19 +571,6 @@ void os_mem_prealloc(int fd, char *area, size_t sz, int smp_cpus, Error **errp); /** - * qemu_get_pmem_size: - * @filename: path to a pmem file - * @errp: pointer to a NULL-initialized error object - * - * Determine the size of a persistent memory file. Besides supporting files on - * DAX file systems, this function also supports Linux devdax character - * devices. - * - * Returns: the size or 0 on failure - */ -uint64_t qemu_get_pmem_size(const char *filename, Error **errp); - -/** * qemu_get_pid_name: * @pid: pid of a process * diff --git a/include/qemu/thread.h b/include/qemu/thread.h index 55d83a907c..047db0307e 100644 --- a/include/qemu/thread.h +++ b/include/qemu/thread.h @@ -34,6 +34,8 @@ typedef void (*QemuRecMutexLockFunc)(QemuRecMutex *m, const char *f, int l); typedef int (*QemuRecMutexTrylockFunc)(QemuRecMutex *m, const char *f, int l); typedef void (*QemuCondWaitFunc)(QemuCond *c, QemuMutex *m, const char *f, int l); +typedef bool (*QemuCondTimedWaitFunc)(QemuCond *c, QemuMutex *m, int ms, + const char *f, int l); extern QemuMutexLockFunc qemu_bql_mutex_lock_func; extern QemuMutexLockFunc qemu_mutex_lock_func; @@ -41,6 +43,7 @@ extern QemuMutexTrylockFunc qemu_mutex_trylock_func; extern QemuRecMutexLockFunc qemu_rec_mutex_lock_func; extern QemuRecMutexTrylockFunc qemu_rec_mutex_trylock_func; extern QemuCondWaitFunc qemu_cond_wait_func; +extern QemuCondTimedWaitFunc qemu_cond_timedwait_func; /* convenience macros to bypass the profiler */ #define qemu_mutex_lock__raw(m) \ @@ -63,6 +66,8 @@ extern QemuCondWaitFunc qemu_cond_wait_func; qemu_rec_mutex_trylock_impl(m, __FILE__, __LINE__); #define qemu_cond_wait(c, m) \ qemu_cond_wait_impl(c, m, __FILE__, __LINE__); +#define qemu_cond_timedwait(c, m, ms) \ + qemu_cond_wait_impl(c, m, ms, __FILE__, __LINE__); #else #define qemu_mutex_lock(m) ({ \ QemuMutexLockFunc _f = atomic_read(&qemu_mutex_lock_func); \ @@ -89,6 +94,11 @@ extern QemuCondWaitFunc qemu_cond_wait_func; QemuCondWaitFunc _f = atomic_read(&qemu_cond_wait_func); \ _f(c, m, __FILE__, __LINE__); \ }) + +#define qemu_cond_timedwait(c, m, ms) ({ \ + QemuCondTimedWaitFunc _f = atomic_read(&qemu_cond_timedwait_func); \ + _f(c, m, ms, __FILE__, __LINE__); \ + }) #endif #define qemu_mutex_unlock(mutex) \ @@ -134,12 +144,21 @@ void qemu_cond_signal(QemuCond *cond); void qemu_cond_broadcast(QemuCond *cond); void qemu_cond_wait_impl(QemuCond *cond, QemuMutex *mutex, const char *file, const int line); +bool qemu_cond_timedwait_impl(QemuCond *cond, QemuMutex *mutex, int ms, + const char *file, const int line); static inline void (qemu_cond_wait)(QemuCond *cond, QemuMutex *mutex) { qemu_cond_wait(cond, mutex); } +/* Returns true if timeout has not expired, and false otherwise */ +static inline bool (qemu_cond_timedwait)(QemuCond *cond, QemuMutex *mutex, + int ms) +{ + return qemu_cond_timedwait(cond, mutex, ms); +} + void qemu_sem_init(QemuSemaphore *sem, int init); void qemu_sem_post(QemuSemaphore *sem); void qemu_sem_wait(QemuSemaphore *sem); diff --git a/job.c b/job.c index 28dd48f8a5..04409b40aa 100644 --- a/job.c +++ b/job.c @@ -523,16 +523,6 @@ void coroutine_fn job_sleep_ns(Job *job, int64_t ns) job_pause_point(job); } -void job_drain(Job *job) -{ - /* If job is !busy this kicks it into the next pause point. */ - job_enter(job); - - if (job->driver->drain) { - job->driver->drain(job); - } -} - /* Assumes the block_job_mutex is held */ static bool job_timer_not_pending(Job *job) { @@ -991,7 +981,7 @@ int job_finish_sync(Job *job, void (*finish)(Job *, Error **errp), Error **errp) } AIO_WAIT_WHILE(job->aio_context, - (job_drain(job), !job_is_completed(job))); + (job_enter(job), !job_is_completed(job))); ret = (job_is_cancelled(job) && job->ret == 0) ? -ECANCELED : job->ret; job_unref(job); diff --git a/linux-headers/linux/kvm.h b/linux-headers/linux/kvm.h index c8423e760c..18892d6541 100644 --- a/linux-headers/linux/kvm.h +++ b/linux-headers/linux/kvm.h @@ -696,9 +696,11 @@ struct kvm_ioeventfd { #define KVM_X86_DISABLE_EXITS_MWAIT (1 << 0) #define KVM_X86_DISABLE_EXITS_HLT (1 << 1) #define KVM_X86_DISABLE_EXITS_PAUSE (1 << 2) +#define KVM_X86_DISABLE_EXITS_CSTATE (1 << 3) #define KVM_X86_DISABLE_VALID_EXITS (KVM_X86_DISABLE_EXITS_MWAIT | \ KVM_X86_DISABLE_EXITS_HLT | \ - KVM_X86_DISABLE_EXITS_PAUSE) + KVM_X86_DISABLE_EXITS_PAUSE | \ + KVM_X86_DISABLE_EXITS_CSTATE) /* for KVM_ENABLE_CAP */ struct kvm_enable_cap { diff --git a/linux-user/arm/target_cpu.h b/linux-user/arm/target_cpu.h index 8a3764919a..3f79356a07 100644 --- a/linux-user/arm/target_cpu.h +++ b/linux-user/arm/target_cpu.h @@ -19,9 +19,27 @@ #ifndef ARM_TARGET_CPU_H #define ARM_TARGET_CPU_H -/* We need to be able to map the commpage. - See validate_guest_space in linux-user/elfload.c. */ -#define MAX_RESERVED_VA 0xffff0000ul +static inline unsigned long arm_max_reserved_va(CPUState *cs) +{ + ARMCPU *cpu = ARM_CPU(cs); + + if (arm_feature(&cpu->env, ARM_FEATURE_M)) { + /* + * There are magic return addresses above 0xfe000000, + * and in general a lot of M-profile system stuff in + * the high addresses. Restrict linux-user to the + * cached write-back RAM in the system map. + */ + return 0x80000000ul; + } else { + /* + * We need to be able to map the commpage. + * See validate_guest_space in linux-user/elfload.c. + */ + return 0xffff0000ul; + } +} +#define MAX_RESERVED_VA arm_max_reserved_va static inline void cpu_clone_regs(CPUARMState *env, target_ulong newsp) { diff --git a/linux-user/elfload.c b/linux-user/elfload.c index 3365e192eb..f6693e5760 100644 --- a/linux-user/elfload.c +++ b/linux-user/elfload.c @@ -607,9 +607,23 @@ enum { ARM_HWCAP_A64_SB = 1 << 29, ARM_HWCAP_A64_PACA = 1 << 30, ARM_HWCAP_A64_PACG = 1UL << 31, + + ARM_HWCAP2_A64_DCPODP = 1 << 0, + ARM_HWCAP2_A64_SVE2 = 1 << 1, + ARM_HWCAP2_A64_SVEAES = 1 << 2, + ARM_HWCAP2_A64_SVEPMULL = 1 << 3, + ARM_HWCAP2_A64_SVEBITPERM = 1 << 4, + ARM_HWCAP2_A64_SVESHA3 = 1 << 5, + ARM_HWCAP2_A64_SVESM4 = 1 << 6, + ARM_HWCAP2_A64_FLAGM2 = 1 << 7, + ARM_HWCAP2_A64_FRINT = 1 << 8, }; -#define ELF_HWCAP get_elf_hwcap() +#define ELF_HWCAP get_elf_hwcap() +#define ELF_HWCAP2 get_elf_hwcap2() + +#define GET_FEATURE_ID(feat, hwcap) \ + do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0) static uint32_t get_elf_hwcap(void) { @@ -621,8 +635,6 @@ static uint32_t get_elf_hwcap(void) hwcaps |= ARM_HWCAP_A64_CPUID; /* probe for the extra features */ -#define GET_FEATURE_ID(feat, hwcap) \ - do { if (cpu_isar_feature(feat, cpu)) { hwcaps |= hwcap; } } while (0) GET_FEATURE_ID(aa64_aes, ARM_HWCAP_A64_AES); GET_FEATURE_ID(aa64_pmull, ARM_HWCAP_A64_PMULL); @@ -645,11 +657,22 @@ static uint32_t get_elf_hwcap(void) GET_FEATURE_ID(aa64_sb, ARM_HWCAP_A64_SB); GET_FEATURE_ID(aa64_condm_4, ARM_HWCAP_A64_FLAGM); -#undef GET_FEATURE_ID + return hwcaps; +} + +static uint32_t get_elf_hwcap2(void) +{ + ARMCPU *cpu = ARM_CPU(thread_cpu); + uint32_t hwcaps = 0; + + GET_FEATURE_ID(aa64_condm_5, ARM_HWCAP2_A64_FLAGM2); + GET_FEATURE_ID(aa64_frint, ARM_HWCAP2_A64_FRINT); return hwcaps; } +#undef GET_FEATURE_ID + #endif /* not TARGET_AARCH64 */ #endif /* TARGET_ARM */ @@ -2380,6 +2403,8 @@ static void load_elf_image(const char *image_name, int image_fd, } info->load_bias = load_bias; + info->code_offset = load_bias; + info->data_offset = load_bias; info->load_addr = load_addr; info->entry = ehdr->e_entry + load_bias; info->start_code = -1; diff --git a/linux-user/ioctls.h b/linux-user/ioctls.h index 3281c97ca2..c6b9d6ad66 100644 --- a/linux-user/ioctls.h +++ b/linux-user/ioctls.h @@ -112,6 +112,14 @@ IOCTL(BLKZEROOUT, IOC_W, MK_PTR(MK_ARRAY(TYPE_ULONGLONG, 2))) #endif + IOCTL(FDMSGON, 0, TYPE_NULL) + IOCTL(FDMSGOFF, 0, TYPE_NULL) + IOCTL(FDFLUSH, 0, TYPE_NULL) + IOCTL(FDRESET, 0, TYPE_NULL) + IOCTL(FDRAWCMD, 0, TYPE_NULL) + IOCTL(FDTWADDLE, 0, TYPE_NULL) + IOCTL(FDEJECT, 0, TYPE_NULL) + #ifdef FIBMAP IOCTL(FIBMAP, IOC_W | IOC_R, MK_PTR(TYPE_LONG)) #endif @@ -177,6 +185,8 @@ #endif #endif /* CONFIG_USBFS */ + IOCTL(FIOGETOWN, IOC_R, MK_PTR(TYPE_INT)) + IOCTL(FIOSETOWN, IOC_W, MK_PTR(TYPE_INT)) IOCTL(SIOCATMARK, IOC_R, MK_PTR(TYPE_INT)) IOCTL(SIOCGIFNAME, IOC_RW, MK_PTR(MK_STRUCT(STRUCT_int_ifreq))) IOCTL(SIOCGIFFLAGS, IOC_W | IOC_R, MK_PTR(MK_STRUCT(STRUCT_short_ifreq))) @@ -246,6 +256,9 @@ IOCTL(RNDADDTOENTCNT, IOC_W, MK_PTR(TYPE_INT)) IOCTL(RNDZAPENTCNT, 0, TYPE_NULL) IOCTL(RNDCLEARPOOL, 0, TYPE_NULL) +#ifdef RNDRESEEDCRNG + IOCTL(RNDRESEEDCRNG, 0, TYPE_NULL) +#endif IOCTL(CDROMPAUSE, 0, TYPE_NULL) IOCTL(CDROMSTART, 0, TYPE_NULL) diff --git a/linux-user/main.c b/linux-user/main.c index 47917bbb20..560d053f72 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -49,7 +49,6 @@ char *exec_path; int singlestep; -static const char *filename; static const char *argv0; static int gdbstub_port; static envlist_t *envlist; @@ -78,12 +77,12 @@ int have_guest_base; (TARGET_LONG_BITS == 32 || defined(TARGET_ABI32)) /* There are a number of places where we assign reserved_va to a variable of type abi_ulong and expect it to fit. Avoid the last page. */ -# define MAX_RESERVED_VA (0xfffffffful & TARGET_PAGE_MASK) +# define MAX_RESERVED_VA(CPU) (0xfffffffful & TARGET_PAGE_MASK) # else -# define MAX_RESERVED_VA (1ul << TARGET_VIRT_ADDR_SPACE_BITS) +# define MAX_RESERVED_VA(CPU) (1ul << TARGET_VIRT_ADDR_SPACE_BITS) # endif # else -# define MAX_RESERVED_VA 0 +# define MAX_RESERVED_VA(CPU) 0 # endif #endif @@ -236,7 +235,7 @@ static void handle_arg_log(const char *arg) static void handle_arg_dfilter(const char *arg) { - qemu_set_dfilter_ranges(arg, NULL); + qemu_set_dfilter_ranges(arg, &error_fatal); } static void handle_arg_log_filename(const char *arg) @@ -357,8 +356,7 @@ static void handle_arg_reserved_va(const char *arg) unsigned long unshifted = reserved_va; p++; reserved_va <<= shift; - if (reserved_va >> shift != unshifted - || (MAX_RESERVED_VA && reserved_va > MAX_RESERVED_VA)) { + if (reserved_va >> shift != unshifted) { fprintf(stderr, "Reserved virtual address too big\n"); exit(EXIT_FAILURE); } @@ -393,6 +391,13 @@ static void handle_arg_trace(const char *arg) trace_file = trace_opt_parse(arg); } +#if defined(TARGET_XTENSA) +static void handle_arg_abi_call0(const char *arg) +{ + xtensa_set_abi_call0(); +} +#endif + struct qemu_argument { const char *argv; const char *env; @@ -446,6 +451,10 @@ static const struct qemu_argument arg_table[] = { "", "[[enable=]<pattern>][,events=<file>][,file=<file>]"}, {"version", "QEMU_VERSION", false, handle_arg_version, "", "display version information and exit"}, +#if defined(TARGET_XTENSA) + {"xtensa-abi-call0", "QEMU_XTENSA_ABI_CALL0", false, handle_arg_abi_call0, + "", "assume CALL0 Xtensa ABI"}, +#endif {NULL, NULL, false, NULL, NULL, NULL} }; @@ -586,7 +595,6 @@ static int parse_args(int argc, char **argv) exit(EXIT_FAILURE); } - filename = argv[optind]; exec_path = argv[optind]; return optind; @@ -607,6 +615,7 @@ int main(int argc, char **argv, char **envp) int i; int ret; int execfd; + unsigned long max_reserved_va; error_init(argv[0]); module_call_init(MODULE_INIT_TRACE); @@ -657,9 +666,9 @@ int main(int argc, char **argv, char **envp) execfd = qemu_getauxval(AT_EXECFD); if (execfd == 0) { - execfd = open(filename, O_RDONLY); + execfd = open(exec_path, O_RDONLY); if (execfd < 0) { - printf("Error while loading %s: %s\n", filename, strerror(errno)); + printf("Error while loading %s: %s\n", exec_path, strerror(errno)); _exit(EXIT_FAILURE); } } @@ -672,31 +681,31 @@ int main(int argc, char **argv, char **envp) /* init tcg before creating CPUs and to get qemu_host_page_size */ tcg_exec_init(0); - /* Reserving *too* much vm space via mmap can run into problems - with rlimits, oom due to page table creation, etc. We will still try it, - if directed by the command-line option, but not by default. */ - if (HOST_LONG_BITS == 64 && - TARGET_VIRT_ADDR_SPACE_BITS <= 32 && - reserved_va == 0) { - /* reserved_va must be aligned with the host page size - * as it is used with mmap() - */ - reserved_va = MAX_RESERVED_VA & qemu_host_page_mask; - } - cpu = cpu_create(cpu_type); env = cpu->env_ptr; cpu_reset(cpu); - thread_cpu = cpu; - if (getenv("QEMU_STRACE")) { - do_strace = 1; + /* + * Reserving too much vm space via mmap can run into problems + * with rlimits, oom due to page table creation, etc. We will + * still try it, if directed by the command-line option, but + * not by default. + */ + max_reserved_va = MAX_RESERVED_VA(cpu); + if (reserved_va != 0) { + if (max_reserved_va && reserved_va > max_reserved_va) { + fprintf(stderr, "Reserved virtual address too big\n"); + exit(EXIT_FAILURE); + } + } else if (HOST_LONG_BITS == 64 && TARGET_VIRT_ADDR_SPACE_BITS <= 32) { + /* + * reserved_va must be aligned with the host page size + * as it is used with mmap() + */ + reserved_va = max_reserved_va & qemu_host_page_mask; } - if (seed_optarg == NULL) { - seed_optarg = getenv("QEMU_RAND_SEED"); - } { Error *err = NULL; if (seed_optarg != NULL) { @@ -784,10 +793,10 @@ int main(int argc, char **argv, char **envp) cpu->opaque = ts; task_settid(ts); - ret = loader_exec(execfd, filename, target_argv, target_environ, regs, + ret = loader_exec(execfd, exec_path, target_argv, target_environ, regs, info, &bprm); if (ret != 0) { - printf("Error while loading %s: %s\n", filename, strerror(-ret)); + printf("Error while loading %s: %s\n", exec_path, strerror(-ret)); _exit(EXIT_FAILURE); } diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 8b41a03901..e2af3c1494 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -20,6 +20,7 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "qemu/path.h" +#include "qemu/memfd.h" #include "qemu/queue.h" #include <elf.h> #include <endian.h> @@ -88,6 +89,7 @@ #include <linux/kd.h> #include <linux/mtio.h> #include <linux/fs.h> +#include <linux/fd.h> #if defined(CONFIG_FIEMAP) #include <linux/fiemap.h> #endif @@ -11847,7 +11849,6 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, timer_t htimer = g_posix_timers[timerid]; ret = get_errno(timer_getoverrun(htimer)); } - fd_trans_unregister(ret); return ret; } #endif @@ -11939,6 +11940,17 @@ static abi_long do_syscall1(void *cpu_env, int num, abi_long arg1, /* PowerPC specific. */ return do_swapcontext(cpu_env, arg1, arg2, arg3); #endif +#ifdef TARGET_NR_memfd_create + case TARGET_NR_memfd_create: + p = lock_user_string(arg1); + if (!p) { + return -TARGET_EFAULT; + } + ret = get_errno(memfd_create(p, arg2)); + fd_trans_unregister(ret); + unlock_user(p, arg1, 0); + return ret; +#endif default: qemu_log_mask(LOG_UNIMP, "Unsupported syscall: %d\n", num); diff --git a/linux-user/syscall_defs.h b/linux-user/syscall_defs.h index 0662270300..fa69c6ab8d 100644 --- a/linux-user/syscall_defs.h +++ b/linux-user/syscall_defs.h @@ -758,10 +758,14 @@ struct target_pollfd { #if defined(TARGET_ALPHA) || defined(TARGET_MIPS) || defined(TARGET_SH4) || \ defined(TARGET_XTENSA) +#define TARGET_FIOGETOWN TARGET_IOR('f', 123, int) +#define TARGET_FIOSETOWN TARGET_IOW('f', 124, int) #define TARGET_SIOCATMARK TARGET_IOR('s', 7, int) #define TARGET_SIOCSPGRP TARGET_IOW('s', 8, pid_t) #define TARGET_SIOCGPGRP TARGET_IOR('s', 9, pid_t) #else +#define TARGET_FIOGETOWN 0x8903 +#define TARGET_FIOSETOWN 0x8901 #define TARGET_SIOCATMARK 0x8905 #define TARGET_SIOCSPGRP 0x8902 #define TARGET_SIOCGPGRP 0x8904 @@ -850,6 +854,7 @@ struct target_pollfd { #define TARGET_RNDADDTOENTCNT TARGET_IOW('R', 0x01, int) #define TARGET_RNDZAPENTCNT TARGET_IO('R', 0x04) #define TARGET_RNDCLEARPOOL TARGET_IO('R', 0x06) +#define TARGET_RNDRESEEDCRNG TARGET_IO('R', 0x07) /* From <linux/fs.h> */ @@ -883,6 +888,16 @@ struct target_pollfd { #define TARGET_BLKROTATIONAL TARGET_IO(0x12, 126) #define TARGET_BLKZEROOUT TARGET_IO(0x12, 127) +/* From <linux/fd.h> */ + +#define TARGET_FDMSGON TARGET_IO(2, 0x45) +#define TARGET_FDMSGOFF TARGET_IO(2, 0x46) +#define TARGET_FDFLUSH TARGET_IO(2, 0x4b) +#define TARGET_FDRESET TARGET_IO(2, 0x54) +#define TARGET_FDRAWCMD TARGET_IO(2, 0x58) +#define TARGET_FDTWADDLE TARGET_IO(2, 0x59) +#define TARGET_FDEJECT TARGET_IO(2, 0x5a) + #define TARGET_FIBMAP TARGET_IO(0x00,1) /* bmap access */ #define TARGET_FIGETBSZ TARGET_IO(0x00,2) /* get the block size used for bmap */ diff --git a/linux-user/xtensa/signal.c b/linux-user/xtensa/signal.c index 8d54ef3ae3..590f0313ff 100644 --- a/linux-user/xtensa/signal.c +++ b/linux-user/xtensa/signal.c @@ -134,6 +134,8 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, abi_ulong frame_addr; struct target_rt_sigframe *frame; uint32_t ra; + bool abi_call0; + unsigned base; int i; frame_addr = get_sigframe(ka, env, sizeof(*frame)); @@ -182,20 +184,27 @@ void setup_rt_frame(int sig, struct target_sigaction *ka, __put_user(0x00, &frame->retcode[5]); #endif } - env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); - if (xtensa_option_enabled(env->config, XTENSA_OPTION_WINDOWED_REGISTER)) { - env->sregs[PS] |= PS_WOE | (1 << PS_CALLINC_SHIFT); - } memset(env->regs, 0, sizeof(env->regs)); env->pc = ka->_sa_handler; env->regs[1] = frame_addr; env->sregs[WINDOW_BASE] = 0; env->sregs[WINDOW_START] = 1; - env->regs[4] = (ra & 0x3fffffff) | 0x40000000; - env->regs[6] = sig; - env->regs[7] = frame_addr + offsetof(struct target_rt_sigframe, info); - env->regs[8] = frame_addr + offsetof(struct target_rt_sigframe, uc); + abi_call0 = (env->sregs[PS] & PS_WOE) == 0; + env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); + + if (abi_call0) { + base = 0; + env->regs[base] = ra; + } else { + env->sregs[PS] |= PS_WOE | (1 << PS_CALLINC_SHIFT); + base = 4; + env->regs[base] = (ra & 0x3fffffff) | 0x40000000; + } + env->regs[base + 2] = sig; + env->regs[base + 3] = frame_addr + offsetof(struct target_rt_sigframe, + info); + env->regs[base + 4] = frame_addr + offsetof(struct target_rt_sigframe, uc); unlock_user_struct(frame, frame_addr, 1); return; diff --git a/memory.c b/memory.c index 61a254c3f9..b9dd6b94ca 100644 --- a/memory.c +++ b/memory.c @@ -3267,21 +3267,3 @@ static void memory_register_types(void) } type_init(memory_register_types) - -MemOp devend_memop(enum device_endian end) -{ - static MemOp conv[] = { - [DEVICE_LITTLE_ENDIAN] = MO_LE, - [DEVICE_BIG_ENDIAN] = MO_BE, - [DEVICE_NATIVE_ENDIAN] = MO_TE, - [DEVICE_HOST_ENDIAN] = 0, - }; - switch (end) { - case DEVICE_LITTLE_ENDIAN: - case DEVICE_BIG_ENDIAN: - case DEVICE_NATIVE_ENDIAN: - return conv[end]; - default: - g_assert_not_reached(); - } -} diff --git a/migration/block-dirty-bitmap.c b/migration/block-dirty-bitmap.c index dd40724b9e..5121f86d73 100644 --- a/migration/block-dirty-bitmap.c +++ b/migration/block-dirty-bitmap.c @@ -733,7 +733,7 @@ void dirty_bitmap_mig_init(void) { QSIMPLEQ_INIT(&dirty_bitmap_mig_state.dbms_list); - register_savevm_live(NULL, "dirty-bitmap", 0, 1, + register_savevm_live("dirty-bitmap", 0, 1, &savevm_dirty_bitmap_handlers, &dirty_bitmap_mig_state); } diff --git a/migration/block.c b/migration/block.c index aa747b55fa..8e49382070 100644 --- a/migration/block.c +++ b/migration/block.c @@ -906,7 +906,7 @@ static int block_load(QEMUFile *f, void *opaque, int version_id) do { addr = qemu_get_be64(f); - flags = addr & ~BDRV_SECTOR_MASK; + flags = addr & (BDRV_SECTOR_SIZE - 1); addr >>= BDRV_SECTOR_BITS; if (flags & BLK_MIG_FLAG_DEVICE_BLOCK) { @@ -1030,6 +1030,6 @@ void blk_mig_init(void) QSIMPLEQ_INIT(&block_mig_state.blk_list); qemu_mutex_init(&block_mig_state.lock); - register_savevm_live(NULL, "block", 0, 1, &savevm_block_handlers, + register_savevm_live("block", 0, 1, &savevm_block_handlers, &block_mig_state); } diff --git a/migration/migration.c b/migration/migration.c index 8b9f2fe30a..01863a95f5 100644 --- a/migration/migration.c +++ b/migration/migration.c @@ -2140,6 +2140,15 @@ bool migrate_ignore_shared(void) return s->enabled_capabilities[MIGRATION_CAPABILITY_X_IGNORE_SHARED]; } +bool migrate_validate_uuid(void) +{ + MigrationState *s; + + s = migrate_get_current(); + + return s->enabled_capabilities[MIGRATION_CAPABILITY_VALIDATE_UUID]; +} + bool migrate_use_events(void) { MigrationState *s; @@ -3016,7 +3025,7 @@ static MigThrError migration_detect_error(MigrationState *s) } } -/* How many bytes have we transferred since the beggining of the migration */ +/* How many bytes have we transferred since the beginning of the migration */ static uint64_t migration_total_bytes(MigrationState *s) { return qemu_ftell(s->to_dst_file) + ram_counters.multifd_bytes; @@ -3327,7 +3336,8 @@ void migrate_fd_connect(MigrationState *s, Error *error_in) if (resume) { /* This is a resumed migration */ - rate_limit = INT64_MAX; + rate_limit = s->parameters.max_postcopy_bandwidth / + XFER_LIMIT_RATIO; } else { /* This is a fresh new migration */ rate_limit = s->parameters.max_bandwidth / XFER_LIMIT_RATIO; diff --git a/migration/migration.h b/migration/migration.h index 3e1ea2b5dc..4f2fe193dc 100644 --- a/migration/migration.h +++ b/migration/migration.h @@ -290,6 +290,7 @@ bool migrate_postcopy_ram(void); bool migrate_zero_blocks(void); bool migrate_dirty_bitmaps(void); bool migrate_ignore_shared(void); +bool migrate_validate_uuid(void); bool migrate_auto_converge(void); bool migrate_use_multifd(void); diff --git a/migration/qemu-file.c b/migration/qemu-file.c index e33c46764f..26fb25ddc1 100644 --- a/migration/qemu-file.c +++ b/migration/qemu-file.c @@ -201,9 +201,8 @@ static void qemu_iovec_release_ram(QEMUFile *f) /** * Flushes QEMUFile buffer * - * If there is writev_buffer QEMUFileOps it uses it otherwise uses - * put_buffer ops. This will flush all pending data. If data was - * only partially flushed, it will set an error state. + * This will flush all pending data. If data was only partially flushed, it + * will set an error state. */ void qemu_fflush(QEMUFile *f) { @@ -382,8 +381,16 @@ int qemu_fclose(QEMUFile *f) return ret; } -static void add_to_iovec(QEMUFile *f, const uint8_t *buf, size_t size, - bool may_free) +/* + * Add buf to iovec. Do flush if iovec is full. + * + * Return values: + * 1 iovec is full and flushed + * 0 iovec is not flushed + * + */ +static int add_to_iovec(QEMUFile *f, const uint8_t *buf, size_t size, + bool may_free) { /* check for adjacent buffer and coalesce them */ if (f->iovcnt > 0 && buf == f->iov[f->iovcnt - 1].iov_base + @@ -401,6 +408,19 @@ static void add_to_iovec(QEMUFile *f, const uint8_t *buf, size_t size, if (f->iovcnt >= MAX_IOV_SIZE) { qemu_fflush(f); + return 1; + } + + return 0; +} + +static void add_buf_to_iovec(QEMUFile *f, size_t len) +{ + if (!add_to_iovec(f, f->buf + f->buf_index, len, false)) { + f->buf_index += len; + if (f->buf_index == IO_BUF_SIZE) { + qemu_fflush(f); + } } } @@ -430,11 +450,7 @@ void qemu_put_buffer(QEMUFile *f, const uint8_t *buf, size_t size) } memcpy(f->buf + f->buf_index, buf, l); f->bytes_xfer += l; - add_to_iovec(f, f->buf + f->buf_index, l, false); - f->buf_index += l; - if (f->buf_index == IO_BUF_SIZE) { - qemu_fflush(f); - } + add_buf_to_iovec(f, l); if (qemu_file_get_error(f)) { break; } @@ -451,11 +467,7 @@ void qemu_put_byte(QEMUFile *f, int v) f->buf[f->buf_index] = v; f->bytes_xfer++; - add_to_iovec(f, f->buf + f->buf_index, 1, false); - f->buf_index++; - if (f->buf_index == IO_BUF_SIZE) { - qemu_fflush(f); - } + add_buf_to_iovec(f, 1); } void qemu_file_skip(QEMUFile *f, int size) @@ -761,13 +773,7 @@ ssize_t qemu_put_compression_data(QEMUFile *f, z_stream *stream, } qemu_put_be32(f, blen); - if (f->ops->writev_buffer) { - add_to_iovec(f, f->buf + f->buf_index, blen, false); - } - f->buf_index += blen; - if (f->buf_index == IO_BUF_SIZE) { - qemu_fflush(f); - } + add_buf_to_iovec(f, blen); return blen + sizeof(int32_t); } diff --git a/migration/ram.c b/migration/ram.c index b01a37e7ca..01df326767 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -1112,6 +1112,7 @@ static void *multifd_send_thread(void *opaque) rcu_register_thread(); if (multifd_send_initial_packet(p, &local_err) < 0) { + ret = -1; goto out; } /* initial packet */ @@ -1179,9 +1180,7 @@ out: * who pay attention to me. */ if (ret != 0) { - if (flags & MULTIFD_FLAG_SYNC) { - qemu_sem_post(&p->sem_sync); - } + qemu_sem_post(&p->sem_sync); qemu_sem_post(&multifd_send_state->channels_ready); } @@ -4676,5 +4675,5 @@ static SaveVMHandlers savevm_ram_handlers = { void ram_mig_init(void) { qemu_mutex_init(&XBZRLE.lock); - register_savevm_live(NULL, "ram", 0, 4, &savevm_ram_handlers, &ram_state); + register_savevm_live("ram", 0, 4, &savevm_ram_handlers, &ram_state); } diff --git a/migration/savevm.c b/migration/savevm.c index 4a86128ac4..ee06f91d42 100644 --- a/migration/savevm.c +++ b/migration/savevm.c @@ -256,6 +256,7 @@ typedef struct SaveState { uint32_t target_page_bits; uint32_t caps_count; MigrationCapability *capabilities; + QemuUUID uuid; } SaveState; static SaveState savevm_state = { @@ -307,6 +308,7 @@ static int configuration_pre_save(void *opaque) state->capabilities[j++] = i; } } + state->uuid = qemu_uuid; return 0; } @@ -464,6 +466,48 @@ static const VMStateDescription vmstate_capabilites = { } }; +static bool vmstate_uuid_needed(void *opaque) +{ + return qemu_uuid_set && migrate_validate_uuid(); +} + +static int vmstate_uuid_post_load(void *opaque, int version_id) +{ + SaveState *state = opaque; + char uuid_src[UUID_FMT_LEN + 1]; + char uuid_dst[UUID_FMT_LEN + 1]; + + if (!qemu_uuid_set) { + /* + * It's warning because user might not know UUID in some cases, + * e.g. load an old snapshot + */ + qemu_uuid_unparse(&state->uuid, uuid_src); + warn_report("UUID is received %s, but local uuid isn't set", + uuid_src); + return 0; + } + if (!qemu_uuid_is_equal(&state->uuid, &qemu_uuid)) { + qemu_uuid_unparse(&state->uuid, uuid_src); + qemu_uuid_unparse(&qemu_uuid, uuid_dst); + error_report("UUID received is %s and local is %s", uuid_src, uuid_dst); + return -EINVAL; + } + return 0; +} + +static const VMStateDescription vmstate_uuid = { + .name = "configuration/uuid", + .version_id = 1, + .minimum_version_id = 1, + .needed = vmstate_uuid_needed, + .post_load = vmstate_uuid_post_load, + .fields = (VMStateField[]) { + VMSTATE_UINT8_ARRAY_V(uuid.data, SaveState, sizeof(QemuUUID), 1), + VMSTATE_END_OF_LIST() + } +}; + static const VMStateDescription vmstate_configuration = { .name = "configuration", .version_id = 1, @@ -478,6 +522,7 @@ static const VMStateDescription vmstate_configuration = { .subsections = (const VMStateDescription*[]) { &vmstate_target_page_bits, &vmstate_capabilites, + &vmstate_uuid, NULL } }; @@ -684,8 +729,7 @@ static void savevm_state_handler_insert(SaveStateEntry *nse) of the system, so instance_id should be removed/replaced. Meanwhile pass -1 as instance_id if you do not already have a clearly distinguishing id for all instances of your device class. */ -int register_savevm_live(DeviceState *dev, - const char *idstr, +int register_savevm_live(const char *idstr, int instance_id, int version_id, const SaveVMHandlers *ops, @@ -704,26 +748,6 @@ int register_savevm_live(DeviceState *dev, se->is_ram = 1; } - if (dev) { - char *id = qdev_get_dev_path(dev); - if (id) { - if (snprintf(se->idstr, sizeof(se->idstr), "%s/", id) >= - sizeof(se->idstr)) { - error_report("Path too long for VMState (%s)", id); - g_free(id); - g_free(se); - - return -1; - } - g_free(id); - - se->compat = g_new0(CompatEntry, 1); - pstrcpy(se->compat->idstr, sizeof(se->compat->idstr), idstr); - se->compat->instance_id = instance_id == -1 ? - calculate_compat_instance_id(idstr) : instance_id; - instance_id = -1; - } - } pstrcat(se->idstr, sizeof(se->idstr), idstr); if (instance_id == -1) { @@ -1100,7 +1124,7 @@ void qemu_savevm_state_setup(QEMUFile *f) if (!se->ops || !se->ops->save_setup) { continue; } - if (se->ops && se->ops->is_active) { + if (se->ops->is_active) { if (!se->ops->is_active(se->opaque)) { continue; } @@ -1131,7 +1155,7 @@ int qemu_savevm_state_resume_prepare(MigrationState *s) if (!se->ops || !se->ops->resume_prepare) { continue; } - if (se->ops && se->ops->is_active) { + if (se->ops->is_active) { if (!se->ops->is_active(se->opaque)) { continue; } @@ -1227,7 +1251,7 @@ void qemu_savevm_state_complete_postcopy(QEMUFile *f) if (!se->ops || !se->ops->save_live_complete_postcopy) { continue; } - if (se->ops && se->ops->is_active) { + if (se->ops->is_active) { if (!se->ops->is_active(se->opaque)) { continue; } @@ -1264,7 +1288,7 @@ int qemu_savevm_state_complete_precopy_iterable(QEMUFile *f, bool in_postcopy) continue; } - if (se->ops && se->ops->is_active) { + if (se->ops->is_active) { if (!se->ops->is_active(se->opaque)) { continue; } @@ -1413,7 +1437,7 @@ void qemu_savevm_state_pending(QEMUFile *f, uint64_t threshold_size, if (!se->ops || !se->ops->save_live_pending) { continue; } - if (se->ops && se->ops->is_active) { + if (se->ops->is_active) { if (!se->ops->is_active(se->opaque)) { continue; } @@ -2334,7 +2358,7 @@ static int qemu_loadvm_state_setup(QEMUFile *f) if (!se->ops || !se->ops->load_setup) { continue; } - if (se->ops && se->ops->is_active) { + if (se->ops->is_active) { if (!se->ops->is_active(se->opaque)) { continue; } diff --git a/nbd/trace-events b/nbd/trace-events index f6cde96790..a955918e97 100644 --- a/nbd/trace-events +++ b/nbd/trace-events @@ -61,8 +61,8 @@ nbd_negotiate_begin(void) "Beginning negotiation" nbd_negotiate_new_style_size_flags(uint64_t size, unsigned flags) "advertising size %" PRIu64 " and flags 0x%x" nbd_negotiate_success(void) "Negotiation succeeded" nbd_receive_request(uint32_t magic, uint16_t flags, uint16_t type, uint64_t from, uint32_t len) "Got request: { magic = 0x%" PRIx32 ", .flags = 0x%" PRIx16 ", .type = 0x%" PRIx16 ", from = %" PRIu64 ", len = %" PRIu32 " }" -nbd_blk_aio_attached(const char *name, void *ctx) "Export %s: Attaching clients to AIO context %p\n" -nbd_blk_aio_detach(const char *name, void *ctx) "Export %s: Detaching clients from AIO context %p\n" +nbd_blk_aio_attached(const char *name, void *ctx) "Export %s: Attaching clients to AIO context %p" +nbd_blk_aio_detach(const char *name, void *ctx) "Export %s: Detaching clients from AIO context %p" nbd_co_send_simple_reply(uint64_t handle, uint32_t error, const char *errname, int len) "Send simple reply: handle = %" PRIu64 ", error = %" PRIu32 " (%s), len = %d" nbd_co_send_structured_done(uint64_t handle) "Send structured reply done: handle = %" PRIu64 nbd_co_send_structured_read(uint64_t handle, uint64_t offset, void *data, size_t size) "Send structured read data reply: handle = %" PRIu64 ", offset = %" PRIu64 ", data = %p, len = %zu" diff --git a/net/slirp.c b/net/slirp.c index b34cb29276..f42f496641 100644 --- a/net/slirp.c +++ b/net/slirp.c @@ -576,7 +576,7 @@ static int net_slirp_init(NetClientState *peer, const char *model, * specific version? */ g_assert(slirp_state_version() == 4); - register_savevm_live(NULL, "slirp", 0, slirp_state_version(), + register_savevm_live("slirp", 0, slirp_state_version(), &savevm_slirp_state, s->slirp); s->poll_notifier.notify = net_slirp_poll_notify; diff --git a/net/trace-events b/net/trace-events index ac57056497..02c13fd0ba 100644 --- a/net/trace-events +++ b/net/trace-events @@ -17,9 +17,9 @@ colo_compare_icmp_miscompare(const char *sta, int size) ": %s = %d" colo_compare_ip_info(int psize, const char *sta, const char *stb, int ssize, const char *stc, const char *std) "ppkt size = %d, ip_src = %s, ip_dst = %s, spkt size = %d, ip_src = %s, ip_dst = %s" colo_old_packet_check_found(int64_t old_time) "%" PRId64 colo_compare_miscompare(void) "" -colo_compare_tcp_info(const char *pkt, uint32_t seq, uint32_t ack, int hdlen, int pdlen, int offset, int flags) "%s: seq/ack= %u/%u hdlen= %d pdlen= %d offset= %d flags=%d\n" +colo_compare_tcp_info(const char *pkt, uint32_t seq, uint32_t ack, int hdlen, int pdlen, int offset, int flags) "%s: seq/ack= %u/%u hdlen= %d pdlen= %d offset= %d flags=%d" # filter-rewriter.c colo_filter_rewriter_debug(void) "" -colo_filter_rewriter_pkt_info(const char *func, const char *src, const char *dst, uint32_t seq, uint32_t ack, uint32_t flag) "%s: src/dst: %s/%s p: seq/ack=%u/%u flags=0x%x\n" -colo_filter_rewriter_conn_offset(uint32_t offset) ": offset=%u\n" +colo_filter_rewriter_pkt_info(const char *func, const char *src, const char *dst, uint32_t seq, uint32_t ack, uint32_t flag) "%s: src/dst: %s/%s p: seq/ack=%u/%u flags=0x%x" +colo_filter_rewriter_conn_offset(uint32_t offset) ": offset=%u" diff --git a/pc-bios/opensbi-riscv32-virt-fw_jump.bin b/pc-bios/opensbi-riscv32-virt-fw_jump.bin index f5bcaa5695..f5bcaa5695 100755..100644 --- a/pc-bios/opensbi-riscv32-virt-fw_jump.bin +++ b/pc-bios/opensbi-riscv32-virt-fw_jump.bin Binary files differdiff --git a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin index 5d7a1ef681..eb22aefdfb 100755..100644 --- a/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin +++ b/pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin Binary files differdiff --git a/pc-bios/opensbi-riscv64-virt-fw_jump.bin b/pc-bios/opensbi-riscv64-virt-fw_jump.bin index 4cec6f0210..4cec6f0210 100755..100644 --- a/pc-bios/opensbi-riscv64-virt-fw_jump.bin +++ b/pc-bios/opensbi-riscv64-virt-fw_jump.bin Binary files differdiff --git a/qapi/migration.json b/qapi/migration.json index 9cfbaf8c6c..82feb5bd39 100644 --- a/qapi/migration.json +++ b/qapi/migration.json @@ -415,6 +415,9 @@ # # @x-ignore-shared: If enabled, QEMU will not migrate shared memory (since 4.0) # +# @validate-uuid: Send the UUID of the source to allow the destination +# to ensure it is the same. (since 4.2) +# # Since: 1.2 ## { 'enum': 'MigrationCapability', @@ -422,7 +425,7 @@ 'compress', 'events', 'postcopy-ram', 'x-colo', 'release-ram', 'block', 'return-path', 'pause-before-switchover', 'multifd', 'dirty-bitmaps', 'postcopy-blocktime', 'late-block-activate', - 'x-ignore-shared' ] } + 'x-ignore-shared', 'validate-uuid' ] } ## # @MigrationCapabilityStatus: diff --git a/qdev-monitor.c b/qdev-monitor.c index 8fe5c2cad2..148df9cacf 100644 --- a/qdev-monitor.c +++ b/qdev-monitor.c @@ -615,6 +615,13 @@ DeviceState *qdev_device_add(QemuOpts *opts, Error **errp) /* create device */ dev = DEVICE(object_new(driver)); + /* Check whether the hotplug is allowed by the machine */ + if (qdev_hotplug && !qdev_hotplug_allowed(dev, &err)) { + /* Error must be set in the machine hook */ + assert(err); + goto err_del_dev; + } + if (bus) { qdev_set_parent_bus(dev, bus); } else if (qdev_hotplug && !qdev_get_machine_hotplug_handler(dev)) { diff --git a/qemu-doc.texi b/qemu-doc.texi index 4d828a5135..2ba6c90c08 100644 --- a/qemu-doc.texi +++ b/qemu-doc.texi @@ -451,15 +451,15 @@ of <protocol>. Example: boot from a remote Fedora 20 live ISO image @example -@value{qemu_system_x86} --drive media=cdrom,file=http://dl.fedoraproject.org/pub/fedora/linux/releases/20/Live/x86_64/Fedora-Live-Desktop-x86_64-20-1.iso,readonly +@value{qemu_system_x86} --drive media=cdrom,file=https://archives.fedoraproject.org/pub/archive/fedora/linux/releases/20/Live/x86_64/Fedora-Live-Desktop-x86_64-20-1.iso,readonly -@value{qemu_system_x86} --drive media=cdrom,file.driver=http,file.url=http://dl.fedoraproject.org/pub/fedora/linux/releases/20/Live/x86_64/Fedora-Live-Desktop-x86_64-20-1.iso,readonly +@value{qemu_system_x86} --drive media=cdrom,file.driver=http,file.url=http://archives.fedoraproject.org/pub/fedora/linux/releases/20/Live/x86_64/Fedora-Live-Desktop-x86_64-20-1.iso,readonly @end example Example: boot from a remote Fedora 20 cloud image using a local overlay for writes, copy-on-read, and a readahead of 64k @example -qemu-img create -f qcow2 -o backing_file='json:@{"file.driver":"http",, "file.url":"https://dl.fedoraproject.org/pub/fedora/linux/releases/20/Images/x86_64/Fedora-x86_64-20-20131211.1-sda.qcow2",, "file.readahead":"64k"@}' /tmp/Fedora-x86_64-20-20131211.1-sda.qcow2 +qemu-img create -f qcow2 -o backing_file='json:@{"file.driver":"http",, "file.url":"http://archives.fedoraproject.org/pub/archive/fedora/linux/releases/20/Images/x86_64/Fedora-x86_64-20-20131211.1-sda.qcow2",, "file.readahead":"64k"@}' /tmp/Fedora-x86_64-20-20131211.1-sda.qcow2 @value{qemu_system_x86} -drive file=/tmp/Fedora-x86_64-20-20131211.1-sda.qcow2,copy-on-read=on @end example @@ -2535,11 +2535,6 @@ so should only be used with trusted guest OS. @c man end -@node QEMU Guest Agent -@chapter QEMU Guest Agent invocation - -@include qemu-ga.texi - @node QEMU User space emulator @chapter QEMU User space emulator diff --git a/qemu-ga.texi b/qemu-ga.texi deleted file mode 100644 index f00ad830f2..0000000000 --- a/qemu-ga.texi +++ /dev/null @@ -1,137 +0,0 @@ -@example -@c man begin SYNOPSIS -@command{qemu-ga} [@var{OPTIONS}] -@c man end -@end example - -@c man begin DESCRIPTION - -The QEMU Guest Agent is a daemon intended to be run within virtual -machines. It allows the hypervisor host to perform various operations -in the guest, such as: - -@itemize -@item -get information from the guest -@item -set the guest's system time -@item -read/write a file -@item -sync and freeze the filesystems -@item -suspend the guest -@item -reconfigure guest local processors -@item -set user's password -@item -... -@end itemize - -qemu-ga will read a system configuration file on startup (located at -@file{@value{CONFDIR}/qemu-ga.conf} by default), then parse remaining -configuration options on the command line. For the same key, the last -option wins, but the lists accumulate (see below for configuration -file format). - -@c man end - -@c man begin OPTIONS -@table @option -@item -m, --method=@var{method} - Transport method: one of @samp{unix-listen}, @samp{virtio-serial}, or - @samp{isa-serial} (@samp{virtio-serial} is the default). - -@item -p, --path=@var{path} - Device/socket path (the default for virtio-serial is - @samp{/dev/virtio-ports/org.qemu.guest_agent.0}, - the default for isa-serial is @samp{/dev/ttyS0}) - -@item -l, --logfile=@var{path} - Set log file path (default is stderr). - -@item -f, --pidfile=@var{path} - Specify pid file (default is @samp{/var/run/qemu-ga.pid}). - -@item -F, --fsfreeze-hook=@var{path} - Enable fsfreeze hook. Accepts an optional argument that specifies - script to run on freeze/thaw. Script will be called with - 'freeze'/'thaw' arguments accordingly (default is - @samp{@value{CONFDIR}/fsfreeze-hook}). If using -F with an argument, do - not follow -F with a space (for example: - @samp{-F/var/run/fsfreezehook.sh}). - -@item -t, --statedir=@var{path} - Specify the directory to store state information (absolute paths only, - default is @samp{/var/run}). - -@item -v, --verbose - Log extra debugging information. - -@item -V, --version - Print version information and exit. - -@item -d, --daemon - Daemonize after startup (detach from terminal). - -@item -b, --blacklist=@var{list} - Comma-separated list of RPCs to disable (no spaces, @samp{?} to list - available RPCs). - -@item -D, --dump-conf - Dump the configuration in a format compatible with @file{qemu-ga.conf} - and exit. - -@item -h, --help - Display this help and exit. -@end table - -@c man end - -@c man begin FILES - -The syntax of the @file{qemu-ga.conf} configuration file follows the -Desktop Entry Specification, here is a quick summary: it consists of -groups of key-value pairs, interspersed with comments. - -@example -# qemu-ga configuration sample -[general] -daemonize = 0 -pidfile = /var/run/qemu-ga.pid -verbose = 0 -method = virtio-serial -path = /dev/virtio-ports/org.qemu.guest_agent.0 -statedir = /var/run -@end example - -The list of keys follows the command line options: -@table @option -@item daemon= boolean -@item method= string -@item path= string -@item logfile= string -@item pidfile= string -@item fsfreeze-hook= string -@item statedir= string -@item verbose= boolean -@item blacklist= string list -@end table - -@c man end - -@ignore - -@setfilename qemu-ga -@settitle QEMU Guest Agent - -@c man begin AUTHOR -Michael Roth <mdroth@linux.vnet.ibm.com> -@c man end - -@c man begin SEEALSO -qemu(1) -@c man end - -@end ignore diff --git a/qemu-img.c b/qemu-img.c index 4ee436fc94..384c6f38bc 100644 --- a/qemu-img.c +++ b/qemu-img.c @@ -2141,7 +2141,7 @@ static int img_convert(int argc, char **argv) int64_t sval; sval = cvtnum(optarg); - if (sval < 0 || sval & (BDRV_SECTOR_SIZE - 1) || + if (sval < 0 || !QEMU_IS_ALIGNED(sval, BDRV_SECTOR_SIZE) || sval / BDRV_SECTOR_SIZE > MAX_BUF_SECTORS) { error_report("Invalid buffer size for sparse output specified. " "Valid sizes are multiples of %llu up to %llu. Select " diff --git a/qemu-io-cmds.c b/qemu-io-cmds.c index d46fa166d3..349256a5fe 100644 --- a/qemu-io-cmds.c +++ b/qemu-io-cmds.c @@ -401,6 +401,7 @@ static void *qemu_io_alloc_from_file(BlockBackend *blk, size_t len, } fclose(f); + f = NULL; if (len > pattern_len) { len -= pattern_len; @@ -420,6 +421,9 @@ static void *qemu_io_alloc_from_file(BlockBackend *blk, size_t len, error: qemu_io_free(buf_origin); + if (f) { + fclose(f); + } return NULL; } diff --git a/qemu.nsi b/qemu.nsi index d0df0f4e3a..0c29ba359c 100644 --- a/qemu.nsi +++ b/qemu.nsi @@ -119,7 +119,7 @@ Section "${PRODUCT} (required)" File "${SRCDIR}\Changelog" File "${SRCDIR}\COPYING" File "${SRCDIR}\COPYING.LIB" - File "${SRCDIR}\README" + File "${SRCDIR}\README.rst" File "${SRCDIR}\VERSION" File "${BINDIR}\*.bmp" @@ -211,7 +211,7 @@ Section "Uninstall" Delete "$INSTDIR\Changelog" Delete "$INSTDIR\COPYING" Delete "$INSTDIR\COPYING.LIB" - Delete "$INSTDIR\README" + Delete "$INSTDIR\README.rst" Delete "$INSTDIR\VERSION" Delete "$INSTDIR\*.bmp" Delete "$INSTDIR\*.bin" diff --git a/roms/Makefile b/roms/Makefile index 775c963f9d..6cf07d3b44 100644 --- a/roms/Makefile +++ b/roms/Makefile @@ -182,8 +182,8 @@ opensbi64-virt: opensbi64-sifive_u: $(MAKE) -C opensbi \ CROSS_COMPILE=$(riscv64_cross_prefix) \ - PLATFORM="qemu/sifive_u" - cp opensbi/build/platform/qemu/sifive_u/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin + PLATFORM="sifive/fu540" + cp opensbi/build/platform/sifive/fu540/firmware/fw_jump.bin ../pc-bios/opensbi-riscv64-sifive_u-fw_jump.bin clean: rm -rf seabios/.config seabios/out seabios/builds diff --git a/scripts/tracetool/__init__.py b/scripts/tracetool/__init__.py index 6fca674936..04279fa62e 100644 --- a/scripts/tracetool/__init__.py +++ b/scripts/tracetool/__init__.py @@ -277,6 +277,9 @@ class Event(object): if fmt.find("%m") != -1 or fmt_trans.find("%m") != -1: raise ValueError("Event format '%m' is forbidden, pass the error " "as an explicit trace argument") + if fmt.endswith(r'\n"'): + raise ValueError("Event format must not end with a newline " + "character") if len(fmt_trans) > 0: fmt = [fmt_trans, fmt] diff --git a/scsi/pr-manager.c b/scsi/pr-manager.c index ee43663576..0c866e8698 100644 --- a/scsi/pr-manager.c +++ b/scsi/pr-manager.c @@ -39,7 +39,6 @@ static int pr_manager_worker(void *opaque) int fd = data->fd; int r; - g_free(data); trace_pr_manager_run(fd, hdr->cmdp[0], hdr->cmdp[1]); /* The reference was taken in pr_manager_execute. */ diff --git a/target/hppa/translate.c b/target/hppa/translate.c index 53e17d8963..c1b2822f60 100644 --- a/target/hppa/translate.c +++ b/target/hppa/translate.c @@ -2214,10 +2214,11 @@ static bool trans_mtsp(DisasContext *ctx, arg_mtsp *a) static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) { unsigned ctl = a->t; - TCGv_reg reg = load_gpr(ctx, a->r); + TCGv_reg reg; TCGv_reg tmp; if (ctl == CR_SAR) { + reg = load_gpr(ctx, a->r); tmp = tcg_temp_new(); tcg_gen_andi_reg(tmp, reg, TARGET_REGISTER_BITS - 1); save_or_nullify(ctx, cpu_sar, tmp); @@ -2232,6 +2233,8 @@ static bool trans_mtctl(DisasContext *ctx, arg_mtctl *a) #ifndef CONFIG_USER_ONLY nullify_over(ctx); + reg = load_gpr(ctx, a->r); + switch (ctl) { case CR_IT: gen_helper_write_interval_timer(cpu_env, reg); @@ -3401,10 +3404,6 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, TCGv_reg mask, tmp, shift, dest; unsigned msb = 1U << (len - 1); - if (c) { - nullify_over(ctx); - } - dest = dest_gpr(ctx, rt); shift = tcg_temp_new(); tmp = tcg_temp_new(); @@ -3437,11 +3436,17 @@ static bool do_depw_sar(DisasContext *ctx, unsigned rt, unsigned c, static bool trans_depw_sar(DisasContext *ctx, arg_depw_sar *a) { + if (a->c) { + nullify_over(ctx); + } return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_gpr(ctx, a->r)); } static bool trans_depwi_sar(DisasContext *ctx, arg_depwi_sar *a) { + if (a->c) { + nullify_over(ctx); + } return do_depw_sar(ctx, a->t, a->c, a->nz, a->clen, load_const(ctx, a->i)); } diff --git a/target/i386/kvm.c b/target/i386/kvm.c index 8023c679ea..92069099ab 100644 --- a/target/i386/kvm.c +++ b/target/i386/kvm.c @@ -41,6 +41,7 @@ #include "hw/i386/apic-msidef.h" #include "hw/i386/intel_iommu.h" #include "hw/i386/x86-iommu.h" +#include "hw/i386/e820_memory_layout.h" #include "hw/pci/pci.h" #include "hw/pci/msi.h" @@ -2076,7 +2077,8 @@ int kvm_arch_init(MachineState *ms, KVMState *s) if (disable_exits) { disable_exits &= (KVM_X86_DISABLE_EXITS_MWAIT | KVM_X86_DISABLE_EXITS_HLT | - KVM_X86_DISABLE_EXITS_PAUSE); + KVM_X86_DISABLE_EXITS_PAUSE | + KVM_X86_DISABLE_EXITS_CSTATE); } ret = kvm_vm_enable_cap(s, KVM_CAP_X86_DISABLE_EXITS, 0, diff --git a/target/mips/cpu.c b/target/mips/cpu.c index 3ffa342187..bbcf7ca463 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -202,7 +202,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->gdb_read_register = mips_cpu_gdb_read_register; cc->gdb_write_register = mips_cpu_gdb_write_register; #ifndef CONFIG_USER_ONLY - cc->do_unassigned_access = mips_cpu_unassigned_access; + cc->do_transaction_failed = mips_cpu_do_transaction_failed; cc->do_unaligned_access = mips_cpu_do_unaligned_access; cc->get_phys_page_debug = mips_cpu_get_phys_page_debug; cc->vmsd = &vmstate_mips_cpu; diff --git a/target/mips/gdbstub.c b/target/mips/gdbstub.c index ebcc98bdde..bbb2544939 100644 --- a/target/mips/gdbstub.c +++ b/target/mips/gdbstub.c @@ -38,7 +38,7 @@ int mips_cpu_gdb_read_register(CPUState *cs, uint8_t *mem_buf, int n) return gdb_get_regl(mem_buf, (int32_t)env->active_fpu.fcr0); default: if (env->CP0_Status & (1 << CP0St_FR)) { - return gdb_get_reg64(mem_buf, + return gdb_get_regl(mem_buf, env->active_fpu.fpr[n - 38].d); } else { return gdb_get_regl(mem_buf, @@ -99,7 +99,6 @@ int mips_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n) break; default: if (env->CP0_Status & (1 << CP0St_FR)) { - uint64_t tmp = ldq_p(mem_buf); env->active_fpu.fpr[n - 38].d = tmp; } else { env->active_fpu.fpr[n - 38].w[FP_ENDIAN_IDX] = tmp; diff --git a/target/mips/internal.h b/target/mips/internal.h index ae29b578a4..685e8d67e9 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -139,9 +139,11 @@ void r4k_helper_tlbinv(CPUMIPSState *env); void r4k_helper_tlbinvf(CPUMIPSState *env); void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); -void mips_cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, int unused, - unsigned size); +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, int rw); #endif diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c index 01b9e78bf3..4de64657ef 100644 --- a/target/mips/op_helper.c +++ b/target/mips/op_helper.c @@ -2668,27 +2668,19 @@ void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, do_raise_exception_err(env, excp, error_code, retaddr); } -void mips_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int unused, - unsigned size) +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; - /* - * Raising an exception with KVM enabled will crash because it won't be from - * the main execution loop so the longjmp won't have a matching setjmp. - * Until we can trigger a bus error exception through KVM lets just ignore - * the access. - */ - if (kvm_enabled()) { - return; - } - - if (is_exec) { - raise_exception(env, EXCP_IBE); + if (access_type == MMU_INST_FETCH) { + do_raise_exception(env, EXCP_IBE, retaddr); } else { - raise_exception(env, EXCP_DBE); + do_raise_exception(env, EXCP_DBE, retaddr); } } #endif /* !CONFIG_USER_ONLY */ diff --git a/target/riscv/Makefile.objs b/target/riscv/Makefile.objs index b1c79bc1d1..ff651f69f6 100644 --- a/target/riscv/Makefile.objs +++ b/target/riscv/Makefile.objs @@ -1,4 +1,9 @@ -obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o pmp.o +obj-y += translate.o op_helper.o cpu_helper.o cpu.o csr.o fpu_helper.o gdbstub.o +obj-$(CONFIG_SOFTMMU) += pmp.o + +ifeq ($(CONFIG_SOFTMMU),y) +obj-y += monitor.o +endif DECODETREE = $(SRC_PATH)/scripts/decodetree.py diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6d52f97d7c..f13e298a36 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -34,17 +34,20 @@ static const char riscv_exts[26] = "IEMAFDQCLBJTPVNSUHKORWXYZG"; const char * const riscv_int_regnames[] = { - "zero", "ra", "sp", "gp", "tp", "t0", "t1", "t2", - "s0", "s1", "a0", "a1", "a2", "a3", "a4", "a5", - "a6", "a7", "s2", "s3", "s4", "s5", "s6", "s7", - "s8", "s9", "s10", "s11", "t3", "t4", "t5", "t6" + "x0/zero", "x1/ra", "x2/sp", "x3/gp", "x4/tp", "x5/t0", "x6/t1", + "x7/t2", "x8/s0", "x9/s1", "x10/a0", "x11/a1", "x12/a2", "x13/a3", + "x14/a4", "x15/a5", "x16/a6", "x17/a7", "x18/s2", "x19/s3", "x20/s4", + "x21/s5", "x22/s6", "x23/s7", "x24/s8", "x25/s9", "x26/s10", "x27/s11", + "x28/t3", "x29/t4", "x30/t5", "x31/t6" }; const char * const riscv_fpr_regnames[] = { - "ft0", "ft1", "ft2", "ft3", "ft4", "ft5", "ft6", "ft7", - "fs0", "fs1", "fa0", "fa1", "fa2", "fa3", "fa4", "fa5", - "fa6", "fa7", "fs2", "fs3", "fs4", "fs5", "fs6", "fs7", - "fs8", "fs9", "fs10", "fs11", "ft8", "ft9", "ft10", "ft11" + "f0/ft0", "f1/ft1", "f2/ft2", "f3/ft3", "f4/ft4", "f5/ft5", + "f6/ft6", "f7/ft7", "f8/fs0", "f9/fs1", "f10/fa0", "f11/fa1", + "f12/fa2", "f13/fa3", "f14/fa4", "f15/fa5", "f16/fa6", "f17/fa7", + "f18/fs2", "f19/fs3", "f20/fs4", "f21/fs5", "f22/fs6", "f23/fs7", + "f24/fs8", "f25/fs9", "f26/fs10", "f27/fs11", "f28/ft8", "f29/ft9", + "f30/ft10", "f31/ft11" }; const char * const riscv_excp_names[] = { diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h index 18d91d0920..124ed33ee4 100644 --- a/target/riscv/cpu.h +++ b/target/riscv/cpu.h @@ -255,6 +255,7 @@ void riscv_cpu_do_interrupt(CPUState *cpu); int riscv_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int riscv_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request); +bool riscv_cpu_fp_enabled(CPURISCVState *env); int riscv_cpu_mmu_index(CPURISCVState *env, bool ifetch); hwaddr riscv_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); void riscv_cpu_do_unaligned_access(CPUState *cs, vaddr addr, @@ -298,7 +299,10 @@ static inline void cpu_get_tb_cpu_state(CPURISCVState *env, target_ulong *pc, #ifdef CONFIG_USER_ONLY *flags = TB_FLAGS_MSTATUS_FS; #else - *flags = cpu_mmu_index(env, 0) | (env->mstatus & MSTATUS_FS); + *flags = cpu_mmu_index(env, 0); + if (riscv_cpu_fp_enabled(env)) { + *flags |= TB_FLAGS_MSTATUS_FS; + } #endif } diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h index 11f971ad5d..e99834856c 100644 --- a/target/riscv/cpu_bits.h +++ b/target/riscv/cpu_bits.h @@ -173,6 +173,24 @@ #define CSR_SPTBR 0x180 #define CSR_SATP 0x180 +/* Hpervisor CSRs */ +#define CSR_HSTATUS 0x600 +#define CSR_HEDELEG 0x602 +#define CSR_HIDELEG 0x603 +#define CSR_HCOUNTERNEN 0x606 +#define CSR_HGATP 0x680 + +#if defined(TARGET_RISCV32) +#define HGATP_MODE SATP32_MODE +#define HGATP_VMID SATP32_ASID +#define HGATP_PPN SATP32_PPN +#endif +#if defined(TARGET_RISCV64) +#define HGATP_MODE SATP64_MODE +#define HGATP_VMID SATP64_ASID +#define HGATP_PPN SATP64_PPN +#endif + /* Physical Memory Protection */ #define CSR_PMPCFG0 0x3a0 #define CSR_PMPCFG1 0x3a1 @@ -206,23 +224,6 @@ #define CSR_DPC 0x7b1 #define CSR_DSCRATCH 0x7b2 -/* Hpervisor CSRs */ -#define CSR_HSTATUS 0xa00 -#define CSR_HEDELEG 0xa02 -#define CSR_HIDELEG 0xa03 -#define CSR_HGATP 0xa80 - -#if defined(TARGET_RISCV32) -#define HGATP_MODE SATP32_MODE -#define HGATP_ASID SATP32_ASID -#define HGATP_PPN SATP32_PPN -#endif -#if defined(TARGET_RISCV64) -#define HGATP_MODE SATP64_MODE -#define HGATP_ASID SATP64_ASID -#define HGATP_PPN SATP64_PPN -#endif - /* Performance Counters */ #define CSR_MHPMCOUNTER3 0xb03 #define CSR_MHPMCOUNTER4 0xb04 diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c index e32b6126af..87dd6a6ece 100644 --- a/target/riscv/cpu_helper.c +++ b/target/riscv/cpu_helper.c @@ -71,6 +71,16 @@ bool riscv_cpu_exec_interrupt(CPUState *cs, int interrupt_request) #if !defined(CONFIG_USER_ONLY) +/* Return true is floating point support is currently enabled */ +bool riscv_cpu_fp_enabled(CPURISCVState *env) +{ + if (env->mstatus & MSTATUS_FS) { + return true; + } + + return false; +} + int riscv_cpu_claim_interrupts(RISCVCPU *cpu, uint32_t interrupts) { CPURISCVState *env = &cpu->env; @@ -176,12 +186,12 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, *prot = 0; - target_ulong base; + hwaddr base; int levels, ptidxbits, ptesize, vm, sum; int mxr = get_field(env->mstatus, MSTATUS_MXR); if (env->priv_ver >= PRIV_VERSION_1_10_0) { - base = get_field(env->satp, SATP_PPN) << PGSHIFT; + base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; sum = get_field(env->mstatus, MSTATUS_SUM); vm = get_field(env->satp, SATP_MODE); switch (vm) { @@ -201,7 +211,7 @@ static int get_physical_address(CPURISCVState *env, hwaddr *physical, g_assert_not_reached(); } } else { - base = env->sptbr << PGSHIFT; + base = (hwaddr)(env->sptbr) << PGSHIFT; sum = !get_field(env->mstatus, MSTATUS_PUM); vm = get_field(env->mstatus, MSTATUS_VM); switch (vm) { @@ -239,7 +249,7 @@ restart: ((1 << ptidxbits) - 1); /* check that physical address of PTE is legal */ - target_ulong pte_addr = base + idx * ptesize; + hwaddr pte_addr = base + idx * ptesize; if (riscv_feature(env, RISCV_FEATURE_PMP) && !pmp_hart_has_privs(env, pte_addr, sizeof(target_ulong), @@ -251,7 +261,7 @@ restart: #elif defined(TARGET_RISCV64) target_ulong pte = ldq_phys(cs->as, pte_addr); #endif - target_ulong ppn = pte >> PTE_PPN_SHIFT; + hwaddr ppn = pte >> PTE_PPN_SHIFT; if (!(pte & PTE_V)) { /* Invalid PTE */ diff --git a/target/riscv/csr.c b/target/riscv/csr.c index e0d4586760..f767ad24be 100644 --- a/target/riscv/csr.c +++ b/target/riscv/csr.c @@ -46,7 +46,7 @@ void riscv_set_csr_ops(int csrno, riscv_csr_operations *ops) static int fs(CPURISCVState *env, int csrno) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -108,7 +108,7 @@ static int pmp(CPURISCVState *env, int csrno) static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -119,7 +119,7 @@ static int read_fflags(CPURISCVState *env, int csrno, target_ulong *val) static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |= MSTATUS_FS; @@ -131,7 +131,7 @@ static int write_fflags(CPURISCVState *env, int csrno, target_ulong val) static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -142,7 +142,7 @@ static int read_frm(CPURISCVState *env, int csrno, target_ulong *val) static int write_frm(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |= MSTATUS_FS; @@ -154,7 +154,7 @@ static int write_frm(CPURISCVState *env, int csrno, target_ulong val) static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } #endif @@ -166,7 +166,7 @@ static int read_fcsr(CPURISCVState *env, int csrno, target_ulong *val) static int write_fcsr(CPURISCVState *env, int csrno, target_ulong val) { #if !defined(CONFIG_USER_ONLY) - if (!env->debugger && !(env->mstatus & MSTATUS_FS)) { + if (!env->debugger && !riscv_cpu_fp_enabled(env)) { return -1; } env->mstatus |= MSTATUS_FS; @@ -307,6 +307,7 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) { target_ulong mstatus = env->mstatus; target_ulong mask = 0; + int dirty; /* flush tlb on mstatus fields that affect VM */ if (env->priv_ver <= PRIV_VERSION_1_09_1) { @@ -334,14 +335,15 @@ static int write_mstatus(CPURISCVState *env, int csrno, target_ulong val) * RV32: MPV and MTL are not in mstatus. The current plan is to * add them to mstatush. For now, we just don't support it. */ - mask |= MSTATUS_MPP | MSTATUS_MPV; + mask |= MSTATUS_MTL | MSTATUS_MPV; #endif } mstatus = (mstatus & ~mask) | (val & mask); - int dirty = ((mstatus & MSTATUS_FS) == MSTATUS_FS) | - ((mstatus & MSTATUS_XS) == MSTATUS_XS); + dirty = (riscv_cpu_fp_enabled(env) && + ((mstatus & MSTATUS_FS) == MSTATUS_FS)) | + ((mstatus & MSTATUS_XS) == MSTATUS_XS); mstatus = set_field(mstatus, MSTATUS_SD, dirty); env->mstatus = mstatus; diff --git a/target/riscv/gdbstub.c b/target/riscv/gdbstub.c index 27be93279b..ded140e8d8 100644 --- a/target/riscv/gdbstub.c +++ b/target/riscv/gdbstub.c @@ -313,7 +313,8 @@ static int riscv_gdb_get_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) * register 33, so we recalculate the map index. * This also works for CSR_FRM and CSR_FCSR. */ - result = riscv_csrrw_debug(env, n - 33 + 8, &val, 0, 0); + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], &val, + 0, 0); if (result == 0) { return gdb_get_regl(mem_buf, val); } @@ -335,7 +336,8 @@ static int riscv_gdb_set_fpu(CPURISCVState *env, uint8_t *mem_buf, int n) * register 33, so we recalculate the map index. * This also works for CSR_FRM and CSR_FCSR. */ - result = riscv_csrrw_debug(env, n - 33 + 8, NULL, val, -1); + result = riscv_csrrw_debug(env, n - 33 + csr_register_map[8], NULL, + val, -1); if (result == 0) { return sizeof(target_ulong); } diff --git a/target/riscv/monitor.c b/target/riscv/monitor.c new file mode 100644 index 0000000000..d725a7a36e --- /dev/null +++ b/target/riscv/monitor.c @@ -0,0 +1,229 @@ +/* + * QEMU monitor for RISC-V + * + * Copyright (c) 2019 Bin Meng <bmeng.cn@gmail.com> + * + * RISC-V specific monitor commands implementation + * + * This program is free software; you can redistribute it and/or modify it + * under the terms and conditions of the GNU General Public License, + * version 2 or later, as published by the Free Software Foundation. + * + * This program is distributed in the hope it will be useful, but WITHOUT + * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for + * more details. + * + * You should have received a copy of the GNU General Public License along with + * this program. If not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "cpu_bits.h" +#include "monitor/monitor.h" +#include "monitor/hmp-target.h" + +#ifdef TARGET_RISCV64 +#define PTE_HEADER_FIELDS "vaddr paddr "\ + "size attr\n" +#define PTE_HEADER_DELIMITER "---------------- ---------------- "\ + "---------------- -------\n" +#else +#define PTE_HEADER_FIELDS "vaddr paddr size attr\n" +#define PTE_HEADER_DELIMITER "-------- ---------------- -------- -------\n" +#endif + +/* Perform linear address sign extension */ +static target_ulong addr_canonical(int va_bits, target_ulong addr) +{ +#ifdef TARGET_RISCV64 + if (addr & (1UL << (va_bits - 1))) { + addr |= (hwaddr)-(1L << va_bits); + } +#endif + + return addr; +} + +static void print_pte_header(Monitor *mon) +{ + monitor_printf(mon, PTE_HEADER_FIELDS); + monitor_printf(mon, PTE_HEADER_DELIMITER); +} + +static void print_pte(Monitor *mon, int va_bits, target_ulong vaddr, + hwaddr paddr, target_ulong size, int attr) +{ + /* santity check on vaddr */ + if (vaddr >= (1UL << va_bits)) { + return; + } + + if (!size) { + return; + } + + monitor_printf(mon, TARGET_FMT_lx " " TARGET_FMT_plx " " TARGET_FMT_lx + " %c%c%c%c%c%c%c\n", + addr_canonical(va_bits, vaddr), + paddr, size, + attr & PTE_R ? 'r' : '-', + attr & PTE_W ? 'w' : '-', + attr & PTE_X ? 'x' : '-', + attr & PTE_U ? 'u' : '-', + attr & PTE_G ? 'g' : '-', + attr & PTE_A ? 'a' : '-', + attr & PTE_D ? 'd' : '-'); +} + +static void walk_pte(Monitor *mon, hwaddr base, target_ulong start, + int level, int ptidxbits, int ptesize, int va_bits, + target_ulong *vbase, hwaddr *pbase, hwaddr *last_paddr, + target_ulong *last_size, int *last_attr) +{ + hwaddr pte_addr; + hwaddr paddr; + target_ulong pgsize; + target_ulong pte; + int ptshift; + int attr; + int idx; + + if (level < 0) { + return; + } + + ptshift = level * ptidxbits; + pgsize = 1UL << (PGSHIFT + ptshift); + + for (idx = 0; idx < (1UL << ptidxbits); idx++) { + pte_addr = base + idx * ptesize; + cpu_physical_memory_read(pte_addr, &pte, ptesize); + + paddr = (hwaddr)(pte >> PTE_PPN_SHIFT) << PGSHIFT; + attr = pte & 0xff; + + /* PTE has to be valid */ + if (attr & PTE_V) { + if (attr & (PTE_R | PTE_W | PTE_X)) { + /* + * A leaf PTE has been found + * + * If current PTE's permission bits differ from the last one, + * or current PTE's ppn does not make a contiguous physical + * address block together with the last one, print out the last + * contiguous mapped block details. + */ + if ((*last_attr != attr) || + (*last_paddr + *last_size != paddr)) { + print_pte(mon, va_bits, *vbase, *pbase, + *last_paddr + *last_size - *pbase, *last_attr); + + *vbase = start; + *pbase = paddr; + *last_attr = attr; + } + + *last_paddr = paddr; + *last_size = pgsize; + } else { + /* pointer to the next level of the page table */ + walk_pte(mon, paddr, start, level - 1, ptidxbits, ptesize, + va_bits, vbase, pbase, last_paddr, + last_size, last_attr); + } + } + + start += pgsize; + } + +} + +static void mem_info_svxx(Monitor *mon, CPUArchState *env) +{ + int levels, ptidxbits, ptesize, vm, va_bits; + hwaddr base; + target_ulong vbase; + hwaddr pbase; + hwaddr last_paddr; + target_ulong last_size; + int last_attr; + + base = (hwaddr)get_field(env->satp, SATP_PPN) << PGSHIFT; + + vm = get_field(env->satp, SATP_MODE); + switch (vm) { + case VM_1_10_SV32: + levels = 2; + ptidxbits = 10; + ptesize = 4; + break; + case VM_1_10_SV39: + levels = 3; + ptidxbits = 9; + ptesize = 8; + break; + case VM_1_10_SV48: + levels = 4; + ptidxbits = 9; + ptesize = 8; + break; + case VM_1_10_SV57: + levels = 5; + ptidxbits = 9; + ptesize = 8; + break; + default: + g_assert_not_reached(); + break; + } + + /* calculate virtual address bits */ + va_bits = PGSHIFT + levels * ptidxbits; + + /* print header */ + print_pte_header(mon); + + vbase = -1; + pbase = -1; + last_paddr = -1; + last_size = 0; + last_attr = 0; + + /* walk page tables, starting from address 0 */ + walk_pte(mon, base, 0, levels - 1, ptidxbits, ptesize, va_bits, + &vbase, &pbase, &last_paddr, &last_size, &last_attr); + + /* don't forget the last one */ + print_pte(mon, va_bits, vbase, pbase, + last_paddr + last_size - pbase, last_attr); +} + +void hmp_info_mem(Monitor *mon, const QDict *qdict) +{ + CPUArchState *env; + + env = mon_get_cpu_env(); + if (!env) { + monitor_printf(mon, "No CPU available\n"); + return; + } + + if (!riscv_feature(env, RISCV_FEATURE_MMU)) { + monitor_printf(mon, "S-mode MMU unavailable\n"); + return; + } + + if (env->priv_ver < PRIV_VERSION_1_10_0) { + monitor_printf(mon, "Privileged mode < 1.10 unsupported\n"); + return; + } + + if (!(env->satp & SATP_MODE)) { + monitor_printf(mon, "No translation or protection\n"); + return; + } + + mem_info_svxx(mon, env); +} diff --git a/target/riscv/pmp.c b/target/riscv/pmp.c index 958c7502a0..d4f1007109 100644 --- a/target/riscv/pmp.c +++ b/target/riscv/pmp.c @@ -27,16 +27,7 @@ #include "qemu/log.h" #include "qapi/error.h" #include "cpu.h" - -#ifndef CONFIG_USER_ONLY - -#define RISCV_DEBUG_PMP 0 -#define PMP_DEBUG(fmt, ...) \ - do { \ - if (RISCV_DEBUG_PMP) { \ - qemu_log_mask(LOG_TRACE, "%s: " fmt "\n", __func__, ##__VA_ARGS__);\ - } \ - } while (0) +#include "trace.h" static void pmp_write_cfg(CPURISCVState *env, uint32_t addr_index, uint8_t val); @@ -304,8 +295,7 @@ void pmpcfg_csr_write(CPURISCVState *env, uint32_t reg_index, int i; uint8_t cfg_val; - PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, - env->mhartid, reg_index, val); + trace_pmpcfg_csr_write(env->mhartid, reg_index, val); if ((reg_index & 1) && (sizeof(target_ulong) == 8)) { qemu_log_mask(LOG_GUEST_ERROR, @@ -334,9 +324,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) val = pmp_read_cfg(env, (reg_index * sizeof(target_ulong)) + i); cfg_val |= (val << (i * 8)); } - - PMP_DEBUG("hart " TARGET_FMT_ld ": reg%d, val: 0x" TARGET_FMT_lx, - env->mhartid, reg_index, cfg_val); + trace_pmpcfg_csr_read(env->mhartid, reg_index, cfg_val); return cfg_val; } @@ -348,9 +336,7 @@ target_ulong pmpcfg_csr_read(CPURISCVState *env, uint32_t reg_index) void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, target_ulong val) { - PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, - env->mhartid, addr_index, val); - + trace_pmpaddr_csr_write(env->mhartid, addr_index, val); if (addr_index < MAX_RISCV_PMPS) { if (!pmp_is_locked(env, addr_index)) { env->pmp_state.pmp[addr_index].addr_reg = val; @@ -371,16 +357,15 @@ void pmpaddr_csr_write(CPURISCVState *env, uint32_t addr_index, */ target_ulong pmpaddr_csr_read(CPURISCVState *env, uint32_t addr_index) { - PMP_DEBUG("hart " TARGET_FMT_ld ": addr%d, val: 0x" TARGET_FMT_lx, - env->mhartid, addr_index, - env->pmp_state.pmp[addr_index].addr_reg); + target_ulong val = 0; + if (addr_index < MAX_RISCV_PMPS) { - return env->pmp_state.pmp[addr_index].addr_reg; + val = env->pmp_state.pmp[addr_index].addr_reg; + trace_pmpaddr_csr_read(env->mhartid, addr_index, val); } else { qemu_log_mask(LOG_GUEST_ERROR, "ignoring pmpaddr read - out of bounds\n"); - return 0; } -} -#endif + return val; +} diff --git a/target/riscv/trace-events b/target/riscv/trace-events index 48af0373df..4b6c652ae9 100644 --- a/target/riscv/trace-events +++ b/target/riscv/trace-events @@ -1,2 +1,8 @@ # target/riscv/cpu_helper.c riscv_trap(uint64_t hartid, bool async, uint64_t cause, uint64_t epc, uint64_t tval, const char *desc) "hart:%"PRId64", async:%d, cause:%"PRId64", epc:0x%"PRIx64", tval:0x%"PRIx64", desc=%s" + +# pmp.c +pmpcfg_csr_read(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": read reg%" PRIu32", val: 0x%" PRIx64 +pmpcfg_csr_write(uint64_t mhartid, uint32_t reg_index, uint64_t val) "hart %" PRIu64 ": write reg%" PRIu32", val: 0x%" PRIx64 +pmpaddr_csr_read(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": read addr%" PRIu32", val: 0x%" PRIx64 +pmpaddr_csr_write(uint64_t mhartid, uint32_t addr_index, uint64_t val) "hart %" PRIu64 ": write addr%" PRIu32", val: 0x%" PRIx64 diff --git a/target/sparc/cpu.c b/target/sparc/cpu.c index ee60a5536a..bc65929552 100644 --- a/target/sparc/cpu.c +++ b/target/sparc/cpu.c @@ -877,7 +877,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->gdb_write_register = sparc_cpu_gdb_write_register; cc->tlb_fill = sparc_cpu_tlb_fill; #ifndef CONFIG_USER_ONLY - cc->do_unassigned_access = sparc_cpu_unassigned_access; + cc->do_transaction_failed = sparc_cpu_do_transaction_failed; cc->do_unaligned_access = sparc_cpu_do_unaligned_access; cc->get_phys_page_debug = sparc_cpu_get_phys_page_debug; cc->vmsd = &vmstate_sparc_cpu; diff --git a/target/sparc/cpu.h b/target/sparc/cpu.h index 490e14dfcf..778aa8e073 100644 --- a/target/sparc/cpu.h +++ b/target/sparc/cpu.h @@ -614,9 +614,11 @@ static inline int tlb_compare_context(const SparcTLBEntry *tlb, /* cpu-exec.c */ #if !defined(CONFIG_USER_ONLY) -void sparc_cpu_unassigned_access(CPUState *cpu, hwaddr addr, - bool is_write, bool is_exec, int is_asi, - unsigned size); +void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); #if defined(TARGET_SPARC64) hwaddr cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong addr, int mmu_idx); diff --git a/target/sparc/ldst_helper.c b/target/sparc/ldst_helper.c index 7f56c100c6..7345827a96 100644 --- a/target/sparc/ldst_helper.c +++ b/target/sparc/ldst_helper.c @@ -422,6 +422,99 @@ static void dump_asi(const char *txt, target_ulong addr, int asi, int size, } #endif +#ifndef CONFIG_USER_ONLY +#ifndef TARGET_SPARC64 +static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, + bool is_write, bool is_exec, int is_asi, + unsigned size, uintptr_t retaddr) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + int fault_type; + +#ifdef DEBUG_UNASSIGNED + if (is_asi) { + printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx + " asi 0x%02x from " TARGET_FMT_lx "\n", + is_exec ? "exec" : is_write ? "write" : "read", size, + size == 1 ? "" : "s", addr, is_asi, env->pc); + } else { + printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx + " from " TARGET_FMT_lx "\n", + is_exec ? "exec" : is_write ? "write" : "read", size, + size == 1 ? "" : "s", addr, env->pc); + } +#endif + /* Don't overwrite translation and access faults */ + fault_type = (env->mmuregs[3] & 0x1c) >> 2; + if ((fault_type > 4) || (fault_type == 0)) { + env->mmuregs[3] = 0; /* Fault status register */ + if (is_asi) { + env->mmuregs[3] |= 1 << 16; + } + if (env->psrs) { + env->mmuregs[3] |= 1 << 5; + } + if (is_exec) { + env->mmuregs[3] |= 1 << 6; + } + if (is_write) { + env->mmuregs[3] |= 1 << 7; + } + env->mmuregs[3] |= (5 << 2) | 2; + /* SuperSPARC will never place instruction fault addresses in the FAR */ + if (!is_exec) { + env->mmuregs[4] = addr; /* Fault address register */ + } + } + /* overflow (same type fault was not read before another fault) */ + if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { + env->mmuregs[3] |= 1; + } + + if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { + int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS; + cpu_raise_exception_ra(env, tt, retaddr); + } + + /* + * flush neverland mappings created during no-fault mode, + * so the sequential MMU faults report proper fault types + */ + if (env->mmuregs[0] & MMU_NF) { + tlb_flush(cs); + } +} +#else +static void sparc_raise_mmu_fault(CPUState *cs, hwaddr addr, + bool is_write, bool is_exec, int is_asi, + unsigned size, uintptr_t retaddr) +{ + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + +#ifdef DEBUG_UNASSIGNED + printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx + "\n", addr, env->pc); +#endif + + if (is_exec) { /* XXX has_hypervisor */ + if (env->lsu & (IMMU_E)) { + cpu_raise_exception_ra(env, TT_CODE_ACCESS, retaddr); + } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { + cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, retaddr); + } + } else { + if (env->lsu & (DMMU_E)) { + cpu_raise_exception_ra(env, TT_DATA_ACCESS, retaddr); + } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { + cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, retaddr); + } + } +} +#endif +#endif + #ifndef TARGET_SPARC64 #ifndef CONFIG_USER_ONLY @@ -625,26 +718,36 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, case ASI_M_DATAC_DATA: /* SparcStation 5 D-cache data */ break; case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ + { + MemTxResult result; + hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); + switch (size) { case 1: - ret = ldub_phys(cs->as, (hwaddr)addr - | ((hwaddr)(asi & 0xf) << 32)); + ret = address_space_ldub(cs->as, access_addr, + MEMTXATTRS_UNSPECIFIED, &result); break; case 2: - ret = lduw_phys(cs->as, (hwaddr)addr - | ((hwaddr)(asi & 0xf) << 32)); + ret = address_space_lduw(cs->as, access_addr, + MEMTXATTRS_UNSPECIFIED, &result); break; default: case 4: - ret = ldl_phys(cs->as, (hwaddr)addr - | ((hwaddr)(asi & 0xf) << 32)); + ret = address_space_ldl(cs->as, access_addr, + MEMTXATTRS_UNSPECIFIED, &result); break; case 8: - ret = ldq_phys(cs->as, (hwaddr)addr - | ((hwaddr)(asi & 0xf) << 32)); + ret = address_space_ldq(cs->as, access_addr, + MEMTXATTRS_UNSPECIFIED, &result); break; } + + if (result != MEMTX_OK) { + sparc_raise_mmu_fault(cs, access_addr, false, false, false, + size, GETPC()); + } break; + } case 0x30: /* Turbosparc secondary cache diagnostic */ case 0x31: /* Turbosparc RAM snoop */ case 0x32: /* Turbosparc page table descriptor diagnostic */ @@ -688,7 +791,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, break; case ASI_USERTXT: /* User code access, XXX */ default: - cpu_unassigned_access(cs, addr, false, false, asi, size); + sparc_raise_mmu_fault(cs, addr, false, false, asi, size, GETPC()); ret = 0; break; @@ -777,6 +880,9 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, } break; case 0x01c00100: /* MXCC stream source */ + { + int i; + if (size == 8) { env->mxccregs[0] = val; } else { @@ -784,20 +890,27 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, "%08x: unimplemented access size: %d\n", addr, size); } - env->mxccdata[0] = ldq_phys(cs->as, - (env->mxccregs[0] & 0xffffffffULL) + - 0); - env->mxccdata[1] = ldq_phys(cs->as, - (env->mxccregs[0] & 0xffffffffULL) + - 8); - env->mxccdata[2] = ldq_phys(cs->as, - (env->mxccregs[0] & 0xffffffffULL) + - 16); - env->mxccdata[3] = ldq_phys(cs->as, - (env->mxccregs[0] & 0xffffffffULL) + - 24); + + for (i = 0; i < 4; i++) { + MemTxResult result; + hwaddr access_addr = (env->mxccregs[0] & 0xffffffffULL) + 8 * i; + + env->mxccdata[i] = address_space_ldq(cs->as, + access_addr, + MEMTXATTRS_UNSPECIFIED, + &result); + if (result != MEMTX_OK) { + /* TODO: investigate whether this is the right behaviour */ + sparc_raise_mmu_fault(cs, access_addr, false, false, + false, size, GETPC()); + } + } break; + } case 0x01c00200: /* MXCC stream destination */ + { + int i; + if (size == 8) { env->mxccregs[1] = val; } else { @@ -805,15 +918,22 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, "%08x: unimplemented access size: %d\n", addr, size); } - stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 0, - env->mxccdata[0]); - stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 8, - env->mxccdata[1]); - stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 16, - env->mxccdata[2]); - stq_phys(cs->as, (env->mxccregs[1] & 0xffffffffULL) + 24, - env->mxccdata[3]); + + for (i = 0; i < 4; i++) { + MemTxResult result; + hwaddr access_addr = (env->mxccregs[1] & 0xffffffffULL) + 8 * i; + + address_space_stq(cs->as, access_addr, env->mxccdata[i], + MEMTXATTRS_UNSPECIFIED, &result); + + if (result != MEMTX_OK) { + /* TODO: investigate whether this is the right behaviour */ + sparc_raise_mmu_fault(cs, access_addr, true, false, + false, size, GETPC()); + } + } break; + } case 0x01c00a00: /* MXCC control register */ if (size == 8) { env->mxccregs[3] = val; @@ -960,25 +1080,32 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, break; case 0x21 ... 0x2f: /* MMU passthrough, 0x100000000 to 0xfffffffff */ { + MemTxResult result; + hwaddr access_addr = (hwaddr)addr | ((hwaddr)(asi & 0xf) << 32); + switch (size) { case 1: - stb_phys(cs->as, (hwaddr)addr - | ((hwaddr)(asi & 0xf) << 32), val); + address_space_stb(cs->as, access_addr, val, + MEMTXATTRS_UNSPECIFIED, &result); break; case 2: - stw_phys(cs->as, (hwaddr)addr - | ((hwaddr)(asi & 0xf) << 32), val); + address_space_stw(cs->as, access_addr, val, + MEMTXATTRS_UNSPECIFIED, &result); break; case 4: default: - stl_phys(cs->as, (hwaddr)addr - | ((hwaddr)(asi & 0xf) << 32), val); + address_space_stl(cs->as, access_addr, val, + MEMTXATTRS_UNSPECIFIED, &result); break; case 8: - stq_phys(cs->as, (hwaddr)addr - | ((hwaddr)(asi & 0xf) << 32), val); + address_space_stq(cs->as, access_addr, val, + MEMTXATTRS_UNSPECIFIED, &result); break; } + if (result != MEMTX_OK) { + sparc_raise_mmu_fault(cs, access_addr, true, false, false, + size, GETPC()); + } } break; case 0x30: /* store buffer tags or Turbosparc secondary cache diagnostic */ @@ -1026,7 +1153,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, uint64_t val, case ASI_USERTXT: /* User code access, XXX */ case ASI_KERNELTXT: /* Supervisor code access, XXX */ default: - cpu_unassigned_access(cs, addr, true, false, asi, size); + sparc_raise_mmu_fault(cs, addr, true, false, asi, size, GETPC()); break; case ASI_USERDATA: /* User data access */ @@ -1292,7 +1419,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, ret = env->immu.tag_access; break; default: - cpu_unassigned_access(cs, addr, false, false, 1, size); + sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); ret = 0; } break; @@ -1358,7 +1485,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, ret = env->dmmu.physical_watchpoint; break; default: - cpu_unassigned_access(cs, addr, false, false, 1, size); + sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); ret = 0; } break; @@ -1407,7 +1534,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ if (unlikely((addr >= 0x20) && (addr < 0x30))) { /* Hyperprivileged access only */ - cpu_unassigned_access(cs, addr, false, false, 1, size); + sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); } /* fall through */ case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ @@ -1425,7 +1552,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, ret = env->dmmu.mmu_secondary_context; break; default: - cpu_unassigned_access(cs, addr, true, false, 1, size); + sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); } break; case ASI_DCACHE_DATA: /* D-cache data */ @@ -1448,7 +1575,7 @@ uint64_t helper_ld_asi(CPUSPARCState *env, target_ulong addr, case ASI_DMMU_DEMAP: /* D-MMU demap, WO */ case ASI_INTR_W: /* Interrupt vector, WO */ default: - cpu_unassigned_access(cs, addr, false, false, 1, size); + sparc_raise_mmu_fault(cs, addr, false, false, 1, size, GETPC()); ret = 0; break; } @@ -1622,7 +1749,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, case 8: return; default: - cpu_unassigned_access(cs, addr, true, false, 1, size); + sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); break; } @@ -1706,7 +1833,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, env->dmmu.physical_watchpoint = val; break; default: - cpu_unassigned_access(cs, addr, true, false, 1, size); + sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); break; } @@ -1750,7 +1877,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, case ASI_SCRATCHPAD: /* UA2005 privileged scratchpad */ if (unlikely((addr >= 0x20) && (addr < 0x30))) { /* Hyperprivileged access only */ - cpu_unassigned_access(cs, addr, true, false, 1, size); + sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); } /* fall through */ case ASI_HYP_SCRATCHPAD: /* UA2005 hyperprivileged scratchpad */ @@ -1776,7 +1903,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, (1 << MMU_KERNEL_SECONDARY_IDX)); break; default: - cpu_unassigned_access(cs, addr, true, false, 1, size); + sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); } } return; @@ -1808,7 +1935,7 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, case ASI_PNFL: /* Primary no-fault LE, RO */ case ASI_SNFL: /* Secondary no-fault LE, RO */ default: - cpu_unassigned_access(cs, addr, true, false, 1, size); + sparc_raise_mmu_fault(cs, addr, true, false, 1, size, GETPC()); return; } } @@ -1816,95 +1943,21 @@ void helper_st_asi(CPUSPARCState *env, target_ulong addr, target_ulong val, #endif /* TARGET_SPARC64 */ #if !defined(CONFIG_USER_ONLY) -#ifndef TARGET_SPARC64 -void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int is_asi, - unsigned size) -{ - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - int fault_type; -#ifdef DEBUG_UNASSIGNED - if (is_asi) { - printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx - " asi 0x%02x from " TARGET_FMT_lx "\n", - is_exec ? "exec" : is_write ? "write" : "read", size, - size == 1 ? "" : "s", addr, is_asi, env->pc); - } else { - printf("Unassigned mem %s access of %d byte%s to " TARGET_FMT_plx - " from " TARGET_FMT_lx "\n", - is_exec ? "exec" : is_write ? "write" : "read", size, - size == 1 ? "" : "s", addr, env->pc); - } -#endif - /* Don't overwrite translation and access faults */ - fault_type = (env->mmuregs[3] & 0x1c) >> 2; - if ((fault_type > 4) || (fault_type == 0)) { - env->mmuregs[3] = 0; /* Fault status register */ - if (is_asi) { - env->mmuregs[3] |= 1 << 16; - } - if (env->psrs) { - env->mmuregs[3] |= 1 << 5; - } - if (is_exec) { - env->mmuregs[3] |= 1 << 6; - } - if (is_write) { - env->mmuregs[3] |= 1 << 7; - } - env->mmuregs[3] |= (5 << 2) | 2; - /* SuperSPARC will never place instruction fault addresses in the FAR */ - if (!is_exec) { - env->mmuregs[4] = addr; /* Fault address register */ - } - } - /* overflow (same type fault was not read before another fault) */ - if (fault_type == ((env->mmuregs[3] & 0x1c)) >> 2) { - env->mmuregs[3] |= 1; - } - - if ((env->mmuregs[0] & MMU_E) && !(env->mmuregs[0] & MMU_NF)) { - int tt = is_exec ? TT_CODE_ACCESS : TT_DATA_ACCESS; - cpu_raise_exception_ra(env, tt, GETPC()); - } - - /* flush neverland mappings created during no-fault mode, - so the sequential MMU faults report proper fault types */ - if (env->mmuregs[0] & MMU_NF) { - tlb_flush(cs); - } -} -#else -void sparc_cpu_unassigned_access(CPUState *cs, hwaddr addr, - bool is_write, bool is_exec, int is_asi, - unsigned size) +void sparc_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) { - SPARCCPU *cpu = SPARC_CPU(cs); - CPUSPARCState *env = &cpu->env; - -#ifdef DEBUG_UNASSIGNED - printf("Unassigned mem access to " TARGET_FMT_plx " from " TARGET_FMT_lx - "\n", addr, env->pc); -#endif + bool is_write = access_type == MMU_DATA_STORE; + bool is_exec = access_type == MMU_INST_FETCH; + bool is_asi = false; - if (is_exec) { /* XXX has_hypervisor */ - if (env->lsu & (IMMU_E)) { - cpu_raise_exception_ra(env, TT_CODE_ACCESS, GETPC()); - } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { - cpu_raise_exception_ra(env, TT_INSN_REAL_TRANSLATION_MISS, GETPC()); - } - } else { - if (env->lsu & (DMMU_E)) { - cpu_raise_exception_ra(env, TT_DATA_ACCESS, GETPC()); - } else if (cpu_has_hypervisor(env) && !(env->hpstate & HS_PRIV)) { - cpu_raise_exception_ra(env, TT_DATA_REAL_TRANSLATION_MISS, GETPC()); - } - } + sparc_raise_mmu_fault(cs, physaddr, is_write, is_exec, + is_asi, size, retaddr); } #endif -#endif #if !defined(CONFIG_USER_ONLY) void QEMU_NORETURN sparc_cpu_do_unaligned_access(CPUState *cs, vaddr addr, diff --git a/target/sparc/mmu_helper.c b/target/sparc/mmu_helper.c index 77dc86ac5c..afbfba7b7e 100644 --- a/target/sparc/mmu_helper.c +++ b/target/sparc/mmu_helper.c @@ -98,6 +98,7 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, int error_code = 0, is_dirty, is_user; unsigned long page_offset; CPUState *cs = env_cpu(env); + MemTxResult result; is_user = mmu_idx == MMU_USER_IDX; @@ -120,7 +121,10 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, /* SPARC reference MMU table walk: Context table->L1->L2->PTE */ /* Context base + context number */ pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); - pde = ldl_phys(cs->as, pde_ptr); + pde = address_space_ldl(cs->as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + return 4 << 2; /* Translation fault, L = 0 */ + } /* Ctx pde */ switch (pde & PTE_ENTRYTYPE_MASK) { @@ -132,7 +136,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, return 4 << 2; case 1: /* L0 PDE */ pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); - pde = ldl_phys(cs->as, pde_ptr); + pde = address_space_ldl(cs->as, pde_ptr, + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + return (1 << 8) | (4 << 2); /* Translation fault, L = 1 */ + } switch (pde & PTE_ENTRYTYPE_MASK) { default: @@ -142,7 +150,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, return (1 << 8) | (4 << 2); case 1: /* L1 PDE */ pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); - pde = ldl_phys(cs->as, pde_ptr); + pde = address_space_ldl(cs->as, pde_ptr, + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + return (2 << 8) | (4 << 2); /* Translation fault, L = 2 */ + } switch (pde & PTE_ENTRYTYPE_MASK) { default: @@ -152,7 +164,11 @@ static int get_physical_address(CPUSPARCState *env, hwaddr *physical, return (2 << 8) | (4 << 2); case 1: /* L2 PDE */ pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); - pde = ldl_phys(cs->as, pde_ptr); + pde = address_space_ldl(cs->as, pde_ptr, + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + return (3 << 8) | (4 << 2); /* Translation fault, L = 3 */ + } switch (pde & PTE_ENTRYTYPE_MASK) { default: @@ -272,11 +288,20 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) CPUState *cs = env_cpu(env); hwaddr pde_ptr; uint32_t pde; + MemTxResult result; + + /* + * TODO: MMU probe operations are supposed to set the fault + * status registers, but we don't do this. + */ /* Context base + context number */ pde_ptr = (hwaddr)(env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); - pde = ldl_phys(cs->as, pde_ptr); + pde = address_space_ldl(cs->as, pde_ptr, MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + return 0; + } switch (pde & PTE_ENTRYTYPE_MASK) { default: @@ -289,7 +314,11 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) return pde; } pde_ptr = ((address >> 22) & ~3) + ((pde & ~3) << 4); - pde = ldl_phys(cs->as, pde_ptr); + pde = address_space_ldl(cs->as, pde_ptr, + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + return 0; + } switch (pde & PTE_ENTRYTYPE_MASK) { default: @@ -303,7 +332,11 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) return pde; } pde_ptr = ((address & 0xfc0000) >> 16) + ((pde & ~3) << 4); - pde = ldl_phys(cs->as, pde_ptr); + pde = address_space_ldl(cs->as, pde_ptr, + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + return 0; + } switch (pde & PTE_ENTRYTYPE_MASK) { default: @@ -317,7 +350,11 @@ target_ulong mmu_probe(CPUSPARCState *env, target_ulong address, int mmulev) return pde; } pde_ptr = ((address & 0x3f000) >> 10) + ((pde & ~3) << 4); - pde = ldl_phys(cs->as, pde_ptr); + pde = address_space_ldl(cs->as, pde_ptr, + MEMTXATTRS_UNSPECIFIED, &result); + if (result != MEMTX_OK) { + return 0; + } switch (pde & PTE_ENTRYTYPE_MASK) { default: @@ -339,11 +376,9 @@ void dump_mmu(CPUSPARCState *env) CPUState *cs = env_cpu(env); target_ulong va, va1, va2; unsigned int n, m, o; - hwaddr pde_ptr, pa; + hwaddr pa; uint32_t pde; - pde_ptr = (env->mmuregs[1] << 4) + (env->mmuregs[2] << 2); - pde = ldl_phys(cs->as, pde_ptr); qemu_printf("Root ptr: " TARGET_FMT_plx ", ctx: %d\n", (hwaddr)env->mmuregs[1] << 4, env->mmuregs[2]); for (n = 0, va = 0; n < 256; n++, va += 16 * 1024 * 1024) { diff --git a/target/xtensa/cpu.c b/target/xtensa/cpu.c index 76db1741a7..c65dcf9dd7 100644 --- a/target/xtensa/cpu.c +++ b/target/xtensa/cpu.c @@ -53,6 +53,20 @@ static bool xtensa_cpu_has_work(CPUState *cs) #endif } +#ifdef CONFIG_USER_ONLY +static bool abi_call0; + +void xtensa_set_abi_call0(void) +{ + abi_call0 = true; +} + +bool xtensa_abi_call0(void) +{ + return abi_call0; +} +#endif + /* CPUClass::reset() */ static void xtensa_cpu_reset(CPUState *s) { @@ -70,10 +84,12 @@ static void xtensa_cpu_reset(CPUState *s) XTENSA_OPTION_INTERRUPT) ? 0x1f : 0x10; env->pending_irq_level = 0; #else - env->sregs[PS] = - (xtensa_option_enabled(env->config, - XTENSA_OPTION_WINDOWED_REGISTER) ? PS_WOE : 0) | - PS_UM | (3 << PS_RING_SHIFT); + env->sregs[PS] = PS_UM | (3 << PS_RING_SHIFT); + if (xtensa_option_enabled(env->config, + XTENSA_OPTION_WINDOWED_REGISTER) && + !xtensa_abi_call0()) { + env->sregs[PS] |= PS_WOE; + } #endif env->sregs[VECBASE] = env->config->vecbase; env->sregs[IBREAKENABLE] = 0; diff --git a/target/xtensa/cpu.h b/target/xtensa/cpu.h index 0459243e6b..b363ffcf10 100644 --- a/target/xtensa/cpu.h +++ b/target/xtensa/cpu.h @@ -673,6 +673,9 @@ static inline MemoryRegion *xtensa_get_er_region(CPUXtensaState *env) { return env->system_er; } +#else +void xtensa_set_abi_call0(void); +bool xtensa_abi_call0(void); #endif static inline uint32_t xtensa_replicate_windowstart(CPUXtensaState *env) diff --git a/tests/Makefile.include b/tests/Makefile.include index f5ac09549c..793632ca72 100644 --- a/tests/Makefile.include +++ b/tests/Makefile.include @@ -1059,26 +1059,29 @@ BUILD_TCG_TARGET_RULES=$(patsubst %,build-tcg-tests-%, $(TARGET_DIRS)) CLEAN_TCG_TARGET_RULES=$(patsubst %,clean-tcg-tests-%, $(TARGET_DIRS)) RUN_TCG_TARGET_RULES=$(patsubst %,run-tcg-tests-%, $(TARGET_DIRS)) -ifeq ($(HAVE_USER_DOCKER),y) # Probe for the Docker Builds needed for each build $(foreach PROBE_TARGET,$(TARGET_DIRS), \ - $(eval -include $(SRC_PATH)/tests/tcg/Makefile.probe) \ - $(if $(DOCKER_PREREQ), \ - $(eval build-tcg-tests-$(PROBE_TARGET): $(DOCKER_PREREQ)))) -endif + $(eval -include $(SRC_PATH)/tests/tcg/Makefile.prereqs)) build-tcg-tests-%: - $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \ - SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" guest-tests, \ + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) \ + -f $(SRC_PATH)/tests/tcg/Makefile.qemu \ + SRC_PATH=$(SRC_PATH) \ + V="$(V)" TARGET="$*" guest-tests, \ "BUILD", "TCG tests for $*") -run-tcg-tests-%: % build-tcg-tests-% - $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" \ - SKIP_DOCKER_BUILD=1 TARGET_DIR="$*/" run-guest-tests, \ +run-tcg-tests-%: build-tcg-tests-% %/all + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) \ + -f $(SRC_PATH)/tests/tcg/Makefile.qemu \ + SRC_PATH=$(SRC_PATH) SPEED="$(SPEED)" \ + V="$(V)" TARGET="$*" run-guest-tests, \ "RUN", "TCG tests for $*") clean-tcg-tests-%: - $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) -C $* V="$(V)" TARGET_DIR="$*/" clean-guest-tests,) + $(call quiet-command,$(MAKE) $(SUBDIR_MAKEFLAGS) \ + -f $(SRC_PATH)/tests/tcg/Makefile.qemu \ + SRC_PATH=$(SRC_PATH) TARGET="$*" clean-guest-tests, \ + "CLEAN", "TCG tests for $*") .PHONY: build-tcg build-tcg: $(BUILD_TCG_TARGET_RULES) @@ -1097,7 +1100,7 @@ QEMU_IOTESTS_HELPERS-$(call land,$(CONFIG_SOFTMMU),$(CONFIG_LINUX)) = tests/qemu check-tests/check-block.sh: tests/check-block.sh qemu-img$(EXESUF) \ qemu-io$(EXESUF) qemu-nbd$(EXESUF) $(QEMU_IOTESTS_HELPERS-y) \ $(patsubst %,%/all,$(filter %-softmmu,$(TARGET_DIRS))) - $< + @$< .PHONY: $(patsubst %, check-%, $(check-qapi-schema-y)) $(patsubst %, check-%, $(check-qapi-schema-y)): check-%.json: $(SRC_PATH)/%.json diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index 2504ef0150..8a9a314ab4 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -76,8 +76,9 @@ class BootLinuxConsole(Test): :avocado: tags=arch:x86_64 :avocado: tags=machine:pc """ - kernel_url = ('https://download.fedoraproject.org/pub/fedora/linux/' - 'releases/29/Everything/x86_64/os/images/pxeboot/vmlinuz') + kernel_url = ('https://archives.fedoraproject.org/pub/archive/fedora' + '/linux/releases/29/Everything/x86_64/os/images/pxeboot' + '/vmlinuz') kernel_hash = '23bebd2680757891cf7adedb033532163a792495' kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) @@ -250,8 +251,9 @@ class BootLinuxConsole(Test): :avocado: tags=arch:aarch64 :avocado: tags=machine:virt """ - kernel_url = ('https://download.fedoraproject.org/pub/fedora/linux/' - 'releases/29/Everything/aarch64/os/images/pxeboot/vmlinuz') + kernel_url = ('https://archives.fedoraproject.org/pub/archive/fedora' + '/linux/releases/29/Everything/aarch64/os/images/pxeboot' + '/vmlinuz') kernel_hash = '8c73e469fc6ea06a58dc83a628fc695b693b8493' kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) @@ -271,8 +273,9 @@ class BootLinuxConsole(Test): :avocado: tags=arch:arm :avocado: tags=machine:virt """ - kernel_url = ('https://download.fedoraproject.org/pub/fedora/linux/' - 'releases/29/Everything/armhfp/os/images/pxeboot/vmlinuz') + kernel_url = ('https://archives.fedoraproject.org/pub/archive/fedora' + '/linux/releases/29/Everything/armhfp/os/images/pxeboot' + '/vmlinuz') kernel_hash = 'e9826d741b4fb04cadba8d4824d1ed3b7fb8b4d4' kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) @@ -318,8 +321,9 @@ class BootLinuxConsole(Test): :avocado: tags=arch:s390x :avocado: tags=machine:s390_ccw_virtio """ - kernel_url = ('https://download.fedoraproject.org/pub/fedora-secondary/' - 'releases/29/Everything/s390x/os/images/kernel.img') + kernel_url = ('https://archives.fedoraproject.org/pub/archive' + '/fedora-secondary/releases/29/Everything/s390x/os/images' + '/kernel.img') kernel_hash = 'e8e8439103ef8053418ef062644ffd46a7919313' kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) @@ -360,8 +364,9 @@ class BootLinuxConsole(Test): :avocado: tags=arch:ppc64 :avocado: tags=machine:pseries """ - kernel_url = ('https://download.fedoraproject.org/pub/fedora-secondary/' - 'releases/29/Everything/ppc64le/os/ppc/ppc64/vmlinuz') + kernel_url = ('https://archives.fedoraproject.org/pub/archive' + '/fedora-secondary/releases/29/Everything/ppc64le/os' + '/ppc/ppc64/vmlinuz') kernel_hash = '3fe04abfc852b66653b8c3c897a59a689270bc77' kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) diff --git a/tests/acceptance/linux_initrd.py b/tests/acceptance/linux_initrd.py index 23be5a63aa..c61d9826a4 100644 --- a/tests/acceptance/linux_initrd.py +++ b/tests/acceptance/linux_initrd.py @@ -54,8 +54,9 @@ class LinuxInitrd(Test): QEMU has supported up to 4 GiB initrd for recent kernel Expect guest can reach 'Unpacking initramfs...' """ - kernel_url = ('https://mirrors.kernel.org/fedora/releases/28/' - 'Everything/x86_64/os/images/pxeboot/vmlinuz') + kernel_url = ('https://archives.fedoraproject.org/pub/archive/fedora' + '/linux/releases/28/Everything/x86_64/os/images/pxeboot/' + 'vmlinuz') kernel_hash = '238e083e114c48200f80d889f7e32eeb2793e02a' kernel_path = self.fetch_asset(kernel_url, asset_hash=kernel_hash) max_size = 2 * (1024 ** 3) + 1 diff --git a/tests/docker/Makefile.include b/tests/docker/Makefile.include index cf535cbd19..50a400b573 100644 --- a/tests/docker/Makefile.include +++ b/tests/docker/Makefile.include @@ -6,7 +6,8 @@ DOCKER_SUFFIX := .docker DOCKER_FILES_DIR := $(SRC_PATH)/tests/docker/dockerfiles DOCKER_DEPRECATED_IMAGES := debian # we don't run tests on intermediate images (used as base by another image) -DOCKER_PARTIAL_IMAGES := debian debian8 debian9 debian8-mxe debian-ports debian-sid debian-bootstrap +DOCKER_PARTIAL_IMAGES := debian debian8 debian9 debian10 debian-sid +DEBIAN_PARTIAL_IMAGES += debian8-mxe debian-9-mxe debian-ports debian-bootstrap DOCKER_IMAGES := $(filter-out $(DOCKER_DEPRECATED_IMAGES),$(sort $(notdir $(basename $(wildcard $(DOCKER_FILES_DIR)/*.docker))))) DOCKER_TARGETS := $(patsubst %,docker-image-%,$(DOCKER_IMAGES)) # Use a global constant ccache directory to speed up repetitive builds @@ -71,7 +72,8 @@ docker-binfmt-image-debian-%: $(DOCKER_FILES_DIR)/debian-bootstrap.docker $(if $(wildcard $(EXECUTABLE)), \ $(call quiet-command, \ DEB_ARCH=$(DEB_ARCH) \ - DEB_TYPE=$(DEB_TYPE) \ + DEB_TYPE=$(DEB_TYPE) \ + $(if $(DEB_URL),DEB_URL=$(DEB_URL),) \ $(DOCKER_SCRIPT) build qemu:debian-$* $< \ $(if $V,,--quiet) $(if $(NOCACHE),--no-cache) \ $(if $(NOUSER),,--add-current-user) \ @@ -86,13 +88,16 @@ docker-binfmt-image-debian-%: $(DOCKER_FILES_DIR)/debian-bootstrap.docker endif # Enforce dependencies for composite images -docker-image-debian: docker-image-debian9 docker-image-debian9-mxe: docker-image-debian9 +ifeq ($(ARCH),x86_64) docker-image-debian-amd64: docker-image-debian9 +DOCKER_PARTIAL_IMAGES += debian-amd64-cross +else +docker-image-debian-amd64-cross: docker-image-debian10 +DOCKER_PARTIAL_IMAGES += debian-amd64 +endif docker-image-debian-armel-cross: docker-image-debian9 docker-image-debian-armhf-cross: docker-image-debian9 -docker-image-debian-arm64-cross: docker-image-debian9 -docker-image-debian-buster-arm64-cross: docker-image-debian10 docker-image-debian-mips-cross: docker-image-debian9 docker-image-debian-mipsel-cross: docker-image-debian9 docker-image-debian-mips64el-cross: docker-image-debian9 @@ -101,25 +106,41 @@ docker-image-debian-s390x-cross: docker-image-debian9 docker-image-debian-win32-cross: docker-image-debian9-mxe docker-image-debian-win64-cross: docker-image-debian9-mxe -docker-image-debian-alpha-cross: docker-image-debian-sid -docker-image-debian-hppa-cross: docker-image-debian-sid -docker-image-debian-m68k-cross: docker-image-debian-sid -docker-image-debian-sh4-cross: docker-image-debian-sid -docker-image-debian-sparc64-cross: docker-image-debian-sid -docker-image-debian-mips64-cross: docker-image-debian-sid -docker-image-debian-riscv64-cross: docker-image-debian-sid -docker-image-debian-powerpc-cross: docker-image-debian-sid -docker-image-debian-ppc64-cross: docker-image-debian-sid +# For non-x86 hosts not all cross-compilers have been packaged +ifneq ($(ARCH),x86_64) +DOCKER_PARTIAL_IMAGES += debian-mips-cross debian-mipsel-cross debian-mips64el-cross +DOCKER_PARTIAL_IMAGES += debian-ppc64el-cross +DOCKER_PARTIAL_IMAGES += debian-s390x-cross +DOCKER_PARTIAL_IMAGES += debian-win32-cross debian-win64-cross +DOCKER_PARTIAL_IMAGES += fedora travis +endif + +docker-image-debian-alpha-cross: docker-image-debian10 +docker-image-debian-arm64-cross: docker-image-debian10 +docker-image-debian-hppa-cross: docker-image-debian10 +docker-image-debian-m68k-cross: docker-image-debian10 +docker-image-debian-mips64-cross: docker-image-debian10 +docker-image-debian-powerpc-cross: docker-image-debian10 +docker-image-debian-ppc64-cross: docker-image-debian10 +docker-image-debian-riscv64-cross: docker-image-debian10 +docker-image-debian-sh4-cross: docker-image-debian10 +docker-image-debian-sparc64-cross: docker-image-debian10 + docker-image-travis: NOUSER=1 # Specialist build images, sometimes very limited tools docker-image-tricore-cross: docker-image-debian9 # These images may be good enough for building tests but not for test builds -DOCKER_PARTIAL_IMAGES += debian-alpha-cross debian-hppa-cross debian-m68k-cross debian-sh4-cross -DOCKER_PARTIAL_IMAGES += debian-sparc64-cross debian-mips64-cross debian-riscv64-cross -DOCKER_PARTIAL_IMAGES += debian-tricore-cross debian-powerpc-cross fedora-i386-cross -DOCKER_PARTIAL_IMAGES += fedora-cris-cross +DOCKER_PARTIAL_IMAGES += debian-alpha-cross +DOCKER_PARTIAL_IMAGES += debian-hppa-cross +DOCKER_PARTIAL_IMAGES += debian-m68k-cross debian-mips64-cross +DOCKER_PARTIAL_IMAGES += debian-powerpc-cross debian-ppc64-cross +DOCKER_PARTIAL_IMAGES += debian-riscv64-cross +DOCKER_PARTIAL_IMAGES += debian-sh4-cross debian-sparc64-cross +DOCKER_PARTIAL_IMAGES += debian-tricore-cross +DOCKER_PARTIAL_IMAGES += debian-xtensa-cross +DOCKER_PARTIAL_IMAGES += fedora-i386-cross fedora-cris-cross # Rules for building linux-user powered images # @@ -131,6 +152,7 @@ DOCKER_PARTIAL_IMAGES += fedora-cris-cross # broken so we need a qemu-linux-user for this target docker-binfmt-image-debian-powerpc-user: DEB_ARCH = powerpc docker-binfmt-image-debian-powerpc-user: DEB_TYPE = jessie +docker-binfmt-image-debian-powerpc-user: DEB_URL = http://snapshot.debian.org/archive/debian/20180615T211437Z docker-binfmt-image-debian-powerpc-user: EXECUTABLE = ${BUILD_DIR}/ppc-linux-user/qemu-ppc docker-image-debian-powerpc-user-cross: docker-binfmt-image-debian-powerpc-user DOCKER_USER_IMAGES += debian-powerpc-user diff --git a/tests/docker/common.rc b/tests/docker/common.rc index 4011561587..512202b0a1 100755 --- a/tests/docker/common.rc +++ b/tests/docker/common.rc @@ -11,6 +11,10 @@ # or (at your option) any later version. See the COPYING file in # the top-level directory. +# This might be set by ENV of a docker container... it is always +# overriden by TARGET_LIST if the user sets it. +DEF_TARGET_LIST=${DEF_TARGET_LIST:-"x86_64-softmmu,aarch64-softmmu"} + requires() { for c in $@; do diff --git a/tests/docker/docker.py b/tests/docker/docker.py index 4bba29e104..29613afd48 100755 --- a/tests/docker/docker.py +++ b/tests/docker/docker.py @@ -111,7 +111,7 @@ def _get_so_libs(executable): libs = [] ldd_re = re.compile(r"(/.*/)(\S*)") try: - ldd_output = subprocess.check_output(["ldd", executable]) + ldd_output = subprocess.check_output(["ldd", executable]).decode('utf-8') for line in ldd_output.split("\n"): search = ldd_re.search(line) if search and len(search.groups()) == 2: @@ -258,10 +258,16 @@ class Docker(object): return self._do_kill_instances(True) def _output(self, cmd, **kwargs): - return subprocess.check_output(self._command + cmd, - stderr=subprocess.STDOUT, - encoding='utf-8', - **kwargs) + if sys.version_info[1] >= 6: + return subprocess.check_output(self._command + cmd, + stderr=subprocess.STDOUT, + encoding='utf-8', + **kwargs) + else: + return subprocess.check_output(self._command + cmd, + stderr=subprocess.STDOUT, + **kwargs).decode('utf-8') + def inspect_tag(self, tag): try: @@ -318,10 +324,18 @@ class Docker(object): return False return checksum == _text_checksum(_dockerfile_preprocess(dockerfile)) - def run(self, cmd, keep, quiet): + def run(self, cmd, keep, quiet, as_user=False): label = uuid.uuid1().hex if not keep: self._instances.append(label) + + if as_user: + uid = os.getuid() + cmd = [ "-u", str(uid) ] + cmd + # podman requires a bit more fiddling + if self._command[0] == "podman": + argv.insert(0, '--userns=keep-id') + ret = self._do_check(["run", "--label", "com.qemu.instance.uuid=" + label] + cmd, quiet=quiet) @@ -364,15 +378,8 @@ class RunCommand(SubCommand): help="Run container using the current user's uid") def run(self, args, argv): - if args.run_as_current_user: - uid = os.getuid() - argv = [ "-u", str(uid) ] + argv - docker = Docker() - if docker._command[0] == "podman": - argv = [ "--uidmap", "%d:0:1" % uid, - "--uidmap", "0:1:%d" % uid, - "--uidmap", "%d:%d:64536" % (uid + 1, uid + 1)] + argv - return Docker().run(argv, args.keep, quiet=args.quiet) + return Docker().run(argv, args.keep, quiet=args.quiet, + as_user=args.run_as_current_user) class BuildCommand(SubCommand): @@ -536,9 +543,9 @@ class ProbeCommand(SubCommand): try: docker = Docker() if docker._command[0] == "docker": - print("yes") + print("docker") elif docker._command[0] == "sudo": - print("sudo") + print("sudo docker") elif docker._command[0] == "podman": print("podman") except Exception: @@ -556,8 +563,6 @@ class CcCommand(SubCommand): help="The docker image in which to run cc") parser.add_argument("--cc", default="cc", help="The compiler executable to call") - parser.add_argument("--user", - help="The user-id to run under") parser.add_argument("--source-path", "-s", nargs="*", dest="paths", help="""Extra paths to (ro) mount into container for reading sources""") @@ -571,11 +576,10 @@ class CcCommand(SubCommand): if args.paths: for p in args.paths: cmd += ["-v", "%s:%s:ro,z" % (p, p)] - if args.user: - cmd += ["-u", args.user] cmd += [args.image, args.cc] cmd += argv - return Docker().command("run", cmd, args.quiet) + return Docker().run(cmd, False, quiet=args.quiet, + as_user=True) class CheckCommand(SubCommand): @@ -651,7 +655,8 @@ def main(): cmd.args(subp) subp.set_defaults(cmdobj=cmd) args, argv = parser.parse_known_args() - USE_ENGINE = args.engine + if args.engine: + USE_ENGINE = args.engine return args.cmdobj.run(args, argv) diff --git a/tests/docker/dockerfiles/debian-alpha-cross.docker b/tests/docker/dockerfiles/debian-alpha-cross.docker index 23444342f0..74bcabfdb1 100644 --- a/tests/docker/dockerfiles/debian-alpha-cross.docker +++ b/tests/docker/dockerfiles/debian-alpha-cross.docker @@ -1,13 +1,12 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ apt install -y --no-install-recommends \ gcc-alpha-linux-gnu \ - libc6.1-dev-alpha-cross || { echo "Failed to build - see debian-sid.docker notes"; exit 1; } + libc6.1-dev-alpha-cross diff --git a/tests/docker/dockerfiles/debian-amd64-cross.docker b/tests/docker/dockerfiles/debian-amd64-cross.docker new file mode 100644 index 0000000000..5d89041925 --- /dev/null +++ b/tests/docker/dockerfiles/debian-amd64-cross.docker @@ -0,0 +1,22 @@ +# +# Docker x86_64 cross target +# +# This docker target is used on non-x86_64 machines which need the +# x86_64 cross compilers installed. +# +FROM qemu:debian10 +MAINTAINER Alex Bennée <alex.bennee@linaro.org> + +# Add the foreign architecture we want and install dependencies +RUN dpkg --add-architecture amd64 +RUN apt update && \ + DEBIAN_FRONTEND=noninteractive eatmydata \ + apt install -y --no-install-recommends \ + crossbuild-essential-amd64 +RUN apt update && \ + DEBIAN_FRONTEND=noninteractive eatmydata \ + apt build-dep -yy -a amd64 --arch-only qemu + +# Specify the cross prefix for this image (see tests/docker/common.rc) +ENV QEMU_CONFIGURE_OPTS --cross-prefix=x86_64-linux-gnu- +ENV DEF_TARGET_LIST x86_64-softmmu,x86_64-linux-user,i386-softmmu,i386-linux-user diff --git a/tests/docker/dockerfiles/debian-arm64-cross.docker b/tests/docker/dockerfiles/debian-arm64-cross.docker index 7c2cc93daf..09ca0a1ba7 100644 --- a/tests/docker/dockerfiles/debian-arm64-cross.docker +++ b/tests/docker/dockerfiles/debian-arm64-cross.docker @@ -1,9 +1,9 @@ # # Docker arm64 cross-compiler target # -# This docker target builds on the debian Stretch base image. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian9 +FROM qemu:debian10 # Add the foreign architecture we want and install dependencies RUN dpkg --add-architecture arm64 @@ -13,10 +13,11 @@ RUN apt update && \ crossbuild-essential-arm64 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ - apt build-dep -yy -a arm64 qemu + apt build-dep -yy -a arm64 --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=aarch64-linux-gnu- +ENV DEF_TARGET_LIST aarch64-softmmu,aarch64-linux-user RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-armel-cross.docker b/tests/docker/dockerfiles/debian-armel-cross.docker index d866fe5d75..15378f8ea2 100644 --- a/tests/docker/dockerfiles/debian-armel-cross.docker +++ b/tests/docker/dockerfiles/debian-armel-cross.docker @@ -11,10 +11,11 @@ RUN dpkg --add-architecture armel && \ apt update && \ apt install -yy crossbuild-essential-armel && \ DEBIAN_FRONTEND=noninteractive eatmydata \ - apt build-dep -yy -a armel qemu + apt build-dep -yy -a armel --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=arm-linux-gnueabi- +ENV DEF_TARGET_LIST arm-softmmu,arm-linux-user,armeb-linux-user RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-armhf-cross.docker b/tests/docker/dockerfiles/debian-armhf-cross.docker index 2b8627673c..4a20af6fe1 100644 --- a/tests/docker/dockerfiles/debian-armhf-cross.docker +++ b/tests/docker/dockerfiles/debian-armhf-cross.docker @@ -13,10 +13,11 @@ RUN apt update && \ crossbuild-essential-armhf RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ - apt build-dep -yy -a armhf qemu + apt build-dep -yy -a armhf --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=arm-linux-gnueabihf- +ENV DEF_TARGET_LIST arm-softmmu,arm-linux-user,armeb-linux-user RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-buster-arm64-cross.docker b/tests/docker/dockerfiles/debian-buster-arm64-cross.docker deleted file mode 100644 index 52787edcc2..0000000000 --- a/tests/docker/dockerfiles/debian-buster-arm64-cross.docker +++ /dev/null @@ -1,16 +0,0 @@ -# -# Docker arm64 cross-compiler target -# -# This docker target builds on the Debian's Buster base image. There -# are no QEMU pre-requistes so this image can only be used to build -# test cases. -# -FROM qemu:debian10 - -# Add the foreign architecture we want and install dependencies -RUN dpkg --add-architecture arm64 -RUN apt update && \ - DEBIAN_FRONTEND=noninteractive apt install -yy eatmydata && \ - DEBIAN_FRONTEND=noninteractive eatmydata \ - apt-get install -y --no-install-recommends \ - crossbuild-essential-arm64 diff --git a/tests/docker/dockerfiles/debian-hppa-cross.docker b/tests/docker/dockerfiles/debian-hppa-cross.docker index ee6d9a24ce..5c68b2d330 100644 --- a/tests/docker/dockerfiles/debian-hppa-cross.docker +++ b/tests/docker/dockerfiles/debian-hppa-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-m68k-cross.docker b/tests/docker/dockerfiles/debian-m68k-cross.docker index 4311c9cf86..25edc80e9a 100644 --- a/tests/docker/dockerfiles/debian-m68k-cross.docker +++ b/tests/docker/dockerfiles/debian-m68k-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-mips-cross.docker b/tests/docker/dockerfiles/debian-mips-cross.docker index 3c4d6f9ec1..08a8e1c29c 100644 --- a/tests/docker/dockerfiles/debian-mips-cross.docker +++ b/tests/docker/dockerfiles/debian-mips-cross.docker @@ -1,9 +1,9 @@ # # Docker mips cross-compiler target # -# This docker target builds on the debian Stretch base image. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian9 +FROM qemu:debian10 MAINTAINER Philippe Mathieu-Daudé <f4bug@amsat.org> @@ -16,10 +16,11 @@ RUN apt update && \ RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ - apt build-dep -yy -a mips qemu + apt build-dep -yy -a mips --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=mips-linux-gnu- +ENV DEF_TARGET_LIST mips-softmmu,mipsel-linux-user # Install extra libraries to increase code coverage RUN apt update && \ diff --git a/tests/docker/dockerfiles/debian-mips64-cross.docker b/tests/docker/dockerfiles/debian-mips64-cross.docker index bf0073a466..1a79505d69 100644 --- a/tests/docker/dockerfiles/debian-mips64-cross.docker +++ b/tests/docker/dockerfiles/debian-mips64-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-mips64el-cross.docker b/tests/docker/dockerfiles/debian-mips64el-cross.docker index 34b0b82895..2fca112405 100644 --- a/tests/docker/dockerfiles/debian-mips64el-cross.docker +++ b/tests/docker/dockerfiles/debian-mips64el-cross.docker @@ -17,10 +17,11 @@ RUN dpkg --add-architecture mips64el && \ RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ - apt build-dep -yy -a mips64el qemu + apt build-dep -yy -a mips64el --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=mips64el-linux-gnuabi64- +ENV DEF_TARGET_LIST mips64el-softmmu,mips64el-linux-user # Install extra libraries to increase code coverage RUN apt update && \ diff --git a/tests/docker/dockerfiles/debian-mipsel-cross.docker b/tests/docker/dockerfiles/debian-mipsel-cross.docker index 88accad269..4abf7832ac 100644 --- a/tests/docker/dockerfiles/debian-mipsel-cross.docker +++ b/tests/docker/dockerfiles/debian-mipsel-cross.docker @@ -16,7 +16,7 @@ RUN apt update && \ RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ - apt build-dep -yy -a mipsel qemu + apt build-dep -yy -a mipsel --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=mipsel-linux-gnu- diff --git a/tests/docker/dockerfiles/debian-powerpc-cross.docker b/tests/docker/dockerfiles/debian-powerpc-cross.docker index 5d08fad7cd..89dd4fbf87 100644 --- a/tests/docker/dockerfiles/debian-powerpc-cross.docker +++ b/tests/docker/dockerfiles/debian-powerpc-cross.docker @@ -1,14 +1,12 @@ # # Docker powerpc cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. The original -# Jessie based no longer builds. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ apt install -y --no-install-recommends \ gcc-powerpc-linux-gnu \ - libc6-dev-powerpc-cross || { echo "Failed to build - see debian-sid.docker notes"; exit 1; } + libc6-dev-powerpc-cross diff --git a/tests/docker/dockerfiles/debian-powerpc-user-cross.docker b/tests/docker/dockerfiles/debian-powerpc-user-cross.docker index 6938a845ee..83749b0abb 100644 --- a/tests/docker/dockerfiles/debian-powerpc-user-cross.docker +++ b/tests/docker/dockerfiles/debian-powerpc-user-cross.docker @@ -8,8 +8,14 @@ # debootstrapped qemu:debian-powerpc-user but doesn't need any extra # magic once it is setup. # +# It can be used to build old versions of QEMU, current versions need +# newer dependencies than Jessie provides. +# FROM qemu:debian-powerpc-user RUN echo man-db man-db/auto-update boolean false | debconf-set-selections RUN apt-get update && \ - DEBIAN_FRONTEND=noninteractive apt-get build-dep -yy qemu + DEBIAN_FRONTEND=noninteractive apt-get build-dep -yy qemu + +ENV QEMU_CONFIGURE_OPTS --disable-werror +ENV DEF_TARGET_LIST powerpc-softmmu,arm-linux-user,aarch64-linux-user diff --git a/tests/docker/dockerfiles/debian-ppc64-cross.docker b/tests/docker/dockerfiles/debian-ppc64-cross.docker index e5757fe46e..4bf88ab02d 100644 --- a/tests/docker/dockerfiles/debian-ppc64-cross.docker +++ b/tests/docker/dockerfiles/debian-ppc64-cross.docker @@ -1,12 +1,11 @@ # # Docker ppc64 cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. -FROM qemu:debian-sid +# This docker target builds on the debian Buster base image. +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ apt install -y --no-install-recommends \ gcc-powerpc64-linux-gnu \ - libc6-dev-ppc64-cross || { echo "Failed to build - see debian-sid.docker notes"; exit 1; } + libc6-dev-ppc64-cross diff --git a/tests/docker/dockerfiles/debian-ppc64el-cross.docker b/tests/docker/dockerfiles/debian-ppc64el-cross.docker index fc056d7bc3..9973df9ff7 100644 --- a/tests/docker/dockerfiles/debian-ppc64el-cross.docker +++ b/tests/docker/dockerfiles/debian-ppc64el-cross.docker @@ -12,10 +12,11 @@ RUN dpkg --add-architecture ppc64el && \ RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ - apt build-dep -yy -a ppc64el qemu + apt build-dep -yy -a ppc64el --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=powerpc64le-linux-gnu- +ENV DEF_TARGET_LIST ppc64-softmmu,ppc64-linux-user,ppc64abi32-linux-user # Install extra libraries to increase code coverage RUN apt update && \ diff --git a/tests/docker/dockerfiles/debian-riscv64-cross.docker b/tests/docker/dockerfiles/debian-riscv64-cross.docker index 221697f9d1..5e2d6ddb60 100644 --- a/tests/docker/dockerfiles/debian-riscv64-cross.docker +++ b/tests/docker/dockerfiles/debian-riscv64-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-s390x-cross.docker b/tests/docker/dockerfiles/debian-s390x-cross.docker index 6732f9ec78..eb73c98855 100644 --- a/tests/docker/dockerfiles/debian-s390x-cross.docker +++ b/tests/docker/dockerfiles/debian-s390x-cross.docker @@ -17,10 +17,11 @@ RUN apt update && \ RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ - apt build-dep -yy -a s390x qemu + apt build-dep -yy -a s390x --arch-only qemu # Specify the cross prefix for this image (see tests/docker/common.rc) ENV QEMU_CONFIGURE_OPTS --cross-prefix=s390x-linux-gnu- +ENV DEF_TARGET_LIST s390x-softmmu,s390x-linux-user # Install extra libraries to increase code coverage RUN apt update && \ diff --git a/tests/docker/dockerfiles/debian-sh4-cross.docker b/tests/docker/dockerfiles/debian-sh4-cross.docker index 29983b2d75..9d7663764e 100644 --- a/tests/docker/dockerfiles/debian-sh4-cross.docker +++ b/tests/docker/dockerfiles/debian-sh4-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/debian-sid.docker b/tests/docker/dockerfiles/debian-sid.docker index 513459ca7f..2a1bcc33b2 100644 --- a/tests/docker/dockerfiles/debian-sid.docker +++ b/tests/docker/dockerfiles/debian-sid.docker @@ -1,25 +1,19 @@ # # Debian Sid Base # -# A number of our guests exist as ports only. We can either use the -# ports repo or get everything from Sid. However Sid is a rolling -# distro which may be broken at any particular time. If you are -# unlucky and try and build your images while gcc is in the process of -# being uploaded this can fail. Your only recourse is to try again in -# a few hours when the repos have re-synced. Once built however you -# won't be affected by repo changes unless the docker recipies are -# updated and trigger a re-build. +# Currently we can build all our guests with cross-compilers in the +# latest Debian release (Buster). However new compilers will first +# arrive in Sid. However Sid is a rolling distro which may be broken +# at any particular time. To try and mitigate this we use Debian's +# snapshot archive which provides a "stable" view of what state Sid +# was in. # # This must be earlier than the snapshot date we are aiming for -FROM debian:sid-20181011-slim +FROM debian:sid-20190812-slim -# Use a snapshot known to work (see http://snapshot.debian.org/#Usage) -ENV DEBIAN_SNAPSHOT_DATE "20181030" -RUN sed -i "s%^deb \(https\?://\)deb.debian.org/debian/\? \(.*\)%deb [check-valid-until=no] \1snapshot.debian.org/archive/debian/${DEBIAN_SNAPSHOT_DATE} \2%" /etc/apt/sources.list - -# Use a snapshot known to work (see http://snapshot.debian.org/#Usage) -ENV DEBIAN_SNAPSHOT_DATE "20181030" + # Use a snapshot known to work (see http://snapshot.debian.org/#Usage) +ENV DEBIAN_SNAPSHOT_DATE "20190820" RUN sed -i "s%^deb \(https\?://\)deb.debian.org/debian/\? \(.*\)%deb [check-valid-until=no] \1snapshot.debian.org/archive/debian/${DEBIAN_SNAPSHOT_DATE} \2%" /etc/apt/sources.list # Duplicate deb line as deb-src diff --git a/tests/docker/dockerfiles/debian-sparc64-cross.docker b/tests/docker/dockerfiles/debian-sparc64-cross.docker index 7a2c2ab19c..31fd34f120 100644 --- a/tests/docker/dockerfiles/debian-sparc64-cross.docker +++ b/tests/docker/dockerfiles/debian-sparc64-cross.docker @@ -1,10 +1,9 @@ # # Docker cross-compiler target # -# This docker target builds on the debian sid base image which -# contains cross compilers for Debian "ports" targets. +# This docker target builds on the debian Buster base image. # -FROM qemu:debian-sid +FROM qemu:debian10 RUN apt update && \ DEBIAN_FRONTEND=noninteractive eatmydata \ diff --git a/tests/docker/dockerfiles/ubuntu1804.docker b/tests/docker/dockerfiles/ubuntu1804.docker index 44bbf0f77a..883f9bcf31 100644 --- a/tests/docker/dockerfiles/ubuntu1804.docker +++ b/tests/docker/dockerfiles/ubuntu1804.docker @@ -56,3 +56,6 @@ RUN apt-get update && \ DEBIAN_FRONTEND=noninteractive apt-get -y install $PACKAGES RUN dpkg -l $PACKAGES | sort > /packages.txt ENV FEATURES clang pyyaml sdl2 + +# https://bugs.launchpad.net/qemu/+bug/1838763 +ENV QEMU_CONFIGURE_OPTS --disable-libssh diff --git a/tests/docker/run b/tests/docker/run index 1014871fec..8edc7026ee 100755 --- a/tests/docker/run +++ b/tests/docker/run @@ -62,7 +62,7 @@ echo "* Prepared to run command:" echo " $CMD" echo "* Hit Ctrl-D to continue, or type 'exit 1' to abort" echo -$SHELL --noprofile --norc +env bash --noprofile --norc if "$CMD"; then exit 0 @@ -72,7 +72,7 @@ elif test -n "$DEBUG"; then echo "* Hit Ctrl-D to exit" echo # Force error after shell exits - $SHELL --noprofile --norc && exit 1 + env bash --noprofile --norc && exit 1 else exit 1 fi diff --git a/tests/docker/test-build b/tests/docker/test-build index 22766cfacc..2b2a7832f1 100755 --- a/tests/docker/test-build +++ b/tests/docker/test-build @@ -15,7 +15,6 @@ cd "$BUILD_DIR" -DEF_TARGET_LIST="x86_64-softmmu,aarch64-softmmu" TARGET_LIST=${TARGET_LIST:-$DEF_TARGET_LIST} \ build_qemu install_qemu diff --git a/tests/docker/test-mingw b/tests/docker/test-mingw index fdb1c2c879..c30eb654eb 100755 --- a/tests/docker/test-mingw +++ b/tests/docker/test-mingw @@ -16,7 +16,6 @@ requires mingw dtc cd "$BUILD_DIR" -DEF_TARGET_LIST="x86_64-softmmu,aarch64-softmmu" for prefix in x86_64-w64-mingw32- i686-w64-mingw32-; do TARGET_LIST=${TARGET_LIST:-$DEF_TARGET_LIST} \ diff --git a/tests/docker/test-quick b/tests/docker/test-quick index eee59c55fb..feee44b247 100755 --- a/tests/docker/test-quick +++ b/tests/docker/test-quick @@ -15,7 +15,6 @@ cd "$BUILD_DIR" -DEF_TARGET_LIST="x86_64-softmmu,aarch64-softmmu" TARGET_LIST=${TARGET_LIST:-$DEF_TARGET_LIST} \ build_qemu check_qemu diff --git a/tests/libqtest.c b/tests/libqtest.c index 0a6b91737e..4a7556462d 100644 --- a/tests/libqtest.c +++ b/tests/libqtest.c @@ -41,6 +41,7 @@ struct QTestState int qmp_fd; pid_t qemu_pid; /* our child QEMU process */ int wstatus; + int expected_status; bool big_endian; bool irq_level[MAX_IRQ]; GString *rx; @@ -111,6 +112,11 @@ bool qtest_probe_child(QTestState *s) return false; } +void qtest_set_expected_status(QTestState *s, int status) +{ + s->expected_status = status; +} + static void kill_qemu(QTestState *s) { pid_t pid = s->qemu_pid; @@ -124,24 +130,23 @@ static void kill_qemu(QTestState *s) } /* - * We expect qemu to exit with status 0; anything else is + * Check whether qemu exited with expected exit status; anything else is * fishy and should be logged with as much detail as possible. */ wstatus = s->wstatus; - if (wstatus) { - if (WIFEXITED(wstatus)) { - fprintf(stderr, "%s:%d: kill_qemu() tried to terminate QEMU " - "process but encountered exit status %d\n", - __FILE__, __LINE__, WEXITSTATUS(wstatus)); - } else if (WIFSIGNALED(wstatus)) { - int sig = WTERMSIG(wstatus); - const char *signame = strsignal(sig) ?: "unknown ???"; - const char *dump = WCOREDUMP(wstatus) ? " (core dumped)" : ""; - - fprintf(stderr, "%s:%d: kill_qemu() detected QEMU death " - "from signal %d (%s)%s\n", - __FILE__, __LINE__, sig, signame, dump); - } + if (WIFEXITED(wstatus) && WEXITSTATUS(wstatus) != s->expected_status) { + fprintf(stderr, "%s:%d: kill_qemu() tried to terminate QEMU " + "process but encountered exit status %d (expected %d)\n", + __FILE__, __LINE__, WEXITSTATUS(wstatus), s->expected_status); + abort(); + } else if (WIFSIGNALED(wstatus)) { + int sig = WTERMSIG(wstatus); + const char *signame = strsignal(sig) ?: "unknown ???"; + const char *dump = WCOREDUMP(wstatus) ? " (core dumped)" : ""; + + fprintf(stderr, "%s:%d: kill_qemu() detected QEMU death " + "from signal %d (%s)%s\n", + __FILE__, __LINE__, sig, signame, dump); abort(); } } @@ -246,6 +251,7 @@ QTestState *qtest_init_without_qmp_handshake(const char *extra_args) g_test_message("starting QEMU: %s", command); s->wstatus = 0; + s->expected_status = 0; s->qemu_pid = fork(); if (s->qemu_pid == 0) { setenv("QEMU_AUDIO_DRV", "none", true); diff --git a/tests/libqtest.h b/tests/libqtest.h index c8cffe5d68..a177e502d9 100644 --- a/tests/libqtest.h +++ b/tests/libqtest.h @@ -708,4 +708,13 @@ void qmp_assert_error_class(QDict *rsp, const char *class); */ bool qtest_probe_child(QTestState *s); +/** + * qtest_set_expected_status: + * @s: QTestState instance to operate on. + * @status: an expected exit status. + * + * Set expected exit status of the child. + */ +void qtest_set_expected_status(QTestState *s, int status); + #endif diff --git a/tests/migration-test.c b/tests/migration-test.c index a9f81cc185..258aa064d4 100644 --- a/tests/migration-test.c +++ b/tests/migration-test.c @@ -512,7 +512,8 @@ static void migrate_postcopy_start(QTestState *from, QTestState *to) static int test_migrate_start(QTestState **from, QTestState **to, const char *uri, bool hide_stderr, - bool use_shmem) + bool use_shmem, const char *opts_src, + const char *opts_dst) { gchar *cmd_src, *cmd_dst; char *bootpath = NULL; @@ -521,6 +522,9 @@ static int test_migrate_start(QTestState **from, QTestState **to, const char *arch = qtest_get_arch(); const char *accel = "kvm:tcg"; + opts_src = opts_src ? opts_src : ""; + opts_dst = opts_dst ? opts_dst : ""; + if (use_shmem) { if (!g_file_test("/dev/shm", G_FILE_TEST_IS_DIR)) { g_test_skip("/dev/shm is not supported"); @@ -539,16 +543,16 @@ static int test_migrate_start(QTestState **from, QTestState **to, cmd_src = g_strdup_printf("-machine accel=%s -m 150M" " -name source,debug-threads=on" " -serial file:%s/src_serial" - " -drive file=%s,format=raw %s", + " -drive file=%s,format=raw %s %s", accel, tmpfs, bootpath, - extra_opts ? extra_opts : ""); + extra_opts ? extra_opts : "", opts_src); cmd_dst = g_strdup_printf("-machine accel=%s -m 150M" " -name target,debug-threads=on" " -serial file:%s/dest_serial" " -drive file=%s,format=raw" - " -incoming %s %s", + " -incoming %s %s %s", accel, tmpfs, bootpath, uri, - extra_opts ? extra_opts : ""); + extra_opts ? extra_opts : "", opts_dst); start_address = X86_TEST_MEM_START; end_address = X86_TEST_MEM_END; } else if (g_str_equal(arch, "s390x")) { @@ -556,15 +560,15 @@ static int test_migrate_start(QTestState **from, QTestState **to, extra_opts = use_shmem ? get_shmem_opts("128M", shmem_path) : NULL; cmd_src = g_strdup_printf("-machine accel=%s -m 128M" " -name source,debug-threads=on" - " -serial file:%s/src_serial -bios %s %s", + " -serial file:%s/src_serial -bios %s %s %s", accel, tmpfs, bootpath, - extra_opts ? extra_opts : ""); + extra_opts ? extra_opts : "", opts_src); cmd_dst = g_strdup_printf("-machine accel=%s -m 128M" " -name target,debug-threads=on" " -serial file:%s/dest_serial -bios %s" - " -incoming %s %s", + " -incoming %s %s %s", accel, tmpfs, bootpath, uri, - extra_opts ? extra_opts : ""); + extra_opts ? extra_opts : "", opts_dst); start_address = S390_TEST_MEM_START; end_address = S390_TEST_MEM_END; } else if (strcmp(arch, "ppc64") == 0) { @@ -575,14 +579,15 @@ static int test_migrate_start(QTestState **from, QTestState **to, " -prom-env 'use-nvramrc?=true' -prom-env " "'nvramrc=hex .\" _\" begin %x %x " "do i c@ 1 + i c! 1000 +loop .\" B\" 0 " - "until' %s", accel, tmpfs, end_address, - start_address, extra_opts ? extra_opts : ""); + "until' %s %s", accel, tmpfs, end_address, + start_address, extra_opts ? extra_opts : "", + opts_src); cmd_dst = g_strdup_printf("-machine accel=%s -m 256M" " -name target,debug-threads=on" " -serial file:%s/dest_serial" - " -incoming %s %s", + " -incoming %s %s %s", accel, tmpfs, uri, - extra_opts ? extra_opts : ""); + extra_opts ? extra_opts : "", opts_dst); start_address = PPC_TEST_MEM_START; end_address = PPC_TEST_MEM_END; @@ -592,16 +597,16 @@ static int test_migrate_start(QTestState **from, QTestState **to, cmd_src = g_strdup_printf("-machine virt,accel=%s,gic-version=max " "-name vmsource,debug-threads=on -cpu max " "-m 150M -serial file:%s/src_serial " - "-kernel %s %s", + "-kernel %s %s %s", accel, tmpfs, bootpath, - extra_opts ? extra_opts : ""); + extra_opts ? extra_opts : "", opts_src); cmd_dst = g_strdup_printf("-machine virt,accel=%s,gic-version=max " "-name vmdest,debug-threads=on -cpu max " "-m 150M -serial file:%s/dest_serial " "-kernel %s " - "-incoming %s %s", + "-incoming %s %s %s", accel, tmpfs, bootpath, uri, - extra_opts ? extra_opts : ""); + extra_opts ? extra_opts : "", opts_dst); start_address = ARM_TEST_MEM_START; end_address = ARM_TEST_MEM_END; @@ -731,7 +736,7 @@ static int migrate_postcopy_prepare(QTestState **from_ptr, char *uri = g_strdup_printf("unix:%s/migsocket", tmpfs); QTestState *from, *to; - if (test_migrate_start(&from, &to, uri, hide_error, false)) { + if (test_migrate_start(&from, &to, uri, hide_error, false, NULL, NULL)) { return -1; } @@ -841,20 +846,16 @@ static void test_postcopy_recovery(void) migrate_postcopy_complete(from, to); } -static void test_baddest(void) +static void wait_for_migration_fail(QTestState *from, bool allow_active) { - QTestState *from, *to; QDict *rsp_return; char *status; bool failed; - if (test_migrate_start(&from, &to, "tcp:0:0", true, false)) { - return; - } - migrate(from, "tcp:0:0", "{}"); do { status = migrate_query_status(from); - g_assert(!strcmp(status, "setup") || !(strcmp(status, "failed"))); + g_assert(!strcmp(status, "setup") || !strcmp(status, "failed") || + (allow_active && !strcmp(status, "active"))); failed = !strcmp(status, "failed"); g_free(status); } while (!failed); @@ -864,7 +865,17 @@ static void test_baddest(void) g_assert(qdict_haskey(rsp_return, "running")); g_assert(qdict_get_bool(rsp_return, "running")); qobject_unref(rsp_return); +} + +static void test_baddest(void) +{ + QTestState *from, *to; + if (test_migrate_start(&from, &to, "tcp:0:0", true, false, NULL, NULL)) { + return; + } + migrate(from, "tcp:0:0", "{}"); + wait_for_migration_fail(from, false); test_migrate_end(from, to, false); } @@ -873,7 +884,7 @@ static void test_precopy_unix(void) char *uri = g_strdup_printf("unix:%s/migsocket", tmpfs); QTestState *from, *to; - if (test_migrate_start(&from, &to, uri, false, false)) { + if (test_migrate_start(&from, &to, uri, false, false, NULL, NULL)) { return; } @@ -916,7 +927,7 @@ static void test_ignore_shared(void) char *uri = g_strdup_printf("unix:%s/migsocket", tmpfs); QTestState *from, *to; - if (test_migrate_start(&from, &to, uri, false, true)) { + if (test_migrate_start(&from, &to, uri, false, true, NULL, NULL)) { return; } @@ -951,7 +962,7 @@ static void test_xbzrle(const char *uri) { QTestState *from, *to; - if (test_migrate_start(&from, &to, uri, false, false)) { + if (test_migrate_start(&from, &to, uri, false, false, NULL, NULL)) { return; } @@ -1003,7 +1014,8 @@ static void test_precopy_tcp(void) char *uri; QTestState *from, *to; - if (test_migrate_start(&from, &to, "tcp:127.0.0.1:0", false, false)) { + if (test_migrate_start(&from, &to, "tcp:127.0.0.1:0", false, false, + NULL, NULL)) { return; } @@ -1049,7 +1061,7 @@ static void test_migrate_fd_proto(void) QDict *rsp; const char *error_desc; - if (test_migrate_start(&from, &to, "defer", false, false)) { + if (test_migrate_start(&from, &to, "defer", false, false, NULL, NULL)) { return; } @@ -1125,6 +1137,68 @@ static void test_migrate_fd_proto(void) test_migrate_end(from, to, true); } +static void do_test_validate_uuid(const char *uuid_arg_src, + const char *uuid_arg_dst, + bool should_fail, bool hide_stderr) +{ + char *uri = g_strdup_printf("unix:%s/migsocket", tmpfs); + QTestState *from, *to; + + if (test_migrate_start(&from, &to, uri, hide_stderr, false, + uuid_arg_src, uuid_arg_dst)) { + return; + } + + /* + * UUID validation is at the begin of migration. So, the main process of + * migration is not interesting for us here. Thus, set huge downtime for + * very fast migration. + */ + migrate_set_parameter_int(from, "downtime-limit", 1000000); + migrate_set_capability(from, "validate-uuid", true); + + /* Wait for the first serial output from the source */ + wait_for_serial("src_serial"); + + migrate(from, uri, "{}"); + + if (should_fail) { + qtest_set_expected_status(to, 1); + wait_for_migration_fail(from, true); + } else { + wait_for_migration_complete(from); + } + + test_migrate_end(from, to, false); + g_free(uri); +} + +static void test_validate_uuid(void) +{ + do_test_validate_uuid("-uuid 11111111-1111-1111-1111-111111111111", + "-uuid 11111111-1111-1111-1111-111111111111", + false, false); +} + +static void test_validate_uuid_error(void) +{ + do_test_validate_uuid("-uuid 11111111-1111-1111-1111-111111111111", + "-uuid 22222222-2222-2222-2222-222222222222", + true, true); +} + +static void test_validate_uuid_src_not_set(void) +{ + do_test_validate_uuid(NULL, "-uuid 11111111-1111-1111-1111-111111111111", + false, true); +} + +static void test_validate_uuid_dst_not_set(void) +{ + do_test_validate_uuid("-uuid 11111111-1111-1111-1111-111111111111", NULL, + false, true); +} + int main(int argc, char **argv) { char template[] = "/tmp/migration-test-XXXXXX"; @@ -1180,6 +1254,12 @@ int main(int argc, char **argv) /* qtest_add_func("/migration/ignore_shared", test_ignore_shared); */ qtest_add_func("/migration/xbzrle/unix", test_xbzrle_unix); qtest_add_func("/migration/fd_proto", test_migrate_fd_proto); + qtest_add_func("/migration/validate_uuid", test_validate_uuid); + qtest_add_func("/migration/validate_uuid_error", test_validate_uuid_error); + qtest_add_func("/migration/validate_uuid_src_not_set", + test_validate_uuid_src_not_set); + qtest_add_func("/migration/validate_uuid_dst_not_set", + test_validate_uuid_dst_not_set); ret = g_test_run(); diff --git a/tests/qemu-iotests/026.out.nocache b/tests/qemu-iotests/026.out.nocache index 1ca6cda15c..6dda95dfb4 100644 --- a/tests/qemu-iotests/026.out.nocache +++ b/tests/qemu-iotests/026.out.nocache @@ -14,8 +14,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l1_update; errno: 5; imm: off; once: off; write -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error 1 leaked clusters were found on the image. @@ -23,8 +23,8 @@ This means waste of disk space, but no harm to data. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l1_update; errno: 5; imm: off; once: off; write -b -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error 1 leaked clusters were found on the image. @@ -42,8 +42,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l1_update; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 1 leaked clusters were found on the image. @@ -51,8 +51,8 @@ This means waste of disk space, but no harm to data. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l1_update; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 1 leaked clusters were found on the image. @@ -136,8 +136,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l2_update; errno: 5; imm: off; once: off; write -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error wrote 131072/131072 bytes at offset 0 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) @@ -146,8 +146,8 @@ This means waste of disk space, but no harm to data. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l2_update; errno: 5; imm: off; once: off; write -b -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error wrote 131072/131072 bytes at offset 0 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) @@ -168,8 +168,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l2_update; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device wrote 131072/131072 bytes at offset 0 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) @@ -178,8 +178,8 @@ This means waste of disk space, but no harm to data. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l2_update; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device wrote 131072/131072 bytes at offset 0 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) @@ -198,15 +198,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l2_alloc_write; errno: 5; imm: off; once: off; write -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l2_alloc_write; errno: 5; imm: off; once: off; write -b -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error 1 leaked clusters were found on the image. @@ -224,15 +224,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l2_alloc_write; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l2_alloc_write; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 1 leaked clusters were found on the image. @@ -250,15 +250,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: write_aio; errno: 5; imm: off; once: off; write -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: write_aio; errno: 5; imm: off; once: off; write -b -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -274,15 +274,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: write_aio; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: write_aio; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -298,15 +298,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_load; errno: 5; imm: off; once: off; write -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_load; errno: 5; imm: off; once: off; write -b -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -322,15 +322,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_load; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_load; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -346,15 +346,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_update_part; errno: 5; imm: off; once: off; write -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_update_part; errno: 5; imm: off; once: off; write -b -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -370,15 +370,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_update_part; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_update_part; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -394,15 +394,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc; errno: 5; imm: off; once: off; write -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc; errno: 5; imm: off; once: off; write -b -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -418,15 +418,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -485,8 +485,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_hookup; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 55 leaked clusters were found on the image. @@ -494,8 +494,8 @@ This means waste of disk space, but no harm to data. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_hookup; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 251 leaked clusters were found on the image. @@ -513,15 +513,15 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_write; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_write; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -537,8 +537,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_write_blocks; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 10 leaked clusters were found on the image. @@ -546,8 +546,8 @@ This means waste of disk space, but no harm to data. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_write_blocks; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 23 leaked clusters were found on the image. @@ -565,8 +565,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_write_table; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 10 leaked clusters were found on the image. @@ -574,8 +574,8 @@ This means waste of disk space, but no harm to data. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_write_table; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 23 leaked clusters were found on the image. @@ -593,8 +593,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_switch_table; errno: 28; imm: off; once: off; write -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 10 leaked clusters were found on the image. @@ -602,8 +602,8 @@ This means waste of disk space, but no harm to data. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: refblock_alloc_switch_table; errno: 28; imm: off; once: off; write -b -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 23 leaked clusters were found on the image. @@ -639,8 +639,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l1_grow_write_table; errno: 5; imm: off; once: off -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -651,8 +651,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l1_grow_write_table; errno: 28; imm: off; once: off -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 @@ -663,8 +663,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l1_grow_activate_table; errno: 5; imm: off; once: off -Failed to flush the L2 table cache: Input/output error -Failed to flush the refcount block cache: Input/output error +qemu-io: Failed to flush the L2 table cache: Input/output error +qemu-io: Failed to flush the refcount block cache: Input/output error write failed: Input/output error 96 leaked clusters were found on the image. @@ -677,8 +677,8 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1073741824 Event: l1_grow_activate_table; errno: 28; imm: off; once: off -Failed to flush the L2 table cache: No space left on device -Failed to flush the refcount block cache: No space left on device +qemu-io: Failed to flush the L2 table cache: No space left on device +qemu-io: Failed to flush the refcount block cache: No space left on device write failed: No space left on device 96 leaked clusters were found on the image. diff --git a/tests/qemu-iotests/028 b/tests/qemu-iotests/028 index 01f495912f..71301ec6e5 100755 --- a/tests/qemu-iotests/028 +++ b/tests/qemu-iotests/028 @@ -110,7 +110,11 @@ echo qemu_comm_method="monitor" _launch_qemu -drive file="${TEST_IMG}",cache=${CACHEMODE},id=disk h=$QEMU_HANDLE -QEMU_COMM_TIMEOUT=1 +if [ "${VALGRIND_QEMU}" == "y" ]; then + QEMU_COMM_TIMEOUT=7 +else + QEMU_COMM_TIMEOUT=1 +fi # Silence output since it contains the disk image path and QEMU's readline # character echoing makes it very hard to filter the output. Plus, there diff --git a/tests/qemu-iotests/030 b/tests/qemu-iotests/030 index 1b69f318c6..f3766f2a81 100755 --- a/tests/qemu-iotests/030 +++ b/tests/qemu-iotests/030 @@ -957,4 +957,5 @@ class TestSetSpeed(iotests.QMPTestCase): self.cancel_and_wait(resume=True) if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2', 'qed']) + iotests.main(supported_fmts=['qcow2', 'qed'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/039 b/tests/qemu-iotests/039 index 7c730d94a7..325da63a4c 100755 --- a/tests/qemu-iotests/039 +++ b/tests/qemu-iotests/039 @@ -65,6 +65,7 @@ echo "== Creating a dirty image file ==" IMGOPTS="compat=1.1,lazy_refcounts=on" _make_test_img $size +_NO_VALGRIND \ $QEMU_IO -c "write -P 0x5a 0 512" \ -c "sigraise $(kill -l KILL)" "$TEST_IMG" 2>&1 \ | _filter_qemu_io @@ -100,6 +101,7 @@ echo "== Opening a dirty image read/write should repair it ==" IMGOPTS="compat=1.1,lazy_refcounts=on" _make_test_img $size +_NO_VALGRIND \ $QEMU_IO -c "write -P 0x5a 0 512" \ -c "sigraise $(kill -l KILL)" "$TEST_IMG" 2>&1 \ | _filter_qemu_io @@ -118,6 +120,7 @@ echo "== Creating an image file with lazy_refcounts=off ==" IMGOPTS="compat=1.1,lazy_refcounts=off" _make_test_img $size +_NO_VALGRIND \ $QEMU_IO -c "write -P 0x5a 0 512" \ -c "sigraise $(kill -l KILL)" "$TEST_IMG" 2>&1 \ | _filter_qemu_io @@ -151,6 +154,7 @@ echo "== Changing lazy_refcounts setting at runtime ==" IMGOPTS="compat=1.1,lazy_refcounts=off" _make_test_img $size +_NO_VALGRIND \ $QEMU_IO -c "reopen -o lazy-refcounts=on" \ -c "write -P 0x5a 0 512" \ -c "sigraise $(kill -l KILL)" "$TEST_IMG" 2>&1 \ @@ -163,6 +167,7 @@ _check_test_img IMGOPTS="compat=1.1,lazy_refcounts=on" _make_test_img $size +_NO_VALGRIND \ $QEMU_IO -c "reopen -o lazy-refcounts=off" \ -c "write -P 0x5a 0 512" \ -c "sigraise $(kill -l KILL)" "$TEST_IMG" 2>&1 \ diff --git a/tests/qemu-iotests/039.out b/tests/qemu-iotests/039.out index 724d7b2508..2e356d51b6 100644 --- a/tests/qemu-iotests/039.out +++ b/tests/qemu-iotests/039.out @@ -11,11 +11,7 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 wrote 512/512 bytes at offset 0 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -./common.rc: Killed ( if [ "${VALGRIND_QEMU}" == "y" ]; then - exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -else - exec "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -fi ) +./common.rc: Killed ( VALGRIND_QEMU="${VALGRIND_QEMU_IO}" _qemu_proc_exec "${VALGRIND_LOGFILE}" "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" ) incompatible_features 0x1 ERROR cluster 5 refcount=0 reference=1 ERROR OFLAG_COPIED data cluster: l2_entry=8000000000050000 refcount=0 @@ -50,11 +46,7 @@ read 512/512 bytes at offset 0 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 wrote 512/512 bytes at offset 0 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -./common.rc: Killed ( if [ "${VALGRIND_QEMU}" == "y" ]; then - exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -else - exec "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -fi ) +./common.rc: Killed ( VALGRIND_QEMU="${VALGRIND_QEMU_IO}" _qemu_proc_exec "${VALGRIND_LOGFILE}" "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" ) incompatible_features 0x1 ERROR cluster 5 refcount=0 reference=1 Rebuilding refcount structure @@ -68,11 +60,7 @@ incompatible_features 0x0 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 wrote 512/512 bytes at offset 0 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -./common.rc: Killed ( if [ "${VALGRIND_QEMU}" == "y" ]; then - exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -else - exec "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -fi ) +./common.rc: Killed ( VALGRIND_QEMU="${VALGRIND_QEMU_IO}" _qemu_proc_exec "${VALGRIND_LOGFILE}" "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" ) incompatible_features 0x0 No errors were found on the image. @@ -91,11 +79,7 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 wrote 512/512 bytes at offset 0 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -./common.rc: Killed ( if [ "${VALGRIND_QEMU}" == "y" ]; then - exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -else - exec "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -fi ) +./common.rc: Killed ( VALGRIND_QEMU="${VALGRIND_QEMU_IO}" _qemu_proc_exec "${VALGRIND_LOGFILE}" "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" ) incompatible_features 0x1 ERROR cluster 5 refcount=0 reference=1 ERROR OFLAG_COPIED data cluster: l2_entry=8000000000050000 refcount=0 @@ -105,11 +89,7 @@ Data may be corrupted, or further writes to the image may corrupt it. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=134217728 wrote 512/512 bytes at offset 0 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -./common.rc: Killed ( if [ "${VALGRIND_QEMU}" == "y" ]; then - exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -else - exec "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -fi ) +./common.rc: Killed ( VALGRIND_QEMU="${VALGRIND_QEMU_IO}" _qemu_proc_exec "${VALGRIND_LOGFILE}" "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" ) incompatible_features 0x0 No errors were found on the image. *** done diff --git a/tests/qemu-iotests/040 b/tests/qemu-iotests/040 index 6db9abf8e6..762ad1ebcb 100755 --- a/tests/qemu-iotests/040 +++ b/tests/qemu-iotests/040 @@ -429,4 +429,5 @@ class TestReopenOverlay(ImageCommitTestCase): self.run_commit_test(self.img1, self.img0) if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2', 'qed']) + iotests.main(supported_fmts=['qcow2', 'qed'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/041 b/tests/qemu-iotests/041 index 8bc8f81db7..8568426311 100755 --- a/tests/qemu-iotests/041 +++ b/tests/qemu-iotests/041 @@ -1122,4 +1122,5 @@ class TestOrphanedSource(iotests.QMPTestCase): self.assert_qmp(result, 'error/class', 'GenericError') if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2', 'qed']) + iotests.main(supported_fmts=['qcow2', 'qed'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/044 b/tests/qemu-iotests/044 index 9ec3dba734..05ea1f49c5 100755 --- a/tests/qemu-iotests/044 +++ b/tests/qemu-iotests/044 @@ -118,4 +118,5 @@ class TestRefcountTableGrowth(iotests.QMPTestCase): pass if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2']) + iotests.main(supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/045 b/tests/qemu-iotests/045 index d5484a0ee1..01cc038884 100755 --- a/tests/qemu-iotests/045 +++ b/tests/qemu-iotests/045 @@ -175,4 +175,5 @@ class TestSCMFd(iotests.QMPTestCase): "File descriptor named '%s' not found" % fdname) if __name__ == '__main__': - iotests.main(supported_fmts=['raw']) + iotests.main(supported_fmts=['raw'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/051 b/tests/qemu-iotests/051 index ce942a5444..53bcdbc911 100755 --- a/tests/qemu-iotests/051 +++ b/tests/qemu-iotests/051 @@ -377,6 +377,10 @@ printf %b "qemu-io $device_id \"write -P 0x33 0 4k\"\ncommit $device_id\n" | $QEMU_IO -c "read -P 0x33 0 4k" "$TEST_IMG" | _filter_qemu_io # Using snapshot=on with a non-existent TMPDIR +if [ "${VALGRIND_QEMU_VM}" == "y" ]; then + _casenotrun "Valgrind needs a valid TMPDIR for itself" +fi +VALGRIND_QEMU_VM= \ TMPDIR=/nonexistent run_qemu -drive driver=null-co,snapshot=on # Using snapshot=on together with read-only=on diff --git a/tests/qemu-iotests/055 b/tests/qemu-iotests/055 index 3437c11507..c732a112d6 100755 --- a/tests/qemu-iotests/055 +++ b/tests/qemu-iotests/055 @@ -563,4 +563,5 @@ class TestDriveCompression(iotests.QMPTestCase): target='drive1') if __name__ == '__main__': - iotests.main(supported_fmts=['raw', 'qcow2']) + iotests.main(supported_fmts=['raw', 'qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/056 b/tests/qemu-iotests/056 index e761e465ae..98c55d8e5a 100755 --- a/tests/qemu-iotests/056 +++ b/tests/qemu-iotests/056 @@ -335,4 +335,5 @@ class BackupTest(iotests.QMPTestCase): self.dismissal_failure(True) if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2', 'qed']) + iotests.main(supported_fmts=['qcow2', 'qed'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/057 b/tests/qemu-iotests/057 index 9f0a5a3057..9fbba759b6 100755 --- a/tests/qemu-iotests/057 +++ b/tests/qemu-iotests/057 @@ -256,4 +256,5 @@ class TestSnapshotDelete(ImageSnapshotTestCase): self.assert_qmp(result, 'error/class', 'GenericError') if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2']) + iotests.main(supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/061 b/tests/qemu-iotests/061 index d7dbd7e2c7..4eac5b83bd 100755 --- a/tests/qemu-iotests/061 +++ b/tests/qemu-iotests/061 @@ -73,6 +73,7 @@ echo echo "=== Testing dirty version downgrade ===" echo IMGOPTS="compat=1.1,lazy_refcounts=on" _make_test_img 64M +_NO_VALGRIND \ $QEMU_IO -c "write -P 0x2a 0 128k" -c flush \ -c "sigraise $(kill -l KILL)" "$TEST_IMG" 2>&1 | _filter_qemu_io $PYTHON qcow2.py "$TEST_IMG" dump-header @@ -107,6 +108,7 @@ echo echo "=== Testing dirty lazy_refcounts=off ===" echo IMGOPTS="compat=1.1,lazy_refcounts=on" _make_test_img 64M +_NO_VALGRIND \ $QEMU_IO -c "write -P 0x2a 0 128k" -c flush \ -c "sigraise $(kill -l KILL)" "$TEST_IMG" 2>&1 | _filter_qemu_io $PYTHON qcow2.py "$TEST_IMG" dump-header diff --git a/tests/qemu-iotests/061.out b/tests/qemu-iotests/061.out index 1aa7d37ff9..d6a7c2af95 100644 --- a/tests/qemu-iotests/061.out +++ b/tests/qemu-iotests/061.out @@ -118,11 +118,7 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 wrote 131072/131072 bytes at offset 0 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -./common.rc: Killed ( if [ "${VALGRIND_QEMU}" == "y" ]; then - exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -else - exec "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -fi ) +./common.rc: Killed ( VALGRIND_QEMU="${VALGRIND_QEMU_IO}" _qemu_proc_exec "${VALGRIND_LOGFILE}" "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" ) magic 0x514649fb version 3 backing_file_offset 0x0 @@ -280,11 +276,7 @@ No errors were found on the image. Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 wrote 131072/131072 bytes at offset 0 128 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -./common.rc: Killed ( if [ "${VALGRIND_QEMU}" == "y" ]; then - exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -else - exec "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -fi ) +./common.rc: Killed ( VALGRIND_QEMU="${VALGRIND_QEMU_IO}" _qemu_proc_exec "${VALGRIND_LOGFILE}" "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" ) magic 0x514649fb version 3 backing_file_offset 0x0 diff --git a/tests/qemu-iotests/065 b/tests/qemu-iotests/065 index 8bac383ea7..5b21eb96bd 100755 --- a/tests/qemu-iotests/065 +++ b/tests/qemu-iotests/065 @@ -129,4 +129,5 @@ TestQemuImgInfo = None TestQMP = None if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2']) + iotests.main(supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/096 b/tests/qemu-iotests/096 index a69439602d..ab9cb47822 100755 --- a/tests/qemu-iotests/096 +++ b/tests/qemu-iotests/096 @@ -67,4 +67,5 @@ class TestLiveSnapshot(iotests.QMPTestCase): self.checkConfig('target') if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2']) + iotests.main(supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/118 b/tests/qemu-iotests/118 index 6f45779ee9..ea0b326ae0 100755 --- a/tests/qemu-iotests/118 +++ b/tests/qemu-iotests/118 @@ -717,4 +717,5 @@ if __name__ == '__main__': iotests.qemu_default_machine) # Need to support image creation iotests.main(supported_fmts=['vpc', 'parallels', 'qcow', 'vdi', 'qcow2', - 'vmdk', 'raw', 'vhdx', 'qed']) + 'vmdk', 'raw', 'vhdx', 'qed'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/124 b/tests/qemu-iotests/124 index 3440f54781..ca40ba3be2 100755 --- a/tests/qemu-iotests/124 +++ b/tests/qemu-iotests/124 @@ -779,4 +779,5 @@ class TestIncrementalBackupBlkdebug(TestIncrementalBackupBase): if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2']) + iotests.main(supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/129 b/tests/qemu-iotests/129 index 9e87e1c8d9..cd6b9e9ce7 100755 --- a/tests/qemu-iotests/129 +++ b/tests/qemu-iotests/129 @@ -83,4 +83,5 @@ class TestStopWithBlockJob(iotests.QMPTestCase): self.do_test_stop("block-commit", device="drive0") if __name__ == '__main__': - iotests.main(supported_fmts=["qcow2"]) + iotests.main(supported_fmts=["qcow2"], + supported_protocols=["file"]) diff --git a/tests/qemu-iotests/132 b/tests/qemu-iotests/132 index f53ef6e391..0f2a106c81 100755 --- a/tests/qemu-iotests/132 +++ b/tests/qemu-iotests/132 @@ -56,4 +56,5 @@ class TestSingleDrive(iotests.QMPTestCase): 'target image does not match source after mirroring') if __name__ == '__main__': - iotests.main(supported_fmts=['raw', 'qcow2']) + iotests.main(supported_fmts=['raw', 'qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/137 b/tests/qemu-iotests/137 index 0c3d2a1cf0..089821da0c 100755 --- a/tests/qemu-iotests/137 +++ b/tests/qemu-iotests/137 @@ -130,6 +130,7 @@ echo # Whether lazy-refcounts was actually enabled can easily be tested: Check if # the dirty bit is set after a crash +_NO_VALGRIND \ $QEMU_IO \ -c "reopen -o lazy-refcounts=on,overlap-check=blubb" \ -c "write -P 0x5a 0 512" \ diff --git a/tests/qemu-iotests/137.out b/tests/qemu-iotests/137.out index 22d59df40c..1c6569eb2c 100644 --- a/tests/qemu-iotests/137.out +++ b/tests/qemu-iotests/137.out @@ -35,11 +35,7 @@ Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 qemu-io: Unsupported value 'blubb' for qcow2 option 'overlap-check'. Allowed are any of the following: none, constant, cached, all wrote 512/512 bytes at offset 0 512 bytes, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) -./common.rc: Killed ( if [ "${VALGRIND_QEMU}" == "y" ]; then - exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -else - exec "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@"; -fi ) +./common.rc: Killed ( VALGRIND_QEMU="${VALGRIND_QEMU_IO}" _qemu_proc_exec "${VALGRIND_LOGFILE}" "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" ) incompatible_features 0x0 Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=67108864 wrote 65536/65536 bytes at offset 0 diff --git a/tests/qemu-iotests/139 b/tests/qemu-iotests/139 index 2176ea51ba..cbb5a76530 100755 --- a/tests/qemu-iotests/139 +++ b/tests/qemu-iotests/139 @@ -358,4 +358,5 @@ class TestBlockdevDel(iotests.QMPTestCase): if __name__ == '__main__': - iotests.main(supported_fmts=["qcow2"]) + iotests.main(supported_fmts=["qcow2"], + supported_protocols=["file"]) diff --git a/tests/qemu-iotests/147 b/tests/qemu-iotests/147 index 2d84fddb01..ab8480b9a4 100755 --- a/tests/qemu-iotests/147 +++ b/tests/qemu-iotests/147 @@ -287,6 +287,5 @@ class BuiltinNBD(NBDBlockdevAddBase): if __name__ == '__main__': - # Need to support image creation - iotests.main(supported_fmts=['vpc', 'parallels', 'qcow', 'vdi', 'qcow2', - 'vmdk', 'raw', 'vhdx', 'qed']) + iotests.main(supported_fmts=['raw'], + supported_protocols=['nbd']) diff --git a/tests/qemu-iotests/148 b/tests/qemu-iotests/148 index e01b061fe7..8c11c53cba 100755 --- a/tests/qemu-iotests/148 +++ b/tests/qemu-iotests/148 @@ -137,4 +137,5 @@ class TestFifoQuorumEvents(TestQuorumEvents): if __name__ == '__main__': iotests.verify_quorum() - iotests.main(supported_fmts=["raw"]) + iotests.main(supported_fmts=["raw"], + supported_protocols=["file"]) diff --git a/tests/qemu-iotests/151 b/tests/qemu-iotests/151 index ad7359fc8d..76ae265cc1 100755 --- a/tests/qemu-iotests/151 +++ b/tests/qemu-iotests/151 @@ -142,4 +142,5 @@ class TestActiveMirror(iotests.QMPTestCase): if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2', 'raw']) + iotests.main(supported_fmts=['qcow2', 'raw'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/152 b/tests/qemu-iotests/152 index fec546d033..732bf5f062 100755 --- a/tests/qemu-iotests/152 +++ b/tests/qemu-iotests/152 @@ -59,4 +59,5 @@ class TestUnaligned(iotests.QMPTestCase): if __name__ == '__main__': - iotests.main(supported_fmts=['raw', 'qcow2']) + iotests.main(supported_fmts=['raw', 'qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/155 b/tests/qemu-iotests/155 index 63a5b5e2c0..e19485911c 100755 --- a/tests/qemu-iotests/155 +++ b/tests/qemu-iotests/155 @@ -258,4 +258,5 @@ BaseClass = None MirrorBaseClass = None if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2']) + iotests.main(supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/163 b/tests/qemu-iotests/163 index 158ba5d092..081ccc8ac1 100755 --- a/tests/qemu-iotests/163 +++ b/tests/qemu-iotests/163 @@ -170,4 +170,5 @@ class TestShrink1M(ShrinkBaseClass): ShrinkBaseClass = None if __name__ == '__main__': - iotests.main(supported_fmts=['raw', 'qcow2']) + iotests.main(supported_fmts=['raw', 'qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/165 b/tests/qemu-iotests/165 index 88f62d3c6d..5650dc7c87 100755 --- a/tests/qemu-iotests/165 +++ b/tests/qemu-iotests/165 @@ -103,4 +103,5 @@ class TestPersistentDirtyBitmap(iotests.QMPTestCase): self.vm.shutdown() if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2']) + iotests.main(supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/169 b/tests/qemu-iotests/169 index 7e06cc1145..8c204caf20 100755 --- a/tests/qemu-iotests/169 +++ b/tests/qemu-iotests/169 @@ -227,4 +227,5 @@ for cmb in list(itertools.product((True, False), repeat=2)): 'do_test_migration_resume_source', *list(cmb)) if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2']) + iotests.main(supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/183 b/tests/qemu-iotests/183 index fbe5a99beb..04fb344d08 100755 --- a/tests/qemu-iotests/183 +++ b/tests/qemu-iotests/183 @@ -94,8 +94,15 @@ if echo "$reply" | grep "compiled without old-style" > /dev/null; then _notrun "migrate -b support not compiled in" fi -QEMU_COMM_TIMEOUT=0.1 qemu_cmd_repeat=50 silent=yes \ +timeout_comm=$QEMU_COMM_TIMEOUT +if [ "${VALGRIND_QEMU}" == "y" ]; then + QEMU_COMM_TIMEOUT=4 +else + QEMU_COMM_TIMEOUT=0.1 +fi +qemu_cmd_repeat=50 silent=yes \ _send_qemu_cmd $src "{ 'execute': 'query-migrate' }" '"status": "completed"' +QEMU_COMM_TIMEOUT=$timeout_comm _send_qemu_cmd $src "{ 'execute': 'query-status' }" "return" echo diff --git a/tests/qemu-iotests/192 b/tests/qemu-iotests/192 index 6193257764..034432272f 100755 --- a/tests/qemu-iotests/192 +++ b/tests/qemu-iotests/192 @@ -60,7 +60,11 @@ fi qemu_comm_method="monitor" _launch_qemu -drive $DRIVE_ARG -incoming defer h=$QEMU_HANDLE -QEMU_COMM_TIMEOUT=1 +if [ "${VALGRIND_QEMU}" == "y" ]; then + QEMU_COMM_TIMEOUT=7 +else + QEMU_COMM_TIMEOUT=1 +fi _send_qemu_cmd $h "nbd_server_start unix:$TEST_DIR/nbd" "(qemu)" _send_qemu_cmd $h "nbd_server_add -w drive0" "(qemu)" diff --git a/tests/qemu-iotests/196 b/tests/qemu-iotests/196 index 4116ebc92b..92fe9244f8 100755 --- a/tests/qemu-iotests/196 +++ b/tests/qemu-iotests/196 @@ -63,4 +63,5 @@ class TestInvalidateAutoclear(iotests.QMPTestCase): self.assertEqual(f.read(1), b'\x00') if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2']) + iotests.main(supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/199 b/tests/qemu-iotests/199 index 651e8df5d9..a2c8ecab5a 100755 --- a/tests/qemu-iotests/199 +++ b/tests/qemu-iotests/199 @@ -115,4 +115,5 @@ class TestDirtyBitmapPostcopyMigration(iotests.QMPTestCase): self.assert_qmp(result, 'return/sha256', sha256); if __name__ == '__main__': - iotests.main(supported_fmts=['qcow2'], supported_cache_modes=['none']) + iotests.main(supported_fmts=['qcow2'], supported_cache_modes=['none'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/205 b/tests/qemu-iotests/205 index b8a86c446e..76f6c5fa2b 100755 --- a/tests/qemu-iotests/205 +++ b/tests/qemu-iotests/205 @@ -153,4 +153,5 @@ class TestNbdServerRemove(iotests.QMPTestCase): if __name__ == '__main__': - iotests.main(supported_fmts=['generic']) + iotests.main(supported_fmts=['raw'], + supported_protocols=['nbd']) diff --git a/tests/qemu-iotests/232 b/tests/qemu-iotests/232 index 2063f78876..65b0e42063 100755 --- a/tests/qemu-iotests/232 +++ b/tests/qemu-iotests/232 @@ -74,6 +74,12 @@ if [ -n "$TEST_IMG_FILE" ]; then TEST_IMG=$TEST_IMG_FILE fi +chmod a-w $TEST_IMG +(echo test > $TEST_IMG) 2>/dev/null && \ + _notrun "Readonly attribute is ignored, probably you run this test as" \ + "root, which is unsupported." +chmod a+w $TEST_IMG + echo echo "=== -drive with read-write image: read-only/auto-read-only combinations ===" echo diff --git a/tests/qemu-iotests/245 b/tests/qemu-iotests/245 index bc1ceb9792..41218d5f1d 100644 --- a/tests/qemu-iotests/245 +++ b/tests/qemu-iotests/245 @@ -1000,4 +1000,5 @@ class TestBlockdevReopen(iotests.QMPTestCase): self.reopen(opts, {'backing': 'hd2'}) if __name__ == '__main__': - iotests.main(supported_fmts=["qcow2"]) + iotests.main(supported_fmts=["qcow2"], + supported_protocols=["file"]) diff --git a/tests/qemu-iotests/247 b/tests/qemu-iotests/247 index 546a794d3d..c853b73819 100755 --- a/tests/qemu-iotests/247 +++ b/tests/qemu-iotests/247 @@ -57,7 +57,11 @@ TEST_IMG="$TEST_IMG.4" _make_test_img $size {"execute":"block-commit", "arguments":{"device":"format-4", "top-node": "format-2", "base-node":"format-0", "job-id":"job0"}} EOF -sleep 1 +if [ "${VALGRIND_QEMU}" == "y" ]; then + sleep 10 +else + sleep 1 +fi echo '{"execute":"quit"}' ) | $QEMU -qmp stdio -nographic -nodefaults \ -blockdev file,node-name=file-0,filename=$TEST_IMG.0,auto-read-only=on \ diff --git a/tests/qemu-iotests/257 b/tests/qemu-iotests/257 index c2a72c577a..4a636d8ab2 100755 --- a/tests/qemu-iotests/257 +++ b/tests/qemu-iotests/257 @@ -557,4 +557,5 @@ def main(): test_backup_api() if __name__ == '__main__': - iotests.script_main(main, supported_fmts=['qcow2']) + iotests.script_main(main, supported_fmts=['qcow2'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/263 b/tests/qemu-iotests/263 new file mode 100755 index 0000000000..d2c030fae9 --- /dev/null +++ b/tests/qemu-iotests/263 @@ -0,0 +1,91 @@ +#!/usr/bin/env bash +# +# Test encrypted write that crosses cluster boundary of two unallocated clusters +# Based on 188 +# +# Copyright (C) 2019 Red Hat, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +# creator +owner=mlevitsk@redhat.com + +seq=`basename $0` +echo "QA output created by $seq" + +status=1 # failure is the default! + +_cleanup() +{ + _cleanup_test_img +} +trap "_cleanup; exit \$status" 0 1 2 3 15 + +# get standard environment, filters and checks +. ./common.rc +. ./common.filter + +_supported_fmt qcow2 +_supported_proto generic +_supported_os Linux + + +size=1M + +SECRET="secret,id=sec0,data=astrochicken" +QEMU_IO_OPTIONS=$QEMU_IO_OPTIONS_NO_FMT + + +_run_test() +{ + echo "== reading the whole image ==" + $QEMU_IO --object $SECRET -c "read -P 0 0 $size" --image-opts "$1" | _filter_qemu_io | _filter_testdir + + echo + echo "== write two 512 byte sectors on a cluster boundary ==" + $QEMU_IO --object $SECRET -c "write -P 0xAA 0xFE00 0x400" --image-opts "$1" | _filter_qemu_io | _filter_testdir + + echo + echo "== verify that the rest of the image is not changed ==" + $QEMU_IO --object $SECRET -c "read -P 0x00 0x00000 0xFE00" --image-opts "$1" | _filter_qemu_io | _filter_testdir + $QEMU_IO --object $SECRET -c "read -P 0xAA 0x0FE00 0x400" --image-opts "$1" | _filter_qemu_io | _filter_testdir + $QEMU_IO --object $SECRET -c "read -P 0x00 0x10200 0xEFE00" --image-opts "$1" | _filter_qemu_io | _filter_testdir + +} + + +echo +echo "testing LUKS qcow2 encryption" +echo + +_make_test_img --object $SECRET -o "encrypt.format=luks,encrypt.key-secret=sec0,encrypt.iter-time=10,cluster_size=64K" $size +_run_test "driver=$IMGFMT,encrypt.key-secret=sec0,file.filename=$TEST_IMG" +_cleanup_test_img + +echo +echo "testing legacy AES qcow2 encryption" +echo + + +_make_test_img --object $SECRET -o "encrypt.format=aes,encrypt.key-secret=sec0,cluster_size=64K" $size +_run_test "driver=$IMGFMT,encrypt.key-secret=sec0,file.filename=$TEST_IMG" +_cleanup_test_img + + + +# success, all done +echo "*** done" +rm -f $seq.full +status=0 diff --git a/tests/qemu-iotests/263.out b/tests/qemu-iotests/263.out new file mode 100644 index 0000000000..0c982c55cb --- /dev/null +++ b/tests/qemu-iotests/263.out @@ -0,0 +1,40 @@ +QA output created by 263 + +testing LUKS qcow2 encryption + +Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 encrypt.format=luks encrypt.key-secret=sec0 encrypt.iter-time=10 +== reading the whole image == +read 1048576/1048576 bytes at offset 0 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) + +== write two 512 byte sectors on a cluster boundary == +wrote 1024/1024 bytes at offset 65024 +1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) + +== verify that the rest of the image is not changed == +read 65024/65024 bytes at offset 0 +63.500 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 1024/1024 bytes at offset 65024 +1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 982528/982528 bytes at offset 66048 +959.500 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) + +testing legacy AES qcow2 encryption + +Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 encrypt.format=aes encrypt.key-secret=sec0 +== reading the whole image == +read 1048576/1048576 bytes at offset 0 +1 MiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) + +== write two 512 byte sectors on a cluster boundary == +wrote 1024/1024 bytes at offset 65024 +1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) + +== verify that the rest of the image is not changed == +read 65024/65024 bytes at offset 0 +63.500 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 1024/1024 bytes at offset 65024 +1 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +read 982528/982528 bytes at offset 66048 +959.500 KiB, X ops; XX:XX:XX.X (XXX YYY/sec and XXX ops/sec) +*** done diff --git a/tests/qemu-iotests/265 b/tests/qemu-iotests/265 new file mode 100755 index 0000000000..dce6f77be3 --- /dev/null +++ b/tests/qemu-iotests/265 @@ -0,0 +1,67 @@ +#!/usr/bin/env bash +# +# Test reverse-ordered qcow2 writes on a sub-cluster level +# +# Copyright (C) 2019 Red Hat, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +seq=$(basename $0) +echo "QA output created by $seq" + +status=1 # failure is the default! + +_cleanup() +{ + _cleanup_test_img +} +trap "_cleanup; exit \$status" 0 1 2 3 15 + +# get standard environment, filters and checks +. ./common.rc +. ./common.filter + +# qcow2-specific test +_supported_fmt qcow2 +_supported_proto file +_supported_os Linux + +echo '--- Writing to the image ---' + +# Reduce cluster size so we get more and quicker I/O +IMGOPTS='cluster_size=4096' _make_test_img 1M +(for ((kb = 1024 - 4; kb >= 0; kb -= 4)); do \ + echo "aio_write -P 42 $((kb + 1))k 2k"; \ + done) \ + | $QEMU_IO "$TEST_IMG" > /dev/null + +echo '--- Verifying its content ---' + +(for ((kb = 0; kb < 1024; kb += 4)); do \ + echo "read -P 0 ${kb}k 1k"; \ + echo "read -P 42 $((kb + 1))k 2k"; \ + echo "read -P 0 $((kb + 3))k 1k"; \ + done) \ + | $QEMU_IO "$TEST_IMG" | _filter_qemu_io | grep 'verification' + +# Status of qemu-io +if [ ${PIPESTATUS[1]} = 0 ]; then + echo 'Content verified.' +fi + +# success, all done +echo "*** done" +rm -f $seq.full +status=0 diff --git a/tests/qemu-iotests/265.out b/tests/qemu-iotests/265.out new file mode 100644 index 0000000000..6eac620f25 --- /dev/null +++ b/tests/qemu-iotests/265.out @@ -0,0 +1,6 @@ +QA output created by 265 +--- Writing to the image --- +Formatting 'TEST_DIR/t.IMGFMT', fmt=IMGFMT size=1048576 +--- Verifying its content --- +Content verified. +*** done diff --git a/tests/qemu-iotests/266 b/tests/qemu-iotests/266 new file mode 100755 index 0000000000..5b35cd67e4 --- /dev/null +++ b/tests/qemu-iotests/266 @@ -0,0 +1,153 @@ +#!/usr/bin/env python +# +# Test VPC and file image creation +# +# Copyright (C) 2019 Red Hat, Inc. +# +# This program is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program. If not, see <http://www.gnu.org/licenses/>. +# + +import iotests +from iotests import imgfmt + + +def blockdev_create(vm, options): + result = vm.qmp_log('blockdev-create', job_id='job0', options=options, + filters=[iotests.filter_qmp_testfiles]) + + if 'return' in result: + assert result['return'] == {} + vm.run_job('job0') + + +# Successful image creation (defaults) +def implicit_defaults(vm, file_path): + iotests.log("=== Successful image creation (defaults) ===") + iotests.log("") + + # 8 heads, 964 cyls/head, 17 secs/cyl + # (Close to 64 MB) + size = 8 * 964 * 17 * 512 + + blockdev_create(vm, { 'driver': imgfmt, + 'file': 'protocol-node', + 'size': size }) + + +# Successful image creation (explicit defaults) +def explicit_defaults(vm, file_path): + iotests.log("=== Successful image creation (explicit defaults) ===") + iotests.log("") + + # 16 heads, 964 cyls/head, 17 secs/cyl + # (Close to 128 MB) + size = 16 * 964 * 17 * 512 + + blockdev_create(vm, { 'driver': imgfmt, + 'file': 'protocol-node', + 'size': size, + 'subformat': 'dynamic', + 'force-size': False }) + + +# Successful image creation (non-default options) +def non_defaults(vm, file_path): + iotests.log("=== Successful image creation (non-default options) ===") + iotests.log("") + + # Not representable in CHS (fine with force-size=True) + size = 1048576 + + blockdev_create(vm, { 'driver': imgfmt, + 'file': 'protocol-node', + 'size': size, + 'subformat': 'fixed', + 'force-size': True }) + + +# Size not representable in CHS with force-size=False +def non_chs_size_without_force(vm, file_path): + iotests.log("=== Size not representable in CHS ===") + iotests.log("") + + # Not representable in CHS (will not work with force-size=False) + size = 1048576 + + blockdev_create(vm, { 'driver': imgfmt, + 'file': 'protocol-node', + 'size': size, + 'force-size': False }) + + +# Zero size +def zero_size(vm, file_path): + iotests.log("=== Zero size===") + iotests.log("") + + blockdev_create(vm, { 'driver': imgfmt, + 'file': 'protocol-node', + 'size': 0 }) + + +# Maximum CHS size +def maximum_chs_size(vm, file_path): + iotests.log("=== Maximum CHS size===") + iotests.log("") + + blockdev_create(vm, { 'driver': imgfmt, + 'file': 'protocol-node', + 'size': 16 * 65535 * 255 * 512 }) + + +# Actual maximum size +def maximum_size(vm, file_path): + iotests.log("=== Actual maximum size===") + iotests.log("") + + blockdev_create(vm, { 'driver': imgfmt, + 'file': 'protocol-node', + 'size': 0xff000000 * 512, + 'force-size': True }) + + +def main(): + for test_func in [implicit_defaults, explicit_defaults, non_defaults, + non_chs_size_without_force, zero_size, maximum_chs_size, + maximum_size]: + + with iotests.FilePath('t.vpc') as file_path, \ + iotests.VM() as vm: + + vm.launch() + + iotests.log('--- Creating empty file ---') + blockdev_create(vm, { 'driver': 'file', + 'filename': file_path, + 'size': 0 }) + + vm.qmp_log('blockdev-add', driver='file', filename=file_path, + node_name='protocol-node', + filters=[iotests.filter_qmp_testfiles]) + iotests.log('') + + print_info = test_func(vm, file_path) + iotests.log('') + + vm.shutdown() + iotests.img_info_log(file_path) + + +iotests.script_main(main, + supported_fmts=['vpc'], + supported_protocols=['file']) diff --git a/tests/qemu-iotests/266.out b/tests/qemu-iotests/266.out new file mode 100644 index 0000000000..b11953e81f --- /dev/null +++ b/tests/qemu-iotests/266.out @@ -0,0 +1,137 @@ +--- Creating empty file --- +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "size": 0}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} +{"execute": "blockdev-add", "arguments": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "node-name": "protocol-node"}} +{"return": {}} + +=== Successful image creation (defaults) === + +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "vpc", "file": "protocol-node", "size": 67125248}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} + +image: TEST_IMG +file format: IMGFMT +virtual size: 64 MiB (67125248 bytes) +cluster_size: 2097152 + +--- Creating empty file --- +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "size": 0}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} +{"execute": "blockdev-add", "arguments": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "node-name": "protocol-node"}} +{"return": {}} + +=== Successful image creation (explicit defaults) === + +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "vpc", "file": "protocol-node", "force-size": false, "size": 134250496, "subformat": "dynamic"}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} + +image: TEST_IMG +file format: IMGFMT +virtual size: 128 MiB (134250496 bytes) +cluster_size: 2097152 + +--- Creating empty file --- +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "size": 0}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} +{"execute": "blockdev-add", "arguments": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "node-name": "protocol-node"}} +{"return": {}} + +=== Successful image creation (non-default options) === + +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "vpc", "file": "protocol-node", "force-size": true, "size": 1048576, "subformat": "fixed"}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} + +image: TEST_IMG +file format: IMGFMT +virtual size: 1 MiB (1048576 bytes) + +--- Creating empty file --- +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "size": 0}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} +{"execute": "blockdev-add", "arguments": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "node-name": "protocol-node"}} +{"return": {}} + +=== Size not representable in CHS === + +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "vpc", "file": "protocol-node", "force-size": false, "size": 1048576}}} +{"return": {}} +Job failed: The requested image size cannot be represented in CHS geometry +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} + +qemu-img: Could not open 'TEST_IMG': File too small for a VHD header + +--- Creating empty file --- +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "size": 0}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} +{"execute": "blockdev-add", "arguments": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "node-name": "protocol-node"}} +{"return": {}} + +=== Zero size=== + +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "vpc", "file": "protocol-node", "size": 0}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} + +image: TEST_IMG +file format: IMGFMT +virtual size: 0 B (0 bytes) +cluster_size: 2097152 + +--- Creating empty file --- +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "size": 0}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} +{"execute": "blockdev-add", "arguments": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "node-name": "protocol-node"}} +{"return": {}} + +=== Maximum CHS size=== + +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "vpc", "file": "protocol-node", "size": 136899993600}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} + +image: TEST_IMG +file format: IMGFMT +virtual size: 127 GiB (136899993600 bytes) +cluster_size: 2097152 + +--- Creating empty file --- +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "size": 0}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} +{"execute": "blockdev-add", "arguments": {"driver": "file", "filename": "TEST_DIR/PID-t.vpc", "node-name": "protocol-node"}} +{"return": {}} + +=== Actual maximum size=== + +{"execute": "blockdev-create", "arguments": {"job-id": "job0", "options": {"driver": "vpc", "file": "protocol-node", "force-size": true, "size": 2190433320960}}} +{"return": {}} +{"execute": "job-dismiss", "arguments": {"id": "job0"}} +{"return": {}} + +image: TEST_IMG +file format: IMGFMT +virtual size: 1.99 TiB (2190433320960 bytes) +cluster_size: 2097152 + diff --git a/tests/qemu-iotests/check b/tests/qemu-iotests/check index a58232eefb..875399d79f 100755 --- a/tests/qemu-iotests/check +++ b/tests/qemu-iotests/check @@ -694,12 +694,12 @@ END { if (NR > 0) { if [ ! -z "$n_bad" -a $n_bad != 0 ] then echo "Failures:$bad" - echo "Failed $n_bad of $try tests" + echo "Failed $n_bad of $try iotests" echo "Failures:$bad" | fmt >>check.log - echo "Failed $n_bad of $try tests" >>check.log + echo "Failed $n_bad of $try iotests" >>check.log else - echo "Passed all $try tests" - echo "Passed all $try tests" >>check.log + echo "Passed all $try iotests" + echo "Passed all $try iotests" >>check.log fi needwrap=false fi diff --git a/tests/qemu-iotests/common.rc b/tests/qemu-iotests/common.rc index ee20be8920..e45cdfa66b 100644 --- a/tests/qemu-iotests/common.rc +++ b/tests/qemu-iotests/common.rc @@ -60,19 +60,68 @@ if ! . ./common.config exit 1 fi +# Set the variables to the empty string to turn Valgrind off +# for specific processes, e.g. +# $ VALGRIND_QEMU_IO= ./check -qcow2 -valgrind 015 + +: ${VALGRIND_QEMU_VM=$VALGRIND_QEMU} +: ${VALGRIND_QEMU_IMG=$VALGRIND_QEMU} +: ${VALGRIND_QEMU_IO=$VALGRIND_QEMU} +: ${VALGRIND_QEMU_NBD=$VALGRIND_QEMU} +: ${VALGRIND_QEMU_VXHS=$VALGRIND_QEMU} + +# The Valgrind own parameters may be set with +# its environment variable VALGRIND_OPTS, e.g. +# $ VALGRIND_OPTS="--leak-check=yes" ./check -qcow2 -valgrind 015 + +_qemu_proc_exec() +{ + local VALGRIND_LOGFILE="$1" + shift + if [[ "${VALGRIND_QEMU}" == "y" && "${NO_VALGRIND}" != "y" ]]; then + exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$@" + else + exec "$@" + fi +} + +_qemu_proc_valgrind_log() +{ + local VALGRIND_LOGFILE="$1" + local RETVAL="$2" + if [[ "${VALGRIND_QEMU}" == "y" && "${NO_VALGRIND}" != "y" ]]; then + if [ $RETVAL == 99 ]; then + cat "${VALGRIND_LOGFILE}" + fi + rm -f "${VALGRIND_LOGFILE}" + fi +} + _qemu_wrapper() { + local VALGRIND_LOGFILE="${TEST_DIR}"/$$.valgrind ( if [ -n "${QEMU_NEED_PID}" ]; then echo $BASHPID > "${QEMU_TEST_DIR}/qemu-${_QEMU_HANDLE}.pid" fi - exec "$QEMU_PROG" $QEMU_OPTIONS "$@" + VALGRIND_QEMU="${VALGRIND_QEMU_VM}" _qemu_proc_exec "${VALGRIND_LOGFILE}" \ + "$QEMU_PROG" $QEMU_OPTIONS "$@" ) + RETVAL=$? + _qemu_proc_valgrind_log "${VALGRIND_LOGFILE}" $RETVAL + return $RETVAL } _qemu_img_wrapper() { - (exec "$QEMU_IMG_PROG" $QEMU_IMG_OPTIONS "$@") + local VALGRIND_LOGFILE="${TEST_DIR}"/$$.valgrind + ( + VALGRIND_QEMU="${VALGRIND_QEMU_IMG}" _qemu_proc_exec "${VALGRIND_LOGFILE}" \ + "$QEMU_IMG_PROG" $QEMU_IMG_OPTIONS "$@" + ) + RETVAL=$? + _qemu_proc_valgrind_log "${VALGRIND_LOGFILE}" $RETVAL + return $RETVAL } _qemu_io_wrapper() @@ -85,36 +134,47 @@ _qemu_io_wrapper() QEMU_IO_ARGS="--object secret,id=keysec0,data=$IMGKEYSECRET $QEMU_IO_ARGS" fi fi - local RETVAL ( - if [ "${VALGRIND_QEMU}" == "y" ]; then - exec valgrind --log-file="${VALGRIND_LOGFILE}" --error-exitcode=99 "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" - else - exec "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" - fi + VALGRIND_QEMU="${VALGRIND_QEMU_IO}" _qemu_proc_exec "${VALGRIND_LOGFILE}" \ + "$QEMU_IO_PROG" $QEMU_IO_ARGS "$@" ) RETVAL=$? - if [ "${VALGRIND_QEMU}" == "y" ]; then - if [ $RETVAL == 99 ]; then - cat "${VALGRIND_LOGFILE}" - fi - rm -f "${VALGRIND_LOGFILE}" - fi - (exit $RETVAL) + _qemu_proc_valgrind_log "${VALGRIND_LOGFILE}" $RETVAL + return $RETVAL } _qemu_nbd_wrapper() { - "$QEMU_NBD_PROG" --pid-file="${QEMU_TEST_DIR}/qemu-nbd.pid" \ - $QEMU_NBD_OPTIONS "$@" + local VALGRIND_LOGFILE="${TEST_DIR}"/$$.valgrind + ( + VALGRIND_QEMU="${VALGRIND_QEMU_NBD}" _qemu_proc_exec "${VALGRIND_LOGFILE}" \ + "$QEMU_NBD_PROG" --pid-file="${QEMU_TEST_DIR}/qemu-nbd.pid" \ + $QEMU_NBD_OPTIONS "$@" + ) + RETVAL=$? + _qemu_proc_valgrind_log "${VALGRIND_LOGFILE}" $RETVAL + return $RETVAL } _qemu_vxhs_wrapper() { + local VALGRIND_LOGFILE="${TEST_DIR}"/$$.valgrind ( echo $BASHPID > "${TEST_DIR}/qemu-vxhs.pid" - exec "$QEMU_VXHS_PROG" $QEMU_VXHS_OPTIONS "$@" + VALGRIND_QEMU="${VALGRIND_QEMU_VXHS}" _qemu_proc_exec "${VALGRIND_LOGFILE}" \ + "$QEMU_VXHS_PROG" $QEMU_VXHS_OPTIONS "$@" ) + RETVAL=$? + _qemu_proc_valgrind_log "${VALGRIND_LOGFILE}" $RETVAL + return $RETVAL +} + +# Valgrind bug #409141 https://bugs.kde.org/show_bug.cgi?id=409141 +# Until valgrind 3.16+ is ubiquitous, we must work around a hang in +# valgrind when issuing sigkill. Disable valgrind for this invocation. +_NO_VALGRIND() +{ + NO_VALGRIND="y" "$@" } export QEMU=_qemu_wrapper @@ -395,6 +455,15 @@ _notrun() exit } +# bail out, setting up .casenotrun file +# The function _casenotrun() is used as a notifier. It is the +# caller's responsibility to make skipped a particular test. +# +_casenotrun() +{ + echo " [case not run] $*" >>"$OUTPUT_DIR/$seq.casenotrun" +} + # just plain bail out # _fail() diff --git a/tests/qemu-iotests/group b/tests/qemu-iotests/group index d95d556414..5d3da937e4 100644 --- a/tests/qemu-iotests/group +++ b/tests/qemu-iotests/group @@ -274,3 +274,6 @@ 257 rw 258 rw quick 262 rw quick migration +263 rw quick +265 rw auto quick +266 rw quick diff --git a/tests/qemu-iotests/iotests.py b/tests/qemu-iotests/iotests.py index 84438e837c..b26271187c 100644 --- a/tests/qemu-iotests/iotests.py +++ b/tests/qemu-iotests/iotests.py @@ -909,7 +909,8 @@ def execute_unittest(output, verbosity, debug): def execute_test(test_function=None, supported_fmts=[], supported_oses=['linux'], - supported_cache_modes=[], unsupported_fmts=[]): + supported_cache_modes=[], unsupported_fmts=[], + supported_protocols=[], unsupported_protocols=[]): """Run either unittest or script-style tests.""" # We are using TEST_DIR and QEMU_DEFAULT_MACHINE as proxies to @@ -923,6 +924,7 @@ def execute_test(test_function=None, debug = '-d' in sys.argv verbosity = 1 verify_image_format(supported_fmts, unsupported_fmts) + verify_protocol(supported_protocols, unsupported_protocols) verify_platform(supported_oses) verify_cache_mode(supported_cache_modes) diff --git a/tests/tcg/.gitignore b/tests/tcg/.gitignore new file mode 100644 index 0000000000..84d7541b28 --- /dev/null +++ b/tests/tcg/.gitignore @@ -0,0 +1,5 @@ +# These are build artefacts which only appear when you are doing +# builds directly in the source tree. +config-*.mak +*-softmmu/ +*-linux-user/ diff --git a/tests/tcg/Makefile.include b/tests/tcg/Makefile.include deleted file mode 100644 index 73b5626fc5..0000000000 --- a/tests/tcg/Makefile.include +++ /dev/null @@ -1,88 +0,0 @@ -# -*- Mode: makefile -*- -# -# TCG tests (per-target rules) -# -# This Makefile fragment is included from the per-target -# Makefile.target so will be invoked for each linux-user program we -# build. We have two options for compiling, either using a configured -# guest compiler or calling one of our docker images to do it for us. -# - -# The per ARCH makefile, if it exists, holds extra information about -# useful docker images or alternative compiler flags. - --include $(SRC_PATH)/tests/tcg/$(TARGET_BASE_ARCH)/Makefile.include --include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.include - -GUEST_BUILD= -TCG_MAKE=$(SRC_PATH)/tests/tcg/Makefile -# Support installed Cross Compilers - -ifdef CROSS_CC_GUEST - -.PHONY: cross-build-guest-tests -cross-build-guest-tests: - $(call quiet-command, \ - (mkdir -p tests && cd tests && \ - $(MAKE) -f $(TCG_MAKE) CC=$(CROSS_CC_GUEST) \ - BUILD_STATIC=$(CROSS_CC_GUEST_STATIC) \ - EXTRA_CFLAGS=$(CROSS_CC_GUEST_CFLAGS)), \ - "BUILD","$(TARGET_NAME) guest-tests with $(CROSS_CC_GUEST)") - -GUEST_BUILD=cross-build-guest-tests - -endif - -# Support building with Docker - -ifeq ($(HAVE_USER_DOCKER)$(GUEST_BUILD),y) -ifneq ($(DOCKER_IMAGE),) - -# We also need the Docker make rules to depend on -include $(SRC_PATH)/tests/docker/Makefile.include - -DOCKER_COMPILE_CMD="$(DOCKER_SCRIPT) cc --user $(shell id -u) \ - --cc $(DOCKER_CROSS_COMPILER) \ - -i qemu:$(DOCKER_IMAGE) \ - -s $(SRC_PATH) -- " -DOCKER_PREREQ=docker-image-$(DOCKER_IMAGE) - -.PHONY: docker-build-guest-tests -docker-build-guest-tests: $(DOCKER_PREREQ) - $(call quiet-command, \ - (mkdir -p tests && cd tests && \ - $(MAKE) -f $(TCG_MAKE) CC=$(DOCKER_COMPILE_CMD) \ - BUILD_STATIC=y \ - EXTRA_CFLAGS=$(DOCKER_CROSS_COMPILER_CFLAGS)), \ - "BUILD","$(TARGET_NAME) guest-tests with docker qemu:$(DOCKER_IMAGE)") - -GUEST_BUILD=docker-build-guest-tests - -endif -endif - -# Final targets -.PHONY: guest-tests - -ifneq ($(GUEST_BUILD),) -guest-tests: $(GUEST_BUILD) - -run-guest-tests: guest-tests qemu-$(subst y,system-,$(CONFIG_SOFTMMU))$(TARGET_NAME) - $(call quiet-command, \ - (cd tests && $(MAKE) -f $(TCG_MAKE) SPEED=$(SPEED) run), \ - "RUN", "tests for $(TARGET_NAME)") - -else -guest-tests: - $(call quiet-command, /bin/true, "BUILD", \ - "$(TARGET_NAME) guest-tests SKIPPED") - -run-guest-tests: - $(call quiet-command, /bin/true, "RUN", \ - "tests for $(TARGET_NAME) SKIPPED") -endif - -# It doesn't matter if these don't exits -.PHONY: clean-guest-tests -clean-guest-tests: - rm -rf tests || echo "no $(TARGET_NAME) tests to remove" diff --git a/tests/tcg/Makefile.prereqs b/tests/tcg/Makefile.prereqs new file mode 100644 index 0000000000..7494b31b95 --- /dev/null +++ b/tests/tcg/Makefile.prereqs @@ -0,0 +1,18 @@ +# -*- Mode: makefile -*- +# +# TCG Compiler Probe +# +# This Makefile fragment is included multiple times in the main make +# script to probe for available compilers. This is used to build up a +# selection of required docker targets before we invoke a sub-make for +# each target. + +DOCKER_IMAGE:= + +-include $(BUILD_DIR)/tests/tcg/config-$(PROBE_TARGET).mak + +ifneq ($(DOCKER_IMAGE),) +build-tcg-tests-$(PROBE_TARGET): docker-image-$(DOCKER_IMAGE) +$(BUILD_DIR)/tests/tcg/config_$(PROBE_TARGET).mak: config-host.mak +config-host.mak: $(SRC_PATH)/tests/tcg/configure.sh +endif diff --git a/tests/tcg/Makefile.probe b/tests/tcg/Makefile.probe deleted file mode 100644 index 9dc654663d..0000000000 --- a/tests/tcg/Makefile.probe +++ /dev/null @@ -1,31 +0,0 @@ -# -*- Mode: makefile -*- -# -# TCG Compiler Probe -# -# This Makefile fragment is included multiple times in the main make -# script to probe for available compilers. This is used to build up a -# selection of required docker targets before we invoke a sub-make for -# each target. - -# First we need the target makefile which tells us the target architecture --include $(BUILD_DIR)/$(PROBE_TARGET)/config-target.mak - -# Then we load up the target architecture makefiles which tell us -# about the compilers -CROSS_CC_GUEST:= -DOCKER_IMAGE:= -DOCKER_PREREQ:= - --include $(SRC_PATH)/tests/tcg/$(TARGET_BASE_ARCH)/Makefile.include --include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.include - -ifndef CROSS_CC_GUEST -ifneq ($(DOCKER_IMAGE),) -DOCKER_PREREQ:=docker-image-$(DOCKER_IMAGE) -endif -endif - -# Clean-up -# undefine TARGET_NAME -# undefine TARGET_BASE_ARCH -# undefine TARGET_ABI_DIR diff --git a/tests/tcg/Makefile.qemu b/tests/tcg/Makefile.qemu new file mode 100644 index 0000000000..9c23aeaa2a --- /dev/null +++ b/tests/tcg/Makefile.qemu @@ -0,0 +1,95 @@ +# -*- Mode: makefile -*- +# +# TCG tests (per-target rules) +# +# This Makefile fragment is included from the build-tcg target, once +# for each target we build. We have two options for compiling, either +# using a configured guest compiler or calling one of our docker images +# to do it for us. +# + +include $(SRC_PATH)/rules.mak + +# The configure script fills in extra information about +# useful docker images or alternative compiler flags. + +CROSS_CC_GUEST:= +DOCKER_IMAGE:= +-include $(BUILD_DIR)/tests/tcg/config-$(TARGET).mak + +GUEST_BUILD= +TCG_MAKE=../Makefile.target + +# We also need the Docker make rules to depend on +SKIP_DOCKER_BUILD=1 +include $(SRC_PATH)/tests/docker/Makefile.include + +# Support installed Cross Compilers + +ifdef CROSS_CC_GUEST + +.PHONY: cross-build-guest-tests +cross-build-guest-tests: + $(call quiet-command, \ + (mkdir -p tests/tcg/$(TARGET) && cd tests/tcg/$(TARGET) && \ + $(MAKE) -f $(TCG_MAKE) TARGET="$(TARGET)" CC="$(CROSS_CC_GUEST)" \ + SRC_PATH="$(SRC_PATH)" BUILD_STATIC=$(CROSS_CC_GUEST_STATIC) \ + EXTRA_CFLAGS="$(CROSS_CC_GUEST_CFLAGS)"), \ + "BUILD","$(TARGET) guest-tests with $(CROSS_CC_GUEST)") + +GUEST_BUILD=cross-build-guest-tests + +endif + +# Support building with Docker + +ifneq ($(DOCKER_IMAGE),) + +DOCKER_COMPILE_CMD="$(DOCKER_SCRIPT) cc \ + --cc $(DOCKER_CROSS_CC_GUEST) \ + -i qemu:$(DOCKER_IMAGE) \ + -s $(SRC_PATH) -- " + +.PHONY: docker-build-guest-tests +docker-build-guest-tests: docker-image-$(DOCKER_IMAGE) + $(call quiet-command, \ + (mkdir -p tests/tcg/$(TARGET) && cd tests/tcg/$(TARGET) && \ + $(MAKE) -f $(TCG_MAKE) TARGET="$(TARGET)" CC=$(DOCKER_COMPILE_CMD) \ + SRC_PATH="$(SRC_PATH)" BUILD_STATIC=y \ + EXTRA_CFLAGS="$(CROSS_CC_GUEST_CFLAGS)"), \ + "BUILD","$(TARGET) guest-tests with docker qemu:$(DOCKER_IMAGE)") + +GUEST_BUILD=docker-build-guest-tests + +endif + +# Final targets +all: + @echo "Do not invoke this Makefile directly"; exit 1 + +.PHONY: guest-tests + +ifneq ($(GUEST_BUILD),) +guest-tests: $(GUEST_BUILD) + +run-guest-tests: guest-tests + $(call quiet-command, \ + (cd tests/tcg/$(TARGET) && \ + $(MAKE) -f $(TCG_MAKE) TARGET="$(TARGET)" \ + SRC_PATH="$(SRC_PATH)" SPEED=$(SPEED) run), \ + "RUN", "tests for $(TARGET_NAME)") + +else +guest-tests: + $(call quiet-command, /bin/true, "BUILD", \ + "$(TARGET) guest-tests SKIPPED") + +run-guest-tests: + $(call quiet-command, /bin/true, "RUN", \ + "tests for $(TARGET) SKIPPED") +endif + +# It doesn't matter if these don't exits +.PHONY: clean-guest-tests +clean-guest-tests: + rm -rf tests/tcg/$(TARGET) diff --git a/tests/tcg/Makefile b/tests/tcg/Makefile.target index 9f56768624..8808beaf74 100644 --- a/tests/tcg/Makefile +++ b/tests/tcg/Makefile.target @@ -29,8 +29,9 @@ # We also expect to be in the tests build dir for the FOO-(linux-user|softmmu). # +all: -include ../../config-host.mak --include ../config-target.mak +-include ../config-$(TARGET).mak # for including , in command strings COMMA := , @@ -62,12 +63,6 @@ CFLAGS= QEMU_CFLAGS= LDFLAGS= -# The QEMU for this TARGET -ifdef CONFIG_USER_ONLY -QEMU=../qemu-$(TARGET_NAME) -else -QEMU=../qemu-system-$(TARGET_NAME) -endif QEMU_OPTS= @@ -82,10 +77,7 @@ ifdef CONFIG_USER_ONLY # The order we include is important. We include multiarch, base arch # and finally arch if it's not the same as base arch. -include $(SRC_PATH)/tests/tcg/multiarch/Makefile.target --include $(SRC_PATH)/tests/tcg/$(TARGET_BASE_ARCH)/Makefile.target -ifneq ($(TARGET_BASE_ARCH),$(TARGET_NAME)) -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.target -endif # Add the common build options CFLAGS+=-Wall -O0 -g -fno-strict-aliasing @@ -101,10 +93,7 @@ else # are expected to provide their own build recipes. -include $(SRC_PATH)/tests/tcg/minilib/Makefile.target -include $(SRC_PATH)/tests/tcg/multiarch/system/Makefile.softmmu-target --include $(SRC_PATH)/tests/tcg/$(TARGET_BASE_ARCH)/Makefile.softmmu-target -ifneq ($(TARGET_BASE_ARCH),$(TARGET_NAME)) -include $(SRC_PATH)/tests/tcg/$(TARGET_NAME)/Makefile.softmmu-target -endif endif diff --git a/tests/tcg/aarch64/Makefile.include b/tests/tcg/aarch64/Makefile.include deleted file mode 100644 index 5d4e4c6f99..0000000000 --- a/tests/tcg/aarch64/Makefile.include +++ /dev/null @@ -1,8 +0,0 @@ -# Makefile.include for AArch64 targets -# -# We don't have any bigendian build tools so we only use this for AArch64 - -ifeq ($(TARGET_NAME),aarch64) -DOCKER_IMAGE=debian-buster-arm64-cross -DOCKER_CROSS_COMPILER=aarch64-linux-gnu-gcc -endif diff --git a/tests/tcg/aarch64/Makefile.softmmu-target b/tests/tcg/aarch64/Makefile.softmmu-target index 2e560e4d08..4c4aaf61dd 100644 --- a/tests/tcg/aarch64/Makefile.softmmu-target +++ b/tests/tcg/aarch64/Makefile.softmmu-target @@ -22,11 +22,11 @@ LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc .PRECIOUS: $(CRT_OBJS) %.o: $(CRT_PATH)/%.S - $(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@ # Build and link the tests %: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) memory: CFLAGS+=-DCHECK_UNALIGNED=1 diff --git a/tests/tcg/aarch64/Makefile.target b/tests/tcg/aarch64/Makefile.target index 31ba9cfcaa..e763dd9da3 100644 --- a/tests/tcg/aarch64/Makefile.target +++ b/tests/tcg/aarch64/Makefile.target @@ -2,12 +2,14 @@ # # AArch64 specific tweaks +ARM_SRC=$(SRC_PATH)/tests/tcg/arm +VPATH += $(ARM_SRC) + AARCH64_SRC=$(SRC_PATH)/tests/tcg/aarch64 VPATH += $(AARCH64_SRC) -# we don't build any of the ARM tests -AARCH64_TESTS=$(filter-out $(ARM_TESTS), $(TESTS)) -AARCH64_TESTS+=fcvt +# we don't build any other ARM test +AARCH64_TESTS=fcvt fcvt: LDFLAGS+=-lm @@ -16,6 +18,6 @@ run-fcvt: fcvt $(call diff-out,$<,$(AARCH64_SRC)/fcvt.ref) AARCH64_TESTS += pauth-1 pauth-2 -run-pauth-%: QEMU += -cpu max +run-pauth-%: QEMU_OPTS += -cpu max -TESTS:=$(AARCH64_TESTS) +TESTS += $(AARCH64_TESTS) diff --git a/tests/tcg/alpha/Makefile.include b/tests/tcg/alpha/Makefile.include deleted file mode 100644 index c7dc48eadb..0000000000 --- a/tests/tcg/alpha/Makefile.include +++ /dev/null @@ -1,2 +0,0 @@ -DOCKER_IMAGE=debian-alpha-cross -DOCKER_CROSS_COMPILER=alpha-linux-gnu-gcc diff --git a/tests/tcg/alpha/Makefile.softmmu-target b/tests/tcg/alpha/Makefile.softmmu-target index 3c0f34cc69..09193a62d6 100644 --- a/tests/tcg/alpha/Makefile.softmmu-target +++ b/tests/tcg/alpha/Makefile.softmmu-target @@ -22,11 +22,11 @@ LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc .PRECIOUS: $(CRT_OBJS) %.o: $(CRT_PATH)/%.S - $(CC) $(CFLAGS) -x assembler-with-cpp -c $< -o $@ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -x assembler-with-cpp -c $< -o $@ # Build and link the tests %: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) memory: CFLAGS+=-DCHECK_UNALIGNED=0 diff --git a/tests/tcg/arm/Makefile.include b/tests/tcg/arm/Makefile.include deleted file mode 100644 index 8e7eac008f..0000000000 --- a/tests/tcg/arm/Makefile.include +++ /dev/null @@ -1,8 +0,0 @@ -# Makefile.include for all ARM targets -# -# We don't have any bigendian build tools so we only use this for armhf - -ifeq ($(TARGET_NAME),arm) -DOCKER_IMAGE=debian-armhf-cross -DOCKER_CROSS_COMPILER=arm-linux-gnueabihf-gcc -endif diff --git a/tests/tcg/arm/Makefile.softmmu-target b/tests/tcg/arm/Makefile.softmmu-target index 49d48d8a1c..231e9a57b4 100644 --- a/tests/tcg/arm/Makefile.softmmu-target +++ b/tests/tcg/arm/Makefile.softmmu-target @@ -3,8 +3,6 @@ # ARM SoftMMU tests - included from tests/tcg/Makefile # -ifeq ($(TARGET_ABI_DIR),arm) - ARM_SRC=$(SRC_PATH)/tests/tcg/arm # Set search path for all sources @@ -18,12 +16,10 @@ CFLAGS+=-Wl,--build-id=none -x assembler-with-cpp LDFLAGS+=-nostdlib -N -static %: %.S %.ld - $(CC) $(CFLAGS) $(ASFLAGS) $< -o $@ $(LDFLAGS) -T $(ARM_SRC)/$@.ld + $(CC) $(CFLAGS) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) -T $(ARM_SRC)/$@.ld # Specific Test Rules test-armv6m-undef: EXTRA_CFLAGS+=-mcpu=cortex-m0 run-test-armv6m-undef: QEMU_OPTS+=-semihosting -M microbit -kernel - -endif diff --git a/tests/tcg/configure.sh b/tests/tcg/configure.sh new file mode 100755 index 0000000000..6c4a471aea --- /dev/null +++ b/tests/tcg/configure.sh @@ -0,0 +1,234 @@ +#! /bin/sh + +if test -z "$source_path"; then + echo Do not invoke this script directly. It is called + echo automatically by configure. + exit 1 +fi + +write_c_skeleton() { + cat > $TMPC <<EOF +int main(void) { return 0; } +EOF +} + +has() { + command -v "$1" >/dev/null 2>&1 +} + +do_compiler() { + # Run the compiler, capturing its output to the log. First argument + # is compiler binary to execute. + local compiler="$1" + shift + if test -n "$BASH_VERSION"; then eval ' + echo >>config.log " +funcs: ${FUNCNAME[*]} +lines: ${BASH_LINENO[*]}" + '; fi + echo $compiler "$@" >> config.log + $compiler "$@" >> config.log 2>&1 || return $? +} + + +TMPDIR1="config-temp" +TMPC="${TMPDIR1}/qemu-conf.c" +TMPE="${TMPDIR1}/qemu-conf.exe" + +container="no" +if has "docker" || has "podman"; then + container=$($python $source_path/tests/docker/docker.py probe) +fi + +# cross compilers defaults, can be overridden with --cross-cc-ARCH +: ${cross_cc_aarch64="aarch64-linux-gnu-gcc"} +: ${cross_cc_aarch64_be="$cross_cc_aarch64"} +: ${cross_cc_cflags_aarch64_be="-mbig-endian"} +: ${cross_cc_arm="arm-linux-gnueabihf-gcc"} +: ${cross_cc_cflags_armeb="-mbig-endian"} +: ${cross_cc_i386="i386-pc-linux-gnu-gcc"} +: ${cross_cc_cflags_i386="-m32"} +: ${cross_cc_x86_64="x86_64-pc-linux-gnu-gcc"} +: ${cross_cc_cflags_x86_64="-m64"} +: ${cross_cc_ppc="powerpc-linux-gnu-gcc"} +: ${cross_cc_cflags_ppc="-m32"} +: ${cross_cc_ppc64="powerpc-linux-gnu-gcc"} +: ${cross_cc_cflags_ppc64="-m64"} +: ${cross_cc_ppc64le="powerpc64le-linux-gnu-gcc"} +: ${cross_cc_cflags_s390x="-m64"} +: ${cross_cc_cflags_sparc="-m32 -mv8plus -mcpu=ultrasparc"} +: ${cross_cc_cflags_sparc64="-m64 -mcpu=ultrasparc"} + +for target in $target_list; do + arch=${target%%-*} + case $arch in + arm|armeb) + arches=arm + ;; + aarch64|aarch64_be) + arches="aarch64 arm" + ;; + mips*) + arches=mips + ;; + ppc*) + arches=ppc + ;; + sh4|sh4eb) + arches=sh4 + ;; + x86_64) + arches="x86_64 i386" + ;; + xtensa|xtensaeb) + arches=xtensa + ;; + alpha|cris|hppa|i386|lm32|m68k|openrisc|riscv64|s390x|sh4|sparc64) + arches=$target + ;; + *) + continue + ;; + esac + + container_image= + case $target in + aarch64-*) + # We don't have any bigendian build tools so we only use this for AArch64 + container_image=debian-arm64-cross + container_cross_cc=aarch64-linux-gnu-gcc + ;; + alpha-*) + container_image=debian-alpha-cross + container_cross_cc=alpha-linux-gnu-gcc + ;; + arm-*) + # We don't have any bigendian build tools so we only use this for ARM + container_image=debian-armhf-cross + container_cross_cc=arm-linux-gnueabihf-gcc + ;; + cris-*) + container_image=fedora-cris-cross + container_cross_cc=cris-linux-gnu-gcc + ;; + hppa-*) + container_image=debian-hppa-cross + container_cross_cc=hppa-linux-gnu-gcc + ;; + i386-*) + container_image=fedora-i386-cross + container_cross_cc=gcc + ;; + m68k-*) + container_image=debian-m68k-cross + container_cross_cc=m68k-linux-gnu-gcc + ;; + mips64el-*) + container_image=debian-mips64el-cross + container_cross_cc=mips64el-linux-gnuabi64-gcc + ;; + mips64-*) + container_image=debian-mips64-cross + container_cross_cc=mips64-linux-gnuabi64-gcc + ;; + mipsel-*) + container_image=debian-mipsel-cross + container_cross_cc=mipsel-linux-gnu-gcc + ;; + mips-*) + container_image=debian-mips-cross + container_cross_cc=mips-linux-gnu-gcc + ;; + ppc-*|ppc64abi32-*) + container_image=debian-powerpc-cross + container_cross_cc=powerpc-linux-gnu-gcc + ;; + ppc64-*) + container_image=debian-ppc64-cross + container_cross_cc=powerpc64-linux-gnu-gcc + ;; + ppc64le-*) + container_image=debian-ppc64el-cross + container_cross_cc=powerpc64le-linux-gnu-gcc + ;; + riscv64-*) + container_image=debian-riscv64-cross + container_cross_cc=riscv64-linux-gnu-gcc + ;; + s390x-*) + container_image=debian-s390x-cross + container_cross_cc=s390x-linux-gnu-gcc + ;; + sh4-*) + container_image=debian-sh4-cross + container_cross_cc=sh4-linux-gnu-gcc + ;; + sparc64-*) + container_image=debian-sparc64-cross + container_cross_cc=sparc64-linux-gnu-gcc + ;; + xtensa*-softmmu) + container_image=debian-xtensa-cross + + # default to the dc232b cpu + container_cross_cc=/opt/2018.02/xtensa-dc232b-elf/bin/xtensa-dc232b-elf-gcc + ;; + esac + + config_target_mak=tests/tcg/config-$target.mak + + echo "# Automatically generated by configure - do not modify" > $config_target_mak + echo "TARGET_NAME=$arch" >> $config_target_mak + case $target in + *-linux-user | *-bsd-user) + echo "CONFIG_USER_ONLY=y" >> $config_target_mak + echo "QEMU=\$(BUILD_DIR)/$target/qemu-$arch" >> $config_target_mak + ;; + *-softmmu) + echo "CONFIG_SOFTMMU=y" >> $config_target_mak + echo "QEMU=\$(BUILD_DIR)/$target/qemu-system-$arch" >> $config_target_mak + ;; + esac + + eval "target_compiler_cflags=\${cross_cc_cflags_$arch}" + echo "CROSS_CC_GUEST_CFLAGS=$target_compiler_cflags" >> $config_target_mak + + got_cross_cc=no + for i in $arch $arches; do + if eval test "x\${cross_cc_$i+yes}" != xyes; then + continue + fi + + eval "target_compiler=\${cross_cc_$i}" + if ! has $target_compiler; then + continue + fi + write_c_skeleton + if ! do_compiler "$target_compiler" $target_compiler_cflags -o $TMPE $TMPC -static ; then + # For host systems we might get away with building without -static + if ! do_compiler "$target_compiler" $target_compiler_cflags -o $TMPE $TMPC ; then + continue + fi + echo "CROSS_CC_GUEST_STATIC=y" >> $config_target_mak + else + echo "CROSS_CC_GUEST_STATIC=y" >> $config_target_mak + fi + echo "CROSS_CC_GUEST=$target_compiler" >> $config_target_mak + enabled_cross_compilers="$enabled_cross_compilers $target_compiler" + got_cross_cc=yes + break + done + + if test $got_cross_cc = no && test "$container" != no && test -n "$container_image"; then + echo "DOCKER_IMAGE=$container_image" >> $config_target_mak + echo "DOCKER_CROSS_CC_GUEST=$container_cross_cc" >> $config_target_mak + fi +done + +# report container support state +echo "cross containers $container" + +if test -n "$enabled_cross_compilers"; then + echo + echo "NOTE: guest cross-compilers enabled:$enabled_cross_compilers" +fi diff --git a/tests/tcg/cris/Makefile.include b/tests/tcg/cris/Makefile.include deleted file mode 100644 index 1c037824bf..0000000000 --- a/tests/tcg/cris/Makefile.include +++ /dev/null @@ -1,6 +0,0 @@ -# -# Makefile.include for all CRIS targets -# - -DOCKER_IMAGE=fedora-cris-cross -DOCKER_CROSS_COMPILER=cris-linux-gnu-gcc diff --git a/tests/tcg/hppa/Makefile.include b/tests/tcg/hppa/Makefile.include deleted file mode 100644 index da2353430e..0000000000 --- a/tests/tcg/hppa/Makefile.include +++ /dev/null @@ -1,2 +0,0 @@ -DOCKER_IMAGE=debian-hppa-cross -DOCKER_CROSS_COMPILER=hppa-linux-gnu-gcc diff --git a/tests/tcg/i386/Makefile.include b/tests/tcg/i386/Makefile.include deleted file mode 100644 index be1c3008dd..0000000000 --- a/tests/tcg/i386/Makefile.include +++ /dev/null @@ -1,9 +0,0 @@ -# -# Makefile.include for all i386 -# -# There is enough brokeness in x86_64 compilers that we don't default -# to using the x86_64 system compiler for i386 binaries. -# - -DOCKER_IMAGE=fedora-i386-cross -DOCKER_CROSS_COMPILER=gcc diff --git a/tests/tcg/i386/Makefile.softmmu-target b/tests/tcg/i386/Makefile.softmmu-target index 0a4364868c..1c8790eecd 100644 --- a/tests/tcg/i386/Makefile.softmmu-target +++ b/tests/tcg/i386/Makefile.softmmu-target @@ -12,17 +12,9 @@ X64_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/x86_64/system # These objects provide the basic boot code and helper functions for all tests CRT_OBJS=boot.o -ifeq ($(TARGET_X86_64), y) -CRT_PATH=$(X64_SYSTEM_SRC) -CFLAGS=-march=x86-64 -LINK_SCRIPT=$(X64_SYSTEM_SRC)/kernel.ld -LDFLAGS=-Wl,-T$(LINK_SCRIPT) -Wl,-melf_x86_64 -else CRT_PATH=$(I386_SYSTEM_SRC) -CFLAGS+=-m32 LINK_SCRIPT=$(I386_SYSTEM_SRC)/kernel.ld LDFLAGS=-Wl,-T$(LINK_SCRIPT) -Wl,-melf_i386 -endif CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc @@ -32,11 +24,11 @@ TESTS+=$(MULTIARCH_TESTS) .PRECIOUS: $(CRT_OBJS) %.o: $(CRT_PATH)/%.S - $(CC) $(CFLAGS) -c $< -o $@ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ # Build and link the tests %: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) - $(CC) $(CFLAGS) $< -o $@ $(LDFLAGS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) memory: CFLAGS+=-DCHECK_UNALIGNED=1 diff --git a/tests/tcg/i386/Makefile.target b/tests/tcg/i386/Makefile.target index d0eb7023e5..08c5736a4d 100644 --- a/tests/tcg/i386/Makefile.target +++ b/tests/tcg/i386/Makefile.target @@ -6,14 +6,11 @@ I386_SRC=$(SRC_PATH)/tests/tcg/i386 VPATH += $(I386_SRC) I386_SRCS=$(notdir $(wildcard $(I386_SRC)/*.c)) -I386_TESTS=$(I386_SRCS:.c=) -I386_ONLY_TESTS=$(filter-out test-i386-ssse3, $(I386_TESTS)) +ALL_X86_TESTS=$(I386_SRCS:.c=) +I386_TESTS:=$(filter-out test-i386-ssse3, $(ALL_X86_TESTS)) +X86_64_TESTS:=$(filter test-i386-ssse3, $(ALL_X86_TESTS)) # Update TESTS -TESTS+=$(I386_ONLY_TESTS) - -ifneq ($(TARGET_NAME),x86_64) -CFLAGS+=-m32 -endif +TESTS=$(MULTIARCH_TESTS) $(I386_TESTS) # # hello-i386 is a barebones app @@ -26,7 +23,7 @@ hello-i386: LDFLAGS+=-nostdlib # test-i386: test-i386.c test-i386-code16.S test-i386-vm86.S test-i386.h test-i386-shift.h test-i386-muldiv.h - $(CC) $(CFLAGS) $(LDFLAGS) -o $@ \ + $(CC) $(CFLAGS) $(LDFLAGS) $(EXTRA_CFLAGS) -o $@ \ $(<D)/test-i386.c $(<D)/test-i386-code16.S $(<D)/test-i386-vm86.S -lm ifeq ($(SPEED), slow) diff --git a/tests/tcg/m68k/Makefile.include b/tests/tcg/m68k/Makefile.include deleted file mode 100644 index cd7c6bf50d..0000000000 --- a/tests/tcg/m68k/Makefile.include +++ /dev/null @@ -1,2 +0,0 @@ -DOCKER_IMAGE=debian-m68k-cross -DOCKER_CROSS_COMPILER=m68k-linux-gnu-gcc diff --git a/tests/tcg/minilib/Makefile.target b/tests/tcg/minilib/Makefile.target index 3ed8077d0f..c821d2806a 100644 --- a/tests/tcg/minilib/Makefile.target +++ b/tests/tcg/minilib/Makefile.target @@ -18,4 +18,4 @@ MINILIB_INC=-isystem $(SYSTEM_MINILIB_SRC) .PRECIOUS: $(MINILIB_OBJS) %.o: $(SYSTEM_MINILIB_SRC)/%.c - $(CC) $(CFLAGS) -c $< -o $@ + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ diff --git a/tests/tcg/mips/Makefile.include b/tests/tcg/mips/Makefile.include deleted file mode 100644 index 4a14fc078d..0000000000 --- a/tests/tcg/mips/Makefile.include +++ /dev/null @@ -1,20 +0,0 @@ -# -# Makefile.include for all MIPs targets -# -# As Debian doesn't support mip64 in big endian mode the only way to -# build BE is to pass a working cross compiler to ./configure -# - -ifeq ($(TARGET_NAME),mips64el) -DOCKER_IMAGE=debian-mips64el-cross -DOCKER_CROSS_COMPILER=mips64el-linux-gnuabi64-gcc -else ifeq ($(TARGET_NAME),mips64) -DOCKER_IMAGE=debian-mips64-cross -DOCKER_CROSS_COMPILER=mips64-linux-gnuabi64-gcc -else ifeq ($(TARGET_NAME),mipsel) -DOCKER_IMAGE=debian-mipsel-cross -DOCKER_CROSS_COMPILER=mipsel-linux-gnu-gcc -else ifeq ($(TARGET_NAME),mips) -DOCKER_IMAGE=debian-mips-cross -DOCKER_CROSS_COMPILER=mips-linux-gnu-gcc -endif diff --git a/tests/tcg/multiarch/Makefile.target b/tests/tcg/multiarch/Makefile.target index b77084c146..6b1e30e2fe 100644 --- a/tests/tcg/multiarch/Makefile.target +++ b/tests/tcg/multiarch/Makefile.target @@ -12,8 +12,13 @@ VPATH += $(MULTIARCH_SRC) MULTIARCH_SRCS =$(notdir $(wildcard $(MULTIARCH_SRC)/*.c)) MULTIARCH_TESTS =$(MULTIARCH_SRCS:.c=) +# FIXME: ppc64abi32 linux-test seems to have issues but the other basic tests work +ifeq ($(TARGET_NAME),ppc64abi32) +BROKEN_TESTS = linux-test +endif + # Update TESTS -TESTS +=$(MULTIARCH_TESTS) +TESTS += $(filter-out $(BROKEN_TESTS), $(MULTIARCH_TESTS)) # # The following are any additional rules needed to build things diff --git a/tests/tcg/ppc/Makefile.include b/tests/tcg/ppc/Makefile.include deleted file mode 100644 index ae01fb8fad..0000000000 --- a/tests/tcg/ppc/Makefile.include +++ /dev/null @@ -1,10 +0,0 @@ -ifeq ($(TARGET_NAME),ppc) -DOCKER_IMAGE=debian-powerpc-cross -DOCKER_CROSS_COMPILER=powerpc-linux-gnu-gcc -else ifeq ($(TARGET_NAME),ppc64) -DOCKER_IMAGE=debian-ppc64-cross -DOCKER_CROSS_COMPILER=powerpc64-linux-gnu-gcc -else ifeq ($(TARGET_NAME),ppc64le) -DOCKER_IMAGE=debian-ppc64el-cross -DOCKER_CROSS_COMPILER=powerpc64le-linux-gnu-gcc -endif diff --git a/tests/tcg/riscv/Makefile.include b/tests/tcg/riscv/Makefile.include deleted file mode 100644 index d92ac6c89f..0000000000 --- a/tests/tcg/riscv/Makefile.include +++ /dev/null @@ -1,10 +0,0 @@ -# -# Makefile.include for all RISCV targets -# -# Debian only really cares about 64 bit going forward -# - -ifeq ($(TARGET_NAME),riscv64) -DOCKER_IMAGE=debian-riscv64-cross -DOCKER_CROSS_COMPILER=riscv64-linux-gnu-gcc -endif diff --git a/tests/tcg/s390x/Makefile.include b/tests/tcg/s390x/Makefile.include deleted file mode 100644 index 1f58115d96..0000000000 --- a/tests/tcg/s390x/Makefile.include +++ /dev/null @@ -1,2 +0,0 @@ -DOCKER_IMAGE=debian-s390x-cross -DOCKER_CROSS_COMPILER=s390x-linux-gnu-gcc diff --git a/tests/tcg/sh4/Makefile.include b/tests/tcg/sh4/Makefile.include deleted file mode 100644 index ad21594d9d..0000000000 --- a/tests/tcg/sh4/Makefile.include +++ /dev/null @@ -1,4 +0,0 @@ -ifneq ($(TARGET_NAME), sh4eb) -DOCKER_IMAGE=debian-sh4-cross -DOCKER_CROSS_COMPILER=sh4-linux-gnu-gcc -endif diff --git a/tests/tcg/sparc64/Makefile.include b/tests/tcg/sparc64/Makefile.include deleted file mode 100644 index 95fc8dee9f..0000000000 --- a/tests/tcg/sparc64/Makefile.include +++ /dev/null @@ -1,2 +0,0 @@ -DOCKER_IMAGE=debian-sparc64-cross -DOCKER_CROSS_COMPILER=sparc64-linux-gnu-gcc diff --git a/tests/tcg/x86_64/Makefile.softmmu-target b/tests/tcg/x86_64/Makefile.softmmu-target new file mode 100644 index 0000000000..df252e761c --- /dev/null +++ b/tests/tcg/x86_64/Makefile.softmmu-target @@ -0,0 +1,36 @@ +# +# x86 system tests +# +# This currently builds only for i386. The common C code is built +# with standard compiler flags however so we can support both by +# adding additional boot files for x86_64. +# + +I386_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/i386/system +X64_SYSTEM_SRC=$(SRC_PATH)/tests/tcg/x86_64/system + +# These objects provide the basic boot code and helper functions for all tests +CRT_OBJS=boot.o + +CRT_PATH=$(X64_SYSTEM_SRC) +LINK_SCRIPT=$(X64_SYSTEM_SRC)/kernel.ld +LDFLAGS=-Wl,-T$(LINK_SCRIPT) -Wl,-melf_x86_64 +CFLAGS+=-nostdlib -ggdb -O0 $(MINILIB_INC) +LDFLAGS+=-static -nostdlib $(CRT_OBJS) $(MINILIB_OBJS) -lgcc + +TESTS+=$(MULTIARCH_TESTS) + +# building head blobs +.PRECIOUS: $(CRT_OBJS) + +%.o: $(CRT_PATH)/%.S + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ + +# Build and link the tests +%: %.c $(LINK_SCRIPT) $(CRT_OBJS) $(MINILIB_OBJS) + $(CC) $(CFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) + +memory: CFLAGS+=-DCHECK_UNALIGNED=1 + +# Running +QEMU_OPTS+=-device isa-debugcon,chardev=output -device isa-debug-exit,iobase=0xf4,iosize=0x4 -kernel diff --git a/tests/tcg/x86_64/Makefile.target b/tests/tcg/x86_64/Makefile.target index 74f170b9ed..20bf96202a 100644 --- a/tests/tcg/x86_64/Makefile.target +++ b/tests/tcg/x86_64/Makefile.target @@ -6,9 +6,10 @@ # $(SRC)/tests/tcg/i386/ # -X86_64_TESTS=$(filter-out $(I386_ONLY_TESTS), $(TESTS)) -X86_64_TESTS+=test-x86_64 -TESTS:=$(X86_64_TESTS) +include $(SRC_PATH)/tests/tcg/i386/Makefile.target + +TESTS=$(MULTIARCH_TESTS) $(X86_64_TESTS) test-x86_64 +QEMU_OPTS += -cpu max test-x86_64: LDFLAGS+=-lm -lc test-x86_64: test-i386.c test-i386.h test-i386-shift.h test-i386-muldiv.h diff --git a/tests/tcg/xtensa/Makefile.include b/tests/tcg/xtensa/Makefile.include deleted file mode 100644 index 423c00a5d3..0000000000 --- a/tests/tcg/xtensa/Makefile.include +++ /dev/null @@ -1,11 +0,0 @@ -# Makefile.include for xtensa targets -# -# The compilers can only be used for building system tests - -ifeq ($(CONFIG_SOFTMMU),y) -DOCKER_IMAGE=debian-xtensa-cross - -# default to the dc232b cpu -DOCKER_CROSS_COMPILER=/opt/2018.02/xtensa-dc232b-elf/bin/xtensa-dc232b-elf-gcc -DOCKER_CROSS_LINKER=/opt/2018.02/xtensa-dc232b-elf/bin/xtensa-dc232b-elf-ld -endif diff --git a/tests/tcg/xtensa/Makefile.softmmu-target b/tests/tcg/xtensa/Makefile.softmmu-target index 8212d96b81..9530cac2ad 100644 --- a/tests/tcg/xtensa/Makefile.softmmu-target +++ b/tests/tcg/xtensa/Makefile.softmmu-target @@ -34,9 +34,9 @@ $(XTENSA_USABLE_TESTS): linker.ld macros.inc $(CRT) Makefile.softmmu-target # special rule for common blobs %.o: %.S - $(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) -c $< -o $@ + $(CC) $(XTENSA_INC) $($*_ASFLAGS) $(ASFLAGS) $(EXTRA_CFLAGS) -c $< -o $@ %: %.S - $(CC) $(XTENSA_INC) $(ASFLAGS) $< -o $@ $(LDFLAGS) $(NOSTDFLAGS) $(CRT) + $(CC) $(XTENSA_INC) $(ASFLAGS) $(EXTRA_CFLAGS) $< -o $@ $(LDFLAGS) $(NOSTDFLAGS) $(CRT) endif diff --git a/tests/test-bdrv-drain.c b/tests/test-bdrv-drain.c index 374bef6bb2..fa0e6a648b 100644 --- a/tests/test-bdrv-drain.c +++ b/tests/test-bdrv-drain.c @@ -848,7 +848,6 @@ BlockJobDriver test_job_driver = { .instance_size = sizeof(TestBlockJob), .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = test_job_run, .complete = test_job_complete, .prepare = test_job_prepare, @@ -1574,7 +1573,6 @@ static const BlockJobDriver test_drop_backing_job_driver = { .instance_size = sizeof(TestDropBackingBlockJob), .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = test_drop_backing_job_run, .commit = test_drop_backing_job_commit, } @@ -1711,7 +1709,6 @@ static const BlockJobDriver test_simple_job_driver = { .instance_size = sizeof(TestSimpleBlockJob), .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = test_simple_job_run, .clean = test_simple_job_clean, }, diff --git a/tests/test-block-iothread.c b/tests/test-block-iothread.c index 926577b1f9..cfe30bab21 100644 --- a/tests/test-block-iothread.c +++ b/tests/test-block-iothread.c @@ -401,7 +401,6 @@ BlockJobDriver test_job_driver = { .instance_size = sizeof(TestBlockJob), .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = test_job_run, .complete = test_job_complete, .prepare = test_job_prepare, diff --git a/tests/test-blockjob-txn.c b/tests/test-blockjob-txn.c index 7da9216d5b..8bd13b9949 100644 --- a/tests/test-blockjob-txn.c +++ b/tests/test-blockjob-txn.c @@ -72,7 +72,6 @@ static const BlockJobDriver test_block_job_driver = { .instance_size = sizeof(TestBlockJob), .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = test_block_job_run, .clean = test_block_job_clean, }, diff --git a/tests/test-blockjob.c b/tests/test-blockjob.c index 68a0819495..7844c9ffcb 100644 --- a/tests/test-blockjob.c +++ b/tests/test-blockjob.c @@ -22,7 +22,6 @@ static const BlockJobDriver test_block_job_driver = { .instance_size = sizeof(BlockJob), .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, }, }; @@ -196,7 +195,6 @@ static const BlockJobDriver test_cancel_driver = { .instance_size = sizeof(CancelJob), .free = block_job_free, .user_resume = block_job_user_resume, - .drain = block_job_drain, .run = cancel_job_run, .complete = cancel_job_complete, }, diff --git a/tests/test-char.c b/tests/test-char.c index f3ebdffd87..d62de1b088 100644 --- a/tests/test-char.c +++ b/tests/test-char.c @@ -1355,6 +1355,18 @@ static void char_hotswap_test(void) g_free(chr_args); } +static SocketAddress tcpaddr = { + .type = SOCKET_ADDRESS_TYPE_INET, + .u.inet.host = (char *)"127.0.0.1", + .u.inet.port = (char *)"0", +}; +#ifndef WIN32 +static SocketAddress unixaddr = { + .type = SOCKET_ADDRESS_TYPE_UNIX, + .u.q_unix.path = (char *)"test-char.sock", +}; +#endif + int main(int argc, char **argv) { bool has_ipv4, has_ipv6; @@ -1390,26 +1402,14 @@ int main(int argc, char **argv) g_test_add_func("/char/file-fifo", char_file_fifo_test); #endif - SocketAddress tcpaddr = { - .type = SOCKET_ADDRESS_TYPE_INET, - .u.inet.host = (char *)"127.0.0.1", - .u.inet.port = (char *)"0", - }; -#ifndef WIN32 - SocketAddress unixaddr = { - .type = SOCKET_ADDRESS_TYPE_UNIX, - .u.q_unix.path = (char *)"test-char.sock", - }; -#endif - #define SOCKET_SERVER_TEST(name, addr) \ - CharSocketServerTestConfig server1 ## name = \ + static CharSocketServerTestConfig server1 ## name = \ { addr, false, false }; \ - CharSocketServerTestConfig server2 ## name = \ + static CharSocketServerTestConfig server2 ## name = \ { addr, true, false }; \ - CharSocketServerTestConfig server3 ## name = \ + static CharSocketServerTestConfig server3 ## name = \ { addr, false, true }; \ - CharSocketServerTestConfig server4 ## name = \ + static CharSocketServerTestConfig server4 ## name = \ { addr, true, true }; \ g_test_add_data_func("/char/socket/server/mainloop/" # name, \ &server1 ##name, char_socket_server_test); \ @@ -1421,17 +1421,17 @@ int main(int argc, char **argv) &server4 ##name, char_socket_server_test) #define SOCKET_CLIENT_TEST(name, addr) \ - CharSocketClientTestConfig client1 ## name = \ + static CharSocketClientTestConfig client1 ## name = \ { addr, NULL, false, false }; \ - CharSocketClientTestConfig client2 ## name = \ + static CharSocketClientTestConfig client2 ## name = \ { addr, NULL, true, false }; \ - CharSocketClientTestConfig client3 ## name = \ + static CharSocketClientTestConfig client3 ## name = \ { addr, ",reconnect=1", false }; \ - CharSocketClientTestConfig client4 ## name = \ + static CharSocketClientTestConfig client4 ## name = \ { addr, ",reconnect=1", true }; \ - CharSocketClientTestConfig client5 ## name = \ + static CharSocketClientTestConfig client5 ## name = \ { addr, NULL, false, true }; \ - CharSocketClientTestConfig client6 ## name = \ + static CharSocketClientTestConfig client6 ## name = \ { addr, NULL, true, true }; \ g_test_add_data_func("/char/socket/client/mainloop/" # name, \ &client1 ##name, char_socket_client_test); \ diff --git a/tests/test-util-filemonitor.c b/tests/test-util-filemonitor.c index 46e781c022..301cd2db61 100644 --- a/tests/test-util-filemonitor.c +++ b/tests/test-util-filemonitor.c @@ -45,6 +45,11 @@ typedef struct { const char *filedst; int64_t *watchid; int eventid; + /* + * Only valid with OP_EVENT - this event might be + * swapped with the next OP_EVENT + */ + bool swapnext; } QFileMonitorTestOp; typedef struct { @@ -98,6 +103,10 @@ qemu_file_monitor_test_handler(int64_t id, QFileMonitorTestData *data = opaque; QFileMonitorTestRecord *rec = g_new0(QFileMonitorTestRecord, 1); + if (debug) { + g_printerr("Queue event id %" PRIx64 " event %d file %s\n", + id, event, filename); + } rec->id = id; rec->event = event; rec->filename = g_strdup(filename); @@ -125,7 +134,8 @@ qemu_file_monitor_test_record_free(QFileMonitorTestRecord *rec) * to wait for the event to be queued for us. */ static QFileMonitorTestRecord * -qemu_file_monitor_test_next_record(QFileMonitorTestData *data) +qemu_file_monitor_test_next_record(QFileMonitorTestData *data, + QFileMonitorTestRecord *pushback) { GTimer *timer = g_timer_new(); QFileMonitorTestRecord *record = NULL; @@ -139,9 +149,15 @@ qemu_file_monitor_test_next_record(QFileMonitorTestData *data) } if (data->records) { record = data->records->data; - tmp = data->records; - data->records = g_list_remove_link(data->records, tmp); - g_list_free(tmp); + if (pushback) { + data->records->data = pushback; + } else { + tmp = data->records; + data->records = g_list_remove_link(data->records, tmp); + g_list_free(tmp); + } + } else if (pushback) { + qemu_file_monitor_test_record_free(pushback); } qemu_mutex_unlock(&data->lock); @@ -158,13 +174,15 @@ static bool qemu_file_monitor_test_expect(QFileMonitorTestData *data, int64_t id, QFileMonitorEvent event, - const char *filename) + const char *filename, + bool swapnext) { QFileMonitorTestRecord *rec; bool ret = false; - rec = qemu_file_monitor_test_next_record(data); + rec = qemu_file_monitor_test_next_record(data, NULL); + retry: if (!rec) { g_printerr("Missing event watch id %" PRIx64 " event %d file %s\n", id, event, filename); @@ -172,6 +190,11 @@ qemu_file_monitor_test_expect(QFileMonitorTestData *data, } if (id != rec->id) { + if (swapnext) { + rec = qemu_file_monitor_test_next_record(data, rec); + swapnext = false; + goto retry; + } g_printerr("Expected watch id %" PRIx64 " but got %" PRIx64 "\n", id, rec->id); goto cleanup; @@ -347,7 +370,8 @@ test_file_monitor_events(void) .filesrc = "fish", }, { .type = QFILE_MONITOR_TEST_OP_EVENT, .filesrc = "", .watchid = &watch4, - .eventid = QFILE_MONITOR_EVENT_IGNORED }, + .eventid = QFILE_MONITOR_EVENT_IGNORED, + .swapnext = true }, { .type = QFILE_MONITOR_TEST_OP_EVENT, .filesrc = "fish", .watchid = &watch0, .eventid = QFILE_MONITOR_EVENT_DELETED }, @@ -493,8 +517,9 @@ test_file_monitor_events(void) g_printerr("Event id=%" PRIx64 " event=%d file=%s\n", *op->watchid, op->eventid, op->filesrc); } - if (!qemu_file_monitor_test_expect( - &data, *op->watchid, op->eventid, op->filesrc)) + if (!qemu_file_monitor_test_expect(&data, *op->watchid, + op->eventid, op->filesrc, + op->swapnext)) goto cleanup; break; case QFILE_MONITOR_TEST_OP_CREATE: diff --git a/tests/vm/fedora b/tests/vm/fedora index e8fa5bf0d2..7fec1479fb 100755 --- a/tests/vm/fedora +++ b/tests/vm/fedora @@ -23,7 +23,7 @@ class FedoraVM(basevm.BaseVM): name = "fedora" arch = "x86_64" - base = "http://dl.fedoraproject.org/pub/fedora/linux/releases/30/" + base = "https://archives.fedoraproject.org/pub/archive/fedora/linux/releases/30/" link = base + "Server/x86_64/iso/Fedora-Server-netinst-x86_64-30-1.2.iso" repo = base + "Server/x86_64/os/" full = base + "Everything/x86_64/os/" diff --git a/util/memfd.c b/util/memfd.c index 00334e5b21..4a3c07e0be 100644 --- a/util/memfd.c +++ b/util/memfd.c @@ -35,7 +35,7 @@ #include <sys/syscall.h> #include <asm/unistd.h> -static int memfd_create(const char *name, unsigned int flags) +int memfd_create(const char *name, unsigned int flags) { #ifdef __NR_memfd_create return syscall(__NR_memfd_create, name, flags); diff --git a/util/oslib-posix.c b/util/oslib-posix.c index 5fda67dedf..f8693384fc 100644 --- a/util/oslib-posix.c +++ b/util/oslib-posix.c @@ -514,60 +514,6 @@ void os_mem_prealloc(int fd, char *area, size_t memory, int smp_cpus, } } -uint64_t qemu_get_pmem_size(const char *filename, Error **errp) -{ - struct stat st; - - if (stat(filename, &st) < 0) { - error_setg(errp, "unable to stat pmem file \"%s\"", filename); - return 0; - } - -#if defined(__linux__) - /* Special handling for devdax character devices */ - if (S_ISCHR(st.st_mode)) { - char *subsystem_path = NULL; - char *subsystem = NULL; - char *size_path = NULL; - char *size_str = NULL; - uint64_t ret = 0; - - subsystem_path = g_strdup_printf("/sys/dev/char/%d:%d/subsystem", - major(st.st_rdev), minor(st.st_rdev)); - subsystem = g_file_read_link(subsystem_path, NULL); - if (!subsystem) { - error_setg(errp, "unable to read subsystem for pmem file \"%s\"", - filename); - goto devdax_err; - } - - if (!g_str_has_suffix(subsystem, "/dax")) { - error_setg(errp, "pmem file \"%s\" is not a dax device", filename); - goto devdax_err; - } - - size_path = g_strdup_printf("/sys/dev/char/%d:%d/size", - major(st.st_rdev), minor(st.st_rdev)); - if (!g_file_get_contents(size_path, &size_str, NULL, NULL)) { - error_setg(errp, "unable to read size for pmem file \"%s\"", - size_path); - goto devdax_err; - } - - ret = g_ascii_strtoull(size_str, NULL, 0); - -devdax_err: - g_free(size_str); - g_free(size_path); - g_free(subsystem); - g_free(subsystem_path); - return ret; - } -#endif /* defined(__linux__) */ - - return st.st_size; -} - char *qemu_get_pid_name(pid_t pid) { char *name = NULL; diff --git a/util/oslib-win32.c b/util/oslib-win32.c index 9583fb4ca4..c62cd4328c 100644 --- a/util/oslib-win32.c +++ b/util/oslib-win32.c @@ -562,12 +562,6 @@ void os_mem_prealloc(int fd, char *area, size_t memory, int smp_cpus, } } -uint64_t qemu_get_pmem_size(const char *filename, Error **errp) -{ - error_setg(errp, "pmem support not available"); - return 0; -} - char *qemu_get_pid_name(pid_t pid) { /* XXX Implement me */ diff --git a/util/qemu-thread-posix.c b/util/qemu-thread-posix.c index 1bf5e65dea..838980aaa5 100644 --- a/util/qemu-thread-posix.c +++ b/util/qemu-thread-posix.c @@ -36,6 +36,18 @@ static void error_exit(int err, const char *msg) abort(); } +static void compute_abs_deadline(struct timespec *ts, int ms) +{ + struct timeval tv; + gettimeofday(&tv, NULL); + ts->tv_nsec = tv.tv_usec * 1000 + (ms % 1000) * 1000000; + ts->tv_sec = tv.tv_sec + ms / 1000; + if (ts->tv_nsec >= 1000000000) { + ts->tv_sec++; + ts->tv_nsec -= 1000000000; + } +} + void qemu_mutex_init(QemuMutex *mutex) { int err; @@ -164,6 +176,23 @@ void qemu_cond_wait_impl(QemuCond *cond, QemuMutex *mutex, const char *file, con error_exit(err, __func__); } +bool qemu_cond_timedwait_impl(QemuCond *cond, QemuMutex *mutex, int ms, + const char *file, const int line) +{ + int err; + struct timespec ts; + + assert(cond->initialized); + trace_qemu_mutex_unlock(mutex, file, line); + compute_abs_deadline(&ts, ms); + err = pthread_cond_timedwait(&cond->cond, &mutex->lock, &ts); + trace_qemu_mutex_locked(mutex, file, line); + if (err && err != ETIMEDOUT) { + error_exit(err, __func__); + } + return err != ETIMEDOUT; +} + void qemu_sem_init(QemuSemaphore *sem, int init) { int rc; @@ -238,18 +267,6 @@ void qemu_sem_post(QemuSemaphore *sem) #endif } -static void compute_abs_deadline(struct timespec *ts, int ms) -{ - struct timeval tv; - gettimeofday(&tv, NULL); - ts->tv_nsec = tv.tv_usec * 1000 + (ms % 1000) * 1000000; - ts->tv_sec = tv.tv_sec + ms / 1000; - if (ts->tv_nsec >= 1000000000) { - ts->tv_sec++; - ts->tv_nsec -= 1000000000; - } -} - int qemu_sem_timedwait(QemuSemaphore *sem, int ms) { int rc; diff --git a/util/qemu-thread-win32.c b/util/qemu-thread-win32.c index 572f88535d..56a83333da 100644 --- a/util/qemu-thread-win32.c +++ b/util/qemu-thread-win32.c @@ -145,6 +145,23 @@ void qemu_cond_wait_impl(QemuCond *cond, QemuMutex *mutex, const char *file, con qemu_mutex_post_lock(mutex, file, line); } +bool qemu_cond_timedwait_impl(QemuCond *cond, QemuMutex *mutex, int ms, + const char *file, const int line) +{ + int rc = 0; + + assert(cond->initialized); + trace_qemu_mutex_unlock(mutex, file, line); + if (!SleepConditionVariableSRW(&cond->var, &mutex->lock, ms, 0)) { + rc = GetLastError(); + } + trace_qemu_mutex_locked(mutex, file, line); + if (rc && rc != ERROR_TIMEOUT) { + error_exit(rc, __func__); + } + return rc != ERROR_TIMEOUT; +} + void qemu_sem_init(QemuSemaphore *sem, int init) { /* Manual reset. */ diff --git a/util/qsp.c b/util/qsp.c index 5264c97342..62265417fd 100644 --- a/util/qsp.c +++ b/util/qsp.c @@ -131,6 +131,7 @@ QemuRecMutexLockFunc qemu_rec_mutex_lock_func = qemu_rec_mutex_lock_impl; QemuRecMutexTrylockFunc qemu_rec_mutex_trylock_func = qemu_rec_mutex_trylock_impl; QemuCondWaitFunc qemu_cond_wait_func = qemu_cond_wait_impl; +QemuCondTimedWaitFunc qemu_cond_timedwait_func = qemu_cond_timedwait_impl; /* * It pays off to _not_ hash callsite->file; hashing a string is slow, and @@ -412,6 +413,23 @@ qsp_cond_wait(QemuCond *cond, QemuMutex *mutex, const char *file, int line) qsp_entry_record(e, t1 - t0); } +static bool +qsp_cond_timedwait(QemuCond *cond, QemuMutex *mutex, int ms, + const char *file, int line) +{ + QSPEntry *e; + int64_t t0, t1; + bool ret; + + t0 = get_clock(); + ret = qemu_cond_timedwait_impl(cond, mutex, ms, file, line); + t1 = get_clock(); + + e = qsp_entry_get(cond, file, line, QSP_CONDVAR); + qsp_entry_record(e, t1 - t0); + return ret; +} + bool qsp_is_enabled(void) { return atomic_read(&qemu_mutex_lock_func) == qsp_mutex_lock; @@ -425,6 +443,7 @@ void qsp_enable(void) atomic_set(&qemu_rec_mutex_lock_func, qsp_rec_mutex_lock); atomic_set(&qemu_rec_mutex_trylock_func, qsp_rec_mutex_trylock); atomic_set(&qemu_cond_wait_func, qsp_cond_wait); + atomic_set(&qemu_cond_timedwait_func, qsp_cond_timedwait); } void qsp_disable(void) @@ -435,6 +454,7 @@ void qsp_disable(void) atomic_set(&qemu_rec_mutex_lock_func, qemu_rec_mutex_lock_impl); atomic_set(&qemu_rec_mutex_trylock_func, qemu_rec_mutex_trylock_impl); atomic_set(&qemu_cond_wait_func, qemu_cond_wait_impl); + atomic_set(&qemu_cond_timedwait_func, qemu_cond_timedwait_impl); } static gint qsp_tree_cmp(gconstpointer ap, gconstpointer bp, gpointer up) |