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-rw-r--r--hw/intc/arm_gicv3_cpuif.c2
-rw-r--r--hw/intc/armv7m_nvic.c8
-rw-r--r--hw/intc/trace-events2
-rw-r--r--target/i386/cpu.c128
-rw-r--r--target/i386/cpu.h4
-rw-r--r--ui/cocoa.m14
6 files changed, 87 insertions, 71 deletions
diff --git a/hw/intc/arm_gicv3_cpuif.c b/hw/intc/arm_gicv3_cpuif.c
index 5c89be1af0..2a60568d82 100644
--- a/hw/intc/arm_gicv3_cpuif.c
+++ b/hw/intc/arm_gicv3_cpuif.c
@@ -1550,7 +1550,7 @@ static void icc_dir_write(CPUARMState *env, const ARMCPRegInfo *ri,
      * tested in cases where we know !IsSecure is true.
      */
     route_fiq_to_el2 = env->cp15.hcr_el2 & HCR_FMO;
-    route_irq_to_el2 = env->cp15.hcr_el2 & HCR_FMO;
+    route_irq_to_el2 = env->cp15.hcr_el2 & HCR_IMO;
 
     switch (arm_current_el(env)) {
     case 3:
diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c
index 7a5330f201..6be7fc5266 100644
--- a/hw/intc/armv7m_nvic.c
+++ b/hw/intc/armv7m_nvic.c
@@ -525,13 +525,17 @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
     NVICState *s = (NVICState *)opaque;
     bool banked = exc_is_banked(irq);
     VecInfo *vec;
+    bool targets_secure;
 
     assert(irq > ARMV7M_EXCP_RESET && irq < s->num_irq);
     assert(!secure || banked);
 
     vec = (banked && secure) ? &s->sec_vectors[irq] : &s->vectors[irq];
 
-    trace_nvic_set_pending(irq, secure, derived, vec->enabled, vec->prio);
+    targets_secure = banked ? secure : exc_targets_secure(s, irq);
+
+    trace_nvic_set_pending(irq, secure, targets_secure,
+                           derived, vec->enabled, vec->prio);
 
     if (derived) {
         /* Derived exceptions are always synchronous. */
@@ -611,7 +615,7 @@ static void do_armv7m_nvic_set_pending(void *opaque, int irq, bool secure,
              */
             irq = ARMV7M_EXCP_HARD;
             if (arm_feature(&s->cpu->env, ARM_FEATURE_M_SECURITY) &&
-                (secure ||
+                (targets_secure ||
                  !(s->cpu->env.v7m.aircr & R_V7M_AIRCR_BFHFNMINS_MASK))) {
                 vec = &s->sec_vectors[irq];
             } else {
diff --git a/hw/intc/trace-events b/hw/intc/trace-events
index 55e8c2570c..5fb18e65c9 100644
--- a/hw/intc/trace-events
+++ b/hw/intc/trace-events
@@ -177,7 +177,7 @@ nvic_set_prio(int irq, bool secure, uint8_t prio) "NVIC set irq %d secure-bank %
 nvic_irq_update(int vectpending, int pendprio, int exception_prio, int level) "NVIC vectpending %d pending prio %d exception_prio %d: setting irq line to %d"
 nvic_escalate_prio(int irq, int irqprio, int runprio) "NVIC escalating irq %d to HardFault: insufficient priority %d >= %d"
 nvic_escalate_disabled(int irq) "NVIC escalating irq %d to HardFault: disabled"
-nvic_set_pending(int irq, bool secure, bool derived, int en, int prio) "NVIC set pending irq %d secure-bank %d derived %d (enabled: %d priority %d)"
+nvic_set_pending(int irq, bool secure, bool targets_secure, bool derived, int en, int prio) "NVIC set pending irq %d secure-bank %d targets_secure %d derived %d (enabled: %d priority %d)"
 nvic_clear_pending(int irq, bool secure, int en, int prio) "NVIC clear pending irq %d secure-bank %d (enabled: %d priority %d)"
 nvic_set_pending_level(int irq) "NVIC set pending: irq %d higher prio than vectpending: setting irq line to 1"
 nvic_acknowledge_irq(int irq, int prio) "NVIC acknowledge IRQ: %d now active (prio %d)"
diff --git a/target/i386/cpu.c b/target/i386/cpu.c
index e0e2f2eea1..f454d4beb3 100644
--- a/target/i386/cpu.c
+++ b/target/i386/cpu.c
@@ -71,123 +71,123 @@ struct CPUID2CacheDescriptorInfo {
  * From Intel SDM Volume 2A, CPUID instruction
  */
 struct CPUID2CacheDescriptorInfo cpuid2_cache_descriptors[] = {
-    [0x06] = { .level = 1, .type = ICACHE,        .size =   8 * KiB,
+    [0x06] = { .level = 1, .type = INSTRUCTION_CACHE, .size =   8 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x08] = { .level = 1, .type = ICACHE,        .size =  16 * KiB,
+    [0x08] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  16 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x09] = { .level = 1, .type = ICACHE,        .size =  32 * KiB,
+    [0x09] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x0A] = { .level = 1, .type = DCACHE,        .size =   8 * KiB,
+    [0x0A] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
                .associativity = 2,  .line_size = 32, },
-    [0x0C] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
+    [0x0C] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x0D] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
+    [0x0D] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x0E] = { .level = 1, .type = DCACHE,        .size =  24 * KiB,
+    [0x0E] = { .level = 1, .type = DATA_CACHE,        .size =  24 * KiB,
                .associativity = 6,  .line_size = 64, },
-    [0x1D] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
+    [0x1D] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
                .associativity = 2,  .line_size = 64, },
-    [0x21] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
+    [0x21] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
                .associativity = 8,  .line_size = 64, },
     /* lines per sector is not supported cpuid2_cache_descriptor(),
     * so descriptors 0x22, 0x23 are not included
     */
-    [0x24] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x24] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 16, .line_size = 64, },
     /* lines per sector is not supported cpuid2_cache_descriptor(),
     * so descriptors 0x25, 0x20 are not included
     */
-    [0x2C] = { .level = 1, .type = DCACHE,        .size =  32 * KiB,
+    [0x2C] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
                .associativity = 8,  .line_size = 64, },
-    [0x30] = { .level = 1, .type = ICACHE,        .size =  32 * KiB,
+    [0x30] = { .level = 1, .type = INSTRUCTION_CACHE, .size =  32 * KiB,
                .associativity = 8,  .line_size = 64, },
-    [0x41] = { .level = 2, .type = UNIFIED_CACHE, .size = 128 * KiB,
+    [0x41] = { .level = 2, .type = UNIFIED_CACHE,     .size = 128 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x42] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
+    [0x42] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x43] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x43] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 4,  .line_size = 32, },
-    [0x44] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x44] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 4,  .line_size = 32, },
-    [0x45] = { .level = 2, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0x45] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 4,  .line_size = 32, },
-    [0x46] = { .level = 3, .type = UNIFIED_CACHE, .size =   4 * MiB,
+    [0x46] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
                .associativity = 4,  .line_size = 64, },
-    [0x47] = { .level = 3, .type = UNIFIED_CACHE, .size =   8 * MiB,
+    [0x47] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0x48] = { .level = 2, .type = UNIFIED_CACHE, .size =   3 * MiB,
+    [0x48] = { .level = 2, .type = UNIFIED_CACHE,     .size =   3 * MiB,
                .associativity = 12, .line_size = 64, },
     /* Descriptor 0x49 depends on CPU family/model, so it is not included */
-    [0x4A] = { .level = 3, .type = UNIFIED_CACHE, .size =   6 * MiB,
+    [0x4A] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0x4B] = { .level = 3, .type = UNIFIED_CACHE, .size =   8 * MiB,
+    [0x4B] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0x4C] = { .level = 3, .type = UNIFIED_CACHE, .size =  12 * MiB,
+    [0x4C] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0x4D] = { .level = 3, .type = UNIFIED_CACHE, .size =  16 * MiB,
+    [0x4D] = { .level = 3, .type = UNIFIED_CACHE,     .size =  16 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0x4E] = { .level = 2, .type = UNIFIED_CACHE, .size =   6 * MiB,
+    [0x4E] = { .level = 2, .type = UNIFIED_CACHE,     .size =   6 * MiB,
                .associativity = 24, .line_size = 64, },
-    [0x60] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
+    [0x60] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
                .associativity = 8,  .line_size = 64, },
-    [0x66] = { .level = 1, .type = DCACHE,        .size =   8 * KiB,
+    [0x66] = { .level = 1, .type = DATA_CACHE,        .size =   8 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x67] = { .level = 1, .type = DCACHE,        .size =  16 * KiB,
+    [0x67] = { .level = 1, .type = DATA_CACHE,        .size =  16 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x68] = { .level = 1, .type = DCACHE,        .size =  32 * KiB,
+    [0x68] = { .level = 1, .type = DATA_CACHE,        .size =  32 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x78] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x78] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 4,  .line_size = 64, },
     /* lines per sector is not supported cpuid2_cache_descriptor(),
     * so descriptors 0x79, 0x7A, 0x7B, 0x7C are not included.
     */
-    [0x7D] = { .level = 2, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0x7D] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0x7F] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x7F] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 2,  .line_size = 64, },
-    [0x80] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x80] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 8,  .line_size = 64, },
-    [0x82] = { .level = 2, .type = UNIFIED_CACHE, .size = 256 * KiB,
+    [0x82] = { .level = 2, .type = UNIFIED_CACHE,     .size = 256 * KiB,
                .associativity = 8,  .line_size = 32, },
-    [0x83] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x83] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 8,  .line_size = 32, },
-    [0x84] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x84] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 8,  .line_size = 32, },
-    [0x85] = { .level = 2, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0x85] = { .level = 2, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 8,  .line_size = 32, },
-    [0x86] = { .level = 2, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0x86] = { .level = 2, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0x87] = { .level = 2, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0x87] = { .level = 2, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0xD0] = { .level = 3, .type = UNIFIED_CACHE, .size = 512 * KiB,
+    [0xD0] = { .level = 3, .type = UNIFIED_CACHE,     .size = 512 * KiB,
                .associativity = 4,  .line_size = 64, },
-    [0xD1] = { .level = 3, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0xD1] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 4,  .line_size = 64, },
-    [0xD2] = { .level = 3, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0xD2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 4,  .line_size = 64, },
-    [0xD6] = { .level = 3, .type = UNIFIED_CACHE, .size =   1 * MiB,
+    [0xD6] = { .level = 3, .type = UNIFIED_CACHE,     .size =   1 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0xD7] = { .level = 3, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0xD7] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0xD8] = { .level = 3, .type = UNIFIED_CACHE, .size =   4 * MiB,
+    [0xD8] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
                .associativity = 8,  .line_size = 64, },
-    [0xDC] = { .level = 3, .type = UNIFIED_CACHE, .size = 1.5 * MiB,
+    [0xDC] = { .level = 3, .type = UNIFIED_CACHE,     .size = 1.5 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0xDD] = { .level = 3, .type = UNIFIED_CACHE, .size =   3 * MiB,
+    [0xDD] = { .level = 3, .type = UNIFIED_CACHE,     .size =   3 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0xDE] = { .level = 3, .type = UNIFIED_CACHE, .size =   6 * MiB,
+    [0xDE] = { .level = 3, .type = UNIFIED_CACHE,     .size =   6 * MiB,
                .associativity = 12, .line_size = 64, },
-    [0xE2] = { .level = 3, .type = UNIFIED_CACHE, .size =   2 * MiB,
+    [0xE2] = { .level = 3, .type = UNIFIED_CACHE,     .size =   2 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0xE3] = { .level = 3, .type = UNIFIED_CACHE, .size =   4 * MiB,
+    [0xE3] = { .level = 3, .type = UNIFIED_CACHE,     .size =   4 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0xE4] = { .level = 3, .type = UNIFIED_CACHE, .size =   8 * MiB,
+    [0xE4] = { .level = 3, .type = UNIFIED_CACHE,     .size =   8 * MiB,
                .associativity = 16, .line_size = 64, },
-    [0xEA] = { .level = 3, .type = UNIFIED_CACHE, .size =  12 * MiB,
+    [0xEA] = { .level = 3, .type = UNIFIED_CACHE,     .size =  12 * MiB,
                .associativity = 24, .line_size = 64, },
-    [0xEB] = { .level = 3, .type = UNIFIED_CACHE, .size =  18 * MiB,
+    [0xEB] = { .level = 3, .type = UNIFIED_CACHE,     .size =  18 * MiB,
                .associativity = 24, .line_size = 64, },
-    [0xEC] = { .level = 3, .type = UNIFIED_CACHE, .size =  24 * MiB,
+    [0xEC] = { .level = 3, .type = UNIFIED_CACHE,     .size =  24 * MiB,
                .associativity = 24, .line_size = 64, },
 };
 
@@ -238,10 +238,10 @@ static uint8_t cpuid2_cache_descriptor(CPUCacheInfo *cache)
 #define CACHE_COMPLEX_IDX     (1 << 2)
 
 /* Encode CacheType for CPUID[4].EAX */
-#define CACHE_TYPE(t) (((t) == DCACHE)  ? CACHE_TYPE_D  : \
-                         ((t) == ICACHE)  ? CACHE_TYPE_I  : \
-                         ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
-                         0 /* Invalid value */)
+#define CACHE_TYPE(t) (((t) == DATA_CACHE) ? CACHE_TYPE_D : \
+                       ((t) == INSTRUCTION_CACHE) ? CACHE_TYPE_I : \
+                       ((t) == UNIFIED_CACHE) ? CACHE_TYPE_UNIFIED : \
+                       0 /* Invalid value */)
 
 
 /* Encode cache info for CPUID[4] */
@@ -538,7 +538,7 @@ static void encode_topo_cpuid8000001e(CPUState *cs, X86CPU *cpu,
 
 /* L1 data cache: */
 static CPUCacheInfo legacy_l1d_cache = {
-    .type = DCACHE,
+    .type = DATA_CACHE,
     .level = 1,
     .size = 32 * KiB,
     .self_init = 1,
@@ -551,7 +551,7 @@ static CPUCacheInfo legacy_l1d_cache = {
 
 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 static CPUCacheInfo legacy_l1d_cache_amd = {
-    .type = DCACHE,
+    .type = DATA_CACHE,
     .level = 1,
     .size = 64 * KiB,
     .self_init = 1,
@@ -565,7 +565,7 @@ static CPUCacheInfo legacy_l1d_cache_amd = {
 
 /* L1 instruction cache: */
 static CPUCacheInfo legacy_l1i_cache = {
-    .type = ICACHE,
+    .type = INSTRUCTION_CACHE,
     .level = 1,
     .size = 32 * KiB,
     .self_init = 1,
@@ -578,7 +578,7 @@ static CPUCacheInfo legacy_l1i_cache = {
 
 /*FIXME: CPUID leaf 0x80000005 is inconsistent with leaves 2 & 4 */
 static CPUCacheInfo legacy_l1i_cache_amd = {
-    .type = ICACHE,
+    .type = INSTRUCTION_CACHE,
     .level = 1,
     .size = 64 * KiB,
     .self_init = 1,
@@ -1310,7 +1310,7 @@ struct X86CPUDefinition {
 
 static CPUCaches epyc_cache_info = {
     .l1d_cache = &(CPUCacheInfo) {
-        .type = DCACHE,
+        .type = DATA_CACHE,
         .level = 1,
         .size = 32 * KiB,
         .line_size = 64,
@@ -1322,7 +1322,7 @@ static CPUCaches epyc_cache_info = {
         .no_invd_sharing = true,
     },
     .l1i_cache = &(CPUCacheInfo) {
-        .type = ICACHE,
+        .type = INSTRUCTION_CACHE,
         .level = 1,
         .size = 64 * KiB,
         .line_size = 64,
diff --git a/target/i386/cpu.h b/target/i386/cpu.h
index 2c5a0d90a6..194e2e6b92 100644
--- a/target/i386/cpu.h
+++ b/target/i386/cpu.h
@@ -1050,8 +1050,8 @@ typedef enum TPRAccess {
 /* Cache information data structures: */
 
 enum CacheType {
-    DCACHE,
-    ICACHE,
+    DATA_CACHE,
+    INSTRUCTION_CACHE,
     UNIFIED_CACHE
 };
 
diff --git a/ui/cocoa.m b/ui/cocoa.m
index cfc70e21a4..ecf12bfc2e 100644
--- a/ui/cocoa.m
+++ b/ui/cocoa.m
@@ -637,6 +637,7 @@ QemuCocoaView *cocoaView;
     int buttons = 0;
     int keycode = 0;
     bool mouse_event = false;
+    static bool switched_to_fullscreen = false;
     NSPoint p = [event locationInWindow];
 
     switch ([event type]) {
@@ -681,7 +682,11 @@ QemuCocoaView *cocoaView;
                     keycode == Q_KEY_CODE_NUM_LOCK) {
                     [self toggleStatefulModifier:keycode];
                 } else if (qemu_console_is_graphic(NULL)) {
-                  [self toggleModifier:keycode];
+                    if (switched_to_fullscreen) {
+                        switched_to_fullscreen = false;
+                    } else {
+                        [self toggleModifier:keycode];
+                    }
                 }
             }
 
@@ -691,6 +696,13 @@ QemuCocoaView *cocoaView;
 
             // forward command key combos to the host UI unless the mouse is grabbed
             if (!isMouseGrabbed && ([event modifierFlags] & NSEventModifierFlagCommand)) {
+                /*
+                 * Prevent the command key from being stuck down in the guest
+                 * when using Command-F to switch to full screen mode.
+                 */
+                if (keycode == Q_KEY_CODE_F) {
+                    switched_to_fullscreen = true;
+                }
                 [NSApp sendEvent:event];
                 return;
             }