diff options
| -rw-r--r-- | target/riscv/cpu.c | 45 |
1 files changed, 29 insertions, 16 deletions
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c index 6b5878c603..08fc24c3f4 100644 --- a/target/riscv/cpu.c +++ b/target/riscv/cpu.c @@ -605,22 +605,6 @@ static void rv64i_bare_cpu_init(Object *obj) { CPURISCVState *env = &RISCV_CPU(obj)->env; riscv_cpu_set_misa_ext(env, RVI); - - /* Remove the defaults from the parent class */ - RISCV_CPU(obj)->cfg.ext_zicntr = false; - RISCV_CPU(obj)->cfg.ext_zihpm = false; - - /* Set to QEMU's first supported priv version */ - env->priv_ver = PRIV_VERSION_1_10_0; - - /* - * Support all available satp_mode settings. The default - * value will be set to MBARE if the user doesn't set - * satp_mode manually (see set_satp_mode_default()). - */ -#ifndef CONFIG_USER_ONLY - set_satp_mode_max_supported(RISCV_CPU(obj), VM_1_10_SV64); -#endif } #else static void rv32_base_cpu_init(Object *obj) @@ -1329,6 +1313,34 @@ static void riscv_cpu_init(Object *obj) cpu->env.vext_ver = VEXT_VERSION_1_00_0; } +static void riscv_bare_cpu_init(Object *obj) +{ + RISCVCPU *cpu = RISCV_CPU(obj); + + /* + * Bare CPUs do not inherit the timer and performance + * counters from the parent class (see riscv_cpu_init() + * for info on why the parent enables them). + * + * Users have to explicitly enable these counters for + * bare CPUs. + */ + cpu->cfg.ext_zicntr = false; + cpu->cfg.ext_zihpm = false; + + /* Set to QEMU's first supported priv version */ + cpu->env.priv_ver = PRIV_VERSION_1_10_0; + + /* + * Support all available satp_mode settings. The default + * value will be set to MBARE if the user doesn't set + * satp_mode manually (see set_satp_mode_default()). + */ +#ifndef CONFIG_USER_ONLY + set_satp_mode_max_supported(cpu, VM_1_10_SV64); +#endif +} + typedef struct misa_ext_info { const char *name; const char *description; @@ -2505,6 +2517,7 @@ static const TypeInfo riscv_cpu_type_infos[] = { { .name = TYPE_RISCV_BARE_CPU, .parent = TYPE_RISCV_CPU, + .instance_init = riscv_bare_cpu_init, .abstract = true, }, #if defined(TARGET_RISCV32) |