diff options
| -rw-r--r-- | hw/riscv/virt.c | 1 | ||||
| -rw-r--r-- | target/riscv/translate.c | 24 |
2 files changed, 17 insertions, 8 deletions
diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index 4a137a503c..2b38f89070 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -240,6 +240,7 @@ static void *create_fdt(RISCVVirtState *s, const struct MemmapEntry *memmap, qemu_fdt_setprop_cells(fdt, nodename, "reg", 0x0, memmap[VIRT_TEST].base, 0x0, memmap[VIRT_TEST].size); + g_free(nodename); nodename = g_strdup_printf("/uart@%lx", (long)memmap[VIRT_UART0].base); diff --git a/target/riscv/translate.c b/target/riscv/translate.c index 18d7b6d147..312bf298b3 100644 --- a/target/riscv/translate.c +++ b/target/riscv/translate.c @@ -1237,13 +1237,14 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, tcg_temp_free(t0); break; -#if defined(TARGET_RISCV64) case OPC_RISC_FMV_X_D: /* also OPC_RISC_FCLASS_D */ switch (rm) { +#if defined(TARGET_RISCV64) case 0: /* FMV */ gen_set_gpr(rd, cpu_fpr[rs1]); break; +#endif case 1: t0 = tcg_temp_new(); gen_helper_fclass_d(t0, cpu_fpr[rs1]); @@ -1255,6 +1256,7 @@ static void gen_fp_arith(DisasContext *ctx, uint32_t opc, int rd, } break; +#if defined(TARGET_RISCV64) case OPC_RISC_FMV_D_X: t0 = tcg_temp_new(); gen_get_gpr(t0, rs1); @@ -1290,10 +1292,14 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, #ifndef CONFIG_USER_ONLY /* Extract funct7 value and check whether it matches SFENCE.VMA */ if ((opc == OPC_RISC_ECALL) && ((csr >> 5) == 9)) { - /* sfence.vma */ - /* TODO: handle ASID specific fences */ - gen_helper_tlb_flush(cpu_env); - return; + if (env->priv_ver == PRIV_VERSION_1_10_0) { + /* sfence.vma */ + /* TODO: handle ASID specific fences */ + gen_helper_tlb_flush(cpu_env); + return; + } else { + gen_exception_illegal(ctx); + } } #endif @@ -1340,7 +1346,11 @@ static void gen_system(CPURISCVState *env, DisasContext *ctx, uint32_t opc, gen_helper_wfi(cpu_env); break; case 0x104: /* SFENCE.VM */ - gen_helper_tlb_flush(cpu_env); + if (env->priv_ver <= PRIV_VERSION_1_09_1) { + gen_helper_tlb_flush(cpu_env); + } else { + gen_exception_illegal(ctx); + } break; #endif default: @@ -1766,7 +1776,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) GET_RM(ctx->opcode)); break; case OPC_RISC_FENCE: -#ifndef CONFIG_USER_ONLY if (ctx->opcode & 0x1000) { /* FENCE_I is a no-op in QEMU, * however we need to end the translation block */ @@ -1777,7 +1786,6 @@ static void decode_RV32_64G(CPURISCVState *env, DisasContext *ctx) /* FENCE is a full memory barrier. */ tcg_gen_mb(TCG_MO_ALL | TCG_BAR_SC); } -#endif break; case OPC_RISC_SYSTEM: gen_system(env, ctx, MASK_OP_SYSTEM(ctx->opcode), rd, rs1, |