diff options
| -rw-r--r-- | hw/hppa/machine.c | 28 | ||||
| -rw-r--r-- | hw/pci-host/astro.c | 26 | ||||
| -rw-r--r-- | pc-bios/hppa-firmware.img | bin | 681388 -> 163324 bytes | |||
| m--------- | roms/seabios-hppa | 0 | ||||
| -rw-r--r-- | target/hppa/cpu.c | 6 | ||||
| -rw-r--r-- | target/hppa/cpu.h | 1 | ||||
| -rw-r--r-- | target/hppa/mem_helper.c | 35 | ||||
| -rw-r--r-- | target/hppa/op_helper.c | 6 |
8 files changed, 64 insertions, 38 deletions
diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index c8da7c18d5..9e611620cc 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -36,8 +36,8 @@ #define MIN_SEABIOS_HPPA_VERSION 12 /* require at least this fw version */ -/* Power button address at &PAGE0->pad[4] */ -#define HPA_POWER_BUTTON (0x40 + 4 * sizeof(uint32_t)) +#define HPA_POWER_BUTTON (FIRMWARE_END - 0x10) +static hwaddr soft_power_reg; #define enable_lasi_lan() 0 @@ -45,7 +45,6 @@ static DeviceState *lasi_dev; static void hppa_powerdown_req(Notifier *n, void *opaque) { - hwaddr soft_power_reg = HPA_POWER_BUTTON; uint32_t val; val = ldl_be_phys(&address_space_memory, soft_power_reg); @@ -221,7 +220,7 @@ static FWCfgState *create_fw_cfg(MachineState *ms, PCIBus *pci_bus, fw_cfg_add_file(fw_cfg, "/etc/hppa/machine", g_memdup(mc->name, len), len); - val = cpu_to_le64(HPA_POWER_BUTTON); + val = cpu_to_le64(soft_power_reg); fw_cfg_add_file(fw_cfg, "/etc/hppa/power-button-addr", g_memdup(&val, sizeof(val)), sizeof(val)); @@ -276,6 +275,7 @@ static TranslateFn *machine_HP_common_init_cpus(MachineState *machine) unsigned int smp_cpus = machine->smp.cpus; TranslateFn *translate; MemoryRegion *cpu_region; + uint64_t ram_max; /* Create CPUs. */ for (unsigned int i = 0; i < smp_cpus; i++) { @@ -288,10 +288,14 @@ static TranslateFn *machine_HP_common_init_cpus(MachineState *machine) */ if (hppa_is_pa20(&cpu[0]->env)) { translate = translate_pa20; + ram_max = 0xf0000000; /* 3.75 GB (limited by 32-bit firmware) */ } else { translate = translate_pa10; + ram_max = 0xf0000000; /* 3.75 GB (32-bit CPU) */ } + soft_power_reg = translate(NULL, HPA_POWER_BUTTON); + for (unsigned int i = 0; i < smp_cpus; i++) { g_autofree char *name = g_strdup_printf("cpu%u-io-eir", i); @@ -311,9 +315,9 @@ static TranslateFn *machine_HP_common_init_cpus(MachineState *machine) cpu_region); /* Main memory region. */ - if (machine->ram_size > 3 * GiB) { - error_report("RAM size is currently restricted to 3GB"); - exit(EXIT_FAILURE); + if (machine->ram_size > ram_max) { + info_report("Max RAM size limited to %" PRIu64 " MB", ram_max / MiB); + machine->ram_size = ram_max; } memory_region_add_subregion_overlap(addr_space, 0, machine->ram, -1); @@ -343,8 +347,10 @@ static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci_bus, SysBusDevice *s; /* SCSI disk setup. */ - dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); - lsi53c8xx_handle_legacy_cmdline(dev); + if (drive_get_max_bus(IF_SCSI) >= 0) { + dev = DEVICE(pci_create_simple(pci_bus, -1, "lsi53c895a")); + lsi53c8xx_handle_legacy_cmdline(dev); + } /* Graphics setup. */ if (machine->enable_graphics && vga_interface_type != VGA_NONE) { @@ -357,7 +363,7 @@ static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci_bus, } /* Network setup. */ - if (enable_lasi_lan()) { + if (nd_table[0].used && enable_lasi_lan()) { lasi_82596_init(addr_space, translate(NULL, LASI_LAN_HPA), qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA)); } @@ -382,7 +388,7 @@ static void machine_HP_common_init_tail(MachineState *machine, PCIBus *pci_bus, pci_set_word(&pci_dev->config[PCI_SUBSYSTEM_ID], 0x1227); /* Powerbar */ /* create a second serial PCI card when running Astro */ - if (!lasi_dev) { + if (serial_hd(1) && !lasi_dev) { pci_dev = pci_new(-1, "pci-serial-4x"); qdev_prop_set_chr(DEVICE(pci_dev), "chardev1", serial_hd(1)); qdev_prop_set_chr(DEVICE(pci_dev), "chardev2", serial_hd(2)); diff --git a/hw/pci-host/astro.c b/hw/pci-host/astro.c index f4de70475c..37d271118c 100644 --- a/hw/pci-host/astro.c +++ b/hw/pci-host/astro.c @@ -166,6 +166,8 @@ static MemTxResult elroy_chip_write_with_attrs(void *opaque, hwaddr addr, trace_elroy_write(addr, size, val); switch ((addr >> 3) << 3) { + case 0x000: /* PCI_ID & PCI_COMMAND_STATUS_REG */ + break; case 0x080: put_val_in_int64(&s->arb_mask, addr, size, val); break; @@ -175,6 +177,9 @@ static MemTxResult elroy_chip_write_with_attrs(void *opaque, hwaddr addr, case 0x200 ... 0x250 - 1: /* LMMIO, GMMIO, WLMMIO, WGMMIO, ... */ put_val_in_arrary(s->mmio_base, 0x200, addr, size, val); break; + case 0x300: /* ibase */ + case 0x308: /* imask */ + break; case 0x0680: put_val_in_int64(&s->error_config, addr, size, val); break; @@ -538,6 +543,9 @@ static MemTxResult astro_chip_read_with_attrs(void *opaque, hwaddr addr, case 0x0030: /* HP-UX 10.20 and 11.11 reads it. No idea. */ val = -1; break; + case 0x0078: /* NetBSD reads 0x78 ? */ + val = -1; + break; case 0x0300 ... 0x03d8: /* LMMIO_DIRECT0_BASE... */ index = (addr - 0x300) / 8; val = s->ioc_ranges[index]; @@ -624,31 +632,43 @@ static MemTxResult astro_chip_write_with_attrs(void *opaque, hwaddr addr, case 0x10220: case 0x10230: /* HP-UX 11.11 reads it. No idea. */ break; - case 0x22108: /* IOC STATUS_CONTROL */ - put_val_in_int64(&s->ioc_status_ctrl, addr, size, val); - break; case 0x20200 ... 0x20240 - 1: /* IOC Rope0_Control ... */ put_val_in_arrary(s->ioc_rope_control, 0x20200, addr, size, val); break; case 0x20040: /* IOC Rope config */ + case 0x22040: put_val_in_int64(&s->ioc_rope_config, addr, size, val); break; case 0x20300: + case 0x22300: put_val_in_int64(&s->tlb_ibase, addr, size, val); break; case 0x20308: + case 0x22308: put_val_in_int64(&s->tlb_imask, addr, size, val); break; case 0x20310: + case 0x22310: put_val_in_int64(&s->tlb_pcom, addr, size, val); /* TODO: flush iommu */ break; case 0x20318: + case 0x22318: put_val_in_int64(&s->tlb_tcnfg, addr, size, val); break; case 0x20320: + case 0x22320: put_val_in_int64(&s->tlb_pdir_base, addr, size, val); break; + case 0x22000: /* func_id */ + break; + case 0x22008: /* func_class */ + break; + case 0x22050: /* rope_debug */ + break; + case 0x22108: /* IOC STATUS_CONTROL */ + put_val_in_int64(&s->ioc_status_ctrl, addr, size, val); + break; /* * empty placeholders for non-existent elroys, e.g. * func_class, pci config & data diff --git a/pc-bios/hppa-firmware.img b/pc-bios/hppa-firmware.img index ab715f0ecd..1b3a841825 100644 --- a/pc-bios/hppa-firmware.img +++ b/pc-bios/hppa-firmware.img Binary files differdiff --git a/roms/seabios-hppa b/roms/seabios-hppa -Subproject 4c6ecda618f2066707f50c53f31419244fd7f77 +Subproject e4eac85880e8677f96d8b9e94de9f2eec9c0751 diff --git a/target/hppa/cpu.c b/target/hppa/cpu.c index e1f252cc45..14e17fa9aa 100644 --- a/target/hppa/cpu.c +++ b/target/hppa/cpu.c @@ -110,11 +110,7 @@ void hppa_cpu_do_unaligned_access(CPUState *cs, vaddr addr, CPUHPPAState *env = &cpu->env; cs->exception_index = EXCP_UNALIGN; - if (env->psw & PSW_Q) { - /* ??? Needs tweaking for hppa64. */ - env->cr[CR_IOR] = addr; - env->cr[CR_ISR] = addr >> 32; - } + hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/hppa/cpu.h b/target/hppa/cpu.h index fd659ca88b..6a153405d2 100644 --- a/target/hppa/cpu.h +++ b/target/hppa/cpu.h @@ -385,6 +385,7 @@ void hppa_cpu_dump_state(CPUState *cs, FILE *f, int); #ifndef CONFIG_USER_ONLY void hppa_ptlbe(CPUHPPAState *env); hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr); +void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled); bool hppa_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, bool probe, uintptr_t retaddr); diff --git a/target/hppa/mem_helper.c b/target/hppa/mem_helper.c index 08abd1a9f9..4fcc612754 100644 --- a/target/hppa/mem_helper.c +++ b/target/hppa/mem_helper.c @@ -55,8 +55,14 @@ hwaddr hppa_abs_to_phys_pa2_w0(vaddr addr) /* I/O address space */ addr = (int32_t)addr; } else { - /* PDC address space */ - addr &= MAKE_64BIT_MASK(0, 24); + /* + * PDC address space: + * Figures H-10 and H-11 of the parisc2.0 spec do not specify + * where to map into the 64-bit PDC address space. + * We map with an offset which equals the 32-bit address, which + * is what can be seen on physical machines too. + */ + addr = (uint32_t)addr; addr |= -1ull << (TARGET_PHYS_ADDR_SPACE_BITS - 4); } return addr; @@ -299,14 +305,8 @@ hwaddr hppa_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return excp == EXCP_DTLB_MISS ? -1 : phys; } -G_NORETURN static void -raise_exception_with_ior(CPUHPPAState *env, int excp, uintptr_t retaddr, - vaddr addr, bool mmu_disabled) +void hppa_set_ior_and_isr(CPUHPPAState *env, vaddr addr, bool mmu_disabled) { - CPUState *cs = env_cpu(env); - - cs->exception_index = excp; - if (env->psw & PSW_Q) { /* * For pa1.x, the offset and space never overlap, and so we @@ -333,16 +333,23 @@ raise_exception_with_ior(CPUHPPAState *env, int excp, uintptr_t retaddr, */ uint64_t b; - cpu_restore_state(cs, retaddr); - - b = env->gr[env->unwind_breg]; + b = env->unwind_breg ? env->gr[env->unwind_breg] : 0; b >>= (env->psw & PSW_W ? 62 : 30); env->cr[CR_IOR] |= b << 62; - - cpu_loop_exit(cs); } } } +} + +G_NORETURN static void +raise_exception_with_ior(CPUHPPAState *env, int excp, uintptr_t retaddr, + vaddr addr, bool mmu_disabled) +{ + CPUState *cs = env_cpu(env); + + cs->exception_index = excp; + hppa_set_ior_and_isr(env, addr, mmu_disabled); + cpu_loop_exit_restore(cs, retaddr); } diff --git a/target/hppa/op_helper.c b/target/hppa/op_helper.c index 7f607c3afd..ce15469465 100644 --- a/target/hppa/op_helper.c +++ b/target/hppa/op_helper.c @@ -351,11 +351,7 @@ target_ulong HELPER(probe)(CPUHPPAState *env, target_ulong addr, excp = hppa_get_physical_address(env, addr, mmu_idx, 0, &phys, &prot, NULL); if (excp >= 0) { - if (env->psw & PSW_Q) { - /* ??? Needs tweaking for hppa64. */ - env->cr[CR_IOR] = addr; - env->cr[CR_ISR] = addr >> 32; - } + hppa_set_ior_and_isr(env, addr, MMU_IDX_MMU_DISABLED(mmu_idx)); if (excp == EXCP_DTLB_MISS) { excp = EXCP_NA_DTLB_MISS; } |