diff options
437 files changed, 3883 insertions, 2754 deletions
diff --git a/.gitlab-ci.d/crossbuilds.yml b/.gitlab-ci.d/crossbuilds.yml index 2d95784ed5..e44e4b49a2 100644 --- a/.gitlab-ci.d/crossbuilds.yml +++ b/.gitlab-ci.d/crossbuilds.yml @@ -176,6 +176,14 @@ cross-s390x-kvm-only: IMAGE: debian-s390x-cross ACCEL_CONFIGURE_OPTS: --disable-tcg +cross-mips64el-kvm-only: + extends: .cross_accel_build_job + needs: + job: mips64el-debian-cross-container + variables: + IMAGE: debian-mips64el-cross + ACCEL_CONFIGURE_OPTS: --disable-tcg --target-list=mips64el-softmmu + cross-win32-system: extends: .cross_system_build_job needs: diff --git a/MAINTAINERS b/MAINTAINERS index 6bc008d825..f880f45a59 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -404,7 +404,8 @@ F: target/arm/kvm.c MIPS KVM CPUs M: Huacai Chen <chenhuacai@kernel.org> S: Odd Fixes -F: target/mips/kvm.c +F: target/mips/kvm* +F: target/mips/sysemu/ PPC KVM CPUs M: David Gibson <david@gibson.dropbear.id.au> @@ -1026,6 +1027,7 @@ F: include/hw/misc/pca9552*.h F: hw/net/ftgmac100.c F: include/hw/net/ftgmac100.h F: docs/system/arm/aspeed.rst +F: tests/qtest/*aspeed* NRF51 M: Joel Stanley <joel@jms.id.au> diff --git a/accel/kvm/kvm-all.c b/accel/kvm/kvm-all.c index b6d9f92f15..4e0168e88b 100644 --- a/accel/kvm/kvm-all.c +++ b/accel/kvm/kvm-all.c @@ -30,11 +30,9 @@ #include "sysemu/kvm_int.h" #include "sysemu/runstate.h" #include "sysemu/cpus.h" -#include "sysemu/sysemu.h" #include "qemu/bswap.h" #include "exec/memory.h" #include "exec/ram_addr.h" -#include "exec/address-spaces.h" #include "qemu/event_notifier.h" #include "qemu/main-loop.h" #include "trace.h" @@ -2269,7 +2267,7 @@ static int kvm_handle_internal_error(CPUState *cpu, struct kvm_run *run) int i; for (i = 0; i < run->internal.ndata; ++i) { - fprintf(stderr, "extra data[%d]: %"PRIx64"\n", + fprintf(stderr, "extra data[%d]: 0x%016"PRIx64"\n", i, (uint64_t)run->internal.data[i]); } } diff --git a/accel/stubs/kvm-stub.c b/accel/stubs/kvm-stub.c index 0f17acfac0..5b1d00a222 100644 --- a/accel/stubs/kvm-stub.c +++ b/accel/stubs/kvm-stub.c @@ -11,7 +11,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "sysemu/kvm.h" #ifndef CONFIG_USER_ONLY diff --git a/accel/stubs/tcg-stub.c b/accel/stubs/tcg-stub.c index 2304606f8e..d8162673ae 100644 --- a/accel/stubs/tcg-stub.c +++ b/accel/stubs/tcg-stub.c @@ -11,7 +11,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "exec/exec-all.h" void tb_flush(CPUState *cpu) diff --git a/accel/tcg/cpu-exec-common.c b/accel/tcg/cpu-exec-common.c index 12c1e3e974..be6fe45aa5 100644 --- a/accel/tcg/cpu-exec-common.c +++ b/accel/tcg/cpu-exec-common.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "sysemu/cpus.h" #include "sysemu/tcg.h" #include "exec/exec-all.h" diff --git a/accel/tcg/cpu-exec.c b/accel/tcg/cpu-exec.c index f62f12e717..0dc5271715 100644 --- a/accel/tcg/cpu-exec.c +++ b/accel/tcg/cpu-exec.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "qemu/qemu-print.h" -#include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "trace.h" #include "disas/disas.h" diff --git a/accel/tcg/cputlb.c b/accel/tcg/cputlb.c index 8a7b779270..84e7d91a5c 100644 --- a/accel/tcg/cputlb.c +++ b/accel/tcg/cputlb.c @@ -19,11 +19,9 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" -#include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "exec/exec-all.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "exec/cpu_ldst.h" #include "exec/cputlb.h" #include "exec/tb-hash.h" diff --git a/accel/tcg/plugin-gen.c b/accel/tcg/plugin-gen.c index c3dc3effe7..7627225aef 100644 --- a/accel/tcg/plugin-gen.c +++ b/accel/tcg/plugin-gen.c @@ -43,7 +43,6 @@ * CPU's index into a TCG temp, since the first callback did it already. */ #include "qemu/osdep.h" -#include "cpu.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" #include "trace/mem.h" diff --git a/accel/tcg/tcg-accel-ops-icount.c b/accel/tcg/tcg-accel-ops-icount.c index 13b8fbeb69..ea42d1d51b 100644 --- a/accel/tcg/tcg-accel-ops-icount.c +++ b/accel/tcg/tcg-accel-ops-icount.c @@ -30,7 +30,6 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" -#include "hw/boards.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-icount.h" diff --git a/accel/tcg/tcg-accel-ops-rr.c b/accel/tcg/tcg-accel-ops-rr.c index 018b54c508..c02c061ecb 100644 --- a/accel/tcg/tcg-accel-ops-rr.c +++ b/accel/tcg/tcg-accel-ops-rr.c @@ -30,7 +30,6 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" -#include "hw/boards.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-rr.h" diff --git a/accel/tcg/tcg-accel-ops.c b/accel/tcg/tcg-accel-ops.c index 6cdcaa2855..7191315aee 100644 --- a/accel/tcg/tcg-accel-ops.c +++ b/accel/tcg/tcg-accel-ops.c @@ -32,7 +32,6 @@ #include "qemu/main-loop.h" #include "qemu/guest-random.h" #include "exec/exec-all.h" -#include "hw/boards.h" #include "tcg-accel-ops.h" #include "tcg-accel-ops-mttcg.h" diff --git a/accel/tcg/translate-all.c b/accel/tcg/translate-all.c index b12d0898d0..ae7e873713 100644 --- a/accel/tcg/translate-all.c +++ b/accel/tcg/translate-all.c @@ -22,7 +22,6 @@ #include "qemu-common.h" #define NO_CPU_IO_DEFS -#include "cpu.h" #include "trace.h" #include "disas/disas.h" #include "exec/exec-all.h" diff --git a/accel/tcg/translator.c b/accel/tcg/translator.c index 2dfc27102f..1d32732198 100644 --- a/accel/tcg/translator.c +++ b/accel/tcg/translator.c @@ -9,7 +9,6 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "cpu.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" #include "exec/exec-all.h" diff --git a/accel/tcg/user-exec-stub.c b/accel/tcg/user-exec-stub.c index b876f5c1e4..968cd3ca60 100644 --- a/accel/tcg/user-exec-stub.c +++ b/accel/tcg/user-exec-stub.c @@ -1,7 +1,6 @@ #include "qemu/osdep.h" #include "hw/core/cpu.h" #include "sysemu/replay.h" -#include "sysemu/sysemu.h" bool enable_cpu_pm = false; diff --git a/accel/tcg/user-exec.c b/accel/tcg/user-exec.c index 0d8cc27b21..fb2d43e6a9 100644 --- a/accel/tcg/user-exec.c +++ b/accel/tcg/user-exec.c @@ -17,7 +17,6 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ #include "qemu/osdep.h" -#include "cpu.h" #include "hw/core/tcg-cpu-ops.h" #include "disas/disas.h" #include "exec/exec-all.h" diff --git a/backends/hostmem-file.c b/backends/hostmem-file.c index b683da9daf..9b1b9f0a56 100644 --- a/backends/hostmem-file.c +++ b/backends/hostmem-file.c @@ -15,7 +15,6 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "sysemu/hostmem.h" -#include "sysemu/sysemu.h" #include "qom/object_interfaces.h" #include "qom/object.h" diff --git a/backends/hostmem-memfd.c b/backends/hostmem-memfd.c index 69b0ae30bb..da75e27057 100644 --- a/backends/hostmem-memfd.c +++ b/backends/hostmem-memfd.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "sysemu/hostmem.h" -#include "sysemu/sysemu.h" #include "qom/object_interfaces.h" #include "qemu/memfd.h" #include "qemu/module.h" diff --git a/backends/hostmem.c b/backends/hostmem.c index c6c1ff5b99..aab3de8408 100644 --- a/backends/hostmem.c +++ b/backends/hostmem.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "sysemu/hostmem.h" -#include "sysemu/sysemu.h" #include "hw/boards.h" #include "qapi/error.h" #include "qapi/qapi-builtin-visit.h" diff --git a/block.c b/block.c index 874c22c43e..9ad725d205 100644 --- a/block.c +++ b/block.c @@ -42,7 +42,6 @@ #include "qapi/qobject-output-visitor.h" #include "qapi/qapi-visit-block-core.h" #include "sysemu/block-backend.h" -#include "sysemu/sysemu.h" #include "qemu/notify.h" #include "qemu/option.h" #include "qemu/coroutine.h" diff --git a/block/block-backend.c b/block/block-backend.c index 6fca9853e1..de5496af66 100644 --- a/block/block-backend.c +++ b/block/block-backend.c @@ -18,7 +18,6 @@ #include "hw/qdev-core.h" #include "sysemu/blockdev.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" #include "sysemu/replay.h" #include "qapi/error.h" #include "qapi/qapi-events-block.h" diff --git a/block/nfs.c b/block/nfs.c index 8c1968bb41..7dff64f489 100644 --- a/block/nfs.c +++ b/block/nfs.c @@ -39,7 +39,6 @@ #include "qemu/option.h" #include "qemu/uri.h" #include "qemu/cutils.h" -#include "sysemu/sysemu.h" #include "sysemu/replay.h" #include "qapi/qapi-visit-block-core.h" #include "qapi/qmp/qdict.h" diff --git a/bsd-user/bsdload.c b/bsd-user/bsdload.c index f38c4faacf..e1ed3b7b60 100644 --- a/bsd-user/bsdload.c +++ b/bsd-user/bsdload.c @@ -13,22 +13,23 @@ abi_long memcpy_to_target(abi_ulong dest, const void *src, void *host_ptr; host_ptr = lock_user(VERIFY_WRITE, dest, len, 0); - if (!host_ptr) + if (!host_ptr) { return -TARGET_EFAULT; + } memcpy(host_ptr, src, len); unlock_user(host_ptr, dest, 1); return 0; } -static int count(char ** vec) +static int count(char **vec) { int i; - for(i = 0; *vec; i++) { + for (i = 0; *vec; i++) { vec++; } - return(i); + return i; } static int prepare_binprm(struct linux_binprm *bprm) @@ -37,23 +38,23 @@ static int prepare_binprm(struct linux_binprm *bprm) int mode; int retval; - if(fstat(bprm->fd, &st) < 0) { - return(-errno); + if (fstat(bprm->fd, &st) < 0) { + return -errno; } mode = st.st_mode; - if(!S_ISREG(mode)) { /* Must be regular file */ - return(-EACCES); + if (!S_ISREG(mode)) { /* Must be regular file */ + return -EACCES; } - if(!(mode & 0111)) { /* Must have at least one execute bit set */ - return(-EACCES); + if (!(mode & 0111)) { /* Must have at least one execute bit set */ + return -EACCES; } bprm->e_uid = geteuid(); bprm->e_gid = getegid(); /* Set-uid? */ - if(mode & S_ISUID) { + if (mode & S_ISUID) { bprm->e_uid = st.st_uid; } @@ -69,16 +70,14 @@ static int prepare_binprm(struct linux_binprm *bprm) memset(bprm->buf, 0, sizeof(bprm->buf)); retval = lseek(bprm->fd, 0L, SEEK_SET); - if(retval >= 0) { + if (retval >= 0) { retval = read(bprm->fd, bprm->buf, 128); } - if(retval < 0) { + if (retval < 0) { perror("prepare_binprm"); exit(-1); - /* return(-errno); */ - } - else { - return(retval); + } else { + return retval; } } @@ -125,19 +124,21 @@ abi_ulong loader_build_argptr(int envc, int argc, abi_ulong sp, return sp; } -int loader_exec(const char * filename, char ** argv, char ** envp, - struct target_pt_regs * regs, struct image_info *infop) +int loader_exec(const char *filename, char **argv, char **envp, + struct target_pt_regs *regs, struct image_info *infop) { struct linux_binprm bprm; int retval; int i; - bprm.p = TARGET_PAGE_SIZE*MAX_ARG_PAGES-sizeof(unsigned int); - for (i=0 ; i<MAX_ARG_PAGES ; i++) /* clear page-table */ + bprm.p = TARGET_PAGE_SIZE * MAX_ARG_PAGES - sizeof(unsigned int); + for (i = 0 ; i < MAX_ARG_PAGES ; i++) { /* clear page-table */ bprm.page[i] = NULL; + } retval = open(filename, O_RDONLY); - if (retval < 0) + if (retval < 0) { return retval; + } bprm.fd = retval; bprm.filename = (char *)filename; bprm.argc = count(argv); @@ -147,27 +148,27 @@ int loader_exec(const char * filename, char ** argv, char ** envp, retval = prepare_binprm(&bprm); - if(retval>=0) { + if (retval >= 0) { if (bprm.buf[0] == 0x7f && bprm.buf[1] == 'E' && bprm.buf[2] == 'L' && bprm.buf[3] == 'F') { - retval = load_elf_binary(&bprm,regs,infop); + retval = load_elf_binary(&bprm, regs, infop); } else { fprintf(stderr, "Unknown binary format\n"); return -1; } } - if(retval>=0) { + if (retval >= 0) { /* success. Initialize important registers */ do_init_thread(regs, infop); return retval; } /* Something went wrong, return the inode and free the argument pages*/ - for (i=0 ; i<MAX_ARG_PAGES ; i++) { + for (i = 0 ; i < MAX_ARG_PAGES ; i++) { g_free(bprm.page[i]); } - return(retval); + return retval; } diff --git a/bsd-user/main.c b/bsd-user/main.c index 798aba512c..36a889d084 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -32,7 +32,6 @@ #include "qemu/path.h" #include "qemu/help_option.h" #include "qemu/module.h" -#include "cpu.h" #include "exec/exec-all.h" #include "tcg/tcg.h" #include "qemu/timer.h" diff --git a/bsd-user/qemu.h b/bsd-user/qemu.h index d2bcaab741..b836b603af 100644 --- a/bsd-user/qemu.h +++ b/bsd-user/qemu.h @@ -233,7 +233,7 @@ static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) #define __put_user(x, hptr)\ ({\ int size = sizeof(*hptr);\ - switch(size) {\ + switch (size) {\ case 1:\ *(uint8_t *)(hptr) = (uint8_t)(typeof(*hptr))(x);\ break;\ @@ -255,7 +255,7 @@ static inline bool access_ok(int type, abi_ulong addr, abi_ulong size) #define __get_user(x, hptr) \ ({\ int size = sizeof(*hptr);\ - switch(size) {\ + switch (size) {\ case 1:\ x = (typeof(*hptr))*(uint8_t *)(hptr);\ break;\ diff --git a/bsd-user/syscall.c b/bsd-user/syscall.c index adc3d21b54..4abff796c7 100644 --- a/bsd-user/syscall.c +++ b/bsd-user/syscall.c @@ -199,6 +199,7 @@ static int sysctl_oldcvt(void *holdp, size_t holdlen, uint32_t kind) #else case CTLTYPE_LONG: *(uint64_t *)holdp = tswap64(*(long *)holdp); + break; case CTLTYPE_ULONG: *(uint64_t *)holdp = tswap64(*(unsigned long *)holdp); break; diff --git a/chardev/char-mux.c b/chardev/char-mux.c index 72beef29d2..5baf419010 100644 --- a/chardev/char-mux.c +++ b/chardev/char-mux.c @@ -28,7 +28,6 @@ #include "qemu/option.h" #include "chardev/char.h" #include "sysemu/block-backend.h" -#include "sysemu/sysemu.h" #include "chardev-internal.h" /* MUX driver for serial I/O splitting */ diff --git a/chardev/char.c b/chardev/char.c index 398f09df19..a4ebfcc5ac 100644 --- a/chardev/char.c +++ b/chardev/char.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include "qemu/cutils.h" #include "monitor/monitor.h" -#include "sysemu/sysemu.h" #include "qemu/config-file.h" #include "qemu/error-report.h" #include "qemu/qemu-print.h" diff --git a/disas.c b/disas.c index a61f95b580..3dab4482d1 100644 --- a/disas.c +++ b/disas.c @@ -4,7 +4,6 @@ #include "elf.h" #include "qemu/qemu-print.h" -#include "cpu.h" #include "disas/disas.h" #include "disas/capstone.h" diff --git a/docs/devel/control-flow-integrity.rst b/docs/devel/control-flow-integrity.rst index d89d70733d..e6b73a4fe1 100644 --- a/docs/devel/control-flow-integrity.rst +++ b/docs/devel/control-flow-integrity.rst @@ -39,7 +39,7 @@ later). Given the use of LTO, a version of AR that supports LLVM IR is required. The easies way of doing this is by selecting the AR provided by LLVM:: - AR=llvm-ar-9 CC=clang-9 CXX=lang++-9 /path/to/configure --enable-cfi + AR=llvm-ar-9 CC=clang-9 CXX=clang++-9 /path/to/configure --enable-cfi CFI is enabled on every binary produced. @@ -131,7 +131,7 @@ lld with version 11+. In other words, to compile with fuzzing and CFI, clang 11+ is required, and lld needs to be used as a linker:: - AR=llvm-ar-11 CC=clang-11 CXX=lang++-11 /path/to/configure --enable-cfi \ + AR=llvm-ar-11 CC=clang-11 CXX=clang++-11 /path/to/configure --enable-cfi \ -enable-fuzzing --extra-ldflags="-fuse-ld=lld" and then, compile the fuzzers as usual. diff --git a/docs/system/arm/aspeed.rst b/docs/system/arm/aspeed.rst index d1fb8f25b3..a1911f9403 100644 --- a/docs/system/arm/aspeed.rst +++ b/docs/system/arm/aspeed.rst @@ -49,6 +49,7 @@ Supported devices * Ethernet controllers * Front LEDs (PCA9552 on I2C bus) * LPC Peripheral Controller (a subset of subdevices are supported) + * Hash/Crypto Engine (HACE) - Hash support only. TODO: HMAC and RSA Missing devices @@ -59,7 +60,6 @@ Missing devices * PWM and Fan Controller * Slave GPIO Controller * Super I/O Controller - * Hash/Crypto Engine * PCI-Express 1 Controller * Graphic Display Controller * PECI Controller diff --git a/docs/system/deprecated.rst b/docs/system/deprecated.rst index 80cae86252..f9169077ae 100644 --- a/docs/system/deprecated.rst +++ b/docs/system/deprecated.rst @@ -245,6 +245,13 @@ The Raspberry Pi machines come in various models (A, A+, B, B+). To be able to distinguish which model QEMU is implementing, the ``raspi2`` and ``raspi3`` machines have been renamed ``raspi2b`` and ``raspi3b``. +Aspeed ``swift-bmc`` machine (since 6.1) +'''''''''''''''''''''''''''''''''''''''' + +This machine is deprecated because we have enough AST2500 based OpenPOWER +machines. It can be easily replaced by the ``witherspoon-bmc`` or the +``romulus-bmc`` machines. + Device options -------------- diff --git a/docs/system/removed-features.rst b/docs/system/removed-features.rst index 29e90601a5..c21e6fa5ee 100644 --- a/docs/system/removed-features.rst +++ b/docs/system/removed-features.rst @@ -285,6 +285,12 @@ The RISC-V no MMU cpus have been removed. The two CPUs: ``rv32imacu-nommu`` and ``rv64imacu-nommu`` can no longer be used. Instead the MMU status can be specified via the CPU ``mmu`` option when using the ``rv32`` or ``rv64`` CPUs. +``compat`` property of server class POWER CPUs (removed in 6.0) +''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''' + +The ``max-cpu-compat`` property of the ``pseries`` machine type should be used +instead. + System emulator machines ------------------------ diff --git a/dump/dump.c b/dump/dump.c index 929138e91d..ab625909f3 100644 --- a/dump/dump.c +++ b/dump/dump.c @@ -15,7 +15,6 @@ #include "qemu-common.h" #include "qemu/cutils.h" #include "elf.h" -#include "cpu.h" #include "exec/hwaddr.h" #include "monitor/monitor.h" #include "sysemu/kvm.h" diff --git a/dump/win_dump.c b/dump/win_dump.c index 652c7bad99..c5eb5a9aac 100644 --- a/dump/win_dump.c +++ b/dump/win_dump.c @@ -12,7 +12,6 @@ #include "qemu-common.h" #include "qemu/cutils.h" #include "elf.h" -#include "cpu.h" #include "exec/hwaddr.h" #include "monitor/monitor.h" #include "sysemu/kvm.h" diff --git a/gdbstub.c b/gdbstub.c index 054665e93e..9103ffc902 100644 --- a/gdbstub.c +++ b/gdbstub.c @@ -37,7 +37,6 @@ #include "monitor/monitor.h" #include "chardev/char.h" #include "chardev/char-fe.h" -#include "sysemu/sysemu.h" #include "exec/gdbstub.h" #include "hw/cpu/cluster.h" #include "hw/boards.h" diff --git a/hw/acpi/cpu.c b/hw/acpi/cpu.c index e2317be546..f82e9512fd 100644 --- a/hw/acpi/cpu.c +++ b/hw/acpi/cpu.c @@ -1,5 +1,4 @@ #include "qemu/osdep.h" -#include "hw/boards.h" #include "migration/vmstate.h" #include "hw/acpi/cpu.h" #include "qapi/error.h" diff --git a/hw/acpi/generic_event_device.c b/hw/acpi/generic_event_device.c index 5454be67d5..39c825763a 100644 --- a/hw/acpi/generic_event_device.c +++ b/hw/acpi/generic_event_device.c @@ -11,7 +11,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "exec/address-spaces.h" #include "hw/acpi/acpi.h" #include "hw/acpi/generic_event_device.h" #include "hw/irq.h" diff --git a/hw/acpi/ich9.c b/hw/acpi/ich9.c index 853447cf9d..4daa79ec8d 100644 --- a/hw/acpi/ich9.c +++ b/hw/acpi/ich9.c @@ -35,7 +35,6 @@ #include "sysemu/runstate.h" #include "hw/acpi/acpi.h" #include "hw/acpi/tco.h" -#include "exec/address-spaces.h" #include "hw/i386/ich9.h" #include "hw/mem/pc-dimm.h" diff --git a/hw/acpi/memory_hotplug.c b/hw/acpi/memory_hotplug.c index 0bdcf15528..af37889423 100644 --- a/hw/acpi/memory_hotplug.c +++ b/hw/acpi/memory_hotplug.c @@ -2,7 +2,6 @@ #include "hw/acpi/memory_hotplug.h" #include "hw/acpi/pc-hotplug.h" #include "hw/mem/pc-dimm.h" -#include "hw/boards.h" #include "hw/qdev-core.h" #include "migration/vmstate.h" #include "trace.h" diff --git a/hw/acpi/pcihp.c b/hw/acpi/pcihp.c index f4cb3c979d..4999277d57 100644 --- a/hw/acpi/pcihp.c +++ b/hw/acpi/pcihp.c @@ -31,7 +31,6 @@ #include "hw/pci/pci.h" #include "hw/pci/pci_bridge.h" #include "hw/acpi/acpi.h" -#include "exec/address-spaces.h" #include "hw/pci/pci_bus.h" #include "migration/vmstate.h" #include "qapi/error.h" diff --git a/hw/acpi/piix4.c b/hw/acpi/piix4.c index 8f8b0e95e5..0bd23d74e2 100644 --- a/hw/acpi/piix4.c +++ b/hw/acpi/piix4.c @@ -33,7 +33,6 @@ #include "sysemu/xen.h" #include "qapi/error.h" #include "qemu/range.h" -#include "exec/address-spaces.h" #include "hw/acpi/pcihp.h" #include "hw/acpi/cpu_hotplug.h" #include "hw/acpi/cpu.h" diff --git a/hw/alpha/dp264.c b/hw/alpha/dp264.c index c8e300d93f..1017ecf330 100644 --- a/hw/alpha/dp264.c +++ b/hw/alpha/dp264.c @@ -13,7 +13,6 @@ #include "hw/loader.h" #include "alpha_sys.h" #include "qemu/error-report.h" -#include "sysemu/sysemu.h" #include "hw/rtc/mc146818rtc.h" #include "hw/ide/pci.h" #include "hw/timer/i8254.h" diff --git a/hw/alpha/typhoon.c b/hw/alpha/typhoon.c index a42b319812..87020cbe0d 100644 --- a/hw/alpha/typhoon.c +++ b/hw/alpha/typhoon.c @@ -11,10 +11,8 @@ #include "qemu/units.h" #include "qapi/error.h" #include "cpu.h" -#include "hw/boards.h" #include "hw/irq.h" #include "alpha_sys.h" -#include "exec/address-spaces.h" #include "qom/object.h" diff --git a/hw/arm/Kconfig b/hw/arm/Kconfig index 8c37cf00da..b887f6a5b1 100644 --- a/hw/arm/Kconfig +++ b/hw/arm/Kconfig @@ -142,6 +142,7 @@ config PXA2XX select SD select SSI select USB_OHCI + select PCMCIA config GUMSTIX bool diff --git a/hw/arm/allwinner-a10.c b/hw/arm/allwinner-a10.c index d404f31e02..05e84728cb 100644 --- a/hw/arm/allwinner-a10.c +++ b/hw/arm/allwinner-a10.c @@ -16,10 +16,8 @@ */ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/allwinner-a10.h" #include "hw/misc/unimp.h" diff --git a/hw/arm/allwinner-h3.c b/hw/arm/allwinner-h3.c index 88259a9c0d..27f1070145 100644 --- a/hw/arm/allwinner-h3.c +++ b/hw/arm/allwinner-h3.c @@ -18,13 +18,11 @@ */ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "qemu/units.h" #include "hw/qdev-core.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/char/serial.h" #include "hw/misc/unimp.h" diff --git a/hw/arm/armv7m.c b/hw/arm/armv7m.c index 6dd10d8470..af0d935bf7 100644 --- a/hw/arm/armv7m.c +++ b/hw/arm/armv7m.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "hw/arm/armv7m.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "hw/loader.h" @@ -19,7 +18,6 @@ #include "sysemu/reset.h" #include "qemu/error-report.h" #include "qemu/module.h" -#include "exec/address-spaces.h" #include "target/arm/idau.h" /* Bitbanded IO. Each word corresponds to a single bit. */ diff --git a/hw/arm/aspeed.c b/hw/arm/aspeed.c index a17b75f494..3fe6c55744 100644 --- a/hw/arm/aspeed.c +++ b/hw/arm/aspeed.c @@ -11,20 +11,15 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" -#include "exec/address-spaces.h" #include "hw/arm/boot.h" #include "hw/arm/aspeed.h" #include "hw/arm/aspeed_soc.h" -#include "hw/boards.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/misc/pca9552.h" #include "hw/misc/tmp105.h" #include "hw/misc/led.h" #include "hw/qdev-properties.h" -#include "qemu/log.h" #include "sysemu/block-backend.h" -#include "sysemu/sysemu.h" #include "hw/loader.h" #include "qemu/error-report.h" #include "qemu/units.h" @@ -138,6 +133,19 @@ struct AspeedMachineState { /* Witherspoon hardware value: 0xF10AD216 (but use romulus definition) */ #define WITHERSPOON_BMC_HW_STRAP1 ROMULUS_BMC_HW_STRAP1 +/* Quanta-Q71l hardware value */ +#define QUANTA_Q71L_BMC_HW_STRAP1 ( \ + SCU_AST2400_HW_STRAP_DRAM_SIZE(DRAM_SIZE_128MB) | \ + SCU_AST2400_HW_STRAP_DRAM_CONFIG(2/* DDR3 with CL=6, CWL=5 */) | \ + SCU_AST2400_HW_STRAP_ACPI_DIS | \ + SCU_AST2400_HW_STRAP_SET_CLK_SOURCE(AST2400_CLK_24M_IN) | \ + SCU_HW_STRAP_VGA_CLASS_CODE | \ + SCU_HW_STRAP_SPI_MODE(SCU_HW_STRAP_SPI_PASS_THROUGH) | \ + SCU_AST2400_HW_STRAP_SET_CPU_AHB_RATIO(AST2400_CPU_AHB_RATIO_2_1) | \ + SCU_HW_STRAP_SPI_WIDTH | \ + SCU_HW_STRAP_VGA_SIZE_SET(VGA_8M_DRAM) | \ + SCU_AST2400_HW_STRAP_BOOT_MODE(AST2400_SPI_BOOT)) + /* AST2600 evb hardware value */ #define AST2600_EVB_HW_STRAP1 0x000000C0 #define AST2600_EVB_HW_STRAP2 0x00000003 @@ -146,6 +154,10 @@ struct AspeedMachineState { #define TACOMA_BMC_HW_STRAP1 0x00000000 #define TACOMA_BMC_HW_STRAP2 0x00000040 +/* Rainier hardware value: (QEMU prototype) */ +#define RAINIER_BMC_HW_STRAP1 0x00000000 +#define RAINIER_BMC_HW_STRAP2 0x00000000 + /* * The max ram region is for firmwares that scan the address space * with load/store to guess how much RAM the SoC has. @@ -327,7 +339,7 @@ static void aspeed_machine_init(MachineState *machine) object_property_set_int(OBJECT(&bmc->soc), "num-cs", amc->num_cs, &error_abort); object_property_set_link(OBJECT(&bmc->soc), "dram", - OBJECT(&bmc->ram_container), &error_abort); + OBJECT(machine->ram), &error_abort); if (machine->kernel_filename) { /* * When booting with a -kernel command line there is no u-boot @@ -433,6 +445,34 @@ static void palmetto_bmc_i2c_init(AspeedMachineState *bmc) object_property_set_int(OBJECT(dev), "temperature3", 110000, &error_abort); } +static void quanta_q71l_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc = &bmc->soc; + + /* + * The quanta-q71l platform expects tmp75s which are compatible with + * tmp105s. + */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4c); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4e); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 1), "tmp105", 0x4f); + + /* TODO: i2c-1: Add baseboard FRU eeprom@54 24c64 */ + /* TODO: i2c-1: Add Frontpanel FRU eeprom@57 24c64 */ + /* TODO: Add Memory Riser i2c mux and eeproms. */ + + /* TODO: i2c-2: pca9546@74 */ + /* TODO: i2c-2: pca9548@77 */ + /* TODO: i2c-3: Add BIOS FRU eeprom@56 24c64 */ + /* TODO: i2c-7: Add pca9546@70 */ + /* - i2c@0: pmbus@59 */ + /* - i2c@1: pmbus@58 */ + /* - i2c@2: pmbus@58 */ + /* - i2c@3: pmbus@59 */ + /* TODO: i2c-7: Add PDB FRU eeprom@52 */ + /* TODO: i2c-8: Add BMC FRU eeprom@50 */ +} + static void ast2500_evb_i2c_init(AspeedMachineState *bmc) { AspeedSoCState *soc = &bmc->soc; @@ -629,6 +669,58 @@ static void g220a_bmc_i2c_init(AspeedMachineState *bmc) eeprom_buf); } +static void rainier_bmc_i2c_init(AspeedMachineState *bmc) +{ + AspeedSoCState *soc = &bmc->soc; + + /* The rainier expects a TMP275 but a TMP105 is compatible */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, + 0x49); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 4), TYPE_TMP105, + 0x4a); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 5), TYPE_TMP105, + 0x49); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, + 0x4a); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 6), TYPE_TMP105, + 0x4b); + + /* Bus 7: TODO dps310@76 */ + /* Bus 7: TODO max31785@52 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), "pca9552", 0x61); + /* Bus 7: TODO si7021-a20@20 */ + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 7), TYPE_TMP105, + 0x48); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), TYPE_TMP105, + 0x4a); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 8), "pca9552", 0x61); + /* Bus 8: ucd90320@11 */ + /* Bus 8: ucd90320@b */ + /* Bus 8: ucd90320@c */ + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4c); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 9), "tmp423", 0x4d); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4c); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 10), "tmp423", 0x4d); + + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, + 0x48); + i2c_slave_create_simple(aspeed_i2c_get_bus(&soc->i2c, 11), TYPE_TMP105, + 0x49); +} + static bool aspeed_get_mmio_exec(Object *obj, Error **errp) { return ASPEED_MACHINE(obj)->mmio_exec; @@ -728,6 +820,23 @@ static void aspeed_machine_palmetto_class_init(ObjectClass *oc, void *data) aspeed_soc_num_cpus(amc->soc_name); }; +static void aspeed_machine_quanta_q71l_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "Quanta-Q71l BMC (ARM926EJ-S)"; + amc->soc_name = "ast2400-a1"; + amc->hw_strap1 = QUANTA_Q71L_BMC_HW_STRAP1; + amc->fmc_model = "n25q256a"; + amc->spi_model = "mx25l25635e"; + amc->num_cs = 1; + amc->i2c_init = quanta_q71l_bmc_i2c_init; + mc->default_ram_size = 128 * MiB; + mc->default_cpus = mc->min_cpus = mc->max_cpus = + aspeed_soc_num_cpus(amc->soc_name); +} + static void aspeed_machine_supermicrox11_bmc_class_init(ObjectClass *oc, void *data) { @@ -811,6 +920,9 @@ static void aspeed_machine_swift_class_init(ObjectClass *oc, void *data) mc->default_ram_size = 512 * MiB; mc->default_cpus = mc->min_cpus = mc->max_cpus = aspeed_soc_num_cpus(amc->soc_name); + + mc->deprecation_reason = "redundant system. Please use a similar " + "OpenPOWER BMC, Witherspoon or Romulus."; }; static void aspeed_machine_witherspoon_class_init(ObjectClass *oc, void *data) @@ -886,6 +998,25 @@ static void aspeed_machine_g220a_class_init(ObjectClass *oc, void *data) aspeed_soc_num_cpus(amc->soc_name); }; +static void aspeed_machine_rainier_class_init(ObjectClass *oc, void *data) +{ + MachineClass *mc = MACHINE_CLASS(oc); + AspeedMachineClass *amc = ASPEED_MACHINE_CLASS(oc); + + mc->desc = "IBM Rainier BMC (Cortex A7)"; + amc->soc_name = "ast2600-a1"; + amc->hw_strap1 = RAINIER_BMC_HW_STRAP1; + amc->hw_strap2 = RAINIER_BMC_HW_STRAP2; + amc->fmc_model = "mx66l1g45g"; + amc->spi_model = "mx66l1g45g"; + amc->num_cs = 2; + amc->macs_mask = ASPEED_MAC2_ON | ASPEED_MAC3_ON; + amc->i2c_init = rainier_bmc_i2c_init; + mc->default_ram_size = 1 * GiB; + mc->default_cpus = mc->min_cpus = mc->max_cpus = + aspeed_soc_num_cpus(amc->soc_name); +}; + static const TypeInfo aspeed_machine_types[] = { { .name = MACHINE_TYPE_NAME("palmetto-bmc"), @@ -928,6 +1059,14 @@ static const TypeInfo aspeed_machine_types[] = { .parent = TYPE_ASPEED_MACHINE, .class_init = aspeed_machine_g220a_class_init, }, { + .name = MACHINE_TYPE_NAME("quanta-q71l-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_quanta_q71l_class_init, + }, { + .name = MACHINE_TYPE_NAME("rainier-bmc"), + .parent = TYPE_ASPEED_MACHINE, + .class_init = aspeed_machine_rainier_class_init, + }, { .name = TYPE_ASPEED_MACHINE, .parent = TYPE_MACHINE, .instance_size = sizeof(AspeedMachineState), diff --git a/hw/arm/aspeed_ast2600.c b/hw/arm/aspeed_ast2600.c index bc87e754a3..e3013128c6 100644 --- a/hw/arm/aspeed_ast2600.c +++ b/hw/arm/aspeed_ast2600.c @@ -9,12 +9,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" -#include "exec/address-spaces.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" #include "hw/char/serial.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" @@ -42,6 +39,7 @@ static const hwaddr aspeed_soc_ast2600_memmap[] = { [ASPEED_DEV_ETH2] = 0x1E680000, [ASPEED_DEV_ETH4] = 0x1E690000, [ASPEED_DEV_VIC] = 0x1E6C0000, + [ASPEED_DEV_HACE] = 0x1E6D0000, [ASPEED_DEV_SDMC] = 0x1E6E0000, [ASPEED_DEV_SCU] = 0x1E6E2000, [ASPEED_DEV_XDMA] = 0x1E6E7000, @@ -102,6 +100,7 @@ static const int aspeed_soc_ast2600_irqmap[] = { [ASPEED_DEV_I2C] = 110, /* 110 -> 125 */ [ASPEED_DEV_ETH1] = 2, [ASPEED_DEV_ETH2] = 3, + [ASPEED_DEV_HACE] = 4, [ASPEED_DEV_ETH3] = 32, [ASPEED_DEV_ETH4] = 33, [ASPEED_DEV_KCS] = 138, /* 138 -> 142 */ @@ -185,7 +184,8 @@ static void aspeed_soc_ast2600_init(Object *obj) object_initialize_child(obj, "mii[*]", &s->mii[i], TYPE_ASPEED_MII); } - object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); + snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); + object_initialize_child(obj, "xdma", &s->xdma, typename); snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "gpio", &s->gpio, typename); @@ -213,6 +213,9 @@ static void aspeed_soc_ast2600_init(Object *obj) TYPE_SYSBUS_SDHCI); object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); + + snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); + object_initialize_child(obj, "hace", &s->hace, typename); } /* @@ -344,10 +347,6 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) /* FMC, The number of CS is set at the board level */ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), &error_abort); - if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", - sc->memmap[ASPEED_DEV_SDRAM], errp)) { - return; - } if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } @@ -498,6 +497,16 @@ static void aspeed_soc_ast2600_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, qdev_get_gpio_in(DEVICE(&s->a7mpcore), sc->irqmap[ASPEED_DEV_KCS] + aspeed_lpc_kcs_4)); + + /* HACE */ + object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); } static void aspeed_soc_ast2600_class_init(ObjectClass *oc, void *data) diff --git a/hw/arm/aspeed_soc.c b/hw/arm/aspeed_soc.c index 057d053c84..3ad6c56fa9 100644 --- a/hw/arm/aspeed_soc.c +++ b/hw/arm/aspeed_soc.c @@ -12,12 +12,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" -#include "exec/address-spaces.h" #include "hw/misc/unimp.h" #include "hw/arm/aspeed_soc.h" #include "hw/char/serial.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/error-report.h" #include "hw/i2c/aspeed_i2c.h" @@ -34,6 +31,7 @@ static const hwaddr aspeed_soc_ast2400_memmap[] = { [ASPEED_DEV_VIC] = 0x1E6C0000, [ASPEED_DEV_SDMC] = 0x1E6E0000, [ASPEED_DEV_SCU] = 0x1E6E2000, + [ASPEED_DEV_HACE] = 0x1E6E3000, [ASPEED_DEV_XDMA] = 0x1E6E7000, [ASPEED_DEV_VIDEO] = 0x1E700000, [ASPEED_DEV_ADC] = 0x1E6E9000, @@ -65,6 +63,7 @@ static const hwaddr aspeed_soc_ast2500_memmap[] = { [ASPEED_DEV_VIC] = 0x1E6C0000, [ASPEED_DEV_SDMC] = 0x1E6E0000, [ASPEED_DEV_SCU] = 0x1E6E2000, + [ASPEED_DEV_HACE] = 0x1E6E3000, [ASPEED_DEV_XDMA] = 0x1E6E7000, [ASPEED_DEV_ADC] = 0x1E6E9000, [ASPEED_DEV_VIDEO] = 0x1E700000, @@ -117,6 +116,7 @@ static const int aspeed_soc_ast2400_irqmap[] = { [ASPEED_DEV_ETH2] = 3, [ASPEED_DEV_XDMA] = 6, [ASPEED_DEV_SDHCI] = 26, + [ASPEED_DEV_HACE] = 4, }; #define aspeed_soc_ast2500_irqmap aspeed_soc_ast2400_irqmap @@ -196,7 +196,8 @@ static void aspeed_soc_init(Object *obj) TYPE_FTGMAC100); } - object_initialize_child(obj, "xdma", &s->xdma, TYPE_ASPEED_XDMA); + snprintf(typename, sizeof(typename), TYPE_ASPEED_XDMA "-%s", socname); + object_initialize_child(obj, "xdma", &s->xdma, typename); snprintf(typename, sizeof(typename), "aspeed.gpio-%s", socname); object_initialize_child(obj, "gpio", &s->gpio, typename); @@ -212,6 +213,9 @@ static void aspeed_soc_init(Object *obj) } object_initialize_child(obj, "lpc", &s->lpc, TYPE_ASPEED_LPC); + + snprintf(typename, sizeof(typename), "aspeed.hace-%s", socname); + object_initialize_child(obj, "hace", &s->hace, typename); } static void aspeed_soc_realize(DeviceState *dev, Error **errp) @@ -301,10 +305,6 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) /* FMC, The number of CS is set at the board level */ object_property_set_link(OBJECT(&s->fmc), "dram", OBJECT(s->dram_mr), &error_abort); - if (!object_property_set_int(OBJECT(&s->fmc), "sdram-base", - sc->memmap[ASPEED_DEV_SDRAM], errp)) { - return; - } if (!sysbus_realize(SYS_BUS_DEVICE(&s->fmc), errp)) { return; } @@ -425,6 +425,16 @@ static void aspeed_soc_realize(DeviceState *dev, Error **errp) sysbus_connect_irq(SYS_BUS_DEVICE(&s->lpc), 1 + aspeed_lpc_kcs_4, qdev_get_gpio_in(DEVICE(&s->lpc), aspeed_lpc_kcs_4)); + + /* HACE */ + object_property_set_link(OBJECT(&s->hace), "dram", OBJECT(s->dram_mr), + &error_abort); + if (!sysbus_realize(SYS_BUS_DEVICE(&s->hace), errp)) { + return; + } + sysbus_mmio_map(SYS_BUS_DEVICE(&s->hace), 0, sc->memmap[ASPEED_DEV_HACE]); + sysbus_connect_irq(SYS_BUS_DEVICE(&s->hace), 0, + aspeed_soc_get_irq(s, ASPEED_DEV_HACE)); } static Property aspeed_soc_properties[] = { DEFINE_PROP_LINK("dram", AspeedSoCState, dram_mr, TYPE_MEMORY_REGION, diff --git a/hw/arm/bcm2836.c b/hw/arm/bcm2836.c index de7ade2878..24354338ca 100644 --- a/hw/arm/bcm2836.c +++ b/hw/arm/bcm2836.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/arm/bcm2836.h" #include "hw/arm/raspi_platform.h" #include "hw/sysbus.h" diff --git a/hw/arm/boot.c b/hw/arm/boot.c index e56c42ac22..d7b059225e 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -25,7 +25,6 @@ #include "sysemu/device_tree.h" #include "qemu/config-file.h" #include "qemu/option.h" -#include "exec/address-spaces.h" #include "qemu/units.h" /* Kernel boot protocol is specified in the kernel docs diff --git a/hw/arm/cubieboard.c b/hw/arm/cubieboard.c index 9d0d728180..294ba5de6e 100644 --- a/hw/arm/cubieboard.c +++ b/hw/arm/cubieboard.c @@ -16,11 +16,7 @@ */ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "qapi/error.h" -#include "cpu.h" -#include "sysemu/sysemu.h" -#include "hw/sysbus.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/allwinner-a10.h" diff --git a/hw/arm/digic_boards.c b/hw/arm/digic_boards.c index 6cdc1d83fc..b771a3d8b7 100644 --- a/hw/arm/digic_boards.c +++ b/hw/arm/digic_boards.c @@ -27,14 +27,11 @@ #include "qapi/error.h" #include "qemu-common.h" #include "qemu/datadir.h" -#include "cpu.h" #include "hw/boards.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "hw/arm/digic.h" #include "hw/block/flash.h" #include "hw/loader.h" -#include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "qemu/units.h" #include "qemu/cutils.h" diff --git a/hw/arm/exynos4210.c b/hw/arm/exynos4210.c index ced2769b10..5c7a51bbad 100644 --- a/hw/arm/exynos4210.c +++ b/hw/arm/exynos4210.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "qemu/log.h" #include "cpu.h" #include "hw/cpu/a9mpcore.h" #include "hw/irq.h" diff --git a/hw/arm/exynos4_boards.c b/hw/arm/exynos4_boards.c index 56b729141b..35dd9875da 100644 --- a/hw/arm/exynos4_boards.c +++ b/hw/arm/exynos4_boards.c @@ -25,8 +25,6 @@ #include "qemu/units.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "cpu.h" -#include "sysemu/sysemu.h" #include "hw/sysbus.h" #include "net/net.h" #include "hw/arm/boot.h" diff --git a/hw/arm/fsl-imx25.c b/hw/arm/fsl-imx25.c index 08a98f828f..24c4374590 100644 --- a/hw/arm/fsl-imx25.c +++ b/hw/arm/fsl-imx25.c @@ -24,10 +24,8 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/fsl-imx25.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" #include "hw/qdev-properties.h" #include "chardev/char.h" diff --git a/hw/arm/fsl-imx31.c b/hw/arm/fsl-imx31.c index 0983998bb4..def27bb913 100644 --- a/hw/arm/fsl-imx31.c +++ b/hw/arm/fsl-imx31.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/fsl-imx31.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index bf886268c5..c3cb315dbc 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -29,7 +29,6 @@ #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "hw/boards.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "hw/char/pl011.h" #include "hw/ide/ahci.h" @@ -170,7 +169,7 @@ struct HighbankRegsState { uint32_t regs[NUM_REGS]; }; -static VMStateDescription vmstate_highbank_regs = { +static const VMStateDescription vmstate_highbank_regs = { .name = "highbank-regs", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/arm/imx25_pdk.c b/hw/arm/imx25_pdk.c index 1c201d0d8e..11426e5ec0 100644 --- a/hw/arm/imx25_pdk.c +++ b/hw/arm/imx25_pdk.c @@ -25,12 +25,10 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/qdev-properties.h" #include "hw/arm/fsl-imx25.h" #include "hw/boards.h" #include "qemu/error-report.h" -#include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "hw/i2c/i2c.h" #include "qemu/cutils.h" diff --git a/hw/arm/kzm.c b/hw/arm/kzm.c index e3f7d4ead2..39559c44c2 100644 --- a/hw/arm/kzm.c +++ b/hw/arm/kzm.c @@ -15,7 +15,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/fsl-imx31.h" #include "hw/boards.h" #include "qemu/error-report.h" diff --git a/hw/arm/mcimx6ul-evk.c b/hw/arm/mcimx6ul-evk.c index ed69a7b037..ce16b6b317 100644 --- a/hw/arm/mcimx6ul-evk.c +++ b/hw/arm/mcimx6ul-evk.c @@ -15,7 +15,6 @@ #include "hw/arm/fsl-imx6ul.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/arm/mcimx7d-sabre.c b/hw/arm/mcimx7d-sabre.c index e57d52b344..e896222c34 100644 --- a/hw/arm/mcimx7d-sabre.c +++ b/hw/arm/mcimx7d-sabre.c @@ -17,7 +17,6 @@ #include "hw/arm/fsl-imx7.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/arm/msf2-soc.c b/hw/arm/msf2-soc.c index d2c29e82d1..5cfe7caf83 100644 --- a/hw/arm/msf2-soc.c +++ b/hw/arm/msf2-soc.c @@ -27,7 +27,6 @@ #include "qapi/error.h" #include "exec/address-spaces.h" #include "hw/char/serial.h" -#include "hw/irq.h" #include "hw/arm/msf2-soc.h" #include "hw/misc/unimp.h" #include "sysemu/sysemu.h" diff --git a/hw/arm/msf2-som.c b/hw/arm/msf2-som.c index f9b61c36dd..343ec977c0 100644 --- a/hw/arm/msf2-som.c +++ b/hw/arm/msf2-som.c @@ -31,7 +31,6 @@ #include "hw/arm/boot.h" #include "exec/address-spaces.h" #include "hw/arm/msf2-soc.h" -#include "cpu.h" #define DDR_BASE_ADDRESS 0xA0000000 #define DDR_SIZE (64 * MiB) diff --git a/hw/arm/musicpal.c b/hw/arm/musicpal.c index 9cebece2de..2d612cc0c9 100644 --- a/hw/arm/musicpal.c +++ b/hw/arm/musicpal.c @@ -19,7 +19,6 @@ #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/char/serial.h" -#include "hw/hw.h" #include "qemu/timer.h" #include "hw/ptimer.h" #include "hw/qdev-properties.h" @@ -32,7 +31,6 @@ #include "sysemu/block-backend.h" #include "sysemu/runstate.h" #include "sysemu/dma.h" -#include "exec/address-spaces.h" #include "ui/pixel_ops.h" #include "qemu/cutils.h" #include "qom/object.h" diff --git a/hw/arm/npcm7xx.c b/hw/arm/npcm7xx.c index 495b0f8e91..2ab0080e0b 100644 --- a/hw/arm/npcm7xx.c +++ b/hw/arm/npcm7xx.c @@ -16,7 +16,6 @@ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "hw/arm/boot.h" #include "hw/arm/npcm7xx.h" #include "hw/char/serial.h" diff --git a/hw/arm/npcm7xx_boards.c b/hw/arm/npcm7xx_boards.c index e22fe4bf8f..d4553e3786 100644 --- a/hw/arm/npcm7xx_boards.c +++ b/hw/arm/npcm7xx_boards.c @@ -16,7 +16,6 @@ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "hw/arm/npcm7xx.h" #include "hw/core/cpu.h" #include "hw/i2c/smbus_eeprom.h" @@ -27,7 +26,6 @@ #include "qemu-common.h" #include "qemu/datadir.h" #include "qemu/units.h" -#include "sysemu/sysemu.h" #define NPCM750_EVB_POWER_ON_STRAPS 0x00001ff7 #define QUANTA_GSJ_POWER_ON_STRAPS 0x00001fff diff --git a/hw/arm/nrf51_soc.c b/hw/arm/nrf51_soc.c index e15981e019..9407c2f268 100644 --- a/hw/arm/nrf51_soc.c +++ b/hw/arm/nrf51_soc.c @@ -13,9 +13,7 @@ #include "hw/arm/boot.h" #include "hw/sysbus.h" #include "hw/misc/unimp.h" -#include "exec/address-spaces.h" #include "qemu/log.h" -#include "cpu.h" #include "hw/arm/nrf51.h" #include "hw/arm/nrf51_soc.h" diff --git a/hw/arm/nseries.c b/hw/arm/nseries.c index 387eea4d44..0aefa5d0f3 100644 --- a/hw/arm/nseries.c +++ b/hw/arm/nseries.c @@ -43,7 +43,6 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "qemu/log.h" -#include "exec/address-spaces.h" /* Nokia N8x0 support */ struct n800_s { diff --git a/hw/arm/omap1.c b/hw/arm/omap1.c index 02c0f66431..180d3788f8 100644 --- a/hw/arm/omap1.c +++ b/hw/arm/omap1.c @@ -24,7 +24,6 @@ #include "qemu-common.h" #include "cpu.h" #include "exec/address-spaces.h" -#include "hw/boards.h" #include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" diff --git a/hw/arm/omap2.c b/hw/arm/omap2.c index 16d388fc79..02b1aa8c97 100644 --- a/hw/arm/omap2.c +++ b/hw/arm/omap2.c @@ -27,7 +27,6 @@ #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "hw/boards.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/arm/boot.h" diff --git a/hw/arm/orangepi.c b/hw/arm/orangepi.c index 40cdb5c6d2..0cf9895ce7 100644 --- a/hw/arm/orangepi.c +++ b/hw/arm/orangepi.c @@ -21,12 +21,9 @@ #include "qemu/units.h" #include "exec/address-spaces.h" #include "qapi/error.h" -#include "cpu.h" -#include "hw/sysbus.h" #include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/arm/allwinner-h3.h" -#include "sysemu/sysemu.h" static struct arm_boot_info orangepi_binfo = { .nb_cpus = AW_H3_NUM_CPUS, diff --git a/hw/arm/palm.c b/hw/arm/palm.c index 4e3dc5fbbf..68e11dd1ec 100644 --- a/hw/arm/palm.c +++ b/hw/arm/palm.c @@ -29,7 +29,6 @@ #include "hw/input/tsc2xxx.h" #include "hw/irq.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "cpu.h" #include "qemu/cutils.h" #include "qom/object.h" diff --git a/hw/arm/pxa2xx_pic.c b/hw/arm/pxa2xx_pic.c index cf6cb2a373..ed032fed54 100644 --- a/hw/arm/pxa2xx_pic.c +++ b/hw/arm/pxa2xx_pic.c @@ -301,7 +301,7 @@ DeviceState *pxa2xx_pic_init(hwaddr base, ARMCPU *cpu) return dev; } -static VMStateDescription vmstate_pxa2xx_pic_regs = { +static const VMStateDescription vmstate_pxa2xx_pic_regs = { .name = "pxa2xx_pic", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/arm/raspi.c b/hw/arm/raspi.c index 990509d385..b30a17871f 100644 --- a/hw/arm/raspi.c +++ b/hw/arm/raspi.c @@ -16,14 +16,12 @@ #include "qemu/units.h" #include "qemu/cutils.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/bcm2836.h" #include "hw/registerfields.h" #include "qemu/error-report.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/arm/boot.h" -#include "sysemu/sysemu.h" #include "qom/object.h" #define SMPBOOT_ADDR 0x300 /* this should leave enough space for ATAGS */ diff --git a/hw/arm/realview.c b/hw/arm/realview.c index 0831159d15..1c54316ba3 100644 --- a/hw/arm/realview.c +++ b/hw/arm/realview.c @@ -20,7 +20,6 @@ #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/i2c/i2c.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "hw/char/pl011.h" #include "hw/cpu/a9mpcore.h" diff --git a/hw/arm/sabrelite.c b/hw/arm/sabrelite.c index a3dbf85e0e..42348e5cb1 100644 --- a/hw/arm/sabrelite.c +++ b/hw/arm/sabrelite.c @@ -15,7 +15,6 @@ #include "hw/arm/fsl-imx6.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/arm/sbsa-ref.c b/hw/arm/sbsa-ref.c index 88dfb2284c..43c19b4923 100644 --- a/hw/arm/sbsa-ref.c +++ b/hw/arm/sbsa-ref.c @@ -27,7 +27,6 @@ #include "sysemu/numa.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" #include "exec/hwaddr.h" #include "kvm_arm.h" #include "hw/arm/boot.h" diff --git a/hw/arm/smmu-common.c b/hw/arm/smmu-common.c index 84d2c62c26..0459850a93 100644 --- a/hw/arm/smmu-common.c +++ b/hw/arm/smmu-common.c @@ -17,7 +17,6 @@ */ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "trace.h" #include "exec/target_page.h" #include "hw/core/cpu.h" diff --git a/hw/arm/smmuv3.c b/hw/arm/smmuv3.c index 228dc54b0b..7bed2ac520 100644 --- a/hw/arm/smmuv3.c +++ b/hw/arm/smmuv3.c @@ -23,7 +23,6 @@ #include "migration/vmstate.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" -#include "exec/address-spaces.h" #include "cpu.h" #include "trace.h" #include "qemu/log.h" diff --git a/hw/arm/spitz.c b/hw/arm/spitz.c index 6b3bf9828b..b45a929cbd 100644 --- a/hw/arm/spitz.c +++ b/hw/arm/spitz.c @@ -1134,7 +1134,7 @@ static bool is_version_0(void *opaque, int version_id) return version_id == 0; } -static VMStateDescription vmstate_sl_nand_info = { +static const VMStateDescription vmstate_sl_nand_info = { .name = "sl-nand", .version_id = 0, .minimum_version_id = 0, @@ -1170,7 +1170,7 @@ static const TypeInfo sl_nand_info = { .class_init = sl_nand_class_init, }; -static VMStateDescription vmstate_spitz_kbd = { +static const VMStateDescription vmstate_spitz_kbd = { .name = "spitz-keyboard", .version_id = 1, .minimum_version_id = 0, diff --git a/hw/arm/stellaris.c b/hw/arm/stellaris.c index 27292ec411..8b4dab9b79 100644 --- a/hw/arm/stellaris.c +++ b/hw/arm/stellaris.c @@ -27,7 +27,6 @@ #include "migration/vmstate.h" #include "hw/misc/unimp.h" #include "hw/qdev-clock.h" -#include "cpu.h" #include "qom/object.h" #define GPIO_A 0 diff --git a/hw/arm/strongarm.c b/hw/arm/strongarm.c index c7ca54bcea..939a57dda5 100644 --- a/hw/arm/strongarm.c +++ b/hw/arm/strongarm.c @@ -30,7 +30,6 @@ #include "qemu/osdep.h" #include "qemu-common.h" #include "cpu.h" -#include "hw/boards.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/qdev-properties-system.h" @@ -207,7 +206,7 @@ static int strongarm_pic_post_load(void *opaque, int version_id) return 0; } -static VMStateDescription vmstate_strongarm_pic_regs = { +static const VMStateDescription vmstate_strongarm_pic_regs = { .name = "strongarm_pic", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/arm/versatilepb.c b/hw/arm/versatilepb.c index 1ea5534626..575399c4fc 100644 --- a/hw/arm/versatilepb.c +++ b/hw/arm/versatilepb.c @@ -21,7 +21,6 @@ #include "hw/i2c/arm_sbcon_i2c.h" #include "hw/irq.h" #include "hw/boards.h" -#include "exec/address-spaces.h" #include "hw/block/flash.h" #include "qemu/error-report.h" #include "hw/char/pl011.h" diff --git a/hw/arm/vexpress.c b/hw/arm/vexpress.c index 326a1a6db5..58481c0762 100644 --- a/hw/arm/vexpress.c +++ b/hw/arm/vexpress.c @@ -35,7 +35,6 @@ #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "hw/block/flash.h" #include "sysemu/device_tree.h" #include "qemu/error-report.h" diff --git a/hw/arm/virt.c b/hw/arm/virt.c index fee696fb0e..0a78532018 100644 --- a/hw/arm/virt.c +++ b/hw/arm/virt.c @@ -36,7 +36,6 @@ #include "monitor/qdev.h" #include "qapi/error.h" #include "hw/sysbus.h" -#include "hw/boards.h" #include "hw/arm/boot.h" #include "hw/arm/primecell.h" #include "hw/arm/virt.h" @@ -48,11 +47,9 @@ #include "sysemu/device_tree.h" #include "sysemu/numa.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" #include "sysemu/tpm.h" #include "sysemu/kvm.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "qemu/bitops.h" #include "qemu/error-report.h" #include "qemu/module.h" diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c index 8db6cfd47f..85f25d15db 100644 --- a/hw/arm/xilinx_zynq.c +++ b/hw/arm/xilinx_zynq.c @@ -22,7 +22,6 @@ #include "hw/sysbus.h" #include "hw/arm/boot.h" #include "net/net.h" -#include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/block/flash.h" diff --git a/hw/arm/xlnx-versal-virt.c b/hw/arm/xlnx-versal-virt.c index 8482cd6196..5bca360dce 100644 --- a/hw/arm/xlnx-versal-virt.c +++ b/hw/arm/xlnx-versal-virt.c @@ -10,11 +10,9 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "sysemu/device_tree.h" -#include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/sysbus.h" #include "hw/arm/sysbus-fdt.h" diff --git a/hw/arm/xlnx-versal.c b/hw/arm/xlnx-versal.c index 79609692e4..fb776834f7 100644 --- a/hw/arm/xlnx-versal.c +++ b/hw/arm/xlnx-versal.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "qemu/log.h" #include "qemu/module.h" #include "hw/sysbus.h" #include "net/net.h" diff --git a/hw/arm/xlnx-zcu102.c b/hw/arm/xlnx-zcu102.c index a9db25eb99..6c6cb02e86 100644 --- a/hw/arm/xlnx-zcu102.c +++ b/hw/arm/xlnx-zcu102.c @@ -17,7 +17,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/arm/xlnx-zynqmp.h" #include "hw/boards.h" #include "qemu/error-report.h" diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c index 7f01284a5c..3597e8db4d 100644 --- a/hw/arm/xlnx-zynqmp.c +++ b/hw/arm/xlnx-zynqmp.c @@ -18,11 +18,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/arm/xlnx-zynqmp.h" #include "hw/intc/arm_gic_common.h" #include "hw/boards.h" -#include "exec/address-spaces.h" #include "sysemu/kvm.h" #include "sysemu/sysemu.h" #include "kvm_arm.h" diff --git a/hw/arm/z2.c b/hw/arm/z2.c index 5099bd8380..9c1e876207 100644 --- a/hw/arm/z2.c +++ b/hw/arm/z2.c @@ -162,7 +162,7 @@ static void zipit_lcd_realize(SSIPeripheral *dev, Error **errp) z->pos = 0; } -static VMStateDescription vmstate_zipit_lcd_state = { +static const VMStateDescription vmstate_zipit_lcd_state = { .name = "zipit-lcd", .version_id = 2, .minimum_version_id = 2, @@ -268,7 +268,7 @@ static uint8_t aer915_recv(I2CSlave *slave) return retval; } -static VMStateDescription vmstate_aer915_state = { +static const VMStateDescription vmstate_aer915_state = { .name = "aer915", .version_id = 1, .minimum_version_id = 1, diff --git a/hw/avr/arduino.c b/hw/avr/arduino.c index 3ff31492fa..48ef478346 100644 --- a/hw/avr/arduino.c +++ b/hw/avr/arduino.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "hw/boards.h" #include "atmega.h" #include "boot.h" #include "qom/object.h" diff --git a/hw/avr/atmega.c b/hw/avr/atmega.c index 44c6afebbb..80b8a41cb5 100644 --- a/hw/avr/atmega.c +++ b/hw/avr/atmega.c @@ -18,7 +18,6 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qom/object.h" -#include "hw/boards.h" /* FIXME memory_region_allocate_system_memory for sram */ #include "hw/misc/unimp.h" #include "atmega.h" diff --git a/hw/block/ecc.c b/hw/block/ecc.c index 1a182367ee..6e0d63842c 100644 --- a/hw/block/ecc.c +++ b/hw/block/ecc.c @@ -78,7 +78,7 @@ void ecc_reset(ECCState *s) } /* Save/restore */ -VMStateDescription vmstate_ecc_state = { +const VMStateDescription vmstate_ecc_state = { .name = "ecc-state", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c index 183d3f44c2..b77503dc84 100644 --- a/hw/block/m25p80.c +++ b/hw/block/m25p80.c @@ -259,6 +259,8 @@ static const FlashPartInfo known_devices[] = { { INFO_STACKED("n25q00a", 0x20bb21, 0x1000, 64 << 10, 2048, ER_4K, 4) }, { INFO_STACKED("mt25ql01g", 0x20ba21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, { INFO_STACKED("mt25qu01g", 0x20bb21, 0x1040, 64 << 10, 2048, ER_4K, 2) }, + { INFO_STACKED("mt25ql02g", 0x20ba22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, + { INFO_STACKED("mt25qu02g", 0x20bb22, 0x1040, 64 << 10, 4096, ER_4K | ER_32K, 2) }, /* Spansion -- single (large) sector size only, at least * for the chips listed here (without boot sectors). diff --git a/hw/block/nvme-subsys.c b/hw/block/nvme-subsys.c index 283a97b79d..9604c19117 100644 --- a/hw/block/nvme-subsys.c +++ b/hw/block/nvme-subsys.c @@ -17,7 +17,6 @@ #include "hw/block/block.h" #include "block/aio.h" #include "block/accounting.h" -#include "sysemu/sysemu.h" #include "hw/pci/pci.h" #include "nvme.h" #include "nvme-subsys.h" diff --git a/hw/char/mchp_pfsoc_mmuart.c b/hw/char/mchp_pfsoc_mmuart.c index 8a002b0a19..2facf85c2d 100644 --- a/hw/char/mchp_pfsoc_mmuart.c +++ b/hw/char/mchp_pfsoc_mmuart.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "chardev/char.h" -#include "exec/address-spaces.h" #include "hw/char/mchp_pfsoc_mmuart.h" static uint64_t mchp_pfsoc_mmuart_read(void *opaque, hwaddr addr, unsigned size) diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index ba1af1cfc4..ddae738d56 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -23,7 +23,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/log.h" -#include "hw/sysbus.h" #include "hw/char/riscv_htif.h" #include "hw/char/serial.h" #include "chardev/char.h" diff --git a/hw/char/sifive_uart.c b/hw/char/sifive_uart.c index 3a00ba7f00..fe12666789 100644 --- a/hw/char/sifive_uart.c +++ b/hw/char/sifive_uart.c @@ -19,10 +19,8 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/log.h" -#include "hw/sysbus.h" #include "chardev/char.h" #include "chardev/char-fe.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/char/sifive_uart.h" diff --git a/hw/char/spapr_vty.c b/hw/char/spapr_vty.c index 79eaa2fa52..91eae1a598 100644 --- a/hw/char/spapr_vty.c +++ b/hw/char/spapr_vty.c @@ -2,7 +2,6 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" -#include "cpu.h" #include "migration/vmstate.h" #include "chardev/char-fe.h" #include "hw/ppc/spapr.h" diff --git a/hw/char/virtio-serial-bus.c b/hw/char/virtio-serial-bus.c index b20038991a..dd6bc27b3b 100644 --- a/hw/char/virtio-serial-bus.c +++ b/hw/char/virtio-serial-bus.c @@ -28,7 +28,6 @@ #include "qemu/error-report.h" #include "qemu/queue.h" #include "hw/qdev-properties.h" -#include "hw/sysbus.h" #include "trace.h" #include "hw/virtio/virtio-serial.h" #include "hw/virtio/virtio-access.h" diff --git a/hw/core/generic-loader.c b/hw/core/generic-loader.c index 2b2a7b5e9a..d14f932eea 100644 --- a/hw/core/generic-loader.c +++ b/hw/core/generic-loader.c @@ -32,7 +32,6 @@ #include "qemu/osdep.h" #include "hw/core/cpu.h" -#include "hw/sysbus.h" #include "sysemu/dma.h" #include "sysemu/reset.h" #include "hw/boards.h" diff --git a/hw/core/guest-loader.c b/hw/core/guest-loader.c index bde44e27b4..d3f9d1a06e 100644 --- a/hw/core/guest-loader.c +++ b/hw/core/guest-loader.c @@ -26,7 +26,6 @@ #include "qemu/osdep.h" #include "hw/core/cpu.h" -#include "hw/sysbus.h" #include "sysemu/dma.h" #include "hw/loader.h" #include "hw/qdev-properties.h" diff --git a/hw/core/loader.c b/hw/core/loader.c index d3e5f3b423..5b34869a54 100644 --- a/hw/core/loader.c +++ b/hw/core/loader.c @@ -57,7 +57,6 @@ #include "hw/loader.h" #include "hw/nvram/fw_cfg.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "hw/boards.h" #include "qemu/cutils.h" #include "sysemu/runstate.h" diff --git a/hw/core/machine-qmp-cmds.c b/hw/core/machine-qmp-cmds.c index 68a942595a..a36c96608f 100644 --- a/hw/core/machine-qmp-cmds.c +++ b/hw/core/machine-qmp-cmds.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "hw/boards.h" #include "qapi/error.h" #include "qapi/qapi-builtin-visit.h" @@ -22,7 +21,6 @@ #include "sysemu/hw_accel.h" #include "sysemu/numa.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" static void cpustate_to_cpuinfo_s390(CpuInfoS390 *info, const CPUState *cpu) { diff --git a/hw/core/null-machine.c b/hw/core/null-machine.c index 7e693523d7..f586a4bef5 100644 --- a/hw/core/null-machine.c +++ b/hw/core/null-machine.c @@ -14,7 +14,6 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" #include "hw/boards.h" -#include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "hw/core/cpu.h" diff --git a/hw/core/numa.c b/hw/core/numa.c index 68cee65f61..ac6bed5817 100644 --- a/hw/core/numa.c +++ b/hw/core/numa.c @@ -26,7 +26,6 @@ #include "qemu/units.h" #include "sysemu/hostmem.h" #include "sysemu/numa.h" -#include "sysemu/sysemu.h" #include "exec/cpu-common.h" #include "exec/ramlist.h" #include "qemu/bitmap.h" diff --git a/hw/cris/axis_dev88.c b/hw/cris/axis_dev88.c index af5a0e3517..d82050d927 100644 --- a/hw/cris/axis_dev88.c +++ b/hw/cris/axis_dev88.c @@ -34,7 +34,6 @@ #include "hw/loader.h" #include "elf.h" #include "boot.h" -#include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "sysemu/sysemu.h" diff --git a/hw/display/next-fb.c b/hw/display/next-fb.c index e2d895109d..dd6a1aa8ae 100644 --- a/hw/display/next-fb.c +++ b/hw/display/next-fb.c @@ -24,8 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "ui/console.h" -#include "hw/hw.h" -#include "hw/boards.h" #include "hw/loader.h" #include "framebuffer.h" #include "ui/pixel_ops.h" diff --git a/hw/display/qxl.c b/hw/display/qxl.c index 93907e82a3..2ba75637ec 100644 --- a/hw/display/qxl.c +++ b/hw/display/qxl.c @@ -2384,7 +2384,7 @@ static bool qxl_monitors_config_needed(void *opaque) } -static VMStateDescription qxl_memslot = { +static const VMStateDescription qxl_memslot = { .name = "qxl-memslot", .version_id = QXL_SAVE_VERSION, .minimum_version_id = QXL_SAVE_VERSION, @@ -2396,7 +2396,7 @@ static VMStateDescription qxl_memslot = { } }; -static VMStateDescription qxl_surface = { +static const VMStateDescription qxl_surface = { .name = "qxl-surface", .version_id = QXL_SAVE_VERSION, .minimum_version_id = QXL_SAVE_VERSION, @@ -2414,7 +2414,7 @@ static VMStateDescription qxl_surface = { } }; -static VMStateDescription qxl_vmstate_monitors_config = { +static const VMStateDescription qxl_vmstate_monitors_config = { .name = "qxl/monitors-config", .version_id = 1, .minimum_version_id = 1, @@ -2425,7 +2425,7 @@ static VMStateDescription qxl_vmstate_monitors_config = { }, }; -static VMStateDescription qxl_vmstate = { +static const VMStateDescription qxl_vmstate = { .name = "qxl", .version_id = QXL_SAVE_VERSION, .minimum_version_id = QXL_SAVE_VERSION, diff --git a/hw/dma/pl080.c b/hw/dma/pl080.c index f1a586b1d7..2627307cc8 100644 --- a/hw/dma/pl080.c +++ b/hw/dma/pl080.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "exec/address-spaces.h" #include "qemu/log.h" #include "qemu/module.h" #include "hw/dma/pl080.h" diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c index b3707ff3de..fa896f7edf 100644 --- a/hw/dma/pxa2xx_dma.c +++ b/hw/dma/pxa2xx_dma.c @@ -525,7 +525,7 @@ static bool is_version_0(void *opaque, int version_id) return version_id == 0; } -static VMStateDescription vmstate_pxa2xx_dma_chan = { +static const VMStateDescription vmstate_pxa2xx_dma_chan = { .name = "pxa2xx_dma_chan", .version_id = 1, .minimum_version_id = 1, @@ -540,7 +540,7 @@ static VMStateDescription vmstate_pxa2xx_dma_chan = { }, }; -static VMStateDescription vmstate_pxa2xx_dma = { +static const VMStateDescription vmstate_pxa2xx_dma = { .name = "pxa2xx_dma", .version_id = 1, .minimum_version_id = 0, diff --git a/hw/dma/sifive_pdma.c b/hw/dma/sifive_pdma.c index e1f6fedbda..9b2ac2017d 100644 --- a/hw/dma/sifive_pdma.c +++ b/hw/dma/sifive_pdma.c @@ -24,7 +24,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" diff --git a/hw/dma/xlnx_csu_dma.c b/hw/dma/xlnx_csu_dma.c index 98324dadcd..797b4fed8f 100644 --- a/hw/dma/xlnx_csu_dma.c +++ b/hw/dma/xlnx_csu_dma.c @@ -21,7 +21,6 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c index 5b82c9440d..eab96dd84e 100644 --- a/hw/hppa/dino.c +++ b/hw/hppa/dino.c @@ -14,13 +14,11 @@ #include "qemu/module.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/irq.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "migration/vmstate.h" #include "hppa_sys.h" -#include "exec/address-spaces.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c index 1a85657948..88c3791eb6 100644 --- a/hw/hppa/lasi.c +++ b/hw/hppa/lasi.c @@ -13,9 +13,7 @@ #include "qemu/units.h" #include "qemu/log.h" #include "qapi/error.h" -#include "cpu.h" #include "trace.h" -#include "hw/hw.h" #include "hw/irq.h" #include "sysemu/sysemu.h" #include "sysemu/runstate.h" @@ -24,7 +22,6 @@ #include "hw/char/parallel.h" #include "hw/char/serial.h" #include "hw/input/lasips2.h" -#include "exec/address-spaces.h" #include "migration/vmstate.h" #include "qom/object.h" diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index f2b71db9bd..2a46af5bc9 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -9,7 +9,6 @@ #include "cpu.h" #include "elf.h" #include "hw/loader.h" -#include "hw/boards.h" #include "qemu/error-report.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" diff --git a/hw/i2c/aspeed_i2c.c b/hw/i2c/aspeed_i2c.c index 518a3f5c6f..8d276d9ed3 100644 --- a/hw/i2c/aspeed_i2c.c +++ b/hw/i2c/aspeed_i2c.c @@ -601,7 +601,7 @@ static void aspeed_i2c_bus_write(void *opaque, hwaddr offset, break; } - bus->dma_addr = value & 0xfffffffc; + bus->dma_addr = value & 0x3ffffffc; break; case I2CD_DMA_LEN: @@ -816,7 +816,8 @@ static void aspeed_i2c_realize(DeviceState *dev, Error **errp) return; } - address_space_init(&s->dram_as, s->dram_mr, "dma-dram"); + address_space_init(&s->dram_as, s->dram_mr, + TYPE_ASPEED_I2C "-dma-dram"); } } diff --git a/hw/i2c/mpc_i2c.c b/hw/i2c/mpc_i2c.c index 720d2331e9..845392505f 100644 --- a/hw/i2c/mpc_i2c.c +++ b/hw/i2c/mpc_i2c.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "hw/i2c/i2c.h" #include "hw/irq.h" -#include "qemu/log.h" #include "qemu/module.h" #include "hw/sysbus.h" #include "migration/vmstate.h" diff --git a/hw/i386/acpi-build.c b/hw/i386/acpi-build.c index de98750aef..bfecb0038c 100644 --- a/hw/i386/acpi-build.c +++ b/hw/i386/acpi-build.c @@ -43,7 +43,6 @@ #include "sysemu/tpm.h" #include "hw/acpi/tpm.h" #include "hw/acpi/vmgenid.h" -#include "hw/boards.h" #include "sysemu/tpm_backend.h" #include "hw/rtc/mc146818rtc_regs.h" #include "migration/vmstate.h" diff --git a/hw/i386/acpi-microvm.c b/hw/i386/acpi-microvm.c index ccd3303aac..1a0f77b911 100644 --- a/hw/i386/acpi-microvm.c +++ b/hw/i386/acpi-microvm.c @@ -30,7 +30,6 @@ #include "hw/acpi/bios-linker-loader.h" #include "hw/acpi/generic_event_device.h" #include "hw/acpi/utils.h" -#include "hw/boards.h" #include "hw/i386/fw_cfg.h" #include "hw/i386/microvm.h" #include "hw/pci/pci.h" diff --git a/hw/i386/intel_iommu.c b/hw/i386/intel_iommu.c index 6be8f32918..209b3f5553 100644 --- a/hw/i386/intel_iommu.c +++ b/hw/i386/intel_iommu.c @@ -24,14 +24,12 @@ #include "qemu/main-loop.h" #include "qapi/error.h" #include "hw/sysbus.h" -#include "exec/address-spaces.h" #include "intel_iommu_internal.h" #include "hw/pci/pci.h" #include "hw/pci/pci_bus.h" #include "hw/qdev-properties.h" #include "hw/i386/pc.h" #include "hw/i386/apic-msidef.h" -#include "hw/boards.h" #include "hw/i386/x86-iommu.h" #include "hw/pci-host/q35.h" #include "sysemu/kvm.h" diff --git a/hw/i386/kvm/apic.c b/hw/i386/kvm/apic.c index 3dbff2be2e..52ff490910 100644 --- a/hw/i386/kvm/apic.c +++ b/hw/i386/kvm/apic.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/i386/apic_internal.h" #include "hw/pci/msi.h" #include "sysemu/hw_accel.h" diff --git a/hw/i386/kvm/clock.c b/hw/i386/kvm/clock.c index 51872dd84c..efbc1e0d12 100644 --- a/hw/i386/kvm/clock.c +++ b/hw/i386/kvm/clock.c @@ -14,7 +14,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/host-utils.h" #include "qemu/module.h" #include "sysemu/kvm.h" diff --git a/hw/i386/kvm/ioapic.c b/hw/i386/kvm/ioapic.c index dfc3c98005..71a563181e 100644 --- a/hw/i386/kvm/ioapic.c +++ b/hw/i386/kvm/ioapic.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "monitor/monitor.h" #include "hw/i386/x86.h" -#include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/i386/ioapic_internal.h" #include "hw/i386/apic_internal.h" diff --git a/hw/i386/kvmvapic.c b/hw/i386/kvmvapic.c index 46315445d2..43f8a8f679 100644 --- a/hw/i386/kvmvapic.c +++ b/hw/i386/kvmvapic.c @@ -11,7 +11,6 @@ #include "qemu/osdep.h" #include "qemu/module.h" -#include "cpu.h" #include "sysemu/sysemu.h" #include "sysemu/cpus.h" #include "sysemu/hw_accel.h" diff --git a/hw/i386/microvm.c b/hw/i386/microvm.c index edf2b0f061..aba0c83219 100644 --- a/hw/i386/microvm.c +++ b/hw/i386/microvm.c @@ -49,7 +49,6 @@ #include "hw/pci-host/gpex.h" #include "hw/usb/xhci.h" -#include "cpu.h" #include "elf.h" #include "kvm/kvm_i386.h" #include "hw/xen/start_info.h" diff --git a/hw/i386/pc.c b/hw/i386/pc.c index 364816efc9..8cfaf216e7 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -65,7 +65,6 @@ #include "hw/xen/start_info.h" #include "ui/qemu-spice.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "sysemu/arch_init.h" #include "qemu/bitmap.h" #include "qemu/config-file.h" @@ -74,7 +73,6 @@ #include "qemu/cutils.h" #include "hw/acpi/acpi.h" #include "hw/acpi/cpu_hotplug.h" -#include "hw/boards.h" #include "acpi-build.h" #include "hw/mem/pc-dimm.h" #include "hw/mem/nvdimm.h" diff --git a/hw/i386/pc_piix.c b/hw/i386/pc_piix.c index 4e8edffeaf..5ac2edbf1f 100644 --- a/hw/i386/pc_piix.c +++ b/hw/i386/pc_piix.c @@ -42,15 +42,12 @@ #include "hw/irq.h" #include "sysemu/kvm.h" #include "hw/kvm/clock.h" -#include "sysemu/sysemu.h" #include "hw/sysbus.h" #include "sysemu/arch_init.h" #include "hw/i2c/smbus_eeprom.h" #include "hw/xen/xen-x86.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "hw/acpi/acpi.h" -#include "cpu.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/xen.h" diff --git a/hw/i386/pc_q35.c b/hw/i386/pc_q35.c index 458ed41c65..46a0f196f4 100644 --- a/hw/i386/pc_q35.c +++ b/hw/i386/pc_q35.c @@ -38,7 +38,6 @@ #include "hw/kvm/clock.h" #include "hw/pci-host/q35.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" #include "hw/i386/x86.h" #include "hw/i386/pc.h" #include "hw/i386/ich9.h" diff --git a/hw/i386/pc_sysfw.c b/hw/i386/pc_sysfw.c index 9fe72b370e..6ce37a2b05 100644 --- a/hw/i386/pc_sysfw.c +++ b/hw/i386/pc_sysfw.c @@ -35,7 +35,6 @@ #include "hw/i386/pc.h" #include "hw/loader.h" #include "hw/qdev-properties.h" -#include "sysemu/sysemu.h" #include "hw/block/flash.h" #include "sysemu/kvm.h" #include "sysemu/sev.h" diff --git a/hw/i386/vmport.c b/hw/i386/vmport.c index 490a57f52c..7cc75dbc6d 100644 --- a/hw/i386/vmport.c +++ b/hw/i386/vmport.c @@ -37,7 +37,6 @@ #include "sysemu/hw_accel.h" #include "sysemu/qtest.h" #include "qemu/log.h" -#include "cpu.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/i386/x86-iommu.c b/hw/i386/x86-iommu.c index 5f4301639c..86ad03972e 100644 --- a/hw/i386/x86-iommu.c +++ b/hw/i386/x86-iommu.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" -#include "hw/boards.h" #include "hw/i386/x86-iommu.h" #include "hw/qdev-properties.h" #include "hw/i386/pc.h" diff --git a/hw/i386/xen/xen-hvm.c b/hw/i386/xen/xen-hvm.c index 7ce672e5a5..c53fa17c50 100644 --- a/hw/i386/xen/xen-hvm.c +++ b/hw/i386/xen/xen-hvm.c @@ -33,7 +33,6 @@ #include "sysemu/xen.h" #include "sysemu/xen-mapcache.h" #include "trace.h" -#include "exec/address-spaces.h" #include <xen/hvm/ioreq.h> #include <xen/hvm/e820.h> diff --git a/hw/i386/xen/xen_platform.c b/hw/i386/xen/xen_platform.c index 01ae1fb161..72028449ba 100644 --- a/hw/i386/xen/xen_platform.c +++ b/hw/i386/xen/xen_platform.c @@ -27,12 +27,10 @@ #include "qapi/error.h" #include "hw/ide.h" #include "hw/pci/pci.h" -#include "hw/irq.h" #include "hw/xen/xen_common.h" #include "migration/vmstate.h" #include "hw/xen/xen-legacy-backend.h" #include "trace.h" -#include "exec/address-spaces.h" #include "sysemu/xen.h" #include "sysemu/block-backend.h" #include "qemu/error-report.h" diff --git a/hw/ide/Kconfig b/hw/ide/Kconfig index 5d9106b1ac..8e2c893454 100644 --- a/hw/ide/Kconfig +++ b/hw/ide/Kconfig @@ -41,6 +41,7 @@ config IDE_VIA config MICRODRIVE bool select IDE_QDEV + depends on PCMCIA config AHCI bool diff --git a/hw/ide/ahci_internal.h b/hw/ide/ahci_internal.h index 7f32e87731..109de9e2d1 100644 --- a/hw/ide/ahci_internal.h +++ b/hw/ide/ahci_internal.h @@ -26,7 +26,6 @@ #include "hw/ide/ahci.h" #include "hw/ide/internal.h" -#include "hw/sysbus.h" #include "hw/pci/pci.h" #define AHCI_MEM_BAR_SIZE 0x1000 diff --git a/hw/input/lasips2.c b/hw/input/lasips2.c index 0786e57338..e7faf24058 100644 --- a/hw/input/lasips2.c +++ b/hw/input/lasips2.c @@ -24,12 +24,9 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "hw/qdev-properties.h" -#include "hw/hw.h" #include "hw/input/ps2.h" #include "hw/input/lasips2.h" -#include "hw/sysbus.h" #include "exec/hwaddr.h" -#include "sysemu/sysemu.h" #include "trace.h" #include "exec/address-spaces.h" #include "migration/vmstate.h" diff --git a/hw/intc/apic.c b/hw/intc/apic.c index f4f50f974e..3df11c34d6 100644 --- a/hw/intc/apic.c +++ b/hw/intc/apic.c @@ -17,7 +17,6 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/> */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/thread.h" #include "hw/i386/apic_internal.h" #include "hw/i386/apic.h" diff --git a/hw/intc/apic_common.c b/hw/intc/apic_common.c index 97dd96dffa..2a20982066 100644 --- a/hw/intc/apic_common.c +++ b/hw/intc/apic_common.c @@ -22,7 +22,6 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" -#include "cpu.h" #include "qapi/visitor.h" #include "hw/i386/apic.h" #include "hw/i386/apic_internal.h" diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 9494185cf4..7d2a13273a 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -22,8 +22,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" -#include "hw/sysbus.h" #include "migration/blocker.h" #include "sysemu/kvm.h" #include "kvm_arm.h" diff --git a/hw/intc/arm_gicv3.c b/hw/intc/arm_gicv3.c index 66eaa97198..d63f8af604 100644 --- a/hw/intc/arm_gicv3.c +++ b/hw/intc/arm_gicv3.c @@ -18,7 +18,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "hw/sysbus.h" #include "hw/intc/arm_gicv3.h" #include "gicv3_internal.h" diff --git a/hw/intc/arm_gicv3_kvm.c b/hw/intc/arm_gicv3_kvm.c index 65a4c880a3..5c09f00dec 100644 --- a/hw/intc/arm_gicv3_kvm.c +++ b/hw/intc/arm_gicv3_kvm.c @@ -22,7 +22,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/intc/arm_gicv3_common.h" -#include "hw/sysbus.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "sysemu/kvm.h" diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 0d8426dafc..c4287d82d8 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "migration/vmstate.h" #include "qemu/timer.h" diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index 984334fa7b..3bfe2544b7 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "hw/irq.h" #include "hw/sysbus.h" -#include "cpu.h" #include "hw/qdev-properties.h" #include "hw/sparc/grlib.h" diff --git a/hw/intc/imx_gpcv2.c b/hw/intc/imx_gpcv2.c index 17007a4078..237d5f97eb 100644 --- a/hw/intc/imx_gpcv2.c +++ b/hw/intc/imx_gpcv2.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "hw/intc/imx_gpcv2.h" #include "migration/vmstate.h" -#include "qemu/log.h" #include "qemu/module.h" #define GPC_PU_PGC_SW_PUP_REQ 0x0f8 diff --git a/hw/intc/ompic.c b/hw/intc/ompic.c index 1731a10683..1f10314807 100644 --- a/hw/intc/ompic.c +++ b/hw/intc/ompic.c @@ -7,7 +7,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qapi/error.h" #include "hw/irq.h" diff --git a/hw/intc/openpic.c b/hw/intc/openpic.c index 65970e1b37..9b4c17854d 100644 --- a/hw/intc/openpic.c +++ b/hw/intc/openpic.c @@ -47,7 +47,6 @@ #include "qapi/error.h" #include "qemu/bitops.h" #include "qapi/qmp/qerror.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/timer.h" #include "qemu/error-report.h" diff --git a/hw/intc/openpic_kvm.c b/hw/intc/openpic_kvm.c index e1a39e33cb..21da680389 100644 --- a/hw/intc/openpic_kvm.c +++ b/hw/intc/openpic_kvm.c @@ -24,9 +24,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include <sys/ioctl.h> -#include "exec/address-spaces.h" #include "hw/ppc/openpic.h" #include "hw/ppc/openpic_kvm.h" #include "hw/pci/msi.h" diff --git a/hw/intc/s390_flic.c b/hw/intc/s390_flic.c index aacdb1bbc2..74e02858d4 100644 --- a/hw/intc/s390_flic.c +++ b/hw/intc/s390_flic.c @@ -20,7 +20,6 @@ #include "hw/qdev-properties.h" #include "hw/s390x/css.h" #include "trace.h" -#include "cpu.h" #include "qapi/error.h" #include "hw/s390x/s390-virtio-ccw.h" diff --git a/hw/intc/s390_flic_kvm.c b/hw/intc/s390_flic_kvm.c index b3fb9f8395..929cfa3a68 100644 --- a/hw/intc/s390_flic_kvm.c +++ b/hw/intc/s390_flic_kvm.c @@ -11,13 +11,11 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "kvm_s390x.h" #include <sys/ioctl.h> #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" -#include "hw/sysbus.h" #include "sysemu/kvm.h" #include "hw/s390x/s390_flic.h" #include "hw/s390x/adapter.h" diff --git a/hw/intc/sifive_plic.c b/hw/intc/sifive_plic.c index 97a1a27a9a..78903beb06 100644 --- a/hw/intc/sifive_plic.c +++ b/hw/intc/sifive_plic.c @@ -25,11 +25,9 @@ #include "qemu/error-report.h" #include "hw/sysbus.h" #include "hw/pci/msi.h" -#include "hw/boards.h" #include "hw/qdev-properties.h" #include "hw/intc/sifive_plic.h" #include "target/riscv/cpu.h" -#include "sysemu/sysemu.h" #include "migration/vmstate.h" #define RISCV_DEBUG_PLIC 0 diff --git a/hw/intc/xics.c b/hw/intc/xics.c index 68f9d44feb..48a835eab7 100644 --- a/hw/intc/xics.c +++ b/hw/intc/xics.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "trace.h" #include "qemu/timer.h" #include "hw/ppc/xics.h" diff --git a/hw/intc/xics_kvm.c b/hw/intc/xics_kvm.c index 570d635bcc..f5bfc501bc 100644 --- a/hw/intc/xics_kvm.c +++ b/hw/intc/xics_kvm.c @@ -28,7 +28,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu-common.h" -#include "cpu.h" #include "trace.h" #include "sysemu/kvm.h" #include "hw/ppc/spapr.h" diff --git a/hw/intc/xics_spapr.c b/hw/intc/xics_spapr.c index 8ae4f41459..37b2d99977 100644 --- a/hw/intc/xics_spapr.c +++ b/hw/intc/xics_spapr.c @@ -26,7 +26,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "trace.h" #include "qemu/timer.h" #include "hw/ppc/spapr.h" diff --git a/hw/ipmi/isa_ipmi_bt.c b/hw/ipmi/isa_ipmi_bt.c index b7c2ad557b..02625eb94e 100644 --- a/hw/ipmi/isa_ipmi_bt.c +++ b/hw/ipmi/isa_ipmi_bt.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qapi/error.h" #include "hw/irq.h" diff --git a/hw/ipmi/isa_ipmi_kcs.c b/hw/ipmi/isa_ipmi_kcs.c index 7dd6bf0040..3b23ad08b3 100644 --- a/hw/ipmi/isa_ipmi_kcs.c +++ b/hw/ipmi/isa_ipmi_kcs.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qapi/error.h" #include "hw/irq.h" diff --git a/hw/isa/isa-superio.c b/hw/isa/isa-superio.c index 179c185695..c81bfe58ef 100644 --- a/hw/isa/isa-superio.c +++ b/hw/isa/isa-superio.c @@ -14,7 +14,6 @@ #include "qemu/error-report.h" #include "qemu/module.h" #include "qapi/error.h" -#include "sysemu/sysemu.h" #include "sysemu/blockdev.h" #include "chardev/char.h" #include "hw/block/fdc.h" diff --git a/hw/isa/lpc_ich9.c b/hw/isa/lpc_ich9.c index 3963b73520..5f9de0239c 100644 --- a/hw/isa/lpc_ich9.c +++ b/hw/isa/lpc_ich9.c @@ -34,7 +34,6 @@ #include "qapi/visitor.h" #include "qemu/range.h" #include "hw/isa/isa.h" -#include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/irq.h" #include "hw/isa/apm.h" @@ -45,7 +44,6 @@ #include "hw/acpi/ich9.h" #include "hw/pci/pci_bus.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "hw/core/cpu.h" diff --git a/hw/isa/piix3.c b/hw/isa/piix3.c index f46ccae25c..dab901c9ad 100644 --- a/hw/isa/piix3.c +++ b/hw/isa/piix3.c @@ -29,7 +29,6 @@ #include "hw/isa/isa.h" #include "hw/xen/xen.h" #include "sysemu/xen.h" -#include "sysemu/sysemu.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" #include "migration/vmstate.h" diff --git a/hw/isa/piix4.c b/hw/isa/piix4.c index b3b6a4378a..0fe7b69bc4 100644 --- a/hw/isa/piix4.c +++ b/hw/isa/piix4.c @@ -29,7 +29,6 @@ #include "hw/southbridge/piix.h" #include "hw/pci/pci.h" #include "hw/isa/isa.h" -#include "hw/sysbus.h" #include "hw/intc/i8259.h" #include "hw/dma/i8257.h" #include "hw/timer/i8254.h" @@ -268,8 +267,9 @@ DeviceState *piix4_create(PCIBus *pci_bus, ISABus **isa_bus, I2CBus **smbus) pci_create_simple(pci_bus, devfn + 2, "piix4-usb-uhci"); if (smbus) { *smbus = piix4_pm_init(pci_bus, devfn + 3, 0x1100, - isa_get_irq(NULL, 9), NULL, 0, NULL); - } + qdev_get_gpio_in_named(dev, "isa", 9), + NULL, 0, NULL); + } return dev; } diff --git a/hw/isa/vt82c686.c b/hw/isa/vt82c686.c index 7b2e90c7e1..f57f3e7067 100644 --- a/hw/isa/vt82c686.c +++ b/hw/isa/vt82c686.c @@ -33,7 +33,6 @@ #include "qemu/module.h" #include "qemu/range.h" #include "qemu/timer.h" -#include "exec/address-spaces.h" #include "trace.h" #define TYPE_VIA_PM "via-pm" diff --git a/hw/lm32/lm32_boards.c b/hw/lm32/lm32_boards.c index b5d97dd53e..2961e4c2b4 100644 --- a/hw/lm32/lm32_boards.c +++ b/hw/lm32/lm32_boards.c @@ -30,7 +30,6 @@ #include "elf.h" #include "lm32_hwsetup.h" #include "lm32.h" -#include "exec/address-spaces.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" diff --git a/hw/lm32/milkymist.c b/hw/lm32/milkymist.c index 72d1326531..bef7855328 100644 --- a/hw/lm32/milkymist.c +++ b/hw/lm32/milkymist.c @@ -37,7 +37,6 @@ #include "hw/display/milkymist_tmu2.h" #include "hw/sd/sd.h" #include "lm32.h" -#include "exec/address-spaces.h" #include "qemu/cutils.h" #define BIOS_FILENAME "mmone-bios.bin" diff --git a/hw/m68k/an5206.c b/hw/m68k/an5206.c index 673898b0ea..11ae4c9795 100644 --- a/hw/m68k/an5206.c +++ b/hw/m68k/an5206.c @@ -13,7 +13,6 @@ #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/m68k/mcf5208.c b/hw/m68k/mcf5208.c index 7a03c71059..93812ee206 100644 --- a/hw/m68k/mcf5208.c +++ b/hw/m68k/mcf5208.c @@ -26,7 +26,6 @@ #include "hw/loader.h" #include "hw/sysbus.h" #include "elf.h" -#include "exec/address-spaces.h" #define SYS_FREQ 166666666 diff --git a/hw/m68k/mcf_intc.c b/hw/m68k/mcf_intc.c index cf02f57a71..4cd30188c0 100644 --- a/hw/m68k/mcf_intc.c +++ b/hw/m68k/mcf_intc.c @@ -11,7 +11,6 @@ #include "qemu/module.h" #include "qemu/log.h" #include "cpu.h" -#include "hw/hw.h" #include "hw/irq.h" #include "hw/sysbus.h" #include "hw/m68k/mcf.h" diff --git a/hw/m68k/next-cube.c b/hw/m68k/next-cube.c index 92b45d760f..de951ffe5d 100644 --- a/hw/m68k/next-cube.c +++ b/hw/m68k/next-cube.c @@ -10,9 +10,7 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "exec/hwaddr.h" -#include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "hw/irq.h" diff --git a/hw/m68k/next-kbd.c b/hw/m68k/next-kbd.c index c11b5281f1..0544160e91 100644 --- a/hw/m68k/next-kbd.c +++ b/hw/m68k/next-kbd.c @@ -29,12 +29,9 @@ #include "qemu/osdep.h" #include "qemu/log.h" -#include "exec/address-spaces.h" -#include "hw/hw.h" #include "hw/sysbus.h" #include "hw/m68k/next-cube.h" #include "ui/console.h" -#include "sysemu/sysemu.h" #include "migration/vmstate.h" #include "qom/object.h" diff --git a/hw/m68k/q800.c b/hw/m68k/q800.c index 4d2e866eec..11376daa85 100644 --- a/hw/m68k/q800.c +++ b/hw/m68k/q800.c @@ -26,14 +26,11 @@ #include "qemu/datadir.h" #include "sysemu/sysemu.h" #include "cpu.h" -#include "hw/hw.h" #include "hw/boards.h" -#include "hw/irq.h" #include "hw/or-irq.h" #include "elf.h" #include "hw/loader.h" #include "ui/console.h" -#include "exec/address-spaces.h" #include "hw/char/escc.h" #include "hw/sysbus.h" #include "hw/scsi/esp.h" diff --git a/hw/m68k/virt.c b/hw/m68k/virt.c index e9a5d4c69b..4e8bce5aa6 100644 --- a/hw/m68k/virt.c +++ b/hw/m68k/virt.c @@ -12,14 +12,11 @@ #include "qemu-common.h" #include "sysemu/sysemu.h" #include "cpu.h" -#include "hw/hw.h" #include "hw/boards.h" -#include "hw/irq.h" #include "hw/qdev-properties.h" #include "elf.h" #include "hw/loader.h" #include "ui/console.h" -#include "exec/address-spaces.h" #include "hw/sysbus.h" #include "standard-headers/asm-m68k/bootinfo.h" #include "standard-headers/asm-m68k/bootinfo-virt.h" diff --git a/hw/mem/sparse-mem.c b/hw/mem/sparse-mem.c index a13ac74dd9..e6640eb8e7 100644 --- a/hw/mem/sparse-mem.c +++ b/hw/mem/sparse-mem.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" -#include "exec/address-spaces.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "qapi/error.h" diff --git a/hw/microblaze/boot.c b/hw/microblaze/boot.c index caaba1aa4c..8821d009f1 100644 --- a/hw/microblaze/boot.c +++ b/hw/microblaze/boot.c @@ -33,7 +33,6 @@ #include "qemu/error-report.h" #include "sysemu/device_tree.h" #include "sysemu/reset.h" -#include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" diff --git a/hw/mips/boston.c b/hw/mips/boston.c index ac2e93a05a..20b06865b2 100644 --- a/hw/mips/boston.c +++ b/hw/mips/boston.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "exec/address-spaces.h" #include "hw/boards.h" #include "hw/char/serial.h" #include "hw/ide/pci.h" diff --git a/hw/mips/fuloong2e.c b/hw/mips/fuloong2e.c index 4f61f2c873..c1b8066a13 100644 --- a/hw/mips/fuloong2e.c +++ b/hw/mips/fuloong2e.c @@ -33,13 +33,11 @@ #include "hw/mips/bootloader.h" #include "hw/mips/cpudevs.h" #include "hw/pci/pci.h" -#include "qemu/log.h" #include "hw/loader.h" #include "hw/ide/pci.h" #include "hw/qdev-properties.h" #include "elf.h" #include "hw/isa/vt82c686.h" -#include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" diff --git a/hw/mips/gt64xxx_pci.c b/hw/mips/gt64xxx_pci.c index 43349d6837..c7480bd019 100644 --- a/hw/mips/gt64xxx_pci.c +++ b/hw/mips/gt64xxx_pci.c @@ -33,7 +33,6 @@ #include "migration/vmstate.h" #include "hw/intc/i8259.h" #include "hw/irq.h" -#include "exec/address-spaces.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/mips/jazz.c b/hw/mips/jazz.c index 1a0888a0fd..dba2088ed1 100644 --- a/hw/mips/jazz.c +++ b/hw/mips/jazz.c @@ -47,7 +47,6 @@ #include "hw/audio/pcspk.h" #include "hw/input/i8042.h" #include "hw/sysbus.h" -#include "exec/address-spaces.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "qapi/error.h" diff --git a/hw/mips/loongson3_virt.c b/hw/mips/loongson3_virt.c index b15071defc..ae192db0c8 100644 --- a/hw/mips/loongson3_virt.c +++ b/hw/mips/loongson3_virt.c @@ -29,10 +29,8 @@ #include "qemu/cutils.h" #include "qemu/datadir.h" #include "qapi/error.h" -#include "cpu.h" #include "elf.h" #include "kvm_mips.h" -#include "hw/boards.h" #include "hw/char/serial.h" #include "hw/intc/loongson_liointc.h" #include "hw/mips/mips.h" @@ -49,12 +47,10 @@ #include "hw/pci-host/gpex.h" #include "hw/usb.h" #include "net/net.h" -#include "exec/address-spaces.h" #include "sysemu/kvm.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "qemu/log.h" #include "qemu/error-report.h" #define PM_CNTL_MODE 0x10 diff --git a/hw/mips/malta.c b/hw/mips/malta.c index 26e7b1bd9f..7dcf175d72 100644 --- a/hw/mips/malta.c +++ b/hw/mips/malta.c @@ -27,7 +27,6 @@ #include "qemu/bitops.h" #include "qemu-common.h" #include "qemu/datadir.h" -#include "cpu.h" #include "hw/clock.h" #include "hw/southbridge/piix.h" #include "hw/isa/superio.h" @@ -39,7 +38,6 @@ #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" #include "hw/pci/pci.h" -#include "sysemu/sysemu.h" #include "sysemu/arch_init.h" #include "qemu/log.h" #include "hw/mips/bios.h" @@ -47,7 +45,6 @@ #include "hw/irq.h" #include "hw/loader.h" #include "elf.h" -#include "exec/address-spaces.h" #include "qom/object.h" #include "hw/sysbus.h" /* SysBusDevice */ #include "qemu/host-utils.h" diff --git a/hw/mips/meson.build b/hw/mips/meson.build index 1195716dc7..dd0101ad4d 100644 --- a/hw/mips/meson.build +++ b/hw/mips/meson.build @@ -1,12 +1,15 @@ mips_ss = ss.source_set() mips_ss.add(files('bootloader.c', 'mips_int.c')) mips_ss.add(when: 'CONFIG_FW_CFG_MIPS', if_true: files('fw_cfg.c')) -mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_LOONGSON3V', if_true: files('loongson3_bootp.c', 'loongson3_virt.c')) -mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MALTA', if_true: files('gt64xxx_pci.c', 'malta.c')) +mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) + +if 'CONFIG_TCG' in config_all +mips_ss.add(when: 'CONFIG_JAZZ', if_true: files('jazz.c')) mips_ss.add(when: 'CONFIG_MIPSSIM', if_true: files('mipssim.c')) +mips_ss.add(when: 'CONFIG_FULOONG', if_true: files('fuloong2e.c')) mips_ss.add(when: 'CONFIG_MIPS_BOSTON', if_true: [files('boston.c'), fdt]) -mips_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('cps.c')) +endif hw_arch += {'mips': mips_ss} diff --git a/hw/mips/mips_int.c b/hw/mips/mips_int.c index 0f9c6f07c1..2db5e10fe0 100644 --- a/hw/mips/mips_int.c +++ b/hw/mips/mips_int.c @@ -24,7 +24,6 @@ #include "qemu/main-loop.h" #include "hw/irq.h" #include "hw/mips/cpudevs.h" -#include "cpu.h" #include "sysemu/kvm.h" #include "kvm_mips.h" diff --git a/hw/mips/mipssim.c b/hw/mips/mipssim.c index f5d0da05aa..2325e7e05a 100644 --- a/hw/mips/mipssim.c +++ b/hw/mips/mipssim.c @@ -29,7 +29,6 @@ #include "qapi/error.h" #include "qemu-common.h" #include "qemu/datadir.h" -#include "cpu.h" #include "hw/clock.h" #include "hw/mips/mips.h" #include "hw/mips/cpudevs.h" @@ -43,7 +42,6 @@ #include "elf.h" #include "hw/sysbus.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" diff --git a/hw/misc/aspeed_hace.c b/hw/misc/aspeed_hace.c new file mode 100644 index 0000000000..10f00e65f4 --- /dev/null +++ b/hw/misc/aspeed_hace.c @@ -0,0 +1,389 @@ +/* + * ASPEED Hash and Crypto Engine + * + * Copyright (C) 2021 IBM Corp. + * + * Joel Stanley <joel@jms.id.au> + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#include "qemu/osdep.h" +#include "qemu/log.h" +#include "qemu/error-report.h" +#include "hw/misc/aspeed_hace.h" +#include "qapi/error.h" +#include "migration/vmstate.h" +#include "crypto/hash.h" +#include "hw/qdev-properties.h" +#include "hw/irq.h" + +#define R_CRYPT_CMD (0x10 / 4) + +#define R_STATUS (0x1c / 4) +#define HASH_IRQ BIT(9) +#define CRYPT_IRQ BIT(12) +#define TAG_IRQ BIT(15) + +#define R_HASH_SRC (0x20 / 4) +#define R_HASH_DEST (0x24 / 4) +#define R_HASH_SRC_LEN (0x2c / 4) + +#define R_HASH_CMD (0x30 / 4) +/* Hash algorithm selection */ +#define HASH_ALGO_MASK (BIT(4) | BIT(5) | BIT(6)) +#define HASH_ALGO_MD5 0 +#define HASH_ALGO_SHA1 BIT(5) +#define HASH_ALGO_SHA224 BIT(6) +#define HASH_ALGO_SHA256 (BIT(4) | BIT(6)) +#define HASH_ALGO_SHA512_SERIES (BIT(5) | BIT(6)) +/* SHA512 algorithm selection */ +#define SHA512_HASH_ALGO_MASK (BIT(10) | BIT(11) | BIT(12)) +#define HASH_ALGO_SHA512_SHA512 0 +#define HASH_ALGO_SHA512_SHA384 BIT(10) +#define HASH_ALGO_SHA512_SHA256 BIT(11) +#define HASH_ALGO_SHA512_SHA224 (BIT(10) | BIT(11)) +/* HMAC modes */ +#define HASH_HMAC_MASK (BIT(7) | BIT(8)) +#define HASH_DIGEST 0 +#define HASH_DIGEST_HMAC BIT(7) +#define HASH_DIGEST_ACCUM BIT(8) +#define HASH_HMAC_KEY (BIT(7) | BIT(8)) +/* Cascaded operation modes */ +#define HASH_ONLY 0 +#define HASH_ONLY2 BIT(0) +#define HASH_CRYPT_THEN_HASH BIT(1) +#define HASH_HASH_THEN_CRYPT (BIT(0) | BIT(1)) +/* Other cmd bits */ +#define HASH_IRQ_EN BIT(9) +#define HASH_SG_EN BIT(18) +/* Scatter-gather data list */ +#define SG_LIST_LEN_SIZE 4 +#define SG_LIST_LEN_MASK 0x0FFFFFFF +#define SG_LIST_LEN_LAST BIT(31) +#define SG_LIST_ADDR_SIZE 4 +#define SG_LIST_ADDR_MASK 0x7FFFFFFF +#define SG_LIST_ENTRY_SIZE (SG_LIST_LEN_SIZE + SG_LIST_ADDR_SIZE) +#define ASPEED_HACE_MAX_SG 256 /* max number of entries */ + +static const struct { + uint32_t mask; + QCryptoHashAlgorithm algo; +} hash_algo_map[] = { + { HASH_ALGO_MD5, QCRYPTO_HASH_ALG_MD5 }, + { HASH_ALGO_SHA1, QCRYPTO_HASH_ALG_SHA1 }, + { HASH_ALGO_SHA224, QCRYPTO_HASH_ALG_SHA224 }, + { HASH_ALGO_SHA256, QCRYPTO_HASH_ALG_SHA256 }, + { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA512, QCRYPTO_HASH_ALG_SHA512 }, + { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA384, QCRYPTO_HASH_ALG_SHA384 }, + { HASH_ALGO_SHA512_SERIES | HASH_ALGO_SHA512_SHA256, QCRYPTO_HASH_ALG_SHA256 }, +}; + +static int hash_algo_lookup(uint32_t reg) +{ + int i; + + reg &= HASH_ALGO_MASK | SHA512_HASH_ALGO_MASK; + + for (i = 0; i < ARRAY_SIZE(hash_algo_map); i++) { + if (reg == hash_algo_map[i].mask) { + return hash_algo_map[i].algo; + } + } + + return -1; +} + +static void do_hash_operation(AspeedHACEState *s, int algo, bool sg_mode) +{ + struct iovec iov[ASPEED_HACE_MAX_SG]; + g_autofree uint8_t *digest_buf; + size_t digest_len = 0; + int i; + + if (sg_mode) { + uint32_t len = 0; + + for (i = 0; !(len & SG_LIST_LEN_LAST); i++) { + uint32_t addr, src; + hwaddr plen; + + if (i == ASPEED_HACE_MAX_SG) { + qemu_log_mask(LOG_GUEST_ERROR, + "aspeed_hace: guest failed to set end of sg list marker\n"); + break; + } + + src = s->regs[R_HASH_SRC] + (i * SG_LIST_ENTRY_SIZE); + + len = address_space_ldl_le(&s->dram_as, src, + MEMTXATTRS_UNSPECIFIED, NULL); + + addr = address_space_ldl_le(&s->dram_as, src + SG_LIST_LEN_SIZE, + MEMTXATTRS_UNSPECIFIED, NULL); + addr &= SG_LIST_ADDR_MASK; + + iov[i].iov_len = len & SG_LIST_LEN_MASK; + plen = iov[i].iov_len; + iov[i].iov_base = address_space_map(&s->dram_as, addr, &plen, false, + MEMTXATTRS_UNSPECIFIED); + } + } else { + hwaddr len = s->regs[R_HASH_SRC_LEN]; + + iov[0].iov_len = len; + iov[0].iov_base = address_space_map(&s->dram_as, s->regs[R_HASH_SRC], + &len, false, + MEMTXATTRS_UNSPECIFIED); + i = 1; + } + + if (qcrypto_hash_bytesv(algo, iov, i, &digest_buf, &digest_len, NULL) < 0) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: qcrypto failed\n", __func__); + return; + } + + if (address_space_write(&s->dram_as, s->regs[R_HASH_DEST], + MEMTXATTRS_UNSPECIFIED, + digest_buf, digest_len)) { + qemu_log_mask(LOG_GUEST_ERROR, + "aspeed_hace: address space write failed\n"); + } + + for (; i > 0; i--) { + address_space_unmap(&s->dram_as, iov[i - 1].iov_base, + iov[i - 1].iov_len, false, + iov[i - 1].iov_len); + } + + /* + * Set status bits to indicate completion. Testing shows hardware sets + * these irrespective of HASH_IRQ_EN. + */ + s->regs[R_STATUS] |= HASH_IRQ; +} + +static uint64_t aspeed_hace_read(void *opaque, hwaddr addr, unsigned int size) +{ + AspeedHACEState *s = ASPEED_HACE(opaque); + + addr >>= 2; + + if (addr >= ASPEED_HACE_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds read at offset 0x%" HWADDR_PRIx "\n", + __func__, addr << 2); + return 0; + } + + return s->regs[addr]; +} + +static void aspeed_hace_write(void *opaque, hwaddr addr, uint64_t data, + unsigned int size) +{ + AspeedHACEState *s = ASPEED_HACE(opaque); + AspeedHACEClass *ahc = ASPEED_HACE_GET_CLASS(s); + + addr >>= 2; + + if (addr >= ASPEED_HACE_NR_REGS) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Out-of-bounds write at offset 0x%" HWADDR_PRIx "\n", + __func__, addr << 2); + return; + } + + switch (addr) { + case R_STATUS: + if (data & HASH_IRQ) { + data &= ~HASH_IRQ; + + if (s->regs[addr] & HASH_IRQ) { + qemu_irq_lower(s->irq); + } + } + break; + case R_HASH_SRC: + data &= ahc->src_mask; + break; + case R_HASH_DEST: + data &= ahc->dest_mask; + break; + case R_HASH_SRC_LEN: + data &= 0x0FFFFFFF; + break; + case R_HASH_CMD: { + int algo; + data &= ahc->hash_mask; + + if ((data & HASH_HMAC_MASK)) { + qemu_log_mask(LOG_UNIMP, + "%s: HMAC engine command mode %"PRIx64" not implemented", + __func__, (data & HASH_HMAC_MASK) >> 8); + } + if (data & BIT(1)) { + qemu_log_mask(LOG_UNIMP, + "%s: Cascaded mode not implemented", + __func__); + } + algo = hash_algo_lookup(data); + if (algo < 0) { + qemu_log_mask(LOG_GUEST_ERROR, + "%s: Invalid hash algorithm selection 0x%"PRIx64"\n", + __func__, data & ahc->hash_mask); + break; + } + do_hash_operation(s, algo, data & HASH_SG_EN); + + if (data & HASH_IRQ_EN) { + qemu_irq_raise(s->irq); + } + break; + } + case R_CRYPT_CMD: + qemu_log_mask(LOG_UNIMP, "%s: Crypt commands not implemented\n", + __func__); + break; + default: + break; + } + + s->regs[addr] = data; +} + +static const MemoryRegionOps aspeed_hace_ops = { + .read = aspeed_hace_read, + .write = aspeed_hace_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 4, + }, +}; + +static void aspeed_hace_reset(DeviceState *dev) +{ + struct AspeedHACEState *s = ASPEED_HACE(dev); + + memset(s->regs, 0, sizeof(s->regs)); +} + +static void aspeed_hace_realize(DeviceState *dev, Error **errp) +{ + AspeedHACEState *s = ASPEED_HACE(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + + sysbus_init_irq(sbd, &s->irq); + + memory_region_init_io(&s->iomem, OBJECT(s), &aspeed_hace_ops, s, + TYPE_ASPEED_HACE, 0x1000); + + if (!s->dram_mr) { + error_setg(errp, TYPE_ASPEED_HACE ": 'dram' link not set"); + return; + } + + address_space_init(&s->dram_as, s->dram_mr, "dram"); + + sysbus_init_mmio(sbd, &s->iomem); +} + +static Property aspeed_hace_properties[] = { + DEFINE_PROP_LINK("dram", AspeedHACEState, dram_mr, + TYPE_MEMORY_REGION, MemoryRegion *), + DEFINE_PROP_END_OF_LIST(), +}; + + +static const VMStateDescription vmstate_aspeed_hace = { + .name = TYPE_ASPEED_HACE, + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32_ARRAY(regs, AspeedHACEState, ASPEED_HACE_NR_REGS), + VMSTATE_END_OF_LIST(), + } +}; + +static void aspeed_hace_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->realize = aspeed_hace_realize; + dc->reset = aspeed_hace_reset; + device_class_set_props(dc, aspeed_hace_properties); + dc->vmsd = &vmstate_aspeed_hace; +} + +static const TypeInfo aspeed_hace_info = { + .name = TYPE_ASPEED_HACE, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(AspeedHACEState), + .class_init = aspeed_hace_class_init, + .class_size = sizeof(AspeedHACEClass) +}; + +static void aspeed_ast2400_hace_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass); + + dc->desc = "AST2400 Hash and Crypto Engine"; + + ahc->src_mask = 0x0FFFFFFF; + ahc->dest_mask = 0x0FFFFFF8; + ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ +} + +static const TypeInfo aspeed_ast2400_hace_info = { + .name = TYPE_ASPEED_AST2400_HACE, + .parent = TYPE_ASPEED_HACE, + .class_init = aspeed_ast2400_hace_class_init, +}; + +static void aspeed_ast2500_hace_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass); + + dc->desc = "AST2500 Hash and Crypto Engine"; + + ahc->src_mask = 0x3fffffff; + ahc->dest_mask = 0x3ffffff8; + ahc->hash_mask = 0x000003ff; /* No SG or SHA512 modes */ +} + +static const TypeInfo aspeed_ast2500_hace_info = { + .name = TYPE_ASPEED_AST2500_HACE, + .parent = TYPE_ASPEED_HACE, + .class_init = aspeed_ast2500_hace_class_init, +}; + +static void aspeed_ast2600_hace_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedHACEClass *ahc = ASPEED_HACE_CLASS(klass); + + dc->desc = "AST2600 Hash and Crypto Engine"; + + ahc->src_mask = 0x7FFFFFFF; + ahc->dest_mask = 0x7FFFFFF8; + ahc->hash_mask = 0x00147FFF; +} + +static const TypeInfo aspeed_ast2600_hace_info = { + .name = TYPE_ASPEED_AST2600_HACE, + .parent = TYPE_ASPEED_HACE, + .class_init = aspeed_ast2600_hace_class_init, +}; + +static void aspeed_hace_register_types(void) +{ + type_register_static(&aspeed_ast2400_hace_info); + type_register_static(&aspeed_ast2500_hace_info); + type_register_static(&aspeed_ast2600_hace_info); + type_register_static(&aspeed_hace_info); +} + +type_init(aspeed_hace_register_types); diff --git a/hw/misc/aspeed_xdma.c b/hw/misc/aspeed_xdma.c index 533d237e3c..1c21577c98 100644 --- a/hw/misc/aspeed_xdma.c +++ b/hw/misc/aspeed_xdma.c @@ -30,6 +30,19 @@ #define XDMA_IRQ_ENG_STAT_US_COMP BIT(4) #define XDMA_IRQ_ENG_STAT_DS_COMP BIT(5) #define XDMA_IRQ_ENG_STAT_RESET 0xF8000000 + +#define XDMA_AST2600_BMC_CMDQ_ADDR 0x14 +#define XDMA_AST2600_BMC_CMDQ_ENDP 0x18 +#define XDMA_AST2600_BMC_CMDQ_WRP 0x1c +#define XDMA_AST2600_BMC_CMDQ_RDP 0x20 +#define XDMA_AST2600_IRQ_CTRL 0x38 +#define XDMA_AST2600_IRQ_CTRL_US_COMP BIT(16) +#define XDMA_AST2600_IRQ_CTRL_DS_COMP BIT(17) +#define XDMA_AST2600_IRQ_CTRL_W_MASK 0x017003FF +#define XDMA_AST2600_IRQ_STATUS 0x3c +#define XDMA_AST2600_IRQ_STATUS_US_COMP BIT(16) +#define XDMA_AST2600_IRQ_STATUS_DS_COMP BIT(17) + #define XDMA_MEM_SIZE 0x1000 #define TO_REG(addr) ((addr) / sizeof(uint32_t)) @@ -52,56 +65,48 @@ static void aspeed_xdma_write(void *opaque, hwaddr addr, uint64_t val, unsigned int idx; uint32_t val32 = (uint32_t)val; AspeedXDMAState *xdma = opaque; + AspeedXDMAClass *axc = ASPEED_XDMA_GET_CLASS(xdma); if (addr >= ASPEED_XDMA_REG_SIZE) { return; } - switch (addr) { - case XDMA_BMC_CMDQ_ENDP: + if (addr == axc->cmdq_endp) { xdma->regs[TO_REG(addr)] = val32 & XDMA_BMC_CMDQ_W_MASK; - break; - case XDMA_BMC_CMDQ_WRP: + } else if (addr == axc->cmdq_wrp) { idx = TO_REG(addr); xdma->regs[idx] = val32 & XDMA_BMC_CMDQ_W_MASK; - xdma->regs[TO_REG(XDMA_BMC_CMDQ_RDP)] = xdma->regs[idx]; + xdma->regs[TO_REG(axc->cmdq_rdp)] = xdma->regs[idx]; trace_aspeed_xdma_write(addr, val); if (xdma->bmc_cmdq_readp_set) { xdma->bmc_cmdq_readp_set = 0; } else { - xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] |= - XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP; + xdma->regs[TO_REG(axc->intr_status)] |= axc->intr_complete; - if (xdma->regs[TO_REG(XDMA_IRQ_ENG_CTRL)] & - (XDMA_IRQ_ENG_CTRL_US_COMP | XDMA_IRQ_ENG_CTRL_DS_COMP)) + if (xdma->regs[TO_REG(axc->intr_ctrl)] & axc->intr_complete) { qemu_irq_raise(xdma->irq); + } } - break; - case XDMA_BMC_CMDQ_RDP: + } else if (addr == axc->cmdq_rdp) { trace_aspeed_xdma_write(addr, val); if (val32 == XDMA_BMC_CMDQ_RDP_MAGIC) { xdma->bmc_cmdq_readp_set = 1; } - break; - case XDMA_IRQ_ENG_CTRL: - xdma->regs[TO_REG(addr)] = val32 & XDMA_IRQ_ENG_CTRL_W_MASK; - break; - case XDMA_IRQ_ENG_STAT: + } else if (addr == axc->intr_ctrl) { + xdma->regs[TO_REG(addr)] = val32 & axc->intr_ctrl_mask; + } else if (addr == axc->intr_status) { trace_aspeed_xdma_write(addr, val); idx = TO_REG(addr); - if (val32 & (XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP)) { - xdma->regs[idx] &= - ~(XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP); + if (val32 & axc->intr_complete) { + xdma->regs[idx] &= ~axc->intr_complete; qemu_irq_lower(xdma->irq); } - break; - default: + } else { xdma->regs[TO_REG(addr)] = val32; - break; } } @@ -127,10 +132,11 @@ static void aspeed_xdma_realize(DeviceState *dev, Error **errp) static void aspeed_xdma_reset(DeviceState *dev) { AspeedXDMAState *xdma = ASPEED_XDMA(dev); + AspeedXDMAClass *axc = ASPEED_XDMA_GET_CLASS(xdma); xdma->bmc_cmdq_readp_set = 0; memset(xdma->regs, 0, ASPEED_XDMA_REG_SIZE); - xdma->regs[TO_REG(XDMA_IRQ_ENG_STAT)] = XDMA_IRQ_ENG_STAT_RESET; + xdma->regs[TO_REG(axc->intr_status)] = XDMA_IRQ_ENG_STAT_RESET; qemu_irq_lower(xdma->irq); } @@ -144,6 +150,73 @@ static const VMStateDescription aspeed_xdma_vmstate = { }, }; +static void aspeed_2600_xdma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedXDMAClass *axc = ASPEED_XDMA_CLASS(klass); + + dc->desc = "ASPEED 2600 XDMA Controller"; + + axc->cmdq_endp = XDMA_AST2600_BMC_CMDQ_ENDP; + axc->cmdq_wrp = XDMA_AST2600_BMC_CMDQ_WRP; + axc->cmdq_rdp = XDMA_AST2600_BMC_CMDQ_RDP; + axc->intr_ctrl = XDMA_AST2600_IRQ_CTRL; + axc->intr_ctrl_mask = XDMA_AST2600_IRQ_CTRL_W_MASK; + axc->intr_status = XDMA_AST2600_IRQ_STATUS; + axc->intr_complete = XDMA_AST2600_IRQ_STATUS_US_COMP | + XDMA_AST2600_IRQ_STATUS_DS_COMP; +} + +static const TypeInfo aspeed_2600_xdma_info = { + .name = TYPE_ASPEED_2600_XDMA, + .parent = TYPE_ASPEED_XDMA, + .class_init = aspeed_2600_xdma_class_init, +}; + +static void aspeed_2500_xdma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedXDMAClass *axc = ASPEED_XDMA_CLASS(klass); + + dc->desc = "ASPEED 2500 XDMA Controller"; + + axc->cmdq_endp = XDMA_BMC_CMDQ_ENDP; + axc->cmdq_wrp = XDMA_BMC_CMDQ_WRP; + axc->cmdq_rdp = XDMA_BMC_CMDQ_RDP; + axc->intr_ctrl = XDMA_IRQ_ENG_CTRL; + axc->intr_ctrl_mask = XDMA_IRQ_ENG_CTRL_W_MASK; + axc->intr_status = XDMA_IRQ_ENG_STAT; + axc->intr_complete = XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP; +}; + +static const TypeInfo aspeed_2500_xdma_info = { + .name = TYPE_ASPEED_2500_XDMA, + .parent = TYPE_ASPEED_XDMA, + .class_init = aspeed_2500_xdma_class_init, +}; + +static void aspeed_2400_xdma_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + AspeedXDMAClass *axc = ASPEED_XDMA_CLASS(klass); + + dc->desc = "ASPEED 2400 XDMA Controller"; + + axc->cmdq_endp = XDMA_BMC_CMDQ_ENDP; + axc->cmdq_wrp = XDMA_BMC_CMDQ_WRP; + axc->cmdq_rdp = XDMA_BMC_CMDQ_RDP; + axc->intr_ctrl = XDMA_IRQ_ENG_CTRL; + axc->intr_ctrl_mask = XDMA_IRQ_ENG_CTRL_W_MASK; + axc->intr_status = XDMA_IRQ_ENG_STAT; + axc->intr_complete = XDMA_IRQ_ENG_STAT_US_COMP | XDMA_IRQ_ENG_STAT_DS_COMP; +}; + +static const TypeInfo aspeed_2400_xdma_info = { + .name = TYPE_ASPEED_2400_XDMA, + .parent = TYPE_ASPEED_XDMA, + .class_init = aspeed_2400_xdma_class_init, +}; + static void aspeed_xdma_class_init(ObjectClass *classp, void *data) { DeviceClass *dc = DEVICE_CLASS(classp); @@ -158,10 +231,15 @@ static const TypeInfo aspeed_xdma_info = { .parent = TYPE_SYS_BUS_DEVICE, .instance_size = sizeof(AspeedXDMAState), .class_init = aspeed_xdma_class_init, + .class_size = sizeof(AspeedXDMAClass), + .abstract = true, }; static void aspeed_xdma_register_type(void) { type_register_static(&aspeed_xdma_info); + type_register_static(&aspeed_2400_xdma_info); + type_register_static(&aspeed_2500_xdma_info); + type_register_static(&aspeed_2600_xdma_info); } type_init(aspeed_xdma_register_type); diff --git a/hw/misc/imx7_snvs.c b/hw/misc/imx7_snvs.c index 45972a5920..ee7698bd9c 100644 --- a/hw/misc/imx7_snvs.c +++ b/hw/misc/imx7_snvs.c @@ -14,7 +14,6 @@ #include "qemu/osdep.h" #include "hw/misc/imx7_snvs.h" -#include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" diff --git a/hw/misc/imx_ccm.c b/hw/misc/imx_ccm.c index 08a50ee4c8..9403c5daa3 100644 --- a/hw/misc/imx_ccm.c +++ b/hw/misc/imx_ccm.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "hw/misc/imx_ccm.h" -#include "qemu/log.h" #include "qemu/module.h" #ifndef DEBUG_IMX_CCM diff --git a/hw/misc/imx_rngc.c b/hw/misc/imx_rngc.c index 4c270df2db..632c03779c 100644 --- a/hw/misc/imx_rngc.c +++ b/hw/misc/imx_rngc.c @@ -14,7 +14,6 @@ #include "qemu/osdep.h" #include "qemu/main-loop.h" #include "qemu/module.h" -#include "qemu/log.h" #include "qemu/guest-random.h" #include "hw/irq.h" #include "hw/misc/imx_rngc.h" diff --git a/hw/misc/led.c b/hw/misc/led.c index f552b8b648..f6d6d68bce 100644 --- a/hw/misc/led.c +++ b/hw/misc/led.c @@ -10,7 +10,6 @@ #include "migration/vmstate.h" #include "hw/qdev-properties.h" #include "hw/misc/led.h" -#include "hw/irq.h" #include "trace.h" #define LED_INTENSITY_PERCENT_MAX 100 diff --git a/hw/misc/macio/macio.c b/hw/misc/macio/macio.c index e6eeb575d5..4515296e66 100644 --- a/hw/misc/macio/macio.c +++ b/hw/misc/macio/macio.c @@ -35,7 +35,6 @@ #include "hw/char/escc.h" #include "hw/misc/macio/macio.h" #include "hw/intc/heathrow_pic.h" -#include "sysemu/sysemu.h" #include "trace.h" /* Note: this code is strongly inspirated from the corresponding code diff --git a/hw/misc/mchp_pfsoc_dmc.c b/hw/misc/mchp_pfsoc_dmc.c index 15cf3d7725..43d8e970ab 100644 --- a/hw/misc/mchp_pfsoc_dmc.c +++ b/hw/misc/mchp_pfsoc_dmc.c @@ -24,7 +24,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/sysbus.h" #include "hw/misc/mchp_pfsoc_dmc.h" diff --git a/hw/misc/mchp_pfsoc_ioscb.c b/hw/misc/mchp_pfsoc_ioscb.c index 8b0d1cacd7..f4fd55a0e5 100644 --- a/hw/misc/mchp_pfsoc_ioscb.c +++ b/hw/misc/mchp_pfsoc_ioscb.c @@ -24,7 +24,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/sysbus.h" #include "hw/misc/mchp_pfsoc_ioscb.h" diff --git a/hw/misc/mchp_pfsoc_sysreg.c b/hw/misc/mchp_pfsoc_sysreg.c index 248a313345..89571eded5 100644 --- a/hw/misc/mchp_pfsoc_sysreg.c +++ b/hw/misc/mchp_pfsoc_sysreg.c @@ -24,7 +24,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qapi/error.h" -#include "hw/hw.h" #include "hw/sysbus.h" #include "hw/misc/mchp_pfsoc_sysreg.h" diff --git a/hw/misc/meson.build b/hw/misc/meson.build index 21034dc60a..1e7b8b064b 100644 --- a/hw/misc/meson.build +++ b/hw/misc/meson.build @@ -109,6 +109,7 @@ softmmu_ss.add(when: 'CONFIG_PVPANIC_ISA', if_true: files('pvpanic-isa.c')) softmmu_ss.add(when: 'CONFIG_PVPANIC_PCI', if_true: files('pvpanic-pci.c')) softmmu_ss.add(when: 'CONFIG_AUX', if_true: files('auxbus.c')) softmmu_ss.add(when: 'CONFIG_ASPEED_SOC', if_true: files( + 'aspeed_hace.c', 'aspeed_lpc.c', 'aspeed_scu.c', 'aspeed_sdmc.c', diff --git a/hw/misc/mips_itu.c b/hw/misc/mips_itu.c index 133399598f..80683fed31 100644 --- a/hw/misc/mips_itu.c +++ b/hw/misc/mips_itu.c @@ -22,7 +22,6 @@ #include "qemu/log.h" #include "qemu/module.h" #include "qapi/error.h" -#include "cpu.h" #include "exec/exec-all.h" #include "hw/misc/mips_itu.h" #include "hw/qdev-properties.h" diff --git a/hw/misc/mst_fpga.c b/hw/misc/mst_fpga.c index edfc35d5f0..2aaadfa966 100644 --- a/hw/misc/mst_fpga.c +++ b/hw/misc/mst_fpga.c @@ -222,7 +222,7 @@ static void mst_fpga_init(Object *obj) sysbus_init_mmio(sbd, &s->iomem); } -static VMStateDescription vmstate_mst_fpga_regs = { +static const VMStateDescription vmstate_mst_fpga_regs = { .name = "mainstone_fpga", .version_id = 0, .minimum_version_id = 0, diff --git a/hw/misc/pvpanic-isa.c b/hw/misc/pvpanic-isa.c index 27113abd6c..7b66d58acc 100644 --- a/hw/misc/pvpanic-isa.c +++ b/hw/misc/pvpanic-isa.c @@ -13,7 +13,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" diff --git a/hw/misc/pvpanic-pci.c b/hw/misc/pvpanic-pci.c index d629639d8f..af8cbe2830 100644 --- a/hw/misc/pvpanic-pci.c +++ b/hw/misc/pvpanic-pci.c @@ -12,7 +12,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" diff --git a/hw/misc/sifive_e_prci.c b/hw/misc/sifive_e_prci.c index 8ec4ee4b41..a8702c6a5d 100644 --- a/hw/misc/sifive_e_prci.c +++ b/hw/misc/sifive_e_prci.c @@ -23,7 +23,6 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" -#include "hw/hw.h" #include "hw/misc/sifive_e_prci.h" static uint64_t sifive_e_prci_read(void *opaque, hwaddr addr, unsigned int size) diff --git a/hw/misc/sifive_test.c b/hw/misc/sifive_test.c index 2deb2072cc..56df45bfe5 100644 --- a/hw/misc/sifive_test.c +++ b/hw/misc/sifive_test.c @@ -24,7 +24,6 @@ #include "qemu/log.h" #include "qemu/module.h" #include "sysemu/runstate.h" -#include "hw/hw.h" #include "hw/misc/sifive_test.h" static uint64_t sifive_test_read(void *opaque, hwaddr addr, unsigned int size) diff --git a/hw/misc/virt_ctrl.c b/hw/misc/virt_ctrl.c index 2ea01bd7a1..3552d7a09a 100644 --- a/hw/misc/virt_ctrl.c +++ b/hw/misc/virt_ctrl.c @@ -5,7 +5,6 @@ */ #include "qemu/osdep.h" -#include "hw/irq.h" #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "migration/vmstate.h" diff --git a/hw/moxie/moxiesim.c b/hw/moxie/moxiesim.c index f7b57fcae1..3d255d4879 100644 --- a/hw/moxie/moxiesim.c +++ b/hw/moxie/moxiesim.c @@ -29,14 +29,12 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "cpu.h" -#include "hw/sysbus.h" #include "net/net.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/char/serial.h" -#include "exec/address-spaces.h" #include "elf.h" #define PHYS_MEM_BASE 0x80000000 diff --git a/hw/net/can/xlnx-zynqmp-can.c b/hw/net/can/xlnx-zynqmp-can.c index affa21a5ed..22bb8910fa 100644 --- a/hw/net/can/xlnx-zynqmp-can.c +++ b/hw/net/can/xlnx-zynqmp-can.c @@ -37,7 +37,6 @@ #include "qemu/bitops.h" #include "qemu/log.h" #include "qemu/cutils.h" -#include "sysemu/sysemu.h" #include "migration/vmstate.h" #include "hw/qdev-properties.h" #include "net/can_emu.h" diff --git a/hw/net/i82596.c b/hw/net/i82596.c index 055c3a1470..ec21e2699a 100644 --- a/hw/net/i82596.c +++ b/hw/net/i82596.c @@ -12,7 +12,6 @@ #include "qemu/timer.h" #include "net/net.h" #include "net/eth.h" -#include "sysemu/sysemu.h" #include "hw/irq.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" diff --git a/hw/net/lasi_i82596.c b/hw/net/lasi_i82596.c index 820b63f350..e37f7fabe9 100644 --- a/hw/net/lasi_i82596.c +++ b/hw/net/lasi_i82596.c @@ -18,7 +18,6 @@ #include "hw/net/lasi_82596.h" #include "hw/net/i82596.h" #include "trace.h" -#include "sysemu/sysemu.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" diff --git a/hw/net/msf2-emac.c b/hw/net/msf2-emac.c index 3e6206044f..9278fdce0b 100644 --- a/hw/net/msf2-emac.c +++ b/hw/net/msf2-emac.c @@ -32,7 +32,6 @@ #include "qemu-common.h" #include "qemu/log.h" #include "qapi/error.h" -#include "exec/address-spaces.h" #include "hw/registerfields.h" #include "hw/net/msf2-emac.h" #include "hw/net/mii.h" diff --git a/hw/net/spapr_llan.c b/hw/net/spapr_llan.c index 10e85a4556..a6876a936d 100644 --- a/hw/net/spapr_llan.c +++ b/hw/net/spapr_llan.c @@ -26,7 +26,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/log.h" #include "qemu/module.h" #include "net/net.h" diff --git a/hw/net/xgmac.c b/hw/net/xgmac.c index 00859a7d50..0ab6ae91aa 100644 --- a/hw/net/xgmac.c +++ b/hw/net/xgmac.c @@ -29,7 +29,6 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "qemu/log.h" #include "qemu/module.h" #include "net/net.h" #include "qom/object.h" diff --git a/hw/nios2/10m50_devboard.c b/hw/nios2/10m50_devboard.c index a14fc31e86..3d1205b8bd 100644 --- a/hw/nios2/10m50_devboard.c +++ b/hw/nios2/10m50_devboard.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/sysbus.h" #include "hw/char/serial.h" diff --git a/hw/nios2/boot.c b/hw/nios2/boot.c index d9969ac148..5b3e4efed5 100644 --- a/hw/nios2/boot.c +++ b/hw/nios2/boot.c @@ -32,13 +32,11 @@ #include "qemu/units.h" #include "qemu-common.h" #include "qemu/datadir.h" -#include "cpu.h" #include "qemu/option.h" #include "qemu/config-file.h" #include "qemu/error-report.h" #include "sysemu/device_tree.h" #include "sysemu/reset.h" -#include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" diff --git a/hw/nios2/generic_nommu.c b/hw/nios2/generic_nommu.c index 19899e2c1e..fbc18dbd04 100644 --- a/hw/nios2/generic_nommu.c +++ b/hw/nios2/generic_nommu.c @@ -29,9 +29,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu-common.h" -#include "cpu.h" -#include "hw/sysbus.h" #include "hw/char/serial.h" #include "hw/boards.h" #include "exec/memory.h" diff --git a/hw/nubus/nubus-bus.c b/hw/nubus/nubus-bus.c index 942a6d5342..5c13452308 100644 --- a/hw/nubus/nubus-bus.c +++ b/hw/nubus/nubus-bus.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "hw/nubus/nubus.h" -#include "hw/sysbus.h" #include "qapi/error.h" diff --git a/hw/nvram/nrf51_nvm.c b/hw/nvram/nrf51_nvm.c index 7b3460d52d..7f1db8c423 100644 --- a/hw/nvram/nrf51_nvm.c +++ b/hw/nvram/nrf51_nvm.c @@ -21,7 +21,6 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" -#include "exec/address-spaces.h" #include "hw/arm/nrf51.h" #include "hw/nvram/nrf51_nvm.h" #include "hw/qdev-properties.h" diff --git a/hw/nvram/spapr_nvram.c b/hw/nvram/spapr_nvram.c index 01f7752014..fbfdf47e26 100644 --- a/hw/nvram/spapr_nvram.c +++ b/hw/nvram/spapr_nvram.c @@ -26,14 +26,12 @@ #include "qemu/module.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" #include <libfdt.h> #include "sysemu/block-backend.h" #include "sysemu/device_tree.h" #include "sysemu/sysemu.h" #include "sysemu/runstate.h" -#include "hw/sysbus.h" #include "migration/vmstate.h" #include "hw/nvram/chrp_nvram.h" #include "hw/ppc/spapr.h" diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c index 39f1d344ae..73fe383c2d 100644 --- a/hw/openrisc/openrisc_sim.c +++ b/hw/openrisc/openrisc_sim.c @@ -29,7 +29,6 @@ #include "net/net.h" #include "hw/loader.h" #include "hw/qdev-properties.h" -#include "exec/address-spaces.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" #include "sysemu/qtest.h" diff --git a/hw/pci-host/bonito.c b/hw/pci-host/bonito.c index 2a2db7cea6..afb3d1f81d 100644 --- a/hw/pci-host/bonito.c +++ b/hw/pci-host/bonito.c @@ -49,7 +49,6 @@ #include "migration/vmstate.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "exec/address-spaces.h" #include "hw/misc/unimp.h" #include "hw/registerfields.h" #include "qom/object.h" diff --git a/hw/pci-host/ppce500.c b/hw/pci-host/ppce500.c index 5ad1424b31..89c1b53dd7 100644 --- a/hw/pci-host/ppce500.c +++ b/hw/pci-host/ppce500.c @@ -415,7 +415,6 @@ static const VMStateDescription vmstate_ppce500_pci = { } }; -#include "exec/address-spaces.h" static void e500_pcihost_bridge_realize(PCIDevice *d, Error **errp) { diff --git a/hw/pci-host/prep.c b/hw/pci-host/prep.c index 0a9162fba9..9fef74fc56 100644 --- a/hw/pci-host/prep.c +++ b/hw/pci-host/prep.c @@ -38,7 +38,6 @@ #include "hw/irq.h" #include "hw/loader.h" #include "hw/or-irq.h" -#include "exec/address-spaces.h" #include "elf.h" #include "qom/object.h" diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index f41a0cc301..949ecc21f2 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -34,7 +34,6 @@ #include "hw/irq.h" #include "hw/pci-bridge/simba.h" #include "hw/pci-host/sabre.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/pci-host/sh_pci.c b/hw/pci-host/sh_pci.c index 734892f47c..08c1562e22 100644 --- a/hw/pci-host/sh_pci.c +++ b/hw/pci-host/sh_pci.c @@ -30,7 +30,6 @@ #include "hw/pci/pci_host.h" #include "qemu/bswap.h" #include "qemu/module.h" -#include "exec/address-spaces.h" #include "qom/object.h" #define TYPE_SH_PCI_HOST_BRIDGE "sh_pci" diff --git a/hw/pci/pci.c b/hw/pci/pci.c index 8f35e13a0c..377084f1a8 100644 --- a/hw/pci/pci.c +++ b/hw/pci/pci.c @@ -45,7 +45,6 @@ #include "trace.h" #include "hw/pci/msi.h" #include "hw/pci/msix.h" -#include "exec/address-spaces.h" #include "hw/hotplug.h" #include "hw/boards.h" #include "qapi/error.h" diff --git a/hw/pci/pcie_host.c b/hw/pci/pcie_host.c index 3534006f99..5abbe83220 100644 --- a/hw/pci/pcie_host.c +++ b/hw/pci/pcie_host.c @@ -23,7 +23,6 @@ #include "hw/pci/pci.h" #include "hw/pci/pcie_host.h" #include "qemu/module.h" -#include "exec/address-spaces.h" /* a helper function to get a PCIDevice for a given mmconfig address */ static inline PCIDevice *pcie_dev_find_by_mmcfg_addr(PCIBus *s, diff --git a/hw/pcmcia/meson.build b/hw/pcmcia/meson.build index ab50bd325d..51f2512b8e 100644 --- a/hw/pcmcia/meson.build +++ b/hw/pcmcia/meson.build @@ -1,2 +1,2 @@ -softmmu_ss.add(files('pcmcia.c')) +softmmu_ss.add(when: 'CONFIG_PCMCIA', if_true: files('pcmcia.c')) softmmu_ss.add(when: 'CONFIG_PXA2XX', if_true: files('pxa2xx.c')) diff --git a/hw/ppc/e500.c b/hw/ppc/e500.c index 79467ac512..95451414dd 100644 --- a/hw/ppc/e500.c +++ b/hw/ppc/e500.c @@ -25,7 +25,6 @@ #include "qemu/config-file.h" #include "hw/char/serial.h" #include "hw/pci/pci.h" -#include "hw/boards.h" #include "sysemu/sysemu.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" @@ -39,7 +38,6 @@ #include "hw/loader.h" #include "elf.h" #include "hw/sysbus.h" -#include "exec/address-spaces.h" #include "qemu/host-utils.h" #include "qemu/option.h" #include "hw/pci-host/ppce500.h" diff --git a/hw/ppc/mac_newworld.c b/hw/ppc/mac_newworld.c index d88b38e925..7bb7ac3997 100644 --- a/hw/ppc/mac_newworld.c +++ b/hw/ppc/mac_newworld.c @@ -58,7 +58,6 @@ #include "hw/pci/pci.h" #include "net/net.h" #include "sysemu/sysemu.h" -#include "hw/boards.h" #include "hw/nvram/fw_cfg.h" #include "hw/char/escc.h" #include "hw/misc/macio/macio.h" @@ -71,7 +70,6 @@ #include "sysemu/reset.h" #include "kvm_ppc.h" #include "hw/usb.h" -#include "exec/address-spaces.h" #include "hw/sysbus.h" #include "trace.h" diff --git a/hw/ppc/mac_oldworld.c b/hw/ppc/mac_oldworld.c index 963d247f5f..de2be960e6 100644 --- a/hw/ppc/mac_oldworld.c +++ b/hw/ppc/mac_oldworld.c @@ -38,7 +38,6 @@ #include "hw/isa/isa.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" -#include "hw/boards.h" #include "hw/nvram/fw_cfg.h" #include "hw/char/escc.h" #include "hw/misc/macio/macio.h" @@ -49,7 +48,6 @@ #include "sysemu/kvm.h" #include "sysemu/reset.h" #include "kvm_ppc.h" -#include "exec/address-spaces.h" #define MAX_IDE_BUS 2 #define CFG_ADDR 0xf0000510 diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index 77af846cdf..ffe01977cd 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -32,14 +32,12 @@ #include "sysemu/device_tree.h" #include "sysemu/hw_accel.h" #include "target/ppc/cpu.h" -#include "qemu/log.h" #include "hw/ppc/fdt.h" #include "hw/ppc/ppc.h" #include "hw/ppc/pnv.h" #include "hw/ppc/pnv_core.h" #include "hw/loader.h" #include "hw/nmi.h" -#include "exec/address-spaces.h" #include "qapi/visitor.h" #include "monitor/monitor.h" #include "hw/intc/intc.h" @@ -53,7 +51,6 @@ #include "hw/ppc/pnv_pnor.h" #include "hw/isa/isa.h" -#include "hw/boards.h" #include "hw/char/serial.h" #include "hw/rtc/mc146818rtc.h" diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c index 4b455de1ea..5ef1cf2afb 100644 --- a/hw/ppc/pnv_pnor.c +++ b/hw/ppc/pnv_pnor.c @@ -10,7 +10,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qemu/units.h" #include "sysemu/block-backend.h" #include "sysemu/blockdev.h" diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 292b373f93..cd9a2c5952 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -26,7 +26,6 @@ #include "qapi/error.h" #include "monitor/monitor.h" -#include "exec/address-spaces.h" #include "hw/ppc/fdt.h" #include "hw/ppc/pnv.h" diff --git a/hw/ppc/ppc.c b/hw/ppc/ppc.c index bf28d6bfc8..7375bf4fa9 100644 --- a/hw/ppc/ppc.c +++ b/hw/ppc/ppc.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "hw/irq.h" #include "hw/ppc/ppc.h" #include "hw/ppc/ppc_e500.h" diff --git a/hw/ppc/ppc405_boards.c b/hw/ppc/ppc405_boards.c index 8f77887fb1..972a7a4a3e 100644 --- a/hw/ppc/ppc405_boards.c +++ b/hw/ppc/ppc405_boards.c @@ -34,15 +34,12 @@ #include "ppc405.h" #include "hw/rtc/m48t59.h" #include "hw/block/flash.h" -#include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "sysemu/reset.h" #include "sysemu/block-backend.h" #include "hw/boards.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "qemu/cutils.h" #define BIOS_FILENAME "ppc405_rom.bin" diff --git a/hw/ppc/ppc405_uc.c b/hw/ppc/ppc405_uc.c index fe047074a1..e632c408bd 100644 --- a/hw/ppc/ppc405_uc.c +++ b/hw/ppc/ppc405_uc.c @@ -34,7 +34,6 @@ #include "qemu/timer.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" -#include "qemu/log.h" #include "exec/address-spaces.h" #include "hw/intc/ppc-uic.h" #include "hw/qdev-properties.h" diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index b7539aa721..7fb620b9a0 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -25,7 +25,6 @@ #include "sysemu/device_tree.h" #include "hw/loader.h" #include "elf.h" -#include "exec/address-spaces.h" #include "hw/char/serial.h" #include "hw/ppc/ppc.h" #include "ppc405.h" diff --git a/hw/ppc/ppc440_pcix.c b/hw/ppc/ppc440_pcix.c index 91cbcd0504..788d25514a 100644 --- a/hw/ppc/ppc440_pcix.c +++ b/hw/ppc/ppc440_pcix.c @@ -28,7 +28,6 @@ #include "hw/ppc/ppc4xx.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" -#include "exec/address-spaces.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/ppc/ppc440_uc.c b/hw/ppc/ppc440_uc.c index f6f89058ab..993e3ba955 100644 --- a/hw/ppc/ppc440_uc.c +++ b/hw/ppc/ppc440_uc.c @@ -14,9 +14,7 @@ #include "qapi/error.h" #include "qemu/log.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/irq.h" -#include "exec/address-spaces.h" #include "exec/memory.h" #include "hw/ppc/ppc.h" #include "hw/qdev-properties.h" diff --git a/hw/ppc/ppc4xx_devs.c b/hw/ppc/ppc4xx_devs.c index fe9d4f7155..980c48944f 100644 --- a/hw/ppc/ppc4xx_devs.c +++ b/hw/ppc/ppc4xx_devs.c @@ -29,7 +29,6 @@ #include "hw/irq.h" #include "hw/ppc/ppc.h" #include "hw/ppc/ppc4xx.h" -#include "hw/boards.h" #include "hw/intc/ppc-uic.h" #include "hw/qdev-properties.h" #include "qemu/log.h" diff --git a/hw/ppc/ppc4xx_pci.c b/hw/ppc/ppc4xx_pci.c index e8789f64e8..8147ba6f94 100644 --- a/hw/ppc/ppc4xx_pci.c +++ b/hw/ppc/ppc4xx_pci.c @@ -28,7 +28,6 @@ #include "sysemu/reset.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" -#include "exec/address-spaces.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/ppc/ppc_booke.c b/hw/ppc/ppc_booke.c index 974c0c8a75..10b643861f 100644 --- a/hw/ppc/ppc_booke.c +++ b/hw/ppc/ppc_booke.c @@ -28,7 +28,6 @@ #include "qemu/timer.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "qemu/log.h" #include "hw/loader.h" #include "kvm_ppc.h" diff --git a/hw/ppc/prep.c b/hw/ppc/prep.c index f1b1efdcef..acfc2a91d8 100644 --- a/hw/ppc/prep.c +++ b/hw/ppc/prep.c @@ -24,12 +24,10 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "hw/rtc/m48t59.h" #include "hw/char/serial.h" #include "hw/block/fdc.h" #include "net/net.h" -#include "sysemu/sysemu.h" #include "hw/isa/isa.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" @@ -38,7 +36,6 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/log.h" -#include "hw/irq.h" #include "hw/loader.h" #include "hw/rtc/mc146818rtc.h" #include "hw/isa/pc87312.h" @@ -46,7 +43,6 @@ #include "sysemu/arch_init.h" #include "sysemu/kvm.h" #include "sysemu/reset.h" -#include "exec/address-spaces.h" #include "trace.h" #include "elf.h" #include "qemu/units.h" diff --git a/hw/ppc/rs6000_mc.c b/hw/ppc/rs6000_mc.c index 4db5b51a2d..c0bc212e92 100644 --- a/hw/ppc/rs6000_mc.c +++ b/hw/ppc/rs6000_mc.c @@ -23,7 +23,6 @@ #include "hw/qdev-properties.h" #include "migration/vmstate.h" #include "exec/address-spaces.h" -#include "hw/boards.h" #include "qapi/error.h" #include "trace.h" #include "qom/object.h" diff --git a/hw/ppc/sam460ex.c b/hw/ppc/sam460ex.c index 0c6baf77e8..0737234d66 100644 --- a/hw/ppc/sam460ex.c +++ b/hw/ppc/sam460ex.c @@ -24,7 +24,6 @@ #include "sysemu/block-backend.h" #include "hw/loader.h" #include "elf.h" -#include "exec/address-spaces.h" #include "exec/memory.h" #include "ppc440.h" #include "ppc405.h" diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index b37ceb8ee8..8f40319aee 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -54,7 +54,6 @@ #include "cpu-models.h" #include "hw/core/cpu.h" -#include "hw/boards.h" #include "hw/ppc/ppc.h" #include "hw/loader.h" @@ -70,7 +69,6 @@ #include "hw/virtio/virtio-scsi.h" #include "hw/virtio/vhost-scsi-common.h" -#include "exec/address-spaces.h" #include "exec/ram_addr.h" #include "hw/usb.h" #include "qemu/config-file.h" diff --git a/hw/ppc/spapr_drc.c b/hw/ppc/spapr_drc.c index 6918e0c9d1..a2f2634601 100644 --- a/hw/ppc/spapr_drc.c +++ b/hw/ppc/spapr_drc.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qapi/qmp/qnull.h" -#include "cpu.h" #include "qemu/cutils.h" #include "hw/ppc/spapr_drc.h" #include "qom/object.h" diff --git a/hw/ppc/spapr_events.c b/hw/ppc/spapr_events.c index d51daedfa6..0cfc19be19 100644 --- a/hw/ppc/spapr_events.c +++ b/hw/ppc/spapr_events.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "sysemu/device_tree.h" #include "sysemu/runstate.h" diff --git a/hw/ppc/spapr_hcall.c b/hw/ppc/spapr_hcall.c index 7275d0bba1..16c719c3de 100644 --- a/hw/ppc/spapr_hcall.c +++ b/hw/ppc/spapr_hcall.c @@ -7,7 +7,6 @@ #include "qemu/main-loop.h" #include "qemu/module.h" #include "qemu/error-report.h" -#include "cpu.h" #include "exec/exec-all.h" #include "helper_regs.h" #include "hw/ppc/spapr.h" diff --git a/hw/ppc/spapr_iommu.c b/hw/ppc/spapr_iommu.c index 24537ffcbd..db01071858 100644 --- a/hw/ppc/spapr_iommu.c +++ b/hw/ppc/spapr_iommu.c @@ -25,7 +25,6 @@ #include "kvm_ppc.h" #include "migration/vmstate.h" #include "sysemu/dma.h" -#include "exec/address-spaces.h" #include "trace.h" #include "hw/ppc/spapr.h" diff --git a/hw/ppc/spapr_pci.c b/hw/ppc/spapr_pci.c index feba18cb12..7a725855f9 100644 --- a/hw/ppc/spapr_pci.c +++ b/hw/ppc/spapr_pci.c @@ -25,7 +25,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "hw/irq.h" #include "hw/sysbus.h" #include "migration/vmstate.h" @@ -35,7 +34,6 @@ #include "hw/pci/pci_host.h" #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" -#include "exec/address-spaces.h" #include "exec/ram_addr.h" #include <libfdt.h> #include "trace.h" diff --git a/hw/ppc/spapr_pci_vfio.c b/hw/ppc/spapr_pci_vfio.c index e0547b1740..7817cf72ee 100644 --- a/hw/ppc/spapr_pci_vfio.c +++ b/hw/ppc/spapr_pci_vfio.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include <linux/vfio.h> -#include "cpu.h" #include "hw/ppc/spapr.h" #include "hw/pci-host/spapr.h" #include "hw/pci/msix.h" diff --git a/hw/ppc/spapr_rng.c b/hw/ppc/spapr_rng.c index d14800e9de..df5c4b9687 100644 --- a/hw/ppc/spapr_rng.c +++ b/hw/ppc/spapr_rng.c @@ -19,7 +19,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "qemu/error-report.h" #include "qemu/main-loop.h" #include "qemu/module.h" diff --git a/hw/ppc/spapr_rtas.c b/hw/ppc/spapr_rtas.c index 6ec3e71757..03355b4c0a 100644 --- a/hw/ppc/spapr_rtas.c +++ b/hw/ppc/spapr_rtas.c @@ -26,7 +26,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/log.h" #include "qemu/error-report.h" #include "sysemu/sysemu.h" @@ -41,7 +40,6 @@ #include "hw/ppc/spapr_rtas.h" #include "hw/ppc/spapr_cpu_core.h" #include "hw/ppc/ppc.h" -#include "hw/boards.h" #include <libfdt.h> #include "hw/ppc/spapr_drc.h" diff --git a/hw/ppc/spapr_rtas_ddw.c b/hw/ppc/spapr_rtas_ddw.c index 3501b05819..3e826e1308 100644 --- a/hw/ppc/spapr_rtas_ddw.c +++ b/hw/ppc/spapr_rtas_ddw.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/error-report.h" #include "qemu/module.h" #include "hw/ppc/spapr.h" diff --git a/hw/ppc/spapr_rtc.c b/hw/ppc/spapr_rtc.c index 68cfc578a3..fba4dfca35 100644 --- a/hw/ppc/spapr_rtc.c +++ b/hw/ppc/spapr_rtc.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qemu-common.h" -#include "cpu.h" #include "qemu/timer.h" #include "sysemu/sysemu.h" #include "hw/ppc/spapr.h" diff --git a/hw/ppc/spapr_tpm_proxy.c b/hw/ppc/spapr_tpm_proxy.c index a01f81f9e0..2454086744 100644 --- a/hw/ppc/spapr_tpm_proxy.c +++ b/hw/ppc/spapr_tpm_proxy.c @@ -15,7 +15,6 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/reset.h" -#include "cpu.h" #include "hw/ppc/spapr.h" #include "hw/qdev-properties.h" #include "trace.h" diff --git a/hw/ppc/virtex_ml507.c b/hw/ppc/virtex_ml507.c index cb421570da..9c575403b8 100644 --- a/hw/ppc/virtex_ml507.c +++ b/hw/ppc/virtex_ml507.c @@ -38,9 +38,7 @@ #include "elf.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qemu/option.h" -#include "exec/address-spaces.h" #include "hw/intc/ppc-uic.h" #include "hw/ppc/ppc.h" diff --git a/hw/remote/iohub.c b/hw/remote/iohub.c index e4ff131a6b..547d597f0f 100644 --- a/hw/remote/iohub.c +++ b/hw/remote/iohub.c @@ -15,7 +15,6 @@ #include "hw/pci/pci_ids.h" #include "hw/pci/pci_bus.h" #include "qemu/thread.h" -#include "hw/boards.h" #include "hw/remote/machine.h" #include "hw/remote/iohub.h" #include "qemu/main-loop.h" diff --git a/hw/remote/machine.c b/hw/remote/machine.c index c0ab4f528a..952105eab5 100644 --- a/hw/remote/machine.c +++ b/hw/remote/machine.c @@ -17,7 +17,6 @@ #include "qemu-common.h" #include "hw/remote/machine.h" -#include "exec/address-spaces.h" #include "exec/memory.h" #include "qapi/error.h" #include "hw/pci/pci_host.h" diff --git a/hw/remote/memory.c b/hw/remote/memory.c index 32085b1e05..2d4174614a 100644 --- a/hw/remote/memory.c +++ b/hw/remote/memory.c @@ -12,7 +12,6 @@ #include "qemu-common.h" #include "hw/remote/memory.h" -#include "exec/address-spaces.h" #include "exec/ram_addr.h" #include "qapi/error.h" diff --git a/hw/remote/proxy-memory-listener.c b/hw/remote/proxy-memory-listener.c index af1fa6f5aa..901dbf1357 100644 --- a/hw/remote/proxy-memory-listener.c +++ b/hw/remote/proxy-memory-listener.c @@ -14,9 +14,7 @@ #include "qemu/range.h" #include "exec/memory.h" #include "exec/cpu-common.h" -#include "cpu.h" #include "exec/ram_addr.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "hw/remote/mpqemu-link.h" #include "hw/remote/proxy-memory-listener.h" diff --git a/hw/riscv/microchip_pfsoc.c b/hw/riscv/microchip_pfsoc.c index c4146b7a6b..6cbd17ebf2 100644 --- a/hw/riscv/microchip_pfsoc.c +++ b/hw/riscv/microchip_pfsoc.c @@ -36,12 +36,10 @@ #include "qemu/osdep.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qemu/units.h" #include "qemu/cutils.h" #include "qapi/error.h" #include "hw/boards.h" -#include "hw/irq.h" #include "hw/loader.h" #include "hw/sysbus.h" #include "chardev/char.h" diff --git a/hw/riscv/numa.c b/hw/riscv/numa.c index 4f92307102..7fe92d402f 100644 --- a/hw/riscv/numa.c +++ b/hw/riscv/numa.c @@ -18,7 +18,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "hw/boards.h" diff --git a/hw/riscv/opentitan.c b/hw/riscv/opentitan.c index e168bffe69..dc9dea117e 100644 --- a/hw/riscv/opentitan.c +++ b/hw/riscv/opentitan.c @@ -24,7 +24,6 @@ #include "hw/boards.h" #include "hw/misc/unimp.h" #include "hw/riscv/boot.h" -#include "exec/address-spaces.h" #include "qemu/units.h" #include "sysemu/sysemu.h" diff --git a/hw/riscv/sifive_e.c b/hw/riscv/sifive_e.c index f939bcf9ea..3e8b44b2c0 100644 --- a/hw/riscv/sifive_e.c +++ b/hw/riscv/sifive_e.c @@ -29,7 +29,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "hw/boards.h" @@ -48,7 +47,6 @@ #include "chardev/char.h" #include "sysemu/arch_init.h" #include "sysemu/sysemu.h" -#include "exec/address-spaces.h" static MemMapEntry sifive_e_memmap[] = { [SIFIVE_E_DEV_DEBUG] = { 0x0, 0x1000 }, diff --git a/hw/riscv/sifive_u.c b/hw/riscv/sifive_u.c index 7b59942369..698637e8e1 100644 --- a/hw/riscv/sifive_u.c +++ b/hw/riscv/sifive_u.c @@ -35,7 +35,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "qapi/visitor.h" diff --git a/hw/riscv/spike.c b/hw/riscv/spike.c index ec7cb2f707..fe0806a476 100644 --- a/hw/riscv/spike.c +++ b/hw/riscv/spike.c @@ -24,7 +24,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "hw/boards.h" diff --git a/hw/riscv/virt.c b/hw/riscv/virt.c index c0dc69ff33..95a11adaa2 100644 --- a/hw/riscv/virt.c +++ b/hw/riscv/virt.c @@ -20,7 +20,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "qemu/log.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "hw/boards.h" diff --git a/hw/rtc/m48t59.c b/hw/rtc/m48t59.c index d54929e861..690f4e071a 100644 --- a/hw/rtc/m48t59.c +++ b/hw/rtc/m48t59.c @@ -32,7 +32,6 @@ #include "sysemu/runstate.h" #include "sysemu/sysemu.h" #include "hw/sysbus.h" -#include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/bcd.h" #include "qemu/module.h" diff --git a/hw/rtc/mc146818rtc.c b/hw/rtc/mc146818rtc.c index 5d0fcacd0c..3d2d3854e7 100644 --- a/hw/rtc/mc146818rtc.c +++ b/hw/rtc/mc146818rtc.c @@ -42,7 +42,6 @@ #include "qapi/error.h" #include "qapi/qapi-events-misc-target.h" #include "qapi/visitor.h" -#include "exec/address-spaces.h" #include "hw/rtc/mc146818rtc_regs.h" #ifdef TARGET_I386 @@ -1040,6 +1039,7 @@ static void rtc_class_initfn(ObjectClass *klass, void *data) dc->vmsd = &vmstate_rtc; isa->build_aml = rtc_build_aml; device_class_set_props(dc, mc146818rtc_properties); + set_bit(DEVICE_CATEGORY_MISC, dc->categories); } static const TypeInfo mc146818rtc_info = { diff --git a/hw/rx/rx-gdbsim.c b/hw/rx/rx-gdbsim.c index b1d7c2488f..75d1fec6ca 100644 --- a/hw/rx/rx-gdbsim.c +++ b/hw/rx/rx-gdbsim.c @@ -21,12 +21,8 @@ #include "qemu/error-report.h" #include "qapi/error.h" #include "qemu-common.h" -#include "cpu.h" -#include "hw/hw.h" -#include "hw/sysbus.h" #include "hw/loader.h" #include "hw/rx/rx62n.h" -#include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "sysemu/device_tree.h" #include "hw/boards.h" @@ -93,6 +89,7 @@ static void rx_gdbsim_init(MachineState *machine) char *sz = size_to_str(mc->default_ram_size); error_report("Invalid RAM size, should be more than %s", sz); g_free(sz); + exit(1); } /* Allocate memory space */ diff --git a/hw/rx/rx62n.c b/hw/rx/rx62n.c index 9c34ce14de..fa5add9f9d 100644 --- a/hw/rx/rx62n.c +++ b/hw/rx/rx62n.c @@ -23,13 +23,11 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/error-report.h" -#include "hw/hw.h" #include "hw/rx/rx62n.h" #include "hw/loader.h" #include "hw/sysbus.h" #include "hw/qdev-properties.h" #include "sysemu/sysemu.h" -#include "cpu.h" #include "qom/object.h" /* diff --git a/hw/s390x/3270-ccw.c b/hw/s390x/3270-ccw.c index f3e7342b1e..25e628f575 100644 --- a/hw/s390x/3270-ccw.c +++ b/hw/s390x/3270-ccw.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/s390x/css.h" #include "hw/s390x/css-bridge.h" #include "hw/qdev-properties.h" diff --git a/hw/s390x/css-bridge.c b/hw/s390x/css-bridge.c index 9d793d671e..191b29f077 100644 --- a/hw/s390x/css-bridge.c +++ b/hw/s390x/css-bridge.c @@ -20,7 +20,6 @@ #include "hw/s390x/css.h" #include "ccw-device.h" #include "hw/s390x/css-bridge.h" -#include "cpu.h" /* * Invoke device-specific unplug handler, disable the subchannel diff --git a/hw/s390x/css.c b/hw/s390x/css.c index 4149b8e5a7..bed46f5ec3 100644 --- a/hw/s390x/css.c +++ b/hw/s390x/css.c @@ -15,7 +15,6 @@ #include "qemu/bitops.h" #include "qemu/error-report.h" #include "exec/address-spaces.h" -#include "cpu.h" #include "hw/s390x/ioinst.h" #include "hw/qdev-properties.h" #include "hw/s390x/css.h" diff --git a/hw/s390x/ipl.c b/hw/s390x/ipl.c index ff6b55e816..8c863cf386 100644 --- a/hw/s390x/ipl.c +++ b/hw/s390x/ipl.c @@ -18,9 +18,7 @@ #include "qapi/error.h" #include "sysemu/reset.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" #include "sysemu/tcg.h" -#include "cpu.h" #include "elf.h" #include "hw/loader.h" #include "hw/qdev-properties.h" diff --git a/hw/s390x/pv.c b/hw/s390x/pv.c index 93eccfc05d..401b63d6cb 100644 --- a/hw/s390x/pv.c +++ b/hw/s390x/pv.c @@ -13,7 +13,6 @@ #include <linux/kvm.h> -#include "cpu.h" #include "qapi/error.h" #include "qemu/error-report.h" #include "sysemu/kvm.h" diff --git a/hw/s390x/s390-ccw.c b/hw/s390x/s390-ccw.c index b497571863..242491a1ae 100644 --- a/hw/s390x/s390-ccw.c +++ b/hw/s390x/s390-ccw.c @@ -15,7 +15,6 @@ #include <libgen.h> #include "qapi/error.h" #include "qemu/module.h" -#include "hw/sysbus.h" #include "hw/s390x/css.h" #include "hw/s390x/css-bridge.h" #include "hw/s390x/s390-ccw.h" diff --git a/hw/s390x/s390-pci-bus.c b/hw/s390x/s390-pci-bus.c index dd138dae94..7db1c5943f 100644 --- a/hw/s390x/s390-pci-bus.c +++ b/hw/s390x/s390-pci-bus.c @@ -14,7 +14,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "qapi/visitor.h" -#include "cpu.h" #include "hw/s390x/s390-pci-bus.h" #include "hw/s390x/s390-pci-inst.h" #include "hw/s390x/s390-pci-vfio.h" diff --git a/hw/s390x/s390-pci-inst.c b/hw/s390x/s390-pci-inst.c index 4b8326afa4..9ec277d50e 100644 --- a/hw/s390x/s390-pci-inst.c +++ b/hw/s390x/s390-pci-inst.c @@ -12,7 +12,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "exec/memop.h" #include "exec/memory-internal.h" #include "qemu/error-report.h" diff --git a/hw/s390x/s390-stattrib-kvm.c b/hw/s390x/s390-stattrib-kvm.c index f89d8d9d16..f0b11a74e4 100644 --- a/hw/s390x/s390-stattrib-kvm.c +++ b/hw/s390x/s390-stattrib-kvm.c @@ -16,7 +16,6 @@ #include "qemu/error-report.h" #include "sysemu/kvm.h" #include "exec/ram_addr.h" -#include "cpu.h" #include "kvm_s390x.h" Object *kvm_s390_stattrib_create(void) diff --git a/hw/s390x/s390-stattrib.c b/hw/s390x/s390-stattrib.c index 4441e1d331..9eda1c3b2a 100644 --- a/hw/s390x/s390-stattrib.c +++ b/hw/s390x/s390-stattrib.c @@ -11,7 +11,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" -#include "cpu.h" #include "migration/qemu-file.h" #include "migration/register.h" #include "hw/s390x/storage-attributes.h" diff --git a/hw/s390x/s390-virtio-ccw.c b/hw/s390x/s390-virtio-ccw.c index 56b52d2d30..7af27ca305 100644 --- a/hw/s390x/s390-virtio-ccw.c +++ b/hw/s390x/s390-virtio-ccw.c @@ -13,11 +13,7 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" -#include "hw/boards.h" -#include "exec/address-spaces.h" #include "exec/ram_addr.h" -#include "hw/boards.h" #include "hw/s390x/s390-virtio-hcall.h" #include "hw/s390x/sclp.h" #include "hw/s390x/s390_flic.h" diff --git a/hw/s390x/sclp.c b/hw/s390x/sclp.c index 0cf2290826..edb6e3ea01 100644 --- a/hw/s390x/sclp.c +++ b/hw/s390x/sclp.c @@ -15,8 +15,6 @@ #include "qemu/osdep.h" #include "qemu/units.h" #include "qapi/error.h" -#include "cpu.h" -#include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/s390x/sclp.h" #include "hw/s390x/event-facility.h" diff --git a/hw/s390x/sclpcpu.c b/hw/s390x/sclpcpu.c index 62806d3273..f2b1a4b037 100644 --- a/hw/s390x/sclpcpu.c +++ b/hw/s390x/sclpcpu.c @@ -17,7 +17,6 @@ #include "hw/s390x/sclp.h" #include "qemu/module.h" #include "hw/s390x/event-facility.h" -#include "cpu.h" #include "sysemu/cpus.h" typedef struct ConfigMgtData { diff --git a/hw/s390x/virtio-ccw.c b/hw/s390x/virtio-ccw.c index 8195f3546e..92b950e09a 100644 --- a/hw/s390x/virtio-ccw.c +++ b/hw/s390x/virtio-ccw.c @@ -17,7 +17,6 @@ #include "hw/virtio/virtio.h" #include "migration/qemu-file-types.h" #include "hw/virtio/virtio-net.h" -#include "hw/sysbus.h" #include "qemu/bitops.h" #include "qemu/error-report.h" #include "qemu/module.h" diff --git a/hw/scsi/spapr_vscsi.c b/hw/scsi/spapr_vscsi.c index ca5c13c4a8..c210262484 100644 --- a/hw/scsi/spapr_vscsi.c +++ b/hw/scsi/spapr_vscsi.c @@ -34,7 +34,6 @@ #include "qemu/osdep.h" #include "qemu/module.h" -#include "cpu.h" #include "hw/scsi/scsi.h" #include "migration/vmstate.h" #include "scsi/constants.h" diff --git a/hw/sd/cadence_sdhci.c b/hw/sd/cadence_sdhci.c index 0b371c843d..56b8bae1c3 100644 --- a/hw/sd/cadence_sdhci.c +++ b/hw/sd/cadence_sdhci.c @@ -23,10 +23,8 @@ #include "qemu/osdep.h" #include "qemu/bitops.h" #include "qemu/error-report.h" -#include "qemu/log.h" #include "qapi/error.h" #include "migration/vmstate.h" -#include "hw/irq.h" #include "hw/sd/cadence_sdhci.h" #include "sdhci-internal.h" diff --git a/hw/sh4/r2d.c b/hw/sh4/r2d.c index 443820901d..006010f30a 100644 --- a/hw/sh4/r2d.c +++ b/hw/sh4/r2d.c @@ -42,7 +42,6 @@ #include "hw/loader.h" #include "hw/usb.h" #include "hw/block/flash.h" -#include "exec/address-spaces.h" #define FLASH_BASE 0x00000000 #define FLASH_SIZE (16 * MiB) diff --git a/hw/sh4/sh7750.c b/hw/sh4/sh7750.c index f8ac3ec6e3..d53a436d8c 100644 --- a/hw/sh4/sh7750.c +++ b/hw/sh4/sh7750.c @@ -31,7 +31,6 @@ #include "sh7750_regnames.h" #include "hw/sh4/sh_intc.h" #include "hw/timer/tmu012.h" -#include "cpu.h" #include "exec/exec-all.h" #define NB_DEVICES 4 diff --git a/hw/sh4/shix.c b/hw/sh4/shix.c index d9a9fcbc59..b0579aa0f1 100644 --- a/hw/sh4/shix.c +++ b/hw/sh4/shix.c @@ -31,11 +31,9 @@ #include "qapi/error.h" #include "cpu.h" #include "hw/sh4/sh.h" -#include "sysemu/sysemu.h" #include "sysemu/qtest.h" #include "hw/boards.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #define BIOS_FILENAME "shix_bios.bin" diff --git a/hw/sparc/leon3.c b/hw/sparc/leon3.c index 7e16eea9e6..eb5d2a6792 100644 --- a/hw/sparc/leon3.c +++ b/hw/sparc/leon3.c @@ -40,7 +40,6 @@ #include "hw/loader.h" #include "elf.h" #include "trace.h" -#include "exec/address-spaces.h" #include "hw/sparc/grlib.h" #include "hw/misc/grlib_ahb_apb_pnp.h" diff --git a/hw/sparc64/niagara.c b/hw/sparc64/niagara.c index a87d55f6bb..f3e42d0326 100644 --- a/hw/sparc64/niagara.c +++ b/hw/sparc64/niagara.c @@ -31,7 +31,6 @@ #include "hw/loader.h" #include "hw/sparc/sparc64.h" #include "hw/rtc/sun4v-rtc.h" -#include "exec/address-spaces.h" #include "sysemu/block-backend.h" #include "qemu/error-report.h" #include "sysemu/qtest.h" diff --git a/hw/ssi/aspeed_smc.c b/hw/ssi/aspeed_smc.c index 16addee4dc..331a2c5446 100644 --- a/hw/ssi/aspeed_smc.c +++ b/hw/ssi/aspeed_smc.c @@ -29,7 +29,6 @@ #include "qemu/module.h" #include "qemu/error-report.h" #include "qapi/error.h" -#include "exec/address-spaces.h" #include "qemu/units.h" #include "trace.h" @@ -127,6 +126,8 @@ /* DMA Control/Status Register */ #define R_DMA_CTRL (0x80 / 4) +#define DMA_CTRL_REQUEST (1 << 31) +#define DMA_CTRL_GRANT (1 << 30) #define DMA_CTRL_DELAY_MASK 0xf #define DMA_CTRL_DELAY_SHIFT 8 #define DMA_CTRL_FREQ_MASK 0xf @@ -178,10 +179,8 @@ * 0: 4 bytes * 0x7FFFFF: 32M bytes */ -#define DMA_DRAM_ADDR(s, val) ((s)->sdram_base | \ - ((val) & (s)->ctrl->dma_dram_mask)) -#define DMA_FLASH_ADDR(s, val) ((s)->ctrl->flash_window_base | \ - ((val) & (s)->ctrl->dma_flash_mask)) +#define DMA_DRAM_ADDR(s, val) ((val) & (s)->ctrl->dma_dram_mask) +#define DMA_FLASH_ADDR(s, val) ((val) & (s)->ctrl->dma_flash_mask) #define DMA_LENGTH(val) ((val) & 0x01FFFFFC) /* Flash opcodes. */ @@ -230,6 +229,7 @@ static uint32_t aspeed_smc_segment_to_reg(const AspeedSMCState *s, const AspeedSegments *seg); static void aspeed_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg, AspeedSegments *seg); +static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t value); /* * AST2600 definitions @@ -259,6 +259,15 @@ static uint32_t aspeed_2600_smc_segment_to_reg(const AspeedSMCState *s, const AspeedSegments *seg); static void aspeed_2600_smc_reg_to_segment(const AspeedSMCState *s, uint32_t reg, AspeedSegments *seg); +static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t value); + +#define ASPEED_SMC_FEATURE_DMA 0x1 +#define ASPEED_SMC_FEATURE_DMA_GRANT 0x2 + +static inline bool aspeed_smc_has_dma(const AspeedSMCState *s) +{ + return !!(s->ctrl->features & ASPEED_SMC_FEATURE_DMA); +} static const AspeedSMCController controllers[] = { { @@ -273,10 +282,11 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_legacy, .flash_window_base = ASPEED_SOC_SMC_FLASH_BASE, .flash_window_size = 0x6000000, - .has_dma = false, + .features = 0x0, .nregs = ASPEED_SMC_R_SMC_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.fmc-ast2400", .r_conf = R_CONF, @@ -289,12 +299,13 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_fmc, .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x1FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.spi1-ast2400", .r_conf = R_SPI_CONF, @@ -307,10 +318,11 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_spi, .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = false, + .features = 0x0, .nregs = ASPEED_SMC_R_SPI_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.fmc-ast2500", .r_conf = R_CONF, @@ -323,12 +335,13 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2500_fmc, .flash_window_base = ASPEED_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x3FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.spi1-ast2500", .r_conf = R_CONF, @@ -341,10 +354,11 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2500_spi1, .flash_window_base = ASPEED_SOC_SPI_FLASH_BASE, .flash_window_size = 0x8000000, - .has_dma = false, + .features = 0x0, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.spi2-ast2500", .r_conf = R_CONF, @@ -357,10 +371,11 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2500_spi2, .flash_window_base = ASPEED_SOC_SPI2_FLASH_BASE, .flash_window_size = 0x8000000, - .has_dma = false, + .features = 0x0, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_smc_segment_to_reg, .reg_to_segment = aspeed_smc_reg_to_segment, + .dma_ctrl = aspeed_smc_dma_ctrl, }, { .name = "aspeed.fmc-ast2600", .r_conf = R_CONF, @@ -373,12 +388,13 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2600_fmc, .flash_window_base = ASPEED26_SOC_FMC_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x3FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_2600_smc_segment_to_reg, .reg_to_segment = aspeed_2600_smc_reg_to_segment, + .dma_ctrl = aspeed_2600_smc_dma_ctrl, }, { .name = "aspeed.spi1-ast2600", .r_conf = R_CONF, @@ -391,12 +407,14 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2600_spi1, .flash_window_base = ASPEED26_SOC_SPI_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_GRANT, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x3FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_2600_smc_segment_to_reg, .reg_to_segment = aspeed_2600_smc_reg_to_segment, + .dma_ctrl = aspeed_2600_smc_dma_ctrl, }, { .name = "aspeed.spi2-ast2600", .r_conf = R_CONF, @@ -409,12 +427,14 @@ static const AspeedSMCController controllers[] = { .segments = aspeed_segments_ast2600_spi2, .flash_window_base = ASPEED26_SOC_SPI2_FLASH_BASE, .flash_window_size = 0x10000000, - .has_dma = true, + .features = ASPEED_SMC_FEATURE_DMA | + ASPEED_SMC_FEATURE_DMA_GRANT, .dma_flash_mask = 0x0FFFFFFC, .dma_dram_mask = 0x3FFFFFFC, .nregs = ASPEED_SMC_R_MAX, .segment_to_reg = aspeed_2600_smc_segment_to_reg, .reg_to_segment = aspeed_2600_smc_reg_to_segment, + .dma_ctrl = aspeed_2600_smc_dma_ctrl, }, }; @@ -999,11 +1019,11 @@ static uint64_t aspeed_smc_read(void *opaque, hwaddr addr, unsigned int size) addr == R_CE_CMD_CTRL || addr == R_INTR_CTRL || addr == R_DUMMY_DATA || - (s->ctrl->has_dma && addr == R_DMA_CTRL) || - (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) || - (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) || - (s->ctrl->has_dma && addr == R_DMA_LEN) || - (s->ctrl->has_dma && addr == R_DMA_CHECKSUM) || + (aspeed_smc_has_dma(s) && addr == R_DMA_CTRL) || + (aspeed_smc_has_dma(s) && addr == R_DMA_FLASH_ADDR) || + (aspeed_smc_has_dma(s) && addr == R_DMA_DRAM_ADDR) || + (aspeed_smc_has_dma(s) && addr == R_DMA_LEN) || + (aspeed_smc_has_dma(s) && addr == R_DMA_CHECKSUM) || (addr >= R_SEG_ADDR0 && addr < R_SEG_ADDR0 + s->ctrl->max_peripherals) || (addr >= s->r_ctrl0 && addr < s->r_ctrl0 + s->ctrl->max_peripherals)) { @@ -1236,7 +1256,7 @@ static void aspeed_smc_dma_done(AspeedSMCState *s) } } -static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl) +static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) { if (!(dma_ctrl & DMA_CTRL_ENABLE)) { s->regs[R_DMA_CTRL] = dma_ctrl; @@ -1261,6 +1281,46 @@ static void aspeed_smc_dma_ctrl(AspeedSMCState *s, uint64_t dma_ctrl) aspeed_smc_dma_done(s); } +static inline bool aspeed_smc_dma_granted(AspeedSMCState *s) +{ + if (!(s->ctrl->features & ASPEED_SMC_FEATURE_DMA_GRANT)) { + return true; + } + + if (!(s->regs[R_DMA_CTRL] & DMA_CTRL_GRANT)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA not granted\n", __func__); + return false; + } + + return true; +} + +static void aspeed_2600_smc_dma_ctrl(AspeedSMCState *s, uint32_t dma_ctrl) +{ + /* Preserve DMA bits */ + dma_ctrl |= s->regs[R_DMA_CTRL] & (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); + + if (dma_ctrl == 0xAEED0000) { + /* automatically grant request */ + s->regs[R_DMA_CTRL] |= (DMA_CTRL_REQUEST | DMA_CTRL_GRANT); + return; + } + + /* clear request */ + if (dma_ctrl == 0xDEEA0000) { + s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); + return; + } + + if (!aspeed_smc_dma_granted(s)) { + qemu_log_mask(LOG_GUEST_ERROR, "%s: DMA not granted\n", __func__); + return; + } + + aspeed_smc_dma_ctrl(s, dma_ctrl); + s->regs[R_DMA_CTRL] &= ~(DMA_CTRL_REQUEST | DMA_CTRL_GRANT); +} + static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, unsigned int size) { @@ -1292,13 +1352,16 @@ static void aspeed_smc_write(void *opaque, hwaddr addr, uint64_t data, s->regs[addr] = value & 0xff; } else if (addr == R_INTR_CTRL) { s->regs[addr] = value; - } else if (s->ctrl->has_dma && addr == R_DMA_CTRL) { - aspeed_smc_dma_ctrl(s, value); - } else if (s->ctrl->has_dma && addr == R_DMA_DRAM_ADDR) { + } else if (aspeed_smc_has_dma(s) && addr == R_DMA_CTRL) { + s->ctrl->dma_ctrl(s, value); + } else if (aspeed_smc_has_dma(s) && addr == R_DMA_DRAM_ADDR && + aspeed_smc_dma_granted(s)) { s->regs[addr] = DMA_DRAM_ADDR(s, value); - } else if (s->ctrl->has_dma && addr == R_DMA_FLASH_ADDR) { + } else if (aspeed_smc_has_dma(s) && addr == R_DMA_FLASH_ADDR && + aspeed_smc_dma_granted(s)) { s->regs[addr] = DMA_FLASH_ADDR(s, value); - } else if (s->ctrl->has_dma && addr == R_DMA_LEN) { + } else if (aspeed_smc_has_dma(s) && addr == R_DMA_LEN && + aspeed_smc_dma_granted(s)) { s->regs[addr] = DMA_LENGTH(value); } else { qemu_log_mask(LOG_UNIMP, "%s: not implemented: 0x%" HWADDR_PRIx "\n", @@ -1386,7 +1449,9 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) memory_region_init_io(&s->mmio_flash, OBJECT(s), &aspeed_smc_flash_default_ops, s, name, s->ctrl->flash_window_size); - sysbus_init_mmio(sbd, &s->mmio_flash); + memory_region_init_alias(&s->mmio_flash_alias, OBJECT(s), name, + &s->mmio_flash, 0, s->ctrl->flash_window_size); + sysbus_init_mmio(sbd, &s->mmio_flash_alias); s->flashes = g_new0(AspeedSMCFlash, s->ctrl->max_peripherals); @@ -1412,7 +1477,7 @@ static void aspeed_smc_realize(DeviceState *dev, Error **errp) } /* DMA support */ - if (s->ctrl->has_dma) { + if (aspeed_smc_has_dma(s)) { aspeed_smc_dma_setup(s, errp); } } @@ -1432,7 +1497,6 @@ static const VMStateDescription vmstate_aspeed_smc = { static Property aspeed_smc_properties[] = { DEFINE_PROP_UINT32("num-cs", AspeedSMCState, num_cs, 1), DEFINE_PROP_BOOL("inject-failure", AspeedSMCState, inject_failure, false), - DEFINE_PROP_UINT64("sdram-base", AspeedSMCState, sdram_base, 0), DEFINE_PROP_LINK("dram", AspeedSMCState, dram_mr, TYPE_MEMORY_REGION, MemoryRegion *), DEFINE_PROP_END_OF_LIST(), diff --git a/hw/ssi/sifive_spi.c b/hw/ssi/sifive_spi.c index 0c9ebca3c8..03540cf5ca 100644 --- a/hw/ssi/sifive_spi.c +++ b/hw/ssi/sifive_spi.c @@ -24,7 +24,6 @@ #include "hw/qdev-properties.h" #include "hw/sysbus.h" #include "hw/ssi/ssi.h" -#include "sysemu/sysemu.h" #include "qemu/fifo8.h" #include "qemu/log.h" #include "qemu/module.h" diff --git a/hw/ssi/xilinx_spi.c b/hw/ssi/xilinx_spi.c index 49ff275593..b2819a7ff0 100644 --- a/hw/ssi/xilinx_spi.c +++ b/hw/ssi/xilinx_spi.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" #include "migration/vmstate.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/fifo8.h" diff --git a/hw/timer/mips_gictimer.c b/hw/timer/mips_gictimer.c index bc44cd934e..2b0696d4ac 100644 --- a/hw/timer/mips_gictimer.c +++ b/hw/timer/mips_gictimer.c @@ -7,7 +7,6 @@ */ #include "qemu/osdep.h" -#include "hw/sysbus.h" #include "qemu/timer.h" #include "hw/timer/mips_gictimer.h" diff --git a/hw/timer/sse-counter.c b/hw/timer/sse-counter.c index 0384051f15..16c0e8ad15 100644 --- a/hw/timer/sse-counter.c +++ b/hw/timer/sse-counter.c @@ -33,7 +33,6 @@ #include "trace.h" #include "hw/timer/sse-counter.h" #include "hw/sysbus.h" -#include "hw/irq.h" #include "hw/registerfields.h" #include "hw/clock.h" #include "hw/qdev-clock.h" diff --git a/hw/tpm/tpm_crb.c b/hw/tpm/tpm_crb.c index aa9c00aad3..58ebd1469c 100644 --- a/hw/tpm/tpm_crb.c +++ b/hw/tpm/tpm_crb.c @@ -18,7 +18,6 @@ #include "qemu/module.h" #include "qapi/error.h" -#include "exec/address-spaces.h" #include "hw/qdev-properties.h" #include "hw/pci/pci_ids.h" #include "hw/acpi/tpm.h" diff --git a/hw/tricore/tc27x_soc.c b/hw/tricore/tc27x_soc.c index 8af079e6b2..ecd92717b5 100644 --- a/hw/tricore/tc27x_soc.c +++ b/hw/tricore/tc27x_soc.c @@ -21,13 +21,9 @@ #include "qemu/osdep.h" #include "qapi/error.h" #include "hw/sysbus.h" -#include "hw/boards.h" #include "hw/loader.h" #include "qemu/units.h" #include "hw/misc/unimp.h" -#include "exec/address-spaces.h" -#include "qemu/log.h" -#include "cpu.h" #include "hw/tricore/tc27x_soc.h" #include "hw/tricore/triboard.h" diff --git a/hw/tricore/triboard.c b/hw/tricore/triboard.c index 16e2fd7e27..4dba0259cd 100644 --- a/hw/tricore/triboard.c +++ b/hw/tricore/triboard.c @@ -22,11 +22,8 @@ #include "qemu/units.h" #include "qapi/error.h" #include "hw/qdev-properties.h" -#include "cpu.h" #include "net/net.h" -#include "hw/boards.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "elf.h" #include "hw/tricore/tricore.h" #include "qemu/error-report.h" diff --git a/hw/tricore/tricore_testboard.c b/hw/tricore/tricore_testboard.c index 12ea1490fd..51658d9e37 100644 --- a/hw/tricore/tricore_testboard.c +++ b/hw/tricore/tricore_testboard.c @@ -25,7 +25,6 @@ #include "net/net.h" #include "hw/boards.h" #include "hw/loader.h" -#include "exec/address-spaces.h" #include "elf.h" #include "hw/tricore/tricore.h" #include "qemu/error-report.h" diff --git a/hw/usb/ccid-card-passthru.c b/hw/usb/ccid-card-passthru.c index c1a90fcc7a..7212d0d7fb 100644 --- a/hw/usb/ccid-card-passthru.c +++ b/hw/usb/ccid-card-passthru.c @@ -374,7 +374,7 @@ static void passthru_realize(CCIDCardState *base, Error **errp) card->atr_length = sizeof(DEFAULT_ATR); } -static VMStateDescription passthru_vmstate = { +static const VMStateDescription passthru_vmstate = { .name = "ccid-card-passthru", .version_id = 1, .minimum_version_id = 1, diff --git a/hw/usb/chipidea.c b/hw/usb/chipidea.c index 3dcd22ccba..b1c85404d6 100644 --- a/hw/usb/chipidea.c +++ b/hw/usb/chipidea.c @@ -12,7 +12,6 @@ #include "qemu/osdep.h" #include "hw/usb/hcd-ehci.h" #include "hw/usb/chipidea.h" -#include "qemu/log.h" #include "qemu/module.h" enum { diff --git a/hw/usb/dev-smartcard-reader.c b/hw/usb/dev-smartcard-reader.c index bc3d94092a..f7043075be 100644 --- a/hw/usb/dev-smartcard-reader.c +++ b/hw/usb/dev-smartcard-reader.c @@ -1365,7 +1365,7 @@ static int ccid_pre_save(void *opaque) return 0; } -static VMStateDescription bulk_in_vmstate = { +static const VMStateDescription bulk_in_vmstate = { .name = "CCID BulkIn state", .version_id = 1, .minimum_version_id = 1, @@ -1377,7 +1377,7 @@ static VMStateDescription bulk_in_vmstate = { } }; -static VMStateDescription answer_vmstate = { +static const VMStateDescription answer_vmstate = { .name = "CCID Answer state", .version_id = 1, .minimum_version_id = 1, @@ -1388,7 +1388,7 @@ static VMStateDescription answer_vmstate = { } }; -static VMStateDescription usb_device_vmstate = { +static const VMStateDescription usb_device_vmstate = { .name = "usb_device", .version_id = 1, .minimum_version_id = 1, @@ -1400,7 +1400,7 @@ static VMStateDescription usb_device_vmstate = { } }; -static VMStateDescription ccid_vmstate = { +static const VMStateDescription ccid_vmstate = { .name = "usb-ccid", .version_id = 1, .minimum_version_id = 1, diff --git a/hw/usb/hcd-dwc3.c b/hw/usb/hcd-dwc3.c index d547d0538d..279263489e 100644 --- a/hw/usb/hcd-dwc3.c +++ b/hw/usb/hcd-dwc3.c @@ -31,7 +31,6 @@ #include "hw/sysbus.h" #include "hw/register.h" #include "qemu/bitops.h" -#include "qemu/log.h" #include "qom/object.h" #include "migration/vmstate.h" #include "hw/qdev-properties.h" diff --git a/hw/usb/imx-usb-phy.c b/hw/usb/imx-usb-phy.c index e705a03a1f..5d7a549e34 100644 --- a/hw/usb/imx-usb-phy.c +++ b/hw/usb/imx-usb-phy.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "hw/usb/imx-usb-phy.h" #include "migration/vmstate.h" -#include "qemu/log.h" #include "qemu/module.h" static const VMStateDescription vmstate_imx_usbphy = { diff --git a/hw/usb/xen-usb.c b/hw/usb/xen-usb.c index 4d266d7bb4..0f7369e7ed 100644 --- a/hw/usb/xen-usb.c +++ b/hw/usb/xen-usb.c @@ -26,7 +26,6 @@ #include "qemu/config-file.h" #include "qemu/main-loop.h" #include "qemu/option.h" -#include "hw/sysbus.h" #include "hw/usb.h" #include "hw/xen/xen-legacy-backend.h" #include "monitor/qdev.h" diff --git a/hw/usb/xlnx-usb-subsystem.c b/hw/usb/xlnx-usb-subsystem.c index 568257370c..d8deeb6ced 100644 --- a/hw/usb/xlnx-usb-subsystem.c +++ b/hw/usb/xlnx-usb-subsystem.c @@ -24,10 +24,8 @@ #include "qemu/osdep.h" #include "hw/sysbus.h" -#include "hw/irq.h" #include "hw/register.h" #include "qemu/bitops.h" -#include "qemu/log.h" #include "qom/object.h" #include "qapi/error.h" #include "hw/qdev-properties.h" diff --git a/hw/usb/xlnx-versal-usb2-ctrl-regs.c b/hw/usb/xlnx-versal-usb2-ctrl-regs.c index 9eaa59ebb8..1c094aa1a6 100644 --- a/hw/usb/xlnx-versal-usb2-ctrl-regs.c +++ b/hw/usb/xlnx-versal-usb2-ctrl-regs.c @@ -32,7 +32,6 @@ #include "hw/irq.h" #include "hw/register.h" #include "qemu/bitops.h" -#include "qemu/log.h" #include "qom/object.h" #include "migration/vmstate.h" #include "hw/usb/xlnx-versal-usb2-ctrl-regs.h" diff --git a/hw/vfio/ap.c b/hw/vfio/ap.c index 9571c2f91f..4b32aca1a0 100644 --- a/hw/vfio/ap.c +++ b/hw/vfio/ap.c @@ -14,7 +14,6 @@ #include <linux/vfio.h> #include <sys/ioctl.h> #include "qapi/error.h" -#include "hw/sysbus.h" #include "hw/vfio/vfio.h" #include "hw/vfio/vfio-common.h" #include "hw/s390x/ap-device.h" @@ -22,7 +21,6 @@ #include "qemu/module.h" #include "qemu/option.h" #include "qemu/config-file.h" -#include "cpu.h" #include "kvm_s390x.h" #include "migration/vmstate.h" #include "hw/qdev-properties.h" diff --git a/hw/vfio/ccw.c b/hw/vfio/ccw.c index b2df708e4b..e752c845e9 100644 --- a/hw/vfio/ccw.c +++ b/hw/vfio/ccw.c @@ -20,7 +20,6 @@ #include <sys/ioctl.h> #include "qapi/error.h" -#include "hw/sysbus.h" #include "hw/vfio/vfio.h" #include "hw/vfio/vfio-common.h" #include "hw/s390x/s390-ccw.h" diff --git a/hw/vfio/display.c b/hw/vfio/display.c index f04473e3ce..89bc90508f 100644 --- a/hw/vfio/display.c +++ b/hw/vfio/display.c @@ -14,7 +14,6 @@ #include <linux/vfio.h> #include <sys/ioctl.h> -#include "sysemu/sysemu.h" #include "hw/display/edid.h" #include "ui/console.h" #include "qapi/error.h" diff --git a/hw/vfio/migration.c b/hw/vfio/migration.c index 384576cfc0..201642d75e 100644 --- a/hw/vfio/migration.c +++ b/hw/vfio/migration.c @@ -15,7 +15,6 @@ #include "sysemu/runstate.h" #include "hw/vfio/vfio-common.h" -#include "cpu.h" #include "migration/migration.h" #include "migration/vmstate.h" #include "migration/qemu-file.h" diff --git a/hw/vfio/pci-quirks.c b/hw/vfio/pci-quirks.c index b90cf3d37c..e21a6ede11 100644 --- a/hw/vfio/pci-quirks.c +++ b/hw/vfio/pci-quirks.c @@ -22,7 +22,6 @@ #include "qapi/error.h" #include "qapi/visitor.h" #include <sys/ioctl.h> -#include "hw/hw.h" #include "hw/nvram/fw_cfg.h" #include "hw/qdev-properties.h" #include "pci.h" diff --git a/hw/vfio/pci.c b/hw/vfio/pci.c index 5c65aa0a98..ab4077aad2 100644 --- a/hw/vfio/pci.c +++ b/hw/vfio/pci.c @@ -37,7 +37,6 @@ #include "qemu/units.h" #include "sysemu/kvm.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" #include "pci.h" #include "trace.h" #include "qapi/error.h" diff --git a/hw/vfio/spapr.c b/hw/vfio/spapr.c index 2900bd1941..ea3f70bd2f 100644 --- a/hw/vfio/spapr.c +++ b/hw/vfio/spapr.c @@ -9,7 +9,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include <sys/ioctl.h> #include <linux/vfio.h> diff --git a/hw/virtio/vhost.c b/hw/virtio/vhost.c index e2163a0d63..7b7bde7657 100644 --- a/hw/virtio/vhost.c +++ b/hw/virtio/vhost.c @@ -21,7 +21,6 @@ #include "qemu/error-report.h" #include "qemu/memfd.h" #include "standard-headers/linux/vhost_types.h" -#include "exec/address-spaces.h" #include "hw/virtio/virtio-bus.h" #include "hw/virtio/virtio-access.h" #include "migration/blocker.h" diff --git a/hw/virtio/virtio.c b/hw/virtio/virtio.c index 07f4e60b30..9e13cb9e3a 100644 --- a/hw/virtio/virtio.c +++ b/hw/virtio/virtio.c @@ -15,7 +15,6 @@ #include "qapi/error.h" #include "cpu.h" #include "trace.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "qemu/log.h" #include "qemu/main-loop.h" diff --git a/hw/xen/xen-bus-helper.c b/hw/xen/xen-bus-helper.c index b459bb9396..5a1e12b374 100644 --- a/hw/xen/xen-bus-helper.c +++ b/hw/xen/xen-bus-helper.c @@ -6,7 +6,6 @@ */ #include "qemu/osdep.h" -#include "hw/sysbus.h" #include "hw/xen/xen.h" #include "hw/xen/xen-bus.h" #include "hw/xen/xen-bus-helper.h" diff --git a/hw/xen/xen-legacy-backend.c b/hw/xen/xen-legacy-backend.c index b61a4855b7..dd8ae1452d 100644 --- a/hw/xen/xen-legacy-backend.c +++ b/hw/xen/xen-legacy-backend.c @@ -27,7 +27,6 @@ #include "hw/sysbus.h" #include "hw/boards.h" #include "hw/qdev-properties.h" -#include "qemu/log.h" #include "qemu/main-loop.h" #include "qapi/error.h" #include "hw/xen/xen-legacy-backend.h" diff --git a/hw/xen/xen_pt.c b/hw/xen/xen_pt.c index a513fdd62d..232482d65f 100644 --- a/hw/xen/xen_pt.c +++ b/hw/xen/xen_pt.c @@ -64,7 +64,6 @@ #include "hw/xen/xen-legacy-backend.h" #include "xen_pt.h" #include "qemu/range.h" -#include "exec/address-spaces.h" static bool has_igd_gfx_passthru; diff --git a/hw/xtensa/sim.c b/hw/xtensa/sim.c index cbac50db2d..2028fe793d 100644 --- a/hw/xtensa/sim.c +++ b/hw/xtensa/sim.c @@ -27,14 +27,12 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "sysemu/reset.h" #include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "elf.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "xtensa_memory.h" #include "xtensa_sim.h" diff --git a/hw/xtensa/virt.c b/hw/xtensa/virt.c index e47e1de676..a18e3fc910 100644 --- a/hw/xtensa/virt.c +++ b/hw/xtensa/virt.c @@ -27,16 +27,13 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "sysemu/reset.h" -#include "sysemu/sysemu.h" #include "hw/boards.h" #include "hw/loader.h" #include "hw/pci-host/gpex.h" #include "net/net.h" #include "elf.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "qemu/error-report.h" #include "xtensa_memory.h" #include "xtensa_sim.h" diff --git a/hw/xtensa/xtensa_memory.c b/hw/xtensa/xtensa_memory.c index 1c5f62b014..2c1095f017 100644 --- a/hw/xtensa/xtensa_memory.c +++ b/hw/xtensa/xtensa_memory.c @@ -27,7 +27,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "exec/memory.h" #include "qemu/error-report.h" #include "xtensa_memory.h" diff --git a/hw/xtensa/xtfpga.c b/hw/xtensa/xtfpga.c index 7be53f1895..17f087b395 100644 --- a/hw/xtensa/xtfpga.c +++ b/hw/xtensa/xtfpga.c @@ -35,7 +35,6 @@ #include "hw/qdev-properties.h" #include "elf.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "hw/char/serial.h" #include "net/net.h" #include "hw/sysbus.h" diff --git a/include/hw/arm/aspeed_soc.h b/include/hw/arm/aspeed_soc.h index 9359d6da33..d9161d26d6 100644 --- a/include/hw/arm/aspeed_soc.h +++ b/include/hw/arm/aspeed_soc.h @@ -21,6 +21,7 @@ #include "hw/rtc/aspeed_rtc.h" #include "hw/i2c/aspeed_i2c.h" #include "hw/ssi/aspeed_smc.h" +#include "hw/misc/aspeed_hace.h" #include "hw/watchdog/wdt_aspeed.h" #include "hw/net/ftgmac100.h" #include "target/arm/cpu.h" @@ -50,6 +51,7 @@ struct AspeedSoCState { AspeedTimerCtrlState timerctrl; AspeedI2CState i2c; AspeedSCUState scu; + AspeedHACEState hace; AspeedXDMAState xdma; AspeedSMCState fmc; AspeedSMCState spi[ASPEED_SPIS_NUM]; @@ -133,6 +135,7 @@ enum { ASPEED_DEV_XDMA, ASPEED_DEV_EMMC, ASPEED_DEV_KCS, + ASPEED_DEV_HACE, }; #endif /* ASPEED_SOC_H */ diff --git a/include/hw/block/flash.h b/include/hw/block/flash.h index 7dde0adcee..86d8363bb0 100644 --- a/include/hw/block/flash.h +++ b/include/hw/block/flash.h @@ -74,6 +74,6 @@ typedef struct { uint8_t ecc_digest(ECCState *s, uint8_t sample); void ecc_reset(ECCState *s); -extern VMStateDescription vmstate_ecc_state; +extern const VMStateDescription vmstate_ecc_state; #endif diff --git a/include/hw/char/avr_usart.h b/include/hw/char/avr_usart.h index bb57532403..62eaa1528e 100644 --- a/include/hw/char/avr_usart.h +++ b/include/hw/char/avr_usart.h @@ -24,7 +24,6 @@ #include "hw/sysbus.h" #include "chardev/char-fe.h" -#include "hw/hw.h" #include "qom/object.h" /* Offsets of registers. */ diff --git a/include/hw/misc/aspeed_hace.h b/include/hw/misc/aspeed_hace.h new file mode 100644 index 0000000000..94d5ada95f --- /dev/null +++ b/include/hw/misc/aspeed_hace.h @@ -0,0 +1,43 @@ +/* + * ASPEED Hash and Crypto Engine + * + * Copyright (C) 2021 IBM Corp. + * + * SPDX-License-Identifier: GPL-2.0-or-later + */ + +#ifndef ASPEED_HACE_H +#define ASPEED_HACE_H + +#include "hw/sysbus.h" + +#define TYPE_ASPEED_HACE "aspeed.hace" +#define TYPE_ASPEED_AST2400_HACE TYPE_ASPEED_HACE "-ast2400" +#define TYPE_ASPEED_AST2500_HACE TYPE_ASPEED_HACE "-ast2500" +#define TYPE_ASPEED_AST2600_HACE TYPE_ASPEED_HACE "-ast2600" +OBJECT_DECLARE_TYPE(AspeedHACEState, AspeedHACEClass, ASPEED_HACE) + +#define ASPEED_HACE_NR_REGS (0x64 >> 2) + +struct AspeedHACEState { + SysBusDevice parent; + + MemoryRegion iomem; + qemu_irq irq; + + uint32_t regs[ASPEED_HACE_NR_REGS]; + + MemoryRegion *dram_mr; + AddressSpace dram_as; +}; + + +struct AspeedHACEClass { + SysBusDeviceClass parent_class; + + uint32_t src_mask; + uint32_t dest_mask; + uint32_t hash_mask; +}; + +#endif /* _ASPEED_HACE_H_ */ diff --git a/include/hw/misc/aspeed_xdma.h b/include/hw/misc/aspeed_xdma.h index a2dea96984..b1478fd1c6 100644 --- a/include/hw/misc/aspeed_xdma.h +++ b/include/hw/misc/aspeed_xdma.h @@ -13,7 +13,10 @@ #include "qom/object.h" #define TYPE_ASPEED_XDMA "aspeed.xdma" -OBJECT_DECLARE_SIMPLE_TYPE(AspeedXDMAState, ASPEED_XDMA) +#define TYPE_ASPEED_2400_XDMA TYPE_ASPEED_XDMA "-ast2400" +#define TYPE_ASPEED_2500_XDMA TYPE_ASPEED_XDMA "-ast2500" +#define TYPE_ASPEED_2600_XDMA TYPE_ASPEED_XDMA "-ast2600" +OBJECT_DECLARE_TYPE(AspeedXDMAState, AspeedXDMAClass, ASPEED_XDMA) #define ASPEED_XDMA_NUM_REGS (ASPEED_XDMA_REG_SIZE / sizeof(uint32_t)) #define ASPEED_XDMA_REG_SIZE 0x7C @@ -28,4 +31,16 @@ struct AspeedXDMAState { uint32_t regs[ASPEED_XDMA_NUM_REGS]; }; +struct AspeedXDMAClass { + SysBusDeviceClass parent_class; + + uint8_t cmdq_endp; + uint8_t cmdq_wrp; + uint8_t cmdq_rdp; + uint8_t intr_ctrl; + uint32_t intr_ctrl_mask; + uint8_t intr_status; + uint32_t intr_complete; +}; + #endif /* ASPEED_XDMA_H */ diff --git a/include/hw/misc/avr_power.h b/include/hw/misc/avr_power.h index 707df030b1..388e421aa7 100644 --- a/include/hw/misc/avr_power.h +++ b/include/hw/misc/avr_power.h @@ -26,7 +26,6 @@ #define HW_MISC_AVR_POWER_H #include "hw/sysbus.h" -#include "hw/hw.h" #include "qom/object.h" diff --git a/include/hw/misc/stm32f4xx_exti.h b/include/hw/misc/stm32f4xx_exti.h index 24b6fa7724..ea6b0097b0 100644 --- a/include/hw/misc/stm32f4xx_exti.h +++ b/include/hw/misc/stm32f4xx_exti.h @@ -26,7 +26,6 @@ #define HW_STM_EXTI_H #include "hw/sysbus.h" -#include "hw/hw.h" #include "qom/object.h" #define EXTI_IMR 0x00 diff --git a/include/hw/misc/stm32f4xx_syscfg.h b/include/hw/misc/stm32f4xx_syscfg.h index 8c31feccd3..6f8ca49228 100644 --- a/include/hw/misc/stm32f4xx_syscfg.h +++ b/include/hw/misc/stm32f4xx_syscfg.h @@ -26,7 +26,6 @@ #define HW_STM_SYSCFG_H #include "hw/sysbus.h" -#include "hw/hw.h" #include "qom/object.h" #define SYSCFG_MEMRMP 0x00 diff --git a/include/hw/pci-host/i440fx.h b/include/hw/pci-host/i440fx.h index 24fd53942c..7fcfd9485c 100644 --- a/include/hw/pci-host/i440fx.h +++ b/include/hw/pci-host/i440fx.h @@ -11,7 +11,6 @@ #ifndef HW_PCI_I440FX_H #define HW_PCI_I440FX_H -#include "hw/hw.h" #include "hw/pci/pci_bus.h" #include "hw/pci-host/pam.h" #include "qom/object.h" diff --git a/include/hw/ssi/aspeed_smc.h b/include/hw/ssi/aspeed_smc.h index 16c03fe64f..cdaf165300 100644 --- a/include/hw/ssi/aspeed_smc.h +++ b/include/hw/ssi/aspeed_smc.h @@ -47,7 +47,7 @@ typedef struct AspeedSMCController { const AspeedSegments *segments; hwaddr flash_window_base; uint32_t flash_window_size; - bool has_dma; + uint32_t features; hwaddr dma_flash_mask; hwaddr dma_dram_mask; uint32_t nregs; @@ -55,6 +55,7 @@ typedef struct AspeedSMCController { const AspeedSegments *seg); void (*reg_to_segment)(const struct AspeedSMCState *s, uint32_t reg, AspeedSegments *seg); + void (*dma_ctrl)(struct AspeedSMCState *s, uint32_t value); } AspeedSMCController; typedef struct AspeedSMCFlash { @@ -84,6 +85,7 @@ struct AspeedSMCState { MemoryRegion mmio; MemoryRegion mmio_flash; + MemoryRegion mmio_flash_alias; qemu_irq irq; int irqline; @@ -103,9 +105,6 @@ struct AspeedSMCState { uint8_t r_timings; uint8_t conf_enable_w0; - /* for DMA support */ - uint64_t sdram_base; - AddressSpace flash_as; MemoryRegion *dram_mr; AddressSpace dram_as; diff --git a/include/hw/timer/avr_timer16.h b/include/hw/timer/avr_timer16.h index 0536254337..a1a032a24d 100644 --- a/include/hw/timer/avr_timer16.h +++ b/include/hw/timer/avr_timer16.h @@ -30,7 +30,6 @@ #include "hw/sysbus.h" #include "qemu/timer.h" -#include "hw/hw.h" #include "qom/object.h" enum NextInterrupt { diff --git a/linux-user/main.c b/linux-user/main.c index f956afccab..57ba1b45ab 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -38,7 +38,6 @@ #include "qemu/help_option.h" #include "qemu/module.h" #include "qemu/plugin.h" -#include "cpu.h" #include "exec/exec-all.h" #include "tcg/tcg.h" #include "qemu/timer.h" diff --git a/linux-user/semihost.c b/linux-user/semihost.c index 82013b8b48..f53ab526fb 100644 --- a/linux-user/semihost.c +++ b/linux-user/semihost.c @@ -11,7 +11,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "semihosting/console.h" #include "qemu.h" #include <termios.h> diff --git a/meson.build b/meson.build index d8bb1ec5aa..1ffdc9e6c4 100644 --- a/meson.build +++ b/meson.build @@ -1751,6 +1751,7 @@ modules = {} hw_arch = {} target_arch = {} target_softmmu_arch = {} +target_user_arch = {} ############### # Trace files # @@ -2168,6 +2169,11 @@ foreach target : target_dirs abi = config_target['TARGET_ABI_DIR'] target_type='user' qemu_target_name = 'qemu-' + target_name + if arch in target_user_arch + t = target_user_arch[arch].apply(config_target, strict: false) + arch_srcs += t.sources() + arch_deps += t.dependencies() + endif if 'CONFIG_LINUX_USER' in config_target base_dir = 'linux-user' target_inc += include_directories('linux-user/host/' / config_host['ARCH']) diff --git a/migration/ram.c b/migration/ram.c index 4682f3625c..ace8ad431c 100644 --- a/migration/ram.c +++ b/migration/ram.c @@ -27,7 +27,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "qemu/cutils.h" #include "qemu/bitops.h" #include "qemu/bitmap.h" @@ -51,7 +50,6 @@ #include "qemu/rcu_queue.h" #include "migration/colo.h" #include "block.h" -#include "sysemu/sysemu.h" #include "sysemu/cpu-throttle.h" #include "savevm.h" #include "qemu/iov.h" diff --git a/monitor/misc.c b/monitor/misc.c index 55f3744053..f3a393ea59 100644 --- a/monitor/misc.c +++ b/monitor/misc.c @@ -24,7 +24,6 @@ #include "qemu/osdep.h" #include "monitor-internal.h" -#include "cpu.h" #include "monitor/qdev.h" #include "hw/usb.h" #include "hw/pci/pci.h" diff --git a/monitor/monitor.c b/monitor/monitor.c index 636bcc81c5..b90c0f4051 100644 --- a/monitor/monitor.c +++ b/monitor/monitor.c @@ -32,7 +32,6 @@ #include "qemu/error-report.h" #include "qemu/option.h" #include "sysemu/qtest.h" -#include "sysemu/sysemu.h" #include "trace.h" /* diff --git a/net/dump.c b/net/dump.c index 4d538d82a6..a07ba62401 100644 --- a/net/dump.c +++ b/net/dump.c @@ -28,7 +28,6 @@ #include "qapi/error.h" #include "qemu/error-report.h" #include "qemu/iov.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/timer.h" #include "qapi/visitor.h" diff --git a/net/filter-replay.c b/net/filter-replay.c index eef8443059..54690676ef 100644 --- a/net/filter-replay.c +++ b/net/filter-replay.c @@ -13,7 +13,6 @@ #include "clients.h" #include "qemu/error-report.h" #include "qemu/iov.h" -#include "qemu/log.h" #include "qemu/module.h" #include "qemu/timer.h" #include "qapi/visitor.h" diff --git a/net/net.c b/net/net.c index edf9b95418..2a472604ec 100644 --- a/net/net.c +++ b/net/net.c @@ -51,9 +51,7 @@ #include "qemu/option.h" #include "qapi/error.h" #include "qapi/opts-visitor.h" -#include "sysemu/sysemu.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" #include "net/filter.h" #include "qapi/string-output-visitor.h" diff --git a/net/netmap.c b/net/netmap.c index 350f097f91..9e0cec58d3 100644 --- a/net/netmap.c +++ b/net/netmap.c @@ -33,7 +33,6 @@ #include "net/net.h" #include "net/tap.h" #include "clients.h" -#include "sysemu/sysemu.h" #include "qemu/error-report.h" #include "qapi/error.h" #include "qemu/iov.h" diff --git a/plugins/api.c b/plugins/api.c index b22998cd7c..817c9b6b69 100644 --- a/plugins/api.c +++ b/plugins/api.c @@ -36,8 +36,6 @@ #include "qemu/osdep.h" #include "qemu/plugin.h" -#include "cpu.h" -#include "sysemu/sysemu.h" #include "tcg/tcg.h" #include "exec/exec-all.h" #include "exec/ram_addr.h" diff --git a/plugins/core.c b/plugins/core.c index 87b823bbc4..55d188af51 100644 --- a/plugins/core.c +++ b/plugins/core.c @@ -23,10 +23,8 @@ #include "hw/core/cpu.h" #include "exec/cpu-common.h" -#include "cpu.h" #include "exec/exec-all.h" #include "exec/helper-proto.h" -#include "sysemu/sysemu.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" #include "trace/mem-internal.h" /* mem_info macros */ diff --git a/plugins/loader.c b/plugins/loader.c index 8550e61184..05df40398d 100644 --- a/plugins/loader.c +++ b/plugins/loader.c @@ -27,7 +27,6 @@ #include "qemu/xxhash.h" #include "qemu/plugin.h" #include "hw/core/cpu.h" -#include "cpu.h" #include "exec/exec-all.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" diff --git a/qemu-options.hx b/qemu-options.hx index fd21002bd6..635dc8a624 100644 --- a/qemu-options.hx +++ b/qemu-options.hx @@ -4508,11 +4508,11 @@ SRST the guest RAM with huge pages. The ``id`` parameter is a unique ID that will be used to - reference this memory region when configuring the ``-numa`` - argument. + reference this memory region in other parameters, e.g. ``-numa``, + ``-device nvdimm``, etc. The ``size`` option provides the size of the memory region, and - accepts common suffixes, eg ``500M``. + accepts common suffixes, e.g. ``500M``. The ``mem-path`` provides the path to either a shared memory or huge page filesystem mount. diff --git a/scripts/qemu-binfmt-conf.sh b/scripts/qemu-binfmt-conf.sh index 573b5dc6ac..7de996d536 100755 --- a/scripts/qemu-binfmt-conf.sh +++ b/scripts/qemu-binfmt-conf.sh @@ -294,7 +294,9 @@ package qemu-$cpu interpreter $qemu magic $magic mask $mask -credential $CREDENTIAL +credentials $CREDENTIAL +preserve $PRESERVE_ARG0 +fix_binary $PERSISTENT EOF } diff --git a/semihosting/arm-compat-semi.c b/semihosting/arm-compat-semi.c index fe079ca93a..1c29146dcf 100644 --- a/semihosting/arm-compat-semi.c +++ b/semihosting/arm-compat-semi.c @@ -33,11 +33,9 @@ #include "qemu/osdep.h" -#include "cpu.h" #include "semihosting/semihost.h" #include "semihosting/console.h" #include "semihosting/common-semi.h" -#include "qemu/log.h" #include "qemu/timer.h" #ifdef CONFIG_USER_ONLY #include "qemu.h" diff --git a/semihosting/config.c b/semihosting/config.c index 3548e0f627..137171b717 100644 --- a/semihosting/config.c +++ b/semihosting/config.c @@ -24,7 +24,6 @@ #include "qemu/error-report.h" #include "semihosting/semihost.h" #include "chardev/char.h" -#include "sysemu/sysemu.h" QemuOptsList qemu_semihosting_config_opts = { .name = "semihosting-config", diff --git a/semihosting/console.c b/semihosting/console.c index c9ebd6fdd0..ef6958d844 100644 --- a/semihosting/console.c +++ b/semihosting/console.c @@ -16,7 +16,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "semihosting/semihost.h" #include "semihosting/console.h" #include "exec/gdbstub.h" @@ -24,7 +23,6 @@ #include "qemu/log.h" #include "chardev/char.h" #include "chardev/char-fe.h" -#include "sysemu/sysemu.h" #include "qemu/main-loop.h" #include "qapi/error.h" #include "qemu/fifo8.h" diff --git a/softmmu/arch_init.c b/softmmu/arch_init.c index 7fd5c09b2b..f09bab830c 100644 --- a/softmmu/arch_init.c +++ b/softmmu/arch_init.c @@ -22,8 +22,6 @@ * THE SOFTWARE. */ #include "qemu/osdep.h" -#include "cpu.h" -#include "sysemu/sysemu.h" #include "sysemu/arch_init.h" #include "hw/pci/pci.h" #include "hw/audio/soundhw.h" diff --git a/softmmu/device_tree.c b/softmmu/device_tree.c index 2691c58cf6..b621f63fba 100644 --- a/softmmu/device_tree.c +++ b/softmmu/device_tree.c @@ -23,7 +23,6 @@ #include "qemu/bswap.h" #include "qemu/cutils.h" #include "sysemu/device_tree.h" -#include "sysemu/sysemu.h" #include "hw/loader.h" #include "hw/boards.h" #include "qemu/config-file.h" diff --git a/softmmu/memory.c b/softmmu/memory.c index d4493ef9e4..3bb533c0bc 100644 --- a/softmmu/memory.c +++ b/softmmu/memory.c @@ -16,9 +16,7 @@ #include "qemu/osdep.h" #include "qemu/log.h" #include "qapi/error.h" -#include "cpu.h" #include "exec/memory.h" -#include "exec/address-spaces.h" #include "qapi/visitor.h" #include "qemu/bitops.h" #include "qemu/error-report.h" diff --git a/softmmu/memory_mapping.c b/softmmu/memory_mapping.c index 18d0b8067c..e7af276546 100644 --- a/softmmu/memory_mapping.c +++ b/softmmu/memory_mapping.c @@ -14,7 +14,6 @@ #include "qemu/osdep.h" #include "qapi/error.h" -#include "cpu.h" #include "sysemu/memory_mapping.h" #include "exec/memory.h" #include "exec/address-spaces.h" diff --git a/softmmu/physmem.c b/softmmu/physmem.c index 85034d9c11..5232696571 100644 --- a/softmmu/physmem.c +++ b/softmmu/physmem.c @@ -23,7 +23,6 @@ #include "qemu/cutils.h" #include "qemu/cacheflush.h" -#include "cpu.h" #ifdef CONFIG_TCG #include "hw/core/tcg-cpu-ops.h" @@ -36,7 +35,6 @@ #include "hw/boards.h" #include "hw/xen/xen.h" #include "sysemu/kvm.h" -#include "sysemu/sysemu.h" #include "sysemu/tcg.h" #include "sysemu/qtest.h" #include "qemu/timer.h" @@ -48,7 +46,6 @@ #include "sysemu/dma.h" #include "sysemu/hostmem.h" #include "sysemu/hw_accel.h" -#include "exec/address-spaces.h" #include "sysemu/xen-mapcache.h" #include "trace/trace-root.h" diff --git a/softmmu/qdev-monitor.c b/softmmu/qdev-monitor.c index a9955b97a0..721dec2d82 100644 --- a/softmmu/qdev-monitor.c +++ b/softmmu/qdev-monitor.c @@ -35,7 +35,6 @@ #include "qemu/qemu-print.h" #include "qemu/option_int.h" #include "sysemu/block-backend.h" -#include "sysemu/sysemu.h" #include "migration/misc.h" #include "migration/migration.h" #include "qemu/cutils.h" diff --git a/softmmu/vl.c b/softmmu/vl.c index aadb526138..307944aef3 100644 --- a/softmmu/vl.c +++ b/softmmu/vl.c @@ -27,7 +27,6 @@ #include "qemu/datadir.h" #include "qemu/units.h" #include "exec/cpu-common.h" -#include "hw/boards.h" #include "hw/qdev-properties.h" #include "qapi/compat-policy.h" #include "qapi/error.h" diff --git a/stubs/semihost.c b/stubs/semihost.c index 1b30f38b03..4bf2cf71b9 100644 --- a/stubs/semihost.c +++ b/stubs/semihost.c @@ -12,7 +12,6 @@ #include "qemu/option.h" #include "qemu/error-report.h" #include "semihosting/semihost.h" -#include "sysemu/sysemu.h" /* Empty config */ QemuOptsList qemu_semihosting_config_opts = { diff --git a/target/arm/cpu.c b/target/arm/cpu.c index 0dd623e590..4eb0d2f85c 100644 --- a/target/arm/cpu.c +++ b/target/arm/cpu.c @@ -36,7 +36,6 @@ #include "hw/loader.h" #include "hw/boards.h" #endif -#include "sysemu/sysemu.h" #include "sysemu/tcg.h" #include "sysemu/hw_accel.h" #include "kvm_arm.h" diff --git a/target/arm/op_helper.c b/target/arm/op_helper.c index 65cb37d088..78b831f181 100644 --- a/target/arm/op_helper.c +++ b/target/arm/op_helper.c @@ -17,7 +17,6 @@ * License along with this library; if not, see <http://www.gnu.org/licenses/>. */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/main-loop.h" #include "cpu.h" #include "exec/helper-proto.h" diff --git a/target/hexagon/cpu.c b/target/hexagon/cpu.c index ff44fd6637..ebe60a6e15 100644 --- a/target/hexagon/cpu.c +++ b/target/hexagon/cpu.c @@ -16,7 +16,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "qemu/qemu-print.h" #include "cpu.h" #include "internal.h" diff --git a/target/hexagon/decode.c b/target/hexagon/decode.c index dffe1d1972..d424245598 100644 --- a/target/hexagon/decode.c +++ b/target/hexagon/decode.c @@ -16,7 +16,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "iclass.h" #include "attribs.h" #include "genptr.h" diff --git a/target/hexagon/genptr.c b/target/hexagon/genptr.c index f93f8953ff..797a6c0cc9 100644 --- a/target/hexagon/genptr.c +++ b/target/hexagon/genptr.c @@ -16,7 +16,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "cpu.h" #include "internal.h" #include "tcg/tcg-op.h" diff --git a/target/i386/cpu.h b/target/i386/cpu.h index 570f916878..1bc300ce85 100644 --- a/target/i386/cpu.h +++ b/target/i386/cpu.h @@ -1786,7 +1786,7 @@ struct X86CPU { #ifndef CONFIG_USER_ONLY -extern VMStateDescription vmstate_x86_cpu; +extern const VMStateDescription vmstate_x86_cpu; #endif int x86_cpu_pending_interrupt(CPUState *cs, int interrupt_request); diff --git a/target/i386/hvf/hvf.c b/target/i386/hvf/hvf.c index 15f14ac69e..f044181d06 100644 --- a/target/i386/hvf/hvf.c +++ b/target/i386/hvf/hvf.c @@ -67,7 +67,6 @@ #include <Hypervisor/hv_vmx.h> #include <sys/sysctl.h> -#include "exec/address-spaces.h" #include "hw/i386/apic_internal.h" #include "qemu/main-loop.h" #include "qemu/accel.h" diff --git a/target/i386/hvf/x86_mmu.c b/target/i386/hvf/x86_mmu.c index 882a6237ee..78fff04684 100644 --- a/target/i386/hvf/x86_mmu.c +++ b/target/i386/hvf/x86_mmu.c @@ -24,7 +24,6 @@ #include "x86_mmu.h" #include "vmcs.h" #include "vmx.h" -#include "exec/address-spaces.h" #define pte_present(pte) (pte & PT_PRESENT) #define pte_write_access(pte) (pte & PT_WRITE) diff --git a/target/i386/machine.c b/target/i386/machine.c index 137604ddb8..f6f094f1c9 100644 --- a/target/i386/machine.c +++ b/target/i386/machine.c @@ -1396,7 +1396,7 @@ static const VMStateDescription vmstate_msr_tsx_ctrl = { } }; -VMStateDescription vmstate_x86_cpu = { +const VMStateDescription vmstate_x86_cpu = { .name = "cpu", .version_id = 12, .minimum_version_id = 11, diff --git a/target/i386/sev.c b/target/i386/sev.c index 72b9e2ab40..9a43be11cb 100644 --- a/target/i386/sev.c +++ b/target/i386/sev.c @@ -30,7 +30,6 @@ #include "trace.h" #include "migration/blocker.h" #include "qom/object.h" -#include "exec/address-spaces.h" #include "monitor/monitor.h" #include "exec/confidential-guest-support.h" #include "hw/i386/pc.h" diff --git a/target/lm32/lm32-semi.c b/target/lm32/lm32-semi.c index 6a11a6299a..661a770249 100644 --- a/target/lm32/lm32-semi.c +++ b/target/lm32/lm32-semi.c @@ -13,7 +13,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "exec/helper-proto.h" -#include "qemu/log.h" #include "exec/softmmu-semi.h" enum { diff --git a/target/mips/cpu.c b/target/mips/cpu.c index dce1e166bd..1ad2fe4aa3 100644 --- a/target/mips/cpu.c +++ b/target/mips/cpu.c @@ -35,155 +35,84 @@ #include "qapi/qapi-commands-machine-target.h" #include "fpu_helper.h" -#if !defined(CONFIG_USER_ONLY) +const char regnames[32][4] = { + "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", + "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", + "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", + "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", +}; -/* Called for updates to CP0_Status. */ -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +static void fpu_dump_fpr(fpr_t *fpr, FILE *f, bool is_fpu64) { - int32_t tcstatus, *tcst; - uint32_t v = cpu->CP0_Status; - uint32_t cu, mx, asid, ksu; - uint32_t mask = ((1 << CP0TCSt_TCU3) - | (1 << CP0TCSt_TCU2) - | (1 << CP0TCSt_TCU1) - | (1 << CP0TCSt_TCU0) - | (1 << CP0TCSt_TMX) - | (3 << CP0TCSt_TKSU) - | (0xff << CP0TCSt_TASID)); - - cu = (v >> CP0St_CU0) & 0xf; - mx = (v >> CP0St_MX) & 0x1; - ksu = (v >> CP0St_KSU) & 0x3; - asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - - tcstatus = cu << CP0TCSt_TCU0; - tcstatus |= mx << CP0TCSt_TMX; - tcstatus |= ksu << CP0TCSt_TKSU; - tcstatus |= asid; - - if (tc == cpu->current_tc) { - tcst = &cpu->active_tc.CP0_TCStatus; + if (is_fpu64) { + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu: %13g\n", + fpr->w[FP_ENDIAN_IDX], fpr->d, + (double)fpr->fd, + (double)fpr->fs[FP_ENDIAN_IDX], + (double)fpr->fs[!FP_ENDIAN_IDX]); } else { - tcst = &cpu->tcs[tc].CP0_TCStatus; - } + fpr_t tmp; - *tcst &= ~mask; - *tcst |= tcstatus; - compute_hflags(cpu); + tmp.w[FP_ENDIAN_IDX] = fpr->w[FP_ENDIAN_IDX]; + tmp.w[!FP_ENDIAN_IDX] = (fpr + 1)->w[FP_ENDIAN_IDX]; + qemu_fprintf(f, "w:%08x d:%016" PRIx64 " fd:%13g fs:%13g psu:%13g\n", + tmp.w[FP_ENDIAN_IDX], tmp.d, + (double)tmp.fd, + (double)tmp.fs[FP_ENDIAN_IDX], + (double)tmp.fs[!FP_ENDIAN_IDX]); + } } -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +static void fpu_dump_state(CPUMIPSState *env, FILE *f, int flags) { - uint32_t mask = env->CP0_Status_rw_bitmask; - target_ulong old = env->CP0_Status; - - if (env->insn_flags & ISA_MIPS_R6) { - bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; -#if defined(TARGET_MIPS64) - uint32_t ksux = (1 << CP0St_KX) & val; - ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ - ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ - val = (val & ~(7 << CP0St_UX)) | ksux; -#endif - if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { - mask &= ~(3 << CP0St_KSU); - } - mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); - } + int i; + bool is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); - env->CP0_Status = (old & ~mask) | (val & mask); -#if defined(TARGET_MIPS64) - if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { - /* Access to at least one of the 64-bit segments has been disabled */ - tlb_flush(env_cpu(env)); - } -#endif - if (ase_mt_available(env)) { - sync_c0_status(env, env, env->current_tc); - } else { - compute_hflags(env); + qemu_fprintf(f, + "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", + env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, + get_float_exception_flags(&env->active_fpu.fp_status)); + for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { + qemu_fprintf(f, "%3s: ", fregnames[i]); + fpu_dump_fpr(&env->active_fpu.fpr[i], f, is_fpu64); } } -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +static void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) { - uint32_t mask = 0x00C00300; - uint32_t old = env->CP0_Cause; + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; int i; - if (env->insn_flags & ISA_MIPS_R2) { - mask |= 1 << CP0Ca_DC; - } - if (env->insn_flags & ISA_MIPS_R6) { - mask &= ~((1 << CP0Ca_WP) & val); - } - - env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); - - if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { - if (env->CP0_Cause & (1 << CP0Ca_DC)) { - cpu_mips_stop_count(env); - } else { - cpu_mips_start_count(env); + qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx + " LO=0x" TARGET_FMT_lx " ds %04x " + TARGET_FMT_lx " " TARGET_FMT_ld "\n", + env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], + env->hflags, env->btarget, env->bcond); + for (i = 0; i < 32; i++) { + if ((i & 3) == 0) { + qemu_fprintf(f, "GPR%02d:", i); } - } - - /* Set/reset software interrupts */ - for (i = 0 ; i < 2 ; i++) { - if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { - cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); + qemu_fprintf(f, " %s " TARGET_FMT_lx, + regnames[i], env->active_tc.gpr[i]); + if ((i & 3) == 3) { + qemu_fprintf(f, "\n"); } } -} -#endif /* !CONFIG_USER_ONLY */ - -static const char * const excp_names[EXCP_LAST + 1] = { - [EXCP_RESET] = "reset", - [EXCP_SRESET] = "soft reset", - [EXCP_DSS] = "debug single step", - [EXCP_DINT] = "debug interrupt", - [EXCP_NMI] = "non-maskable interrupt", - [EXCP_MCHECK] = "machine check", - [EXCP_EXT_INTERRUPT] = "interrupt", - [EXCP_DFWATCH] = "deferred watchpoint", - [EXCP_DIB] = "debug instruction breakpoint", - [EXCP_IWATCH] = "instruction fetch watchpoint", - [EXCP_AdEL] = "address error load", - [EXCP_AdES] = "address error store", - [EXCP_TLBF] = "TLB refill", - [EXCP_IBE] = "instruction bus error", - [EXCP_DBp] = "debug breakpoint", - [EXCP_SYSCALL] = "syscall", - [EXCP_BREAK] = "break", - [EXCP_CpU] = "coprocessor unusable", - [EXCP_RI] = "reserved instruction", - [EXCP_OVERFLOW] = "arithmetic overflow", - [EXCP_TRAP] = "trap", - [EXCP_FPE] = "floating point", - [EXCP_DDBS] = "debug data break store", - [EXCP_DWATCH] = "data watchpoint", - [EXCP_LTLBL] = "TLB modify", - [EXCP_TLBL] = "TLB load", - [EXCP_TLBS] = "TLB store", - [EXCP_DBE] = "data bus error", - [EXCP_DDBL] = "debug data break load", - [EXCP_THREAD] = "thread", - [EXCP_MDMX] = "MDMX", - [EXCP_C2E] = "precise coprocessor 2", - [EXCP_CACHE] = "cache error", - [EXCP_TLBXI] = "TLB execute-inhibit", - [EXCP_TLBRI] = "TLB read-inhibit", - [EXCP_MSADIS] = "MSA disabled", - [EXCP_MSAFPE] = "MSA floating point", -}; - -const char *mips_exception_name(int32_t exception) -{ - if (exception < 0 || exception > EXCP_LAST) { - return "unknown"; + qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" + TARGET_FMT_lx "\n", + env->CP0_Status, env->CP0_Cause, env->CP0_EPC); + qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" + PRIx64 "\n", + env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); + qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", + env->CP0_Config2, env->CP0_Config3); + qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", + env->CP0_Config4, env->CP0_Config5); + if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { + fpu_dump_state(env, f, flags); } - return excp_names[exception]; } void cpu_set_exception_base(int vp_index, target_ulong address) @@ -192,101 +121,13 @@ void cpu_set_exception_base(int vp_index, target_ulong address) vp->env.exception_base = address; } -target_ulong exception_resume_pc(CPUMIPSState *env) -{ - target_ulong bad_pc; - target_ulong isa_mode; - - isa_mode = !!(env->hflags & MIPS_HFLAG_M16); - bad_pc = env->active_tc.PC | isa_mode; - if (env->hflags & MIPS_HFLAG_BMASK) { - /* - * If the exception was raised from a delay slot, come back to - * the jump. - */ - bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - } - - return bad_pc; -} - -bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) -{ - if (interrupt_request & CPU_INTERRUPT_HARD) { - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - if (cpu_mips_hw_interrupts_enabled(env) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cs->exception_index = EXCP_EXT_INTERRUPT; - env->error_code = 0; - mips_cpu_do_interrupt(cs); - return true; - } - } - return false; -} - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, - uint32_t exception, - int error_code, - uintptr_t pc) -{ - CPUState *cs = env_cpu(env); - - qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", - __func__, exception, mips_exception_name(exception), - error_code); - cs->exception_index = exception; - env->error_code = error_code; - - cpu_loop_exit_restore(cs, pc); -} - static void mips_cpu_set_pc(CPUState *cs, vaddr value) { MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - env->active_tc.PC = value & ~(target_ulong)1; - if (value & 1) { - env->hflags |= MIPS_HFLAG_M16; - } else { - env->hflags &= ~(MIPS_HFLAG_M16); - } + mips_env_set_pc(&cpu->env, value); } -#ifdef CONFIG_TCG -static void mips_cpu_synchronize_from_tb(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - env->active_tc.PC = tb->pc; - env->hflags &= ~MIPS_HFLAG_BMASK; - env->hflags |= tb->flags & MIPS_HFLAG_BMASK; -} - -# ifndef CONFIG_USER_ONLY -static bool mips_io_recompile_replay_branch(CPUState *cs, - const TranslationBlock *tb) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - if ((env->hflags & MIPS_HFLAG_BMASK) != 0 - && env->active_tc.PC != tb->pc) { - env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); - env->hflags &= ~MIPS_HFLAG_BMASK; - return true; - } - return false; -} -# endif /* !CONFIG_USER_ONLY */ -#endif /* CONFIG_TCG */ - static bool mips_cpu_has_work(CPUState *cs) { MIPSCPU *cpu = MIPS_CPU(cs); @@ -634,7 +475,7 @@ static void mips_cpu_realizefn(DeviceState *dev, Error **errp) env->exception_base = (int32_t)0xBFC00000; -#ifndef CONFIG_USER_ONLY +#if defined(CONFIG_TCG) && !defined(CONFIG_USER_ONLY) mmu_init(env, env->cpu_model); #endif fpu_init(env, env->cpu_model); diff --git a/target/mips/fpu.c b/target/mips/fpu.c new file mode 100644 index 0000000000..c7c487c1f9 --- /dev/null +++ b/target/mips/fpu.c @@ -0,0 +1,25 @@ +/* + * Helpers for emulation of FPU-related MIPS instructions. + * + * Copyright (C) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ +#include "qemu/osdep.h" +#include "fpu/softfloat-helpers.h" +#include "fpu_helper.h" + +/* convert MIPS rounding mode in FCR31 to IEEE library */ +const FloatRoundMode ieee_rm[4] = { + float_round_nearest_even, + float_round_to_zero, + float_round_up, + float_round_down +}; + +const char fregnames[32][4] = { + "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", + "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", + "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", + "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", +}; diff --git a/target/mips/helper.h b/target/mips/helper.h index 709494445d..a9c6c7d1a3 100644 --- a/target/mips/helper.h +++ b/target/mips/helper.h @@ -2,10 +2,6 @@ DEF_HELPER_3(raise_exception_err, noreturn, env, i32, int) DEF_HELPER_2(raise_exception, noreturn, env, i32) DEF_HELPER_1(raise_exception_debug, noreturn, env) -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(do_semihosting, void, env) -#endif - #ifdef TARGET_MIPS64 DEF_HELPER_4(sdl, void, env, tl, tl, int) DEF_HELPER_4(sdr, void, env, tl, tl, int) @@ -42,164 +38,6 @@ DEF_HELPER_FLAGS_1(dbitswap, TCG_CALL_NO_RWG_SE, tl, tl) DEF_HELPER_FLAGS_4(rotx, TCG_CALL_NO_RWG_SE, tl, tl, i32, i32, i32) -#ifndef CONFIG_USER_ONLY -/* CP0 helpers */ -DEF_HELPER_1(mfc0_mvpcontrol, tl, env) -DEF_HELPER_1(mfc0_mvpconf0, tl, env) -DEF_HELPER_1(mfc0_mvpconf1, tl, env) -DEF_HELPER_1(mftc0_vpecontrol, tl, env) -DEF_HELPER_1(mftc0_vpeconf0, tl, env) -DEF_HELPER_1(mfc0_random, tl, env) -DEF_HELPER_1(mfc0_tcstatus, tl, env) -DEF_HELPER_1(mftc0_tcstatus, tl, env) -DEF_HELPER_1(mfc0_tcbind, tl, env) -DEF_HELPER_1(mftc0_tcbind, tl, env) -DEF_HELPER_1(mfc0_tcrestart, tl, env) -DEF_HELPER_1(mftc0_tcrestart, tl, env) -DEF_HELPER_1(mfc0_tchalt, tl, env) -DEF_HELPER_1(mftc0_tchalt, tl, env) -DEF_HELPER_1(mfc0_tccontext, tl, env) -DEF_HELPER_1(mftc0_tccontext, tl, env) -DEF_HELPER_1(mfc0_tcschedule, tl, env) -DEF_HELPER_1(mftc0_tcschedule, tl, env) -DEF_HELPER_1(mfc0_tcschefback, tl, env) -DEF_HELPER_1(mftc0_tcschefback, tl, env) -DEF_HELPER_1(mfc0_count, tl, env) -DEF_HELPER_1(mfc0_saar, tl, env) -DEF_HELPER_1(mfhc0_saar, tl, env) -DEF_HELPER_1(mftc0_entryhi, tl, env) -DEF_HELPER_1(mftc0_status, tl, env) -DEF_HELPER_1(mftc0_cause, tl, env) -DEF_HELPER_1(mftc0_epc, tl, env) -DEF_HELPER_1(mftc0_ebase, tl, env) -DEF_HELPER_2(mftc0_configx, tl, env, tl) -DEF_HELPER_1(mfc0_lladdr, tl, env) -DEF_HELPER_1(mfc0_maar, tl, env) -DEF_HELPER_1(mfhc0_maar, tl, env) -DEF_HELPER_2(mfc0_watchlo, tl, env, i32) -DEF_HELPER_2(mfc0_watchhi, tl, env, i32) -DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) -DEF_HELPER_1(mfc0_debug, tl, env) -DEF_HELPER_1(mftc0_debug, tl, env) -#ifdef TARGET_MIPS64 -DEF_HELPER_1(dmfc0_tcrestart, tl, env) -DEF_HELPER_1(dmfc0_tchalt, tl, env) -DEF_HELPER_1(dmfc0_tccontext, tl, env) -DEF_HELPER_1(dmfc0_tcschedule, tl, env) -DEF_HELPER_1(dmfc0_tcschefback, tl, env) -DEF_HELPER_1(dmfc0_lladdr, tl, env) -DEF_HELPER_1(dmfc0_maar, tl, env) -DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) -DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) -DEF_HELPER_1(dmfc0_saar, tl, env) -#endif /* TARGET_MIPS64 */ - -DEF_HELPER_2(mtc0_index, void, env, tl) -DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) -DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) -DEF_HELPER_2(mtc0_yqmask, void, env, tl) -DEF_HELPER_2(mtc0_vpeopt, void, env, tl) -DEF_HELPER_2(mtc0_entrylo0, void, env, tl) -DEF_HELPER_2(mtc0_tcstatus, void, env, tl) -DEF_HELPER_2(mttc0_tcstatus, void, env, tl) -DEF_HELPER_2(mtc0_tcbind, void, env, tl) -DEF_HELPER_2(mttc0_tcbind, void, env, tl) -DEF_HELPER_2(mtc0_tcrestart, void, env, tl) -DEF_HELPER_2(mttc0_tcrestart, void, env, tl) -DEF_HELPER_2(mtc0_tchalt, void, env, tl) -DEF_HELPER_2(mttc0_tchalt, void, env, tl) -DEF_HELPER_2(mtc0_tccontext, void, env, tl) -DEF_HELPER_2(mttc0_tccontext, void, env, tl) -DEF_HELPER_2(mtc0_tcschedule, void, env, tl) -DEF_HELPER_2(mttc0_tcschedule, void, env, tl) -DEF_HELPER_2(mtc0_tcschefback, void, env, tl) -DEF_HELPER_2(mttc0_tcschefback, void, env, tl) -DEF_HELPER_2(mtc0_entrylo1, void, env, tl) -DEF_HELPER_2(mtc0_context, void, env, tl) -DEF_HELPER_2(mtc0_memorymapid, void, env, tl) -DEF_HELPER_2(mtc0_pagemask, void, env, tl) -DEF_HELPER_2(mtc0_pagegrain, void, env, tl) -DEF_HELPER_2(mtc0_segctl0, void, env, tl) -DEF_HELPER_2(mtc0_segctl1, void, env, tl) -DEF_HELPER_2(mtc0_segctl2, void, env, tl) -DEF_HELPER_2(mtc0_pwfield, void, env, tl) -DEF_HELPER_2(mtc0_pwsize, void, env, tl) -DEF_HELPER_2(mtc0_wired, void, env, tl) -DEF_HELPER_2(mtc0_srsconf0, void, env, tl) -DEF_HELPER_2(mtc0_srsconf1, void, env, tl) -DEF_HELPER_2(mtc0_srsconf2, void, env, tl) -DEF_HELPER_2(mtc0_srsconf3, void, env, tl) -DEF_HELPER_2(mtc0_srsconf4, void, env, tl) -DEF_HELPER_2(mtc0_hwrena, void, env, tl) -DEF_HELPER_2(mtc0_pwctl, void, env, tl) -DEF_HELPER_2(mtc0_count, void, env, tl) -DEF_HELPER_2(mtc0_saari, void, env, tl) -DEF_HELPER_2(mtc0_saar, void, env, tl) -DEF_HELPER_2(mthc0_saar, void, env, tl) -DEF_HELPER_2(mtc0_entryhi, void, env, tl) -DEF_HELPER_2(mttc0_entryhi, void, env, tl) -DEF_HELPER_2(mtc0_compare, void, env, tl) -DEF_HELPER_2(mtc0_status, void, env, tl) -DEF_HELPER_2(mttc0_status, void, env, tl) -DEF_HELPER_2(mtc0_intctl, void, env, tl) -DEF_HELPER_2(mtc0_srsctl, void, env, tl) -DEF_HELPER_2(mtc0_cause, void, env, tl) -DEF_HELPER_2(mttc0_cause, void, env, tl) -DEF_HELPER_2(mtc0_ebase, void, env, tl) -DEF_HELPER_2(mttc0_ebase, void, env, tl) -DEF_HELPER_2(mtc0_config0, void, env, tl) -DEF_HELPER_2(mtc0_config2, void, env, tl) -DEF_HELPER_2(mtc0_config3, void, env, tl) -DEF_HELPER_2(mtc0_config4, void, env, tl) -DEF_HELPER_2(mtc0_config5, void, env, tl) -DEF_HELPER_2(mtc0_lladdr, void, env, tl) -DEF_HELPER_2(mtc0_maar, void, env, tl) -DEF_HELPER_2(mthc0_maar, void, env, tl) -DEF_HELPER_2(mtc0_maari, void, env, tl) -DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) -DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) -DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) -DEF_HELPER_2(mtc0_xcontext, void, env, tl) -DEF_HELPER_2(mtc0_framemask, void, env, tl) -DEF_HELPER_2(mtc0_debug, void, env, tl) -DEF_HELPER_2(mttc0_debug, void, env, tl) -DEF_HELPER_2(mtc0_performance0, void, env, tl) -DEF_HELPER_2(mtc0_errctl, void, env, tl) -DEF_HELPER_2(mtc0_taglo, void, env, tl) -DEF_HELPER_2(mtc0_datalo, void, env, tl) -DEF_HELPER_2(mtc0_taghi, void, env, tl) -DEF_HELPER_2(mtc0_datahi, void, env, tl) - -#if defined(TARGET_MIPS64) -DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) -DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) -#endif - -/* MIPS MT functions */ -DEF_HELPER_2(mftgpr, tl, env, i32) -DEF_HELPER_2(mftlo, tl, env, i32) -DEF_HELPER_2(mfthi, tl, env, i32) -DEF_HELPER_2(mftacx, tl, env, i32) -DEF_HELPER_1(mftdsp, tl, env) -DEF_HELPER_3(mttgpr, void, env, tl, i32) -DEF_HELPER_3(mttlo, void, env, tl, i32) -DEF_HELPER_3(mtthi, void, env, tl, i32) -DEF_HELPER_3(mttacx, void, env, tl, i32) -DEF_HELPER_2(mttdsp, void, env, tl) -DEF_HELPER_0(dmt, tl) -DEF_HELPER_0(emt, tl) -DEF_HELPER_1(dvpe, tl, env) -DEF_HELPER_1(evpe, tl, env) - -/* R6 Multi-threading */ -DEF_HELPER_1(dvp, tl, env) -DEF_HELPER_1(evp, tl, env) -#endif /* !CONFIG_USER_ONLY */ - /* microMIPS functions */ DEF_HELPER_4(lwm, void, env, tl, tl, i32) DEF_HELPER_4(swm, void, env, tl, tl, i32) @@ -364,21 +202,6 @@ FOP_PROTO(sune) FOP_PROTO(sne) #undef FOP_PROTO -/* Special functions */ -#ifndef CONFIG_USER_ONLY -DEF_HELPER_1(tlbwi, void, env) -DEF_HELPER_1(tlbwr, void, env) -DEF_HELPER_1(tlbp, void, env) -DEF_HELPER_1(tlbr, void, env) -DEF_HELPER_1(tlbinv, void, env) -DEF_HELPER_1(tlbinvf, void, env) -DEF_HELPER_1(di, tl, env) -DEF_HELPER_1(ei, tl, env) -DEF_HELPER_1(eret, void, env) -DEF_HELPER_1(eretnc, void, env) -DEF_HELPER_1(deret, void, env) -DEF_HELPER_3(ginvt, void, env, tl, i32) -#endif /* !CONFIG_USER_ONLY */ DEF_HELPER_1(rdhwr_cpunum, tl, env) DEF_HELPER_1(rdhwr_synci_step, tl, env) DEF_HELPER_1(rdhwr_cc, tl, env) @@ -781,6 +604,8 @@ DEF_HELPER_FLAGS_3(dmthlip, 0, void, tl, tl, env) DEF_HELPER_FLAGS_3(wrdsp, 0, void, tl, tl, env) DEF_HELPER_FLAGS_2(rddsp, 0, tl, tl, env) -DEF_HELPER_3(cache, void, env, tl, i32) +#ifndef CONFIG_USER_ONLY +#include "tcg/sysemu_helper.h.inc" +#endif /* !CONFIG_USER_ONLY */ -#include "msa_helper.h.inc" +#include "tcg/msa_helper.h.inc" diff --git a/target/mips/internal.h b/target/mips/internal.h index 99264b8bf6..18d5da64a5 100644 --- a/target/mips/internal.h +++ b/target/mips/internal.h @@ -9,6 +9,9 @@ #define MIPS_INTERNAL_H #include "exec/memattrs.h" +#ifdef CONFIG_TCG +#include "tcg/tcg-internal.h" +#endif /* * MMU types, the first four entries have the same layout as the @@ -71,21 +74,41 @@ struct mips_def_t { int32_t SAARP; }; +extern const char regnames[32][4]; +extern const char fregnames[32][4]; + extern const struct mips_def_t mips_defs[]; extern const int mips_defs_number; -void mips_cpu_do_interrupt(CPUState *cpu); -bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); -void mips_cpu_dump_state(CPUState *cpu, FILE *f, int flags); -hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int mips_cpu_gdb_read_register(CPUState *cpu, GByteArray *buf, int reg); int mips_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); -void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr); + +#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) +#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) +#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) +#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) +#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) + +#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) +#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) #if !defined(CONFIG_USER_ONLY) +enum { + TLBRET_XI = -6, + TLBRET_RI = -5, + TLBRET_DIRTY = -4, + TLBRET_INVALID = -3, + TLBRET_NOMATCH = -2, + TLBRET_BADADDR = -1, + TLBRET_MATCH = 0 +}; + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx); +hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); + typedef struct r4k_tlb_t r4k_tlb_t; struct r4k_tlb_t { target_ulong VPN; @@ -125,35 +148,15 @@ struct CPUMIPSTLBContext { } mmu; }; -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type); -void r4k_helper_tlbwi(CPUMIPSState *env); -void r4k_helper_tlbwr(CPUMIPSState *env); -void r4k_helper_tlbp(CPUMIPSState *env); -void r4k_helper_tlbr(CPUMIPSState *env); -void r4k_helper_tlbinv(CPUMIPSState *env); -void r4k_helper_tlbinvf(CPUMIPSState *env); -void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); -uint32_t cpu_mips_get_random(CPUMIPSState *env); - -void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr); -hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type); -#endif - -#define cpu_signal_handler cpu_mips_signal_handler +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); -#ifndef CONFIG_USER_ONLY extern const VMStateDescription vmstate_mips_cpu; -#endif + +#endif /* !CONFIG_USER_ONLY */ + +#define cpu_signal_handler cpu_mips_signal_handler static inline bool cpu_mips_hw_interrupts_enabled(CPUMIPSState *env) { @@ -197,8 +200,6 @@ static inline bool cpu_mips_hw_interrupts_pending(CPUMIPSState *env) return r; } -void mips_tcg_init(void); - void msa_reset(CPUMIPSState *env); /* cp0_timer.c */ @@ -208,14 +209,15 @@ void cpu_mips_store_compare(CPUMIPSState *env, uint32_t value); void cpu_mips_start_count(CPUMIPSState *env); void cpu_mips_stop_count(CPUMIPSState *env); -/* helper.c */ -void mmu_init(CPUMIPSState *env, const mips_def_t *def); -bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, - MMUAccessType access_type, int mmu_idx, - bool probe, uintptr_t retaddr); - -/* op_helper.c */ -void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); +static inline void mips_env_set_pc(CPUMIPSState *env, target_ulong value) +{ + env->active_tc.PC = value & ~(target_ulong)1; + if (value & 1) { + env->hflags |= MIPS_HFLAG_M16; + } else { + env->hflags &= ~(MIPS_HFLAG_M16); + } +} static inline void restore_pamask(CPUMIPSState *env) { @@ -397,21 +399,4 @@ static inline void compute_hflags(CPUMIPSState *env) } } -void cpu_mips_tlb_flush(CPUMIPSState *env); -void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc); -void cpu_mips_store_status(CPUMIPSState *env, target_ulong val); -void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val); - -const char *mips_exception_name(int32_t exception); - -void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, - int error_code, uintptr_t pc); - -static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, - uint32_t exception, - uintptr_t pc) -{ - do_raise_exception_err(env, exception, 0, pc); -} - #endif diff --git a/target/mips/meson.build b/target/mips/meson.build index 3b131c4a7f..2407a05d4c 100644 --- a/target/mips/meson.build +++ b/target/mips/meson.build @@ -1,52 +1,23 @@ -gen = [ - decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'), - decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'), - decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'), - decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'), - decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), -] - +mips_user_ss = ss.source_set() +mips_softmmu_ss = ss.source_set() mips_ss = ss.source_set() mips_ss.add(files( 'cpu.c', + 'fpu.c', 'gdbstub.c', -)) -mips_tcg_ss = ss.source_set() -mips_tcg_ss.add(gen) -mips_tcg_ss.add(files( - 'dsp_helper.c', - 'fpu_helper.c', - 'lmmi_helper.c', - 'msa_helper.c', - 'msa_translate.c', - 'op_helper.c', - 'rel6_translate.c', - 'tlb_helper.c', - 'translate.c', - 'translate_addr_const.c', - 'txx9_translate.c', -)) -mips_ss.add(when: ['CONFIG_TCG', 'TARGET_MIPS64'], if_true: files( - 'tx79_translate.c', -)) -mips_tcg_ss.add(when: 'TARGET_MIPS64', if_false: files( - 'mxu_translate.c', + 'msa.c', )) -mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) +if have_system + subdir('sysemu') +endif -mips_softmmu_ss = ss.source_set() -mips_softmmu_ss.add(files( - 'addr.c', - 'cp0_timer.c', - 'machine.c', -)) -mips_softmmu_ss.add(when: 'CONFIG_TCG', if_true: files( - 'cp0_helper.c', - 'mips-semi.c', -)) +if 'CONFIG_TCG' in config_all + subdir('tcg') +endif -mips_ss.add_all(when: 'CONFIG_TCG', if_true: [mips_tcg_ss]) +mips_ss.add(when: 'CONFIG_KVM', if_true: files('kvm.c')) target_arch += {'mips': mips_ss} target_softmmu_arch += {'mips': mips_softmmu_ss} +target_user_arch += {'mips': mips_user_ss} diff --git a/target/mips/msa.c b/target/mips/msa.c new file mode 100644 index 0000000000..61f1a9a593 --- /dev/null +++ b/target/mips/msa.c @@ -0,0 +1,60 @@ +/* + * MIPS SIMD Architecture Module Instruction emulation helpers for QEMU. + * + * Copyright (c) 2014 Imagination Technologies + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "fpu/softfloat.h" +#include "fpu_helper.h" + +void msa_reset(CPUMIPSState *env) +{ + if (!ase_msa_available(env)) { + return; + } + +#ifdef CONFIG_USER_ONLY + /* MSA access enabled */ + env->CP0_Config5 |= 1 << CP0C5_MSAEn; + env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); +#endif + + /* + * MSA CSR: + * - non-signaling floating point exception mode off (NX bit is 0) + * - Cause, Enables, and Flags are all 0 + * - round to nearest / ties to even (RM bits are 0) + */ + env->active_tc.msacsr = 0; + + restore_msa_fp_status(env); + + /* tininess detected after rounding.*/ + set_float_detect_tininess(float_tininess_after_rounding, + &env->active_tc.msa_fp_status); + + /* clear float_status exception flags */ + set_float_exception_flags(0, &env->active_tc.msa_fp_status); + + /* clear float_status nan mode */ + set_default_nan_mode(0, &env->active_tc.msa_fp_status); + + /* set proper signanling bit meaning ("1" means "quiet") */ + set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); +} diff --git a/target/mips/op_helper.c b/target/mips/op_helper.c deleted file mode 100644 index b80e8f7540..0000000000 --- a/target/mips/op_helper.c +++ /dev/null @@ -1,1210 +0,0 @@ -/* - * MIPS emulation helpers for qemu. - * - * Copyright (c) 2004-2005 Jocelyn Mayer - * - * This library is free software; you can redistribute it and/or - * modify it under the terms of the GNU Lesser General Public - * License as published by the Free Software Foundation; either - * version 2.1 of the License, or (at your option) any later version. - * - * This library is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU - * Lesser General Public License for more details. - * - * You should have received a copy of the GNU Lesser General Public - * License along with this library; if not, see <http://www.gnu.org/licenses/>. - * - */ - -#include "qemu/osdep.h" -#include "cpu.h" -#include "internal.h" -#include "exec/helper-proto.h" -#include "exec/exec-all.h" -#include "exec/memop.h" -#include "fpu_helper.h" - -/*****************************************************************************/ -/* Exceptions processing helpers */ - -void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, - int error_code) -{ - do_raise_exception_err(env, exception, error_code, 0); -} - -void helper_raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, GETPC()); -} - -void helper_raise_exception_debug(CPUMIPSState *env) -{ - do_raise_exception(env, EXCP_DEBUG, 0); -} - -static void raise_exception(CPUMIPSState *env, uint32_t exception) -{ - do_raise_exception(env, exception, 0); -} - -/* 64 bits arithmetic for 32 bits hosts */ -static inline uint64_t get_HILO(CPUMIPSState *env) -{ - return ((uint64_t)(env->active_tc.HI[0]) << 32) | - (uint32_t)env->active_tc.LO[0]; -} - -static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) -{ - env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); - return env->active_tc.HI[0] = (int32_t)(HILO >> 32); -} - -static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) -{ - target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); - env->active_tc.HI[0] = (int32_t)(HILO >> 32); - return tmp; -} - -/* Multiplication variants of the vr54xx. */ -target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2)); -} - -target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (uint64_t)get_HILO(env) + - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)get_HILO(env) + - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HI_LOT0(env, (uint64_t)get_HILO(env) - - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)get_HILO(env) - - (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); -} - -target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - -target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * - (int64_t)(int32_t)arg2); -} - -target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, - target_ulong arg2) -{ - return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * - (uint64_t)(uint32_t)arg2); -} - -static inline target_ulong bitswap(target_ulong v) -{ - v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) | - ((v & (target_ulong)0x5555555555555555ULL) << 1); - v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) | - ((v & (target_ulong)0x3333333333333333ULL) << 2); - v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) | - ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4); - return v; -} - -#ifdef TARGET_MIPS64 -target_ulong helper_dbitswap(target_ulong rt) -{ - return bitswap(rt); -} -#endif - -target_ulong helper_bitswap(target_ulong rt) -{ - return (int32_t)bitswap(rt); -} - -target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx, - uint32_t stripe) -{ - int i; - uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff); - uint64_t tmp1 = tmp0; - for (i = 0; i <= 46; i++) { - int s; - if (i & 0x8) { - s = shift; - } else { - s = shiftx; - } - - if (stripe != 0 && !(i & 0x4)) { - s = ~s; - } - if (s & 0x10) { - if (tmp0 & (1LL << (i + 16))) { - tmp1 |= 1LL << i; - } else { - tmp1 &= ~(1LL << i); - } - } - } - - uint64_t tmp2 = tmp1; - for (i = 0; i <= 38; i++) { - int s; - if (i & 0x4) { - s = shift; - } else { - s = shiftx; - } - - if (s & 0x8) { - if (tmp1 & (1LL << (i + 8))) { - tmp2 |= 1LL << i; - } else { - tmp2 &= ~(1LL << i); - } - } - } - - uint64_t tmp3 = tmp2; - for (i = 0; i <= 34; i++) { - int s; - if (i & 0x2) { - s = shift; - } else { - s = shiftx; - } - if (s & 0x4) { - if (tmp2 & (1LL << (i + 4))) { - tmp3 |= 1LL << i; - } else { - tmp3 &= ~(1LL << i); - } - } - } - - uint64_t tmp4 = tmp3; - for (i = 0; i <= 32; i++) { - int s; - if (i & 0x1) { - s = shift; - } else { - s = shiftx; - } - if (s & 0x2) { - if (tmp3 & (1LL << (i + 2))) { - tmp4 |= 1LL << i; - } else { - tmp4 &= ~(1LL << i); - } - } - } - - uint64_t tmp5 = tmp4; - for (i = 0; i <= 31; i++) { - int s; - s = shift; - if (s & 0x1) { - if (tmp4 & (1LL << (i + 1))) { - tmp5 |= 1LL << i; - } else { - tmp5 &= ~(1LL << i); - } - } - } - - return (int64_t)(int32_t)(uint32_t)tmp5; -} - -#ifndef CONFIG_USER_ONLY - -static inline hwaddr do_translate_address(CPUMIPSState *env, - target_ulong address, - MMUAccessType access_type, - uintptr_t retaddr) -{ - hwaddr paddr; - CPUState *cs = env_cpu(env); - - paddr = cpu_mips_translate_address(env, address, access_type); - - if (paddr == -1LL) { - cpu_loop_exit_restore(cs, retaddr); - } else { - return paddr; - } -} - -#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \ -target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ -{ \ - if (arg & almask) { \ - if (!(env->hflags & MIPS_HFLAG_DM)) { \ - env->CP0_BadVAddr = arg; \ - } \ - do_raise_exception(env, EXCP_AdEL, GETPC()); \ - } \ - env->CP0_LLAddr = do_translate_address(env, arg, MMU_DATA_LOAD, GETPC()); \ - env->lladdr = arg; \ - env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \ - return env->llval; \ -} -HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) -#ifdef TARGET_MIPS64 -HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) -#endif -#undef HELPER_LD_ATOMIC -#endif - -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK(v) ((v) & 3) -#define GET_OFFSET(addr, offset) (addr + (offset)) -#else -#define GET_LMASK(v) (((v) & 3) ^ 3) -#define GET_OFFSET(addr, offset) (addr - (offset)) -#endif - -void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); - - if (GET_LMASK(arg2) <= 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) <= 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) == 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK(arg2) >= 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) >= 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK(arg2) == 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } -} - -#if defined(TARGET_MIPS64) -/* - * "half" load and stores. We must do the memory access inline, - * or fault handling won't work. - */ -#ifdef TARGET_WORDS_BIGENDIAN -#define GET_LMASK64(v) ((v) & 7) -#else -#define GET_LMASK64(v) (((v) & 7) ^ 7) -#endif - -void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); - - if (GET_LMASK64(arg2) <= 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <= 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <= 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <= 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <= 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <= 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) <= 0) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, - mem_idx, GETPC()); - } -} - -void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, - int mem_idx) -{ - cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); - - if (GET_LMASK64(arg2) >= 1) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >= 2) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >= 3) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >= 4) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >= 5) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) >= 6) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), - mem_idx, GETPC()); - } - - if (GET_LMASK64(arg2) == 7) { - cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), - mem_idx, GETPC()); - } -} -#endif /* TARGET_MIPS64 */ - -static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; - -void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist = reglist & 0xf; - target_ulong do_r31 = reglist & 0x10; - - if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i = 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] = - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); - addr += 4; - } - } - - if (do_r31) { - env->active_tc.gpr[31] = - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist = reglist & 0xf; - target_ulong do_r31 = reglist & 0x10; - - if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i = 0; i < base_reglist; i++) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]], - mem_idx, GETPC()); - addr += 4; - } - } - - if (do_r31) { - cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); - } -} - -#if defined(TARGET_MIPS64) -void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist = reglist & 0xf; - target_ulong do_r31 = reglist & 0x10; - - if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i = 0; i < base_reglist; i++) { - env->active_tc.gpr[multiple_regs[i]] = - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - addr += 8; - } - } - - if (do_r31) { - env->active_tc.gpr[31] = - cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); - } -} - -void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, - uint32_t mem_idx) -{ - target_ulong base_reglist = reglist & 0xf; - target_ulong do_r31 = reglist & 0x10; - - if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { - target_ulong i; - - for (i = 0; i < base_reglist; i++) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]], - mem_idx, GETPC()); - addr += 8; - } - } - - if (do_r31) { - cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); - } -} -#endif - - -void helper_fork(target_ulong arg1, target_ulong arg2) -{ - /* - * arg1 = rt, arg2 = rs - * TODO: store to TC register - */ -} - -target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) -{ - target_long arg1 = arg; - - if (arg1 < 0) { - /* No scheduling policy implemented. */ - if (arg1 != -2) { - if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && - env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); - env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; - do_raise_exception(env, EXCP_THREAD, GETPC()); - } - } - } else if (arg1 == 0) { - if (0) { - /* TODO: TC underflow */ - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); - do_raise_exception(env, EXCP_THREAD, GETPC()); - } else { - /* TODO: Deallocate TC */ - } - } else if (arg1 > 0) { - /* Yield qualifier inputs not implemented. */ - env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); - env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; - do_raise_exception(env, EXCP_THREAD, GETPC()); - } - return env->CP0_YQMask; -} - -#ifndef CONFIG_USER_ONLY -/* TLB management */ -static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) -{ - /* Discard entries from env->tlb[first] onwards. */ - while (env->tlb->tlb_in_use > first) { - r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); - } -} - -static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) -{ -#if defined(TARGET_MIPS64) - return extract64(entrylo, 6, 54); -#else - return extract64(entrylo, 6, 24) | /* PFN */ - (extract64(entrylo, 32, 32) << 24); /* PFNX */ -#endif -} - -static void r4k_fill_tlb(CPUMIPSState *env, int idx) -{ - r4k_tlb_t *tlb; - uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); - - /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ - tlb = &env->tlb->mmu.r4k.tlb[idx]; - if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { - tlb->EHINV = 1; - return; - } - tlb->EHINV = 0; - tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - tlb->VPN &= env->SEGMask; -#endif - tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - tlb->MMID = env->CP0_MemoryMapID; - tlb->PageMask = env->CP0_PageMask; - tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; - tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; - tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; - tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; - tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; - tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12; - tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; - tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; - tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; - tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; - tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; - tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12; -} - -void r4k_helper_tlbinv(CPUMIPSState *env) -{ - bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID = env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID = mi ? MMID : (uint32_t) ASID; - for (idx = 0; idx < env->tlb->nb_tlb; idx++) { - tlb = &env->tlb->mmu.r4k.tlb[idx]; - tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; - if (!tlb->G && tlb_mmid == MMID) { - tlb->EHINV = 1; - } - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbinvf(CPUMIPSState *env) -{ - int idx; - - for (idx = 0; idx < env->tlb->nb_tlb; idx++) { - env->tlb->mmu.r4k.tlb[idx].EHINV = 1; - } - cpu_mips_tlb_flush(env); -} - -void r4k_helper_tlbwi(CPUMIPSState *env) -{ - bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); - target_ulong VPN; - uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID = env->CP0_MemoryMapID; - uint32_t tlb_mmid; - bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; - r4k_tlb_t *tlb; - int idx; - - MMID = mi ? MMID : (uint32_t) ASID; - - idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb = &env->tlb->mmu.r4k.tlb[idx]; - VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); -#if defined(TARGET_MIPS64) - VPN &= env->SEGMask; -#endif - EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0; - G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; - V0 = (env->CP0_EntryLo0 & 2) != 0; - D0 = (env->CP0_EntryLo0 & 4) != 0; - XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; - RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; - V1 = (env->CP0_EntryLo1 & 2) != 0; - D1 = (env->CP0_EntryLo1 & 4) != 0; - XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; - RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; - - tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* - * Discard cached TLB entries, unless tlbwi is just upgrading access - * permissions on the current entry. - */ - if (tlb->VPN != VPN || tlb_mmid != MMID || tlb->G != G || - (!tlb->EHINV && EHINV) || - (tlb->V0 && !V0) || (tlb->D0 && !D0) || - (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || - (tlb->V1 && !V1) || (tlb->D1 && !D1) || - (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - } - - r4k_invalidate_tlb(env, idx, 0); - r4k_fill_tlb(env, idx); -} - -void r4k_helper_tlbwr(CPUMIPSState *env) -{ - int r = cpu_mips_get_random(env); - - r4k_invalidate_tlb(env, r, 1); - r4k_fill_tlb(env, r); -} - -void r4k_helper_tlbp(CPUMIPSState *env) -{ - bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); - r4k_tlb_t *tlb; - target_ulong mask; - target_ulong tag; - target_ulong VPN; - uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID = env->CP0_MemoryMapID; - uint32_t tlb_mmid; - int i; - - MMID = mi ? MMID : (uint32_t) ASID; - for (i = 0; i < env->tlb->nb_tlb; i++) { - tlb = &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag = env->CP0_EntryHi & ~mask; - VPN = tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &= env->SEGMask; -#endif - tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) { - /* TLB match */ - env->CP0_Index = i; - break; - } - } - if (i == env->tlb->nb_tlb) { - /* No match. Discard any shadow entries, if any of them match. */ - for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { - tlb = &env->tlb->mmu.r4k.tlb[i]; - /* 1k pages are not supported. */ - mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); - tag = env->CP0_EntryHi & ~mask; - VPN = tlb->VPN & ~mask; -#if defined(TARGET_MIPS64) - tag &= env->SEGMask; -#endif - tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* Check ASID/MMID, virtual page number & size */ - if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag) { - r4k_mips_tlb_flush_extra(env, i); - break; - } - } - - env->CP0_Index |= 0x80000000; - } -} - -static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) -{ -#if defined(TARGET_MIPS64) - return tlb_pfn << 6; -#else - return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ - (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ -#endif -} - -void r4k_helper_tlbr(CPUMIPSState *env) -{ - bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); - uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; - uint32_t MMID = env->CP0_MemoryMapID; - uint32_t tlb_mmid; - r4k_tlb_t *tlb; - int idx; - - MMID = mi ? MMID : (uint32_t) ASID; - idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; - tlb = &env->tlb->mmu.r4k.tlb[idx]; - - tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; - /* If this will change the current ASID/MMID, flush qemu's TLB. */ - if (MMID != tlb_mmid) { - cpu_mips_tlb_flush(env); - } - - r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); - - if (tlb->EHINV) { - env->CP0_EntryHi = 1 << CP0EnHi_EHINV; - env->CP0_PageMask = 0; - env->CP0_EntryLo0 = 0; - env->CP0_EntryLo1 = 0; - } else { - env->CP0_EntryHi = mi ? tlb->VPN : tlb->VPN | tlb->ASID; - env->CP0_MemoryMapID = tlb->MMID; - env->CP0_PageMask = tlb->PageMask; - env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | - ((uint64_t)tlb->RI0 << CP0EnLo_RI) | - ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) | - get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); - env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | - ((uint64_t)tlb->RI1 << CP0EnLo_RI) | - ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) | - get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); - } -} - -void helper_tlbwi(CPUMIPSState *env) -{ - env->tlb->helper_tlbwi(env); -} - -void helper_tlbwr(CPUMIPSState *env) -{ - env->tlb->helper_tlbwr(env); -} - -void helper_tlbp(CPUMIPSState *env) -{ - env->tlb->helper_tlbp(env); -} - -void helper_tlbr(CPUMIPSState *env) -{ - env->tlb->helper_tlbr(env); -} - -void helper_tlbinv(CPUMIPSState *env) -{ - env->tlb->helper_tlbinv(env); -} - -void helper_tlbinvf(CPUMIPSState *env) -{ - env->tlb->helper_tlbinvf(env); -} - -static void global_invalidate_tlb(CPUMIPSState *env, - uint32_t invMsgVPN2, - uint8_t invMsgR, - uint32_t invMsgMMid, - bool invAll, - bool invVAMMid, - bool invMMid, - bool invVA) -{ - - int idx; - r4k_tlb_t *tlb; - bool VAMatch; - bool MMidMatch; - - for (idx = 0; idx < env->tlb->nb_tlb; idx++) { - tlb = &env->tlb->mmu.r4k.tlb[idx]; - VAMatch = - (((tlb->VPN & ~tlb->PageMask) == (invMsgVPN2 & ~tlb->PageMask)) -#ifdef TARGET_MIPS64 - && - (extract64(env->CP0_EntryHi, 62, 2) == invMsgR) -#endif - ); - MMidMatch = tlb->MMID == invMsgMMid; - if ((invAll && (idx > env->CP0_Wired)) || - (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || - (VAMatch && invVA) || - (MMidMatch && !(tlb->G) && invMMid)) { - tlb->EHINV = 1; - } - } - cpu_mips_tlb_flush(env); -} - -void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) -{ - bool invAll = type == 0; - bool invVA = type == 1; - bool invMMid = type == 2; - bool invVAMMid = type == 3; - uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1); - uint8_t invMsgR = 0; - uint32_t invMsgMMid = env->CP0_MemoryMapID; - CPUState *other_cs = first_cpu; - -#ifdef TARGET_MIPS64 - invMsgR = extract64(arg, 62, 2); -#endif - - CPU_FOREACH(other_cs) { - MIPSCPU *other_cpu = MIPS_CPU(other_cs); - global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid, - invAll, invVAMMid, invMMid, invVA); - } -} - -/* Specials */ -target_ulong helper_di(CPUMIPSState *env) -{ - target_ulong t0 = env->CP0_Status; - - env->CP0_Status = t0 & ~(1 << CP0St_IE); - return t0; -} - -target_ulong helper_ei(CPUMIPSState *env) -{ - target_ulong t0 = env->CP0_Status; - - env->CP0_Status = t0 | (1 << CP0St_IE); - return t0; -} - -static void debug_pre_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - qemu_log("\n"); - } -} - -static void debug_post_eret(CPUMIPSState *env) -{ - if (qemu_loglevel_mask(CPU_LOG_EXEC)) { - qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, - env->active_tc.PC, env->CP0_EPC); - if (env->CP0_Status & (1 << CP0St_ERL)) { - qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); - } - if (env->hflags & MIPS_HFLAG_DM) { - qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); - } - switch (cpu_mmu_index(env, false)) { - case 3: - qemu_log(", ERL\n"); - break; - case MIPS_HFLAG_UM: - qemu_log(", UM\n"); - break; - case MIPS_HFLAG_SM: - qemu_log(", SM\n"); - break; - case MIPS_HFLAG_KM: - qemu_log("\n"); - break; - default: - cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); - break; - } - } -} - -static void set_pc(CPUMIPSState *env, target_ulong error_pc) -{ - env->active_tc.PC = error_pc & ~(target_ulong)1; - if (error_pc & 1) { - env->hflags |= MIPS_HFLAG_M16; - } else { - env->hflags &= ~(MIPS_HFLAG_M16); - } -} - -static inline void exception_return(CPUMIPSState *env) -{ - debug_pre_eret(env); - if (env->CP0_Status & (1 << CP0St_ERL)) { - set_pc(env, env->CP0_ErrorEPC); - env->CP0_Status &= ~(1 << CP0St_ERL); - } else { - set_pc(env, env->CP0_EPC); - env->CP0_Status &= ~(1 << CP0St_EXL); - } - compute_hflags(env); - debug_post_eret(env); -} - -void helper_eret(CPUMIPSState *env) -{ - exception_return(env); - env->CP0_LLAddr = 1; - env->lladdr = 1; -} - -void helper_eretnc(CPUMIPSState *env) -{ - exception_return(env); -} - -void helper_deret(CPUMIPSState *env) -{ - debug_pre_eret(env); - - env->hflags &= ~MIPS_HFLAG_DM; - compute_hflags(env); - - set_pc(env, env->CP0_DEPC); - - debug_post_eret(env); -} -#endif /* !CONFIG_USER_ONLY */ - -static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) -{ - if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) { - return; - } - do_raise_exception(env, EXCP_RI, pc); -} - -target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) -{ - check_hwrena(env, 0, GETPC()); - return env->CP0_EBase & 0x3ff; -} - -target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) -{ - check_hwrena(env, 1, GETPC()); - return env->SYNCI_Step; -} - -target_ulong helper_rdhwr_cc(CPUMIPSState *env) -{ - check_hwrena(env, 2, GETPC()); -#ifdef CONFIG_USER_ONLY - return env->CP0_Count; -#else - return (int32_t)cpu_mips_get_count(env); -#endif -} - -target_ulong helper_rdhwr_ccres(CPUMIPSState *env) -{ - check_hwrena(env, 3, GETPC()); - return env->CCRes; -} - -target_ulong helper_rdhwr_performance(CPUMIPSState *env) -{ - check_hwrena(env, 4, GETPC()); - return env->CP0_Performance0; -} - -target_ulong helper_rdhwr_xnp(CPUMIPSState *env) -{ - check_hwrena(env, 5, GETPC()); - return (env->CP0_Config5 >> CP0C5_XNP) & 1; -} - -void helper_pmon(CPUMIPSState *env, int function) -{ - function /= 2; - switch (function) { - case 2: /* TODO: char inbyte(int waitflag); */ - if (env->active_tc.gpr[4] == 0) { - env->active_tc.gpr[2] = -1; - } - /* Fall through */ - case 11: /* TODO: char inbyte (void); */ - env->active_tc.gpr[2] = -1; - break; - case 3: - case 12: - printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); - break; - case 17: - break; - case 158: - { - unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4]; - printf("%s", fmt); - } - break; - } -} - -void helper_wait(CPUMIPSState *env) -{ - CPUState *cs = env_cpu(env); - - cs->halted = 1; - cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); - /* - * Last instruction in the block, PC was updated before - * - no need to recover PC and icount. - */ - raise_exception(env, EXCP_HLT); -} - -#if !defined(CONFIG_USER_ONLY) - -void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, - MMUAccessType access_type, - int mmu_idx, uintptr_t retaddr) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - int error_code = 0; - int excp; - - if (!(env->hflags & MIPS_HFLAG_DM)) { - env->CP0_BadVAddr = addr; - } - - if (access_type == MMU_DATA_STORE) { - excp = EXCP_AdES; - } else { - excp = EXCP_AdEL; - if (access_type == MMU_INST_FETCH) { - error_code |= EXCP_INST_NOTAVAIL; - } - } - - do_raise_exception_err(env, excp, error_code, retaddr); -} - -void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, - vaddr addr, unsigned size, - MMUAccessType access_type, - int mmu_idx, MemTxAttrs attrs, - MemTxResult response, uintptr_t retaddr) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - - if (access_type == MMU_INST_FETCH) { - do_raise_exception(env, EXCP_IBE, retaddr); - } else { - do_raise_exception(env, EXCP_DBE, retaddr); - } -} -#endif /* !CONFIG_USER_ONLY */ - -void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) -{ -#ifndef CONFIG_USER_ONLY - static const char *const type_name[] = { - "Primary Instruction", - "Primary Data or Unified Primary", - "Tertiary", - "Secondary" - }; - uint32_t cache_type = extract32(op, 0, 2); - uint32_t cache_operation = extract32(op, 2, 3); - target_ulong index = addr & 0x1fffffff; - - switch (cache_operation) { - case 0b010: /* Index Store Tag */ - memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b001: /* Index Load Tag */ - memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, - MO_64, MEMTXATTRS_UNSPECIFIED); - break; - case 0b000: /* Index Invalidate */ - case 0b100: /* Hit Invalidate */ - case 0b110: /* Hit Writeback */ - /* no-op */ - break; - default: - qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", - cache_operation, type_name[cache_type]); - break; - } -#endif -} diff --git a/target/mips/addr.c b/target/mips/sysemu/addr.c index 86f1c129c9..86f1c129c9 100644 --- a/target/mips/addr.c +++ b/target/mips/sysemu/addr.c diff --git a/target/mips/sysemu/cp0.c b/target/mips/sysemu/cp0.c new file mode 100644 index 0000000000..bae37f515b --- /dev/null +++ b/target/mips/sysemu/cp0.c @@ -0,0 +1,123 @@ +/* + * QEMU MIPS CPU + * + * Copyright (c) 2012 SUSE LINUX Products GmbH + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see + * <http://www.gnu.org/licenses/lgpl-2.1.html> + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/exec-all.h" + +/* Called for updates to CP0_Status. */ +void sync_c0_status(CPUMIPSState *env, CPUMIPSState *cpu, int tc) +{ + int32_t tcstatus, *tcst; + uint32_t v = cpu->CP0_Status; + uint32_t cu, mx, asid, ksu; + uint32_t mask = ((1 << CP0TCSt_TCU3) + | (1 << CP0TCSt_TCU2) + | (1 << CP0TCSt_TCU1) + | (1 << CP0TCSt_TCU0) + | (1 << CP0TCSt_TMX) + | (3 << CP0TCSt_TKSU) + | (0xff << CP0TCSt_TASID)); + + cu = (v >> CP0St_CU0) & 0xf; + mx = (v >> CP0St_MX) & 0x1; + ksu = (v >> CP0St_KSU) & 0x3; + asid = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + + tcstatus = cu << CP0TCSt_TCU0; + tcstatus |= mx << CP0TCSt_TMX; + tcstatus |= ksu << CP0TCSt_TKSU; + tcstatus |= asid; + + if (tc == cpu->current_tc) { + tcst = &cpu->active_tc.CP0_TCStatus; + } else { + tcst = &cpu->tcs[tc].CP0_TCStatus; + } + + *tcst &= ~mask; + *tcst |= tcstatus; + compute_hflags(cpu); +} + +void cpu_mips_store_status(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask = env->CP0_Status_rw_bitmask; + target_ulong old = env->CP0_Status; + + if (env->insn_flags & ISA_MIPS_R6) { + bool has_supervisor = extract32(mask, CP0St_KSU, 2) == 0x3; +#if defined(TARGET_MIPS64) + uint32_t ksux = (1 << CP0St_KX) & val; + ksux |= (ksux >> 1) & val; /* KX = 0 forces SX to be 0 */ + ksux |= (ksux >> 1) & val; /* SX = 0 forces UX to be 0 */ + val = (val & ~(7 << CP0St_UX)) | ksux; +#endif + if (has_supervisor && extract32(val, CP0St_KSU, 2) == 0x3) { + mask &= ~(3 << CP0St_KSU); + } + mask &= ~(((1 << CP0St_SR) | (1 << CP0St_NMI)) & val); + } + + env->CP0_Status = (old & ~mask) | (val & mask); +#if defined(TARGET_MIPS64) + if ((env->CP0_Status ^ old) & (old & (7 << CP0St_UX))) { + /* Access to at least one of the 64-bit segments has been disabled */ + tlb_flush(env_cpu(env)); + } +#endif + if (ase_mt_available(env)) { + sync_c0_status(env, env, env->current_tc); + } else { + compute_hflags(env); + } +} + +void cpu_mips_store_cause(CPUMIPSState *env, target_ulong val) +{ + uint32_t mask = 0x00C00300; + uint32_t old = env->CP0_Cause; + int i; + + if (env->insn_flags & ISA_MIPS_R2) { + mask |= 1 << CP0Ca_DC; + } + if (env->insn_flags & ISA_MIPS_R6) { + mask &= ~((1 << CP0Ca_WP) & val); + } + + env->CP0_Cause = (env->CP0_Cause & ~mask) | (val & mask); + + if ((old ^ env->CP0_Cause) & (1 << CP0Ca_DC)) { + if (env->CP0_Cause & (1 << CP0Ca_DC)) { + cpu_mips_stop_count(env); + } else { + cpu_mips_start_count(env); + } + } + + /* Set/reset software interrupts */ + for (i = 0 ; i < 2 ; i++) { + if ((old ^ env->CP0_Cause) & (1 << (CP0Ca_IP + i))) { + cpu_mips_soft_irq(env, i, env->CP0_Cause & (1 << (CP0Ca_IP + i))); + } + } +} diff --git a/target/mips/cp0_timer.c b/target/mips/sysemu/cp0_timer.c index 70de95d338..70de95d338 100644 --- a/target/mips/cp0_timer.c +++ b/target/mips/sysemu/cp0_timer.c diff --git a/target/mips/machine.c b/target/mips/sysemu/machine.c index b5fda6a278..80d37f9c2f 100644 --- a/target/mips/machine.c +++ b/target/mips/sysemu/machine.c @@ -81,6 +81,9 @@ const VMStateDescription vmstate_inactive_fpu = { static VMStateField vmstate_tc_fields[] = { VMSTATE_UINTTL_ARRAY(gpr, TCState, 32), +#if defined(TARGET_MIPS64) + VMSTATE_UINT64_ARRAY(gpr_hi, TCState, 32), +#endif /* TARGET_MIPS64 */ VMSTATE_UINTTL(PC, TCState), VMSTATE_UINTTL_ARRAY(HI, TCState, MIPS_DSP_ACC), VMSTATE_UINTTL_ARRAY(LO, TCState, MIPS_DSP_ACC), @@ -95,20 +98,22 @@ static VMStateField vmstate_tc_fields[] = { VMSTATE_INT32(CP0_Debug_tcstatus, TCState), VMSTATE_UINTTL(CP0_UserLocal, TCState), VMSTATE_INT32(msacsr, TCState), + VMSTATE_UINTTL_ARRAY(mxu_gpr, TCState, NUMBER_OF_MXU_REGISTERS - 1), + VMSTATE_UINTTL(mxu_cr, TCState), VMSTATE_END_OF_LIST() }; const VMStateDescription vmstate_tc = { .name = "cpu/tc", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = vmstate_tc_fields }; const VMStateDescription vmstate_inactive_tc = { .name = "cpu/inactive_tc", - .version_id = 1, - .minimum_version_id = 1, + .version_id = 2, + .minimum_version_id = 2, .fields = vmstate_tc_fields }; @@ -213,8 +218,8 @@ const VMStateDescription vmstate_tlb = { const VMStateDescription vmstate_mips_cpu = { .name = "cpu", - .version_id = 20, - .minimum_version_id = 20, + .version_id = 21, + .minimum_version_id = 21, .post_load = cpu_post_load, .fields = (VMStateField[]) { /* Active TC */ @@ -241,6 +246,7 @@ const VMStateDescription vmstate_mips_cpu = { /* Remaining CP0 registers */ VMSTATE_INT32(env.CP0_Index, MIPSCPU), + VMSTATE_INT32(env.CP0_VPControl, MIPSCPU), VMSTATE_INT32(env.CP0_Random, MIPSCPU), VMSTATE_INT32(env.CP0_VPEControl, MIPSCPU), VMSTATE_INT32(env.CP0_VPEConf0, MIPSCPU), @@ -251,6 +257,7 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_INT32(env.CP0_VPEOpt, MIPSCPU), VMSTATE_UINT64(env.CP0_EntryLo0, MIPSCPU), VMSTATE_UINT64(env.CP0_EntryLo1, MIPSCPU), + VMSTATE_INT32(env.CP0_GlobalNumber, MIPSCPU), VMSTATE_UINTTL(env.CP0_Context, MIPSCPU), VMSTATE_INT32(env.CP0_MemoryMapID, MIPSCPU), VMSTATE_INT32(env.CP0_PageMask, MIPSCPU), @@ -286,6 +293,7 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_UINTTL(env.CP0_EPC, MIPSCPU), VMSTATE_INT32(env.CP0_PRid, MIPSCPU), VMSTATE_UINTTL(env.CP0_EBase, MIPSCPU), + VMSTATE_UINTTL(env.CP0_CMGCRBase, MIPSCPU), VMSTATE_INT32(env.CP0_Config0, MIPSCPU), VMSTATE_INT32(env.CP0_Config1, MIPSCPU), VMSTATE_INT32(env.CP0_Config2, MIPSCPU), @@ -305,6 +313,7 @@ const VMStateDescription vmstate_mips_cpu = { VMSTATE_INT32(env.CP0_Debug, MIPSCPU), VMSTATE_UINTTL(env.CP0_DEPC, MIPSCPU), VMSTATE_INT32(env.CP0_Performance0, MIPSCPU), + VMSTATE_INT32(env.CP0_ErrCtl, MIPSCPU), VMSTATE_UINT64(env.CP0_TagLo, MIPSCPU), VMSTATE_INT32(env.CP0_DataLo, MIPSCPU), VMSTATE_INT32(env.CP0_TagHi, MIPSCPU), diff --git a/target/mips/sysemu/meson.build b/target/mips/sysemu/meson.build new file mode 100644 index 0000000000..cefc227582 --- /dev/null +++ b/target/mips/sysemu/meson.build @@ -0,0 +1,7 @@ +mips_softmmu_ss.add(files( + 'addr.c', + 'cp0.c', + 'cp0_timer.c', + 'machine.c', + 'physaddr.c', +)) diff --git a/target/mips/sysemu/physaddr.c b/target/mips/sysemu/physaddr.c new file mode 100644 index 0000000000..1918633aa1 --- /dev/null +++ b/target/mips/sysemu/physaddr.c @@ -0,0 +1,257 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/exec-all.h" +#include "../internal.h" + +static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) +{ + /* + * Interpret access control mode and mmu_idx. + * AdE? TLB? + * AM K S U E K S U E + * UK 0 0 1 1 0 0 - - 0 + * MK 1 0 1 1 0 1 - - !eu + * MSK 2 0 0 1 0 1 1 - !eu + * MUSK 3 0 0 0 0 1 1 1 !eu + * MUSUK 4 0 0 0 0 0 1 1 0 + * USK 5 0 0 1 0 0 0 - 0 + * - 6 - - - - - - - - + * UUSK 7 0 0 0 0 0 0 0 0 + */ + int32_t adetlb_mask; + + switch (mmu_idx) { + case 3: /* ERL */ + /* If EU is set, always unmapped */ + if (eu) { + return 0; + } + /* fall through */ + case MIPS_HFLAG_KM: + /* Never AdE, TLB mapped if AM={1,2,3} */ + adetlb_mask = 0x70000000; + goto check_tlb; + + case MIPS_HFLAG_SM: + /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */ + adetlb_mask = 0xc0380000; + goto check_ade; + + case MIPS_HFLAG_UM: + /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */ + adetlb_mask = 0xe4180000; + /* fall through */ + check_ade: + /* does this AM cause AdE in current execution mode */ + if ((adetlb_mask << am) < 0) { + return TLBRET_BADADDR; + } + adetlb_mask <<= 8; + /* fall through */ + check_tlb: + /* is this AM mapped in current execution mode */ + return ((adetlb_mask << am) < 0); + default: + assert(0); + return TLBRET_BADADDR; + }; +} + +static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx, + unsigned int am, bool eu, + target_ulong segmask, + hwaddr physical_base) +{ + int mapped = is_seg_am_mapped(am, eu, mmu_idx); + + if (mapped < 0) { + /* is_seg_am_mapped can report TLBRET_BADADDR */ + return mapped; + } else if (mapped) { + /* The segment is TLB mapped */ + return env->tlb->map_address(env, physical, prot, real_address, + access_type); + } else { + /* The segment is unmapped */ + *physical = physical_base | (real_address & segmask); + *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; + return TLBRET_MATCH; + } +} + +static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx, + uint16_t segctl, target_ulong segmask) +{ + unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM; + bool eu = (segctl >> CP0SC_EU) & 1; + hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20; + + return get_seg_physical_address(env, physical, prot, real_address, + access_type, mmu_idx, am, eu, segmask, + pa & ~(hwaddr)segmask); +} + +int get_physical_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong real_address, + MMUAccessType access_type, int mmu_idx) +{ + /* User mode can only access useg/xuseg */ +#if defined(TARGET_MIPS64) + int user_mode = mmu_idx == MIPS_HFLAG_UM; + int supervisor_mode = mmu_idx == MIPS_HFLAG_SM; + int kernel_mode = !user_mode && !supervisor_mode; + int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; + int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; + int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; +#endif + int ret = TLBRET_MATCH; + /* effective address (modified for KVM T&E kernel segments) */ + target_ulong address = real_address; + + if (mips_um_ksegs_enabled()) { + /* KVM T&E adds guest kernel segments in useg */ + if (real_address >= KVM_KSEG0_BASE) { + if (real_address < KVM_KSEG2_BASE) { + /* kseg0 */ + address += KSEG0_BASE - KVM_KSEG0_BASE; + } else if (real_address <= USEG_LIMIT) { + /* kseg2/3 */ + address += KSEG2_BASE - KVM_KSEG2_BASE; + } + } + } + + if (address <= USEG_LIMIT) { + /* useg */ + uint16_t segctl; + + if (address >= 0x40000000UL) { + segctl = env->CP0_SegCtl2; + } else { + segctl = env->CP0_SegCtl2 >> 16; + } + ret = get_segctl_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, segctl, 0x3FFFFFFF); +#if defined(TARGET_MIPS64) + } else if (address < 0x4000000000000000ULL) { + /* xuseg */ + if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret = env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret = TLBRET_BADADDR; + } + } else if (address < 0x8000000000000000ULL) { + /* xsseg */ + if ((supervisor_mode || kernel_mode) && + SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { + ret = env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret = TLBRET_BADADDR; + } + } else if (address < 0xC000000000000000ULL) { + /* xkphys */ + if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { + /* KX/SX/UX bit to check for each xkphys EVA access mode */ + static const uint8_t am_ksux[8] = { + [CP0SC_AM_UK] = (1u << CP0St_KX), + [CP0SC_AM_MK] = (1u << CP0St_KX), + [CP0SC_AM_MSK] = (1u << CP0St_SX), + [CP0SC_AM_MUSK] = (1u << CP0St_UX), + [CP0SC_AM_MUSUK] = (1u << CP0St_UX), + [CP0SC_AM_USK] = (1u << CP0St_SX), + [6] = (1u << CP0St_KX), + [CP0SC_AM_UUSK] = (1u << CP0St_UX), + }; + unsigned int am = CP0SC_AM_UK; + unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR; + + if (xr & (1 << ((address >> 59) & 0x7))) { + am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; + } + /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ + if (env->CP0_Status & am_ksux[am]) { + ret = get_seg_physical_address(env, physical, prot, + real_address, access_type, + mmu_idx, am, false, env->PAMask, + 0); + } else { + ret = TLBRET_BADADDR; + } + } else { + ret = TLBRET_BADADDR; + } + } else if (address < 0xFFFFFFFF80000000ULL) { + /* xkseg */ + if (kernel_mode && KX && + address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { + ret = env->tlb->map_address(env, physical, prot, + real_address, access_type); + } else { + ret = TLBRET_BADADDR; + } +#endif + } else if (address < KSEG1_BASE) { + /* kseg0 */ + ret = get_segctl_physical_address(env, physical, prot, real_address, + access_type, mmu_idx, + env->CP0_SegCtl1 >> 16, 0x1FFFFFFF); + } else if (address < KSEG2_BASE) { + /* kseg1 */ + ret = get_segctl_physical_address(env, physical, prot, real_address, + access_type, mmu_idx, + env->CP0_SegCtl1, 0x1FFFFFFF); + } else if (address < KSEG3_BASE) { + /* sseg (kseg2) */ + ret = get_segctl_physical_address(env, physical, prot, real_address, + access_type, mmu_idx, + env->CP0_SegCtl0 >> 16, 0x1FFFFFFF); + } else { + /* + * kseg3 + * XXX: debug segment is not emulated + */ + ret = get_segctl_physical_address(env, physical, prot, real_address, + access_type, mmu_idx, + env->CP0_SegCtl0, 0x1FFFFFFF); + } + return ret; +} + +hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + hwaddr phys_addr; + int prot; + + if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, + cpu_mmu_index(env, false)) != 0) { + return -1; + } + return phys_addr; +} diff --git a/target/mips/dsp_helper.c b/target/mips/tcg/dsp_helper.c index 09b6e5fb15..09b6e5fb15 100644 --- a/target/mips/dsp_helper.c +++ b/target/mips/tcg/dsp_helper.c diff --git a/target/mips/tcg/exception.c b/target/mips/tcg/exception.c new file mode 100644 index 0000000000..4fb8b00711 --- /dev/null +++ b/target/mips/tcg/exception.c @@ -0,0 +1,167 @@ +/* + * MIPS Exceptions processing helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" + +target_ulong exception_resume_pc(CPUMIPSState *env) +{ + target_ulong bad_pc; + target_ulong isa_mode; + + isa_mode = !!(env->hflags & MIPS_HFLAG_M16); + bad_pc = env->active_tc.PC | isa_mode; + if (env->hflags & MIPS_HFLAG_BMASK) { + /* + * If the exception was raised from a delay slot, come back to + * the jump. + */ + bad_pc -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + } + + return bad_pc; +} + +void helper_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code) +{ + do_raise_exception_err(env, exception, error_code, 0); +} + +void helper_raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, GETPC()); +} + +void helper_raise_exception_debug(CPUMIPSState *env) +{ + do_raise_exception(env, EXCP_DEBUG, 0); +} + +static void raise_exception(CPUMIPSState *env, uint32_t exception) +{ + do_raise_exception(env, exception, 0); +} + +void helper_wait(CPUMIPSState *env) +{ + CPUState *cs = env_cpu(env); + + cs->halted = 1; + cpu_reset_interrupt(cs, CPU_INTERRUPT_WAKE); + /* + * Last instruction in the block, PC was updated before + * - no need to recover PC and icount. + */ + raise_exception(env, EXCP_HLT); +} + +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + env->active_tc.PC = tb->pc; + env->hflags &= ~MIPS_HFLAG_BMASK; + env->hflags |= tb->flags & MIPS_HFLAG_BMASK; +} + +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if (cpu_mips_hw_interrupts_enabled(env) && + cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index = EXCP_EXT_INTERRUPT; + env->error_code = 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + +static const char * const excp_names[EXCP_LAST + 1] = { + [EXCP_RESET] = "reset", + [EXCP_SRESET] = "soft reset", + [EXCP_DSS] = "debug single step", + [EXCP_DINT] = "debug interrupt", + [EXCP_NMI] = "non-maskable interrupt", + [EXCP_MCHECK] = "machine check", + [EXCP_EXT_INTERRUPT] = "interrupt", + [EXCP_DFWATCH] = "deferred watchpoint", + [EXCP_DIB] = "debug instruction breakpoint", + [EXCP_IWATCH] = "instruction fetch watchpoint", + [EXCP_AdEL] = "address error load", + [EXCP_AdES] = "address error store", + [EXCP_TLBF] = "TLB refill", + [EXCP_IBE] = "instruction bus error", + [EXCP_DBp] = "debug breakpoint", + [EXCP_SYSCALL] = "syscall", + [EXCP_BREAK] = "break", + [EXCP_CpU] = "coprocessor unusable", + [EXCP_RI] = "reserved instruction", + [EXCP_OVERFLOW] = "arithmetic overflow", + [EXCP_TRAP] = "trap", + [EXCP_FPE] = "floating point", + [EXCP_DDBS] = "debug data break store", + [EXCP_DWATCH] = "data watchpoint", + [EXCP_LTLBL] = "TLB modify", + [EXCP_TLBL] = "TLB load", + [EXCP_TLBS] = "TLB store", + [EXCP_DBE] = "data bus error", + [EXCP_DDBL] = "debug data break load", + [EXCP_THREAD] = "thread", + [EXCP_MDMX] = "MDMX", + [EXCP_C2E] = "precise coprocessor 2", + [EXCP_CACHE] = "cache error", + [EXCP_TLBXI] = "TLB execute-inhibit", + [EXCP_TLBRI] = "TLB read-inhibit", + [EXCP_MSADIS] = "MSA disabled", + [EXCP_MSAFPE] = "MSA floating point", +}; + +const char *mips_exception_name(int32_t exception) +{ + if (exception < 0 || exception > EXCP_LAST) { + return "unknown"; + } + return excp_names[exception]; +} + +void do_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code, uintptr_t pc) +{ + CPUState *cs = env_cpu(env); + + qemu_log_mask(CPU_LOG_INT, "%s: %d (%s) %d\n", + __func__, exception, mips_exception_name(exception), + error_code); + cs->exception_index = exception; + env->error_code = error_code; + + cpu_loop_exit_restore(cs, pc); +} diff --git a/target/mips/fpu_helper.c b/target/mips/tcg/fpu_helper.c index 6dd853259e..8ce56ed7c8 100644 --- a/target/mips/fpu_helper.c +++ b/target/mips/tcg/fpu_helper.c @@ -38,14 +38,6 @@ #define FP_TO_INT32_OVERFLOW 0x7fffffff #define FP_TO_INT64_OVERFLOW 0x7fffffffffffffffULL -/* convert MIPS rounding mode in FCR31 to IEEE library */ -const FloatRoundMode ieee_rm[4] = { - float_round_nearest_even, - float_round_to_zero, - float_round_up, - float_round_down -}; - target_ulong helper_cfc1(CPUMIPSState *env, uint32_t reg) { target_ulong arg1 = 0; diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c new file mode 100644 index 0000000000..d42812b8a6 --- /dev/null +++ b/target/mips/tcg/ldst_helper.c @@ -0,0 +1,288 @@ +/* + * MIPS emulation load/store helpers for QEMU. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * SPDX-License-Identifier: LGPL-2.1-or-later + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "exec/memop.h" +#include "internal.h" + +#ifndef CONFIG_USER_ONLY + +#define HELPER_LD_ATOMIC(name, insn, almask, do_cast) \ +target_ulong helper_##name(CPUMIPSState *env, target_ulong arg, int mem_idx) \ +{ \ + if (arg & almask) { \ + if (!(env->hflags & MIPS_HFLAG_DM)) { \ + env->CP0_BadVAddr = arg; \ + } \ + do_raise_exception(env, EXCP_AdEL, GETPC()); \ + } \ + env->CP0_LLAddr = cpu_mips_translate_address(env, arg, MMU_DATA_LOAD, \ + GETPC()); \ + env->lladdr = arg; \ + env->llval = do_cast cpu_##insn##_mmuidx_ra(env, arg, mem_idx, GETPC()); \ + return env->llval; \ +} +HELPER_LD_ATOMIC(ll, ldl, 0x3, (target_long)(int32_t)) +#ifdef TARGET_MIPS64 +HELPER_LD_ATOMIC(lld, ldq, 0x7, (target_ulong)) +#endif +#undef HELPER_LD_ATOMIC + +#endif /* !CONFIG_USER_ONLY */ + +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK(v) ((v) & 3) +#define GET_OFFSET(addr, offset) (addr + (offset)) +#else +#define GET_LMASK(v) (((v) & 3) ^ 3) +#define GET_OFFSET(addr, offset) (addr - (offset)) +#endif + +void helper_swl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 24), mem_idx, GETPC()); + + if (GET_LMASK(arg2) <= 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) <= 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) == 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_swr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK(arg2) >= 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) >= 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK(arg2) == 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } +} + +#if defined(TARGET_MIPS64) +/* + * "half" load and stores. We must do the memory access inline, + * or fault handling won't work. + */ +#ifdef TARGET_WORDS_BIGENDIAN +#define GET_LMASK64(v) ((v) & 7) +#else +#define GET_LMASK64(v) (((v) & 7) ^ 7) +#endif + +void helper_sdl(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)(arg1 >> 56), mem_idx, GETPC()); + + if (GET_LMASK64(arg2) <= 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 1), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <= 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 2), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <= 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 3), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <= 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 4), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <= 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 5), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <= 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 6), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) <= 0) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, 7), (uint8_t)arg1, + mem_idx, GETPC()); + } +} + +void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, + int mem_idx) +{ + cpu_stb_mmuidx_ra(env, arg2, (uint8_t)arg1, mem_idx, GETPC()); + + if (GET_LMASK64(arg2) >= 1) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -1), (uint8_t)(arg1 >> 8), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >= 2) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -2), (uint8_t)(arg1 >> 16), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >= 3) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -3), (uint8_t)(arg1 >> 24), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >= 4) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -4), (uint8_t)(arg1 >> 32), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >= 5) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -5), (uint8_t)(arg1 >> 40), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) >= 6) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -6), (uint8_t)(arg1 >> 48), + mem_idx, GETPC()); + } + + if (GET_LMASK64(arg2) == 7) { + cpu_stb_mmuidx_ra(env, GET_OFFSET(arg2, -7), (uint8_t)(arg1 >> 56), + mem_idx, GETPC()); + } +} +#endif /* TARGET_MIPS64 */ + +static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; + +void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist = reglist & 0xf; + target_ulong do_r31 = reglist & 0x10; + + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i = 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] = + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); + addr += 4; + } + } + + if (do_r31) { + env->active_tc.gpr[31] = + (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_swm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist = reglist & 0xf; + target_ulong do_r31 = reglist & 0x10; + + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i = 0; i < base_reglist; i++) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]], + mem_idx, GETPC()); + addr += 4; + } + } + + if (do_r31) { + cpu_stw_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); + } +} + +#if defined(TARGET_MIPS64) +void helper_ldm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist = reglist & 0xf; + target_ulong do_r31 = reglist & 0x10; + + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i = 0; i < base_reglist; i++) { + env->active_tc.gpr[multiple_regs[i]] = + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + addr += 8; + } + } + + if (do_r31) { + env->active_tc.gpr[31] = + cpu_ldq_mmuidx_ra(env, addr, mem_idx, GETPC()); + } +} + +void helper_sdm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, + uint32_t mem_idx) +{ + target_ulong base_reglist = reglist & 0xf; + target_ulong do_r31 = reglist & 0x10; + + if (base_reglist > 0 && base_reglist <= ARRAY_SIZE(multiple_regs)) { + target_ulong i; + + for (i = 0; i < base_reglist; i++) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[multiple_regs[i]], + mem_idx, GETPC()); + addr += 8; + } + } + + if (do_r31) { + cpu_stq_mmuidx_ra(env, addr, env->active_tc.gpr[31], mem_idx, GETPC()); + } +} + +#endif /* TARGET_MIPS64 */ diff --git a/target/mips/lmmi_helper.c b/target/mips/tcg/lmmi_helper.c index abeb7736ae..abeb7736ae 100644 --- a/target/mips/lmmi_helper.c +++ b/target/mips/tcg/lmmi_helper.c diff --git a/target/mips/tcg/meson.build b/target/mips/tcg/meson.build new file mode 100644 index 0000000000..5d8acbaf0d --- /dev/null +++ b/target/mips/tcg/meson.build @@ -0,0 +1,35 @@ +gen = [ + decodetree.process('mips32r6.decode', extra_args: '--static-decode=decode_mips32r6'), + decodetree.process('mips64r6.decode', extra_args: '--static-decode=decode_mips64r6'), + decodetree.process('msa32.decode', extra_args: '--static-decode=decode_msa32'), + decodetree.process('msa64.decode', extra_args: '--static-decode=decode_msa64'), + decodetree.process('tx79.decode', extra_args: '--static-decode=decode_tx79'), +] + +mips_ss.add(gen) +mips_ss.add(files( + 'dsp_helper.c', + 'exception.c', + 'fpu_helper.c', + 'ldst_helper.c', + 'lmmi_helper.c', + 'msa_helper.c', + 'msa_translate.c', + 'op_helper.c', + 'rel6_translate.c', + 'translate.c', + 'translate_addr_const.c', + 'txx9_translate.c', +)) +mips_ss.add(when: 'TARGET_MIPS64', if_true: files( + 'tx79_translate.c', +), if_false: files( + 'mxu_translate.c', +)) + +if have_user + subdir('user') +endif +if have_system + subdir('sysemu') +endif diff --git a/target/mips/mips32r6.decode b/target/mips/tcg/mips32r6.decode index 837c991edc..837c991edc 100644 --- a/target/mips/mips32r6.decode +++ b/target/mips/tcg/mips32r6.decode diff --git a/target/mips/mips64r6.decode b/target/mips/tcg/mips64r6.decode index b58d8009cc..b58d8009cc 100644 --- a/target/mips/mips64r6.decode +++ b/target/mips/tcg/mips64r6.decode diff --git a/target/mips/msa32.decode b/target/mips/tcg/msa32.decode index ca200e373b..ca200e373b 100644 --- a/target/mips/msa32.decode +++ b/target/mips/tcg/msa32.decode diff --git a/target/mips/msa64.decode b/target/mips/tcg/msa64.decode index d2442474d0..d2442474d0 100644 --- a/target/mips/msa64.decode +++ b/target/mips/tcg/msa64.decode diff --git a/target/mips/msa_helper.c b/target/mips/tcg/msa_helper.c index 4caefe29ad..04af54f66d 100644 --- a/target/mips/msa_helper.c +++ b/target/mips/tcg/msa_helper.c @@ -8595,39 +8595,3 @@ void helper_msa_st_d(CPUMIPSState *env, uint32_t wd, cpu_stq_data(env, addr + (1 << DF_DOUBLE), pwd->d[1]); #endif } - -void msa_reset(CPUMIPSState *env) -{ - if (!ase_msa_available(env)) { - return; - } - -#ifdef CONFIG_USER_ONLY - /* MSA access enabled */ - env->CP0_Config5 |= 1 << CP0C5_MSAEn; - env->CP0_Status |= (1 << CP0St_CU1) | (1 << CP0St_FR); -#endif - - /* - * MSA CSR: - * - non-signaling floating point exception mode off (NX bit is 0) - * - Cause, Enables, and Flags are all 0 - * - round to nearest / ties to even (RM bits are 0) - */ - env->active_tc.msacsr = 0; - - restore_msa_fp_status(env); - - /* tininess detected after rounding.*/ - set_float_detect_tininess(float_tininess_after_rounding, - &env->active_tc.msa_fp_status); - - /* clear float_status exception flags */ - set_float_exception_flags(0, &env->active_tc.msa_fp_status); - - /* clear float_status nan mode */ - set_default_nan_mode(0, &env->active_tc.msa_fp_status); - - /* set proper signanling bit meaning ("1" means "quiet") */ - set_snan_bit_is_one(0, &env->active_tc.msa_fp_status); -} diff --git a/target/mips/msa_helper.h.inc b/target/mips/tcg/msa_helper.h.inc index 4963d1553a..4963d1553a 100644 --- a/target/mips/msa_helper.h.inc +++ b/target/mips/tcg/msa_helper.h.inc diff --git a/target/mips/msa_translate.c b/target/mips/tcg/msa_translate.c index ae6587edf6..ae6587edf6 100644 --- a/target/mips/msa_translate.c +++ b/target/mips/tcg/msa_translate.c diff --git a/target/mips/mxu_translate.c b/target/mips/tcg/mxu_translate.c index fb0a811af6..fb0a811af6 100644 --- a/target/mips/mxu_translate.c +++ b/target/mips/tcg/mxu_translate.c diff --git a/target/mips/tcg/op_helper.c b/target/mips/tcg/op_helper.c new file mode 100644 index 0000000000..ce1549c985 --- /dev/null +++ b/target/mips/tcg/op_helper.c @@ -0,0 +1,420 @@ +/* + * MIPS emulation helpers for qemu. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "internal.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "exec/memop.h" +#include "fpu_helper.h" + +/* 64 bits arithmetic for 32 bits hosts */ +static inline uint64_t get_HILO(CPUMIPSState *env) +{ + return ((uint64_t)(env->active_tc.HI[0]) << 32) | + (uint32_t)env->active_tc.LO[0]; +} + +static inline target_ulong set_HIT0_LO(CPUMIPSState *env, uint64_t HILO) +{ + env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); + return env->active_tc.HI[0] = (int32_t)(HILO >> 32); +} + +static inline target_ulong set_HI_LOT0(CPUMIPSState *env, uint64_t HILO) +{ + target_ulong tmp = env->active_tc.LO[0] = (int32_t)(HILO & 0xFFFFFFFF); + env->active_tc.HI[0] = (int32_t)(HILO >> 32); + return tmp; +} + +/* Multiplication variants of the vr54xx. */ +target_ulong helper_muls(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, 0 - ((int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2)); +} + +target_ulong helper_mulsu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_macc(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_macchi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)get_HILO(env) + (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_maccu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (uint64_t)get_HILO(env) + + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_macchiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)get_HILO(env) + + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_msac(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_msachi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)get_HILO(env) - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_msacu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HI_LOT0(env, (uint64_t)get_HILO(env) - + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_msachiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)get_HILO(env) - + (uint64_t)(uint32_t)arg1 * (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_mulhi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (int64_t)(int32_t)arg1 * (int64_t)(int32_t)arg2); +} + +target_ulong helper_mulhiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +target_ulong helper_mulshi(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, 0 - (int64_t)(int32_t)arg1 * + (int64_t)(int32_t)arg2); +} + +target_ulong helper_mulshiu(CPUMIPSState *env, target_ulong arg1, + target_ulong arg2) +{ + return set_HIT0_LO(env, 0 - (uint64_t)(uint32_t)arg1 * + (uint64_t)(uint32_t)arg2); +} + +static inline target_ulong bitswap(target_ulong v) +{ + v = ((v >> 1) & (target_ulong)0x5555555555555555ULL) | + ((v & (target_ulong)0x5555555555555555ULL) << 1); + v = ((v >> 2) & (target_ulong)0x3333333333333333ULL) | + ((v & (target_ulong)0x3333333333333333ULL) << 2); + v = ((v >> 4) & (target_ulong)0x0F0F0F0F0F0F0F0FULL) | + ((v & (target_ulong)0x0F0F0F0F0F0F0F0FULL) << 4); + return v; +} + +#ifdef TARGET_MIPS64 +target_ulong helper_dbitswap(target_ulong rt) +{ + return bitswap(rt); +} +#endif + +target_ulong helper_bitswap(target_ulong rt) +{ + return (int32_t)bitswap(rt); +} + +target_ulong helper_rotx(target_ulong rs, uint32_t shift, uint32_t shiftx, + uint32_t stripe) +{ + int i; + uint64_t tmp0 = ((uint64_t)rs) << 32 | ((uint64_t)rs & 0xffffffff); + uint64_t tmp1 = tmp0; + for (i = 0; i <= 46; i++) { + int s; + if (i & 0x8) { + s = shift; + } else { + s = shiftx; + } + + if (stripe != 0 && !(i & 0x4)) { + s = ~s; + } + if (s & 0x10) { + if (tmp0 & (1LL << (i + 16))) { + tmp1 |= 1LL << i; + } else { + tmp1 &= ~(1LL << i); + } + } + } + + uint64_t tmp2 = tmp1; + for (i = 0; i <= 38; i++) { + int s; + if (i & 0x4) { + s = shift; + } else { + s = shiftx; + } + + if (s & 0x8) { + if (tmp1 & (1LL << (i + 8))) { + tmp2 |= 1LL << i; + } else { + tmp2 &= ~(1LL << i); + } + } + } + + uint64_t tmp3 = tmp2; + for (i = 0; i <= 34; i++) { + int s; + if (i & 0x2) { + s = shift; + } else { + s = shiftx; + } + if (s & 0x4) { + if (tmp2 & (1LL << (i + 4))) { + tmp3 |= 1LL << i; + } else { + tmp3 &= ~(1LL << i); + } + } + } + + uint64_t tmp4 = tmp3; + for (i = 0; i <= 32; i++) { + int s; + if (i & 0x1) { + s = shift; + } else { + s = shiftx; + } + if (s & 0x2) { + if (tmp3 & (1LL << (i + 2))) { + tmp4 |= 1LL << i; + } else { + tmp4 &= ~(1LL << i); + } + } + } + + uint64_t tmp5 = tmp4; + for (i = 0; i <= 31; i++) { + int s; + s = shift; + if (s & 0x1) { + if (tmp4 & (1LL << (i + 1))) { + tmp5 |= 1LL << i; + } else { + tmp5 &= ~(1LL << i); + } + } + } + + return (int64_t)(int32_t)(uint32_t)tmp5; +} + +void helper_fork(target_ulong arg1, target_ulong arg2) +{ + /* + * arg1 = rt, arg2 = rs + * TODO: store to TC register + */ +} + +target_ulong helper_yield(CPUMIPSState *env, target_ulong arg) +{ + target_long arg1 = arg; + + if (arg1 < 0) { + /* No scheduling policy implemented. */ + if (arg1 != -2) { + if (env->CP0_VPEControl & (1 << CP0VPECo_YSI) && + env->active_tc.CP0_TCStatus & (1 << CP0TCSt_DT)) { + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |= 4 << CP0VPECo_EXCPT; + do_raise_exception(env, EXCP_THREAD, GETPC()); + } + } + } else if (arg1 == 0) { + if (0) { + /* TODO: TC underflow */ + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + do_raise_exception(env, EXCP_THREAD, GETPC()); + } else { + /* TODO: Deallocate TC */ + } + } else if (arg1 > 0) { + /* Yield qualifier inputs not implemented. */ + env->CP0_VPEControl &= ~(0x7 << CP0VPECo_EXCPT); + env->CP0_VPEControl |= 2 << CP0VPECo_EXCPT; + do_raise_exception(env, EXCP_THREAD, GETPC()); + } + return env->CP0_YQMask; +} + +static inline void check_hwrena(CPUMIPSState *env, int reg, uintptr_t pc) +{ + if ((env->hflags & MIPS_HFLAG_CP0) || (env->CP0_HWREna & (1 << reg))) { + return; + } + do_raise_exception(env, EXCP_RI, pc); +} + +target_ulong helper_rdhwr_cpunum(CPUMIPSState *env) +{ + check_hwrena(env, 0, GETPC()); + return env->CP0_EBase & 0x3ff; +} + +target_ulong helper_rdhwr_synci_step(CPUMIPSState *env) +{ + check_hwrena(env, 1, GETPC()); + return env->SYNCI_Step; +} + +target_ulong helper_rdhwr_cc(CPUMIPSState *env) +{ + check_hwrena(env, 2, GETPC()); +#ifdef CONFIG_USER_ONLY + return env->CP0_Count; +#else + return (int32_t)cpu_mips_get_count(env); +#endif +} + +target_ulong helper_rdhwr_ccres(CPUMIPSState *env) +{ + check_hwrena(env, 3, GETPC()); + return env->CCRes; +} + +target_ulong helper_rdhwr_performance(CPUMIPSState *env) +{ + check_hwrena(env, 4, GETPC()); + return env->CP0_Performance0; +} + +target_ulong helper_rdhwr_xnp(CPUMIPSState *env) +{ + check_hwrena(env, 5, GETPC()); + return (env->CP0_Config5 >> CP0C5_XNP) & 1; +} + +void helper_pmon(CPUMIPSState *env, int function) +{ + function /= 2; + switch (function) { + case 2: /* TODO: char inbyte(int waitflag); */ + if (env->active_tc.gpr[4] == 0) { + env->active_tc.gpr[2] = -1; + } + /* Fall through */ + case 11: /* TODO: char inbyte (void); */ + env->active_tc.gpr[2] = -1; + break; + case 3: + case 12: + printf("%c", (char)(env->active_tc.gpr[4] & 0xFF)); + break; + case 17: + break; + case 158: + { + unsigned char *fmt = (void *)(uintptr_t)env->active_tc.gpr[4]; + printf("%s", fmt); + } + break; + } +} + +#if !defined(CONFIG_USER_ONLY) + +void mips_cpu_do_unaligned_access(CPUState *cs, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + int error_code = 0; + int excp; + + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr = addr; + } + + if (access_type == MMU_DATA_STORE) { + excp = EXCP_AdES; + } else { + excp = EXCP_AdEL; + if (access_type == MMU_INST_FETCH) { + error_code |= EXCP_INST_NOTAVAIL; + } + } + + do_raise_exception_err(env, excp, error_code, retaddr); +} + +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if (access_type == MMU_INST_FETCH) { + do_raise_exception(env, EXCP_IBE, retaddr); + } else { + do_raise_exception(env, EXCP_DBE, retaddr); + } +} +#endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/rel6_translate.c b/target/mips/tcg/rel6_translate.c index 0354370927..0354370927 100644 --- a/target/mips/rel6_translate.c +++ b/target/mips/tcg/rel6_translate.c diff --git a/target/mips/cp0_helper.c b/target/mips/tcg/sysemu/cp0_helper.c index aae2af6ecc..aae2af6ecc 100644 --- a/target/mips/cp0_helper.c +++ b/target/mips/tcg/sysemu/cp0_helper.c diff --git a/target/mips/tcg/sysemu/meson.build b/target/mips/tcg/sysemu/meson.build new file mode 100644 index 0000000000..4da2c577b2 --- /dev/null +++ b/target/mips/tcg/sysemu/meson.build @@ -0,0 +1,6 @@ +mips_softmmu_ss.add(files( + 'cp0_helper.c', + 'mips-semi.c', + 'special_helper.c', + 'tlb_helper.c', +)) diff --git a/target/mips/mips-semi.c b/target/mips/tcg/sysemu/mips-semi.c index 6de60fa6dd..6de60fa6dd 100644 --- a/target/mips/mips-semi.c +++ b/target/mips/tcg/sysemu/mips-semi.c diff --git a/target/mips/tcg/sysemu/special_helper.c b/target/mips/tcg/sysemu/special_helper.c new file mode 100644 index 0000000000..2a2afb49e8 --- /dev/null +++ b/target/mips/tcg/sysemu/special_helper.c @@ -0,0 +1,173 @@ +/* + * QEMU MIPS emulation: Special opcode helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + * + */ + +#include "qemu/osdep.h" +#include "cpu.h" +#include "exec/helper-proto.h" +#include "exec/exec-all.h" +#include "internal.h" + +/* Specials */ +target_ulong helper_di(CPUMIPSState *env) +{ + target_ulong t0 = env->CP0_Status; + + env->CP0_Status = t0 & ~(1 << CP0St_IE); + return t0; +} + +target_ulong helper_ei(CPUMIPSState *env) +{ + target_ulong t0 = env->CP0_Status; + + env->CP0_Status = t0 | (1 << CP0St_IE); + return t0; +} + +static void debug_pre_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log("ERET: PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + qemu_log("\n"); + } +} + +static void debug_post_eret(CPUMIPSState *env) +{ + if (qemu_loglevel_mask(CPU_LOG_EXEC)) { + qemu_log(" => PC " TARGET_FMT_lx " EPC " TARGET_FMT_lx, + env->active_tc.PC, env->CP0_EPC); + if (env->CP0_Status & (1 << CP0St_ERL)) { + qemu_log(" ErrorEPC " TARGET_FMT_lx, env->CP0_ErrorEPC); + } + if (env->hflags & MIPS_HFLAG_DM) { + qemu_log(" DEPC " TARGET_FMT_lx, env->CP0_DEPC); + } + switch (cpu_mmu_index(env, false)) { + case 3: + qemu_log(", ERL\n"); + break; + case MIPS_HFLAG_UM: + qemu_log(", UM\n"); + break; + case MIPS_HFLAG_SM: + qemu_log(", SM\n"); + break; + case MIPS_HFLAG_KM: + qemu_log("\n"); + break; + default: + cpu_abort(env_cpu(env), "Invalid MMU mode!\n"); + break; + } + } +} + +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if ((env->hflags & MIPS_HFLAG_BMASK) != 0 + && env->active_tc.PC != tb->pc) { + env->active_tc.PC -= (env->hflags & MIPS_HFLAG_B16 ? 2 : 4); + env->hflags &= ~MIPS_HFLAG_BMASK; + return true; + } + return false; +} + +static inline void exception_return(CPUMIPSState *env) +{ + debug_pre_eret(env); + if (env->CP0_Status & (1 << CP0St_ERL)) { + mips_env_set_pc(env, env->CP0_ErrorEPC); + env->CP0_Status &= ~(1 << CP0St_ERL); + } else { + mips_env_set_pc(env, env->CP0_EPC); + env->CP0_Status &= ~(1 << CP0St_EXL); + } + compute_hflags(env); + debug_post_eret(env); +} + +void helper_eret(CPUMIPSState *env) +{ + exception_return(env); + env->CP0_LLAddr = 1; + env->lladdr = 1; +} + +void helper_eretnc(CPUMIPSState *env) +{ + exception_return(env); +} + +void helper_deret(CPUMIPSState *env) +{ + debug_pre_eret(env); + + env->hflags &= ~MIPS_HFLAG_DM; + compute_hflags(env); + + mips_env_set_pc(env, env->CP0_DEPC); + + debug_post_eret(env); +} + +void helper_cache(CPUMIPSState *env, target_ulong addr, uint32_t op) +{ + static const char *const type_name[] = { + "Primary Instruction", + "Primary Data or Unified Primary", + "Tertiary", + "Secondary" + }; + uint32_t cache_type = extract32(op, 0, 2); + uint32_t cache_operation = extract32(op, 2, 3); + target_ulong index = addr & 0x1fffffff; + + switch (cache_operation) { + case 0b010: /* Index Store Tag */ + memory_region_dispatch_write(env->itc_tag, index, env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b001: /* Index Load Tag */ + memory_region_dispatch_read(env->itc_tag, index, &env->CP0_TagLo, + MO_64, MEMTXATTRS_UNSPECIFIED); + break; + case 0b000: /* Index Invalidate */ + case 0b100: /* Hit Invalidate */ + case 0b110: /* Hit Writeback */ + /* no-op */ + break; + default: + qemu_log_mask(LOG_UNIMP, "cache operation:%u (type: %s cache)\n", + cache_operation, type_name[cache_type]); + break; + } +} diff --git a/target/mips/tlb_helper.c b/target/mips/tcg/sysemu/tlb_helper.c index 8d3ea49780..259f780d19 100644 --- a/target/mips/tlb_helper.c +++ b/target/mips/tcg/sysemu/tlb_helper.c @@ -24,22 +24,341 @@ #include "exec/cpu_ldst.h" #include "exec/log.h" #include "hw/mips/cpudevs.h" +#include "exec/helper-proto.h" -enum { - TLBRET_XI = -6, - TLBRET_RI = -5, - TLBRET_DIRTY = -4, - TLBRET_INVALID = -3, - TLBRET_NOMATCH = -2, - TLBRET_BADADDR = -1, - TLBRET_MATCH = 0 -}; +/* TLB management */ +static void r4k_mips_tlb_flush_extra(CPUMIPSState *env, int first) +{ + /* Discard entries from env->tlb[first] onwards. */ + while (env->tlb->tlb_in_use > first) { + r4k_invalidate_tlb(env, --env->tlb->tlb_in_use, 0); + } +} + +static inline uint64_t get_tlb_pfn_from_entrylo(uint64_t entrylo) +{ +#if defined(TARGET_MIPS64) + return extract64(entrylo, 6, 54); +#else + return extract64(entrylo, 6, 24) | /* PFN */ + (extract64(entrylo, 32, 32) << 24); /* PFNX */ +#endif +} + +static void r4k_fill_tlb(CPUMIPSState *env, int idx) +{ + r4k_tlb_t *tlb; + uint64_t mask = env->CP0_PageMask >> (TARGET_PAGE_BITS + 1); + + /* XXX: detect conflicting TLBs and raise a MCHECK exception when needed */ + tlb = &env->tlb->mmu.r4k.tlb[idx]; + if (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) { + tlb->EHINV = 1; + return; + } + tlb->EHINV = 0; + tlb->VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + tlb->VPN &= env->SEGMask; +#endif + tlb->ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + tlb->MMID = env->CP0_MemoryMapID; + tlb->PageMask = env->CP0_PageMask; + tlb->G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + tlb->V0 = (env->CP0_EntryLo0 & 2) != 0; + tlb->D0 = (env->CP0_EntryLo0 & 4) != 0; + tlb->C0 = (env->CP0_EntryLo0 >> 3) & 0x7; + tlb->XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) & 1; + tlb->RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) & 1; + tlb->PFN[0] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo0) & ~mask) << 12; + tlb->V1 = (env->CP0_EntryLo1 & 2) != 0; + tlb->D1 = (env->CP0_EntryLo1 & 4) != 0; + tlb->C1 = (env->CP0_EntryLo1 >> 3) & 0x7; + tlb->XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) & 1; + tlb->RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) & 1; + tlb->PFN[1] = (get_tlb_pfn_from_entrylo(env->CP0_EntryLo1) & ~mask) << 12; +} + +static void r4k_helper_tlbinv(CPUMIPSState *env) +{ + bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID = env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID = mi ? MMID : (uint32_t) ASID; + for (idx = 0; idx < env->tlb->nb_tlb; idx++) { + tlb = &env->tlb->mmu.r4k.tlb[idx]; + tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; + if (!tlb->G && tlb_mmid == MMID) { + tlb->EHINV = 1; + } + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbinvf(CPUMIPSState *env) +{ + int idx; + + for (idx = 0; idx < env->tlb->nb_tlb; idx++) { + env->tlb->mmu.r4k.tlb[idx].EHINV = 1; + } + cpu_mips_tlb_flush(env); +} + +static void r4k_helper_tlbwi(CPUMIPSState *env) +{ + bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); + target_ulong VPN; + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID = env->CP0_MemoryMapID; + uint32_t tlb_mmid; + bool EHINV, G, V0, D0, V1, D1, XI0, XI1, RI0, RI1; + r4k_tlb_t *tlb; + int idx; + + MMID = mi ? MMID : (uint32_t) ASID; + + idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb = &env->tlb->mmu.r4k.tlb[idx]; + VPN = env->CP0_EntryHi & (TARGET_PAGE_MASK << 1); +#if defined(TARGET_MIPS64) + VPN &= env->SEGMask; +#endif + EHINV = (env->CP0_EntryHi & (1 << CP0EnHi_EHINV)) != 0; + G = env->CP0_EntryLo0 & env->CP0_EntryLo1 & 1; + V0 = (env->CP0_EntryLo0 & 2) != 0; + D0 = (env->CP0_EntryLo0 & 4) != 0; + XI0 = (env->CP0_EntryLo0 >> CP0EnLo_XI) &1; + RI0 = (env->CP0_EntryLo0 >> CP0EnLo_RI) &1; + V1 = (env->CP0_EntryLo1 & 2) != 0; + D1 = (env->CP0_EntryLo1 & 4) != 0; + XI1 = (env->CP0_EntryLo1 >> CP0EnLo_XI) &1; + RI1 = (env->CP0_EntryLo1 >> CP0EnLo_RI) &1; + + tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* + * Discard cached TLB entries, unless tlbwi is just upgrading access + * permissions on the current entry. + */ + if (tlb->VPN != VPN || tlb_mmid != MMID || tlb->G != G || + (!tlb->EHINV && EHINV) || + (tlb->V0 && !V0) || (tlb->D0 && !D0) || + (!tlb->XI0 && XI0) || (!tlb->RI0 && RI0) || + (tlb->V1 && !V1) || (tlb->D1 && !D1) || + (!tlb->XI1 && XI1) || (!tlb->RI1 && RI1)) { + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + } + + r4k_invalidate_tlb(env, idx, 0); + r4k_fill_tlb(env, idx); +} + +static void r4k_helper_tlbwr(CPUMIPSState *env) +{ + int r = cpu_mips_get_random(env); + + r4k_invalidate_tlb(env, r, 1); + r4k_fill_tlb(env, r); +} + +static void r4k_helper_tlbp(CPUMIPSState *env) +{ + bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); + r4k_tlb_t *tlb; + target_ulong mask; + target_ulong tag; + target_ulong VPN; + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID = env->CP0_MemoryMapID; + uint32_t tlb_mmid; + int i; + + MMID = mi ? MMID : (uint32_t) ASID; + for (i = 0; i < env->tlb->nb_tlb; i++) { + tlb = &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag = env->CP0_EntryHi & ~mask; + VPN = tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &= env->SEGMask; +#endif + tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag && !tlb->EHINV) { + /* TLB match */ + env->CP0_Index = i; + break; + } + } + if (i == env->tlb->nb_tlb) { + /* No match. Discard any shadow entries, if any of them match. */ + for (i = env->tlb->nb_tlb; i < env->tlb->tlb_in_use; i++) { + tlb = &env->tlb->mmu.r4k.tlb[i]; + /* 1k pages are not supported. */ + mask = tlb->PageMask | ~(TARGET_PAGE_MASK << 1); + tag = env->CP0_EntryHi & ~mask; + VPN = tlb->VPN & ~mask; +#if defined(TARGET_MIPS64) + tag &= env->SEGMask; +#endif + tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* Check ASID/MMID, virtual page number & size */ + if ((tlb->G == 1 || tlb_mmid == MMID) && VPN == tag) { + r4k_mips_tlb_flush_extra(env, i); + break; + } + } + + env->CP0_Index |= 0x80000000; + } +} + +static inline uint64_t get_entrylo_pfn_from_tlb(uint64_t tlb_pfn) +{ +#if defined(TARGET_MIPS64) + return tlb_pfn << 6; +#else + return (extract64(tlb_pfn, 0, 24) << 6) | /* PFN */ + (extract64(tlb_pfn, 24, 32) << 32); /* PFNX */ +#endif +} + +static void r4k_helper_tlbr(CPUMIPSState *env) +{ + bool mi = !!((env->CP0_Config5 >> CP0C5_MI) & 1); + uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; + uint32_t MMID = env->CP0_MemoryMapID; + uint32_t tlb_mmid; + r4k_tlb_t *tlb; + int idx; + + MMID = mi ? MMID : (uint32_t) ASID; + idx = (env->CP0_Index & ~0x80000000) % env->tlb->nb_tlb; + tlb = &env->tlb->mmu.r4k.tlb[idx]; + + tlb_mmid = mi ? tlb->MMID : (uint32_t) tlb->ASID; + /* If this will change the current ASID/MMID, flush qemu's TLB. */ + if (MMID != tlb_mmid) { + cpu_mips_tlb_flush(env); + } + + r4k_mips_tlb_flush_extra(env, env->tlb->nb_tlb); + + if (tlb->EHINV) { + env->CP0_EntryHi = 1 << CP0EnHi_EHINV; + env->CP0_PageMask = 0; + env->CP0_EntryLo0 = 0; + env->CP0_EntryLo1 = 0; + } else { + env->CP0_EntryHi = mi ? tlb->VPN : tlb->VPN | tlb->ASID; + env->CP0_MemoryMapID = tlb->MMID; + env->CP0_PageMask = tlb->PageMask; + env->CP0_EntryLo0 = tlb->G | (tlb->V0 << 1) | (tlb->D0 << 2) | + ((uint64_t)tlb->RI0 << CP0EnLo_RI) | + ((uint64_t)tlb->XI0 << CP0EnLo_XI) | (tlb->C0 << 3) | + get_entrylo_pfn_from_tlb(tlb->PFN[0] >> 12); + env->CP0_EntryLo1 = tlb->G | (tlb->V1 << 1) | (tlb->D1 << 2) | + ((uint64_t)tlb->RI1 << CP0EnLo_RI) | + ((uint64_t)tlb->XI1 << CP0EnLo_XI) | (tlb->C1 << 3) | + get_entrylo_pfn_from_tlb(tlb->PFN[1] >> 12); + } +} -#if !defined(CONFIG_USER_ONLY) +void helper_tlbwi(CPUMIPSState *env) +{ + env->tlb->helper_tlbwi(env); +} + +void helper_tlbwr(CPUMIPSState *env) +{ + env->tlb->helper_tlbwr(env); +} + +void helper_tlbp(CPUMIPSState *env) +{ + env->tlb->helper_tlbp(env); +} + +void helper_tlbr(CPUMIPSState *env) +{ + env->tlb->helper_tlbr(env); +} + +void helper_tlbinv(CPUMIPSState *env) +{ + env->tlb->helper_tlbinv(env); +} + +void helper_tlbinvf(CPUMIPSState *env) +{ + env->tlb->helper_tlbinvf(env); +} + +static void global_invalidate_tlb(CPUMIPSState *env, + uint32_t invMsgVPN2, + uint8_t invMsgR, + uint32_t invMsgMMid, + bool invAll, + bool invVAMMid, + bool invMMid, + bool invVA) +{ + + int idx; + r4k_tlb_t *tlb; + bool VAMatch; + bool MMidMatch; + + for (idx = 0; idx < env->tlb->nb_tlb; idx++) { + tlb = &env->tlb->mmu.r4k.tlb[idx]; + VAMatch = + (((tlb->VPN & ~tlb->PageMask) == (invMsgVPN2 & ~tlb->PageMask)) +#ifdef TARGET_MIPS64 + && + (extract64(env->CP0_EntryHi, 62, 2) == invMsgR) +#endif + ); + MMidMatch = tlb->MMID == invMsgMMid; + if ((invAll && (idx > env->CP0_Wired)) || + (VAMatch && invVAMMid && (tlb->G || MMidMatch)) || + (VAMatch && invVA) || + (MMidMatch && !(tlb->G) && invMMid)) { + tlb->EHINV = 1; + } + } + cpu_mips_tlb_flush(env); +} + +void helper_ginvt(CPUMIPSState *env, target_ulong arg, uint32_t type) +{ + bool invAll = type == 0; + bool invVA = type == 1; + bool invMMid = type == 2; + bool invVAMMid = type == 3; + uint32_t invMsgVPN2 = arg & (TARGET_PAGE_MASK << 1); + uint8_t invMsgR = 0; + uint32_t invMsgMMid = env->CP0_MemoryMapID; + CPUState *other_cs = first_cpu; + +#ifdef TARGET_MIPS64 + invMsgR = extract64(arg, 62, 2); +#endif + + CPU_FOREACH(other_cs) { + MIPSCPU *other_cpu = MIPS_CPU(other_cs); + global_invalidate_tlb(&other_cpu->env, invMsgVPN2, invMsgR, invMsgMMid, + invAll, invVAMMid, invMMid, invVA); + } +} /* no MMU emulation */ -int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, MMUAccessType access_type) { *physical = address; *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; @@ -47,8 +366,9 @@ int no_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, } /* fixed mapping MMU emulation */ -int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, + int *prot, target_ulong address, + MMUAccessType access_type) { if (address <= (int32_t)0x7FFFFFFFUL) { if (!(env->CP0_Status & (1 << CP0St_ERL))) { @@ -67,8 +387,8 @@ int fixed_mmu_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, } /* MIPS32/MIPS64 R4000-style MMU emulation */ -int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, - target_ulong address, MMUAccessType access_type) +static int r4k_map_address(CPUMIPSState *env, hwaddr *physical, int *prot, + target_ulong address, MMUAccessType access_type) { uint16_t ASID = env->CP0_EntryHi & env->CP0_EntryHi_ASID_mask; uint32_t MMID = env->CP0_MemoryMapID; @@ -166,236 +486,6 @@ void mmu_init(CPUMIPSState *env, const mips_def_t *def) } } -static int is_seg_am_mapped(unsigned int am, bool eu, int mmu_idx) -{ - /* - * Interpret access control mode and mmu_idx. - * AdE? TLB? - * AM K S U E K S U E - * UK 0 0 1 1 0 0 - - 0 - * MK 1 0 1 1 0 1 - - !eu - * MSK 2 0 0 1 0 1 1 - !eu - * MUSK 3 0 0 0 0 1 1 1 !eu - * MUSUK 4 0 0 0 0 0 1 1 0 - * USK 5 0 0 1 0 0 0 - 0 - * - 6 - - - - - - - - - * UUSK 7 0 0 0 0 0 0 0 0 - */ - int32_t adetlb_mask; - - switch (mmu_idx) { - case 3: /* ERL */ - /* If EU is set, always unmapped */ - if (eu) { - return 0; - } - /* fall through */ - case MIPS_HFLAG_KM: - /* Never AdE, TLB mapped if AM={1,2,3} */ - adetlb_mask = 0x70000000; - goto check_tlb; - - case MIPS_HFLAG_SM: - /* AdE if AM={0,1}, TLB mapped if AM={2,3,4} */ - adetlb_mask = 0xc0380000; - goto check_ade; - - case MIPS_HFLAG_UM: - /* AdE if AM={0,1,2,5}, TLB mapped if AM={3,4} */ - adetlb_mask = 0xe4180000; - /* fall through */ - check_ade: - /* does this AM cause AdE in current execution mode */ - if ((adetlb_mask << am) < 0) { - return TLBRET_BADADDR; - } - adetlb_mask <<= 8; - /* fall through */ - check_tlb: - /* is this AM mapped in current execution mode */ - return ((adetlb_mask << am) < 0); - default: - assert(0); - return TLBRET_BADADDR; - }; -} - -static int get_seg_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx, - unsigned int am, bool eu, - target_ulong segmask, - hwaddr physical_base) -{ - int mapped = is_seg_am_mapped(am, eu, mmu_idx); - - if (mapped < 0) { - /* is_seg_am_mapped can report TLBRET_BADADDR */ - return mapped; - } else if (mapped) { - /* The segment is TLB mapped */ - return env->tlb->map_address(env, physical, prot, real_address, - access_type); - } else { - /* The segment is unmapped */ - *physical = physical_base | (real_address & segmask); - *prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC; - return TLBRET_MATCH; - } -} - -static int get_segctl_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx, - uint16_t segctl, target_ulong segmask) -{ - unsigned int am = (segctl & CP0SC_AM_MASK) >> CP0SC_AM; - bool eu = (segctl >> CP0SC_EU) & 1; - hwaddr pa = ((hwaddr)segctl & CP0SC_PA_MASK) << 20; - - return get_seg_physical_address(env, physical, prot, real_address, - access_type, mmu_idx, am, eu, segmask, - pa & ~(hwaddr)segmask); -} - -static int get_physical_address(CPUMIPSState *env, hwaddr *physical, - int *prot, target_ulong real_address, - MMUAccessType access_type, int mmu_idx) -{ - /* User mode can only access useg/xuseg */ -#if defined(TARGET_MIPS64) - int user_mode = mmu_idx == MIPS_HFLAG_UM; - int supervisor_mode = mmu_idx == MIPS_HFLAG_SM; - int kernel_mode = !user_mode && !supervisor_mode; - int UX = (env->CP0_Status & (1 << CP0St_UX)) != 0; - int SX = (env->CP0_Status & (1 << CP0St_SX)) != 0; - int KX = (env->CP0_Status & (1 << CP0St_KX)) != 0; -#endif - int ret = TLBRET_MATCH; - /* effective address (modified for KVM T&E kernel segments) */ - target_ulong address = real_address; - -#define USEG_LIMIT ((target_ulong)(int32_t)0x7FFFFFFFUL) -#define KSEG0_BASE ((target_ulong)(int32_t)0x80000000UL) -#define KSEG1_BASE ((target_ulong)(int32_t)0xA0000000UL) -#define KSEG2_BASE ((target_ulong)(int32_t)0xC0000000UL) -#define KSEG3_BASE ((target_ulong)(int32_t)0xE0000000UL) - -#define KVM_KSEG0_BASE ((target_ulong)(int32_t)0x40000000UL) -#define KVM_KSEG2_BASE ((target_ulong)(int32_t)0x60000000UL) - - if (mips_um_ksegs_enabled()) { - /* KVM T&E adds guest kernel segments in useg */ - if (real_address >= KVM_KSEG0_BASE) { - if (real_address < KVM_KSEG2_BASE) { - /* kseg0 */ - address += KSEG0_BASE - KVM_KSEG0_BASE; - } else if (real_address <= USEG_LIMIT) { - /* kseg2/3 */ - address += KSEG2_BASE - KVM_KSEG2_BASE; - } - } - } - - if (address <= USEG_LIMIT) { - /* useg */ - uint16_t segctl; - - if (address >= 0x40000000UL) { - segctl = env->CP0_SegCtl2; - } else { - segctl = env->CP0_SegCtl2 >> 16; - } - ret = get_segctl_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, segctl, 0x3FFFFFFF); -#if defined(TARGET_MIPS64) - } else if (address < 0x4000000000000000ULL) { - /* xuseg */ - if (UX && address <= (0x3FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret = env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret = TLBRET_BADADDR; - } - } else if (address < 0x8000000000000000ULL) { - /* xsseg */ - if ((supervisor_mode || kernel_mode) && - SX && address <= (0x7FFFFFFFFFFFFFFFULL & env->SEGMask)) { - ret = env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret = TLBRET_BADADDR; - } - } else if (address < 0xC000000000000000ULL) { - /* xkphys */ - if ((address & 0x07FFFFFFFFFFFFFFULL) <= env->PAMask) { - /* KX/SX/UX bit to check for each xkphys EVA access mode */ - static const uint8_t am_ksux[8] = { - [CP0SC_AM_UK] = (1u << CP0St_KX), - [CP0SC_AM_MK] = (1u << CP0St_KX), - [CP0SC_AM_MSK] = (1u << CP0St_SX), - [CP0SC_AM_MUSK] = (1u << CP0St_UX), - [CP0SC_AM_MUSUK] = (1u << CP0St_UX), - [CP0SC_AM_USK] = (1u << CP0St_SX), - [6] = (1u << CP0St_KX), - [CP0SC_AM_UUSK] = (1u << CP0St_UX), - }; - unsigned int am = CP0SC_AM_UK; - unsigned int xr = (env->CP0_SegCtl2 & CP0SC2_XR_MASK) >> CP0SC2_XR; - - if (xr & (1 << ((address >> 59) & 0x7))) { - am = (env->CP0_SegCtl1 & CP0SC1_XAM_MASK) >> CP0SC1_XAM; - } - /* Does CP0_Status.KX/SX/UX permit the access mode (am) */ - if (env->CP0_Status & am_ksux[am]) { - ret = get_seg_physical_address(env, physical, prot, - real_address, access_type, - mmu_idx, am, false, env->PAMask, - 0); - } else { - ret = TLBRET_BADADDR; - } - } else { - ret = TLBRET_BADADDR; - } - } else if (address < 0xFFFFFFFF80000000ULL) { - /* xkseg */ - if (kernel_mode && KX && - address <= (0xFFFFFFFF7FFFFFFFULL & env->SEGMask)) { - ret = env->tlb->map_address(env, physical, prot, - real_address, access_type); - } else { - ret = TLBRET_BADADDR; - } -#endif - } else if (address < KSEG1_BASE) { - /* kseg0 */ - ret = get_segctl_physical_address(env, physical, prot, real_address, - access_type, mmu_idx, - env->CP0_SegCtl1 >> 16, 0x1FFFFFFF); - } else if (address < KSEG2_BASE) { - /* kseg1 */ - ret = get_segctl_physical_address(env, physical, prot, real_address, - access_type, mmu_idx, - env->CP0_SegCtl1, 0x1FFFFFFF); - } else if (address < KSEG3_BASE) { - /* sseg (kseg2) */ - ret = get_segctl_physical_address(env, physical, prot, real_address, - access_type, mmu_idx, - env->CP0_SegCtl0 >> 16, 0x1FFFFFFF); - } else { - /* - * kseg3 - * XXX: debug segment is not emulated - */ - ret = get_segctl_physical_address(env, physical, prot, real_address, - access_type, mmu_idx, - env->CP0_SegCtl0, 0x1FFFFFFF); - } - return ret; -} - void cpu_mips_tlb_flush(CPUMIPSState *env) { /* Flush qemu's TLB and discard all shadowed entries. */ @@ -403,8 +493,6 @@ void cpu_mips_tlb_flush(CPUMIPSState *env) env->tlb->tlb_in_use = env->tlb->nb_tlb; } -#endif /* !CONFIG_USER_ONLY */ - static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, MMUAccessType access_type, int tlb_error) { @@ -484,22 +572,6 @@ static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, env->error_code = error_code; } -#if !defined(CONFIG_USER_ONLY) - -hwaddr mips_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - hwaddr phys_addr; - int prot; - - if (get_physical_address(env, &phys_addr, &prot, addr, MMU_DATA_LOAD, - cpu_mmu_index(env, false)) != 0) { - return -1; - } - return phys_addr; -} - #if !defined(TARGET_MIPS64) /* @@ -833,7 +905,6 @@ refill: return true; } #endif -#endif /* !CONFIG_USER_ONLY */ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, MMUAccessType access_type, int mmu_idx, @@ -841,14 +912,11 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, { MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; -#if !defined(CONFIG_USER_ONLY) hwaddr physical; int prot; -#endif int ret = TLBRET_BADADDR; /* data access */ -#if !defined(CONFIG_USER_ONLY) /* XXX: put correct access by using cpu_restore_state() correctly */ ret = get_physical_address(env, &physical, &prot, address, access_type, mmu_idx); @@ -896,29 +964,28 @@ bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, if (probe) { return false; } -#endif raise_mmu_exception(env, address, access_type, ret); do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); } -#ifndef CONFIG_USER_ONLY hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, - MMUAccessType access_type) + MMUAccessType access_type, uintptr_t retaddr) { hwaddr physical; int prot; int ret = 0; + CPUState *cs = env_cpu(env); /* data access */ ret = get_physical_address(env, &physical, &prot, address, access_type, cpu_mmu_index(env, false)); - if (ret != TLBRET_MATCH) { - raise_mmu_exception(env, address, access_type, ret); - return -1LL; - } else { + if (ret == TLBRET_MATCH) { return physical; } + + raise_mmu_exception(env, address, access_type, ret); + cpu_loop_exit_restore(cs, retaddr); } static void set_hflags_for_handler(CPUMIPSState *env) @@ -964,11 +1031,8 @@ static inline void set_badinstr_registers(CPUMIPSState *env) } } -#endif /* !CONFIG_USER_ONLY */ - void mips_cpu_do_interrupt(CPUState *cs) { -#if !defined(CONFIG_USER_ONLY) MIPSCPU *cpu = MIPS_CPU(cs); CPUMIPSState *env = &cpu->env; bool update_badinstr = 0; @@ -1271,11 +1335,9 @@ void mips_cpu_do_interrupt(CPUState *cs) env->CP0_Status, env->CP0_Cause, env->CP0_BadVAddr, env->CP0_DEPC); } -#endif cs->exception_index = EXCP_NONE; } -#if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) { CPUState *cs = env_cpu(env); @@ -1340,4 +1402,3 @@ void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra) } } } -#endif /* !CONFIG_USER_ONLY */ diff --git a/target/mips/tcg/sysemu_helper.h.inc b/target/mips/tcg/sysemu_helper.h.inc new file mode 100644 index 0000000000..4353a966f9 --- /dev/null +++ b/target/mips/tcg/sysemu_helper.h.inc @@ -0,0 +1,185 @@ +/* + * QEMU MIPS sysemu helpers + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * Copyright (c) 2006 Marius Groeger (FPU operations) + * Copyright (c) 2006 Thiemo Seufer (MIPS32R2 support) + * Copyright (c) 2009 CodeSourcery (MIPS16 and microMIPS support) + * + * SPDX-License-Identifier: LGPL-2.1-or-later + */ + +DEF_HELPER_1(do_semihosting, void, env) + +/* CP0 helpers */ +DEF_HELPER_1(mfc0_mvpcontrol, tl, env) +DEF_HELPER_1(mfc0_mvpconf0, tl, env) +DEF_HELPER_1(mfc0_mvpconf1, tl, env) +DEF_HELPER_1(mftc0_vpecontrol, tl, env) +DEF_HELPER_1(mftc0_vpeconf0, tl, env) +DEF_HELPER_1(mfc0_random, tl, env) +DEF_HELPER_1(mfc0_tcstatus, tl, env) +DEF_HELPER_1(mftc0_tcstatus, tl, env) +DEF_HELPER_1(mfc0_tcbind, tl, env) +DEF_HELPER_1(mftc0_tcbind, tl, env) +DEF_HELPER_1(mfc0_tcrestart, tl, env) +DEF_HELPER_1(mftc0_tcrestart, tl, env) +DEF_HELPER_1(mfc0_tchalt, tl, env) +DEF_HELPER_1(mftc0_tchalt, tl, env) +DEF_HELPER_1(mfc0_tccontext, tl, env) +DEF_HELPER_1(mftc0_tccontext, tl, env) +DEF_HELPER_1(mfc0_tcschedule, tl, env) +DEF_HELPER_1(mftc0_tcschedule, tl, env) +DEF_HELPER_1(mfc0_tcschefback, tl, env) +DEF_HELPER_1(mftc0_tcschefback, tl, env) +DEF_HELPER_1(mfc0_count, tl, env) +DEF_HELPER_1(mfc0_saar, tl, env) +DEF_HELPER_1(mfhc0_saar, tl, env) +DEF_HELPER_1(mftc0_entryhi, tl, env) +DEF_HELPER_1(mftc0_status, tl, env) +DEF_HELPER_1(mftc0_cause, tl, env) +DEF_HELPER_1(mftc0_epc, tl, env) +DEF_HELPER_1(mftc0_ebase, tl, env) +DEF_HELPER_2(mftc0_configx, tl, env, tl) +DEF_HELPER_1(mfc0_lladdr, tl, env) +DEF_HELPER_1(mfc0_maar, tl, env) +DEF_HELPER_1(mfhc0_maar, tl, env) +DEF_HELPER_2(mfc0_watchlo, tl, env, i32) +DEF_HELPER_2(mfc0_watchhi, tl, env, i32) +DEF_HELPER_2(mfhc0_watchhi, tl, env, i32) +DEF_HELPER_1(mfc0_debug, tl, env) +DEF_HELPER_1(mftc0_debug, tl, env) +#ifdef TARGET_MIPS64 +DEF_HELPER_1(dmfc0_tcrestart, tl, env) +DEF_HELPER_1(dmfc0_tchalt, tl, env) +DEF_HELPER_1(dmfc0_tccontext, tl, env) +DEF_HELPER_1(dmfc0_tcschedule, tl, env) +DEF_HELPER_1(dmfc0_tcschefback, tl, env) +DEF_HELPER_1(dmfc0_lladdr, tl, env) +DEF_HELPER_1(dmfc0_maar, tl, env) +DEF_HELPER_2(dmfc0_watchlo, tl, env, i32) +DEF_HELPER_2(dmfc0_watchhi, tl, env, i32) +DEF_HELPER_1(dmfc0_saar, tl, env) +#endif /* TARGET_MIPS64 */ + +DEF_HELPER_2(mtc0_index, void, env, tl) +DEF_HELPER_2(mtc0_mvpcontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mttc0_vpecontrol, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mttc0_vpeconf0, void, env, tl) +DEF_HELPER_2(mtc0_vpeconf1, void, env, tl) +DEF_HELPER_2(mtc0_yqmask, void, env, tl) +DEF_HELPER_2(mtc0_vpeopt, void, env, tl) +DEF_HELPER_2(mtc0_entrylo0, void, env, tl) +DEF_HELPER_2(mtc0_tcstatus, void, env, tl) +DEF_HELPER_2(mttc0_tcstatus, void, env, tl) +DEF_HELPER_2(mtc0_tcbind, void, env, tl) +DEF_HELPER_2(mttc0_tcbind, void, env, tl) +DEF_HELPER_2(mtc0_tcrestart, void, env, tl) +DEF_HELPER_2(mttc0_tcrestart, void, env, tl) +DEF_HELPER_2(mtc0_tchalt, void, env, tl) +DEF_HELPER_2(mttc0_tchalt, void, env, tl) +DEF_HELPER_2(mtc0_tccontext, void, env, tl) +DEF_HELPER_2(mttc0_tccontext, void, env, tl) +DEF_HELPER_2(mtc0_tcschedule, void, env, tl) +DEF_HELPER_2(mttc0_tcschedule, void, env, tl) +DEF_HELPER_2(mtc0_tcschefback, void, env, tl) +DEF_HELPER_2(mttc0_tcschefback, void, env, tl) +DEF_HELPER_2(mtc0_entrylo1, void, env, tl) +DEF_HELPER_2(mtc0_context, void, env, tl) +DEF_HELPER_2(mtc0_memorymapid, void, env, tl) +DEF_HELPER_2(mtc0_pagemask, void, env, tl) +DEF_HELPER_2(mtc0_pagegrain, void, env, tl) +DEF_HELPER_2(mtc0_segctl0, void, env, tl) +DEF_HELPER_2(mtc0_segctl1, void, env, tl) +DEF_HELPER_2(mtc0_segctl2, void, env, tl) +DEF_HELPER_2(mtc0_pwfield, void, env, tl) +DEF_HELPER_2(mtc0_pwsize, void, env, tl) +DEF_HELPER_2(mtc0_wired, void, env, tl) +DEF_HELPER_2(mtc0_srsconf0, void, env, tl) +DEF_HELPER_2(mtc0_srsconf1, void, env, tl) +DEF_HELPER_2(mtc0_srsconf2, void, env, tl) +DEF_HELPER_2(mtc0_srsconf3, void, env, tl) +DEF_HELPER_2(mtc0_srsconf4, void, env, tl) +DEF_HELPER_2(mtc0_hwrena, void, env, tl) +DEF_HELPER_2(mtc0_pwctl, void, env, tl) +DEF_HELPER_2(mtc0_count, void, env, tl) +DEF_HELPER_2(mtc0_saari, void, env, tl) +DEF_HELPER_2(mtc0_saar, void, env, tl) +DEF_HELPER_2(mthc0_saar, void, env, tl) +DEF_HELPER_2(mtc0_entryhi, void, env, tl) +DEF_HELPER_2(mttc0_entryhi, void, env, tl) +DEF_HELPER_2(mtc0_compare, void, env, tl) +DEF_HELPER_2(mtc0_status, void, env, tl) +DEF_HELPER_2(mttc0_status, void, env, tl) +DEF_HELPER_2(mtc0_intctl, void, env, tl) +DEF_HELPER_2(mtc0_srsctl, void, env, tl) +DEF_HELPER_2(mtc0_cause, void, env, tl) +DEF_HELPER_2(mttc0_cause, void, env, tl) +DEF_HELPER_2(mtc0_ebase, void, env, tl) +DEF_HELPER_2(mttc0_ebase, void, env, tl) +DEF_HELPER_2(mtc0_config0, void, env, tl) +DEF_HELPER_2(mtc0_config2, void, env, tl) +DEF_HELPER_2(mtc0_config3, void, env, tl) +DEF_HELPER_2(mtc0_config4, void, env, tl) +DEF_HELPER_2(mtc0_config5, void, env, tl) +DEF_HELPER_2(mtc0_lladdr, void, env, tl) +DEF_HELPER_2(mtc0_maar, void, env, tl) +DEF_HELPER_2(mthc0_maar, void, env, tl) +DEF_HELPER_2(mtc0_maari, void, env, tl) +DEF_HELPER_3(mtc0_watchlo, void, env, tl, i32) +DEF_HELPER_3(mtc0_watchhi, void, env, tl, i32) +DEF_HELPER_3(mthc0_watchhi, void, env, tl, i32) +DEF_HELPER_2(mtc0_xcontext, void, env, tl) +DEF_HELPER_2(mtc0_framemask, void, env, tl) +DEF_HELPER_2(mtc0_debug, void, env, tl) +DEF_HELPER_2(mttc0_debug, void, env, tl) +DEF_HELPER_2(mtc0_performance0, void, env, tl) +DEF_HELPER_2(mtc0_errctl, void, env, tl) +DEF_HELPER_2(mtc0_taglo, void, env, tl) +DEF_HELPER_2(mtc0_datalo, void, env, tl) +DEF_HELPER_2(mtc0_taghi, void, env, tl) +DEF_HELPER_2(mtc0_datahi, void, env, tl) + +#if defined(TARGET_MIPS64) +DEF_HELPER_2(dmtc0_entrylo0, void, env, i64) +DEF_HELPER_2(dmtc0_entrylo1, void, env, i64) +#endif + +/* MIPS MT functions */ +DEF_HELPER_2(mftgpr, tl, env, i32) +DEF_HELPER_2(mftlo, tl, env, i32) +DEF_HELPER_2(mfthi, tl, env, i32) +DEF_HELPER_2(mftacx, tl, env, i32) +DEF_HELPER_1(mftdsp, tl, env) +DEF_HELPER_3(mttgpr, void, env, tl, i32) +DEF_HELPER_3(mttlo, void, env, tl, i32) +DEF_HELPER_3(mtthi, void, env, tl, i32) +DEF_HELPER_3(mttacx, void, env, tl, i32) +DEF_HELPER_2(mttdsp, void, env, tl) +DEF_HELPER_0(dmt, tl) +DEF_HELPER_0(emt, tl) +DEF_HELPER_1(dvpe, tl, env) +DEF_HELPER_1(evpe, tl, env) + +/* R6 Multi-threading */ +DEF_HELPER_1(dvp, tl, env) +DEF_HELPER_1(evp, tl, env) + +/* TLB */ +DEF_HELPER_1(tlbwi, void, env) +DEF_HELPER_1(tlbwr, void, env) +DEF_HELPER_1(tlbp, void, env) +DEF_HELPER_1(tlbr, void, env) +DEF_HELPER_1(tlbinv, void, env) +DEF_HELPER_1(tlbinvf, void, env) +DEF_HELPER_3(ginvt, void, env, tl, i32) + +/* Special */ +DEF_HELPER_1(di, tl, env) +DEF_HELPER_1(ei, tl, env) +DEF_HELPER_1(eret, void, env) +DEF_HELPER_1(eretnc, void, env) +DEF_HELPER_1(deret, void, env) +DEF_HELPER_3(cache, void, env, tl, i32) diff --git a/target/mips/tcg/tcg-internal.h b/target/mips/tcg/tcg-internal.h new file mode 100644 index 0000000000..81b14eb219 --- /dev/null +++ b/target/mips/tcg/tcg-internal.h @@ -0,0 +1,64 @@ +/* + * MIPS internal definitions and helpers (TCG accelerator) + * + * SPDX-License-Identifier: GPL-2.0-or-later + * + * This work is licensed under the terms of the GNU GPL, version 2 or later. + * See the COPYING file in the top-level directory. + */ + +#ifndef MIPS_TCG_INTERNAL_H +#define MIPS_TCG_INTERNAL_H + +#include "tcg/tcg.h" +#include "exec/memattrs.h" +#include "hw/core/cpu.h" +#include "cpu.h" + +void mips_tcg_init(void); + +void mips_cpu_synchronize_from_tb(CPUState *cs, const TranslationBlock *tb); +void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr); +void mips_cpu_do_unaligned_access(CPUState *cpu, vaddr addr, + MMUAccessType access_type, + int mmu_idx, uintptr_t retaddr); + +const char *mips_exception_name(int32_t exception); + +void QEMU_NORETURN do_raise_exception_err(CPUMIPSState *env, uint32_t exception, + int error_code, uintptr_t pc); + +static inline void QEMU_NORETURN do_raise_exception(CPUMIPSState *env, + uint32_t exception, + uintptr_t pc) +{ + do_raise_exception_err(env, exception, 0, pc); +} + +#if !defined(CONFIG_USER_ONLY) + +void mmu_init(CPUMIPSState *env, const mips_def_t *def); + +void update_pagemask(CPUMIPSState *env, target_ulong arg1, int32_t *pagemask); + +void r4k_invalidate_tlb(CPUMIPSState *env, int idx, int use_extra); +uint32_t cpu_mips_get_random(CPUMIPSState *env); + +bool mips_io_recompile_replay_branch(CPUState *cs, const TranslationBlock *tb); + +hwaddr cpu_mips_translate_address(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type, uintptr_t retaddr); +void mips_cpu_do_transaction_failed(CPUState *cs, hwaddr physaddr, + vaddr addr, unsigned size, + MMUAccessType access_type, + int mmu_idx, MemTxAttrs attrs, + MemTxResult response, uintptr_t retaddr); +void cpu_mips_tlb_flush(CPUMIPSState *env); + +#endif /* !CONFIG_USER_ONLY */ + +#endif diff --git a/target/mips/translate.c b/target/mips/tcg/translate.c index 71fa5ec197..c03a8ae1fe 100644 --- a/target/mips/translate.c +++ b/target/mips/tcg/translate.c @@ -39,6 +39,19 @@ #include "fpu_helper.h" #include "translate.h" +/* + * Many sysemu-only helpers are not reachable for user-only. + * Define stub generators here, so that we need not either sprinkle + * ifdefs through the translator, nor provide the helper function. + */ +#define STUB_HELPER(NAME, ...) \ + static inline void gen_helper_##NAME(__VA_ARGS__) \ + { g_assert_not_reached(); } + +#ifdef CONFIG_USER_ONLY +STUB_HELPER(cache, TCGv_env env, TCGv val, TCGv_i32 reg) +#endif + enum { /* indirect opcode tables */ OPC_SPECIAL = (0x00 << 26), @@ -1267,13 +1280,6 @@ TCGv_i64 fpu_f64[32]; #define DISAS_STOP DISAS_TARGET_0 #define DISAS_EXIT DISAS_TARGET_1 -static const char * const regnames[] = { - "r0", "at", "v0", "v1", "a0", "a1", "a2", "a3", - "t0", "t1", "t2", "t3", "t4", "t5", "t6", "t7", - "s0", "s1", "s2", "s3", "s4", "s5", "s6", "s7", - "t8", "t9", "k0", "k1", "gp", "sp", "s8", "ra", -}; - static const char * const regnames_HI[] = { "HI0", "HI1", "HI2", "HI3", }; @@ -1282,13 +1288,6 @@ static const char * const regnames_LO[] = { "LO0", "LO1", "LO2", "LO3", }; -static const char * const fregnames[] = { - "f0", "f1", "f2", "f3", "f4", "f5", "f6", "f7", - "f8", "f9", "f10", "f11", "f12", "f13", "f14", "f15", - "f16", "f17", "f18", "f19", "f20", "f21", "f22", "f23", - "f24", "f25", "f26", "f27", "f28", "f29", "f30", "f31", -}; - /* General purpose registers moves. */ void gen_load_gpr(TCGv t, int reg) { @@ -1572,11 +1571,13 @@ void gen_move_high32(TCGv ret, TCGv_i64 arg) #endif } -void check_cp0_enabled(DisasContext *ctx) +bool check_cp0_enabled(DisasContext *ctx) { if (unlikely(!(ctx->hflags & MIPS_HFLAG_CP0))) { generate_exception_end(ctx, EXCP_CpU); + return false; } + return true; } void check_cp1_enabled(DisasContext *ctx) @@ -5945,6 +5946,7 @@ static void gen_mthc0(DisasContext *ctx, TCGv arg, int reg, int sel) goto cp0_unimplemented; } trace_mips_translate_c0("mthc0", register_name, reg, sel); + return; cp0_unimplemented: qemu_log_mask(LOG_UNIMP, "mthc0 %s (reg %d sel %d)\n", @@ -18969,9 +18971,11 @@ static void gen_pool32axf_nanomips_insn(CPUMIPSState *env, DisasContext *ctx) } break; case NM_RDPGPR: + check_cp0_enabled(ctx); gen_load_srsgpr(rs, rt); break; case NM_WRPGPR: + check_cp0_enabled(ctx); gen_store_srsgpr(rs, rt); break; case NM_WAIT: @@ -20957,6 +20961,8 @@ static int decode_nanomips_32_48_opc(CPUMIPSState *env, DisasContext *ctx) gen_ld(ctx, OPC_LHUE, rt, rs, s); break; case NM_CACHEE: + check_eva(ctx); + check_cp0_enabled(ctx); check_nms_dl_il_sl_tl_l2c(ctx); gen_cache_operation(ctx, rt, rs, s); break; @@ -24530,11 +24536,11 @@ static void decode_opc_special3(CPUMIPSState *env, DisasContext *ctx) gen_st_cond(ctx, rt, rs, imm, MO_TESL, true); return; case OPC_CACHEE: + check_eva(ctx); check_cp0_enabled(ctx); if (ctx->hflags & MIPS_HFLAG_ITC_CACHE) { gen_cache_operation(ctx, rt, rs, imm); } - /* Treat as NOP. */ return; case OPC_PREFE: check_cp0_enabled(ctx); @@ -25593,83 +25599,6 @@ void gen_intermediate_code(CPUState *cs, TranslationBlock *tb, int max_insns) translator_loop(&mips_tr_ops, &ctx.base, cs, tb, max_insns); } -static void fpu_dump_state(CPUMIPSState *env, FILE * f, int flags) -{ - int i; - int is_fpu64 = !!(env->hflags & MIPS_HFLAG_F64); - -#define printfpr(fp) \ - do { \ - if (is_fpu64) \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu: %13g\n", \ - (fp)->w[FP_ENDIAN_IDX], (fp)->d, \ - (double)(fp)->fd, \ - (double)(fp)->fs[FP_ENDIAN_IDX], \ - (double)(fp)->fs[!FP_ENDIAN_IDX]); \ - else { \ - fpr_t tmp; \ - tmp.w[FP_ENDIAN_IDX] = (fp)->w[FP_ENDIAN_IDX]; \ - tmp.w[!FP_ENDIAN_IDX] = ((fp) + 1)->w[FP_ENDIAN_IDX]; \ - qemu_fprintf(f, "w:%08x d:%016" PRIx64 \ - " fd:%13g fs:%13g psu:%13g\n", \ - tmp.w[FP_ENDIAN_IDX], tmp.d, \ - (double)tmp.fd, \ - (double)tmp.fs[FP_ENDIAN_IDX], \ - (double)tmp.fs[!FP_ENDIAN_IDX]); \ - } \ - } while (0) - - - qemu_fprintf(f, - "CP1 FCR0 0x%08x FCR31 0x%08x SR.FR %d fp_status 0x%02x\n", - env->active_fpu.fcr0, env->active_fpu.fcr31, is_fpu64, - get_float_exception_flags(&env->active_fpu.fp_status)); - for (i = 0; i < 32; (is_fpu64) ? i++ : (i += 2)) { - qemu_fprintf(f, "%3s: ", fregnames[i]); - printfpr(&env->active_fpu.fpr[i]); - } - -#undef printfpr -} - -void mips_cpu_dump_state(CPUState *cs, FILE *f, int flags) -{ - MIPSCPU *cpu = MIPS_CPU(cs); - CPUMIPSState *env = &cpu->env; - int i; - - qemu_fprintf(f, "pc=0x" TARGET_FMT_lx " HI=0x" TARGET_FMT_lx - " LO=0x" TARGET_FMT_lx " ds %04x " - TARGET_FMT_lx " " TARGET_FMT_ld "\n", - env->active_tc.PC, env->active_tc.HI[0], env->active_tc.LO[0], - env->hflags, env->btarget, env->bcond); - for (i = 0; i < 32; i++) { - if ((i & 3) == 0) { - qemu_fprintf(f, "GPR%02d:", i); - } - qemu_fprintf(f, " %s " TARGET_FMT_lx, - regnames[i], env->active_tc.gpr[i]); - if ((i & 3) == 3) { - qemu_fprintf(f, "\n"); - } - } - - qemu_fprintf(f, "CP0 Status 0x%08x Cause 0x%08x EPC 0x" - TARGET_FMT_lx "\n", - env->CP0_Status, env->CP0_Cause, env->CP0_EPC); - qemu_fprintf(f, " Config0 0x%08x Config1 0x%08x LLAddr 0x%016" - PRIx64 "\n", - env->CP0_Config0, env->CP0_Config1, env->CP0_LLAddr); - qemu_fprintf(f, " Config2 0x%08x Config3 0x%08x\n", - env->CP0_Config2, env->CP0_Config3); - qemu_fprintf(f, " Config4 0x%08x Config5 0x%08x\n", - env->CP0_Config4, env->CP0_Config5); - if ((flags & CPU_DUMP_FPU) && (env->hflags & MIPS_HFLAG_FPU)) { - fpu_dump_state(env, f, flags); - } -} - void mips_tcg_init(void) { int i; diff --git a/target/mips/translate_addr_const.c b/target/mips/tcg/translate_addr_const.c index 96f483418e..96f483418e 100644 --- a/target/mips/translate_addr_const.c +++ b/target/mips/tcg/translate_addr_const.c diff --git a/target/mips/tx79.decode b/target/mips/tcg/tx79.decode index 0f748b53a6..0f748b53a6 100644 --- a/target/mips/tx79.decode +++ b/target/mips/tcg/tx79.decode diff --git a/target/mips/tx79_translate.c b/target/mips/tcg/tx79_translate.c index ad83774b97..ad83774b97 100644 --- a/target/mips/tx79_translate.c +++ b/target/mips/tcg/tx79_translate.c diff --git a/target/mips/txx9_translate.c b/target/mips/tcg/txx9_translate.c index 8a2c0b766b..8a2c0b766b 100644 --- a/target/mips/txx9_translate.c +++ b/target/mips/tcg/txx9_translate.c diff --git a/target/mips/tcg/user/meson.build b/target/mips/tcg/user/meson.build new file mode 100644 index 0000000000..79badcd321 --- /dev/null +++ b/target/mips/tcg/user/meson.build @@ -0,0 +1,3 @@ +mips_user_ss.add(files( + 'tlb_helper.c', +)) diff --git a/target/mips/tcg/user/tlb_helper.c b/target/mips/tcg/user/tlb_helper.c new file mode 100644 index 0000000000..b835144b82 --- /dev/null +++ b/target/mips/tcg/user/tlb_helper.c @@ -0,0 +1,64 @@ +/* + * MIPS TLB (Translation lookaside buffer) helpers. + * + * Copyright (c) 2004-2005 Jocelyn Mayer + * + * This library is free software; you can redistribute it and/or + * modify it under the terms of the GNU Lesser General Public + * License as published by the Free Software Foundation; either + * version 2.1 of the License, or (at your option) any later version. + * + * This library is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU + * Lesser General Public License for more details. + * + * You should have received a copy of the GNU Lesser General Public + * License along with this library; if not, see <http://www.gnu.org/licenses/>. + */ +#include "qemu/osdep.h" + +#include "cpu.h" +#include "exec/exec-all.h" +#include "internal.h" + +static void raise_mmu_exception(CPUMIPSState *env, target_ulong address, + MMUAccessType access_type) +{ + CPUState *cs = env_cpu(env); + + env->error_code = 0; + if (access_type == MMU_INST_FETCH) { + env->error_code |= EXCP_INST_NOTAVAIL; + } + + /* Reference to kernel address from user mode or supervisor mode */ + /* Reference to supervisor address from user mode */ + if (access_type == MMU_DATA_STORE) { + cs->exception_index = EXCP_AdES; + } else { + cs->exception_index = EXCP_AdEL; + } + + /* Raise exception */ + if (!(env->hflags & MIPS_HFLAG_DM)) { + env->CP0_BadVAddr = address; + } +} + +bool mips_cpu_tlb_fill(CPUState *cs, vaddr address, int size, + MMUAccessType access_type, int mmu_idx, + bool probe, uintptr_t retaddr) +{ + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + /* data access */ + raise_mmu_exception(env, address, access_type); + do_raise_exception_err(env, cs->exception_index, env->error_code, retaddr); +} + +void mips_cpu_do_interrupt(CPUState *cs) +{ + cs->exception_index = EXCP_NONE; +} diff --git a/target/mips/translate.h b/target/mips/translate.h index 2b3c7a69ec..6144259034 100644 --- a/target/mips/translate.h +++ b/target/mips/translate.h @@ -120,7 +120,12 @@ void gen_reserved_instruction(DisasContext *ctx); void check_insn(DisasContext *ctx, uint64_t flags); void check_mips_64(DisasContext *ctx); -void check_cp0_enabled(DisasContext *ctx); +/** + * check_cp0_enabled: + * Return %true if CP0 is enabled, otherwise return %false + * and emit a 'coprocessor unusable' exception. + */ +bool check_cp0_enabled(DisasContext *ctx); void check_cp1_enabled(DisasContext *ctx); void check_cp1_64bitmode(DisasContext *ctx); void check_cp1_registers(DisasContext *ctx, int regs); diff --git a/target/openrisc/sys_helper.c b/target/openrisc/sys_helper.c index 41390d046f..48674231e7 100644 --- a/target/openrisc/sys_helper.c +++ b/target/openrisc/sys_helper.c @@ -23,7 +23,6 @@ #include "exec/exec-all.h" #include "exec/helper-proto.h" #include "exception.h" -#include "sysemu/sysemu.h" #ifndef CONFIG_USER_ONLY #include "hw/boards.h" #endif diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c index 1eddcb94de..f0bbd73ca5 100644 --- a/target/riscv/op_helper.c +++ b/target/riscv/op_helper.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "cpu.h" #include "qemu/main-loop.h" #include "exec/exec-all.h" diff --git a/target/rx/helper.c b/target/rx/helper.c index 3e380a94fe..db6b07e389 100644 --- a/target/rx/helper.c +++ b/target/rx/helper.c @@ -21,7 +21,6 @@ #include "cpu.h" #include "exec/log.h" #include "exec/cpu_ldst.h" -#include "sysemu/sysemu.h" #include "hw/irq.h" void rx_cpu_unpack_psw(CPURXState *env, uint32_t psw, int rte) diff --git a/target/s390x/cpu.c b/target/s390x/cpu.c index d35eb39a1b..64455cf309 100644 --- a/target/s390x/cpu.c +++ b/target/s390x/cpu.c @@ -40,7 +40,6 @@ #include "hw/s390x/pv.h" #include "hw/boards.h" #include "sysemu/arch_init.h" -#include "sysemu/sysemu.h" #include "sysemu/tcg.h" #endif #include "fpu/softfloat-helpers.h" diff --git a/target/s390x/diag.c b/target/s390x/diag.c index 1a48429564..d620cd4bd4 100644 --- a/target/s390x/diag.c +++ b/target/s390x/diag.c @@ -15,7 +15,6 @@ #include "qemu/osdep.h" #include "cpu.h" #include "internal.h" -#include "exec/address-spaces.h" #include "hw/watchdog/wdt_diag288.h" #include "sysemu/cpus.h" #include "hw/s390x/ipl.h" diff --git a/target/s390x/excp_helper.c b/target/s390x/excp_helper.c index c48cd6b46f..20625c2c8f 100644 --- a/target/s390x/excp_helper.c +++ b/target/s390x/excp_helper.c @@ -29,7 +29,6 @@ #include "exec/address-spaces.h" #include "tcg_s390x.h" #ifndef CONFIG_USER_ONLY -#include "sysemu/sysemu.h" #include "hw/s390x/s390_flic.h" #include "hw/boards.h" #endif diff --git a/target/s390x/interrupt.c b/target/s390x/interrupt.c index 4cdbbc8849..9b4d08f2be 100644 --- a/target/s390x/interrupt.c +++ b/target/s390x/interrupt.c @@ -8,7 +8,6 @@ */ #include "qemu/osdep.h" -#include "qemu/log.h" #include "cpu.h" #include "kvm_s390x.h" #include "internal.h" diff --git a/target/xtensa/op_helper.c b/target/xtensa/op_helper.c index 143476849f..d85d3516d6 100644 --- a/target/xtensa/op_helper.c +++ b/target/xtensa/op_helper.c @@ -32,7 +32,6 @@ #include "qemu/host-utils.h" #include "exec/exec-all.h" #include "exec/cpu_ldst.h" -#include "exec/address-spaces.h" #include "qemu/timer.h" #ifndef CONFIG_USER_ONLY diff --git a/tcg/tcg-op-vec.c b/tcg/tcg-op-vec.c index d19aa7373e..15e026ae49 100644 --- a/tcg/tcg-op-vec.c +++ b/tcg/tcg-op-vec.c @@ -18,7 +18,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" #include "tcg/tcg-mo.h" diff --git a/tcg/tcg-op.c b/tcg/tcg-op.c index 70475773f4..dcc2ed0bbc 100644 --- a/tcg/tcg-op.c +++ b/tcg/tcg-op.c @@ -23,7 +23,6 @@ */ #include "qemu/osdep.h" -#include "cpu.h" #include "exec/exec-all.h" #include "tcg/tcg.h" #include "tcg/tcg-op.h" diff --git a/tcg/tcg.c b/tcg/tcg.c index 1fbe0b686d..db806a6658 100644 --- a/tcg/tcg.c +++ b/tcg/tcg.c @@ -41,7 +41,6 @@ CPU definitions. Currently they are used for qemu_ld/st instructions */ #define NO_CPU_IO_DEFS -#include "cpu.h" #include "exec/exec-all.h" @@ -64,7 +63,6 @@ #include "elf.h" #include "exec/log.h" -#include "sysemu/sysemu.h" /* Forward declarations for functions declared in tcg-target.c.inc and used here. */ diff --git a/tests/acceptance/boot_linux_console.py b/tests/acceptance/boot_linux_console.py index 1ca32ecf25..276a53f146 100644 --- a/tests/acceptance/boot_linux_console.py +++ b/tests/acceptance/boot_linux_console.py @@ -1010,6 +1010,74 @@ class BootLinuxConsole(LinuxKernelTest): self.vm.add_args('-dtb', self.workdir + '/day16/vexpress-v2p-ca9.dtb') self.do_test_advcal_2018('16', tar_hash, 'winter.zImage') + def test_arm_ast2400_palmetto_openbmc_v2_9_0(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:palmetto-bmc + """ + + image_url = ('https://github.com/openbmc/openbmc/releases/download/2.9.0/' + 'obmc-phosphor-image-palmetto.static.mtd') + image_hash = ('3e13bbbc28e424865dc42f35ad672b10f2e82cdb11846bb28fa625b48beafd0d') + image_path = self.fetch_asset(image_url, asset_hash=image_hash, + algorithm='sha256') + + self.do_test_arm_aspeed(image_path) + + def test_arm_ast2500_romulus_openbmc_v2_9_0(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:romulus-bmc + """ + + image_url = ('https://github.com/openbmc/openbmc/releases/download/2.9.0/' + 'obmc-phosphor-image-romulus.static.mtd') + image_hash = ('820341076803f1955bc31e647a512c79f9add4f5233d0697678bab4604c7bb25') + image_path = self.fetch_asset(image_url, asset_hash=image_hash, + algorithm='sha256') + + self.do_test_arm_aspeed(image_path) + + def do_test_arm_aspeed(self, image): + self.vm.set_console() + self.vm.add_args('-drive', 'file=' + image + ',if=mtd,format=raw', + '-net', 'nic') + self.vm.launch() + + self.wait_for_console_pattern("U-Boot 2016.07") + self.wait_for_console_pattern("## Loading kernel from FIT Image at 20080000") + self.wait_for_console_pattern("Starting kernel ...") + self.wait_for_console_pattern("Booting Linux on physical CPU 0x0") + self.wait_for_console_pattern( + "aspeed-smc 1e620000.spi: read control register: 203b0641") + self.wait_for_console_pattern("ftgmac100 1e660000.ethernet eth0: irq ") + self.wait_for_console_pattern("systemd[1]: Set hostname to") + + def test_arm_ast2600_debian(self): + """ + :avocado: tags=arch:arm + :avocado: tags=machine:tacoma-bmc + """ + deb_url = ('http://snapshot.debian.org/archive/debian/' + '20210302T203551Z/' + 'pool/main/l/linux/' + 'linux-image-5.10.0-3-armmp_5.10.13-1_armhf.deb') + deb_hash = 'db40d32fe39255d05482bea48d72467b67d6225bb2a2a4d6f618cb8976f1e09e' + deb_path = self.fetch_asset(deb_url, asset_hash=deb_hash, + algorithm='sha256') + kernel_path = self.extract_from_deb(deb_path, '/boot/vmlinuz-5.10.0-3-armmp') + dtb_path = self.extract_from_deb(deb_path, + '/usr/lib/linux-image-5.10.0-3-armmp/aspeed-bmc-opp-tacoma.dtb') + + self.vm.set_console() + self.vm.add_args('-kernel', kernel_path, + '-dtb', dtb_path, + '-net', 'nic') + self.vm.launch() + self.wait_for_console_pattern("Booting Linux on physical CPU 0xf00") + self.wait_for_console_pattern("SMP: Total of 2 processors activated") + self.wait_for_console_pattern("No filesystem could mount root") + def test_m68k_mcf5208evb(self): """ :avocado: tags=arch:m68k diff --git a/tests/qtest/aspeed_hace-test.c b/tests/qtest/aspeed_hace-test.c new file mode 100644 index 0000000000..09ee31545e --- /dev/null +++ b/tests/qtest/aspeed_hace-test.c @@ -0,0 +1,469 @@ +/* + * QTest testcase for the ASPEED Hash and Crypto Engine + * + * SPDX-License-Identifier: GPL-2.0-or-later + * Copyright 2021 IBM Corp. + */ + +#include "qemu/osdep.h" + +#include "libqos/libqtest.h" +#include "qemu-common.h" +#include "qemu/bitops.h" + +#define HACE_CMD 0x10 +#define HACE_SHA_BE_EN BIT(3) +#define HACE_MD5_LE_EN BIT(2) +#define HACE_ALGO_MD5 0 +#define HACE_ALGO_SHA1 BIT(5) +#define HACE_ALGO_SHA224 BIT(6) +#define HACE_ALGO_SHA256 (BIT(4) | BIT(6)) +#define HACE_ALGO_SHA512 (BIT(5) | BIT(6)) +#define HACE_ALGO_SHA384 (BIT(5) | BIT(6) | BIT(10)) +#define HACE_SG_EN BIT(18) + +#define HACE_STS 0x1c +#define HACE_RSA_ISR BIT(13) +#define HACE_CRYPTO_ISR BIT(12) +#define HACE_HASH_ISR BIT(9) +#define HACE_RSA_BUSY BIT(2) +#define HACE_CRYPTO_BUSY BIT(1) +#define HACE_HASH_BUSY BIT(0) +#define HACE_HASH_SRC 0x20 +#define HACE_HASH_DIGEST 0x24 +#define HACE_HASH_KEY_BUFF 0x28 +#define HACE_HASH_DATA_LEN 0x2c +#define HACE_HASH_CMD 0x30 +/* Scatter-Gather Hash */ +#define SG_LIST_LEN_LAST BIT(31) +struct AspeedSgList { + uint32_t len; + uint32_t addr; +} __attribute__ ((__packed__)); + +/* + * Test vector is the ascii "abc" + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abc' | dd of=/tmp/test + * for hash in sha512sum sha256sum md5sum; do $hash /tmp/test; done + * + */ +static const uint8_t test_vector[] = {0x61, 0x62, 0x63}; + +static const uint8_t test_result_sha512[] = { + 0xdd, 0xaf, 0x35, 0xa1, 0x93, 0x61, 0x7a, 0xba, 0xcc, 0x41, 0x73, 0x49, + 0xae, 0x20, 0x41, 0x31, 0x12, 0xe6, 0xfa, 0x4e, 0x89, 0xa9, 0x7e, 0xa2, + 0x0a, 0x9e, 0xee, 0xe6, 0x4b, 0x55, 0xd3, 0x9a, 0x21, 0x92, 0x99, 0x2a, + 0x27, 0x4f, 0xc1, 0xa8, 0x36, 0xba, 0x3c, 0x23, 0xa3, 0xfe, 0xeb, 0xbd, + 0x45, 0x4d, 0x44, 0x23, 0x64, 0x3c, 0xe8, 0x0e, 0x2a, 0x9a, 0xc9, 0x4f, + 0xa5, 0x4c, 0xa4, 0x9f}; + +static const uint8_t test_result_sha256[] = { + 0xba, 0x78, 0x16, 0xbf, 0x8f, 0x01, 0xcf, 0xea, 0x41, 0x41, 0x40, 0xde, + 0x5d, 0xae, 0x22, 0x23, 0xb0, 0x03, 0x61, 0xa3, 0x96, 0x17, 0x7a, 0x9c, + 0xb4, 0x10, 0xff, 0x61, 0xf2, 0x00, 0x15, 0xad}; + +static const uint8_t test_result_md5[] = { + 0x90, 0x01, 0x50, 0x98, 0x3c, 0xd2, 0x4f, 0xb0, 0xd6, 0x96, 0x3f, 0x7d, + 0x28, 0xe1, 0x7f, 0x72}; + +/* + * The Scatter-Gather Test vector is the ascii "abc" "def" "ghi", broken + * into blocks of 3 characters as shown + * + * Expected results were generated using command line utitiles: + * + * echo -n -e 'abcdefghijkl' | dd of=/tmp/test + * for hash in sha512sum sha256sum; do $hash /tmp/test; done + * + */ +static const uint8_t test_vector_sg1[] = {0x61, 0x62, 0x63, 0x64, 0x65, 0x66}; +static const uint8_t test_vector_sg2[] = {0x67, 0x68, 0x69}; +static const uint8_t test_vector_sg3[] = {0x6a, 0x6b, 0x6c}; + +static const uint8_t test_result_sg_sha512[] = { + 0x17, 0x80, 0x7c, 0x72, 0x8e, 0xe3, 0xba, 0x35, 0xe7, 0xcf, 0x7a, 0xf8, + 0x23, 0x11, 0x6d, 0x26, 0xe4, 0x1e, 0x5d, 0x4d, 0x6c, 0x2f, 0xf1, 0xf3, + 0x72, 0x0d, 0x3d, 0x96, 0xaa, 0xcb, 0x6f, 0x69, 0xde, 0x64, 0x2e, 0x63, + 0xd5, 0xb7, 0x3f, 0xc3, 0x96, 0xc1, 0x2b, 0xe3, 0x8b, 0x2b, 0xd5, 0xd8, + 0x84, 0x25, 0x7c, 0x32, 0xc8, 0xf6, 0xd0, 0x85, 0x4a, 0xe6, 0xb5, 0x40, + 0xf8, 0x6d, 0xda, 0x2e}; + +static const uint8_t test_result_sg_sha256[] = { + 0xd6, 0x82, 0xed, 0x4c, 0xa4, 0xd9, 0x89, 0xc1, 0x34, 0xec, 0x94, 0xf1, + 0x55, 0x1e, 0x1e, 0xc5, 0x80, 0xdd, 0x6d, 0x5a, 0x6e, 0xcd, 0xe9, 0xf3, + 0xd3, 0x5e, 0x6e, 0x4a, 0x71, 0x7f, 0xbd, 0xe4}; + + +static void write_regs(QTestState *s, uint32_t base, uint32_t src, + uint32_t length, uint32_t out, uint32_t method) +{ + qtest_writel(s, base + HACE_HASH_SRC, src); + qtest_writel(s, base + HACE_HASH_DIGEST, out); + qtest_writel(s, base + HACE_HASH_DATA_LEN, length); + qtest_writel(s, base + HACE_HASH_CMD, HACE_SHA_BE_EN | method); +} + +static void test_md5(const char *machine, const uint32_t base, + const uint32_t src_addr) + +{ + QTestState *s = qtest_init(machine); + + uint32_t digest_addr = src_addr + 0x01000000; + uint8_t digest[16] = {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_MD5); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_md5, sizeof(digest)); + + qtest_quit(s); +} + +static void test_sha256(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s = qtest_init(machine); + + const uint32_t digest_addr = src_addr + 0x1000000; + uint8_t digest[32] = {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA256); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sha256, sizeof(digest)); + + qtest_quit(s); +} + +static void test_sha512(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s = qtest_init(machine); + + const uint32_t digest_addr = src_addr + 0x1000000; + uint8_t digest[64] = {0}; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr, test_vector, sizeof(test_vector)); + + write_regs(s, base, src_addr, sizeof(test_vector), digest_addr, HACE_ALGO_SHA512); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sha512, sizeof(digest)); + + qtest_quit(s); +} + +static void test_sha256_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s = qtest_init(machine); + + const uint32_t src_addr_1 = src_addr + 0x1000000; + const uint32_t src_addr_2 = src_addr + 0x2000000; + const uint32_t src_addr_3 = src_addr + 0x3000000; + const uint32_t digest_addr = src_addr + 0x4000000; + uint8_t digest[32] = {0}; + struct AspeedSgList array[] = { + { cpu_to_le32(sizeof(test_vector_sg1)), + cpu_to_le32(src_addr_1) }, + { cpu_to_le32(sizeof(test_vector_sg2)), + cpu_to_le32(src_addr_2) }, + { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), + cpu_to_le32(src_addr_3) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA256 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha256, sizeof(digest)); + + qtest_quit(s); +} + +static void test_sha512_sg(const char *machine, const uint32_t base, + const uint32_t src_addr) +{ + QTestState *s = qtest_init(machine); + + const uint32_t src_addr_1 = src_addr + 0x1000000; + const uint32_t src_addr_2 = src_addr + 0x2000000; + const uint32_t src_addr_3 = src_addr + 0x3000000; + const uint32_t digest_addr = src_addr + 0x4000000; + uint8_t digest[64] = {0}; + struct AspeedSgList array[] = { + { cpu_to_le32(sizeof(test_vector_sg1)), + cpu_to_le32(src_addr_1) }, + { cpu_to_le32(sizeof(test_vector_sg2)), + cpu_to_le32(src_addr_2) }, + { cpu_to_le32(sizeof(test_vector_sg3) | SG_LIST_LEN_LAST), + cpu_to_le32(src_addr_3) }, + }; + + /* Check engine is idle, no busy or irq bits set */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Write test vector into memory */ + qtest_memwrite(s, src_addr_1, test_vector_sg1, sizeof(test_vector_sg1)); + qtest_memwrite(s, src_addr_2, test_vector_sg2, sizeof(test_vector_sg2)); + qtest_memwrite(s, src_addr_3, test_vector_sg3, sizeof(test_vector_sg3)); + qtest_memwrite(s, src_addr, array, sizeof(array)); + + write_regs(s, base, src_addr, + (sizeof(test_vector_sg1) + + sizeof(test_vector_sg2) + + sizeof(test_vector_sg3)), + digest_addr, HACE_ALGO_SHA512 | HACE_SG_EN); + + /* Check hash IRQ status is asserted */ + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0x00000200); + + /* Clear IRQ status and check status is deasserted */ + qtest_writel(s, base + HACE_STS, 0x00000200); + g_assert_cmphex(qtest_readl(s, base + HACE_STS), ==, 0); + + /* Read computed digest from memory */ + qtest_memread(s, digest_addr, digest, sizeof(digest)); + + /* Check result of computation */ + g_assert_cmpmem(digest, sizeof(digest), + test_result_sg_sha512, sizeof(digest)); + + qtest_quit(s); +} + +struct masks { + uint32_t src; + uint32_t dest; + uint32_t len; +}; + +static const struct masks ast2600_masks = { + .src = 0x7fffffff, + .dest = 0x7ffffff8, + .len = 0x0fffffff, +}; + +static const struct masks ast2500_masks = { + .src = 0x3fffffff, + .dest = 0x3ffffff8, + .len = 0x0fffffff, +}; + +static const struct masks ast2400_masks = { + .src = 0x0fffffff, + .dest = 0x0ffffff8, + .len = 0x0fffffff, +}; + +static void test_addresses(const char *machine, const uint32_t base, + const struct masks *expected) +{ + QTestState *s = qtest_init(machine); + + /* + * Check command mode is zero, meaning engine is in direct access mode, + * as this affects the masking behavior of the HASH_SRC register. + */ + g_assert_cmphex(qtest_readl(s, base + HACE_CMD), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); + + + /* Check that the address masking is correct */ + qtest_writel(s, base + HACE_HASH_SRC, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, expected->src); + + qtest_writel(s, base + HACE_HASH_DIGEST, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, expected->dest); + + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0xffffffff); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, expected->len); + + /* Reset to zero */ + qtest_writel(s, base + HACE_HASH_SRC, 0); + qtest_writel(s, base + HACE_HASH_DIGEST, 0); + qtest_writel(s, base + HACE_HASH_DATA_LEN, 0); + + /* Check that all bits are now zero */ + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_SRC), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DIGEST), ==, 0); + g_assert_cmphex(qtest_readl(s, base + HACE_HASH_DATA_LEN), ==, 0); + + qtest_quit(s); +} + +/* ast2600 */ +static void test_md5_ast2600(void) +{ + test_md5("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + +static void test_sha256_ast2600(void) +{ + test_sha256("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + +static void test_sha256_sg_ast2600(void) +{ + test_sha256_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + +static void test_sha512_ast2600(void) +{ + test_sha512("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + +static void test_sha512_sg_ast2600(void) +{ + test_sha512_sg("-machine ast2600-evb", 0x1e6d0000, 0x80000000); +} + +static void test_addresses_ast2600(void) +{ + test_addresses("-machine ast2600-evb", 0x1e6d0000, &ast2600_masks); +} + +/* ast2500 */ +static void test_md5_ast2500(void) +{ + test_md5("-machine ast2500-evb", 0x1e6e3000, 0x80000000); +} + +static void test_sha256_ast2500(void) +{ + test_sha256("-machine ast2500-evb", 0x1e6e3000, 0x80000000); +} + +static void test_sha512_ast2500(void) +{ + test_sha512("-machine ast2500-evb", 0x1e6e3000, 0x80000000); +} + +static void test_addresses_ast2500(void) +{ + test_addresses("-machine ast2500-evb", 0x1e6e3000, &ast2500_masks); +} + +/* ast2400 */ +static void test_md5_ast2400(void) +{ + test_md5("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); +} + +static void test_sha256_ast2400(void) +{ + test_sha256("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); +} + +static void test_sha512_ast2400(void) +{ + test_sha512("-machine palmetto-bmc", 0x1e6e3000, 0x40000000); +} + +static void test_addresses_ast2400(void) +{ + test_addresses("-machine palmetto-bmc", 0x1e6e3000, &ast2400_masks); +} + +int main(int argc, char **argv) +{ + g_test_init(&argc, &argv, NULL); + + qtest_add_func("ast2600/hace/addresses", test_addresses_ast2600); + qtest_add_func("ast2600/hace/sha512", test_sha512_ast2600); + qtest_add_func("ast2600/hace/sha256", test_sha256_ast2600); + qtest_add_func("ast2600/hace/md5", test_md5_ast2600); + + qtest_add_func("ast2600/hace/sha512_sg", test_sha512_sg_ast2600); + qtest_add_func("ast2600/hace/sha256_sg", test_sha256_sg_ast2600); + + qtest_add_func("ast2500/hace/addresses", test_addresses_ast2500); + qtest_add_func("ast2500/hace/sha512", test_sha512_ast2500); + qtest_add_func("ast2500/hace/sha256", test_sha256_ast2500); + qtest_add_func("ast2500/hace/md5", test_md5_ast2500); + + qtest_add_func("ast2400/hace/addresses", test_addresses_ast2400); + qtest_add_func("ast2400/hace/sha512", test_sha512_ast2400); + qtest_add_func("ast2400/hace/sha256", test_sha256_ast2400); + qtest_add_func("ast2400/hace/md5", test_md5_ast2400); + + return g_test_run(); +} diff --git a/tests/qtest/m25p80-test.c b/tests/qtest/aspeed_smc-test.c index f860cef5f0..87b40a0ef1 100644 --- a/tests/qtest/m25p80-test.c +++ b/tests/qtest/aspeed_smc-test.c @@ -367,12 +367,12 @@ int main(int argc, char **argv) "-drive file=%s,format=raw,if=mtd", tmp_path); - qtest_add_func("/m25p80/read_jedec", test_read_jedec); - qtest_add_func("/m25p80/erase_sector", test_erase_sector); - qtest_add_func("/m25p80/erase_all", test_erase_all); - qtest_add_func("/m25p80/write_page", test_write_page); - qtest_add_func("/m25p80/read_page_mem", test_read_page_mem); - qtest_add_func("/m25p80/write_page_mem", test_write_page_mem); + qtest_add_func("/ast2400/smc/read_jedec", test_read_jedec); + qtest_add_func("/ast2400/smc/erase_sector", test_erase_sector); + qtest_add_func("/ast2400/smc/erase_all", test_erase_all); + qtest_add_func("/ast2400/smc/write_page", test_write_page); + qtest_add_func("/ast2400/smc/read_page_mem", test_read_page_mem); + qtest_add_func("/ast2400/smc/write_page_mem", test_write_page_mem); ret = g_test_run(); diff --git a/tests/qtest/fuzz/fuzz.c b/tests/qtest/fuzz/fuzz.c index 496d11a231..04b70e114b 100644 --- a/tests/qtest/fuzz/fuzz.c +++ b/tests/qtest/fuzz/fuzz.c @@ -18,7 +18,6 @@ #include "qemu/datadir.h" #include "sysemu/qtest.h" #include "sysemu/runstate.h" -#include "sysemu/sysemu.h" #include "qemu/main-loop.h" #include "qemu/rcu.h" #include "tests/qtest/libqos/libqtest.h" diff --git a/tests/qtest/fuzz/generic_fuzz.c b/tests/qtest/fuzz/generic_fuzz.c index ae219540b4..cea7d4058e 100644 --- a/tests/qtest/fuzz/generic_fuzz.c +++ b/tests/qtest/fuzz/generic_fuzz.c @@ -19,11 +19,9 @@ #include "tests/qtest/libqos/pci-pc.h" #include "fuzz.h" #include "fork_fuzz.h" -#include "exec/address-spaces.h" #include "string.h" #include "exec/memory.h" #include "exec/ramblock.h" -#include "exec/address-spaces.h" #include "hw/qdev-core.h" #include "hw/pci/pci.h" #include "hw/boards.h" diff --git a/tests/qtest/fuzz/qos_fuzz.c b/tests/qtest/fuzz/qos_fuzz.c index cee1a2a60f..7a244c951e 100644 --- a/tests/qtest/fuzz/qos_fuzz.c +++ b/tests/qtest/fuzz/qos_fuzz.c @@ -21,8 +21,6 @@ #include "qapi/error.h" #include "qemu-common.h" #include "exec/memory.h" -#include "exec/address-spaces.h" -#include "sysemu/sysemu.h" #include "qemu/main-loop.h" #include "tests/qtest/libqos/libqtest.h" diff --git a/tests/qtest/meson.build b/tests/qtest/meson.build index 0c76738921..966bc93efa 100644 --- a/tests/qtest/meson.build +++ b/tests/qtest/meson.build @@ -161,16 +161,19 @@ qtests_npcm7xx = \ 'npcm7xx_timer-test', 'npcm7xx_watchdog_timer-test'] + \ (slirp.found() ? ['npcm7xx_emc-test'] : []) +qtests_aspeed = \ + ['aspeed_hace-test', + 'aspeed_smc-test'] qtests_arm = \ (config_all_devices.has_key('CONFIG_MPS2') ? ['sse-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_DUALTIMER') ? ['cmsdk-apb-dualtimer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_TIMER') ? ['cmsdk-apb-timer-test'] : []) + \ (config_all_devices.has_key('CONFIG_CMSDK_APB_WATCHDOG') ? ['cmsdk-apb-watchdog-test'] : []) + \ (config_all_devices.has_key('CONFIG_PFLASH_CFI02') ? ['pflash-cfi02-test'] : []) + \ + (config_all_devices.has_key('CONFIG_ASPEED_SOC') ? qtests_aspeed : []) + \ (config_all_devices.has_key('CONFIG_NPCM7XX') ? qtests_npcm7xx : []) + \ ['arm-cpu-features', 'microbit-test', - 'm25p80-test', 'test-arm-mptimer', 'boot-serial-test', 'hexloader-test'] diff --git a/ui/x_keymap.c b/ui/x_keymap.c index 555086fb6b..2ce7b89961 100644 --- a/ui/x_keymap.c +++ b/ui/x_keymap.c @@ -56,6 +56,7 @@ const guint16 *qemu_xkeymap_mapping_table(Display *dpy, size_t *maplen) { XkbDescPtr desc; const gchar *keycodes = NULL; + const guint16 *map; /* There is no easy way to determine what X11 server * and platform & keyboard driver is in use. Thus we @@ -83,21 +84,21 @@ const guint16 *qemu_xkeymap_mapping_table(Display *dpy, size_t *maplen) if (check_for_xwin(dpy)) { trace_xkeymap_keymap("xwin"); *maplen = qemu_input_map_xorgxwin_to_qcode_len; - return qemu_input_map_xorgxwin_to_qcode; + map = qemu_input_map_xorgxwin_to_qcode; } else if (check_for_xquartz(dpy)) { trace_xkeymap_keymap("xquartz"); *maplen = qemu_input_map_xorgxquartz_to_qcode_len; - return qemu_input_map_xorgxquartz_to_qcode; + map = qemu_input_map_xorgxquartz_to_qcode; } else if ((keycodes && g_str_has_prefix(keycodes, "evdev")) || (XKeysymToKeycode(dpy, XK_Page_Up) == 0x70)) { trace_xkeymap_keymap("evdev"); *maplen = qemu_input_map_xorgevdev_to_qcode_len; - return qemu_input_map_xorgevdev_to_qcode; + map = qemu_input_map_xorgevdev_to_qcode; } else if ((keycodes && g_str_has_prefix(keycodes, "xfree86")) || (XKeysymToKeycode(dpy, XK_Page_Up) == 0x63)) { trace_xkeymap_keymap("kbd"); *maplen = qemu_input_map_xorgkbd_to_qcode_len; - return qemu_input_map_xorgkbd_to_qcode; + map = qemu_input_map_xorgkbd_to_qcode; } else { trace_xkeymap_keymap("NULL"); g_warning("Unknown X11 keycode mapping '%s'.\n" @@ -109,6 +110,10 @@ const guint16 *qemu_xkeymap_mapping_table(Display *dpy, size_t *maplen) " - xprop -root\n" " - xdpyinfo\n", keycodes ? keycodes : "<null>"); - return NULL; + map = NULL; } + if (keycodes) { + XFree((void *)keycodes); + } + return map; } diff --git a/util/oslib-win32.c b/util/oslib-win32.c index f68b8012bb..1fc42ec0e3 100644 --- a/util/oslib-win32.c +++ b/util/oslib-win32.c @@ -34,7 +34,6 @@ #include <windows.h> #include "qemu-common.h" #include "qapi/error.h" -#include "sysemu/sysemu.h" #include "qemu/main-loop.h" #include "trace.h" #include "qemu/sockets.h" |