diff options
55 files changed, 467 insertions, 336 deletions
diff --git a/cpu-exec.c b/cpu-exec.c index bd93165209..3913de020b 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -317,10 +317,7 @@ volatile sig_atomic_t exit_request; int cpu_exec(CPUArchState *env) { CPUState *cpu = ENV_GET_CPU(env); -#if !(defined(CONFIG_USER_ONLY) && \ - (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X))) CPUClass *cc = CPU_GET_CLASS(cpu); -#endif #ifdef TARGET_I386 X86CPU *x86_cpu = X86_CPU(cpu); #endif @@ -355,36 +352,7 @@ int cpu_exec(CPUArchState *env) cpu->exit_request = 1; } -#if defined(TARGET_I386) - /* put eflags in CPU temporary format */ - CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); - env->df = 1 - (2 * ((env->eflags >> 10) & 1)); - CC_OP = CC_OP_EFLAGS; - env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); -#elif defined(TARGET_SPARC) -#elif defined(TARGET_M68K) - env->cc_op = CC_OP_FLAGS; - env->cc_dest = env->sr & 0xf; - env->cc_x = (env->sr >> 4) & 1; -#elif defined(TARGET_ALPHA) -#elif defined(TARGET_ARM) -#elif defined(TARGET_UNICORE32) -#elif defined(TARGET_PPC) - env->reserve_addr = -1; -#elif defined(TARGET_LM32) -#elif defined(TARGET_MICROBLAZE) -#elif defined(TARGET_MIPS) -#elif defined(TARGET_MOXIE) -#elif defined(TARGET_OPENRISC) -#elif defined(TARGET_SH4) -#elif defined(TARGET_CRIS) -#elif defined(TARGET_S390X) -#elif defined(TARGET_XTENSA) -#elif defined(TARGET_TRICORE) - /* XXXXX */ -#else -#error unsupported target CPU -#endif + cc->cpu_exec_enter(cpu); cpu->exception_index = -1; /* Calculate difference between guest clock and host clock. @@ -436,17 +404,12 @@ int cpu_exec(CPUArchState *env) cpu->exception_index = EXCP_DEBUG; cpu_loop_exit(cpu); } -#if defined(TARGET_ARM) || defined(TARGET_SPARC) || defined(TARGET_MIPS) || \ - defined(TARGET_PPC) || defined(TARGET_ALPHA) || defined(TARGET_CRIS) || \ - defined(TARGET_MICROBLAZE) || defined(TARGET_LM32) || \ - defined(TARGET_UNICORE32) || defined(TARGET_TRICORE) if (interrupt_request & CPU_INTERRUPT_HALT) { cpu->interrupt_request &= ~CPU_INTERRUPT_HALT; cpu->halted = 1; cpu->exception_index = EXCP_HLT; cpu_loop_exit(cpu); } -#endif #if defined(TARGET_I386) if (interrupt_request & CPU_INTERRUPT_INIT) { cpu_svm_check_intercept_param(env, SVM_EXIT_INIT, 0); @@ -459,257 +422,15 @@ int cpu_exec(CPUArchState *env) cpu_reset(cpu); } #endif -#if defined(TARGET_I386) -#if !defined(CONFIG_USER_ONLY) - if (interrupt_request & CPU_INTERRUPT_POLL) { - cpu->interrupt_request &= ~CPU_INTERRUPT_POLL; - apic_poll_irq(x86_cpu->apic_state); - } -#endif - if (interrupt_request & CPU_INTERRUPT_SIPI) { - do_cpu_sipi(x86_cpu); - } else if (env->hflags2 & HF2_GIF_MASK) { - if ((interrupt_request & CPU_INTERRUPT_SMI) && - !(env->hflags & HF_SMM_MASK)) { - cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, - 0); - cpu->interrupt_request &= ~CPU_INTERRUPT_SMI; - do_smm_enter(x86_cpu); - next_tb = 0; - } else if ((interrupt_request & CPU_INTERRUPT_NMI) && - !(env->hflags2 & HF2_NMI_MASK)) { - cpu->interrupt_request &= ~CPU_INTERRUPT_NMI; - env->hflags2 |= HF2_NMI_MASK; - do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); - next_tb = 0; - } else if (interrupt_request & CPU_INTERRUPT_MCE) { - cpu->interrupt_request &= ~CPU_INTERRUPT_MCE; - do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); - next_tb = 0; - } else if ((interrupt_request & CPU_INTERRUPT_HARD) && - (((env->hflags2 & HF2_VINTR_MASK) && - (env->hflags2 & HF2_HIF_MASK)) || - (!(env->hflags2 & HF2_VINTR_MASK) && - (env->eflags & IF_MASK && - !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { - int intno; - cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, - 0); - cpu->interrupt_request &= ~(CPU_INTERRUPT_HARD | - CPU_INTERRUPT_VIRQ); - intno = cpu_get_pic_interrupt(env); - qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing hardware INT=0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - /* ensure that no TB jump will be modified as - the program flow was changed */ - next_tb = 0; -#if !defined(CONFIG_USER_ONLY) - } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && - (env->eflags & IF_MASK) && - !(env->hflags & HF_INHIBIT_IRQ_MASK)) { - int intno; - /* FIXME: this should respect TPR */ - cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, - 0); - intno = ldl_phys(cpu->as, - env->vm_vmcb - + offsetof(struct vmcb, - control.int_vector)); - qemu_log_mask(CPU_LOG_TB_IN_ASM, "Servicing virtual hardware INT=0x%02x\n", intno); - do_interrupt_x86_hardirq(env, intno, 1); - cpu->interrupt_request &= ~CPU_INTERRUPT_VIRQ; - next_tb = 0; -#endif - } - } -#elif defined(TARGET_PPC) - if (interrupt_request & CPU_INTERRUPT_HARD) { - ppc_hw_interrupt(env); - if (env->pending_interrupts == 0) { - cpu->interrupt_request &= ~CPU_INTERRUPT_HARD; - } - next_tb = 0; - } -#elif defined(TARGET_LM32) - if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->ie & IE_IE)) { - cpu->exception_index = EXCP_IRQ; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_MICROBLAZE) - if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->sregs[SR_MSR] & MSR_IE) - && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) - && !(env->iflags & (D_FLAG | IMM_FLAG))) { - cpu->exception_index = EXCP_IRQ; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_MIPS) - if ((interrupt_request & CPU_INTERRUPT_HARD) && - cpu_mips_hw_interrupts_pending(env)) { - /* Raise it */ - cpu->exception_index = EXCP_EXT_INTERRUPT; - env->error_code = 0; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_TRICORE) - if ((interrupt_request & CPU_INTERRUPT_HARD)) { - cc->do_interrupt(cpu); - next_tb = 0; - } - -#elif defined(TARGET_OPENRISC) - { - int idx = -1; - if ((interrupt_request & CPU_INTERRUPT_HARD) - && (env->sr & SR_IEE)) { - idx = EXCP_INT; - } - if ((interrupt_request & CPU_INTERRUPT_TIMER) - && (env->sr & SR_TEE)) { - idx = EXCP_TICK; - } - if (idx >= 0) { - cpu->exception_index = idx; - cc->do_interrupt(cpu); - next_tb = 0; - } - } -#elif defined(TARGET_SPARC) - if (interrupt_request & CPU_INTERRUPT_HARD) { - if (cpu_interrupts_enabled(env) && - env->interrupt_index > 0) { - int pil = env->interrupt_index & 0xf; - int type = env->interrupt_index & 0xf0; - - if (((type == TT_EXTINT) && - cpu_pil_allowed(env, pil)) || - type != TT_EXTINT) { - cpu->exception_index = env->interrupt_index; - cc->do_interrupt(cpu); - next_tb = 0; - } - } - } -#elif defined(TARGET_ARM) - if (interrupt_request & CPU_INTERRUPT_FIQ - && !(env->daif & PSTATE_F)) { - cpu->exception_index = EXCP_FIQ; - cc->do_interrupt(cpu); - next_tb = 0; - } - /* ARMv7-M interrupt return works by loading a magic value - into the PC. On real hardware the load causes the - return to occur. The qemu implementation performs the - jump normally, then does the exception return when the - CPU tries to execute code at the magic address. - This will cause the magic PC value to be pushed to - the stack if an interrupt occurred at the wrong time. - We avoid this by disabling interrupts when - pc contains a magic address. */ - if (interrupt_request & CPU_INTERRUPT_HARD - && !(env->daif & PSTATE_I) - && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { - cpu->exception_index = EXCP_IRQ; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_UNICORE32) - if (interrupt_request & CPU_INTERRUPT_HARD - && !(env->uncached_asr & ASR_I)) { - cpu->exception_index = UC32_EXCP_INTR; - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_SH4) - if (interrupt_request & CPU_INTERRUPT_HARD) { - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_ALPHA) - { - int idx = -1; - /* ??? This hard-codes the OSF/1 interrupt levels. */ - switch (env->pal_mode ? 7 : env->ps & PS_INT_MASK) { - case 0 ... 3: - if (interrupt_request & CPU_INTERRUPT_HARD) { - idx = EXCP_DEV_INTERRUPT; - } - /* FALLTHRU */ - case 4: - if (interrupt_request & CPU_INTERRUPT_TIMER) { - idx = EXCP_CLK_INTERRUPT; - } - /* FALLTHRU */ - case 5: - if (interrupt_request & CPU_INTERRUPT_SMP) { - idx = EXCP_SMP_INTERRUPT; - } - /* FALLTHRU */ - case 6: - if (interrupt_request & CPU_INTERRUPT_MCHK) { - idx = EXCP_MCHK; - } - } - if (idx >= 0) { - cpu->exception_index = idx; - env->error_code = 0; - cc->do_interrupt(cpu); - next_tb = 0; - } - } -#elif defined(TARGET_CRIS) - if (interrupt_request & CPU_INTERRUPT_HARD - && (env->pregs[PR_CCS] & I_FLAG) - && !env->locked_irq) { - cpu->exception_index = EXCP_IRQ; - cc->do_interrupt(cpu); + /* The target hook has 3 exit conditions: + False when the interrupt isn't processed, + True when it is, and we should restart on a new TB, + and via longjmp via cpu_loop_exit. */ + if (cc->cpu_exec_interrupt(cpu, interrupt_request)) { next_tb = 0; } - if (interrupt_request & CPU_INTERRUPT_NMI) { - unsigned int m_flag_archval; - if (env->pregs[PR_VR] < 32) { - m_flag_archval = M_FLAG_V10; - } else { - m_flag_archval = M_FLAG_V32; - } - if ((env->pregs[PR_CCS] & m_flag_archval)) { - cpu->exception_index = EXCP_NMI; - cc->do_interrupt(cpu); - next_tb = 0; - } - } -#elif defined(TARGET_M68K) - if (interrupt_request & CPU_INTERRUPT_HARD - && ((env->sr & SR_I) >> SR_I_SHIFT) - < env->pending_level) { - /* Real hardware gets the interrupt vector via an - IACK cycle at this point. Current emulated - hardware doesn't rely on this, so we - provide/save the vector when the interrupt is - first signalled. */ - cpu->exception_index = env->pending_vector; - do_interrupt_m68k_hardirq(env); - next_tb = 0; - } -#elif defined(TARGET_S390X) && !defined(CONFIG_USER_ONLY) - if ((interrupt_request & CPU_INTERRUPT_HARD) && - (env->psw.mask & PSW_MASK_EXT)) { - cc->do_interrupt(cpu); - next_tb = 0; - } -#elif defined(TARGET_XTENSA) - if (interrupt_request & CPU_INTERRUPT_HARD) { - cpu->exception_index = EXC_IRQ; - cc->do_interrupt(cpu); - next_tb = 0; - } -#endif - /* Don't use the cached interrupt_request value, - do_interrupt may have updated the EXITTB flag. */ + /* Don't use the cached interrupt_request value, + do_interrupt may have updated the EXITTB flag. */ if (cpu->interrupt_request & CPU_INTERRUPT_EXITTB) { cpu->interrupt_request &= ~CPU_INTERRUPT_EXITTB; /* ensure that no TB jump will be modified as @@ -815,10 +536,7 @@ int cpu_exec(CPUArchState *env) * local variables as longjmp is marked 'noreturn'. */ cpu = current_cpu; env = cpu->env_ptr; -#if !(defined(CONFIG_USER_ONLY) && \ - (defined(TARGET_M68K) || defined(TARGET_PPC) || defined(TARGET_S390X))) cc = CPU_GET_CLASS(cpu); -#endif #ifdef TARGET_I386 x86_cpu = X86_CPU(cpu); #endif @@ -829,36 +547,7 @@ int cpu_exec(CPUArchState *env) } } /* for(;;) */ - -#if defined(TARGET_I386) - /* restore flags in standard format */ - env->eflags = env->eflags | cpu_cc_compute_all(env, CC_OP) - | (env->df & DF_MASK); -#elif defined(TARGET_ARM) - /* XXX: Save/restore host fpu exception state?. */ -#elif defined(TARGET_UNICORE32) -#elif defined(TARGET_SPARC) -#elif defined(TARGET_PPC) -#elif defined(TARGET_LM32) -#elif defined(TARGET_M68K) - cpu_m68k_flush_flags(env, env->cc_op); - env->cc_op = CC_OP_FLAGS; - env->sr = (env->sr & 0xffe0) - | env->cc_dest | (env->cc_x << 4); -#elif defined(TARGET_MICROBLAZE) -#elif defined(TARGET_MIPS) -#elif defined(TARGET_TRICORE) -#elif defined(TARGET_MOXIE) -#elif defined(TARGET_OPENRISC) -#elif defined(TARGET_SH4) -#elif defined(TARGET_ALPHA) -#elif defined(TARGET_CRIS) -#elif defined(TARGET_S390X) -#elif defined(TARGET_XTENSA) - /* XXXXX */ -#else -#error unsupported target CPU -#endif + cc->cpu_exec_exit(cpu); /* fail safe : never use current_cpu outside cpu_exec() */ current_cpu = NULL; diff --git a/include/qom/cpu.h b/include/qom/cpu.h index 370b3ebee9..f576b472fd 100644 --- a/include/qom/cpu.h +++ b/include/qom/cpu.h @@ -99,6 +99,9 @@ struct TranslationBlock; * @vmsd: State description for migration. * @gdb_num_core_regs: Number of core registers accessible to GDB. * @gdb_core_xml_file: File name for core registers GDB XML description. + * @cpu_exec_enter: Callback for cpu_exec preparation. + * @cpu_exec_exit: Callback for cpu_exec cleanup. + * @cpu_exec_interrupt: Callback for processing interrupts in cpu_exec. * * Represents a CPU family or model. */ @@ -149,6 +152,10 @@ typedef struct CPUClass { const struct VMStateDescription *vmsd; int gdb_num_core_regs; const char *gdb_core_xml_file; + + void (*cpu_exec_enter)(CPUState *cpu); + void (*cpu_exec_exit)(CPUState *cpu); + bool (*cpu_exec_interrupt)(CPUState *cpu, int interrupt_request); } CPUClass; #ifdef HOST_WORDS_BIGENDIAN diff --git a/main-loop.c b/main-loop.c index 53393a4b18..d2e64f1fa4 100644 --- a/main-loop.c +++ b/main-loop.c @@ -84,6 +84,9 @@ static int qemu_signal_init(void) sigaddset(&set, SIGIO); sigaddset(&set, SIGALRM); sigaddset(&set, SIGBUS); + sigaddset(&set, SIGINT); + sigaddset(&set, SIGHUP); + sigaddset(&set, SIGTERM); pthread_sigmask(SIG_BLOCK, &set, NULL); sigdelset(&set, SIG_IPI); diff --git a/qom/cpu.c b/qom/cpu.c index ba8b402617..0ec33377f2 100644 --- a/qom/cpu.c +++ b/qom/cpu.c @@ -202,10 +202,15 @@ static bool cpu_common_virtio_is_big_endian(CPUState *cpu) return target_words_bigendian(); } -static void cpu_common_debug_excp_handler(CPUState *cpu) +static void cpu_common_noop(CPUState *cpu) { } +static bool cpu_common_exec_interrupt(CPUState *cpu, int int_req) +{ + return false; +} + void cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags) { @@ -344,7 +349,10 @@ static void cpu_class_init(ObjectClass *klass, void *data) k->gdb_read_register = cpu_common_gdb_read_register; k->gdb_write_register = cpu_common_gdb_write_register; k->virtio_is_big_endian = cpu_common_virtio_is_big_endian; - k->debug_excp_handler = cpu_common_debug_excp_handler; + k->debug_excp_handler = cpu_common_noop; + k->cpu_exec_enter = cpu_common_noop; + k->cpu_exec_exit = cpu_common_noop; + k->cpu_exec_interrupt = cpu_common_exec_interrupt; dc->realize = cpu_common_realizefn; /* * Reason: CPUs still need special care by board code: wiring up diff --git a/target-alpha/cpu-qom.h b/target-alpha/cpu-qom.h index 0caa362f5b..b01c6c82eb 100644 --- a/target-alpha/cpu-qom.h +++ b/target-alpha/cpu-qom.h @@ -79,6 +79,7 @@ extern const struct VMStateDescription vmstate_alpha_cpu; #endif void alpha_cpu_do_interrupt(CPUState *cpu); +bool alpha_cpu_exec_interrupt(CPUState *cpu, int int_req); void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr alpha_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target-alpha/cpu.c b/target-alpha/cpu.c index 2491f0a301..a98b7d8d72 100644 --- a/target-alpha/cpu.c +++ b/target-alpha/cpu.c @@ -284,6 +284,7 @@ static void alpha_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = alpha_cpu_class_by_name; cc->has_work = alpha_cpu_has_work; cc->do_interrupt = alpha_cpu_do_interrupt; + cc->cpu_exec_interrupt = alpha_cpu_exec_interrupt; cc->dump_state = alpha_cpu_dump_state; cc->set_pc = alpha_cpu_set_pc; cc->gdb_read_register = alpha_cpu_gdb_read_register; diff --git a/target-alpha/helper.c b/target-alpha/helper.c index 7c053a3eae..a8aa782a2a 100644 --- a/target-alpha/helper.c +++ b/target-alpha/helper.c @@ -470,6 +470,50 @@ void alpha_cpu_do_interrupt(CPUState *cs) #endif /* !USER_ONLY */ } +bool alpha_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + AlphaCPU *cpu = ALPHA_CPU(cs); + CPUAlphaState *env = &cpu->env; + int idx = -1; + + /* We never take interrupts while in PALmode. */ + if (env->pal_mode) { + return false; + } + + /* Fall through the switch, collecting the highest priority + interrupt that isn't masked by the processor status IPL. */ + /* ??? This hard-codes the OSF/1 interrupt levels. */ + switch (env->ps & PS_INT_MASK) { + case 0 ... 3: + if (interrupt_request & CPU_INTERRUPT_HARD) { + idx = EXCP_DEV_INTERRUPT; + } + /* FALLTHRU */ + case 4: + if (interrupt_request & CPU_INTERRUPT_TIMER) { + idx = EXCP_CLK_INTERRUPT; + } + /* FALLTHRU */ + case 5: + if (interrupt_request & CPU_INTERRUPT_SMP) { + idx = EXCP_SMP_INTERRUPT; + } + /* FALLTHRU */ + case 6: + if (interrupt_request & CPU_INTERRUPT_MCHK) { + idx = EXCP_MCHK; + } + } + if (idx >= 0) { + cs->exception_index = idx; + env->error_code = 0; + alpha_cpu_do_interrupt(cs); + return true; + } + return false; +} + void alpha_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags) { diff --git a/target-arm/cpu-qom.h b/target-arm/cpu-qom.h index 07f3c9e866..96a3da9a8f 100644 --- a/target-arm/cpu-qom.h +++ b/target-arm/cpu-qom.h @@ -192,6 +192,7 @@ void init_cpreg_list(ARMCPU *cpu); void arm_cpu_do_interrupt(CPUState *cpu); void arm_v7m_cpu_do_interrupt(CPUState *cpu); +bool arm_cpu_exec_interrupt(CPUState *cpu, int int_req); void arm_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); diff --git a/target-arm/cpu.c b/target-arm/cpu.c index 7ea12bda1c..407f977742 100644 --- a/target-arm/cpu.c +++ b/target-arm/cpu.c @@ -188,6 +188,39 @@ static void arm_cpu_reset(CPUState *s) hw_watchpoint_update_all(cpu); } +bool arm_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc = CPU_GET_CLASS(cs); + ARMCPU *cpu = ARM_CPU(cs); + CPUARMState *env = &cpu->env; + bool ret = false; + + if (interrupt_request & CPU_INTERRUPT_FIQ + && !(env->daif & PSTATE_F)) { + cs->exception_index = EXCP_FIQ; + cc->do_interrupt(cs); + ret = true; + } + /* ARMv7-M interrupt return works by loading a magic value + into the PC. On real hardware the load causes the + return to occur. The qemu implementation performs the + jump normally, then does the exception return when the + CPU tries to execute code at the magic address. + This will cause the magic PC value to be pushed to + the stack if an interrupt occurred at the wrong time. + We avoid this by disabling interrupts when + pc contains a magic address. */ + if (interrupt_request & CPU_INTERRUPT_HARD + && !(env->daif & PSTATE_I) + && (!IS_M(env) || env->regs[15] < 0xfffffff0)) { + cs->exception_index = EXCP_IRQ; + cc->do_interrupt(cs); + ret = true; + } + + return ret; +} + #ifndef CONFIG_USER_ONLY static void arm_cpu_set_irq(void *opaque, int irq, int level) { @@ -1053,6 +1086,7 @@ static void arm_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = arm_cpu_class_by_name; cc->has_work = arm_cpu_has_work; cc->do_interrupt = arm_cpu_do_interrupt; + cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; cc->dump_state = arm_cpu_dump_state; cc->set_pc = arm_cpu_set_pc; cc->gdb_read_register = arm_cpu_gdb_read_register; diff --git a/target-arm/cpu64.c b/target-arm/cpu64.c index aa42803959..c30f47eca7 100644 --- a/target-arm/cpu64.c +++ b/target-arm/cpu64.c @@ -197,6 +197,7 @@ static void aarch64_cpu_class_init(ObjectClass *oc, void *data) CPUClass *cc = CPU_CLASS(oc); cc->do_interrupt = aarch64_cpu_do_interrupt; + cc->cpu_exec_interrupt = arm_cpu_exec_interrupt; cc->set_pc = aarch64_cpu_set_pc; cc->gdb_read_register = aarch64_cpu_gdb_read_register; cc->gdb_write_register = aarch64_cpu_gdb_write_register; diff --git a/target-cris/cpu-qom.h b/target-cris/cpu-qom.h index 75593667d6..6fc30c2084 100644 --- a/target-cris/cpu-qom.h +++ b/target-cris/cpu-qom.h @@ -75,6 +75,7 @@ static inline CRISCPU *cris_env_get_cpu(CPUCRISState *env) void cris_cpu_do_interrupt(CPUState *cpu); void crisv10_cpu_do_interrupt(CPUState *cpu); +bool cris_cpu_exec_interrupt(CPUState *cpu, int int_req); void cris_cpu_dump_state(CPUState *cs, FILE *f, fprintf_function cpu_fprintf, int flags); diff --git a/target-cris/cpu.c b/target-cris/cpu.c index 20d8809699..528e458aaa 100644 --- a/target-cris/cpu.c +++ b/target-cris/cpu.c @@ -279,6 +279,7 @@ static void cris_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = cris_cpu_class_by_name; cc->has_work = cris_cpu_has_work; cc->do_interrupt = cris_cpu_do_interrupt; + cc->cpu_exec_interrupt = cris_cpu_exec_interrupt; cc->dump_state = cris_cpu_dump_state; cc->set_pc = cris_cpu_set_pc; cc->gdb_read_register = cris_cpu_gdb_read_register; diff --git a/target-cris/helper.c b/target-cris/helper.c index e8b8261fe9..e901c3a008 100644 --- a/target-cris/helper.c +++ b/target-cris/helper.c @@ -283,3 +283,34 @@ hwaddr cris_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return phy; } #endif + +bool cris_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + CPUClass *cc = CPU_GET_CLASS(cs); + CRISCPU *cpu = CRIS_CPU(cs); + CPUCRISState *env = &cpu->env; + bool ret = false; + + if (interrupt_request & CPU_INTERRUPT_HARD + && (env->pregs[PR_CCS] & I_FLAG) + && !env->locked_irq) { + cs->exception_index = EXCP_IRQ; + cc->do_interrupt(cs); + ret = true; + } + if (interrupt_request & CPU_INTERRUPT_NMI) { + unsigned int m_flag_archval; + if (env->pregs[PR_VR] < 32) { + m_flag_archval = M_FLAG_V10; + } else { + m_flag_archval = M_FLAG_V32; + } + if ((env->pregs[PR_CCS] & m_flag_archval)) { + cs->exception_index = EXCP_NMI; + cc->do_interrupt(cs); + ret = true; + } + } + + return ret; +} diff --git a/target-i386/cpu-qom.h b/target-i386/cpu-qom.h index 77554663a7..b557b619cf 100644 --- a/target-i386/cpu-qom.h +++ b/target-i386/cpu-qom.h @@ -130,6 +130,7 @@ extern struct VMStateDescription vmstate_x86_cpu; * @cpu: vCPU the interrupt is to be handled by. */ void x86_cpu_do_interrupt(CPUState *cpu); +bool x86_cpu_exec_interrupt(CPUState *cpu, int int_req); int x86_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cpu, int cpuid, void *opaque); @@ -151,4 +152,7 @@ hwaddr x86_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int x86_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int x86_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void x86_cpu_exec_enter(CPUState *cpu); +void x86_cpu_exec_exit(CPUState *cpu); + #endif diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 90d0a05eb1..2406c727a5 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -2920,6 +2920,7 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) cc->parse_features = x86_cpu_parse_featurestr; cc->has_work = x86_cpu_has_work; cc->do_interrupt = x86_cpu_do_interrupt; + cc->cpu_exec_interrupt = x86_cpu_exec_interrupt; cc->dump_state = x86_cpu_dump_state; cc->set_pc = x86_cpu_set_pc; cc->synchronize_from_tb = x86_cpu_synchronize_from_tb; @@ -2942,6 +2943,8 @@ static void x86_cpu_common_class_init(ObjectClass *oc, void *data) #ifndef CONFIG_USER_ONLY cc->debug_excp_handler = breakpoint_handler; #endif + cc->cpu_exec_enter = x86_cpu_exec_enter; + cc->cpu_exec_exit = x86_cpu_exec_exit; } static const TypeInfo x86_cpu_type_info = { diff --git a/target-i386/helper.c b/target-i386/helper.c index 28fefe0a1f..345bda188d 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1262,3 +1262,24 @@ void do_cpu_sipi(X86CPU *cpu) { } #endif + +/* Frob eflags into and out of the CPU temporary format. */ + +void x86_cpu_exec_enter(CPUState *cs) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + + CC_SRC = env->eflags & (CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); + env->df = 1 - (2 * ((env->eflags >> 10) & 1)); + CC_OP = CC_OP_EFLAGS; + env->eflags &= ~(DF_MASK | CC_O | CC_S | CC_Z | CC_A | CC_P | CC_C); +} + +void x86_cpu_exec_exit(CPUState *cs) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + + env->eflags = cpu_compute_eflags(env); +} diff --git a/target-i386/seg_helper.c b/target-i386/seg_helper.c index 13eefbac3b..af5c1c6830 100644 --- a/target-i386/seg_helper.c +++ b/target-i386/seg_helper.c @@ -1279,6 +1279,75 @@ void do_interrupt_x86_hardirq(CPUX86State *env, int intno, int is_hw) do_interrupt_all(x86_env_get_cpu(env), intno, 0, 0, 0, is_hw); } +bool x86_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + X86CPU *cpu = X86_CPU(cs); + CPUX86State *env = &cpu->env; + bool ret = false; + +#if !defined(CONFIG_USER_ONLY) + if (interrupt_request & CPU_INTERRUPT_POLL) { + cs->interrupt_request &= ~CPU_INTERRUPT_POLL; + apic_poll_irq(cpu->apic_state); + } +#endif + if (interrupt_request & CPU_INTERRUPT_SIPI) { + do_cpu_sipi(cpu); + } else if (env->hflags2 & HF2_GIF_MASK) { + if ((interrupt_request & CPU_INTERRUPT_SMI) && + !(env->hflags & HF_SMM_MASK)) { + cpu_svm_check_intercept_param(env, SVM_EXIT_SMI, 0); + cs->interrupt_request &= ~CPU_INTERRUPT_SMI; + do_smm_enter(cpu); + ret = true; + } else if ((interrupt_request & CPU_INTERRUPT_NMI) && + !(env->hflags2 & HF2_NMI_MASK)) { + cs->interrupt_request &= ~CPU_INTERRUPT_NMI; + env->hflags2 |= HF2_NMI_MASK; + do_interrupt_x86_hardirq(env, EXCP02_NMI, 1); + ret = true; + } else if (interrupt_request & CPU_INTERRUPT_MCE) { + cs->interrupt_request &= ~CPU_INTERRUPT_MCE; + do_interrupt_x86_hardirq(env, EXCP12_MCHK, 0); + ret = true; + } else if ((interrupt_request & CPU_INTERRUPT_HARD) && + (((env->hflags2 & HF2_VINTR_MASK) && + (env->hflags2 & HF2_HIF_MASK)) || + (!(env->hflags2 & HF2_VINTR_MASK) && + (env->eflags & IF_MASK && + !(env->hflags & HF_INHIBIT_IRQ_MASK))))) { + int intno; + cpu_svm_check_intercept_param(env, SVM_EXIT_INTR, 0); + cs->interrupt_request &= ~(CPU_INTERRUPT_HARD | + CPU_INTERRUPT_VIRQ); + intno = cpu_get_pic_interrupt(env); + qemu_log_mask(CPU_LOG_TB_IN_ASM, + "Servicing hardware INT=0x%02x\n", intno); + do_interrupt_x86_hardirq(env, intno, 1); + /* ensure that no TB jump will be modified as + the program flow was changed */ + ret = true; +#if !defined(CONFIG_USER_ONLY) + } else if ((interrupt_request & CPU_INTERRUPT_VIRQ) && + (env->eflags & IF_MASK) && + !(env->hflags & HF_INHIBIT_IRQ_MASK)) { + int intno; + /* FIXME: this should respect TPR */ + cpu_svm_check_intercept_param(env, SVM_EXIT_VINTR, 0); + intno = ldl_phys(cs->as, env->vm_vmcb + + offsetof(struct vmcb, control.int_vector)); + qemu_log_mask(CPU_LOG_TB_IN_ASM, + "Servicing virtual hardware INT=0x%02x\n", intno); + do_interrupt_x86_hardirq(env, intno, 1); + cs->interrupt_request &= ~CPU_INTERRUPT_VIRQ; + ret = true; +#endif + } + } + + return ret; +} + void helper_enter_level(CPUX86State *env, int level, int data32, target_ulong t1) { diff --git a/target-lm32/cpu-qom.h b/target-lm32/cpu-qom.h index 9f15093879..77bc7b2686 100644 --- a/target-lm32/cpu-qom.h +++ b/target-lm32/cpu-qom.h @@ -82,6 +82,7 @@ extern const struct VMStateDescription vmstate_lm32_cpu; #endif void lm32_cpu_do_interrupt(CPUState *cpu); +bool lm32_cpu_exec_interrupt(CPUState *cs, int int_req); void lm32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr lm32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 419d664845..6c5de660dd 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -261,6 +261,7 @@ static void lm32_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = lm32_cpu_class_by_name; cc->has_work = lm32_cpu_has_work; cc->do_interrupt = lm32_cpu_do_interrupt; + cc->cpu_exec_interrupt = lm32_cpu_exec_interrupt; cc->dump_state = lm32_cpu_dump_state; cc->set_pc = lm32_cpu_set_pc; cc->gdb_read_register = lm32_cpu_gdb_read_register; diff --git a/target-lm32/helper.c b/target-lm32/helper.c index ad724aecbc..7a41f29730 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -202,6 +202,19 @@ void lm32_cpu_do_interrupt(CPUState *cs) } } +bool lm32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + LM32CPU *cpu = LM32_CPU(cs); + CPULM32State *env = &cpu->env; + + if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->ie & IE_IE)) { + cs->exception_index = EXCP_IRQ; + lm32_cpu_do_interrupt(cs); + return true; + } + return false; +} + LM32CPU *cpu_lm32_init(const char *cpu_model) { return LM32_CPU(cpu_generic_init(TYPE_LM32_CPU, cpu_model)); diff --git a/target-m68k/cpu-qom.h b/target-m68k/cpu-qom.h index 7f388eda68..c28e55d6b7 100644 --- a/target-m68k/cpu-qom.h +++ b/target-m68k/cpu-qom.h @@ -71,10 +71,14 @@ static inline M68kCPU *m68k_env_get_cpu(CPUM68KState *env) #define ENV_OFFSET offsetof(M68kCPU, env) void m68k_cpu_do_interrupt(CPUState *cpu); +bool m68k_cpu_exec_interrupt(CPUState *cpu, int int_req); void m68k_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr m68k_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); int m68k_cpu_gdb_read_register(CPUState *cpu, uint8_t *buf, int reg); int m68k_cpu_gdb_write_register(CPUState *cpu, uint8_t *buf, int reg); +void m68k_cpu_exec_enter(CPUState *cs); +void m68k_cpu_exec_exit(CPUState *cs); + #endif diff --git a/target-m68k/cpu.c b/target-m68k/cpu.c index c9cff19efc..4cfb7256c6 100644 --- a/target-m68k/cpu.c +++ b/target-m68k/cpu.c @@ -196,6 +196,7 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = m68k_cpu_class_by_name; cc->has_work = m68k_cpu_has_work; cc->do_interrupt = m68k_cpu_do_interrupt; + cc->cpu_exec_interrupt = m68k_cpu_exec_interrupt; cc->dump_state = m68k_cpu_dump_state; cc->set_pc = m68k_cpu_set_pc; cc->gdb_read_register = m68k_cpu_gdb_read_register; @@ -205,6 +206,9 @@ static void m68k_cpu_class_init(ObjectClass *c, void *data) #else cc->get_phys_page_debug = m68k_cpu_get_phys_page_debug; #endif + cc->cpu_exec_enter = m68k_cpu_exec_enter; + cc->cpu_exec_exit = m68k_cpu_exec_exit; + dc->vmsd = &vmstate_m68k_cpu; cc->gdb_num_core_regs = 18; cc->gdb_core_xml_file = "cf-core.xml"; diff --git a/target-m68k/cpu.h b/target-m68k/cpu.h index 6e4001d523..f67bbcc646 100644 --- a/target-m68k/cpu.h +++ b/target-m68k/cpu.h @@ -120,7 +120,6 @@ void m68k_tcg_init(void); void m68k_cpu_init_gdb(M68kCPU *cpu); M68kCPU *cpu_m68k_init(const char *cpu_model); int cpu_m68k_exec(CPUM68KState *s); -void do_interrupt_m68k_hardirq(CPUM68KState *env1); /* you can call this signal handler from your SIGBUS and SIGSEGV signal handlers to inform the virtual CPU of exceptions. non zero is returned if the signal was handled by the virtual CPU. */ diff --git a/target-m68k/helper.c b/target-m68k/helper.c index 8be9745697..77225a2005 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -864,3 +864,23 @@ void HELPER(set_mac_extu)(CPUM68KState *env, uint32_t val, uint32_t acc) res |= (uint64_t)(val & 0xffff0000) << 16; env->macc[acc + 1] = res; } + +void m68k_cpu_exec_enter(CPUState *cs) +{ + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + + env->cc_op = CC_OP_FLAGS; + env->cc_dest = env->sr & 0xf; + env->cc_x = (env->sr >> 4) & 1; +} + +void m68k_cpu_exec_exit(CPUState *cs) +{ + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + + cpu_m68k_flush_flags(env, env->cc_op); + env->cc_op = CC_OP_FLAGS; + env->sr = (env->sr & 0xffe0) | env->cc_dest | (env->cc_x << 4); +} diff --git a/target-m68k/op_helper.c b/target-m68k/op_helper.c index 9dd3e74ab8..06661f58ca 100644 --- a/target-m68k/op_helper.c +++ b/target-m68k/op_helper.c @@ -27,7 +27,7 @@ void m68k_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } -void do_interrupt_m68k_hardirq(CPUM68KState *env) +static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) { } @@ -141,12 +141,30 @@ void m68k_cpu_do_interrupt(CPUState *cs) do_interrupt_all(env, 0); } -void do_interrupt_m68k_hardirq(CPUM68KState *env) +static inline void do_interrupt_m68k_hardirq(CPUM68KState *env) { do_interrupt_all(env, 1); } #endif +bool m68k_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + M68kCPU *cpu = M68K_CPU(cs); + CPUM68KState *env = &cpu->env; + + if (interrupt_request & CPU_INTERRUPT_HARD + && ((env->sr & SR_I) >> SR_I_SHIFT) < env->pending_level) { + /* Real hardware gets the interrupt vector via an IACK cycle + at this point. Current emulated hardware doesn't rely on + this, so we provide/save the vector when the interrupt is + first signalled. */ + cs->exception_index = env->pending_vector; + do_interrupt_m68k_hardirq(env); + return true; + } + return false; +} + static void raise_exception(CPUM68KState *env, int tt) { CPUState *cs = CPU(m68k_env_get_cpu(env)); diff --git a/target-microblaze/cpu-qom.h b/target-microblaze/cpu-qom.h index 35a12b42a5..e3e070159f 100644 --- a/target-microblaze/cpu-qom.h +++ b/target-microblaze/cpu-qom.h @@ -72,6 +72,7 @@ static inline MicroBlazeCPU *mb_env_get_cpu(CPUMBState *env) #define ENV_OFFSET offsetof(MicroBlazeCPU, env) void mb_cpu_do_interrupt(CPUState *cs); +bool mb_cpu_exec_interrupt(CPUState *cs, int int_req); void mb_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr mb_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target-microblaze/cpu.c b/target-microblaze/cpu.c index 0379f2be2c..67e3182f70 100644 --- a/target-microblaze/cpu.c +++ b/target-microblaze/cpu.c @@ -169,6 +169,7 @@ static void mb_cpu_class_init(ObjectClass *oc, void *data) cc->has_work = mb_cpu_has_work; cc->do_interrupt = mb_cpu_do_interrupt; + cc->cpu_exec_interrupt = mb_cpu_exec_interrupt; cc->dump_state = mb_cpu_dump_state; cc->set_pc = mb_cpu_set_pc; cc->gdb_read_register = mb_cpu_gdb_read_register; diff --git a/target-microblaze/helper.c b/target-microblaze/helper.c index 59c9ad5aef..59466c9742 100644 --- a/target-microblaze/helper.c +++ b/target-microblaze/helper.c @@ -286,3 +286,19 @@ hwaddr mb_cpu_get_phys_page_debug(CPUState *cs, vaddr addr) return paddr; } #endif + +bool mb_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + MicroBlazeCPU *cpu = MICROBLAZE_CPU(cs); + CPUMBState *env = &cpu->env; + + if ((interrupt_request & CPU_INTERRUPT_HARD) + && (env->sregs[SR_MSR] & MSR_IE) + && !(env->sregs[SR_MSR] & (MSR_EIP | MSR_BIP)) + && !(env->iflags & (D_FLAG | IMM_FLAG))) { + cs->exception_index = EXCP_IRQ; + mb_cpu_do_interrupt(cs); + return true; + } + return false; +} diff --git a/target-mips/cpu-qom.h b/target-mips/cpu-qom.h index 2cff15a273..2ffc1bf3f2 100644 --- a/target-mips/cpu-qom.h +++ b/target-mips/cpu-qom.h @@ -75,6 +75,7 @@ static inline MIPSCPU *mips_env_get_cpu(CPUMIPSState *env) #define ENV_OFFSET offsetof(MIPSCPU, env) void mips_cpu_do_interrupt(CPUState *cpu); +bool mips_cpu_exec_interrupt(CPUState *cpu, int int_req); void mips_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr mips_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target-mips/cpu.c b/target-mips/cpu.c index b3e0e6cce7..5ed60f78a7 100644 --- a/target-mips/cpu.c +++ b/target-mips/cpu.c @@ -136,6 +136,7 @@ static void mips_cpu_class_init(ObjectClass *c, void *data) cc->has_work = mips_cpu_has_work; cc->do_interrupt = mips_cpu_do_interrupt; + cc->cpu_exec_interrupt = mips_cpu_exec_interrupt; cc->dump_state = mips_cpu_dump_state; cc->set_pc = mips_cpu_set_pc; cc->synchronize_from_tb = mips_cpu_synchronize_from_tb; diff --git a/target-mips/helper.c b/target-mips/helper.c index 8a997e44e5..fe16820885 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -675,6 +675,23 @@ void mips_cpu_do_interrupt(CPUState *cs) cs->exception_index = EXCP_NONE; } +bool mips_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + MIPSCPU *cpu = MIPS_CPU(cs); + CPUMIPSState *env = &cpu->env; + + if (cpu_mips_hw_interrupts_pending(env)) { + /* Raise it */ + cs->exception_index = EXCP_EXT_INTERRUPT; + env->error_code = 0; + mips_cpu_do_interrupt(cs); + return true; + } + } + return false; +} + #if !defined(CONFIG_USER_ONLY) void r4k_invalidate_tlb (CPUMIPSState *env, int idx, int use_extra) { diff --git a/target-openrisc/cpu.c b/target-openrisc/cpu.c index 08e724c126..39bedc108e 100644 --- a/target-openrisc/cpu.c +++ b/target-openrisc/cpu.c @@ -165,6 +165,7 @@ static void openrisc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = openrisc_cpu_class_by_name; cc->has_work = openrisc_cpu_has_work; cc->do_interrupt = openrisc_cpu_do_interrupt; + cc->cpu_exec_interrupt = openrisc_cpu_exec_interrupt; cc->dump_state = openrisc_cpu_dump_state; cc->set_pc = openrisc_cpu_set_pc; cc->gdb_read_register = openrisc_cpu_gdb_read_register; diff --git a/target-openrisc/cpu.h b/target-openrisc/cpu.h index 4512f459bf..69b96c6666 100644 --- a/target-openrisc/cpu.h +++ b/target-openrisc/cpu.h @@ -348,6 +348,7 @@ OpenRISCCPU *cpu_openrisc_init(const char *cpu_model); void cpu_openrisc_list(FILE *f, fprintf_function cpu_fprintf); int cpu_openrisc_exec(CPUOpenRISCState *s); void openrisc_cpu_do_interrupt(CPUState *cpu); +bool openrisc_cpu_exec_interrupt(CPUState *cpu, int int_req); void openrisc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr openrisc_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target-openrisc/interrupt.c b/target-openrisc/interrupt.c index 3de567eee8..e480cfd1b7 100644 --- a/target-openrisc/interrupt.c +++ b/target-openrisc/interrupt.c @@ -63,3 +63,23 @@ void openrisc_cpu_do_interrupt(CPUState *cs) cs->exception_index = -1; } + +bool openrisc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + OpenRISCCPU *cpu = OPENRISC_CPU(cs); + CPUOpenRISCState *env = &cpu->env; + int idx = -1; + + if ((interrupt_request & CPU_INTERRUPT_HARD) && (env->sr & SR_IEE)) { + idx = EXCP_INT; + } + if ((interrupt_request & CPU_INTERRUPT_TIMER) && (env->sr & SR_TEE)) { + idx = EXCP_TICK; + } + if (idx >= 0) { + cs->exception_index = idx; + openrisc_cpu_do_interrupt(cs); + return true; + } + return false; +} diff --git a/target-ppc/cpu-qom.h b/target-ppc/cpu-qom.h index a379f795bc..6967a8028b 100644 --- a/target-ppc/cpu-qom.h +++ b/target-ppc/cpu-qom.h @@ -113,6 +113,7 @@ PowerPCCPUClass *ppc_cpu_class_by_pvr(uint32_t pvr); PowerPCCPUClass *ppc_cpu_class_by_pvr_mask(uint32_t pvr); void ppc_cpu_do_interrupt(CPUState *cpu); +bool ppc_cpu_exec_interrupt(CPUState *cpu, int int_req); void ppc_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); void ppc_cpu_dump_statistics(CPUState *cpu, FILE *f, diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index b64c65295f..872456171f 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1147,7 +1147,6 @@ int cpu_ppc_exec (CPUPPCState *s); is returned if the signal was handled by the virtual CPU. */ int cpu_ppc_signal_handler (int host_signum, void *pinfo, void *puc); -void ppc_hw_interrupt (CPUPPCState *env); #if defined(CONFIG_USER_ONLY) int ppc_cpu_handle_mmu_fault(CPUState *cpu, vaddr address, int rw, int mmu_idx); diff --git a/target-ppc/excp_helper.c b/target-ppc/excp_helper.c index 922e86d54b..b803475060 100644 --- a/target-ppc/excp_helper.c +++ b/target-ppc/excp_helper.c @@ -48,7 +48,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) env->error_code = 0; } -void ppc_hw_interrupt(CPUPPCState *env) +static void ppc_hw_interrupt(CPUPPCState *env) { CPUState *cs = CPU(ppc_env_get_cpu(env)); @@ -692,7 +692,7 @@ void ppc_cpu_do_interrupt(CPUState *cs) powerpc_excp(cpu, env->excp_model, cs->exception_index); } -void ppc_hw_interrupt(CPUPPCState *env) +static void ppc_hw_interrupt(CPUPPCState *env) { PowerPCCPU *cpu = ppc_env_get_cpu(env); int hdice; @@ -820,6 +820,21 @@ void ppc_cpu_do_system_reset(CPUState *cs) } #endif /* !CONFIG_USER_ONLY */ +bool ppc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + if (interrupt_request & CPU_INTERRUPT_HARD) { + ppc_hw_interrupt(env); + if (env->pending_interrupts == 0) { + cs->interrupt_request &= ~CPU_INTERRUPT_HARD; + } + return true; + } + return false; +} + #if defined(DEBUG_OP) static void cpu_dump_rfi(target_ulong RA, target_ulong msr) { diff --git a/target-ppc/translate_init.c b/target-ppc/translate_init.c index 48177ed0a0..65b840da03 100644 --- a/target-ppc/translate_init.c +++ b/target-ppc/translate_init.c @@ -9456,6 +9456,14 @@ static bool ppc_cpu_has_work(CPUState *cs) return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD); } +static void ppc_cpu_exec_enter(CPUState *cs) +{ + PowerPCCPU *cpu = POWERPC_CPU(cs); + CPUPPCState *env = &cpu->env; + + env->reserve_addr = -1; +} + /* CPUClass::reset() */ static void ppc_cpu_reset(CPUState *s) { @@ -9623,6 +9631,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = ppc_cpu_class_by_name; cc->has_work = ppc_cpu_has_work; cc->do_interrupt = ppc_cpu_do_interrupt; + cc->cpu_exec_interrupt = ppc_cpu_exec_interrupt; cc->dump_state = ppc_cpu_dump_state; cc->dump_statistics = ppc_cpu_dump_statistics; cc->set_pc = ppc_cpu_set_pc; @@ -9638,6 +9647,7 @@ static void ppc_cpu_class_init(ObjectClass *oc, void *data) cc->write_elf64_qemunote = ppc64_cpu_write_elf64_qemunote; #endif #endif + cc->cpu_exec_enter = ppc_cpu_exec_enter; cc->gdb_num_core_regs = 71; diff --git a/target-s390x/cpu-qom.h b/target-s390x/cpu-qom.h index 80dd74142c..4f7d4cbe14 100644 --- a/target-s390x/cpu-qom.h +++ b/target-s390x/cpu-qom.h @@ -78,6 +78,7 @@ static inline S390CPU *s390_env_get_cpu(CPUS390XState *env) #define ENV_OFFSET offsetof(S390CPU, env) void s390_cpu_do_interrupt(CPUState *cpu); +bool s390_cpu_exec_interrupt(CPUState *cpu, int int_req); void s390_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); int s390_cpu_write_elf64_note(WriteCoreDumpFunction f, CPUState *cs, diff --git a/target-s390x/cpu.c b/target-s390x/cpu.c index 97a92168a8..2cfeb829a1 100644 --- a/target-s390x/cpu.c +++ b/target-s390x/cpu.c @@ -262,6 +262,7 @@ static void s390_cpu_class_init(ObjectClass *oc, void *data) cc->get_phys_page_debug = s390_cpu_get_phys_page_debug; cc->write_elf64_note = s390_cpu_write_elf64_note; cc->write_elf64_qemunote = s390_cpu_write_elf64_qemunote; + cc->cpu_exec_interrupt = s390_cpu_exec_interrupt; #endif dc->vmsd = &vmstate_s390_cpu; cc->gdb_num_core_regs = S390_NUM_CORE_REGS; diff --git a/target-s390x/helper.c b/target-s390x/helper.c index 67ab1065aa..e21afe6b46 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -876,4 +876,17 @@ void s390_cpu_do_interrupt(CPUState *cs) } } +bool s390_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + S390CPU *cpu = S390_CPU(cs); + CPUS390XState *env = &cpu->env; + + if (env->psw.mask & PSW_MASK_EXT) { + s390_cpu_do_interrupt(cs); + return true; + } + } + return false; +} #endif /* CONFIG_USER_ONLY */ diff --git a/target-sh4/cpu-qom.h b/target-sh4/cpu-qom.h index c04e78631b..6341238aa1 100644 --- a/target-sh4/cpu-qom.h +++ b/target-sh4/cpu-qom.h @@ -84,6 +84,7 @@ static inline SuperHCPU *sh_env_get_cpu(CPUSH4State *env) #define ENV_OFFSET offsetof(SuperHCPU, env) void superh_cpu_do_interrupt(CPUState *cpu); +bool superh_cpu_exec_interrupt(CPUState *cpu, int int_req); void superh_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr superh_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target-sh4/cpu.c b/target-sh4/cpu.c index e7f05212da..d187a2bdba 100644 --- a/target-sh4/cpu.c +++ b/target-sh4/cpu.c @@ -276,6 +276,7 @@ static void superh_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = superh_cpu_class_by_name; cc->has_work = superh_cpu_has_work; cc->do_interrupt = superh_cpu_do_interrupt; + cc->cpu_exec_interrupt = superh_cpu_exec_interrupt; cc->dump_state = superh_cpu_dump_state; cc->set_pc = superh_cpu_set_pc; cc->synchronize_from_tb = superh_cpu_synchronize_from_tb; diff --git a/target-sh4/helper.c b/target-sh4/helper.c index 9ebdd5c9b5..58113601ec 100644 --- a/target-sh4/helper.c +++ b/target-sh4/helper.c @@ -863,3 +863,12 @@ int cpu_sh4_is_cached(CPUSH4State * env, target_ulong addr) } #endif + +bool superh_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + superh_cpu_do_interrupt(cs); + return true; + } + return false; +} diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 3a0ee504e5..aa7626c1bf 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -70,6 +70,26 @@ static void sparc_cpu_reset(CPUState *s) env->cache_control = 0; } +static bool sparc_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + SPARCCPU *cpu = SPARC_CPU(cs); + CPUSPARCState *env = &cpu->env; + + if (cpu_interrupts_enabled(env) && env->interrupt_index > 0) { + int pil = env->interrupt_index & 0xf; + int type = env->interrupt_index & 0xf0; + + if (type != TT_EXTINT || cpu_pil_allowed(env, pil)) { + cs->exception_index = env->interrupt_index; + sparc_cpu_do_interrupt(cs); + return true; + } + } + } + return false; +} + static int cpu_sparc_register(SPARCCPU *cpu, const char *cpu_model) { CPUClass *cc = CPU_GET_CLASS(cpu); @@ -813,6 +833,7 @@ static void sparc_cpu_class_init(ObjectClass *oc, void *data) cc->parse_features = sparc_cpu_parse_features; cc->has_work = sparc_cpu_has_work; cc->do_interrupt = sparc_cpu_do_interrupt; + cc->cpu_exec_interrupt = sparc_cpu_exec_interrupt; cc->dump_state = sparc_cpu_dump_state; #if !defined(TARGET_SPARC64) && !defined(CONFIG_USER_ONLY) cc->memory_rw_debug = sparc_cpu_memory_rw_debug; diff --git a/target-tricore/cpu-qom.h b/target-tricore/cpu-qom.h index 470215ac9e..66c9664745 100644 --- a/target-tricore/cpu-qom.h +++ b/target-tricore/cpu-qom.h @@ -63,7 +63,6 @@ static inline TriCoreCPU *tricore_env_get_cpu(CPUTriCoreState *env) #define ENV_OFFSET offsetof(TriCoreCPU, env) hwaddr tricore_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); -void tricore_cpu_do_interrupt(CPUState *cpu); void tricore_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); diff --git a/target-tricore/cpu.c b/target-tricore/cpu.c index db9f404b44..7bf041afb9 100644 --- a/target-tricore/cpu.c +++ b/target-tricore/cpu.c @@ -145,7 +145,6 @@ static void tricore_cpu_class_init(ObjectClass *c, void *data) cc->class_by_name = tricore_cpu_class_by_name; cc->has_work = tricore_cpu_has_work; - cc->do_interrupt = tricore_cpu_do_interrupt; cc->dump_state = tricore_cpu_dump_state; cc->set_pc = tricore_cpu_set_pc; cc->synchronize_from_tb = tricore_cpu_synchronize_from_tb; diff --git a/target-tricore/cpu.h b/target-tricore/cpu.h index b036ff1159..7555b70a47 100644 --- a/target-tricore/cpu.h +++ b/target-tricore/cpu.h @@ -400,6 +400,4 @@ static inline void cpu_pc_from_tb(CPUTriCoreState *env, TranslationBlock *tb) env->PC = tb->pc; } -void do_interrupt(CPUTriCoreState *env); - #endif /*__TRICORE_CPU_H__ */ diff --git a/target-tricore/helper.c b/target-tricore/helper.c index e4af6f1ac2..f52504c9f8 100644 --- a/target-tricore/helper.c +++ b/target-tricore/helper.c @@ -82,10 +82,6 @@ int cpu_tricore_handle_mmu_fault(CPUState *cs, target_ulong address, return ret; } -void tricore_cpu_do_interrupt(CPUState *cs) -{ -} - TriCoreCPU *cpu_tricore_init(const char *cpu_model) { return TRICORE_CPU(cpu_generic_init(TYPE_TRICORE_CPU, cpu_model)); diff --git a/target-unicore32/cpu-qom.h b/target-unicore32/cpu-qom.h index f727760d9e..ea65b83318 100644 --- a/target-unicore32/cpu-qom.h +++ b/target-unicore32/cpu-qom.h @@ -61,6 +61,7 @@ static inline UniCore32CPU *uc32_env_get_cpu(CPUUniCore32State *env) #define ENV_OFFSET offsetof(UniCore32CPU, env) void uc32_cpu_do_interrupt(CPUState *cpu); +bool uc32_cpu_exec_interrupt(CPUState *cpu, int int_req); void uc32_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr uc32_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target-unicore32/cpu.c b/target-unicore32/cpu.c index 2d2c429a35..5b32987173 100644 --- a/target-unicore32/cpu.c +++ b/target-unicore32/cpu.c @@ -146,6 +146,7 @@ static void uc32_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = uc32_cpu_class_by_name; cc->has_work = uc32_cpu_has_work; cc->do_interrupt = uc32_cpu_do_interrupt; + cc->cpu_exec_interrupt = uc32_cpu_exec_interrupt; cc->dump_state = uc32_cpu_dump_state; cc->set_pc = uc32_cpu_set_pc; #ifdef CONFIG_USER_ONLY diff --git a/target-unicore32/helper.c b/target-unicore32/helper.c index e5ebbf4b18..b4654fa98a 100644 --- a/target-unicore32/helper.c +++ b/target-unicore32/helper.c @@ -250,3 +250,18 @@ int uc32_cpu_handle_mmu_fault(CPUState *cs, vaddr address, return 1; } #endif + +bool uc32_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + UniCore32CPU *cpu = UNICORE32_CPU(cs); + CPUUniCore32State *env = &cpu->env; + + if (!(env->uncached_asr & ASR_I)) { + cs->exception_index = UC32_EXCP_INTR; + uc32_cpu_do_interrupt(cs); + return true; + } + } + return false; +} diff --git a/target-xtensa/cpu-qom.h b/target-xtensa/cpu-qom.h index f320486a68..9de5c6eb9f 100644 --- a/target-xtensa/cpu-qom.h +++ b/target-xtensa/cpu-qom.h @@ -84,6 +84,7 @@ static inline XtensaCPU *xtensa_env_get_cpu(const CPUXtensaState *env) #define ENV_OFFSET offsetof(XtensaCPU, env) void xtensa_cpu_do_interrupt(CPUState *cpu); +bool xtensa_cpu_exec_interrupt(CPUState *cpu, int interrupt_request); void xtensa_cpu_dump_state(CPUState *cpu, FILE *f, fprintf_function cpu_fprintf, int flags); hwaddr xtensa_cpu_get_phys_page_debug(CPUState *cpu, vaddr addr); diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index 936d526d41..51c41d526d 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -142,6 +142,7 @@ static void xtensa_cpu_class_init(ObjectClass *oc, void *data) cc->class_by_name = xtensa_cpu_class_by_name; cc->has_work = xtensa_cpu_has_work; cc->do_interrupt = xtensa_cpu_do_interrupt; + cc->cpu_exec_interrupt = xtensa_cpu_exec_interrupt; cc->dump_state = xtensa_cpu_dump_state; cc->set_pc = xtensa_cpu_set_pc; cc->gdb_read_register = xtensa_cpu_gdb_read_register; diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 6671e40289..d84d259cf8 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -256,6 +256,16 @@ void xtensa_cpu_do_interrupt(CPUState *cs) check_interrupts(env); } +bool xtensa_cpu_exec_interrupt(CPUState *cs, int interrupt_request) +{ + if (interrupt_request & CPU_INTERRUPT_HARD) { + cs->exception_index = EXC_IRQ; + xtensa_cpu_do_interrupt(cs); + return true; + } + return false; +} + static void reset_tlb_mmu_all_ways(CPUXtensaState *env, const xtensa_tlb *tlb, xtensa_tlb_entry entry[][MAX_TLB_WAY_SIZE]) { |