diff options
| -rw-r--r-- | hw/apic.h | 5 | ||||
| -rw-r--r-- | hw/apic_common.c | 16 | ||||
| -rw-r--r-- | hw/pc.c | 9 | ||||
| -rw-r--r-- | target-i386/cpu.c | 16 | ||||
| -rw-r--r-- | target-i386/helper.c | 1 | ||||
| -rw-r--r-- | target-i386/kvm.c | 4 |
6 files changed, 36 insertions, 15 deletions
diff --git a/hw/apic.h b/hw/apic.h index a89542b231..1d48e027c3 100644 --- a/hw/apic.h +++ b/hw/apic.h @@ -21,9 +21,12 @@ void apic_sipi(DeviceState *s); void apic_handle_tpr_access_report(DeviceState *d, target_ulong ip, TPRAccess access); void apic_poll_irq(DeviceState *d); +void apic_designate_bsp(DeviceState *d); /* pc.c */ -int cpu_is_bsp(CPUX86State *env); DeviceState *cpu_get_current_apic(void); +/* cpu.c */ +bool cpu_is_bsp(X86CPU *cpu); + #endif diff --git a/hw/apic_common.c b/hw/apic_common.c index 60b82596e7..58e63b00da 100644 --- a/hw/apic_common.c +++ b/hw/apic_common.c @@ -43,8 +43,8 @@ uint64_t cpu_get_apic_base(DeviceState *d) trace_cpu_get_apic_base((uint64_t)s->apicbase); return s->apicbase; } else { - trace_cpu_get_apic_base(0); - return 0; + trace_cpu_get_apic_base(MSR_IA32_APICBASE_BSP); + return MSR_IA32_APICBASE_BSP; } } @@ -201,13 +201,23 @@ void apic_init_reset(DeviceState *d) s->timer_expiry = -1; } +void apic_designate_bsp(DeviceState *d) +{ + if (d == NULL) { + return; + } + + APICCommonState *s = APIC_COMMON(d); + s->apicbase |= MSR_IA32_APICBASE_BSP; +} + static void apic_reset_common(DeviceState *d) { APICCommonState *s = DO_UPCAST(APICCommonState, busdev.qdev, d); APICCommonClass *info = APIC_COMMON_GET_CLASS(s); bool bsp; - bsp = cpu_is_bsp(s->cpu_env); + bsp = cpu_is_bsp(x86_env_get_cpu(s->cpu_env)); s->apicbase = 0xfee00000 | (bsp ? MSR_IA32_APICBASE_BSP : 0) | MSR_IA32_APICBASE_ENABLE; diff --git a/hw/pc.c b/hw/pc.c index 598267af89..a920686cec 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -857,12 +857,6 @@ void pc_init_ne2k_isa(ISABus *bus, NICInfo *nd) nb_ne2k++; } -int cpu_is_bsp(CPUX86State *env) -{ - /* We hard-wire the BSP to the first CPU. */ - return env->cpu_index == 0; -} - DeviceState *cpu_get_current_apic(void) { if (cpu_single_env) { @@ -913,10 +907,7 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level) static void pc_cpu_reset(void *opaque) { X86CPU *cpu = opaque; - CPUX86State *env = &cpu->env; - cpu_reset(CPU(cpu)); - env->halted = !cpu_is_bsp(env); } static X86CPU *pc_new_cpu(const char *cpu_model) diff --git a/target-i386/cpu.c b/target-i386/cpu.c index 6b9659f9e7..365c2ffae9 100644 --- a/target-i386/cpu.c +++ b/target-i386/cpu.c @@ -1686,8 +1686,24 @@ static void x86_cpu_reset(CPUState *s) env->dr[7] = DR7_FIXED_1; cpu_breakpoint_remove_all(env, BP_CPU); cpu_watchpoint_remove_all(env, BP_CPU); + +#if !defined(CONFIG_USER_ONLY) + /* We hard-wire the BSP to the first CPU. */ + if (env->cpu_index == 0) { + apic_designate_bsp(env->apic_state); + } + + env->halted = !cpu_is_bsp(cpu); +#endif } +#ifndef CONFIG_USER_ONLY +bool cpu_is_bsp(X86CPU *cpu) +{ + return cpu_get_apic_base(cpu->env.apic_state) & MSR_IA32_APICBASE_BSP; +} +#endif + static void mce_init(X86CPU *cpu) { CPUX86State *cenv = &cpu->env; diff --git a/target-i386/helper.c b/target-i386/helper.c index d3af6eaf71..b748d90063 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -1191,7 +1191,6 @@ void do_cpu_init(X86CPU *cpu) env->interrupt_request = sipi; env->pat = pat; apic_init_reset(env->apic_state); - env->halted = !cpu_is_bsp(env); } void do_cpu_sipi(X86CPU *cpu) diff --git a/target-i386/kvm.c b/target-i386/kvm.c index e53c2f6bdf..4cfb3faf01 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -584,11 +584,13 @@ int kvm_arch_init_vcpu(CPUX86State *env) void kvm_arch_reset_vcpu(CPUX86State *env) { + X86CPU *cpu = x86_env_get_cpu(env); + env->exception_injected = -1; env->interrupt_injected = -1; env->xcr0 = 1; if (kvm_irqchip_in_kernel()) { - env->mp_state = cpu_is_bsp(env) ? KVM_MP_STATE_RUNNABLE : + env->mp_state = cpu_is_bsp(cpu) ? KVM_MP_STATE_RUNNABLE : KVM_MP_STATE_UNINITIALIZED; } else { env->mp_state = KVM_MP_STATE_RUNNABLE; |