diff options
73 files changed, 517 insertions, 390 deletions
diff --git a/bsd-user/main.c b/bsd-user/main.c index 0689e38fb8..cd33d655f5 100644 --- a/bsd-user/main.c +++ b/bsd-user/main.c @@ -918,7 +918,7 @@ int main(int argc, char **argv) exit(1); } #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) - cpu_state_reset(env); + cpu_reset(ENV_GET_CPU(env)); #endif thread_env = env; diff --git a/cpu-all.h b/cpu-all.h index 028528f0be..3a93c0c98a 100644 --- a/cpu-all.h +++ b/cpu-all.h @@ -443,7 +443,6 @@ void cpu_watchpoint_remove_all(CPUArchState *env, int mask); #define SSTEP_NOTIMER 0x4 /* Do not Timers while single stepping */ void cpu_single_step(CPUArchState *env, int enabled); -void cpu_state_reset(CPUArchState *s); int cpu_is_stopped(CPUArchState *env); void run_on_cpu(CPUArchState *env, void (*func)(void *data), void *data); diff --git a/cpu-exec.c b/cpu-exec.c index 0344cd5c59..83cac932ed 100644 --- a/cpu-exec.c +++ b/cpu-exec.c @@ -184,6 +184,9 @@ volatile sig_atomic_t exit_request; int cpu_exec(CPUArchState *env) { +#ifdef TARGET_PPC + CPUState *cpu = ENV_GET_CPU(env); +#endif int ret, interrupt_request; TranslationBlock *tb; uint8_t *tc_ptr; @@ -287,11 +290,11 @@ int cpu_exec(CPUArchState *env) #if defined(TARGET_I386) if (interrupt_request & CPU_INTERRUPT_INIT) { svm_check_intercept(env, SVM_EXIT_INIT); - do_cpu_init(env); + do_cpu_init(x86_env_get_cpu(env)); env->exception_index = EXCP_HALTED; cpu_loop_exit(env); } else if (interrupt_request & CPU_INTERRUPT_SIPI) { - do_cpu_sipi(env); + do_cpu_sipi(x86_env_get_cpu(env)); } else if (env->hflags2 & HF2_GIF_MASK) { if ((interrupt_request & CPU_INTERRUPT_SMI) && !(env->hflags & HF_SMM_MASK)) { @@ -341,7 +344,7 @@ int cpu_exec(CPUArchState *env) } #elif defined(TARGET_PPC) if ((interrupt_request & CPU_INTERRUPT_RESET)) { - cpu_state_reset(env); + cpu_reset(cpu); } if (interrupt_request & CPU_INTERRUPT_HARD) { ppc_hw_interrupt(env); diff --git a/hw/arm_boot.c b/hw/arm_boot.c index 7447f5c169..eb2d1760b0 100644 --- a/hw/arm_boot.c +++ b/hw/arm_boot.c @@ -274,10 +274,11 @@ static int load_dtb(target_phys_addr_t addr, const struct arm_boot_info *binfo) static void do_cpu_reset(void *opaque) { - CPUARMState *env = opaque; + ARMCPU *cpu = opaque; + CPUARMState *env = &cpu->env; const struct arm_boot_info *info = env->boot_info; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); if (info) { if (!info->is_linux) { /* Jump to the entry point. */ @@ -302,6 +303,7 @@ static void do_cpu_reset(void *opaque) void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info) { + ARMCPU *cpu; int kernel_size; int initrd_size; int n; @@ -406,7 +408,8 @@ void arm_load_kernel(CPUARMState *env, struct arm_boot_info *info) info->is_linux = is_linux; for (; env; env = env->next_cpu) { + cpu = arm_env_get_cpu(env); env->boot_info = info; - qemu_register_reset(do_cpu_reset, env); + qemu_register_reset(do_cpu_reset, cpu); } } diff --git a/hw/armv7m.c b/hw/armv7m.c index 4aac076e48..418139aa08 100644 --- a/hw/armv7m.c +++ b/hw/armv7m.c @@ -149,7 +149,9 @@ static void armv7m_bitband_init(void) static void armv7m_reset(void *opaque) { - cpu_state_reset((CPUARMState *)opaque); + ARMCPU *cpu = opaque; + + cpu_reset(CPU(cpu)); } /* Init CPU and memory for a v7-M based board. @@ -160,6 +162,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem, int flash_size, int sram_size, const char *kernel_filename, const char *cpu_model) { + ARMCPU *cpu; CPUARMState *env; DeviceState *nvic; /* FIXME: make this local state. */ @@ -177,13 +180,15 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem, flash_size *= 1024; sram_size *= 1024; - if (!cpu_model) + if (cpu_model == NULL) { cpu_model = "cortex-m3"; - env = cpu_init(cpu_model); - if (!env) { + } + cpu = cpu_arm_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + env = &cpu->env; #if 0 /* > 32Mb SRAM gets complicated because it overlaps the bitband area. @@ -241,7 +246,7 @@ qemu_irq *armv7m_init(MemoryRegion *address_space_mem, vmstate_register_ram_global(hack); memory_region_add_subregion(address_space_mem, 0xfffff000, hack); - qemu_register_reset(armv7m_reset, env); + qemu_register_reset(armv7m_reset, cpu); return pic; } diff --git a/hw/axis_dev88.c b/hw/axis_dev88.c index 2304e3533a..eab6327bed 100644 --- a/hw/axis_dev88.c +++ b/hw/axis_dev88.c @@ -247,6 +247,7 @@ void axisdev88_init (ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { + CRISCPU *cpu; CPUCRISState *env; DeviceState *dev; SysBusDevice *s; @@ -263,7 +264,8 @@ void axisdev88_init (ram_addr_t ram_size, if (cpu_model == NULL) { cpu_model = "crisv32"; } - env = cpu_init(cpu_model); + cpu = cpu_cris_init(cpu_model); + env = &cpu->env; /* allocate RAM */ memory_region_init_ram(phys_ram, "axisdev88.ram", ram_size); @@ -344,7 +346,7 @@ void axisdev88_init (ram_addr_t ram_size, li.image_filename = kernel_filename; li.cmdline = kernel_cmdline; - cris_load_image(env, &li); + cris_load_image(cpu, &li); } static QEMUMachine axisdev88_machine = { diff --git a/hw/cris-boot.c b/hw/cris-boot.c index ca6c52fa8e..b21326fade 100644 --- a/hw/cris-boot.c +++ b/hw/cris-boot.c @@ -29,12 +29,13 @@ static void main_cpu_reset(void *opaque) { - CPUCRISState *env = opaque; + CRISCPU *cpu = opaque; + CPUCRISState *env = &cpu->env; struct cris_load_info *li; li = env->load_info; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); if (!li) { /* nothing more to do. */ @@ -60,8 +61,9 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return addr - 0x80000000LL; } -void cris_load_image(CPUCRISState *env, struct cris_load_info *li) +void cris_load_image(CRISCPU *cpu, struct cris_load_info *li) { + CPUCRISState *env = &cpu->env; uint64_t entry, high; int kcmdline_len; int image_size; @@ -92,5 +94,5 @@ void cris_load_image(CPUCRISState *env, struct cris_load_info *li) } pstrcpy_targphys("cmdline", 0x40000000, 256, li->cmdline); } - qemu_register_reset(main_cpu_reset, env); + qemu_register_reset(main_cpu_reset, cpu); } diff --git a/hw/cris-boot.h b/hw/cris-boot.h index ecb9779e49..0a2c242411 100644 --- a/hw/cris-boot.h +++ b/hw/cris-boot.h @@ -8,4 +8,4 @@ struct cris_load_info target_phys_addr_t entry; }; -void cris_load_image(CPUCRISState *env, struct cris_load_info *li); +void cris_load_image(CRISCPU *cpu, struct cris_load_info *li); diff --git a/hw/leon3.c b/hw/leon3.c index 0a5ff165a1..878d3aa557 100644 --- a/hw/leon3.c +++ b/hw/leon3.c @@ -42,16 +42,16 @@ #define MAX_PILS 16 typedef struct ResetData { - CPUSPARCState *env; + SPARCCPU *cpu; uint32_t entry; /* save kernel entry in case of reset */ } ResetData; static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUSPARCState *env = s->env; + CPUSPARCState *env = &s->cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(s->cpu)); env->halted = 0; env->pc = s->entry; @@ -101,6 +101,7 @@ static void leon3_generic_hw_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { + SPARCCPU *cpu; CPUSPARCState *env; MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); @@ -117,17 +118,18 @@ static void leon3_generic_hw_init(ram_addr_t ram_size, cpu_model = "LEON3"; } - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_sparc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); exit(1); } + env = &cpu->env; cpu_sparc_set_id(env, 0); /* Reset data */ reset_info = g_malloc0(sizeof(ResetData)); - reset_info->env = env; + reset_info->cpu = cpu; qemu_register_reset(main_cpu_reset, reset_info); /* Allocate IRQ manager */ diff --git a/hw/lm32_boards.c b/hw/lm32_boards.c index 4dd4f0ab90..b76d8008be 100644 --- a/hw/lm32_boards.c +++ b/hw/lm32_boards.c @@ -31,7 +31,7 @@ #include "exec-memory.h" typedef struct { - CPULM32State *env; + LM32CPU *cpu; target_phys_addr_t bootstrap_pc; target_phys_addr_t flash_base; target_phys_addr_t hwsetup_base; @@ -54,9 +54,9 @@ static void cpu_irq_handler(void *opaque, int irq, int level) static void main_cpu_reset(void *opaque) { ResetInfo *reset_info = opaque; - CPULM32State *env = reset_info->env; + CPULM32State *env = &reset_info->cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(reset_info->cpu)); /* init defaults */ env->pc = (uint32_t)reset_info->bootstrap_pc; @@ -75,6 +75,7 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { + LM32CPU *cpu; CPULM32State *env; DriveInfo *dinfo; MemoryRegion *address_space_mem = get_system_memory(); @@ -101,8 +102,9 @@ static void lm32_evr_init(ram_addr_t ram_size_not_used, if (cpu_model == NULL) { cpu_model = "lm32-full"; } - env = cpu_init(cpu_model); - reset_info->env = env; + cpu = cpu_lm32_init(cpu_model); + env = &cpu->env; + reset_info->cpu = cpu; reset_info->flash_base = flash_base; @@ -163,6 +165,7 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { + LM32CPU *cpu; CPULM32State *env; DriveInfo *dinfo; MemoryRegion *address_space_mem = get_system_memory(); @@ -196,8 +199,9 @@ static void lm32_uclinux_init(ram_addr_t ram_size_not_used, if (cpu_model == NULL) { cpu_model = "lm32-full"; } - env = cpu_init(cpu_model); - reset_info->env = env; + cpu = cpu_lm32_init(cpu_model); + env = &cpu->env; + reset_info->cpu = cpu; reset_info->flash_base = flash_base; diff --git a/hw/mainstone.c b/hw/mainstone.c index 27f59009f6..00a8adc850 100644 --- a/hw/mainstone.c +++ b/hw/mainstone.c @@ -168,7 +168,7 @@ static void mainstone_common_init(MemoryRegion *address_space_mem, mainstone_binfo.kernel_cmdline = kernel_cmdline; mainstone_binfo.initrd_filename = initrd_filename; mainstone_binfo.board_id = arm_id; - arm_load_kernel(cpu->env, &mainstone_binfo); + arm_load_kernel(&cpu->cpu->env, &mainstone_binfo); } static void mainstone_init(ram_addr_t ram_size, diff --git a/hw/microblaze_boot.c b/hw/microblaze_boot.c index b4fbb10dd0..1030e9c8ed 100644 --- a/hw/microblaze_boot.c +++ b/hw/microblaze_boot.c @@ -35,7 +35,7 @@ static struct { - void (*machine_cpu_reset)(CPUMBState *); + void (*machine_cpu_reset)(MicroBlazeCPU *); uint32_t bootstrap_pc; uint32_t cmdline; uint32_t fdt; @@ -43,14 +43,15 @@ static struct static void main_cpu_reset(void *opaque) { - CPUMBState *env = opaque; + MicroBlazeCPU *cpu = opaque; + CPUMBState *env = &cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); env->regs[5] = boot_info.cmdline; env->regs[7] = boot_info.fdt; env->sregs[SR_PC] = boot_info.bootstrap_pc; if (boot_info.machine_cpu_reset) { - boot_info.machine_cpu_reset(env); + boot_info.machine_cpu_reset(cpu); } } @@ -99,11 +100,10 @@ static uint64_t translate_kernel_address(void *opaque, uint64_t addr) return addr - 0x30000000LL; } -void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base, uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUMBState *)) + void (*machine_cpu_reset)(MicroBlazeCPU *)) { - QemuOpts *machine_opts; const char *kernel_filename = NULL; const char *kernel_cmdline = NULL; @@ -122,7 +122,7 @@ void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, } boot_info.machine_cpu_reset = machine_cpu_reset; - qemu_register_reset(main_cpu_reset, env); + qemu_register_reset(main_cpu_reset, cpu); if (kernel_filename) { int kernel_size; diff --git a/hw/microblaze_boot.h b/hw/microblaze_boot.h index bf9d136f12..c9a3064d27 100644 --- a/hw/microblaze_boot.h +++ b/hw/microblaze_boot.h @@ -3,8 +3,8 @@ #include "hw.h" -void microblaze_load_kernel(CPUMBState *env, target_phys_addr_t ddr_base, +void microblaze_load_kernel(MicroBlazeCPU *cpu, target_phys_addr_t ddr_base, uint32_t ramsize, const char *dtb_filename, - void (*machine_cpu_reset)(CPUMBState *)); + void (*machine_cpu_reset)(MicroBlazeCPU *)); #endif /* __MICROBLAZE_BOOT __ */ diff --git a/hw/milkymist.c b/hw/milkymist.c index 8bb6a97b22..2e7235b4b3 100644 --- a/hw/milkymist.c +++ b/hw/milkymist.c @@ -37,7 +37,7 @@ #define KERNEL_LOAD_ADDR 0x40000000 typedef struct { - CPULM32State *env; + LM32CPU *cpu; target_phys_addr_t bootstrap_pc; target_phys_addr_t flash_base; target_phys_addr_t initrd_base; @@ -59,9 +59,9 @@ static void cpu_irq_handler(void *opaque, int irq, int level) static void main_cpu_reset(void *opaque) { ResetInfo *reset_info = opaque; - CPULM32State *env = reset_info->env; + CPULM32State *env = &reset_info->cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(reset_info->cpu)); /* init defaults */ env->pc = reset_info->bootstrap_pc; @@ -79,6 +79,7 @@ milkymist_init(ram_addr_t ram_size_not_used, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { + LM32CPU *cpu; CPULM32State *env; int kernel_size; DriveInfo *dinfo; @@ -105,8 +106,9 @@ milkymist_init(ram_addr_t ram_size_not_used, if (cpu_model == NULL) { cpu_model = "lm32-full"; } - env = cpu_init(cpu_model); - reset_info->env = env; + cpu = cpu_lm32_init(cpu_model); + env = &cpu->env; + reset_info->cpu = cpu; cpu_lm32_set_phys_msb_ignore(env, 1); diff --git a/hw/mips_fulong2e.c b/hw/mips_fulong2e.c index 1a8df10429..38e4b86150 100644 --- a/hw/mips_fulong2e.c +++ b/hw/mips_fulong2e.c @@ -198,9 +198,10 @@ static void write_bootloader (CPUMIPSState *env, uint8_t *base, int64_t kernel_a static void main_cpu_reset(void *opaque) { - CPUMIPSState *env = opaque; + MIPSCPU *cpu = opaque; + CPUMIPSState *env = &cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); /* TODO: 2E reset stuff */ if (loaderparams.kernel_filename) { env->CP0_Status &= ~((1 << CP0St_BEV) | (1 << CP0St_ERL)); @@ -272,19 +273,21 @@ static void mips_fulong2e_init(ram_addr_t ram_size, const char *boot_device, i2c_bus *smbus; int i; DriveInfo *hd[MAX_IDE_BUS * MAX_IDE_DEVS]; + MIPSCPU *cpu; CPUMIPSState *env; /* init CPUs */ if (cpu_model == NULL) { cpu_model = "Loongson-2E"; } - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_mips_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + env = &cpu->env; - qemu_register_reset(main_cpu_reset, env); + qemu_register_reset(main_cpu_reset, cpu); /* fulong 2e has 256M ram. */ ram_size = 256 * 1024 * 1024; diff --git a/hw/mips_jazz.c b/hw/mips_jazz.c index a6bc7badff..bf1b799c4d 100644 --- a/hw/mips_jazz.c +++ b/hw/mips_jazz.c @@ -50,8 +50,9 @@ enum jazz_model_e static void main_cpu_reset(void *opaque) { - CPUMIPSState *env = opaque; - cpu_state_reset(env); + MIPSCPU *cpu = opaque; + + cpu_reset(CPU(cpu)); } static uint64_t rtc_read(void *opaque, target_phys_addr_t addr, unsigned size) @@ -112,6 +113,7 @@ static void mips_jazz_init(MemoryRegion *address_space, { char *filename; int bios_size, n; + MIPSCPU *cpu; CPUMIPSState *env; qemu_irq *rc4030, *i8259; rc4030_dma *dmas; @@ -140,12 +142,13 @@ static void mips_jazz_init(MemoryRegion *address_space, cpu_model = "24Kf"; #endif } - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_mips_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } - qemu_register_reset(main_cpu_reset, env); + env = &cpu->env; + qemu_register_reset(main_cpu_reset, cpu); /* allocate RAM */ memory_region_init_ram(ram, "mips_jazz.ram", ram_size); diff --git a/hw/mips_malta.c b/hw/mips_malta.c index 4752bb2865..dfd7b6b113 100644 --- a/hw/mips_malta.c +++ b/hw/mips_malta.c @@ -751,8 +751,10 @@ static void malta_mips_config(CPUMIPSState *env) static void main_cpu_reset(void *opaque) { - CPUMIPSState *env = opaque; - cpu_state_reset(env); + MIPSCPU *cpu = opaque; + CPUMIPSState *env = &cpu->env; + + cpu_reset(CPU(cpu)); /* The bootloader does not need to be rewritten as it is located in a read only location. The kernel location and the arguments table @@ -788,6 +790,7 @@ void mips_malta_init (ram_addr_t ram_size, int64_t kernel_entry; PCIBus *pci_bus; ISABus *isa_bus; + MIPSCPU *cpu; CPUMIPSState *env; qemu_irq *isa_irq; qemu_irq *cpu_exit_irq; @@ -825,15 +828,17 @@ void mips_malta_init (ram_addr_t ram_size, } for (i = 0; i < smp_cpus; i++) { - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_mips_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + env = &cpu->env; + /* Init internal devices */ cpu_mips_irq_init_cpu(env); cpu_mips_clock_init(env); - qemu_register_reset(main_cpu_reset, env); + qemu_register_reset(main_cpu_reset, cpu); } env = first_cpu; diff --git a/hw/mips_mipssim.c b/hw/mips_mipssim.c index 1ea7b58323..eb03047433 100644 --- a/hw/mips_mipssim.c +++ b/hw/mips_mipssim.c @@ -46,7 +46,7 @@ static struct _loaderparams { } loaderparams; typedef struct ResetData { - CPUMIPSState *env; + MIPSCPU *cpu; uint64_t vector; } ResetData; @@ -105,9 +105,9 @@ static int64_t load_kernel(void) static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUMIPSState *env = s->env; + CPUMIPSState *env = &s->cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(s->cpu)); env->active_tc.PC = s->vector & ~(target_ulong)1; if (s->vector & 1) { env->hflags |= MIPS_HFLAG_M16; @@ -140,6 +140,7 @@ mips_mipssim_init (ram_addr_t ram_size, MemoryRegion *address_space_mem = get_system_memory(); MemoryRegion *ram = g_new(MemoryRegion, 1); MemoryRegion *bios = g_new(MemoryRegion, 1); + MIPSCPU *cpu; CPUMIPSState *env; ResetData *reset_info; int bios_size; @@ -152,13 +153,15 @@ mips_mipssim_init (ram_addr_t ram_size, cpu_model = "24Kf"; #endif } - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_mips_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + env = &cpu->env; + reset_info = g_malloc0(sizeof(ResetData)); - reset_info->env = env; + reset_info->cpu = cpu; reset_info->vector = env->active_tc.PC; qemu_register_reset(main_cpu_reset, reset_info); diff --git a/hw/mips_r4k.c b/hw/mips_r4k.c index e2da49c09d..d68599965a 100644 --- a/hw/mips_r4k.c +++ b/hw/mips_r4k.c @@ -65,7 +65,7 @@ static const MemoryRegionOps mips_qemu_ops = { }; typedef struct ResetData { - CPUMIPSState *env; + MIPSCPU *cpu; uint64_t vector; } ResetData; @@ -143,9 +143,9 @@ static int64_t load_kernel(void) static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUMIPSState *env = s->env; + CPUMIPSState *env = &s->cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(s->cpu)); env->active_tc.PC = s->vector; } @@ -162,6 +162,7 @@ void mips_r4k_init (ram_addr_t ram_size, MemoryRegion *bios; MemoryRegion *iomem = g_new(MemoryRegion, 1); int bios_size; + MIPSCPU *cpu; CPUMIPSState *env; ResetData *reset_info; int i; @@ -179,13 +180,15 @@ void mips_r4k_init (ram_addr_t ram_size, cpu_model = "24Kf"; #endif } - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_mips_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + env = &cpu->env; + reset_info = g_malloc0(sizeof(ResetData)); - reset_info->env = env; + reset_info->cpu = cpu; reset_info->vector = env->active_tc.PC; qemu_register_reset(main_cpu_reset, reset_info); diff --git a/hw/nseries.c b/hw/nseries.c index a5cfa8ccbc..b8c6a29227 100644 --- a/hw/nseries.c +++ b/hw/nseries.c @@ -1023,7 +1023,7 @@ static void n8x0_boot_init(void *opaque) n800_dss_init(&s->blizzard); /* CPU setup */ - s->cpu->env->GE = 0x5; + s->cpu->cpu->env.GE = 0x5; /* If the machine has a slided keyboard, open it */ if (s->kbd) @@ -1329,7 +1329,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device, binfo->kernel_filename = kernel_filename; binfo->kernel_cmdline = kernel_cmdline; binfo->initrd_filename = initrd_filename; - arm_load_kernel(s->cpu->env, binfo); + arm_load_kernel(&s->cpu->cpu->env, binfo); qemu_register_reset(n8x0_boot_init, s); } @@ -1338,7 +1338,7 @@ static void n8x0_init(ram_addr_t ram_size, const char *boot_device, int rom_size; uint8_t nolo_tags[0x10000]; /* No, wait, better start at the ROM. */ - s->cpu->env->regs[15] = OMAP2_Q2_BASE + 0x400000; + s->cpu->cpu->env.regs[15] = OMAP2_Q2_BASE + 0x400000; /* This is intended for loading the `secondary.bin' program from * Nokia images (the NOLO bootloader). The entry point seems diff --git a/hw/omap.h b/hw/omap.h index 6c3d004719..2819e5df9a 100644 --- a/hw/omap.h +++ b/hw/omap.h @@ -804,7 +804,7 @@ struct omap_mpu_state_s { omap3630, } mpu_model; - CPUARMState *env; + ARMCPU *cpu; qemu_irq *drq; diff --git a/hw/omap1.c b/hw/omap1.c index 80d47f0b85..a997d300b5 100644 --- a/hw/omap1.c +++ b/hw/omap1.c @@ -1519,8 +1519,9 @@ static inline void omap_clkm_idlect1_update(struct omap_mpu_state_s *s, { omap_clk clk; - if (value & (1 << 11)) /* SETARM_IDLE */ - cpu_interrupt(s->env, CPU_INTERRUPT_HALT); + if (value & (1 << 11)) { /* SETARM_IDLE */ + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT); + } if (!(value & (1 << 10))) /* WKUP_MODE */ qemu_system_shutdown_request(); /* XXX: disable wakeup from IRQ */ @@ -1734,7 +1735,7 @@ static uint64_t omap_clkdsp_read(void *opaque, target_phys_addr_t addr, case 0x18: /* DSP_SYSST */ return (s->clkm.clocking_scheme << 11) | s->clkm.cold_start | - (s->env->halted << 6); /* Quite useless... */ + (s->cpu->env.halted << 6); /* Quite useless... */ } OMAP_BAD_REG(addr); @@ -3701,7 +3702,7 @@ static void omap1_mpu_reset(void *opaque) omap_lpg_reset(mpu->led[0]); omap_lpg_reset(mpu->led[1]); omap_clkm_reset(mpu); - cpu_state_reset(mpu->env); + cpu_reset(CPU(mpu->cpu)); } static const struct omap_map_s { @@ -3751,8 +3752,9 @@ void omap_mpu_wakeup(void *opaque, int irq, int req) { struct omap_mpu_state_s *mpu = (struct omap_mpu_state_s *) opaque; - if (mpu->env->halted) - cpu_interrupt(mpu->env, CPU_INTERRUPT_EXITTB); + if (mpu->cpu->env.halted) { + cpu_interrupt(&mpu->cpu->env, CPU_INTERRUPT_EXITTB); + } } static const struct dma_irq_map omap1_dma_irq_map[] = { @@ -3829,8 +3831,8 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, /* Core */ s->mpu_model = omap310; - s->env = cpu_init(core); - if (!s->env) { + s->cpu = cpu_arm_init(core); + if (s->cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } @@ -3852,7 +3854,7 @@ struct omap_mpu_state_s *omap310_mpu_init(MemoryRegion *system_memory, omap_clkm_init(system_memory, 0xfffece00, 0xe1008000, s); - cpu_irq = arm_pic_init_cpu(s->env); + cpu_irq = arm_pic_init_cpu(&s->cpu->env); s->ih[0] = qdev_create(NULL, "omap-intc"); qdev_prop_set_uint32(s->ih[0], "size", 0x100); qdev_prop_set_ptr(s->ih[0], "clk", omap_findclk(s, "arminth_ck")); diff --git a/hw/omap2.c b/hw/omap2.c index 42fce5e986..196c4b6cc8 100644 --- a/hw/omap2.c +++ b/hw/omap2.c @@ -2222,7 +2222,7 @@ static void omap2_mpu_reset(void *opaque) omap_mmc_reset(mpu->mmc); omap_mcspi_reset(mpu->mcspi[0]); omap_mcspi_reset(mpu->mcspi[1]); - cpu_state_reset(mpu->env); + cpu_reset(CPU(mpu->cpu)); } static int omap2_validate_addr(struct omap_mpu_state_s *s, @@ -2253,8 +2253,8 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, /* Core */ s->mpu_model = omap2420; - s->env = cpu_init(core ?: "arm1136-r2"); - if (!s->env) { + s->cpu = cpu_arm_init(core ?: "arm1136-r2"); + if (s->cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } @@ -2277,7 +2277,7 @@ struct omap_mpu_state_s *omap2420_mpu_init(MemoryRegion *sysmem, s->l4 = omap_l4_init(sysmem, OMAP2_L4_BASE, 54); /* Actually mapped at any 2K boundary in the ARM11 private-peripheral if */ - cpu_irq = arm_pic_init_cpu(s->env); + cpu_irq = arm_pic_init_cpu(&s->cpu->env); s->ih[0] = qdev_create(NULL, "omap2-intc"); qdev_prop_set_uint8(s->ih[0], "revision", 0x21); qdev_prop_set_ptr(s->ih[0], "fclk", omap_findclk(s, "mpu_intc_fclk")); diff --git a/hw/omap_sx1.c b/hw/omap_sx1.c index 4e8ec4a990..c7618c6cdf 100644 --- a/hw/omap_sx1.c +++ b/hw/omap_sx1.c @@ -202,7 +202,7 @@ static void sx1_init(ram_addr_t ram_size, sx1_binfo.kernel_filename = kernel_filename; sx1_binfo.kernel_cmdline = kernel_cmdline; sx1_binfo.initrd_filename = initrd_filename; - arm_load_kernel(cpu->env, &sx1_binfo); + arm_load_kernel(&cpu->cpu->env, &sx1_binfo); } /* TODO: fix next line */ diff --git a/hw/palm.c b/hw/palm.c index b1252ab1e9..6d818294d2 100644 --- a/hw/palm.c +++ b/hw/palm.c @@ -265,7 +265,7 @@ static void palmte_init(ram_addr_t ram_size, palmte_binfo.kernel_filename = kernel_filename; palmte_binfo.kernel_cmdline = kernel_cmdline; palmte_binfo.initrd_filename = initrd_filename; - arm_load_kernel(cpu->env, &palmte_binfo); + arm_load_kernel(&cpu->cpu->env, &palmte_binfo); } /* FIXME: We shouldn't really be doing this here. The LCD controller diff --git a/hw/pc.c b/hw/pc.c index c790bcbfd7..8368701efb 100644 --- a/hw/pc.c +++ b/hw/pc.c @@ -926,27 +926,30 @@ void pc_acpi_smi_interrupt(void *opaque, int irq, int level) static void pc_cpu_reset(void *opaque) { - CPUX86State *env = opaque; + X86CPU *cpu = opaque; + CPUX86State *env = &cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); env->halted = !cpu_is_bsp(env); } -static CPUX86State *pc_new_cpu(const char *cpu_model) +static X86CPU *pc_new_cpu(const char *cpu_model) { + X86CPU *cpu; CPUX86State *env; - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_x86_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find x86 CPU definition\n"); exit(1); } + env = &cpu->env; if ((env->cpuid_features & CPUID_APIC) || smp_cpus > 1) { env->apic_state = apic_init(env, env->cpuid_apic_id); } - qemu_register_reset(pc_cpu_reset, env); - pc_cpu_reset(env); - return env; + qemu_register_reset(pc_cpu_reset, cpu); + pc_cpu_reset(cpu); + return cpu; } void pc_cpus_init(const char *cpu_model) diff --git a/hw/petalogix_ml605_mmu.c b/hw/petalogix_ml605_mmu.c index 31a434872d..bff63e389a 100644 --- a/hw/petalogix_ml605_mmu.c +++ b/hw/petalogix_ml605_mmu.c @@ -54,8 +54,10 @@ #define AXIENET_BASEADDR 0x82780000 #define AXIDMA_BASEADDR 0x84600000 -static void machine_cpu_reset(CPUMBState *env) +static void machine_cpu_reset(MicroBlazeCPU *cpu) { + CPUMBState *env = &cpu->env; + env->pvr.regs[10] = 0x0e000000; /* virtex 6 */ /* setup pvr to match kernel setting */ env->pvr.regs[5] |= PVR5_DCACHE_WRITEBACK_MASK; @@ -75,6 +77,7 @@ petalogix_ml605_init(ram_addr_t ram_size, { MemoryRegion *address_space_mem = get_system_memory(); DeviceState *dev; + MicroBlazeCPU *cpu; CPUMBState *env; DriveInfo *dinfo; int i; @@ -87,7 +90,8 @@ petalogix_ml605_init(ram_addr_t ram_size, if (cpu_model == NULL) { cpu_model = "microblaze"; } - env = cpu_init(cpu_model); + cpu = cpu_mb_init(cpu_model); + env = &cpu->env; /* Attach emulated BRAM through the LMB. */ memory_region_init_ram(phys_lmb_bram, "petalogix_ml605.lmb_bram", @@ -131,7 +135,7 @@ petalogix_ml605_init(ram_addr_t ram_size, irq[1], irq[0], 100 * 1000000); } - microblaze_load_kernel(env, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, + microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, machine_cpu_reset); } diff --git a/hw/petalogix_s3adsp1800_mmu.c b/hw/petalogix_s3adsp1800_mmu.c index 8b37336001..f41c559e61 100644 --- a/hw/petalogix_s3adsp1800_mmu.c +++ b/hw/petalogix_s3adsp1800_mmu.c @@ -49,8 +49,10 @@ #define UARTLITE_BASEADDR 0x84000000 #define ETHLITE_BASEADDR 0x81000000 -static void machine_cpu_reset(CPUMBState *env) +static void machine_cpu_reset(MicroBlazeCPU *cpu) { + CPUMBState *env = &cpu->env; + env->pvr.regs[10] = 0x0c000000; /* spartan 3a dsp family. */ } @@ -62,6 +64,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { DeviceState *dev; + MicroBlazeCPU *cpu; CPUMBState *env; DriveInfo *dinfo; int i; @@ -75,7 +78,8 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, if (cpu_model == NULL) { cpu_model = "microblaze"; } - env = cpu_init(cpu_model); + cpu = cpu_mb_init(cpu_model); + env = &cpu->env; /* Attach emulated BRAM through the LMB. */ memory_region_init_ram(phys_lmb_bram, @@ -105,7 +109,7 @@ petalogix_s3adsp1800_init(ram_addr_t ram_size, xilinx_timer_create(TIMER_BASEADDR, irq[0], 2, 62 * 1000000); xilinx_ethlite_create(&nd_table[0], ETHLITE_BASEADDR, irq[1], 0, 0); - microblaze_load_kernel(env, ddr_base, ram_size, + microblaze_load_kernel(cpu, ddr_base, ram_size, BINARY_DEVICE_TREE_FILE, machine_cpu_reset); } diff --git a/hw/ppc440_bamboo.c b/hw/ppc440_bamboo.c index f0a3ae49e6..0dd4dab318 100644 --- a/hw/ppc440_bamboo.c +++ b/hw/ppc440_bamboo.c @@ -145,9 +145,10 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, static void main_cpu_reset(void *opaque) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); env->gpr[1] = (16<<20) - 8; env->gpr[3] = FDT_ADDR; env->nip = entry; @@ -172,6 +173,7 @@ static void bamboo_init(ram_addr_t ram_size, qemu_irq *pic; qemu_irq *irqs; PCIBus *pcibus; + PowerPCCPU *cpu; CPUPPCState *env; uint64_t elf_entry; uint64_t elf_lowaddr; @@ -185,13 +187,14 @@ static void bamboo_init(ram_addr_t ram_size, if (cpu_model == NULL) { cpu_model = "440EP"; } - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_ppc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to initialize CPU!\n"); exit(1); } + env = &cpu->env; - qemu_register_reset(main_cpu_reset, env); + qemu_register_reset(main_cpu_reset, cpu); ppc_booke_timers_init(env, 400000000, 0); ppc_dcr_init(env, NULL, NULL); diff --git a/hw/ppc4xx_devs.c b/hw/ppc4xx_devs.c index 00e36f4109..41163e607d 100644 --- a/hw/ppc4xx_devs.c +++ b/hw/ppc4xx_devs.c @@ -40,9 +40,9 @@ static void ppc4xx_reset(void *opaque) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); } /*****************************************************************************/ @@ -51,15 +51,18 @@ CPUPPCState *ppc4xx_init (const char *cpu_model, clk_setup_t *cpu_clk, clk_setup_t *tb_clk, uint32_t sysclk) { + PowerPCCPU *cpu; CPUPPCState *env; /* init CPUs */ - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_ppc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find PowerPC %s CPU definition\n", cpu_model); exit(1); } + env = &cpu->env; + cpu_clk->cb = NULL; /* We don't care about CPU clock frequency changes */ cpu_clk->opaque = env; /* Set time-base frequency to sysclk */ @@ -67,7 +70,7 @@ CPUPPCState *ppc4xx_init (const char *cpu_model, tb_clk->opaque = env; ppc_dcr_init(env, NULL, NULL); /* Register qemu callbacks */ - qemu_register_reset(ppc4xx_reset, env); + qemu_register_reset(ppc4xx_reset, cpu); return env; } diff --git a/hw/ppc_newworld.c b/hw/ppc_newworld.c index 879651018b..4e2a6e691b 100644 --- a/hw/ppc_newworld.c +++ b/hw/ppc_newworld.c @@ -123,9 +123,9 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) static void ppc_core99_reset(void *opaque) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); } /* PowerPC Mac99 hardware initialisation */ @@ -136,6 +136,7 @@ static void ppc_core99_init (ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { + PowerPCCPU *cpu = NULL; CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **openpic_irqs; @@ -166,14 +167,16 @@ static void ppc_core99_init (ram_addr_t ram_size, cpu_model = "G4"; #endif for (i = 0; i < smp_cpus; i++) { - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_ppc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } + env = &cpu->env; + /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); - qemu_register_reset(ppc_core99_reset, env); + qemu_register_reset(ppc_core99_reset, cpu); } /* allocate RAM */ diff --git a/hw/ppc_oldworld.c b/hw/ppc_oldworld.c index 7e73d37c34..f2c6908534 100644 --- a/hw/ppc_oldworld.c +++ b/hw/ppc_oldworld.c @@ -67,9 +67,9 @@ static target_phys_addr_t round_page(target_phys_addr_t addr) static void ppc_heathrow_reset(void *opaque) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); } static void ppc_heathrow_init (ram_addr_t ram_size, @@ -80,6 +80,7 @@ static void ppc_heathrow_init (ram_addr_t ram_size, const char *cpu_model) { MemoryRegion *sysmem = get_system_memory(); + PowerPCCPU *cpu = NULL; CPUPPCState *env = NULL; char *filename; qemu_irq *pic, **heathrow_irqs; @@ -104,14 +105,16 @@ static void ppc_heathrow_init (ram_addr_t ram_size, if (cpu_model == NULL) cpu_model = "G3"; for (i = 0; i < smp_cpus; i++) { - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_ppc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } + env = &cpu->env; + /* Set time-base frequency to 16.6 Mhz */ cpu_ppc_tb_init(env, 16600000UL); - qemu_register_reset(ppc_heathrow_reset, env); + qemu_register_reset(ppc_heathrow_reset, cpu); } /* allocate RAM */ diff --git a/hw/ppc_prep.c b/hw/ppc_prep.c index b1da114114..be2b26830d 100644 --- a/hw/ppc_prep.c +++ b/hw/ppc_prep.c @@ -441,9 +441,9 @@ static void cpu_request_exit(void *opaque, int irq, int level) static void ppc_prep_reset(void *opaque) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); } /* PowerPC PREP hardware initialisation */ @@ -455,6 +455,7 @@ static void ppc_prep_init (ram_addr_t ram_size, const char *cpu_model) { MemoryRegion *sysmem = get_system_memory(); + PowerPCCPU *cpu = NULL; CPUPPCState *env = NULL; char *filename; nvram_t nvram; @@ -487,11 +488,13 @@ static void ppc_prep_init (ram_addr_t ram_size, if (cpu_model == NULL) cpu_model = "602"; for (i = 0; i < smp_cpus; i++) { - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_ppc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } + env = &cpu->env; + if (env->flags & POWERPC_FLAG_RTC_CLK) { /* POWER / PowerPC 601 RTC clock frequency is 7.8125 MHz */ cpu_ppc_tb_init(env, 7812500UL); @@ -499,7 +502,7 @@ static void ppc_prep_init (ram_addr_t ram_size, /* Set time-base frequency to 100 Mhz */ cpu_ppc_tb_init(env, 100UL * 1000UL * 1000UL); } - qemu_register_reset(ppc_prep_reset, env); + qemu_register_reset(ppc_prep_reset, cpu); } /* allocate RAM */ diff --git a/hw/ppce500_mpc8544ds.c b/hw/ppce500_mpc8544ds.c index f1dfbe181c..3eb8a23779 100644 --- a/hw/ppce500_mpc8544ds.c +++ b/hw/ppce500_mpc8544ds.c @@ -196,9 +196,10 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, static void mpc8544ds_cpu_reset_sec(void *opaque) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); /* Secondary CPU starts in halted state for now. Needs to change when implementing non-kernel boot. */ @@ -208,10 +209,11 @@ static void mpc8544ds_cpu_reset_sec(void *opaque) static void mpc8544ds_cpu_reset(void *opaque) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; struct boot_info *bi = env->load_info; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); /* Set initial guest state. */ env->halted = 0; @@ -254,12 +256,15 @@ static void mpc8544ds_init(ram_addr_t ram_size, irqs = g_malloc0(smp_cpus * sizeof(qemu_irq *)); irqs[0] = g_malloc0(smp_cpus * sizeof(qemu_irq) * OPENPIC_OUTPUT_NB); for (i = 0; i < smp_cpus; i++) { + PowerPCCPU *cpu; qemu_irq *input; - env = cpu_ppc_init(cpu_model); - if (!env) { + + cpu = cpu_ppc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to initialize CPU!\n"); exit(1); } + env = &cpu->env; if (!firstenv) { firstenv = env; @@ -278,11 +283,11 @@ static void mpc8544ds_init(ram_addr_t ram_size, /* Primary CPU */ struct boot_info *boot_info; boot_info = g_malloc0(sizeof(struct boot_info)); - qemu_register_reset(mpc8544ds_cpu_reset, env); + qemu_register_reset(mpc8544ds_cpu_reset, cpu); env->load_info = boot_info; } else { /* Secondary CPUs */ - qemu_register_reset(mpc8544ds_cpu_reset_sec, env); + qemu_register_reset(mpc8544ds_cpu_reset_sec, cpu); } } diff --git a/hw/pxa.h b/hw/pxa.h index 025be34f86..2be006d29c 100644 --- a/hw/pxa.h +++ b/hw/pxa.h @@ -122,7 +122,7 @@ typedef struct PXA2xxI2SState PXA2xxI2SState; typedef struct PXA2xxFIrState PXA2xxFIrState; typedef struct { - CPUARMState *env; + ARMCPU *cpu; DeviceState *pic; qemu_irq reset; MemoryRegion sdram; diff --git a/hw/pxa2xx.c b/hw/pxa2xx.c index ddaa846882..5f8f226a29 100644 --- a/hw/pxa2xx.c +++ b/hw/pxa2xx.c @@ -269,24 +269,24 @@ static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm, case 1: /* Idle */ if (!(s->cm_regs[CCCR >> 2] & (1 << 31))) { /* CPDIS */ - cpu_interrupt(s->env, CPU_INTERRUPT_HALT); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT); break; } /* Fall through. */ case 2: /* Deep-Idle */ - cpu_interrupt(s->env, CPU_INTERRUPT_HALT); + cpu_interrupt(&s->cpu->env, CPU_INTERRUPT_HALT); s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ goto message; case 3: - s->env->uncached_cpsr = + s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC | CPSR_A | CPSR_F | CPSR_I; - s->env->cp15.c1_sys = 0; - s->env->cp15.c1_coproc = 0; - s->env->cp15.c2_base0 = 0; - s->env->cp15.c3 = 0; + s->cpu->env.cp15.c1_sys = 0; + s->cpu->env.cp15.c1_coproc = 0; + s->cpu->env.cp15.c2_base0 = 0; + s->cpu->env.cp15.c3 = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ s->pm_regs[RCSR >> 2] |= 0x8; /* Set GPR */ @@ -296,8 +296,8 @@ static void pxa2xx_clkpwr_write(void *opaque, int op2, int reg, int crm, * lack of a resuming bootloader, perform a jump * directly to that address. */ - memset(s->env->regs, 0, 4 * 15); - s->env->regs[15] = s->pm_regs[PSPR >> 2]; + memset(s->cpu->env.regs, 0, 4 * 15); + s->cpu->env.regs[15] = s->pm_regs[PSPR >> 2]; #if 0 buffer = 0xe59ff000; /* ldr pc, [pc, #0] */ @@ -2044,7 +2044,7 @@ static void pxa2xx_reset(void *opaque, int line, int level) PXA2xxState *s = (PXA2xxState *) opaque; if (level && (s->pm_regs[PCFR >> 2] & 0x10)) { /* GPR_EN */ - cpu_state_reset(s->env); + cpu_reset(CPU(s->cpu)); /* TODO: reset peripherals */ } } @@ -2065,8 +2065,8 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, if (!revision) revision = "pxa270"; - s->env = cpu_init(revision); - if (!s->env) { + s->cpu = cpu_arm_init(revision); + if (s->cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } @@ -2081,7 +2081,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, &s->internal); - s->pic = pxa2xx_pic_init(0x40d00000, s->env); + s->pic = pxa2xx_pic_init(0x40d00000, &s->cpu->env); s->dma = pxa27x_dma_init(0x40000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); @@ -2094,7 +2094,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, qdev_get_gpio_in(s->pic, PXA27X_PIC_OST_4_11), NULL); - s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 121); + s->gpio = pxa2xx_gpio_init(0x40e00000, &s->cpu->env, s->pic, 121); dinfo = drive_get(IF_SD, 0, 0); if (!dinfo) { @@ -2133,7 +2133,7 @@ PXA2xxState *pxa270_init(MemoryRegion *address_space, memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); - cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); + cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); s->mm_base = 0x48000000; s->mm_regs[MDMRS >> 2] = 0x00020002; @@ -2196,8 +2196,8 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) s = (PXA2xxState *) g_malloc0(sizeof(PXA2xxState)); - s->env = cpu_init("pxa255"); - if (!s->env) { + s->cpu = cpu_arm_init("pxa255"); + if (s->cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } @@ -2213,7 +2213,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) memory_region_add_subregion(address_space, PXA2XX_INTERNAL_BASE, &s->internal); - s->pic = pxa2xx_pic_init(0x40d00000, s->env); + s->pic = pxa2xx_pic_init(0x40d00000, &s->cpu->env); s->dma = pxa255_dma_init(0x40000000, qdev_get_gpio_in(s->pic, PXA2XX_PIC_DMA)); @@ -2225,7 +2225,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) qdev_get_gpio_in(s->pic, PXA2XX_PIC_OST_0 + 3), NULL); - s->gpio = pxa2xx_gpio_init(0x40e00000, s->env, s->pic, 85); + s->gpio = pxa2xx_gpio_init(0x40e00000, &s->cpu->env, s->pic, 85); dinfo = drive_get(IF_SD, 0, 0); if (!dinfo) { @@ -2264,7 +2264,7 @@ PXA2xxState *pxa255_init(MemoryRegion *address_space, unsigned int sdram_size) memory_region_add_subregion(address_space, s->cm_base, &s->cm_iomem); vmstate_register(NULL, 0, &vmstate_pxa2xx_cm, s); - cpu_arm_set_cp_io(s->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); + cpu_arm_set_cp_io(&s->cpu->env, 14, pxa2xx_cp14_read, pxa2xx_cp14_write, s); s->mm_base = 0x48000000; s->mm_regs[MDMRS >> 2] = 0x00020002; diff --git a/hw/r2d.c b/hw/r2d.c index c55de0141b..0f16e81afe 100644 --- a/hw/r2d.c +++ b/hw/r2d.c @@ -192,16 +192,16 @@ static qemu_irq *r2d_fpga_init(MemoryRegion *sysmem, } typedef struct ResetData { - CPUSH4State *env; + SuperHCPU *cpu; uint32_t vector; } ResetData; static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUSH4State *env = s->env; + CPUSH4State *env = &s->cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(s->cpu)); env->pc = s->vector; } @@ -224,6 +224,7 @@ static void r2d_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { + SuperHCPU *cpu; CPUSH4State *env; ResetData *reset_info; struct SH7750State *s; @@ -235,16 +236,19 @@ static void r2d_init(ram_addr_t ram_size, SysBusDevice *busdev; MemoryRegion *address_space_mem = get_system_memory(); - if (!cpu_model) + if (cpu_model == NULL) { cpu_model = "SH7751R"; + } - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_sh4_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + env = &cpu->env; + reset_info = g_malloc0(sizeof(ResetData)); - reset_info->env = env; + reset_info->cpu = cpu; reset_info->vector = env->pc; qemu_register_reset(main_cpu_reset, reset_info); diff --git a/hw/spapr.c b/hw/spapr.c index cca20f9a51..d0bddbce95 100644 --- a/hw/spapr.c +++ b/hw/spapr.c @@ -505,9 +505,9 @@ static void spapr_reset(void *opaque) static void spapr_cpu_reset(void *opaque) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); } /* pSeries LPAR / sPAPR hardware init */ @@ -518,6 +518,7 @@ static void ppc_spapr_init(ram_addr_t ram_size, const char *initrd_filename, const char *cpu_model) { + PowerPCCPU *cpu; CPUPPCState *env; int i; MemoryRegion *sysmem = get_system_memory(); @@ -560,15 +561,16 @@ static void ppc_spapr_init(ram_addr_t ram_size, cpu_model = kvm_enabled() ? "host" : "POWER7"; } for (i = 0; i < smp_cpus; i++) { - env = cpu_init(cpu_model); - - if (!env) { + cpu = cpu_ppc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find PowerPC CPU definition\n"); exit(1); } + env = &cpu->env; + /* Set time-base frequency to 512 MHz */ cpu_ppc_tb_init(env, TIMEBASE_FREQ); - qemu_register_reset(spapr_cpu_reset, env); + qemu_register_reset(spapr_cpu_reset, cpu); env->hreset_vector = 0x60; env->hreset_excp_prefix = 0; diff --git a/hw/spitz.c b/hw/spitz.c index 1d6d2b0e1b..9042d44596 100644 --- a/hw/spitz.c +++ b/hw/spitz.c @@ -932,7 +932,7 @@ static void spitz_common_init(ram_addr_t ram_size, spitz_binfo.kernel_cmdline = kernel_cmdline; spitz_binfo.initrd_filename = initrd_filename; spitz_binfo.board_id = arm_id; - arm_load_kernel(cpu->env, &spitz_binfo); + arm_load_kernel(&cpu->cpu->env, &spitz_binfo); sl_bootparam_write(SL_PXA_PARAM_BASE); } diff --git a/hw/sun4m.c b/hw/sun4m.c index 34088ad185..a959261209 100644 --- a/hw/sun4m.c +++ b/hw/sun4m.c @@ -281,17 +281,19 @@ static void dummy_cpu_set_irq(void *opaque, int irq, int level) static void main_cpu_reset(void *opaque) { - CPUSPARCState *env = opaque; + SPARCCPU *cpu = opaque; + CPUSPARCState *env = &cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); env->halted = 0; } static void secondary_cpu_reset(void *opaque) { - CPUSPARCState *env = opaque; + SPARCCPU *cpu = opaque; + CPUSPARCState *env = &cpu->env; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); env->halted = 1; } @@ -809,19 +811,21 @@ static TypeInfo ram_info = { static void cpu_devinit(const char *cpu_model, unsigned int id, uint64_t prom_addr, qemu_irq **cpu_irqs) { + SPARCCPU *cpu; CPUSPARCState *env; - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_sparc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "qemu: Unable to find Sparc CPU definition\n"); exit(1); } + env = &cpu->env; cpu_sparc_set_id(env, id); if (id == 0) { - qemu_register_reset(main_cpu_reset, env); + qemu_register_reset(main_cpu_reset, cpu); } else { - qemu_register_reset(secondary_cpu_reset, env); + qemu_register_reset(secondary_cpu_reset, cpu); env->halted = 1; } *cpu_irqs = qemu_allocate_irqs(cpu_set_irq, env, MAX_PILS); diff --git a/hw/sun4u.c b/hw/sun4u.c index 517bdb818d..137a7c6666 100644 --- a/hw/sun4u.c +++ b/hw/sun4u.c @@ -342,7 +342,7 @@ static void cpu_set_ivec_irq(void *opaque, int irq, int level) } typedef struct ResetData { - CPUSPARCState *env; + SPARCCPU *cpu; uint64_t prom_addr; } ResetData; @@ -395,10 +395,10 @@ static void cpu_timer_reset(CPUTimer *timer) static void main_cpu_reset(void *opaque) { ResetData *s = (ResetData *)opaque; - CPUSPARCState *env = s->env; + CPUSPARCState *env = &s->cpu->env; static unsigned int nr_resets; - cpu_state_reset(env); + cpu_reset(CPU(s->cpu)); cpu_timer_reset(env->tick); cpu_timer_reset(env->stick); @@ -752,8 +752,9 @@ static TypeInfo ram_info = { .class_init = ram_class_init, }; -static CPUSPARCState *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) +static SPARCCPU *cpu_devinit(const char *cpu_model, const struct hwdef *hwdef) { + SPARCCPU *cpu; CPUSPARCState *env; ResetData *reset_info; @@ -761,13 +762,15 @@ static CPUSPARCState *cpu_devinit(const char *cpu_model, const struct hwdef *hwd uint32_t stick_frequency = 100*1000000; uint32_t hstick_frequency = 100*1000000; - if (!cpu_model) + if (cpu_model == NULL) { cpu_model = hwdef->default_cpu_model; - env = cpu_init(cpu_model); - if (!env) { + } + cpu = cpu_sparc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find Sparc CPU definition\n"); exit(1); } + env = &cpu->env; env->tick = cpu_timer_create("tick", env, tick_irq, tick_frequency, TICK_NPT_MASK); @@ -779,11 +782,11 @@ static CPUSPARCState *cpu_devinit(const char *cpu_model, const struct hwdef *hwd hstick_frequency, TICK_INT_DIS); reset_info = g_malloc0(sizeof(ResetData)); - reset_info->env = env; + reset_info->cpu = cpu; reset_info->prom_addr = hwdef->prom_addr; qemu_register_reset(main_cpu_reset, reset_info); - return env; + return cpu; } static void sun4uv_init(MemoryRegion *address_space_mem, @@ -793,6 +796,7 @@ static void sun4uv_init(MemoryRegion *address_space_mem, const char *initrd_filename, const char *cpu_model, const struct hwdef *hwdef) { + SPARCCPU *cpu; CPUSPARCState *env; M48t59State *nvram; unsigned int i; @@ -805,7 +809,8 @@ static void sun4uv_init(MemoryRegion *address_space_mem, void *fw_cfg; /* init CPUs */ - env = cpu_devinit(cpu_model, hwdef); + cpu = cpu_devinit(cpu_model, hwdef); + env = &cpu->env; /* set up devices */ ram_init(0, RAM_size); diff --git a/hw/tosa.c b/hw/tosa.c index 6baa17d6b5..d1ede8dc08 100644 --- a/hw/tosa.c +++ b/hw/tosa.c @@ -242,7 +242,7 @@ static void tosa_init(ram_addr_t ram_size, tosa_binfo.kernel_cmdline = kernel_cmdline; tosa_binfo.initrd_filename = initrd_filename; tosa_binfo.board_id = 0x208; - arm_load_kernel(cpu->env, &tosa_binfo); + arm_load_kernel(&cpu->cpu->env, &tosa_binfo); sl_bootparam_write(SL_PXA_PARAM_BASE); } diff --git a/hw/virtex_ml507.c b/hw/virtex_ml507.c index 4a133b5d1e..cace86b5e4 100644 --- a/hw/virtex_ml507.c +++ b/hw/virtex_ml507.c @@ -78,19 +78,21 @@ static void mmubooke_create_initial_mapping(CPUPPCState *env, tlb->PID = 0; } -static CPUPPCState *ppc440_init_xilinx(ram_addr_t *ram_size, - int do_init, - const char *cpu_model, - uint32_t sysclk) +static PowerPCCPU *ppc440_init_xilinx(ram_addr_t *ram_size, + int do_init, + const char *cpu_model, + uint32_t sysclk) { + PowerPCCPU *cpu; CPUPPCState *env; qemu_irq *irqs; - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_ppc_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to initialize CPU!\n"); exit(1); } + env = &cpu->env; ppc_booke_timers_init(env, sysclk, 0/* no flags */); @@ -101,15 +103,16 @@ static CPUPPCState *ppc440_init_xilinx(ram_addr_t *ram_size, irqs[PPCUIC_OUTPUT_INT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_INT]; irqs[PPCUIC_OUTPUT_CINT] = ((qemu_irq *)env->irq_inputs)[PPC40x_INPUT_CINT]; ppcuic_init(env, irqs, 0x0C0, 0, 1); - return env; + return cpu; } static void main_cpu_reset(void *opaque) { - CPUPPCState *env = opaque; + PowerPCCPU *cpu = opaque; + CPUPPCState *env = &cpu->env; struct boot_info *bi = env->load_info; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); /* Linux Kernel Parameters (passing device tree): * r3: pointer to the fdt * r4: 0 @@ -188,6 +191,7 @@ static void virtex_init(ram_addr_t ram_size, { MemoryRegion *address_space_mem = get_system_memory(); DeviceState *dev; + PowerPCCPU *cpu; CPUPPCState *env; target_phys_addr_t ram_base = 0; DriveInfo *dinfo; @@ -201,8 +205,9 @@ static void virtex_init(ram_addr_t ram_size, cpu_model = "440-Xilinx"; } - env = ppc440_init_xilinx(&ram_size, 1, cpu_model, 400000000); - qemu_register_reset(main_cpu_reset, env); + cpu = ppc440_init_xilinx(&ram_size, 1, cpu_model, 400000000); + env = &cpu->env; + qemu_register_reset(main_cpu_reset, cpu); memory_region_init_ram(phys_ram, "ram", ram_size); vmstate_register_ram_global(phys_ram); diff --git a/hw/xtensa_lx60.c b/hw/xtensa_lx60.c index afdef494b2..b153bfdddf 100644 --- a/hw/xtensa_lx60.c +++ b/hw/xtensa_lx60.c @@ -148,9 +148,9 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr) static void lx60_reset(void *opaque) { - CPUXtensaState *env = opaque; + XtensaCPU *cpu = opaque; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); } static void lx_init(const LxBoardDesc *board, @@ -164,6 +164,7 @@ static void lx_init(const LxBoardDesc *board, int be = 0; #endif MemoryRegion *system_memory = get_system_memory(); + XtensaCPU *cpu = NULL; CPUXtensaState *env = NULL; MemoryRegion *ram, *rom, *system_io; DriveInfo *dinfo; @@ -175,17 +176,19 @@ static void lx_init(const LxBoardDesc *board, } for (n = 0; n < smp_cpus; n++) { - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_xtensa_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + env = &cpu->env; + env->sregs[PRID] = n; - qemu_register_reset(lx60_reset, env); + qemu_register_reset(lx60_reset, cpu); /* Need MMU initialized prior to ELF loading, * so that ELF gets loaded into virtual addresses */ - cpu_state_reset(env); + cpu_reset(CPU(cpu)); } ram = g_malloc(sizeof(*ram)); diff --git a/hw/xtensa_sim.c b/hw/xtensa_sim.c index c7e05dcf4e..1ce07fb899 100644 --- a/hw/xtensa_sim.c +++ b/hw/xtensa_sim.c @@ -37,9 +37,11 @@ static uint64_t translate_phys_addr(void *env, uint64_t addr) return cpu_get_phys_page_debug(env, addr); } -static void sim_reset(void *env) +static void sim_reset(void *opaque) { - cpu_state_reset(env); + XtensaCPU *cpu = opaque; + + cpu_reset(CPU(cpu)); } static void sim_init(ram_addr_t ram_size, @@ -47,22 +49,25 @@ static void sim_init(ram_addr_t ram_size, const char *kernel_filename, const char *kernel_cmdline, const char *initrd_filename, const char *cpu_model) { + XtensaCPU *cpu = NULL; CPUXtensaState *env = NULL; MemoryRegion *ram, *rom; int n; for (n = 0; n < smp_cpus; n++) { - env = cpu_init(cpu_model); - if (!env) { + cpu = cpu_xtensa_init(cpu_model); + if (cpu == NULL) { fprintf(stderr, "Unable to find CPU definition\n"); exit(1); } + env = &cpu->env; + env->sregs[PRID] = n; - qemu_register_reset(sim_reset, env); + qemu_register_reset(sim_reset, cpu); /* Need MMU initialized prior to ELF loading, * so that ELF gets loaded into virtual addresses */ - sim_reset(env); + sim_reset(cpu); } ram = g_malloc(sizeof(*ram)); diff --git a/hw/z2.c b/hw/z2.c index 654ac55f5c..9dd83ffb4b 100644 --- a/hw/z2.c +++ b/hw/z2.c @@ -363,7 +363,7 @@ static void z2_init(ram_addr_t ram_size, z2_binfo.kernel_cmdline = kernel_cmdline; z2_binfo.initrd_filename = initrd_filename; z2_binfo.board_id = 0x6dd; - arm_load_kernel(cpu->env, &z2_binfo); + arm_load_kernel(&cpu->cpu->env, &z2_binfo); } } diff --git a/linux-user/main.c b/linux-user/main.c index 191b75060d..49108b81d3 100644 --- a/linux-user/main.c +++ b/linux-user/main.c @@ -3405,7 +3405,7 @@ int main(int argc, char **argv, char **envp) exit(1); } #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) - cpu_state_reset(env); + cpu_reset(ENV_GET_CPU(env)); #endif thread_env = env; diff --git a/linux-user/syscall.c b/linux-user/syscall.c index 20d2a74877..539af3f94b 100644 --- a/linux-user/syscall.c +++ b/linux-user/syscall.c @@ -4262,7 +4262,7 @@ static int do_fork(CPUArchState *env, unsigned int flags, abi_ulong newsp, /* we create a new CPU instance. */ new_env = cpu_copy(env); #if defined(TARGET_I386) || defined(TARGET_SPARC) || defined(TARGET_PPC) - cpu_state_reset(new_env); + cpu_reset(ENV_GET_CPU(new_env)); #endif /* Init regs that differ from the parent. */ cpu_clone_regs(new_env, newsp); diff --git a/target-arm/helper.c b/target-arm/helper.c index 7e1c2c06bd..bbb1d05d10 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -4,11 +4,6 @@ #include "host-utils.h" #include "sysemu.h" -void cpu_state_reset(CPUARMState *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} - static int vfp_gdb_get_reg(CPUARMState *env, uint8_t *buf, int reg) { int nregs; @@ -80,7 +75,7 @@ ARMCPU *cpu_arm_init(const char *cpu_model) arm_translate_init(); } - cpu_state_reset(env); + cpu_reset(CPU(cpu)); if (arm_feature(env, ARM_FEATURE_NEON)) { gdb_register_coprocessor(env, vfp_gdb_get_reg, vfp_gdb_set_reg, 51, "arm-neon.xml", 0); diff --git a/target-cris/cpu.h b/target-cris/cpu.h index 5449cc48b6..a7603678fc 100644 --- a/target-cris/cpu.h +++ b/target-cris/cpu.h @@ -171,7 +171,7 @@ typedef struct CPUCRISState { #include "cpu-qom.h" -CPUCRISState *cpu_cris_init(const char *cpu_model); +CRISCPU *cpu_cris_init(const char *cpu_model); int cpu_cris_exec(CPUCRISState *s); void cpu_cris_close(CPUCRISState *s); void do_interrupt(CPUCRISState *env); @@ -216,7 +216,15 @@ enum { #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define cpu_init cpu_cris_init +static inline CPUCRISState *cpu_init(const char *cpu_model) +{ + CRISCPU *cpu = cpu_cris_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + #define cpu_exec cpu_cris_exec #define cpu_gen_code cpu_cris_gen_code #define cpu_signal_handler cpu_cris_signal_handler diff --git a/target-cris/translate.c b/target-cris/translate.c index e353ea3fa8..1ad9ec788e 100644 --- a/target-cris/translate.c +++ b/target-cris/translate.c @@ -3503,81 +3503,77 @@ static uint32_t vr_by_name(const char *name) return 32; } -CPUCRISState *cpu_cris_init (const char *cpu_model) +CRISCPU *cpu_cris_init(const char *cpu_model) { CRISCPU *cpu; - CPUCRISState *env; - static int tcg_initialized = 0; - int i; + CPUCRISState *env; + static int tcg_initialized = 0; + int i; cpu = CRIS_CPU(object_new(TYPE_CRIS_CPU)); env = &cpu->env; - env->pregs[PR_VR] = vr_by_name(cpu_model); + env->pregs[PR_VR] = vr_by_name(cpu_model); cpu_reset(CPU(cpu)); - qemu_init_vcpu(env); + qemu_init_vcpu(env); - if (tcg_initialized) - return env; + if (tcg_initialized) { + return cpu; + } - tcg_initialized = 1; + tcg_initialized = 1; #define GEN_HELPER 2 #include "helper.h" - if (env->pregs[PR_VR] < 32) { - cpu_crisv10_init(env); - return env; - } - + if (env->pregs[PR_VR] < 32) { + cpu_crisv10_init(env); + return cpu; + } - cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); - cc_x = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, cc_x), "cc_x"); - cc_src = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, cc_src), "cc_src"); - cc_dest = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, cc_dest), - "cc_dest"); - cc_result = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, cc_result), - "cc_result"); - cc_op = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, cc_op), "cc_op"); - cc_size = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, cc_size), - "cc_size"); - cc_mask = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, cc_mask), - "cc_mask"); - - env_pc = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, pc), - "pc"); - env_btarget = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, btarget), - "btarget"); - env_btaken = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, btaken), - "btaken"); - for (i = 0; i < 16; i++) { - cpu_R[i] = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, regs[i]), - regnames[i]); - } - for (i = 0; i < 16; i++) { - cpu_PR[i] = tcg_global_mem_new(TCG_AREG0, - offsetof(CPUCRISState, pregs[i]), - pregnames[i]); - } - return env; -} + cpu_env = tcg_global_reg_new_ptr(TCG_AREG0, "env"); + cc_x = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, cc_x), "cc_x"); + cc_src = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, cc_src), "cc_src"); + cc_dest = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, cc_dest), + "cc_dest"); + cc_result = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, cc_result), + "cc_result"); + cc_op = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, cc_op), "cc_op"); + cc_size = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, cc_size), + "cc_size"); + cc_mask = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, cc_mask), + "cc_mask"); + + env_pc = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, pc), + "pc"); + env_btarget = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, btarget), + "btarget"); + env_btaken = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, btaken), + "btaken"); + for (i = 0; i < 16; i++) { + cpu_R[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, regs[i]), + regnames[i]); + } + for (i = 0; i < 16; i++) { + cpu_PR[i] = tcg_global_mem_new(TCG_AREG0, + offsetof(CPUCRISState, pregs[i]), + pregnames[i]); + } -void cpu_state_reset(CPUCRISState *env) -{ - cpu_reset(ENV_GET_CPU(env)); + return cpu; } void restore_state_to_opc(CPUCRISState *env, TranslationBlock *tb, int pc_pos) diff --git a/target-i386/cpu.h b/target-i386/cpu.h index 2460f6348b..bcf663eeb5 100644 --- a/target-i386/cpu.h +++ b/target-i386/cpu.h @@ -787,7 +787,7 @@ typedef struct CPUX86State { #include "cpu-qom.h" -CPUX86State *cpu_x86_init(const char *cpu_model); +X86CPU *cpu_x86_init(const char *cpu_model); int cpu_x86_exec(CPUX86State *s); void x86_cpu_list (FILE *f, fprintf_function cpu_fprintf, const char *optarg); void x86_cpudef_setup(void); @@ -960,7 +960,15 @@ uint64_t cpu_get_tsc(CPUX86State *env); #define TARGET_VIRT_ADDR_SPACE_BITS 32 #endif -#define cpu_init cpu_x86_init +static inline CPUX86State *cpu_init(const char *cpu_model) +{ + X86CPU *cpu = cpu_x86_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + #define cpu_exec cpu_x86_exec #define cpu_gen_code cpu_x86_gen_code #define cpu_signal_handler cpu_x86_signal_handler @@ -1053,8 +1061,8 @@ static inline void cpu_get_tb_cpu_state(CPUX86State *env, target_ulong *pc, (env->eflags & (IOPL_MASK | TF_MASK | RF_MASK | VM_MASK)); } -void do_cpu_init(CPUX86State *env); -void do_cpu_sipi(CPUX86State *env); +void do_cpu_init(X86CPU *cpu); +void do_cpu_sipi(X86CPU *cpu); #define MCE_INJECT_BROADCAST 1 #define MCE_INJECT_UNCOND_AO 2 diff --git a/target-i386/helper.c b/target-i386/helper.c index 3421be2276..2cc80977e8 100644 --- a/target-i386/helper.c +++ b/target-i386/helper.c @@ -26,12 +26,6 @@ //#define DEBUG_MMU -/* NOTE: must be called outside the CPU execute loop */ -void cpu_state_reset(CPUX86State *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} - static void cpu_x86_version(CPUX86State *env, int *family, int *model) { int cpuver = env->cpuid_version; @@ -1157,7 +1151,7 @@ int cpu_x86_get_descr_debug(CPUX86State *env, unsigned int selector, return 1; } -CPUX86State *cpu_x86_init(const char *cpu_model) +X86CPU *cpu_x86_init(const char *cpu_model) { X86CPU *cpu; CPUX86State *env; @@ -1183,31 +1177,34 @@ CPUX86State *cpu_x86_init(const char *cpu_model) x86_cpu_realize(OBJECT(cpu), NULL); - return env; + return cpu; } #if !defined(CONFIG_USER_ONLY) -void do_cpu_init(CPUX86State *env) +void do_cpu_init(X86CPU *cpu) { + CPUX86State *env = &cpu->env; int sipi = env->interrupt_request & CPU_INTERRUPT_SIPI; uint64_t pat = env->pat; - cpu_state_reset(env); + cpu_reset(CPU(cpu)); env->interrupt_request = sipi; env->pat = pat; apic_init_reset(env->apic_state); env->halted = !cpu_is_bsp(env); } -void do_cpu_sipi(CPUX86State *env) +void do_cpu_sipi(X86CPU *cpu) { + CPUX86State *env = &cpu->env; + apic_sipi(env->apic_state); } #else -void do_cpu_init(CPUX86State *env) +void do_cpu_init(X86CPU *cpu) { } -void do_cpu_sipi(CPUX86State *env) +void do_cpu_sipi(X86CPU *cpu) { } #endif diff --git a/target-i386/kvm.c b/target-i386/kvm.c index e74a9e4641..0d0d8f69d3 100644 --- a/target-i386/kvm.c +++ b/target-i386/kvm.c @@ -1698,6 +1698,8 @@ void kvm_arch_post_run(CPUX86State *env, struct kvm_run *run) int kvm_arch_process_async_events(CPUX86State *env) { + X86CPU *cpu = x86_env_get_cpu(env); + if (env->interrupt_request & CPU_INTERRUPT_MCE) { /* We must not raise CPU_INTERRUPT_MCE if it's not supported. */ assert(env->mcg_cap); @@ -1732,11 +1734,11 @@ int kvm_arch_process_async_events(CPUX86State *env) } if (env->interrupt_request & CPU_INTERRUPT_INIT) { kvm_cpu_synchronize_state(env); - do_cpu_init(env); + do_cpu_init(cpu); } if (env->interrupt_request & CPU_INTERRUPT_SIPI) { kvm_cpu_synchronize_state(env); - do_cpu_sipi(env); + do_cpu_sipi(cpu); } if (env->interrupt_request & CPU_INTERRUPT_TPR) { env->interrupt_request &= ~CPU_INTERRUPT_TPR; diff --git a/target-lm32/cpu.c b/target-lm32/cpu.c index 48a5fe3f86..caa4834075 100644 --- a/target-lm32/cpu.c +++ b/target-lm32/cpu.c @@ -18,7 +18,7 @@ * <http://www.gnu.org/licenses/lgpl-2.1.html> */ -#include "cpu-qom.h" +#include "cpu.h" #include "qemu-common.h" diff --git a/target-lm32/cpu.h b/target-lm32/cpu.h index 422a55b063..da80469f51 100644 --- a/target-lm32/cpu.h +++ b/target-lm32/cpu.h @@ -186,7 +186,7 @@ struct CPULM32State { #include "cpu-qom.h" -CPULM32State *cpu_lm32_init(const char *cpu_model); +LM32CPU *cpu_lm32_init(const char *cpu_model); void cpu_lm32_list(FILE *f, fprintf_function cpu_fprintf); int cpu_lm32_exec(CPULM32State *s); void cpu_lm32_close(CPULM32State *s); @@ -199,8 +199,16 @@ int cpu_lm32_signal_handler(int host_signum, void *pinfo, void lm32_translate_init(void); void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value); +static inline CPULM32State *cpu_init(const char *cpu_model) +{ + LM32CPU *cpu = cpu_lm32_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + #define cpu_list cpu_lm32_list -#define cpu_init cpu_lm32_init #define cpu_exec cpu_lm32_exec #define cpu_gen_code cpu_lm32_gen_code #define cpu_signal_handler cpu_lm32_signal_handler diff --git a/target-lm32/helper.c b/target-lm32/helper.c index d0bc1931d8..1ea477fea3 100644 --- a/target-lm32/helper.c +++ b/target-lm32/helper.c @@ -192,7 +192,7 @@ static uint32_t cfg_by_def(const LM32Def *def) return cfg; } -CPULM32State *cpu_lm32_init(const char *cpu_model) +LM32CPU *cpu_lm32_init(const char *cpu_model) { LM32CPU *cpu; CPULM32State *env; @@ -219,7 +219,7 @@ CPULM32State *cpu_lm32_init(const char *cpu_model) lm32_translate_init(); } - return env; + return cpu; } /* Some soc ignores the MSB on the address bus. Thus creating a shadow memory @@ -233,9 +233,3 @@ void cpu_lm32_set_phys_msb_ignore(CPULM32State *env, int value) env->flags &= ~LM32_FLAG_IGNORE_MSB; } } - -void cpu_state_reset(CPULM32State *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} - diff --git a/target-m68k/helper.c b/target-m68k/helper.c index f428375d7d..eac0053c5d 100644 --- a/target-m68k/helper.c +++ b/target-m68k/helper.c @@ -98,11 +98,6 @@ static int fpu_gdb_set_reg(CPUM68KState *env, uint8_t *mem_buf, int n) return 0; } -void cpu_state_reset(CPUM68KState *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} - CPUM68KState *cpu_m68k_init(const char *cpu_model) { M68kCPU *cpu; diff --git a/target-microblaze/cpu.h b/target-microblaze/cpu.h index b0ba9fe296..4968c244e8 100644 --- a/target-microblaze/cpu.h +++ b/target-microblaze/cpu.h @@ -272,7 +272,7 @@ struct CPUMBState { #include "cpu-qom.h" -CPUMBState *cpu_mb_init(const char *cpu_model); +MicroBlazeCPU *cpu_mb_init(const char *cpu_model); int cpu_mb_exec(CPUMBState *s); void cpu_mb_close(CPUMBState *s); void do_interrupt(CPUMBState *env); @@ -295,7 +295,15 @@ enum { #define TARGET_PHYS_ADDR_SPACE_BITS 32 #define TARGET_VIRT_ADDR_SPACE_BITS 32 -#define cpu_init cpu_mb_init +static inline CPUMBState *cpu_init(const char *cpu_model) +{ + MicroBlazeCPU *cpu = cpu_mb_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + #define cpu_exec cpu_mb_exec #define cpu_gen_code cpu_mb_gen_code #define cpu_signal_handler cpu_mb_signal_handler diff --git a/target-microblaze/translate.c b/target-microblaze/translate.c index f0ebd596c0..02b2dc6b96 100644 --- a/target-microblaze/translate.c +++ b/target-microblaze/translate.c @@ -1951,21 +1951,20 @@ void cpu_dump_state (CPUMBState *env, FILE *f, fprintf_function cpu_fprintf, cpu_fprintf(f, "\n\n"); } -CPUMBState *cpu_mb_init (const char *cpu_model) +MicroBlazeCPU *cpu_mb_init(const char *cpu_model) { MicroBlazeCPU *cpu; - CPUMBState *env; static int tcg_initialized = 0; int i; cpu = MICROBLAZE_CPU(object_new(TYPE_MICROBLAZE_CPU)); - env = &cpu->env; cpu_reset(CPU(cpu)); - qemu_init_vcpu(env); + qemu_init_vcpu(&cpu->env); - if (tcg_initialized) - return env; + if (tcg_initialized) { + return cpu; + } tcg_initialized = 1; @@ -1999,12 +1998,7 @@ CPUMBState *cpu_mb_init (const char *cpu_model) #define GEN_HELPER 2 #include "helper.h" - return env; -} - -void cpu_state_reset(CPUMBState *env) -{ - cpu_reset(ENV_GET_CPU(env)); + return cpu; } void restore_state_to_opc(CPUMBState *env, TranslationBlock *tb, int pc_pos) diff --git a/target-mips/cpu.h b/target-mips/cpu.h index 44c1152a3a..ce3467f140 100644 --- a/target-mips/cpu.h +++ b/target-mips/cpu.h @@ -496,7 +496,6 @@ void cpu_unassigned_access(CPUMIPSState *env, target_phys_addr_t addr, void mips_cpu_list (FILE *f, fprintf_function cpu_fprintf); -#define cpu_init cpu_mips_init #define cpu_exec cpu_mips_exec #define cpu_gen_code cpu_mips_gen_code #define cpu_signal_handler cpu_mips_signal_handler @@ -626,9 +625,21 @@ enum { #define CPU_INTERRUPT_WAKE CPU_INTERRUPT_TGT_INT_0 int cpu_mips_exec(CPUMIPSState *s); -CPUMIPSState *cpu_mips_init(const char *cpu_model); +MIPSCPU *cpu_mips_init(const char *cpu_model); int cpu_mips_signal_handler(int host_signum, void *pinfo, void *puc); +static inline CPUMIPSState *cpu_init(const char *cpu_model) +{ + MIPSCPU *cpu = cpu_mips_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + +/* TODO QOM'ify CPU reset and remove */ +void cpu_state_reset(CPUMIPSState *s); + /* mips_timer.c */ uint32_t cpu_mips_get_random (CPUMIPSState *env); uint32_t cpu_mips_get_count (CPUMIPSState *env); diff --git a/target-mips/helper.c b/target-mips/helper.c index ddf9cb72f4..4208bb20c8 100644 --- a/target-mips/helper.c +++ b/target-mips/helper.c @@ -399,6 +399,7 @@ static void set_hflags_for_handler (CPUMIPSState *env) void do_interrupt (CPUMIPSState *env) { #if !defined(CONFIG_USER_ONLY) + MIPSCPU *cpu = mips_env_get_cpu(env); target_ulong offset; int cause = -1; const char *name; @@ -452,7 +453,7 @@ void do_interrupt (CPUMIPSState *env) set_hflags_for_handler(env); break; case EXCP_RESET: - cpu_state_reset(env); + cpu_reset(CPU(cpu)); break; case EXCP_SRESET: env->CP0_Status |= (1 << CP0St_SR); diff --git a/target-mips/translate.c b/target-mips/translate.c index 0c563eedfa..4e15ee36b8 100644 --- a/target-mips/translate.c +++ b/target-mips/translate.c @@ -12689,7 +12689,7 @@ static void mips_tcg_init(void) #include "translate_init.c" -CPUMIPSState *cpu_mips_init (const char *cpu_model) +MIPSCPU *cpu_mips_init(const char *cpu_model) { MIPSCPU *cpu; CPUMIPSState *env; @@ -12709,9 +12709,9 @@ CPUMIPSState *cpu_mips_init (const char *cpu_model) fpu_init(env, def); mvp_init(env, def); mips_tcg_init(); - cpu_state_reset(env); + cpu_reset(CPU(cpu)); qemu_init_vcpu(env); - return env; + return cpu; } void cpu_state_reset(CPUMIPSState *env) diff --git a/target-ppc/cpu.h b/target-ppc/cpu.h index 84c9674157..77a28580af 100644 --- a/target-ppc/cpu.h +++ b/target-ppc/cpu.h @@ -1099,7 +1099,7 @@ struct mmu_ctx_t { #include "cpu-qom.h" /*****************************************************************************/ -CPUPPCState *cpu_ppc_init (const char *cpu_model); +PowerPCCPU *cpu_ppc_init(const char *cpu_model); void ppc_translate_init(void); int cpu_ppc_exec (CPUPPCState *s); /* you can call this signal handler from your SIGBUS and SIGSEGV @@ -1214,7 +1214,15 @@ static inline uint64_t ppc_dump_gpr(CPUPPCState *env, int gprn) int ppc_dcr_read (ppc_dcr_t *dcr_env, int dcrn, uint32_t *valp); int ppc_dcr_write (ppc_dcr_t *dcr_env, int dcrn, uint32_t val); -#define cpu_init cpu_ppc_init +static inline CPUPPCState *cpu_init(const char *cpu_model) +{ + PowerPCCPU *cpu = cpu_ppc_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + #define cpu_exec cpu_ppc_exec #define cpu_gen_code cpu_ppc_gen_code #define cpu_signal_handler cpu_ppc_signal_handler diff --git a/target-ppc/helper.c b/target-ppc/helper.c index e97e49640d..f556f8567a 100644 --- a/target-ppc/helper.c +++ b/target-ppc/helper.c @@ -3186,12 +3186,7 @@ void cpu_dump_rfi (target_ulong RA, target_ulong msr) TARGET_FMT_lx "\n", RA, msr); } -void cpu_state_reset(CPUPPCState *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} - -CPUPPCState *cpu_ppc_init (const char *cpu_model) +PowerPCCPU *cpu_ppc_init(const char *cpu_model) { PowerPCCPU *cpu; CPUPPCState *env; @@ -3213,5 +3208,5 @@ CPUPPCState *cpu_ppc_init (const char *cpu_model) qemu_init_vcpu(env); - return env; + return cpu; } diff --git a/target-s390x/helper.c b/target-s390x/helper.c index 209a69603c..a34a35b536 100644 --- a/target-s390x/helper.c +++ b/target-s390x/helper.c @@ -106,14 +106,7 @@ int cpu_s390x_handle_mmu_fault (CPUS390XState *env, target_ulong address, int rw return 1; } -#endif /* CONFIG_USER_ONLY */ - -void cpu_state_reset(CPUS390XState *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} - -#ifndef CONFIG_USER_ONLY +#else /* !CONFIG_USER_ONLY */ /* Ensure to exit the TB after this call! */ static void trigger_pgm_exception(CPUS390XState *env, uint32_t code, uint32_t ilc) diff --git a/target-sh4/cpu.h b/target-sh4/cpu.h index b6768f1648..bf592227ee 100644 --- a/target-sh4/cpu.h +++ b/target-sh4/cpu.h @@ -191,7 +191,7 @@ typedef struct CPUSH4State { #include "cpu-qom.h" -CPUSH4State *cpu_sh4_init(const char *cpu_model); +SuperHCPU *cpu_sh4_init(const char *cpu_model); int cpu_sh4_exec(CPUSH4State * s); int cpu_sh4_signal_handler(int host_signum, void *pinfo, void *puc); @@ -232,7 +232,15 @@ void cpu_load_tlb(CPUSH4State * env); #include "softfloat.h" -#define cpu_init cpu_sh4_init +static inline CPUSH4State *cpu_init(const char *cpu_model) +{ + SuperHCPU *cpu = cpu_sh4_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + #define cpu_exec cpu_sh4_exec #define cpu_gen_code cpu_sh4_gen_code #define cpu_signal_handler cpu_sh4_signal_handler diff --git a/target-sh4/translate.c b/target-sh4/translate.c index d25f0c5a29..6532ad2ade 100644 --- a/target-sh4/translate.c +++ b/target-sh4/translate.c @@ -178,11 +178,6 @@ void cpu_dump_state(CPUSH4State * env, FILE * f, } } -void cpu_state_reset(CPUSH4State *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} - typedef struct { const char *name; int id; @@ -247,7 +242,7 @@ static void cpu_register(CPUSH4State *env, const sh4_def_t *def) env->id = def->id; } -CPUSH4State *cpu_sh4_init(const char *cpu_model) +SuperHCPU *cpu_sh4_init(const char *cpu_model) { SuperHCPU *cpu; CPUSH4State *env; @@ -264,7 +259,7 @@ CPUSH4State *cpu_sh4_init(const char *cpu_model) cpu_reset(CPU(cpu)); cpu_register(env, def); qemu_init_vcpu(env); - return env; + return cpu; } static void gen_goto_tb(DisasContext * ctx, int n, target_ulong dest) diff --git a/target-sparc/cpu.c b/target-sparc/cpu.c index 7ac6bdb058..f7c004c7d8 100644 --- a/target-sparc/cpu.c +++ b/target-sparc/cpu.c @@ -23,11 +23,6 @@ static int cpu_sparc_find_by_name(sparc_def_t *cpu_def, const char *cpu_model); -void cpu_state_reset(CPUSPARCState *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} - /* CPUClass::reset() */ static void sparc_cpu_reset(CPUState *s) { @@ -111,7 +106,7 @@ static int cpu_sparc_register(CPUSPARCState *env, const char *cpu_model) return 0; } -CPUSPARCState *cpu_sparc_init(const char *cpu_model) +SPARCCPU *cpu_sparc_init(const char *cpu_model) { SPARCCPU *cpu; CPUSPARCState *env; @@ -129,7 +124,7 @@ CPUSPARCState *cpu_sparc_init(const char *cpu_model) } qemu_init_vcpu(env); - return env; + return cpu; } void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu) diff --git a/target-sparc/cpu.h b/target-sparc/cpu.h index 29c63c711f..e16b7b3515 100644 --- a/target-sparc/cpu.h +++ b/target-sparc/cpu.h @@ -511,9 +511,11 @@ struct CPUSPARCState { uint32_t cache_control; }; +#include "cpu-qom.h" + #ifndef NO_CPU_IO_DEFS /* cpu_init.c */ -CPUSPARCState *cpu_sparc_init(const char *cpu_model); +SPARCCPU *cpu_sparc_init(const char *cpu_model); void cpu_sparc_set_id(CPUSPARCState *env, unsigned int cpu); void sparc_cpu_list(FILE *f, fprintf_function cpu_fprintf); /* mmu_helper.c */ @@ -590,7 +592,17 @@ target_phys_addr_t cpu_get_phys_page_nofault(CPUSPARCState *env, target_ulong ad #endif int cpu_sparc_signal_handler(int host_signum, void *pinfo, void *puc); -#define cpu_init cpu_sparc_init +#ifndef NO_CPU_IO_DEFS +static inline CPUSPARCState *cpu_init(const char *cpu_model) +{ + SPARCCPU *cpu = cpu_sparc_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} +#endif + #define cpu_exec cpu_sparc_exec #define cpu_gen_code cpu_sparc_gen_code #define cpu_signal_handler cpu_sparc_signal_handler @@ -691,7 +703,6 @@ static inline void cpu_clone_regs(CPUSPARCState *env, target_ulong newsp) #endif #include "cpu-all.h" -#include "cpu-qom.h" #ifdef TARGET_SPARC64 /* sun4u.c */ diff --git a/target-xtensa/cpu.c b/target-xtensa/cpu.c index 97deacb478..9d01983d44 100644 --- a/target-xtensa/cpu.c +++ b/target-xtensa/cpu.c @@ -28,7 +28,7 @@ * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. */ -#include "cpu-qom.h" +#include "cpu.h" #include "qemu-common.h" diff --git a/target-xtensa/cpu.h b/target-xtensa/cpu.h index 6d0ea7c038..81f7833039 100644 --- a/target-xtensa/cpu.h +++ b/target-xtensa/cpu.h @@ -344,13 +344,24 @@ typedef struct CPUXtensaState { CPU_COMMON } CPUXtensaState; -#define cpu_init cpu_xtensa_init +#include "cpu-qom.h" + #define cpu_exec cpu_xtensa_exec #define cpu_gen_code cpu_xtensa_gen_code #define cpu_signal_handler cpu_xtensa_signal_handler #define cpu_list xtensa_cpu_list -CPUXtensaState *cpu_xtensa_init(const char *cpu_model); +XtensaCPU *cpu_xtensa_init(const char *cpu_model); + +static inline CPUXtensaState *cpu_init(const char *cpu_model) +{ + XtensaCPU *cpu = cpu_xtensa_init(cpu_model); + if (cpu == NULL) { + return NULL; + } + return &cpu->env; +} + void xtensa_translate_init(void); int cpu_xtensa_exec(CPUXtensaState *s); void xtensa_register_core(XtensaConfigList *node); @@ -471,7 +482,6 @@ static inline void cpu_get_tb_cpu_state(CPUXtensaState *env, target_ulong *pc, } #include "cpu-all.h" -#include "cpu-qom.h" #include "exec-all.h" static inline int cpu_has_work(CPUXtensaState *env) diff --git a/target-xtensa/helper.c b/target-xtensa/helper.c index 2094227843..5e7e72e113 100644 --- a/target-xtensa/helper.c +++ b/target-xtensa/helper.c @@ -33,11 +33,6 @@ #include "hw/loader.h" #endif -void cpu_state_reset(CPUXtensaState *env) -{ - cpu_reset(ENV_GET_CPU(env)); -} - static struct XtensaConfigList *xtensa_cores; void xtensa_register_core(XtensaConfigList *node) @@ -80,7 +75,7 @@ static void breakpoint_handler(CPUXtensaState *env) } } -CPUXtensaState *cpu_xtensa_init(const char *cpu_model) +XtensaCPU *cpu_xtensa_init(const char *cpu_model) { static int tcg_inited; static int debug_handler_inited; @@ -116,7 +111,7 @@ CPUXtensaState *cpu_xtensa_init(const char *cpu_model) xtensa_irq_init(env); qemu_init_vcpu(env); - return env; + return cpu; } |