diff options
Diffstat (limited to 'hw/apb_pci.c')
| -rw-r--r-- | hw/apb_pci.c | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/hw/apb_pci.c b/hw/apb_pci.c index f2ed136fda..fe8faa6d05 100644 --- a/hw/apb_pci.c +++ b/hw/apb_pci.c @@ -182,6 +182,25 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level) qemu_set_irq(pic[irq_num], level); } +static void apb_pci_bridge_init(PCIBus *b) +{ + PCIDevice *dev = pci_bridge_get_device(b); + + /* + * command register: + * According to PCI bridge spec, after reset + * bus master bit is off + * memory space enable bit is off + * According to manual (805-1251.pdf). + * the reset value should be zero unless the boot pin is tied high + * (which is true) and thus it should be PCI_COMMAND_MEMORY. + */ + pci_set_word(dev->config + PCI_COMMAND, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); + dev->config[PCI_LATENCY_TIMER] = 0x10; + dev->config[PCI_HEADER_TYPE] |= PCI_HEADER_TYPE_MULTI_FUNCTION; +} + PCIBus *pci_apb_init(target_phys_addr_t special_base, target_phys_addr_t mem_base, qemu_irq *pic, PCIBus **bus2, PCIBus **bus3) @@ -212,10 +231,13 @@ PCIBus *pci_apb_init(target_phys_addr_t special_base, PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 1"); + apb_pci_bridge_init(*bus2); + *bus3 = pci_bridge_init(d->host_state.bus, PCI_DEVFN(1, 1), PCI_VENDOR_ID_SUN, PCI_DEVICE_ID_SUN_SIMBA, pci_apb_map_irq, "Advanced PCI Bus secondary bridge 2"); + apb_pci_bridge_init(*bus3); return d->host_state.bus; } |