diff options
Diffstat (limited to 'hw/arm')
| -rw-r--r-- | hw/arm/boot.c | 6 | ||||
| -rw-r--r-- | hw/arm/highbank.c | 12 | ||||
| -rw-r--r-- | hw/arm/pxa2xx.c | 2 |
3 files changed, 14 insertions, 6 deletions
diff --git a/hw/arm/boot.c b/hw/arm/boot.c index a48d1b28d4..fa6950352c 100644 --- a/hw/arm/boot.c +++ b/hw/arm/boot.c @@ -170,7 +170,8 @@ static void default_reset_secondary(ARMCPU *cpu, { CPUARMState *env = &cpu->env; - stl_phys_notdirty(&address_space_memory, info->smp_bootreg_addr, 0); + address_space_stl_notdirty(&address_space_memory, info->smp_bootreg_addr, + 0, MEMTXATTRS_UNSPECIFIED, NULL); env->regs[15] = info->smp_loader_start; } @@ -180,7 +181,8 @@ static inline bool have_dtb(const struct arm_boot_info *info) } #define WRITE_WORD(p, value) do { \ - stl_phys_notdirty(&address_space_memory, p, value); \ + address_space_stl_notdirty(&address_space_memory, p, value, \ + MEMTXATTRS_UNSPECIFIED, NULL); \ p += 4; \ } while (0) diff --git a/hw/arm/highbank.c b/hw/arm/highbank.c index dd2a67bcf0..b2d048b911 100644 --- a/hw/arm/highbank.c +++ b/hw/arm/highbank.c @@ -69,11 +69,17 @@ static void hb_reset_secondary(ARMCPU *cpu, const struct arm_boot_info *info) switch (info->nb_cpus) { case 4: - stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x30, 0); + address_space_stl_notdirty(&address_space_memory, + SMP_BOOT_REG + 0x30, 0, + MEMTXATTRS_UNSPECIFIED, NULL); case 3: - stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x20, 0); + address_space_stl_notdirty(&address_space_memory, + SMP_BOOT_REG + 0x20, 0, + MEMTXATTRS_UNSPECIFIED, NULL); case 2: - stl_phys_notdirty(&address_space_memory, SMP_BOOT_REG + 0x10, 0); + address_space_stl_notdirty(&address_space_memory, + SMP_BOOT_REG + 0x10, 0, + MEMTXATTRS_UNSPECIFIED, NULL); env->regs[15] = SMP_BOOT_ADDR; break; default: diff --git a/hw/arm/pxa2xx.c b/hw/arm/pxa2xx.c index 165ba2a169..f921a5680c 100644 --- a/hw/arm/pxa2xx.c +++ b/hw/arm/pxa2xx.c @@ -274,7 +274,7 @@ static void pxa2xx_pwrmode_write(CPUARMState *env, const ARMCPRegInfo *ri, s->cpu->env.uncached_cpsr = ARM_CPU_MODE_SVC; s->cpu->env.daif = PSTATE_A | PSTATE_F | PSTATE_I; s->cpu->env.cp15.sctlr_ns = 0; - s->cpu->env.cp15.c1_coproc = 0; + s->cpu->env.cp15.cpacr_el1 = 0; s->cpu->env.cp15.ttbr0_el[1] = 0; s->cpu->env.cp15.dacr_ns = 0; s->pm_regs[PSSR >> 2] |= 0x8; /* Set STS */ |