diff options
Diffstat (limited to 'hw/arm_timer.c')
| -rw-r--r-- | hw/arm_timer.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/hw/arm_timer.c b/hw/arm_timer.c index c93f333d7a..0eff7b9482 100644 --- a/hw/arm_timer.c +++ b/hw/arm_timer.c @@ -62,8 +62,7 @@ static uint32_t arm_timer_read(void *opaque, target_phys_addr_t offset) return 0; return s->int_level; default: - cpu_abort (cpu_single_env, "arm_timer_read: Bad offset %x\n", - (int)offset); + hw_error("arm_timer_read: Bad offset %x\n", (int)offset); return 0; } } @@ -130,8 +129,7 @@ static void arm_timer_write(void *opaque, target_phys_addr_t offset, arm_timer_recalibrate(s, 0); break; default: - cpu_abort (cpu_single_env, "arm_timer_write: Bad offset %x\n", - (int)offset); + hw_error("arm_timer_write: Bad offset %x\n", (int)offset); } arm_timer_update(s); } @@ -290,8 +288,9 @@ static uint32_t icp_pit_read(void *opaque, target_phys_addr_t offset) /* ??? Don't know the PrimeCell ID for this device. */ n = offset >> 8; - if (n > 3) - cpu_abort(cpu_single_env, "sp804_read: Bad timer %d\n", n); + if (n > 3) { + hw_error("sp804_read: Bad timer %d\n", n); + } return arm_timer_read(s->timer[n], offset & 0xff); } @@ -303,8 +302,9 @@ static void icp_pit_write(void *opaque, target_phys_addr_t offset, int n; n = offset >> 8; - if (n > 3) - cpu_abort(cpu_single_env, "sp804_write: Bad timer %d\n", n); + if (n > 3) { + hw_error("sp804_write: Bad timer %d\n", n); + } arm_timer_write(s->timer[n], offset & 0xff, value); } |