diff options
Diffstat (limited to 'hw/char')
| -rw-r--r-- | hw/char/Kconfig | 4 | ||||
| -rw-r--r-- | hw/char/meson.build | 1 | ||||
| -rw-r--r-- | hw/char/omap_uart.c | 2 | ||||
| -rw-r--r-- | hw/char/riscv_htif.c | 1 | ||||
| -rw-r--r-- | hw/char/serial-isa.c | 1 | ||||
| -rw-r--r-- | hw/char/serial-mm.c | 157 | ||||
| -rw-r--r-- | hw/char/serial.c | 126 |
7 files changed, 164 insertions, 128 deletions
diff --git a/hw/char/Kconfig b/hw/char/Kconfig index 4fd74ea878..4b73a803bf 100644 --- a/hw/char/Kconfig +++ b/hw/char/Kconfig @@ -21,6 +21,10 @@ config SERIAL_ISA depends on ISA_BUS select SERIAL +config SERIAL_MM + bool + select SERIAL + config SERIAL_PCI bool default y if PCI_DEVICES diff --git a/hw/char/meson.build b/hw/char/meson.build index a4c4c5ff0f..1750834385 100644 --- a/hw/char/meson.build +++ b/hw/char/meson.build @@ -13,6 +13,7 @@ system_ss.add(when: 'CONFIG_PL011', if_true: files('pl011.c')) system_ss.add(when: 'CONFIG_SCLPCONSOLE', if_true: files('sclpconsole.c', 'sclpconsole-lm.c')) system_ss.add(when: 'CONFIG_SERIAL', if_true: files('serial.c')) system_ss.add(when: 'CONFIG_SERIAL_ISA', if_true: files('serial-isa.c')) +system_ss.add(when: 'CONFIG_SERIAL_MM', if_true: files('serial-mm.c')) system_ss.add(when: 'CONFIG_SERIAL_PCI', if_true: files('serial-pci.c')) system_ss.add(when: 'CONFIG_SERIAL_PCI_MULTI', if_true: files('serial-pci-multi.c')) system_ss.add(when: 'CONFIG_SHAKTI_UART', if_true: files('shakti_uart.c')) diff --git a/hw/char/omap_uart.c b/hw/char/omap_uart.c index d789c253b4..07fb868965 100644 --- a/hw/char/omap_uart.c +++ b/hw/char/omap_uart.c @@ -20,7 +20,7 @@ #include "qemu/osdep.h" #include "chardev/char.h" #include "hw/arm/omap.h" -#include "hw/char/serial.h" +#include "hw/char/serial-mm.h" #include "exec/address-spaces.h" /* UARTs */ diff --git a/hw/char/riscv_htif.c b/hw/char/riscv_htif.c index 9bef60def1..54fd55c3e6 100644 --- a/hw/char/riscv_htif.c +++ b/hw/char/riscv_htif.c @@ -24,7 +24,6 @@ #include "qapi/error.h" #include "qemu/log.h" #include "hw/char/riscv_htif.h" -#include "hw/char/serial.h" #include "chardev/char.h" #include "chardev/char-fe.h" #include "qemu/timer.h" diff --git a/hw/char/serial-isa.c b/hw/char/serial-isa.c index 329b352b9a..b562ec9d37 100644 --- a/hw/char/serial-isa.c +++ b/hw/char/serial-isa.c @@ -29,6 +29,7 @@ #include "sysemu/sysemu.h" #include "hw/acpi/acpi_aml_interface.h" #include "hw/char/serial.h" +#include "hw/char/serial-isa.h" #include "hw/isa/isa.h" #include "hw/qdev-properties.h" #include "migration/vmstate.h" diff --git a/hw/char/serial-mm.c b/hw/char/serial-mm.c new file mode 100644 index 0000000000..2f67776b19 --- /dev/null +++ b/hw/char/serial-mm.c @@ -0,0 +1,157 @@ +/* + * QEMU 16550A UART emulation + * + * Copyright (c) 2003-2004 Fabrice Bellard + * Copyright (c) 2008 Citrix Systems, Inc. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "hw/char/serial-mm.h" +#include "exec/cpu-common.h" +#include "migration/vmstate.h" +#include "qapi/error.h" +#include "hw/qdev-properties.h" + +static uint64_t serial_mm_read(void *opaque, hwaddr addr, unsigned size) +{ + SerialMM *s = SERIAL_MM(opaque); + return serial_io_ops.read(&s->serial, addr >> s->regshift, 1); +} + +static void serial_mm_write(void *opaque, hwaddr addr, + uint64_t value, unsigned size) +{ + SerialMM *s = SERIAL_MM(opaque); + value &= 255; + serial_io_ops.write(&s->serial, addr >> s->regshift, value, 1); +} + +static const MemoryRegionOps serial_mm_ops[3] = { + [DEVICE_NATIVE_ENDIAN] = { + .read = serial_mm_read, + .write = serial_mm_write, + .endianness = DEVICE_NATIVE_ENDIAN, + .valid.max_access_size = 8, + .impl.max_access_size = 8, + }, + [DEVICE_LITTLE_ENDIAN] = { + .read = serial_mm_read, + .write = serial_mm_write, + .endianness = DEVICE_LITTLE_ENDIAN, + .valid.max_access_size = 8, + .impl.max_access_size = 8, + }, + [DEVICE_BIG_ENDIAN] = { + .read = serial_mm_read, + .write = serial_mm_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid.max_access_size = 8, + .impl.max_access_size = 8, + }, +}; + +static void serial_mm_realize(DeviceState *dev, Error **errp) +{ + SerialMM *smm = SERIAL_MM(dev); + SerialState *s = &smm->serial; + + if (!qdev_realize(DEVICE(s), NULL, errp)) { + return; + } + + memory_region_init_io(&s->io, OBJECT(dev), + &serial_mm_ops[smm->endianness], smm, "serial", + 8 << smm->regshift); + sysbus_init_mmio(SYS_BUS_DEVICE(smm), &s->io); + sysbus_init_irq(SYS_BUS_DEVICE(smm), &smm->serial.irq); +} + +static const VMStateDescription vmstate_serial_mm = { + .name = "serial", + .version_id = 3, + .minimum_version_id = 2, + .fields = (const VMStateField[]) { + VMSTATE_STRUCT(serial, SerialMM, 0, vmstate_serial, SerialState), + VMSTATE_END_OF_LIST() + } +}; + +SerialMM *serial_mm_init(MemoryRegion *address_space, + hwaddr base, int regshift, + qemu_irq irq, int baudbase, + Chardev *chr, enum device_endian end) +{ + SerialMM *smm = SERIAL_MM(qdev_new(TYPE_SERIAL_MM)); + MemoryRegion *mr; + + qdev_prop_set_uint8(DEVICE(smm), "regshift", regshift); + qdev_prop_set_uint32(DEVICE(smm), "baudbase", baudbase); + qdev_prop_set_chr(DEVICE(smm), "chardev", chr); + qdev_set_legacy_instance_id(DEVICE(smm), base, 2); + qdev_prop_set_uint8(DEVICE(smm), "endianness", end); + sysbus_realize_and_unref(SYS_BUS_DEVICE(smm), &error_fatal); + + sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq); + mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0); + memory_region_add_subregion(address_space, base, mr); + + return smm; +} + +static void serial_mm_instance_init(Object *o) +{ + SerialMM *smm = SERIAL_MM(o); + + object_initialize_child(o, "serial", &smm->serial, TYPE_SERIAL); + + qdev_alias_all_properties(DEVICE(&smm->serial), o); +} + +static Property serial_mm_properties[] = { + /* + * Set the spacing between adjacent memory-mapped UART registers. + * Each register will be at (1 << regshift) bytes after the previous one. + */ + DEFINE_PROP_UINT8("regshift", SerialMM, regshift, 0), + DEFINE_PROP_UINT8("endianness", SerialMM, endianness, DEVICE_NATIVE_ENDIAN), + DEFINE_PROP_END_OF_LIST(), +}; + +static void serial_mm_class_init(ObjectClass *oc, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(oc); + + device_class_set_props(dc, serial_mm_properties); + dc->realize = serial_mm_realize; + dc->vmsd = &vmstate_serial_mm; +} + +static const TypeInfo types[] = { + { + .name = TYPE_SERIAL_MM, + .parent = TYPE_SYS_BUS_DEVICE, + .class_init = serial_mm_class_init, + .instance_init = serial_mm_instance_init, + .instance_size = sizeof(SerialMM), + }, +}; + +DEFINE_TYPES(types) diff --git a/hw/char/serial.c b/hw/char/serial.c index 6c5c4a23c7..b50a8a1313 100644 --- a/hw/char/serial.c +++ b/hw/char/serial.c @@ -989,135 +989,9 @@ static const TypeInfo serial_info = { .class_init = serial_class_init, }; -/* Memory mapped interface */ -static uint64_t serial_mm_read(void *opaque, hwaddr addr, - unsigned size) -{ - SerialMM *s = SERIAL_MM(opaque); - return serial_ioport_read(&s->serial, addr >> s->regshift, 1); -} - -static void serial_mm_write(void *opaque, hwaddr addr, - uint64_t value, unsigned size) -{ - SerialMM *s = SERIAL_MM(opaque); - value &= 255; - serial_ioport_write(&s->serial, addr >> s->regshift, value, 1); -} - -static const MemoryRegionOps serial_mm_ops[3] = { - [DEVICE_NATIVE_ENDIAN] = { - .read = serial_mm_read, - .write = serial_mm_write, - .endianness = DEVICE_NATIVE_ENDIAN, - .valid.max_access_size = 8, - .impl.max_access_size = 8, - }, - [DEVICE_LITTLE_ENDIAN] = { - .read = serial_mm_read, - .write = serial_mm_write, - .endianness = DEVICE_LITTLE_ENDIAN, - .valid.max_access_size = 8, - .impl.max_access_size = 8, - }, - [DEVICE_BIG_ENDIAN] = { - .read = serial_mm_read, - .write = serial_mm_write, - .endianness = DEVICE_BIG_ENDIAN, - .valid.max_access_size = 8, - .impl.max_access_size = 8, - }, -}; - -static void serial_mm_realize(DeviceState *dev, Error **errp) -{ - SerialMM *smm = SERIAL_MM(dev); - SerialState *s = &smm->serial; - - if (!qdev_realize(DEVICE(s), NULL, errp)) { - return; - } - - memory_region_init_io(&s->io, OBJECT(dev), - &serial_mm_ops[smm->endianness], smm, "serial", - 8 << smm->regshift); - sysbus_init_mmio(SYS_BUS_DEVICE(smm), &s->io); - sysbus_init_irq(SYS_BUS_DEVICE(smm), &smm->serial.irq); -} - -static const VMStateDescription vmstate_serial_mm = { - .name = "serial", - .version_id = 3, - .minimum_version_id = 2, - .fields = (const VMStateField[]) { - VMSTATE_STRUCT(serial, SerialMM, 0, vmstate_serial, SerialState), - VMSTATE_END_OF_LIST() - } -}; - -SerialMM *serial_mm_init(MemoryRegion *address_space, - hwaddr base, int regshift, - qemu_irq irq, int baudbase, - Chardev *chr, enum device_endian end) -{ - SerialMM *smm = SERIAL_MM(qdev_new(TYPE_SERIAL_MM)); - MemoryRegion *mr; - - qdev_prop_set_uint8(DEVICE(smm), "regshift", regshift); - qdev_prop_set_uint32(DEVICE(smm), "baudbase", baudbase); - qdev_prop_set_chr(DEVICE(smm), "chardev", chr); - qdev_set_legacy_instance_id(DEVICE(smm), base, 2); - qdev_prop_set_uint8(DEVICE(smm), "endianness", end); - sysbus_realize_and_unref(SYS_BUS_DEVICE(smm), &error_fatal); - - sysbus_connect_irq(SYS_BUS_DEVICE(smm), 0, irq); - mr = sysbus_mmio_get_region(SYS_BUS_DEVICE(smm), 0); - memory_region_add_subregion(address_space, base, mr); - - return smm; -} - -static void serial_mm_instance_init(Object *o) -{ - SerialMM *smm = SERIAL_MM(o); - - object_initialize_child(o, "serial", &smm->serial, TYPE_SERIAL); - - qdev_alias_all_properties(DEVICE(&smm->serial), o); -} - -static Property serial_mm_properties[] = { - /* - * Set the spacing between adjacent memory-mapped UART registers. - * Each register will be at (1 << regshift) bytes after the - * previous one. - */ - DEFINE_PROP_UINT8("regshift", SerialMM, regshift, 0), - DEFINE_PROP_UINT8("endianness", SerialMM, endianness, DEVICE_NATIVE_ENDIAN), - DEFINE_PROP_END_OF_LIST(), -}; - -static void serial_mm_class_init(ObjectClass *oc, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(oc); - - device_class_set_props(dc, serial_mm_properties); - dc->realize = serial_mm_realize; - dc->vmsd = &vmstate_serial_mm; -} - -static const TypeInfo serial_mm_info = { - .name = TYPE_SERIAL_MM, - .parent = TYPE_SYS_BUS_DEVICE, - .class_init = serial_mm_class_init, - .instance_init = serial_mm_instance_init, - .instance_size = sizeof(SerialMM), -}; - static void serial_register_types(void) { type_register_static(&serial_info); - type_register_static(&serial_mm_info); } type_init(serial_register_types) |