diff options
Diffstat (limited to 'hw/dma')
| -rw-r--r-- | hw/dma/omap_dma.c | 26 | ||||
| -rw-r--r-- | hw/dma/pl330.c | 2 | ||||
| -rw-r--r-- | hw/dma/pxa2xx_dma.c | 14 | ||||
| -rw-r--r-- | hw/dma/xlnx-zynq-devcfg.c | 2 | ||||
| -rw-r--r-- | hw/dma/xlnx_dpdma.c | 2 |
5 files changed, 23 insertions, 23 deletions
diff --git a/hw/dma/omap_dma.c b/hw/dma/omap_dma.c index 45dfe7aadd..abd18c67ea 100644 --- a/hw/dma/omap_dma.c +++ b/hw/dma/omap_dma.c @@ -161,7 +161,7 @@ static void omap_dma_channel_load(struct omap_dma_channel_s *ch) a->pck_element = 0; if (unlikely(!ch->elements || !ch->frames)) { - printf("%s: bad DMA request\n", __FUNCTION__); + printf("%s: bad DMA request\n", __func__); return; } @@ -519,7 +519,7 @@ static void omap_dma_transfer_setup(struct soc_dma_ch_s *dma) continue; #endif printf("%s: Bus time-out in DMA%i operation\n", - __FUNCTION__, dma->num); + __func__, dma->num); } min_elems = INT_MAX; @@ -879,14 +879,14 @@ static int omap_dma_ch_reg_write(struct omap_dma_s *s, ch->pack[0] = (value & 0x0040) >> 6; ch->port[0] = (enum omap_dma_port) ((value & 0x003c) >> 2); if (ch->port[0] >= __omap_dma_port_last) - printf("%s: invalid DMA port %i\n", __FUNCTION__, + printf("%s: invalid DMA port %i\n", __func__, ch->port[0]); if (ch->port[1] >= __omap_dma_port_last) - printf("%s: invalid DMA port %i\n", __FUNCTION__, + printf("%s: invalid DMA port %i\n", __func__, ch->port[1]); ch->data_type = 1 << (value & 3); if ((value & 3) == 3) { - printf("%s: bad data_type for DMA channel\n", __FUNCTION__); + printf("%s: bad data_type for DMA channel\n", __func__); ch->data_type >>= 1; } break; @@ -1440,7 +1440,7 @@ static int omap_dma_sys_read(struct omap_dma_s *s, int offset, case 0x482: /* DMA_PCh1_SR */ case 0x4c0: /* DMA_PChD_SR_0 */ printf("%s: Physical Channel Status Registers not implemented.\n", - __FUNCTION__); + __func__); *ret = 0xff; break; @@ -1898,13 +1898,13 @@ static void omap_dma4_write(void *opaque, hwaddr addr, omap_dma_reset(s->dma); s->ocp = value & 0x3321; if (((s->ocp >> 12) & 3) == 3) /* MIDLEMODE */ - fprintf(stderr, "%s: invalid DMA power mode\n", __FUNCTION__); + fprintf(stderr, "%s: invalid DMA power mode\n", __func__); return; case 0x78: /* DMA4_GCR */ s->gcr = value & 0x00ff00ff; if ((value & 0xff) == 0x00) /* MAX_CHANNEL_FIFO_DEPTH */ - fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __FUNCTION__); + fprintf(stderr, "%s: wrong FIFO depth in GCR\n", __func__); return; case 0x80 ... 0xfff: @@ -1935,7 +1935,7 @@ static void omap_dma4_write(void *opaque, hwaddr addr, ch->src_sync = (value >> 24) & 1; /* XXX For CamDMA must be 1 */ if (ch->buf_disable && !ch->src_sync) fprintf(stderr, "%s: Buffering disable is not allowed in " - "destination synchronised mode\n", __FUNCTION__); + "destination synchronised mode\n", __func__); ch->prefetch = (value >> 23) & 1; ch->bs = (value >> 18) & 1; ch->transparent_copy = (value >> 17) & 1; @@ -1947,7 +1947,7 @@ static void omap_dma4_write(void *opaque, hwaddr addr, ch->fs = (value & 0x0020) >> 5; if (ch->fs && ch->bs && ch->mode[0] && ch->mode[1]) fprintf(stderr, "%s: For a packet transfer at least one port " - "must be constant-addressed\n", __FUNCTION__); + "must be constant-addressed\n", __func__); ch->sync = (value & 0x001f) | ((value >> 14) & 0x0060); /* XXX must be 0x01 for CamDMA */ @@ -1978,7 +1978,7 @@ static void omap_dma4_write(void *opaque, hwaddr addr, ch->endian_lock[1] =(value >> 18) & 1; if (ch->endian[0] != ch->endian[1]) fprintf(stderr, "%s: DMA endianness conversion enable attempt\n", - __FUNCTION__); + __func__); ch->write_mode = (value >> 16) & 3; ch->burst[1] = (value & 0xc000) >> 14; ch->pack[1] = (value & 0x2000) >> 13; @@ -1988,10 +1988,10 @@ static void omap_dma4_write(void *opaque, hwaddr addr, ch->translate[0] = (value & 0x003c) >> 2; if (ch->translate[0] | ch->translate[1]) fprintf(stderr, "%s: bad MReqAddressTranslate sideband signal\n", - __FUNCTION__); + __func__); ch->data_type = 1 << (value & 3); if ((value & 3) == 3) { - printf("%s: bad data_type for DMA channel\n", __FUNCTION__); + printf("%s: bad data_type for DMA channel\n", __func__); ch->data_type >>= 1; } break; diff --git a/hw/dma/pl330.c b/hw/dma/pl330.c index 32cf8399b8..d071049233 100644 --- a/hw/dma/pl330.c +++ b/hw/dma/pl330.c @@ -29,7 +29,7 @@ if (PL330_ERR_DEBUG >= lvl) {\ fprintf(stderr, "PL330: %s:" fmt, __func__, ## args);\ } \ -} while (0); +} while (0) #define DB_PRINT(fmt, args...) DB_PRINT_L(1, fmt, ## args) diff --git a/hw/dma/pxa2xx_dma.c b/hw/dma/pxa2xx_dma.c index 634a4328f0..f4eb26cf17 100644 --- a/hw/dma/pxa2xx_dma.c +++ b/hw/dma/pxa2xx_dma.c @@ -169,7 +169,7 @@ static inline void pxa2xx_dma_descriptor_fetch( s->chan[ch].dest &= ~3; if (s->chan[ch].cmd & (DCMD_CMPEN | DCMD_FLYBYS | DCMD_FLYBYT)) - printf("%s: unsupported mode in channel %i\n", __FUNCTION__, ch); + printf("%s: unsupported mode in channel %i\n", __func__, ch); if (s->chan[ch].cmd & DCMD_STARTIRQEN) s->chan[ch].state |= DCSR_STARTINTR; @@ -264,7 +264,7 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset, unsigned int channel; if (size != 4) { - hw_error("%s: Bad access width\n", __FUNCTION__); + hw_error("%s: Bad access width\n", __func__); return 5; } @@ -312,7 +312,7 @@ static uint64_t pxa2xx_dma_read(void *opaque, hwaddr offset, } } - hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __FUNCTION__, offset); + hw_error("%s: Bad offset 0x" TARGET_FMT_plx "\n", __func__, offset); return 7; } @@ -323,7 +323,7 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset, unsigned int channel; if (size != 4) { - hw_error("%s: Bad access width\n", __FUNCTION__); + hw_error("%s: Bad access width\n", __func__); return; } @@ -337,7 +337,7 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset, if (value & DRCMR_MAPVLD) if ((value & DRCMR_CHLNUM) > s->channels) hw_error("%s: Bad DMA channel %i\n", - __FUNCTION__, (unsigned)value & DRCMR_CHLNUM); + __func__, (unsigned)value & DRCMR_CHLNUM); s->req[channel] = value; break; @@ -416,7 +416,7 @@ static void pxa2xx_dma_write(void *opaque, hwaddr offset, break; } fail: - hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __FUNCTION__, offset); + hw_error("%s: Bad offset " TARGET_FMT_plx "\n", __func__, offset); } } @@ -431,7 +431,7 @@ static void pxa2xx_dma_request(void *opaque, int req_num, int on) PXA2xxDMAState *s = opaque; int ch; if (req_num < 0 || req_num >= PXA2XX_DMA_NUM_REQUESTS) - hw_error("%s: Bad DMA request %i\n", __FUNCTION__, req_num); + hw_error("%s: Bad DMA request %i\n", __func__, req_num); if (!(s->req[req_num] & DRCMR_MAPVLD)) return; diff --git a/hw/dma/xlnx-zynq-devcfg.c b/hw/dma/xlnx-zynq-devcfg.c index 3b10523430..12bb2e3716 100644 --- a/hw/dma/xlnx-zynq-devcfg.c +++ b/hw/dma/xlnx-zynq-devcfg.c @@ -43,7 +43,7 @@ if (XLNX_ZYNQ_DEVCFG_ERR_DEBUG) { \ qemu_log("%s: " fmt, __func__, ## args); \ } \ -} while (0); +} while (0) REG32(CTRL, 0x00) FIELD(CTRL, FORCE_RST, 31, 1) /* Not supported, wr ignored */ diff --git a/hw/dma/xlnx_dpdma.c b/hw/dma/xlnx_dpdma.c index 8ceb21ddb3..077c7da9cc 100644 --- a/hw/dma/xlnx_dpdma.c +++ b/hw/dma/xlnx_dpdma.c @@ -34,7 +34,7 @@ if (DEBUG_DPDMA) { \ qemu_log("xlnx_dpdma: " fmt , ## __VA_ARGS__); \ } \ -} while (0); +} while (0) /* * Registers offset for DPDMA. |