diff options
Diffstat (limited to 'hw/hppa')
| -rw-r--r-- | hw/hppa/Kconfig | 5 | ||||
| -rw-r--r-- | hw/hppa/dino.c | 608 | ||||
| -rw-r--r-- | hw/hppa/hppa_hardware.h | 5 | ||||
| -rw-r--r-- | hw/hppa/hppa_sys.h | 24 | ||||
| -rw-r--r-- | hw/hppa/lasi.c | 367 | ||||
| -rw-r--r-- | hw/hppa/machine.c | 124 | ||||
| -rw-r--r-- | hw/hppa/meson.build | 2 | ||||
| -rw-r--r-- | hw/hppa/pci.c | 88 | ||||
| -rw-r--r-- | hw/hppa/trace-events | 14 |
9 files changed, 105 insertions, 1132 deletions
diff --git a/hw/hppa/Kconfig b/hw/hppa/Kconfig index 22948db025..5dd8b5b21e 100644 --- a/hw/hppa/Kconfig +++ b/hw/hppa/Kconfig @@ -1,9 +1,10 @@ -config DINO +config HPPA_B160L bool imply PCI_DEVICES imply E1000_PCI imply VIRTIO_VGA - select PCI + select DINO + select LASI select SERIAL select ISA_BUS select I8259 diff --git a/hw/hppa/dino.c b/hw/hppa/dino.c deleted file mode 100644 index eab96dd84e..0000000000 --- a/hw/hppa/dino.c +++ /dev/null @@ -1,608 +0,0 @@ -/* - * HP-PARISC Dino PCI chipset emulation, as in B160L and similiar machines - * - * (C) 2017-2019 by Helge Deller <deller@gmx.de> - * - * This work is licensed under the GNU GPL license version 2 or later. - * - * Documentation available at: - * https://parisc.wiki.kernel.org/images-parisc/9/91/Dino_ers.pdf - * https://parisc.wiki.kernel.org/images-parisc/7/70/Dino_3_1_Errata.pdf - */ - -#include "qemu/osdep.h" -#include "qemu/module.h" -#include "qemu/units.h" -#include "qapi/error.h" -#include "hw/irq.h" -#include "hw/pci/pci.h" -#include "hw/pci/pci_bus.h" -#include "migration/vmstate.h" -#include "hppa_sys.h" -#include "trace.h" -#include "qom/object.h" - - -#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" - -#define DINO_IAR0 0x004 -#define DINO_IODC 0x008 -#define DINO_IRR0 0x00C /* RO */ -#define DINO_IAR1 0x010 -#define DINO_IRR1 0x014 /* RO */ -#define DINO_IMR 0x018 -#define DINO_IPR 0x01C -#define DINO_TOC_ADDR 0x020 -#define DINO_ICR 0x024 -#define DINO_ILR 0x028 /* RO */ -#define DINO_IO_COMMAND 0x030 /* WO */ -#define DINO_IO_STATUS 0x034 /* RO */ -#define DINO_IO_CONTROL 0x038 -#define DINO_IO_GSC_ERR_RESP 0x040 /* RO */ -#define DINO_IO_ERR_INFO 0x044 /* RO */ -#define DINO_IO_PCI_ERR_RESP 0x048 /* RO */ -#define DINO_IO_FBB_EN 0x05c -#define DINO_IO_ADDR_EN 0x060 -#define DINO_PCI_CONFIG_ADDR 0x064 -#define DINO_PCI_CONFIG_DATA 0x068 -#define DINO_PCI_IO_DATA 0x06c -#define DINO_PCI_MEM_DATA 0x070 /* Dino 3.x only */ -#define DINO_GSC2X_CONFIG 0x7b4 /* RO */ -#define DINO_GMASK 0x800 -#define DINO_PAMR 0x804 -#define DINO_PAPR 0x808 -#define DINO_DAMODE 0x80c -#define DINO_PCICMD 0x810 -#define DINO_PCISTS 0x814 /* R/WC */ -#define DINO_MLTIM 0x81c -#define DINO_BRDG_FEAT 0x820 -#define DINO_PCIROR 0x824 -#define DINO_PCIWOR 0x828 -#define DINO_TLTIM 0x830 - -#define DINO_IRQS 11 /* bits 0-10 are architected */ -#define DINO_IRR_MASK 0x5ff /* only 10 bits are implemented */ -#define DINO_LOCAL_IRQS (DINO_IRQS + 1) -#define DINO_MASK_IRQ(x) (1 << (x)) - -#define PCIINTA 0x001 -#define PCIINTB 0x002 -#define PCIINTC 0x004 -#define PCIINTD 0x008 -#define PCIINTE 0x010 -#define PCIINTF 0x020 -#define GSCEXTINT 0x040 -/* #define xxx 0x080 - bit 7 is "default" */ -/* #define xxx 0x100 - bit 8 not used */ -/* #define xxx 0x200 - bit 9 not used */ -#define RS232INT 0x400 - -#define DINO_MEM_CHUNK_SIZE (8 * MiB) - -OBJECT_DECLARE_SIMPLE_TYPE(DinoState, DINO_PCI_HOST_BRIDGE) - -#define DINO800_REGS (1 + (DINO_TLTIM - DINO_GMASK) / 4) -static const uint32_t reg800_keep_bits[DINO800_REGS] = { - MAKE_64BIT_MASK(0, 1), /* GMASK */ - MAKE_64BIT_MASK(0, 7), /* PAMR */ - MAKE_64BIT_MASK(0, 7), /* PAPR */ - MAKE_64BIT_MASK(0, 8), /* DAMODE */ - MAKE_64BIT_MASK(0, 7), /* PCICMD */ - MAKE_64BIT_MASK(0, 9), /* PCISTS */ - MAKE_64BIT_MASK(0, 32), /* Undefined */ - MAKE_64BIT_MASK(0, 8), /* MLTIM */ - MAKE_64BIT_MASK(0, 30), /* BRDG_FEAT */ - MAKE_64BIT_MASK(0, 24), /* PCIROR */ - MAKE_64BIT_MASK(0, 22), /* PCIWOR */ - MAKE_64BIT_MASK(0, 32), /* Undocumented */ - MAKE_64BIT_MASK(0, 9), /* TLTIM */ -}; - -struct DinoState { - PCIHostState parent_obj; - - /* PCI_CONFIG_ADDR is parent_obj.config_reg, via pci_host_conf_be_ops, - so that we can map PCI_CONFIG_DATA to pci_host_data_be_ops. */ - uint32_t config_reg_dino; /* keep original copy, including 2 lowest bits */ - - uint32_t iar0; - uint32_t iar1; - uint32_t imr; - uint32_t ipr; - uint32_t icr; - uint32_t ilr; - uint32_t io_fbb_en; - uint32_t io_addr_en; - uint32_t io_control; - uint32_t toc_addr; - - uint32_t reg800[DINO800_REGS]; - - MemoryRegion this_mem; - MemoryRegion pci_mem; - MemoryRegion pci_mem_alias[32]; - - AddressSpace bm_as; - MemoryRegion bm; - MemoryRegion bm_ram_alias; - MemoryRegion bm_pci_alias; - MemoryRegion bm_cpu_alias; -}; - -/* - * Dino can forward memory accesses from the CPU in the range between - * 0xf0800000 and 0xff000000 to the PCI bus. - */ -static void gsc_to_pci_forwarding(DinoState *s) -{ - uint32_t io_addr_en, tmp; - int enabled, i; - - tmp = extract32(s->io_control, 7, 2); - enabled = (tmp == 0x01); - io_addr_en = s->io_addr_en; - /* Mask out first (=firmware) and last (=Dino) areas. */ - io_addr_en &= ~(BIT(31) | BIT(0)); - - memory_region_transaction_begin(); - for (i = 1; i < 31; i++) { - MemoryRegion *mem = &s->pci_mem_alias[i]; - if (enabled && (io_addr_en & (1U << i))) { - if (!memory_region_is_mapped(mem)) { - uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; - memory_region_add_subregion(get_system_memory(), addr, mem); - } - } else if (memory_region_is_mapped(mem)) { - memory_region_del_subregion(get_system_memory(), mem); - } - } - memory_region_transaction_commit(); -} - -static bool dino_chip_mem_valid(void *opaque, hwaddr addr, - unsigned size, bool is_write, - MemTxAttrs attrs) -{ - bool ret = false; - - switch (addr) { - case DINO_IAR0: - case DINO_IAR1: - case DINO_IRR0: - case DINO_IRR1: - case DINO_IMR: - case DINO_IPR: - case DINO_ICR: - case DINO_ILR: - case DINO_IO_CONTROL: - case DINO_IO_FBB_EN: - case DINO_IO_ADDR_EN: - case DINO_PCI_IO_DATA: - case DINO_TOC_ADDR: - case DINO_GMASK ... DINO_PCISTS: - case DINO_MLTIM ... DINO_PCIWOR: - case DINO_TLTIM: - ret = true; - break; - case DINO_PCI_IO_DATA + 2: - ret = (size <= 2); - break; - case DINO_PCI_IO_DATA + 1: - case DINO_PCI_IO_DATA + 3: - ret = (size == 1); - } - trace_dino_chip_mem_valid(addr, ret); - return ret; -} - -static MemTxResult dino_chip_read_with_attrs(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - DinoState *s = opaque; - MemTxResult ret = MEMTX_OK; - AddressSpace *io; - uint16_t ioaddr; - uint32_t val; - - switch (addr) { - case DINO_PCI_IO_DATA ... DINO_PCI_IO_DATA + 3: - /* Read from PCI IO space. */ - io = &address_space_io; - ioaddr = s->parent_obj.config_reg + (addr & 3); - switch (size) { - case 1: - val = address_space_ldub(io, ioaddr, attrs, &ret); - break; - case 2: - val = address_space_lduw_be(io, ioaddr, attrs, &ret); - break; - case 4: - val = address_space_ldl_be(io, ioaddr, attrs, &ret); - break; - default: - g_assert_not_reached(); - } - break; - - case DINO_IO_FBB_EN: - val = s->io_fbb_en; - break; - case DINO_IO_ADDR_EN: - val = s->io_addr_en; - break; - case DINO_IO_CONTROL: - val = s->io_control; - break; - - case DINO_IAR0: - val = s->iar0; - break; - case DINO_IAR1: - val = s->iar1; - break; - case DINO_IMR: - val = s->imr; - break; - case DINO_ICR: - val = s->icr; - break; - case DINO_IPR: - val = s->ipr; - /* Any read to IPR clears the register. */ - s->ipr = 0; - break; - case DINO_ILR: - val = s->ilr; - break; - case DINO_IRR0: - val = s->ilr & s->imr & ~s->icr; - break; - case DINO_IRR1: - val = s->ilr & s->imr & s->icr; - break; - case DINO_TOC_ADDR: - val = s->toc_addr; - break; - case DINO_GMASK ... DINO_TLTIM: - val = s->reg800[(addr - DINO_GMASK) / 4]; - if (addr == DINO_PAMR) { - val &= ~0x01; /* LSB is hardwired to 0 */ - } - if (addr == DINO_MLTIM) { - val &= ~0x07; /* 3 LSB are hardwired to 0 */ - } - if (addr == DINO_BRDG_FEAT) { - val &= ~(0x10710E0ul | 8); /* bits 5-7, 24 & 15 reserved */ - } - break; - - default: - /* Controlled by dino_chip_mem_valid above. */ - g_assert_not_reached(); - } - - trace_dino_chip_read(addr, val); - *data = val; - return ret; -} - -static MemTxResult dino_chip_write_with_attrs(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - DinoState *s = opaque; - AddressSpace *io; - MemTxResult ret; - uint16_t ioaddr; - int i; - - trace_dino_chip_write(addr, val); - - switch (addr) { - case DINO_IO_DATA ... DINO_PCI_IO_DATA + 3: - /* Write into PCI IO space. */ - io = &address_space_io; - ioaddr = s->parent_obj.config_reg + (addr & 3); - switch (size) { - case 1: - address_space_stb(io, ioaddr, val, attrs, &ret); - break; - case 2: - address_space_stw_be(io, ioaddr, val, attrs, &ret); - break; - case 4: - address_space_stl_be(io, ioaddr, val, attrs, &ret); - break; - default: - g_assert_not_reached(); - } - return ret; - - case DINO_IO_FBB_EN: - s->io_fbb_en = val & 0x03; - break; - case DINO_IO_ADDR_EN: - s->io_addr_en = val; - gsc_to_pci_forwarding(s); - break; - case DINO_IO_CONTROL: - s->io_control = val; - gsc_to_pci_forwarding(s); - break; - - case DINO_IAR0: - s->iar0 = val; - break; - case DINO_IAR1: - s->iar1 = val; - break; - case DINO_IMR: - s->imr = val; - break; - case DINO_ICR: - s->icr = val; - break; - case DINO_IPR: - /* Any write to IPR clears the register. */ - s->ipr = 0; - break; - case DINO_TOC_ADDR: - /* IO_COMMAND of CPU with client_id bits */ - s->toc_addr = 0xFFFA0030 | (val & 0x1e000); - break; - - case DINO_ILR: - case DINO_IRR0: - case DINO_IRR1: - /* These registers are read-only. */ - break; - - case DINO_GMASK ... DINO_TLTIM: - i = (addr - DINO_GMASK) / 4; - val &= reg800_keep_bits[i]; - s->reg800[i] = val; - break; - - default: - /* Controlled by dino_chip_mem_valid above. */ - g_assert_not_reached(); - } - return MEMTX_OK; -} - -static const MemoryRegionOps dino_chip_ops = { - .read_with_attrs = dino_chip_read_with_attrs, - .write_with_attrs = dino_chip_write_with_attrs, - .endianness = DEVICE_BIG_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - .accepts = dino_chip_mem_valid, - }, - .impl = { - .min_access_size = 1, - .max_access_size = 4, - }, -}; - -static const VMStateDescription vmstate_dino = { - .name = "Dino", - .version_id = 2, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT32(iar0, DinoState), - VMSTATE_UINT32(iar1, DinoState), - VMSTATE_UINT32(imr, DinoState), - VMSTATE_UINT32(ipr, DinoState), - VMSTATE_UINT32(icr, DinoState), - VMSTATE_UINT32(ilr, DinoState), - VMSTATE_UINT32(io_fbb_en, DinoState), - VMSTATE_UINT32(io_addr_en, DinoState), - VMSTATE_UINT32(io_control, DinoState), - VMSTATE_UINT32(toc_addr, DinoState), - VMSTATE_END_OF_LIST() - } -}; - -/* Unlike pci_config_data_le_ops, no check of high bit set in config_reg. */ - -static uint64_t dino_config_data_read(void *opaque, hwaddr addr, unsigned len) -{ - PCIHostState *s = opaque; - return pci_data_read(s->bus, s->config_reg | (addr & 3), len); -} - -static void dino_config_data_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) -{ - PCIHostState *s = opaque; - pci_data_write(s->bus, s->config_reg | (addr & 3), val, len); -} - -static const MemoryRegionOps dino_config_data_ops = { - .read = dino_config_data_read, - .write = dino_config_data_write, - .endianness = DEVICE_LITTLE_ENDIAN, -}; - -static uint64_t dino_config_addr_read(void *opaque, hwaddr addr, unsigned len) -{ - DinoState *s = opaque; - return s->config_reg_dino; -} - -static void dino_config_addr_write(void *opaque, hwaddr addr, - uint64_t val, unsigned len) -{ - PCIHostState *s = opaque; - DinoState *ds = opaque; - ds->config_reg_dino = val; /* keep a copy of original value */ - s->config_reg = val & ~3U; -} - -static const MemoryRegionOps dino_config_addr_ops = { - .read = dino_config_addr_read, - .write = dino_config_addr_write, - .valid.min_access_size = 4, - .valid.max_access_size = 4, - .endianness = DEVICE_BIG_ENDIAN, -}; - -static AddressSpace *dino_pcihost_set_iommu(PCIBus *bus, void *opaque, - int devfn) -{ - DinoState *s = opaque; - - return &s->bm_as; -} - -/* - * Dino interrupts are connected as shown on Page 78, Table 23 - * (Little-endian bit numbers) - * 0 PCI INTA - * 1 PCI INTB - * 2 PCI INTC - * 3 PCI INTD - * 4 PCI INTE - * 5 PCI INTF - * 6 GSC External Interrupt - * 7 Bus Error for "less than fatal" mode - * 8 PS2 - * 9 Unused - * 10 RS232 - */ - -static void dino_set_irq(void *opaque, int irq, int level) -{ - DinoState *s = opaque; - uint32_t bit = 1u << irq; - uint32_t old_ilr = s->ilr; - - if (level) { - uint32_t ena = bit & ~old_ilr; - s->ipr |= ena; - s->ilr = old_ilr | bit; - if (ena & s->imr) { - uint32_t iar = (ena & s->icr ? s->iar1 : s->iar0); - stl_be_phys(&address_space_memory, iar & -32, iar & 31); - } - } else { - s->ilr = old_ilr & ~bit; - } -} - -static int dino_pci_map_irq(PCIDevice *d, int irq_num) -{ - int slot = PCI_SLOT(d->devfn); - - assert(irq_num >= 0 && irq_num <= 3); - - return slot & 0x03; -} - -static void dino_set_timer_irq(void *opaque, int irq, int level) -{ - /* ??? Not connected. */ -} - -static void dino_set_serial_irq(void *opaque, int irq, int level) -{ - dino_set_irq(opaque, 10, level); -} - -PCIBus *dino_init(MemoryRegion *addr_space, - qemu_irq *p_rtc_irq, qemu_irq *p_ser_irq) -{ - DeviceState *dev; - DinoState *s; - PCIBus *b; - int i; - - dev = qdev_new(TYPE_DINO_PCI_HOST_BRIDGE); - s = DINO_PCI_HOST_BRIDGE(dev); - s->iar0 = s->iar1 = CPU_HPA + 3; - s->toc_addr = 0xFFFA0030; /* IO_COMMAND of CPU */ - - /* Dino PCI access from main memory. */ - memory_region_init_io(&s->this_mem, OBJECT(s), &dino_chip_ops, - s, "dino", 4096); - memory_region_add_subregion(addr_space, DINO_HPA, &s->this_mem); - - /* Dino PCI config. */ - memory_region_init_io(&s->parent_obj.conf_mem, OBJECT(&s->parent_obj), - &dino_config_addr_ops, dev, "pci-conf-idx", 4); - memory_region_init_io(&s->parent_obj.data_mem, OBJECT(&s->parent_obj), - &dino_config_data_ops, dev, "pci-conf-data", 4); - memory_region_add_subregion(&s->this_mem, DINO_PCI_CONFIG_ADDR, - &s->parent_obj.conf_mem); - memory_region_add_subregion(&s->this_mem, DINO_CONFIG_DATA, - &s->parent_obj.data_mem); - - /* Dino PCI bus memory. */ - memory_region_init(&s->pci_mem, OBJECT(s), "pci-memory", 4 * GiB); - - b = pci_register_root_bus(dev, "pci", dino_set_irq, dino_pci_map_irq, s, - &s->pci_mem, get_system_io(), - PCI_DEVFN(0, 0), 32, TYPE_PCI_BUS); - s->parent_obj.bus = b; - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - - /* Set up windows into PCI bus memory. */ - for (i = 1; i < 31; i++) { - uint32_t addr = 0xf0000000 + i * DINO_MEM_CHUNK_SIZE; - char *name = g_strdup_printf("PCI Outbound Window %d", i); - memory_region_init_alias(&s->pci_mem_alias[i], OBJECT(s), - name, &s->pci_mem, addr, - DINO_MEM_CHUNK_SIZE); - g_free(name); - } - - /* Set up PCI view of memory: Bus master address space. */ - memory_region_init(&s->bm, OBJECT(s), "bm-dino", 4 * GiB); - memory_region_init_alias(&s->bm_ram_alias, OBJECT(s), - "bm-system", addr_space, 0, - 0xf0000000 + DINO_MEM_CHUNK_SIZE); - memory_region_init_alias(&s->bm_pci_alias, OBJECT(s), - "bm-pci", &s->pci_mem, - 0xf0000000 + DINO_MEM_CHUNK_SIZE, - 30 * DINO_MEM_CHUNK_SIZE); - memory_region_init_alias(&s->bm_cpu_alias, OBJECT(s), - "bm-cpu", addr_space, 0xfff00000, - 0xfffff); - memory_region_add_subregion(&s->bm, 0, - &s->bm_ram_alias); - memory_region_add_subregion(&s->bm, - 0xf0000000 + DINO_MEM_CHUNK_SIZE, - &s->bm_pci_alias); - memory_region_add_subregion(&s->bm, 0xfff00000, - &s->bm_cpu_alias); - address_space_init(&s->bm_as, &s->bm, "pci-bm"); - pci_setup_iommu(b, dino_pcihost_set_iommu, s); - - *p_rtc_irq = qemu_allocate_irq(dino_set_timer_irq, s, 0); - *p_ser_irq = qemu_allocate_irq(dino_set_serial_irq, s, 0); - - return b; -} - -static void dino_pcihost_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->vmsd = &vmstate_dino; -} - -static const TypeInfo dino_pcihost_info = { - .name = TYPE_DINO_PCI_HOST_BRIDGE, - .parent = TYPE_PCI_HOST_BRIDGE, - .instance_size = sizeof(DinoState), - .class_init = dino_pcihost_class_init, -}; - -static void dino_register_types(void) -{ - type_register_static(&dino_pcihost_info); -} - -type_init(dino_register_types) diff --git a/hw/hppa/hppa_hardware.h b/hw/hppa/hppa_hardware.h index 5edf577563..8b6b9222cb 100644 --- a/hw/hppa/hppa_hardware.h +++ b/hw/hppa/hppa_hardware.h @@ -30,11 +30,6 @@ #define PCI_HPA DINO_HPA /* PCI bus */ #define IDE_HPA 0xf9000000 /* Boot disc controller */ -/* offsets to DINO HPA: */ -#define DINO_PCI_ADDR 0x064 -#define DINO_CONFIG_DATA 0x068 -#define DINO_IO_DATA 0x06c - #define PORT_PCI_CMD (PCI_HPA + DINO_PCI_ADDR) #define PORT_PCI_DATA (PCI_HPA + DINO_CONFIG_DATA) diff --git a/hw/hppa/hppa_sys.h b/hw/hppa/hppa_sys.h deleted file mode 100644 index 0b18271cc9..0000000000 --- a/hw/hppa/hppa_sys.h +++ /dev/null @@ -1,24 +0,0 @@ -/* HPPA cores and system support chips. */ - -#ifndef HW_HPPA_SYS_H -#define HW_HPPA_SYS_H - -#include "hw/pci/pci.h" -#include "hw/pci/pci_host.h" -#include "hw/boards.h" -#include "hw/intc/i8259.h" - -#include "hppa_hardware.h" - -PCIBus *dino_init(MemoryRegion *, qemu_irq *, qemu_irq *); -DeviceState *lasi_init(MemoryRegion *); -#define enable_lasi_lan() 0 - -#define TYPE_DINO_PCI_HOST_BRIDGE "dino-pcihost" - -/* hppa_pci.c. */ -extern const MemoryRegionOps hppa_pci_ignore_ops; -extern const MemoryRegionOps hppa_pci_conf1_ops; -extern const MemoryRegionOps hppa_pci_iack_ops; - -#endif diff --git a/hw/hppa/lasi.c b/hw/hppa/lasi.c deleted file mode 100644 index 88c3791eb6..0000000000 --- a/hw/hppa/lasi.c +++ /dev/null @@ -1,367 +0,0 @@ -/* - * HP-PARISC Lasi chipset emulation. - * - * (C) 2019 by Helge Deller <deller@gmx.de> - * - * This work is licensed under the GNU GPL license version 2 or later. - * - * Documentation available at: - * https://parisc.wiki.kernel.org/images-parisc/7/79/Lasi_ers.pdf - */ - -#include "qemu/osdep.h" -#include "qemu/units.h" -#include "qemu/log.h" -#include "qapi/error.h" -#include "trace.h" -#include "hw/irq.h" -#include "sysemu/sysemu.h" -#include "sysemu/runstate.h" -#include "hppa_sys.h" -#include "hw/net/lasi_82596.h" -#include "hw/char/parallel.h" -#include "hw/char/serial.h" -#include "hw/input/lasips2.h" -#include "migration/vmstate.h" -#include "qom/object.h" - -#define TYPE_LASI_CHIP "lasi-chip" - -#define LASI_IRR 0x00 /* RO */ -#define LASI_IMR 0x04 -#define LASI_IPR 0x08 -#define LASI_ICR 0x0c -#define LASI_IAR 0x10 - -#define LASI_PCR 0x0C000 /* LASI Power Control register */ -#define LASI_ERRLOG 0x0C004 /* LASI Error Logging register */ -#define LASI_VER 0x0C008 /* LASI Version Control register */ -#define LASI_IORESET 0x0C00C /* LASI I/O Reset register */ -#define LASI_AMR 0x0C010 /* LASI Arbitration Mask register */ -#define LASI_IO_CONF 0x7FFFE /* LASI primary configuration register */ -#define LASI_IO_CONF2 0x7FFFF /* LASI secondary configuration register */ - -#define LASI_BIT(x) (1ul << (x)) -#define LASI_IRQ_BITS (LASI_BIT(5) | LASI_BIT(7) | LASI_BIT(8) | LASI_BIT(9) \ - | LASI_BIT(13) | LASI_BIT(14) | LASI_BIT(16) | LASI_BIT(17) \ - | LASI_BIT(18) | LASI_BIT(19) | LASI_BIT(20) | LASI_BIT(21) \ - | LASI_BIT(26)) - -#define ICR_BUS_ERROR_BIT LASI_BIT(8) /* bit 8 in ICR */ -#define ICR_TOC_BIT LASI_BIT(1) /* bit 1 in ICR */ - -OBJECT_DECLARE_SIMPLE_TYPE(LasiState, LASI_CHIP) - -struct LasiState { - PCIHostState parent_obj; - - uint32_t irr; - uint32_t imr; - uint32_t ipr; - uint32_t icr; - uint32_t iar; - - uint32_t errlog; - uint32_t amr; - uint32_t rtc; - time_t rtc_ref; - - MemoryRegion this_mem; -}; - -static bool lasi_chip_mem_valid(void *opaque, hwaddr addr, - unsigned size, bool is_write, - MemTxAttrs attrs) -{ - bool ret = false; - - switch (addr) { - case LASI_IRR: - case LASI_IMR: - case LASI_IPR: - case LASI_ICR: - case LASI_IAR: - - case (LASI_LAN_HPA - LASI_HPA): - case (LASI_LPT_HPA - LASI_HPA): - case (LASI_UART_HPA - LASI_HPA): - case (LASI_RTC_HPA - LASI_HPA): - - case LASI_PCR ... LASI_AMR: - ret = true; - } - - trace_lasi_chip_mem_valid(addr, ret); - return ret; -} - -static MemTxResult lasi_chip_read_with_attrs(void *opaque, hwaddr addr, - uint64_t *data, unsigned size, - MemTxAttrs attrs) -{ - LasiState *s = opaque; - MemTxResult ret = MEMTX_OK; - uint32_t val; - - switch (addr) { - case LASI_IRR: - val = s->irr; - break; - case LASI_IMR: - val = s->imr; - break; - case LASI_IPR: - val = s->ipr; - /* Any read to IPR clears the register. */ - s->ipr = 0; - break; - case LASI_ICR: - val = s->icr & ICR_BUS_ERROR_BIT; /* bus_error */ - break; - case LASI_IAR: - val = s->iar; - break; - - case (LASI_LAN_HPA - LASI_HPA): - case (LASI_LPT_HPA - LASI_HPA): - case (LASI_UART_HPA - LASI_HPA): - val = 0; - break; - case (LASI_RTC_HPA - LASI_HPA): - val = time(NULL); - val += s->rtc_ref; - break; - - case LASI_PCR: - case LASI_VER: /* only version 0 existed. */ - case LASI_IORESET: - val = 0; - break; - case LASI_ERRLOG: - val = s->errlog; - break; - case LASI_AMR: - val = s->amr; - break; - - default: - /* Controlled by lasi_chip_mem_valid above. */ - g_assert_not_reached(); - } - - trace_lasi_chip_read(addr, val); - - *data = val; - return ret; -} - -static MemTxResult lasi_chip_write_with_attrs(void *opaque, hwaddr addr, - uint64_t val, unsigned size, - MemTxAttrs attrs) -{ - LasiState *s = opaque; - - trace_lasi_chip_write(addr, val); - - switch (addr) { - case LASI_IRR: - /* read-only. */ - break; - case LASI_IMR: - s->imr = val; - if (((val & LASI_IRQ_BITS) != val) && (val != 0xffffffff)) - qemu_log_mask(LOG_GUEST_ERROR, - "LASI: tried to set invalid %lx IMR value.\n", - (unsigned long) val); - break; - case LASI_IPR: - /* Any write to IPR clears the register. */ - s->ipr = 0; - break; - case LASI_ICR: - s->icr = val; - /* if (val & ICR_TOC_BIT) issue_toc(); */ - break; - case LASI_IAR: - s->iar = val; - break; - - case (LASI_LAN_HPA - LASI_HPA): - /* XXX: reset LAN card */ - break; - case (LASI_LPT_HPA - LASI_HPA): - /* XXX: reset parallel port */ - break; - case (LASI_UART_HPA - LASI_HPA): - /* XXX: reset serial port */ - break; - case (LASI_RTC_HPA - LASI_HPA): - s->rtc_ref = val - time(NULL); - break; - - case LASI_PCR: - if (val == 0x02) /* immediately power off */ - qemu_system_shutdown_request(SHUTDOWN_CAUSE_GUEST_SHUTDOWN); - break; - case LASI_ERRLOG: - s->errlog = val; - break; - case LASI_VER: - /* read-only. */ - break; - case LASI_IORESET: - break; /* XXX: TODO: Reset various devices. */ - case LASI_AMR: - s->amr = val; - break; - - default: - /* Controlled by lasi_chip_mem_valid above. */ - g_assert_not_reached(); - } - return MEMTX_OK; -} - -static const MemoryRegionOps lasi_chip_ops = { - .read_with_attrs = lasi_chip_read_with_attrs, - .write_with_attrs = lasi_chip_write_with_attrs, - .endianness = DEVICE_BIG_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 4, - .accepts = lasi_chip_mem_valid, - }, - .impl = { - .min_access_size = 1, - .max_access_size = 4, - }, -}; - -static const VMStateDescription vmstate_lasi = { - .name = "Lasi", - .version_id = 1, - .minimum_version_id = 1, - .fields = (VMStateField[]) { - VMSTATE_UINT32(irr, LasiState), - VMSTATE_UINT32(imr, LasiState), - VMSTATE_UINT32(ipr, LasiState), - VMSTATE_UINT32(icr, LasiState), - VMSTATE_UINT32(iar, LasiState), - VMSTATE_UINT32(errlog, LasiState), - VMSTATE_UINT32(amr, LasiState), - VMSTATE_END_OF_LIST() - } -}; - - -static void lasi_set_irq(void *opaque, int irq, int level) -{ - LasiState *s = opaque; - uint32_t bit = 1u << irq; - - if (level) { - s->ipr |= bit; - if (bit & s->imr) { - uint32_t iar = s->iar; - s->irr |= bit; - if ((s->icr & ICR_BUS_ERROR_BIT) == 0) { - stl_be_phys(&address_space_memory, iar & -32, iar & 31); - } - } - } -} - -static int lasi_get_irq(unsigned long hpa) -{ - switch (hpa) { - case LASI_HPA: - return 14; - case LASI_UART_HPA: - return 5; - case LASI_LPT_HPA: - return 7; - case LASI_LAN_HPA: - return 8; - case LASI_SCSI_HPA: - return 9; - case LASI_AUDIO_HPA: - return 13; - case LASI_PS2KBD_HPA: - case LASI_PS2MOU_HPA: - return 26; - default: - g_assert_not_reached(); - } -} - -DeviceState *lasi_init(MemoryRegion *address_space) -{ - DeviceState *dev; - LasiState *s; - - dev = qdev_new(TYPE_LASI_CHIP); - s = LASI_CHIP(dev); - s->iar = CPU_HPA + 3; - - /* Lasi access from main memory. */ - memory_region_init_io(&s->this_mem, OBJECT(s), &lasi_chip_ops, - s, "lasi", 0x100000); - memory_region_add_subregion(address_space, LASI_HPA, &s->this_mem); - - sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); - - /* LAN */ - if (enable_lasi_lan()) { - qemu_irq lan_irq = qemu_allocate_irq(lasi_set_irq, s, - lasi_get_irq(LASI_LAN_HPA)); - lasi_82596_init(address_space, LASI_LAN_HPA, lan_irq); - } - - /* Parallel port */ - qemu_irq lpt_irq = qemu_allocate_irq(lasi_set_irq, s, - lasi_get_irq(LASI_LPT_HPA)); - parallel_mm_init(address_space, LASI_LPT_HPA + 0x800, 0, - lpt_irq, parallel_hds[0]); - - /* Real time clock (RTC), it's only one 32-bit counter @9000 */ - - s->rtc = time(NULL); - s->rtc_ref = 0; - - if (serial_hd(1)) { - /* Serial port */ - qemu_irq serial_irq = qemu_allocate_irq(lasi_set_irq, s, - lasi_get_irq(LASI_UART_HPA)); - serial_mm_init(address_space, LASI_UART_HPA + 0x800, 0, - serial_irq, 8000000 / 16, - serial_hd(0), DEVICE_NATIVE_ENDIAN); - } - - /* PS/2 Keyboard/Mouse */ - qemu_irq ps2kbd_irq = qemu_allocate_irq(lasi_set_irq, s, - lasi_get_irq(LASI_PS2KBD_HPA)); - lasips2_init(address_space, LASI_PS2KBD_HPA, ps2kbd_irq); - - return dev; -} - -static void lasi_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - - dc->vmsd = &vmstate_lasi; -} - -static const TypeInfo lasi_pcihost_info = { - .name = TYPE_LASI_CHIP, - .parent = TYPE_SYS_BUS_DEVICE, - .instance_size = sizeof(LasiState), - .class_init = lasi_class_init, -}; - -static void lasi_register_types(void) -{ - type_register_static(&lasi_pcihost_info); -} - -type_init(lasi_register_types) diff --git a/hw/hppa/machine.c b/hw/hppa/machine.c index f7595c0857..ae0bc07e75 100644 --- a/hw/hppa/machine.c +++ b/hw/hppa/machine.c @@ -15,9 +15,15 @@ #include "hw/rtc/mc146818rtc.h" #include "hw/timer/i8254.h" #include "hw/char/serial.h" +#include "hw/char/parallel.h" +#include "hw/intc/i8259.h" +#include "hw/input/lasips2.h" #include "hw/net/lasi_82596.h" #include "hw/nmi.h" -#include "hppa_sys.h" +#include "hw/pci/pci.h" +#include "hw/pci-host/dino.h" +#include "hw/misc/lasi.h" +#include "hppa_hardware.h" #include "qemu/units.h" #include "qapi/error.h" #include "net/net.h" @@ -30,6 +36,9 @@ #define HPA_POWER_BUTTON (FIRMWARE_END - 0x10) +#define enable_lasi_lan() 0 + + static void hppa_powerdown_req(Notifier *n, void *opaque) { hwaddr soft_power_reg = HPA_POWER_BUTTON; @@ -51,6 +60,29 @@ static Notifier hppa_system_powerdown_notifier = { .notify = hppa_powerdown_req }; +/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */ +static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size) +{ + return 0; +} + +static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size) +{ +} + +static const MemoryRegionOps hppa_pci_ignore_ops = { + .read = ignore_read, + .write = ignore_write, + .endianness = DEVICE_BIG_ENDIAN, + .valid = { + .min_access_size = 1, + .max_access_size = 8, + }, + .impl = { + .min_access_size = 1, + .max_access_size = 8, + }, +}; static ISABus *hppa_isa_bus(void) { @@ -121,15 +153,36 @@ static FWCfgState *create_fw_cfg(MachineState *ms) return fw_cfg; } +static LasiState *lasi_init(void) +{ + DeviceState *dev; + + dev = qdev_new(TYPE_LASI_CHIP); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + return LASI_CHIP(dev); +} + +static DinoState *dino_init(MemoryRegion *addr_space) +{ + DeviceState *dev; + + dev = qdev_new(TYPE_DINO_PCI_HOST_BRIDGE); + object_property_set_link(OBJECT(dev), "memory-as", OBJECT(addr_space), + &error_fatal); + sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal); + + return DINO_PCI_HOST_BRIDGE(dev); +} + static void machine_hppa_init(MachineState *machine) { const char *kernel_filename = machine->kernel_filename; const char *kernel_cmdline = machine->kernel_cmdline; const char *initrd_filename = machine->initrd_filename; - DeviceState *dev; + DeviceState *dev, *dino_dev, *lasi_dev; PCIBus *pci_bus; ISABus *isa_bus; - qemu_irq rtc_irq, serial_irq; char *firmware_filename; uint64_t firmware_low, firmware_high; long size; @@ -163,10 +216,17 @@ static void machine_hppa_init(MachineState *machine) /* Init Lasi chip */ - lasi_init(addr_space); + lasi_dev = DEVICE(lasi_init()); + memory_region_add_subregion(addr_space, LASI_HPA, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(lasi_dev), 0)); /* Init Dino (PCI host bus chip). */ - pci_bus = dino_init(addr_space, &rtc_irq, &serial_irq); + dino_dev = DEVICE(dino_init(addr_space)); + memory_region_add_subregion(addr_space, DINO_HPA, + sysbus_mmio_get_region( + SYS_BUS_DEVICE(dino_dev), 0)); + pci_bus = PCI_BUS(qdev_get_child_bus(dino_dev, "pci")); assert(pci_bus); /* Create ISA bus. */ @@ -174,15 +234,28 @@ static void machine_hppa_init(MachineState *machine) assert(isa_bus); /* Realtime clock, used by firmware for PDC_TOD call. */ - mc146818_rtc_init(isa_bus, 2000, rtc_irq); + mc146818_rtc_init(isa_bus, 2000, NULL); /* Serial code setup. */ if (serial_hd(0)) { uint32_t addr = DINO_UART_HPA + 0x800; - serial_mm_init(addr_space, addr, 0, serial_irq, + serial_mm_init(addr_space, addr, 0, + qdev_get_gpio_in(dino_dev, DINO_IRQ_RS232INT), 115200, serial_hd(0), DEVICE_BIG_ENDIAN); } + if (serial_hd(1)) { + /* Serial port */ + serial_mm_init(addr_space, LASI_UART_HPA + 0x800, 0, + qdev_get_gpio_in(lasi_dev, LASI_IRQ_UART_HPA), 8000000 / 16, + serial_hd(1), DEVICE_BIG_ENDIAN); + } + + /* Parallel port */ + parallel_mm_init(addr_space, LASI_LPT_HPA + 0x800, 0, + qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA), + parallel_hds[0]); + /* fw_cfg configuration interface */ create_fw_cfg(machine); @@ -200,12 +273,21 @@ static void machine_hppa_init(MachineState *machine) } /* Network setup. */ + if (enable_lasi_lan()) { + lasi_82596_init(addr_space, LASI_LAN_HPA, + qdev_get_gpio_in(lasi_dev, LASI_IRQ_LAN_HPA)); + } + for (i = 0; i < nb_nics; i++) { if (!enable_lasi_lan()) { pci_nic_init_nofail(&nd_table[i], pci_bus, "tulip", NULL); } } + /* PS/2 Keyboard/Mouse */ + lasips2_init(addr_space, LASI_PS2KBD_HPA, + qdev_get_gpio_in(lasi_dev, LASI_IRQ_PS2KBD_HPA)); + /* register power switch emulation */ qemu_register_powerdown_notifier(&hppa_system_powerdown_notifier); @@ -364,9 +446,12 @@ static void hppa_nmi(NMIState *n, int cpu_index, Error **errp) } } -static void machine_hppa_machine_init(MachineClass *mc) +static void hppa_machine_init_class_init(ObjectClass *oc, void *data) { - mc->desc = "HPPA generic machine"; + MachineClass *mc = MACHINE_CLASS(oc); + NMIClass *nc = NMI_CLASS(oc); + + mc->desc = "HPPA B160L machine"; mc->default_cpu_type = TYPE_HPPA_CPU; mc->init = machine_hppa_init; mc->reset = hppa_machine_reset; @@ -377,30 +462,23 @@ static void machine_hppa_machine_init(MachineClass *mc) mc->default_ram_size = 512 * MiB; mc->default_boot_order = "cd"; mc->default_ram_id = "ram"; -} -static void machine_hppa_machine_init_class_init(ObjectClass *oc, void *data) -{ - MachineClass *mc = MACHINE_CLASS(oc); - machine_hppa_machine_init(mc); - - NMIClass *nc = NMI_CLASS(oc); nc->nmi_monitor_handler = hppa_nmi; } -static const TypeInfo machine_hppa_machine_init_typeinfo = { - .name = ("hppa" "-machine"), - .parent = "machine", - .class_init = machine_hppa_machine_init_class_init, +static const TypeInfo hppa_machine_init_typeinfo = { + .name = MACHINE_TYPE_NAME("hppa"), + .parent = TYPE_MACHINE, + .class_init = hppa_machine_init_class_init, .interfaces = (InterfaceInfo[]) { { TYPE_NMI }, { } }, }; -static void machine_hppa_machine_init_register_types(void) +static void hppa_machine_init_register_types(void) { - type_register_static(&machine_hppa_machine_init_typeinfo); + type_register_static(&hppa_machine_init_typeinfo); } -type_init(machine_hppa_machine_init_register_types) +type_init(hppa_machine_init_register_types) diff --git a/hw/hppa/meson.build b/hw/hppa/meson.build index 1deae83aee..3d0c586c30 100644 --- a/hw/hppa/meson.build +++ b/hw/hppa/meson.build @@ -1,4 +1,4 @@ hppa_ss = ss.source_set() -hppa_ss.add(when: 'CONFIG_DINO', if_true: files('pci.c', 'machine.c', 'dino.c', 'lasi.c')) +hppa_ss.add(when: 'CONFIG_HPPA_B160L', if_true: files('machine.c')) hw_arch += {'hppa': hppa_ss} diff --git a/hw/hppa/pci.c b/hw/hppa/pci.c deleted file mode 100644 index 32609aba63..0000000000 --- a/hw/hppa/pci.c +++ /dev/null @@ -1,88 +0,0 @@ -/* - * QEMU HP-PARISC PCI support functions. - * - */ - -#include "qemu/osdep.h" -#include "hppa_sys.h" -#include "qemu/log.h" -#include "trace.h" - - -/* Fallback for unassigned PCI I/O operations. Avoids MCHK. */ - -static uint64_t ignore_read(void *opaque, hwaddr addr, unsigned size) -{ - return 0; -} - -static void ignore_write(void *opaque, hwaddr addr, uint64_t v, unsigned size) -{ -} - -const MemoryRegionOps hppa_pci_ignore_ops = { - .read = ignore_read, - .write = ignore_write, - .endianness = DEVICE_BIG_ENDIAN, - .valid = { - .min_access_size = 1, - .max_access_size = 8, - }, - .impl = { - .min_access_size = 1, - .max_access_size = 8, - }, -}; - - -/* PCI config space reads/writes, to byte-word addressable memory. */ -static uint64_t bw_conf1_read(void *opaque, hwaddr addr, - unsigned size) -{ - PCIBus *b = opaque; - return pci_data_read(b, addr, size); -} - -static void bw_conf1_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - PCIBus *b = opaque; - pci_data_write(b, addr, val, size); -} - -const MemoryRegionOps hppa_pci_conf1_ops = { - .read = bw_conf1_read, - .write = bw_conf1_write, - .endianness = DEVICE_BIG_ENDIAN, - .impl = { - .min_access_size = 1, - .max_access_size = 4, - }, -}; - -/* PCI/EISA Interrupt Acknowledge Cycle. */ - -static uint64_t iack_read(void *opaque, hwaddr addr, unsigned size) -{ - return pic_read_irq(isa_pic); -} - -static void special_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) -{ - trace_hppa_pci_iack_write(); -} - -const MemoryRegionOps hppa_pci_iack_ops = { - .read = iack_read, - .write = special_write, - .endianness = DEVICE_BIG_ENDIAN, - .valid = { - .min_access_size = 4, - .max_access_size = 4, - }, - .impl = { - .min_access_size = 4, - .max_access_size = 4, - }, -}; diff --git a/hw/hppa/trace-events b/hw/hppa/trace-events deleted file mode 100644 index 3f42be9056..0000000000 --- a/hw/hppa/trace-events +++ /dev/null @@ -1,14 +0,0 @@ -# See docs/devel/tracing.rst for syntax documentation. - -# pci.c -hppa_pci_iack_write(void) "" - -# dino.c -dino_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" -dino_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" -dino_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" - -# lasi.c -lasi_chip_mem_valid(uint64_t addr, uint32_t val) "access to addr 0x%"PRIx64" is %d" -lasi_chip_read(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" -lasi_chip_write(uint64_t addr, uint32_t val) "addr 0x%"PRIx64" val 0x%08x" |