diff options
Diffstat (limited to 'hw/i386/pc.c')
| -rw-r--r-- | hw/i386/pc.c | 225 |
1 files changed, 29 insertions, 196 deletions
diff --git a/hw/i386/pc.c b/hw/i386/pc.c index bad866fe44..bcda50efcc 100644 --- a/hw/i386/pc.c +++ b/hw/i386/pc.c @@ -87,6 +87,8 @@ #include "sysemu/replay.h" #include "qapi/qmp/qerror.h" #include "config-devices.h" +#include "e820_memory_layout.h" +#include "fw_cfg.h" /* debug PC/ISA interrupts */ //#define DEBUG_IRQ @@ -98,22 +100,6 @@ #define DPRINTF(fmt, ...) #endif -#define E820_NR_ENTRIES 16 - -struct e820_entry { - uint64_t address; - uint64_t length; - uint32_t type; -} QEMU_PACKED __attribute((__aligned__(4))); - -struct e820_table { - uint32_t count; - struct e820_entry entry[E820_NR_ENTRIES]; -} QEMU_PACKED __attribute((__aligned__(4))); - -static struct e820_table e820_reserve; -static struct e820_entry *e820_table; -static unsigned e820_entries; struct hpet_fw_config hpet_cfg = {.count = UINT8_MAX}; /* Physical Address of PVH entry point read from kernel ELF NOTE */ @@ -880,50 +866,6 @@ static void handle_a20_line_change(void *opaque, int irq, int level) x86_cpu_set_a20(cpu, level); } -int e820_add_entry(uint64_t address, uint64_t length, uint32_t type) -{ - int index = le32_to_cpu(e820_reserve.count); - struct e820_entry *entry; - - if (type != E820_RAM) { - /* old FW_CFG_E820_TABLE entry -- reservations only */ - if (index >= E820_NR_ENTRIES) { - return -EBUSY; - } - entry = &e820_reserve.entry[index++]; - - entry->address = cpu_to_le64(address); - entry->length = cpu_to_le64(length); - entry->type = cpu_to_le32(type); - - e820_reserve.count = cpu_to_le32(index); - } - - /* new "etc/e820" file -- include ram too */ - e820_table = g_renew(struct e820_entry, e820_table, e820_entries + 1); - e820_table[e820_entries].address = cpu_to_le64(address); - e820_table[e820_entries].length = cpu_to_le64(length); - e820_table[e820_entries].type = cpu_to_le32(type); - e820_entries++; - - return e820_entries; -} - -int e820_get_num_entries(void) -{ - return e820_entries; -} - -bool e820_get_entry(int idx, uint32_t type, uint64_t *address, uint64_t *length) -{ - if (idx < e820_entries && e820_table[idx].type == cpu_to_le32(type)) { - *address = le64_to_cpu(e820_table[idx].address); - *length = le64_to_cpu(e820_table[idx].length); - return true; - } - return false; -} - /* Calculates initial APIC ID for a specific CPU index * * Currently we need to be able to calculate the APIC ID from the CPU index @@ -953,108 +895,6 @@ static uint32_t x86_cpu_apic_id_from_index(PCMachineState *pcms, } } -static void pc_build_smbios(PCMachineState *pcms) -{ - uint8_t *smbios_tables, *smbios_anchor; - size_t smbios_tables_len, smbios_anchor_len; - struct smbios_phys_mem_area *mem_array; - unsigned i, array_count; - MachineState *ms = MACHINE(pcms); - X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); - - /* tell smbios about cpuid version and features */ - smbios_set_cpuid(cpu->env.cpuid_version, cpu->env.features[FEAT_1_EDX]); - - smbios_tables = smbios_get_table_legacy(ms, &smbios_tables_len); - if (smbios_tables) { - fw_cfg_add_bytes(pcms->fw_cfg, FW_CFG_SMBIOS_ENTRIES, - smbios_tables, smbios_tables_len); - } - - /* build the array of physical mem area from e820 table */ - mem_array = g_malloc0(sizeof(*mem_array) * e820_get_num_entries()); - for (i = 0, array_count = 0; i < e820_get_num_entries(); i++) { - uint64_t addr, len; - - if (e820_get_entry(i, E820_RAM, &addr, &len)) { - mem_array[array_count].address = addr; - mem_array[array_count].length = len; - array_count++; - } - } - smbios_get_tables(ms, mem_array, array_count, - &smbios_tables, &smbios_tables_len, - &smbios_anchor, &smbios_anchor_len); - g_free(mem_array); - - if (smbios_anchor) { - fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-tables", - smbios_tables, smbios_tables_len); - fw_cfg_add_file(pcms->fw_cfg, "etc/smbios/smbios-anchor", - smbios_anchor, smbios_anchor_len); - } -} - -static FWCfgState *bochs_bios_init(AddressSpace *as, PCMachineState *pcms) -{ - FWCfgState *fw_cfg; - uint64_t *numa_fw_cfg; - int i; - const CPUArchIdList *cpus; - MachineClass *mc = MACHINE_GET_CLASS(pcms); - MachineState *ms = MACHINE(pcms); - int nb_numa_nodes = ms->numa_state->num_nodes; - - fw_cfg = fw_cfg_init_io_dma(FW_CFG_IO_BASE, FW_CFG_IO_BASE + 4, as); - fw_cfg_add_i16(fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); - - /* FW_CFG_MAX_CPUS is a bit confusing/problematic on x86: - * - * For machine types prior to 1.8, SeaBIOS needs FW_CFG_MAX_CPUS for - * building MPTable, ACPI MADT, ACPI CPU hotplug and ACPI SRAT table, - * that tables are based on xAPIC ID and QEMU<->SeaBIOS interface - * for CPU hotplug also uses APIC ID and not "CPU index". - * This means that FW_CFG_MAX_CPUS is not the "maximum number of CPUs", - * but the "limit to the APIC ID values SeaBIOS may see". - * - * So for compatibility reasons with old BIOSes we are stuck with - * "etc/max-cpus" actually being apic_id_limit - */ - fw_cfg_add_i16(fw_cfg, FW_CFG_MAX_CPUS, (uint16_t)pcms->apic_id_limit); - fw_cfg_add_i64(fw_cfg, FW_CFG_RAM_SIZE, (uint64_t)ram_size); - fw_cfg_add_bytes(fw_cfg, FW_CFG_ACPI_TABLES, - acpi_tables, acpi_tables_len); - fw_cfg_add_i32(fw_cfg, FW_CFG_IRQ0_OVERRIDE, kvm_allows_irq0_override()); - - fw_cfg_add_bytes(fw_cfg, FW_CFG_E820_TABLE, - &e820_reserve, sizeof(e820_reserve)); - fw_cfg_add_file(fw_cfg, "etc/e820", e820_table, - sizeof(struct e820_entry) * e820_entries); - - fw_cfg_add_bytes(fw_cfg, FW_CFG_HPET, &hpet_cfg, sizeof(hpet_cfg)); - /* allocate memory for the NUMA channel: one (64bit) word for the number - * of nodes, one word for each VCPU->node and one word for each node to - * hold the amount of memory. - */ - numa_fw_cfg = g_new0(uint64_t, 1 + pcms->apic_id_limit + nb_numa_nodes); - numa_fw_cfg[0] = cpu_to_le64(nb_numa_nodes); - cpus = mc->possible_cpu_arch_ids(MACHINE(pcms)); - for (i = 0; i < cpus->len; i++) { - unsigned int apic_id = cpus->cpus[i].arch_id; - assert(apic_id < pcms->apic_id_limit); - numa_fw_cfg[apic_id + 1] = cpu_to_le64(cpus->cpus[i].props.node_id); - } - for (i = 0; i < nb_numa_nodes; i++) { - numa_fw_cfg[pcms->apic_id_limit + 1 + i] = - cpu_to_le64(ms->numa_state->nodes[i].node_mem); - } - fw_cfg_add_bytes(fw_cfg, FW_CFG_NUMA, numa_fw_cfg, - (1 + pcms->apic_id_limit + nb_numa_nodes) * - sizeof(*numa_fw_cfg)); - - return fw_cfg; -} - static long get_file_size(FILE *f) { long where, size; @@ -1672,7 +1512,7 @@ void pc_cpus_init(PCMachineState *pcms) * Limit for the APIC ID value, so that all * CPU APIC IDs are < pcms->apic_id_limit. * - * This is used for FW_CFG_MAX_CPUS. See comments on bochs_bios_init(). + * This is used for FW_CFG_MAX_CPUS. See comments on fw_cfg_arch_create(). */ pcms->apic_id_limit = x86_cpu_apic_id_from_index(pcms, ms->smp.max_cpus - 1) + 1; @@ -1682,35 +1522,6 @@ void pc_cpus_init(PCMachineState *pcms) } } -static void pc_build_feature_control_file(PCMachineState *pcms) -{ - MachineState *ms = MACHINE(pcms); - X86CPU *cpu = X86_CPU(ms->possible_cpus->cpus[0].cpu); - CPUX86State *env = &cpu->env; - uint32_t unused, ecx, edx; - uint64_t feature_control_bits = 0; - uint64_t *val; - - cpu_x86_cpuid(env, 1, 0, &unused, &unused, &ecx, &edx); - if (ecx & CPUID_EXT_VMX) { - feature_control_bits |= FEATURE_CONTROL_VMXON_ENABLED_OUTSIDE_SMX; - } - - if ((edx & (CPUID_EXT2_MCE | CPUID_EXT2_MCA)) == - (CPUID_EXT2_MCE | CPUID_EXT2_MCA) && - (env->mcg_cap & MCG_LMCE_P)) { - feature_control_bits |= FEATURE_CONTROL_LMCE; - } - - if (!feature_control_bits) { - return; - } - - val = g_malloc(sizeof(*val)); - *val = cpu_to_le64(feature_control_bits | FEATURE_CONTROL_LOCKED); - fw_cfg_add_file(pcms->fw_cfg, "etc/msr_feature_control", val, sizeof(*val)); -} - static void rtc_set_cpus_count(ISADevice *rtc, uint16_t cpus_count) { if (cpus_count > 0xff) { @@ -1753,8 +1564,8 @@ void pc_machine_done(Notifier *notifier, void *data) acpi_setup(); if (pcms->fw_cfg) { - pc_build_smbios(pcms); - pc_build_feature_control_file(pcms); + fw_cfg_build_smbios(MACHINE(pcms), pcms->fw_cfg); + fw_cfg_build_feature_control(MACHINE(pcms), pcms->fw_cfg); /* update FW_CFG_NB_CPUS to account for -device added CPUs */ fw_cfg_modify_i16(pcms->fw_cfg, FW_CFG_NB_CPUS, pcms->boot_cpus); } @@ -1831,6 +1642,7 @@ void pc_memory_init(PCMachineState *pcms, MemoryRegion *ram_below_4g, *ram_above_4g; FWCfgState *fw_cfg; MachineState *machine = MACHINE(pcms); + MachineClass *mc = MACHINE_GET_CLASS(machine); PCMachineClass *pcmc = PC_MACHINE_GET_CLASS(pcms); assert(machine->ram_size == pcms->below_4g_mem_size + @@ -1864,7 +1676,6 @@ void pc_memory_init(PCMachineState *pcms, if (!pcmc->has_reserved_memory && (machine->ram_slots || (machine->maxram_size > machine->ram_size))) { - MachineClass *mc = MACHINE_GET_CLASS(machine); error_report("\"-memory 'slots|maxmem'\" is not supported by: %s", mc->name); @@ -1927,7 +1738,8 @@ void pc_memory_init(PCMachineState *pcms, option_rom_mr, 1); - fw_cfg = bochs_bios_init(&address_space_memory, pcms); + fw_cfg = fw_cfg_arch_create(machine, + pcms->boot_cpus, pcms->apic_id_limit); rom_set_fw(fw_cfg); @@ -2944,6 +2756,26 @@ static void x86_nmi(NMIState *n, int cpu_index, Error **errp) } } + +static bool pc_hotplug_allowed(MachineState *ms, DeviceState *dev, Error **errp) +{ + X86IOMMUState *iommu = x86_iommu_get_default(); + IntelIOMMUState *intel_iommu; + + if (iommu && + object_dynamic_cast((Object *)iommu, TYPE_INTEL_IOMMU_DEVICE) && + object_dynamic_cast((Object *)dev, "vfio-pci")) { + intel_iommu = INTEL_IOMMU_DEVICE(iommu); + if (!intel_iommu->caching_mode) { + error_setg(errp, "Device assignment is not allowed without " + "enabling caching-mode=on for Intel IOMMU."); + return false; + } + } + + return true; +} + static void pc_machine_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -2968,6 +2800,7 @@ static void pc_machine_class_init(ObjectClass *oc, void *data) pcmc->pvh_enabled = true; assert(!mc->get_hotplug_handler); mc->get_hotplug_handler = pc_get_hotplug_handler; + mc->hotplug_allowed = pc_hotplug_allowed; mc->cpu_index_to_instance_props = pc_cpu_index_to_props; mc->get_default_cpu_node_id = pc_get_default_cpu_node_id; mc->possible_cpu_arch_ids = pc_possible_cpu_arch_ids; |