diff options
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/arm_gic.c | 33 | ||||
| -rw-r--r-- | hw/intc/arm_gic_common.c | 1 | ||||
| -rw-r--r-- | hw/intc/arm_gic_kvm.c | 9 | ||||
| -rw-r--r-- | hw/intc/armv7m_nvic.c | 20 |
4 files changed, 51 insertions, 12 deletions
diff --git a/hw/intc/arm_gic.c b/hw/intc/arm_gic.c index 1d7da7baa2..c60dc6b5e6 100644 --- a/hw/intc/arm_gic.c +++ b/hw/intc/arm_gic.c @@ -641,6 +641,23 @@ uint32_t gic_acknowledge_irq(GICState *s, int cpu, MemTxAttrs attrs) return ret; } +static uint32_t gic_fullprio_mask(GICState *s, int cpu) +{ + /* + * Return a mask word which clears the unimplemented priority + * bits from a priority value for an interrupt. (Not to be + * confused with the group priority, whose mask depends on BPR.) + */ + int priBits; + + if (gic_is_vcpu(cpu)) { + priBits = GIC_VIRT_MAX_GROUP_PRIO_BITS; + } else { + priBits = s->n_prio_bits; + } + return ~0U << (8 - priBits); +} + void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, MemTxAttrs attrs) { @@ -651,6 +668,8 @@ void gic_dist_set_priority(GICState *s, int cpu, int irq, uint8_t val, val = 0x80 | (val >> 1); /* Non-secure view */ } + val &= gic_fullprio_mask(s, cpu); + if (irq < GIC_INTERNAL) { s->priority1[irq][cpu] = val; } else { @@ -669,7 +688,7 @@ static uint32_t gic_dist_get_priority(GICState *s, int cpu, int irq, } prio = (prio << 1) & 0xff; /* Non-secure view */ } - return prio; + return prio & gic_fullprio_mask(s, cpu); } static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, @@ -684,7 +703,7 @@ static void gic_set_priority_mask(GICState *s, int cpu, uint8_t pmask, return; } } - s->priority_mask[cpu] = pmask; + s->priority_mask[cpu] = pmask & gic_fullprio_mask(s, cpu); } static uint32_t gic_get_priority_mask(GICState *s, int cpu, MemTxAttrs attrs) @@ -2055,6 +2074,16 @@ static void arm_gic_realize(DeviceState *dev, Error **errp) return; } + if (s->n_prio_bits > GIC_MAX_PRIORITY_BITS || + (s->virt_extn ? s->n_prio_bits < GIC_VIRT_MAX_GROUP_PRIO_BITS : + s->n_prio_bits < GIC_MIN_PRIORITY_BITS)) { + error_setg(errp, "num-priority-bits cannot be greater than %d" + " or less than %d", GIC_MAX_PRIORITY_BITS, + s->virt_extn ? GIC_VIRT_MAX_GROUP_PRIO_BITS : + GIC_MIN_PRIORITY_BITS); + return; + } + /* This creates distributor, main CPU interface (s->cpuiomem[0]) and if * enabled, virtualization extensions related interfaces (main virtual * interface (s->vifaceiomem[0]) and virtual CPU interface). diff --git a/hw/intc/arm_gic_common.c b/hw/intc/arm_gic_common.c index e6c4fe7a5a..7b44d5625b 100644 --- a/hw/intc/arm_gic_common.c +++ b/hw/intc/arm_gic_common.c @@ -357,6 +357,7 @@ static Property arm_gic_common_properties[] = { DEFINE_PROP_BOOL("has-security-extensions", GICState, security_extn, 0), /* True if the GIC should implement the virtualization extensions */ DEFINE_PROP_BOOL("has-virtualization-extensions", GICState, virt_extn, 0), + DEFINE_PROP_UINT32("num-priority-bits", GICState, n_prio_bits, 8), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/intc/arm_gic_kvm.c b/hw/intc/arm_gic_kvm.c index 9deb15e7e6..d7df423a7a 100644 --- a/hw/intc/arm_gic_kvm.c +++ b/hw/intc/arm_gic_kvm.c @@ -551,7 +551,16 @@ static void kvm_arm_gic_realize(DeviceState *dev, Error **errp) KVM_DEV_ARM_VGIC_CTRL_INIT, NULL, true, &error_abort); } + } else if (kvm_check_extension(kvm_state, KVM_CAP_DEVICE_CTRL)) { + error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); + error_append_hint(errp, + "Perhaps the host CPU does not support GICv2?\n"); } else if (ret != -ENODEV && ret != -ENOTSUP) { + /* + * Very ancient kernel without KVM_CAP_DEVICE_CTRL: assume that + * ENODEV or ENOTSUP mean "can't create GICv2 with KVM_CREATE_DEVICE", + * and that we will get a GICv2 via KVM_CREATE_IRQCHIP. + */ error_setg_errno(errp, -ret, "error creating in-kernel VGIC"); return; } diff --git a/hw/intc/armv7m_nvic.c b/hw/intc/armv7m_nvic.c index 22a43e4984..a62587eb3f 100644 --- a/hw/intc/armv7m_nvic.c +++ b/hw/intc/armv7m_nvic.c @@ -1262,12 +1262,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) case 0xd84: /* CSSELR */ return cpu->env.v7m.csselr[attrs.secure]; case 0xd88: /* CPACR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.cpacr[attrs.secure]; case 0xd8c: /* NSACR */ - if (!attrs.secure || !arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!attrs.secure || !cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.nsacr; @@ -1417,7 +1417,7 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) } return cpu->env.v7m.sfar; case 0xf34: /* FPCCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } if (attrs.secure) { @@ -1444,12 +1444,12 @@ static uint32_t nvic_readl(NVICState *s, uint32_t offset, MemTxAttrs attrs) return value; } case 0xf38: /* FPCAR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpcar[attrs.secure]; case 0xf3c: /* FPDSCR */ - if (!arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (!cpu_isar_feature(aa32_vfp_simd, cpu)) { return 0; } return cpu->env.v7m.fpdscr[attrs.secure]; @@ -1711,13 +1711,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } break; case 0xd88: /* CPACR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 */ cpu->env.v7m.cpacr[attrs.secure] = value & (0xf << 20); } break; case 0xd8c: /* NSACR */ - if (attrs.secure && arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (attrs.secure && cpu_isar_feature(aa32_vfp_simd, cpu)) { /* We implement only the Floating Point extension's CP10/CP11 */ cpu->env.v7m.nsacr = value & (3 << 10); } @@ -1951,7 +1951,7 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, break; } case 0xf34: /* FPCCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { /* Not all bits here are banked. */ uint32_t fpccr_s; @@ -2005,13 +2005,13 @@ static void nvic_writel(NVICState *s, uint32_t offset, uint32_t value, } break; case 0xf38: /* FPCAR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &= ~7; cpu->env.v7m.fpcar[attrs.secure] = value; } break; case 0xf3c: /* FPDSCR */ - if (arm_feature(&cpu->env, ARM_FEATURE_VFP)) { + if (cpu_isar_feature(aa32_vfp_simd, cpu)) { value &= 0x07c00000; cpu->env.v7m.fpdscr[attrs.secure] = value; } |