diff options
Diffstat (limited to 'hw/intc')
| -rw-r--r-- | hw/intc/Kconfig | 17 | ||||
| -rw-r--r-- | hw/intc/grlib_irqmp.c | 5 | ||||
| -rw-r--r-- | hw/intc/loongson_liointc.c | 36 | ||||
| -rw-r--r-- | hw/intc/meson.build | 13 | ||||
| -rw-r--r-- | hw/intc/ppc-uic.c | 321 | ||||
| -rw-r--r-- | hw/intc/spapr_xive.c | 2 |
6 files changed, 354 insertions, 40 deletions
diff --git a/hw/intc/Kconfig b/hw/intc/Kconfig index d07954086a..c18d11142a 100644 --- a/hw/intc/Kconfig +++ b/hw/intc/Kconfig @@ -30,23 +30,11 @@ config ARM_GIC_KVM default y depends on ARM_GIC && KVM -config OPENPIC_KVM - bool - default y - depends on OPENPIC && KVM - config XICS bool - depends on POWERNV || PSERIES - -config XICS_SPAPR - bool - select XICS -config XICS_KVM +config XIVE bool - default y - depends on XICS && KVM config ALLWINNER_A10_PIC bool @@ -62,6 +50,9 @@ config S390_FLIC_KVM config OMPIC bool +config PPC_UIC + bool + config RX_ICU bool diff --git a/hw/intc/grlib_irqmp.c b/hw/intc/grlib_irqmp.c index ffec4a07ee..984334fa7b 100644 --- a/hw/intc/grlib_irqmp.c +++ b/hw/intc/grlib_irqmp.c @@ -51,6 +51,8 @@ #define FORCE_OFFSET 0x80 #define EXTENDED_OFFSET 0xC0 +#define MAX_PILS 16 + OBJECT_DECLARE_SIMPLE_TYPE(IRQMP, GRLIB_IRQMP) typedef struct IRQMPState IRQMPState; @@ -126,7 +128,7 @@ void grlib_irqmp_ack(DeviceState *dev, int intno) grlib_irqmp_ack_mask(state, mask); } -void grlib_irqmp_set_irq(void *opaque, int irq, int level) +static void grlib_irqmp_set_irq(void *opaque, int irq, int level) { IRQMP *irqmp = GRLIB_IRQMP(opaque); IRQMPState *s; @@ -328,6 +330,7 @@ static void grlib_irqmp_init(Object *obj) IRQMP *irqmp = GRLIB_IRQMP(obj); SysBusDevice *dev = SYS_BUS_DEVICE(obj); + qdev_init_gpio_in(DEVICE(obj), grlib_irqmp_set_irq, MAX_PILS); qdev_init_gpio_out_named(DEVICE(obj), &irqmp->irq, "grlib-irq", 1); memory_region_init_io(&irqmp->iomem, obj, &grlib_irqmp_ops, irqmp, "irqmp", IRQMP_REG_SIZE); diff --git a/hw/intc/loongson_liointc.c b/hw/intc/loongson_liointc.c index fbbfb57ee9..f823d484e0 100644 --- a/hw/intc/loongson_liointc.c +++ b/hw/intc/loongson_liointc.c @@ -1,6 +1,7 @@ /* * QEMU Loongson Local I/O interrupt controler. * + * Copyright (c) 2020 Huacai Chen <chenhc@lemote.com> * Copyright (c) 2020 Jiaxun Yang <jiaxun.yang@flygoat.com> * * This program is free software: you can redistribute it and/or modify @@ -19,13 +20,11 @@ */ #include "qemu/osdep.h" -#include "hw/sysbus.h" #include "qemu/module.h" +#include "qemu/log.h" #include "hw/irq.h" #include "hw/qdev-properties.h" -#include "qom/object.h" - -#define D(x) +#include "hw/intc/loongson_liointc.h" #define NUM_IRQS 32 @@ -40,13 +39,10 @@ #define R_IEN 0x24 #define R_IEN_SET 0x28 #define R_IEN_CLR 0x2c -#define R_PERCORE_ISR(x) (0x40 + 0x8 * x) +#define R_ISR_SIZE 0x8 +#define R_START 0x40 #define R_END 0x64 -#define TYPE_LOONGSON_LIOINTC "loongson.liointc" -DECLARE_INSTANCE_CHECKER(struct loongson_liointc, LOONGSON_LIOINTC, - TYPE_LOONGSON_LIOINTC) - struct loongson_liointc { SysBusDevice parent_obj; @@ -123,14 +119,13 @@ liointc_read(void *opaque, hwaddr addr, unsigned int size) goto out; } - /* Rest is 4 byte */ + /* Rest are 4 bytes */ if (size != 4 || (addr % 4)) { goto out; } - if (addr >= R_PERCORE_ISR(0) && - addr < R_PERCORE_ISR(NUM_CORES)) { - int core = (addr - R_PERCORE_ISR(0)) / 8; + if (addr >= R_START && addr < R_END) { + int core = (addr - R_START) / R_ISR_SIZE; r = p->per_core_isr[core]; goto out; } @@ -147,7 +142,8 @@ liointc_read(void *opaque, hwaddr addr, unsigned int size) } out: - D(qemu_log("%s: size=%d addr=%lx val=%x\n", __func__, size, addr, r)); + qemu_log_mask(CPU_LOG_INT, "%s: size=%d, addr=%"HWADDR_PRIx", val=%x\n", + __func__, size, addr, r); return r; } @@ -158,7 +154,8 @@ liointc_write(void *opaque, hwaddr addr, struct loongson_liointc *p = opaque; uint32_t value = val64; - D(qemu_log("%s: size=%d, addr=%lx val=%x\n", __func__, size, addr, value)); + qemu_log_mask(CPU_LOG_INT, "%s: size=%d, addr=%"HWADDR_PRIx", val=%x\n", + __func__, size, addr, value); /* Mapper is 1 byte */ if (size == 1 && addr < R_MAPPER_END) { @@ -166,14 +163,13 @@ liointc_write(void *opaque, hwaddr addr, goto out; } - /* Rest is 4 byte */ + /* Rest are 4 bytes */ if (size != 4 || (addr % 4)) { goto out; } - if (addr >= R_PERCORE_ISR(0) && - addr < R_PERCORE_ISR(NUM_CORES)) { - int core = (addr - R_PERCORE_ISR(0)) / 8; + if (addr >= R_START && addr < R_END) { + int core = (addr - R_START) / R_ISR_SIZE; p->per_core_isr[core] = value; goto out; } @@ -224,7 +220,7 @@ static void loongson_liointc_init(Object *obj) } memory_region_init_io(&p->mmio, obj, &pic_ops, p, - "loongson.liointc", R_END); + TYPE_LOONGSON_LIOINTC, R_END); sysbus_init_mmio(SYS_BUS_DEVICE(obj), &p->mmio); } diff --git a/hw/intc/meson.build b/hw/intc/meson.build index 7c3e9daf58..53cba11569 100644 --- a/hw/intc/meson.build +++ b/hw/intc/meson.build @@ -39,8 +39,10 @@ specific_ss.add(when: 'CONFIG_LOONGSON_LIOINTC', if_true: files('loongson_lioint specific_ss.add(when: 'CONFIG_MIPS_CPS', if_true: files('mips_gic.c')) specific_ss.add(when: 'CONFIG_OMAP', if_true: files('omap_intc.c')) specific_ss.add(when: 'CONFIG_OMPIC', if_true: files('ompic.c')) -specific_ss.add(when: 'CONFIG_OPENPIC_KVM', if_true: files('openpic_kvm.c')) +specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_OPENPIC'], + if_true: files('openpic_kvm.c')) specific_ss.add(when: 'CONFIG_POWERNV', if_true: files('xics_pnv.c', 'pnv_xive.c')) +specific_ss.add(when: 'CONFIG_PPC_UIC', if_true: files('ppc-uic.c')) specific_ss.add(when: 'CONFIG_RASPI', if_true: files('bcm2835_ic.c', 'bcm2836_control.c')) specific_ss.add(when: 'CONFIG_RX_ICU', if_true: files('rx_icu.c')) specific_ss.add(when: 'CONFIG_S390_FLIC', if_true: files('s390_flic.c')) @@ -49,8 +51,9 @@ specific_ss.add(when: 'CONFIG_SH4', if_true: files('sh_intc.c')) specific_ss.add(when: 'CONFIG_SIFIVE_CLINT', if_true: files('sifive_clint.c')) specific_ss.add(when: 'CONFIG_SIFIVE_PLIC', if_true: files('sifive_plic.c')) specific_ss.add(when: 'CONFIG_XICS', if_true: files('xics.c')) -specific_ss.add(when: 'CONFIG_XICS_KVM', if_true: files('xics_kvm.c')) -specific_ss.add(when: 'CONFIG_XICS_SPAPR', if_true: files('xics_spapr.c')) +specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XICS'], + if_true: files('xics_kvm.c')) +specific_ss.add(when: 'CONFIG_PSERIES', if_true: files('xics_spapr.c', 'spapr_xive.c')) specific_ss.add(when: 'CONFIG_XIVE', if_true: files('xive.c')) -specific_ss.add(when: 'CONFIG_XIVE_KVM', if_true: files('spapr_xive_kvm.c')) -specific_ss.add(when: 'CONFIG_XIVE_SPAPR', if_true: files('spapr_xive.c')) +specific_ss.add(when: ['CONFIG_KVM', 'CONFIG_XIVE'], + if_true: files('spapr_xive_kvm.c')) diff --git a/hw/intc/ppc-uic.c b/hw/intc/ppc-uic.c new file mode 100644 index 0000000000..b21951eea8 --- /dev/null +++ b/hw/intc/ppc-uic.c @@ -0,0 +1,321 @@ +/* + * "Universal" Interrupt Controller for PowerPPC 4xx embedded processors + * + * Copyright (c) 2007 Jocelyn Mayer + * + * Permission is hereby granted, free of charge, to any person obtaining a copy + * of this software and associated documentation files (the "Software"), to deal + * in the Software without restriction, including without limitation the rights + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell + * copies of the Software, and to permit persons to whom the Software is + * furnished to do so, subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in + * all copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN + * THE SOFTWARE. + */ + +#include "qemu/osdep.h" +#include "include/hw/intc/ppc-uic.h" +#include "hw/irq.h" +#include "cpu.h" +#include "hw/ppc/ppc.h" +#include "hw/qdev-properties.h" +#include "migration/vmstate.h" +#include "qapi/error.h" + +enum { + DCR_UICSR = 0x000, + DCR_UICSRS = 0x001, + DCR_UICER = 0x002, + DCR_UICCR = 0x003, + DCR_UICPR = 0x004, + DCR_UICTR = 0x005, + DCR_UICMSR = 0x006, + DCR_UICVR = 0x007, + DCR_UICVCR = 0x008, + DCR_UICMAX = 0x009, +}; + +/*#define DEBUG_UIC*/ + +#ifdef DEBUG_UIC +# define LOG_UIC(...) qemu_log_mask(CPU_LOG_INT, ## __VA_ARGS__) +#else +# define LOG_UIC(...) do { } while (0) +#endif + +static void ppcuic_trigger_irq(PPCUIC *uic) +{ + uint32_t ir, cr; + int start, end, inc, i; + + /* Trigger interrupt if any is pending */ + ir = uic->uicsr & uic->uicer & (~uic->uiccr); + cr = uic->uicsr & uic->uicer & uic->uiccr; + LOG_UIC("%s: uicsr %08" PRIx32 " uicer %08" PRIx32 + " uiccr %08" PRIx32 "\n" + " %08" PRIx32 " ir %08" PRIx32 " cr %08" PRIx32 "\n", + __func__, uic->uicsr, uic->uicer, uic->uiccr, + uic->uicsr & uic->uicer, ir, cr); + if (ir != 0x0000000) { + LOG_UIC("Raise UIC interrupt\n"); + qemu_irq_raise(uic->output_int); + } else { + LOG_UIC("Lower UIC interrupt\n"); + qemu_irq_lower(uic->output_int); + } + /* Trigger critical interrupt if any is pending and update vector */ + if (cr != 0x0000000) { + qemu_irq_raise(uic->output_cint); + if (uic->use_vectors) { + /* Compute critical IRQ vector */ + if (uic->uicvcr & 1) { + start = 31; + end = 0; + inc = -1; + } else { + start = 0; + end = 31; + inc = 1; + } + uic->uicvr = uic->uicvcr & 0xFFFFFFFC; + for (i = start; i <= end; i += inc) { + if (cr & (1 << i)) { + uic->uicvr += (i - start) * 512 * inc; + break; + } + } + } + LOG_UIC("Raise UIC critical interrupt - " + "vector %08" PRIx32 "\n", uic->uicvr); + } else { + LOG_UIC("Lower UIC critical interrupt\n"); + qemu_irq_lower(uic->output_cint); + uic->uicvr = 0x00000000; + } +} + +static void ppcuic_set_irq(void *opaque, int irq_num, int level) +{ + PPCUIC *uic; + uint32_t mask, sr; + + uic = opaque; + mask = 1U << (31 - irq_num); + LOG_UIC("%s: irq %d level %d uicsr %08" PRIx32 + " mask %08" PRIx32 " => %08" PRIx32 " %08" PRIx32 "\n", + __func__, irq_num, level, + uic->uicsr, mask, uic->uicsr & mask, level << irq_num); + if (irq_num < 0 || irq_num > 31) { + return; + } + sr = uic->uicsr; + + /* Update status register */ + if (uic->uictr & mask) { + /* Edge sensitive interrupt */ + if (level == 1) { + uic->uicsr |= mask; + } + } else { + /* Level sensitive interrupt */ + if (level == 1) { + uic->uicsr |= mask; + uic->level |= mask; + } else { + uic->uicsr &= ~mask; + uic->level &= ~mask; + } + } + LOG_UIC("%s: irq %d level %d sr %" PRIx32 " => " + "%08" PRIx32 "\n", __func__, irq_num, level, uic->uicsr, sr); + if (sr != uic->uicsr) { + ppcuic_trigger_irq(uic); + } +} + +static uint32_t dcr_read_uic(void *opaque, int dcrn) +{ + PPCUIC *uic; + uint32_t ret; + + uic = opaque; + dcrn -= uic->dcr_base; + switch (dcrn) { + case DCR_UICSR: + case DCR_UICSRS: + ret = uic->uicsr; + break; + case DCR_UICER: + ret = uic->uicer; + break; + case DCR_UICCR: + ret = uic->uiccr; + break; + case DCR_UICPR: + ret = uic->uicpr; + break; + case DCR_UICTR: + ret = uic->uictr; + break; + case DCR_UICMSR: + ret = uic->uicsr & uic->uicer; + break; + case DCR_UICVR: + if (!uic->use_vectors) { + goto no_read; + } + ret = uic->uicvr; + break; + case DCR_UICVCR: + if (!uic->use_vectors) { + goto no_read; + } + ret = uic->uicvcr; + break; + default: + no_read: + ret = 0x00000000; + break; + } + + return ret; +} + +static void dcr_write_uic(void *opaque, int dcrn, uint32_t val) +{ + PPCUIC *uic; + + uic = opaque; + dcrn -= uic->dcr_base; + LOG_UIC("%s: dcr %d val 0x%x\n", __func__, dcrn, val); + switch (dcrn) { + case DCR_UICSR: + uic->uicsr &= ~val; + uic->uicsr |= uic->level; + ppcuic_trigger_irq(uic); + break; + case DCR_UICSRS: + uic->uicsr |= val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICER: + uic->uicer = val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICCR: + uic->uiccr = val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICPR: + uic->uicpr = val; + break; + case DCR_UICTR: + uic->uictr = val; + ppcuic_trigger_irq(uic); + break; + case DCR_UICMSR: + break; + case DCR_UICVR: + break; + case DCR_UICVCR: + uic->uicvcr = val & 0xFFFFFFFD; + ppcuic_trigger_irq(uic); + break; + } +} + +static void ppc_uic_reset(DeviceState *dev) +{ + PPCUIC *uic = PPC_UIC(dev); + + uic->uiccr = 0x00000000; + uic->uicer = 0x00000000; + uic->uicpr = 0x00000000; + uic->uicsr = 0x00000000; + uic->uictr = 0x00000000; + if (uic->use_vectors) { + uic->uicvcr = 0x00000000; + uic->uicvr = 0x0000000; + } +} + +static void ppc_uic_realize(DeviceState *dev, Error **errp) +{ + PPCUIC *uic = PPC_UIC(dev); + SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + PowerPCCPU *cpu; + int i; + + if (!uic->cpu) { + /* This is a programming error in the code using this device */ + error_setg(errp, "ppc-uic 'cpu' link property was not set"); + return; + } + + cpu = POWERPC_CPU(uic->cpu); + for (i = 0; i < DCR_UICMAX; i++) { + ppc_dcr_register(&cpu->env, uic->dcr_base + i, uic, + &dcr_read_uic, &dcr_write_uic); + } + + sysbus_init_irq(sbd, &uic->output_int); + sysbus_init_irq(sbd, &uic->output_cint); + qdev_init_gpio_in(dev, ppcuic_set_irq, UIC_MAX_IRQ); +} + +static Property ppc_uic_properties[] = { + DEFINE_PROP_LINK("cpu", PPCUIC, cpu, TYPE_CPU, CPUState *), + DEFINE_PROP_UINT32("dcr-base", PPCUIC, dcr_base, 0x30), + DEFINE_PROP_BOOL("use-vectors", PPCUIC, use_vectors, true), + DEFINE_PROP_END_OF_LIST() +}; + +static const VMStateDescription ppc_uic_vmstate = { + .name = "ppc-uic", + .version_id = 1, + .minimum_version_id = 1, + .fields = (VMStateField[]) { + VMSTATE_UINT32(level, PPCUIC), + VMSTATE_UINT32(uicsr, PPCUIC), + VMSTATE_UINT32(uicer, PPCUIC), + VMSTATE_UINT32(uiccr, PPCUIC), + VMSTATE_UINT32(uicpr, PPCUIC), + VMSTATE_UINT32(uictr, PPCUIC), + VMSTATE_UINT32(uicvcr, PPCUIC), + VMSTATE_UINT32(uicvr, PPCUIC), + VMSTATE_END_OF_LIST() + }, +}; + +static void ppc_uic_class_init(ObjectClass *klass, void *data) +{ + DeviceClass *dc = DEVICE_CLASS(klass); + + dc->reset = ppc_uic_reset; + dc->realize = ppc_uic_realize; + dc->vmsd = &ppc_uic_vmstate; + device_class_set_props(dc, ppc_uic_properties); +} + +static const TypeInfo ppc_uic_info = { + .name = TYPE_PPC_UIC, + .parent = TYPE_SYS_BUS_DEVICE, + .instance_size = sizeof(PPCUIC), + .class_init = ppc_uic_class_init, +}; + +static void ppc_uic_register_types(void) +{ + type_register_static(&ppc_uic_info); +} + +type_init(ppc_uic_register_types); diff --git a/hw/intc/spapr_xive.c b/hw/intc/spapr_xive.c index caedd312d7..801bc19341 100644 --- a/hw/intc/spapr_xive.c +++ b/hw/intc/spapr_xive.c @@ -156,7 +156,7 @@ static void spapr_xive_end_pic_print_info(SpaprXive *xive, XiveEND *end, #define spapr_xive_in_kernel(xive) \ (kvm_irqchip_in_kernel() && (xive)->fd != -1) -void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) +static void spapr_xive_pic_print_info(SpaprXive *xive, Monitor *mon) { XiveSource *xsrc = &xive->source; int i; |