diff options
Diffstat (limited to 'hw/m48t59.c')
| -rw-r--r-- | hw/m48t59.c | 72 |
1 files changed, 36 insertions, 36 deletions
diff --git a/hw/m48t59.c b/hw/m48t59.c index b9892cc1f8..b8ad5b8a09 100644 --- a/hw/m48t59.c +++ b/hw/m48t59.c @@ -41,7 +41,7 @@ * alarm and a watchdog timer and related control registers. In the * PPC platform there is also a nvram lock function. */ -struct m48t59_t { +struct m48t59 { /* Model parameters */ uint32_t type; // 2 = m48t02, 8 = m48t08, 59 = m48t59 /* Hardware parameters */ @@ -63,12 +63,12 @@ struct m48t59_t { typedef struct M48t59ISAState { ISADevice busdev; - m48t59_t state; + a_m48t59 state; } M48t59ISAState; typedef struct M48t59SysBusState { SysBusDevice busdev; - m48t59_t state; + a_m48t59 state; } M48t59SysBusState; /* Fake timer functions */ @@ -88,7 +88,7 @@ static void alarm_cb (void *opaque) { struct tm tm; uint64_t next_time; - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; qemu_set_irq(NVRAM->IRQ, 1); if ((NVRAM->buffer[0x1FF5] & 0x80) == 0 && @@ -130,7 +130,7 @@ static void alarm_cb (void *opaque) qemu_set_irq(NVRAM->IRQ, 0); } -static void set_alarm (m48t59_t *NVRAM) +static void set_alarm (a_m48t59 *NVRAM) { int diff; if (NVRAM->alrm_timer != NULL) { @@ -142,12 +142,12 @@ static void set_alarm (m48t59_t *NVRAM) } /* RTC management helpers */ -static inline void get_time (m48t59_t *NVRAM, struct tm *tm) +static inline void get_time (a_m48t59 *NVRAM, struct tm *tm) { qemu_get_timedate(tm, NVRAM->time_offset); } -static void set_time (m48t59_t *NVRAM, struct tm *tm) +static void set_time (a_m48t59 *NVRAM, struct tm *tm) { NVRAM->time_offset = qemu_timedate_diff(tm); set_alarm(NVRAM); @@ -156,7 +156,7 @@ static void set_time (m48t59_t *NVRAM, struct tm *tm) /* Watchdog management */ static void watchdog_cb (void *opaque) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; NVRAM->buffer[0x1FF0] |= 0x80; if (NVRAM->buffer[0x1FF7] & 0x80) { @@ -170,7 +170,7 @@ static void watchdog_cb (void *opaque) } } -static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) +static void set_up_watchdog (a_m48t59 *NVRAM, uint8_t value) { uint64_t interval; /* in 1/16 seconds */ @@ -188,7 +188,7 @@ static void set_up_watchdog (m48t59_t *NVRAM, uint8_t value) /* Direct access to NVRAM */ void m48t59_write (void *opaque, uint32_t addr, uint32_t val) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; struct tm tm; int tmp; @@ -356,7 +356,7 @@ void m48t59_write (void *opaque, uint32_t addr, uint32_t val) uint32_t m48t59_read (void *opaque, uint32_t addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; struct tm tm; uint32_t retval = 0xFF; @@ -463,14 +463,14 @@ uint32_t m48t59_read (void *opaque, uint32_t addr) void m48t59_set_addr (void *opaque, uint32_t addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; NVRAM->addr = addr; } void m48t59_toggle_lock (void *opaque, int lock) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; NVRAM->lock ^= 1 << lock; } @@ -478,7 +478,7 @@ void m48t59_toggle_lock (void *opaque, int lock) /* IO access to NVRAM */ static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; addr -= NVRAM->io_base; NVRAM_PRINTF("%s: 0x%08x => 0x%08x\n", __func__, addr, val); @@ -502,7 +502,7 @@ static void NVRAM_writeb (void *opaque, uint32_t addr, uint32_t val) static uint32_t NVRAM_readb (void *opaque, uint32_t addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; uint32_t retval; addr -= NVRAM->io_base; @@ -519,24 +519,24 @@ static uint32_t NVRAM_readb (void *opaque, uint32_t addr) return retval; } -static void nvram_writeb (void *opaque, target_phys_addr_t addr, uint32_t value) +static void nvram_writeb (void *opaque, a_target_phys_addr addr, uint32_t value) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; m48t59_write(NVRAM, addr, value & 0xff); } -static void nvram_writew (void *opaque, target_phys_addr_t addr, uint32_t value) +static void nvram_writew (void *opaque, a_target_phys_addr addr, uint32_t value) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; m48t59_write(NVRAM, addr, (value >> 8) & 0xff); m48t59_write(NVRAM, addr + 1, value & 0xff); } -static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) +static void nvram_writel (void *opaque, a_target_phys_addr addr, uint32_t value) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; m48t59_write(NVRAM, addr, (value >> 24) & 0xff); m48t59_write(NVRAM, addr + 1, (value >> 16) & 0xff); @@ -544,18 +544,18 @@ static void nvram_writel (void *opaque, target_phys_addr_t addr, uint32_t value) m48t59_write(NVRAM, addr + 3, value & 0xff); } -static uint32_t nvram_readb (void *opaque, target_phys_addr_t addr) +static uint32_t nvram_readb (void *opaque, a_target_phys_addr addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; uint32_t retval; retval = m48t59_read(NVRAM, addr); return retval; } -static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) +static uint32_t nvram_readw (void *opaque, a_target_phys_addr addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; uint32_t retval; retval = m48t59_read(NVRAM, addr) << 8; @@ -563,9 +563,9 @@ static uint32_t nvram_readw (void *opaque, target_phys_addr_t addr) return retval; } -static uint32_t nvram_readl (void *opaque, target_phys_addr_t addr) +static uint32_t nvram_readl (void *opaque, a_target_phys_addr addr) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; uint32_t retval; retval = m48t59_read(NVRAM, addr) << 24; @@ -589,7 +589,7 @@ static CPUReadMemoryFunc * const nvram_read[] = { static void m48t59_save(QEMUFile *f, void *opaque) { - m48t59_t *s = opaque; + a_m48t59 *s = opaque; qemu_put_8s(f, &s->lock); qemu_put_be16s(f, &s->addr); @@ -598,7 +598,7 @@ static void m48t59_save(QEMUFile *f, void *opaque) static int m48t59_load(QEMUFile *f, void *opaque, int version_id) { - m48t59_t *s = opaque; + a_m48t59 *s = opaque; if (version_id != 1) return -EINVAL; @@ -612,7 +612,7 @@ static int m48t59_load(QEMUFile *f, void *opaque, int version_id) static void m48t59_reset(void *opaque) { - m48t59_t *NVRAM = opaque; + a_m48t59 *NVRAM = opaque; NVRAM->addr = 0; NVRAM->lock = 0; @@ -624,7 +624,7 @@ static void m48t59_reset(void *opaque) } /* Initialisation routine */ -m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, +a_m48t59 *m48t59_init (qemu_irq IRQ, a_target_phys_addr mem_base, uint32_t io_base, uint16_t size, int type) { @@ -652,11 +652,11 @@ m48t59_t *m48t59_init (qemu_irq IRQ, target_phys_addr_t mem_base, return &d->state; } -m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) +a_m48t59 *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) { M48t59ISAState *d; ISADevice *dev; - m48t59_t *s; + a_m48t59 *s; dev = isa_create("m48t59_isa"); qdev_prop_set_uint32(&dev->qdev, "type", type); @@ -674,7 +674,7 @@ m48t59_t *m48t59_init_isa(uint32_t io_base, uint16_t size, int type) return s; } -static void m48t59_init_common(m48t59_t *s) +static void m48t59_init_common(a_m48t59 *s) { s->buffer = qemu_mallocz(s->size); if (s->type == 59) { @@ -690,7 +690,7 @@ static void m48t59_init_common(m48t59_t *s) static int m48t59_init_isa1(ISADevice *dev) { M48t59ISAState *d = DO_UPCAST(M48t59ISAState, busdev, dev); - m48t59_t *s = &d->state; + a_m48t59 *s = &d->state; isa_init_irq(dev, &s->IRQ, 8); m48t59_init_common(s); @@ -701,7 +701,7 @@ static int m48t59_init_isa1(ISADevice *dev) static int m48t59_init1(SysBusDevice *dev) { M48t59SysBusState *d = FROM_SYSBUS(M48t59SysBusState, dev); - m48t59_t *s = &d->state; + a_m48t59 *s = &d->state; int mem_index; sysbus_init_irq(dev, &s->IRQ); |