diff options
Diffstat (limited to 'hw/net/vmware_utils.h')
| -rw-r--r-- | hw/net/vmware_utils.h | 55 |
1 files changed, 31 insertions, 24 deletions
diff --git a/hw/net/vmware_utils.h b/hw/net/vmware_utils.h index c0dbb2ff41..550060170e 100644 --- a/hw/net/vmware_utils.h +++ b/hw/net/vmware_utils.h @@ -26,97 +26,104 @@ * */ static inline void -vmw_shmem_read(hwaddr addr, void *buf, int len) +vmw_shmem_read(PCIDevice *d, hwaddr addr, void *buf, int len) { VMW_SHPRN("SHMEM r: %" PRIx64 ", len: %d to %p", addr, len, buf); - cpu_physical_memory_read(addr, buf, len); + pci_dma_read(d, addr, buf, len); } static inline void -vmw_shmem_write(hwaddr addr, void *buf, int len) +vmw_shmem_write(PCIDevice *d, hwaddr addr, void *buf, int len) { VMW_SHPRN("SHMEM w: %" PRIx64 ", len: %d to %p", addr, len, buf); - cpu_physical_memory_write(addr, buf, len); + pci_dma_write(d, addr, buf, len); } static inline void -vmw_shmem_rw(hwaddr addr, void *buf, int len, int is_write) +vmw_shmem_rw(PCIDevice *d, hwaddr addr, void *buf, int len, int is_write) { VMW_SHPRN("SHMEM r/w: %" PRIx64 ", len: %d (to %p), is write: %d", addr, len, buf, is_write); - cpu_physical_memory_rw(addr, buf, len, is_write); + if (is_write) + pci_dma_write(d, addr, buf, len); + else + pci_dma_read(d, addr, buf, len); } static inline void -vmw_shmem_set(hwaddr addr, uint8_t val, int len) +vmw_shmem_set(PCIDevice *d, hwaddr addr, uint8_t val, int len) { int i; VMW_SHPRN("SHMEM set: %" PRIx64 ", len: %d (value 0x%X)", addr, len, val); for (i = 0; i < len; i++) { - cpu_physical_memory_write(addr + i, &val, 1); + pci_dma_write(d, addr + i, &val, 1); } } static inline uint32_t -vmw_shmem_ld8(hwaddr addr) +vmw_shmem_ld8(PCIDevice *d, hwaddr addr) { - uint8_t res = ldub_phys(&address_space_memory, addr); + uint8_t res; + pci_dma_read(d, addr, &res, 1); VMW_SHPRN("SHMEM load8: %" PRIx64 " (value 0x%X)", addr, res); return res; } static inline void -vmw_shmem_st8(hwaddr addr, uint8_t value) +vmw_shmem_st8(PCIDevice *d, hwaddr addr, uint8_t value) { VMW_SHPRN("SHMEM store8: %" PRIx64 " (value 0x%X)", addr, value); - stb_phys(&address_space_memory, addr, value); + pci_dma_write(d, addr, &value, 1); } static inline uint32_t -vmw_shmem_ld16(hwaddr addr) +vmw_shmem_ld16(PCIDevice *d, hwaddr addr) { - uint16_t res = lduw_le_phys(&address_space_memory, addr); + uint16_t res; + pci_dma_read(d, addr, &res, 2); VMW_SHPRN("SHMEM load16: %" PRIx64 " (value 0x%X)", addr, res); return res; } static inline void -vmw_shmem_st16(hwaddr addr, uint16_t value) +vmw_shmem_st16(PCIDevice *d, hwaddr addr, uint16_t value) { VMW_SHPRN("SHMEM store16: %" PRIx64 " (value 0x%X)", addr, value); - stw_le_phys(&address_space_memory, addr, value); + pci_dma_write(d, addr, &value, 2); } static inline uint32_t -vmw_shmem_ld32(hwaddr addr) +vmw_shmem_ld32(PCIDevice *d, hwaddr addr) { - uint32_t res = ldl_le_phys(&address_space_memory, addr); + uint32_t res; + pci_dma_read(d, addr, &res, 4); VMW_SHPRN("SHMEM load32: %" PRIx64 " (value 0x%X)", addr, res); return res; } static inline void -vmw_shmem_st32(hwaddr addr, uint32_t value) +vmw_shmem_st32(PCIDevice *d, hwaddr addr, uint32_t value) { VMW_SHPRN("SHMEM store32: %" PRIx64 " (value 0x%X)", addr, value); - stl_le_phys(&address_space_memory, addr, value); + pci_dma_write(d, addr, &value, 4); } static inline uint64_t -vmw_shmem_ld64(hwaddr addr) +vmw_shmem_ld64(PCIDevice *d, hwaddr addr) { - uint64_t res = ldq_le_phys(&address_space_memory, addr); + uint64_t res; + pci_dma_read(d, addr, &res, 8); VMW_SHPRN("SHMEM load64: %" PRIx64 " (value %" PRIx64 ")", addr, res); return res; } static inline void -vmw_shmem_st64(hwaddr addr, uint64_t value) +vmw_shmem_st64(PCIDevice *d, hwaddr addr, uint64_t value) { VMW_SHPRN("SHMEM store64: %" PRIx64 " (value %" PRIx64 ")", addr, value); - stq_le_phys(&address_space_memory, addr, value); + pci_dma_write(d, addr, &value, 8); } /* Macros for simplification of operations on array-style registers */ |