diff options
Diffstat (limited to 'hw/pci-host/sabre.c')
| -rw-r--r-- | hw/pci-host/sabre.c | 28 |
1 files changed, 5 insertions, 23 deletions
diff --git a/hw/pci-host/sabre.c b/hw/pci-host/sabre.c index 5ac6283623..f41a0cc301 100644 --- a/hw/pci-host/sabre.c +++ b/hw/pci-host/sabre.c @@ -44,7 +44,7 @@ /* * Chipset docs: * PBM: "UltraSPARC IIi User's Manual", - * http://www.sun.com/processors/manuals/805-0087.pdf + * https://web.archive.org/web/20030403110020/http://www.sun.com/processors/manuals/805-0087.pdf */ #define PBM_PCI_IMR_MASK 0x7fffffff @@ -120,7 +120,7 @@ static void sabre_config_write(void *opaque, hwaddr addr, trace_sabre_config_write(addr, val); - switch (addr & 0xffff) { + switch (addr) { case 0x30 ... 0x4f: /* DMA error registers */ /* XXX: not implemented yet */ break; @@ -195,32 +195,25 @@ static uint64_t sabre_config_read(void *opaque, hwaddr addr, unsigned size) { SabreState *s = opaque; - uint32_t val; + uint32_t val = 0; - switch (addr & 0xffff) { + switch (addr) { case 0x30 ... 0x4f: /* DMA error registers */ - val = 0; /* XXX: not implemented yet */ break; case 0xc00 ... 0xc3f: /* PCI interrupt control */ if (addr & 4) { val = s->pci_irq_map[(addr & 0x3f) >> 3]; - } else { - val = 0; } break; case 0x1000 ... 0x107f: /* OBIO interrupt control */ if (addr & 4) { val = s->obio_irq_map[(addr & 0xff) >> 3]; - } else { - val = 0; } break; case 0x1080 ... 0x108f: /* PCI bus error */ if (addr & 4) { val = s->pci_err_irq_map[(addr & 0xf) >> 3]; - } else { - val = 0; } break; case 0x2000 ... 0x202f: /* PCI control */ @@ -229,8 +222,6 @@ static uint64_t sabre_config_read(void *opaque, case 0xf020 ... 0xf027: /* Reset control */ if (addr & 4) { val = s->reset_control; - } else { - val = 0; } break; case 0x5000 ... 0x51cf: /* PIO/DMA diagnostics */ @@ -239,7 +230,6 @@ static uint64_t sabre_config_read(void *opaque, case 0xf000 ... 0xf01f: /* FFB config, memory control */ /* we don't care */ default: - val = 0; break; } trace_sabre_config_read(addr, val); @@ -378,16 +368,8 @@ static void sabre_realize(DeviceState *dev, Error **errp) { SabreState *s = SABRE(dev); PCIHostState *phb = PCI_HOST_BRIDGE(dev); - SysBusDevice *sbd = SYS_BUS_DEVICE(s); PCIDevice *pci_dev; - /* sabre_config */ - sysbus_mmio_map(sbd, 0, s->special_base); - /* PCI configuration space */ - sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); - /* pci_ioport */ - sysbus_mmio_map(sbd, 2, s->special_base + 0x2000000ULL); - memory_region_init(&s->pci_mmio, OBJECT(s), "pci-mmio", 0x100000000ULL); memory_region_add_subregion(get_system_memory(), s->mem_base, &s->pci_mmio); @@ -396,7 +378,7 @@ static void sabre_realize(DeviceState *dev, Error **errp) pci_sabre_set_irq, pci_sabre_map_irq, s, &s->pci_mmio, &s->pci_ioport, - 0, 32, TYPE_PCI_BUS); + 0, 0x40, TYPE_PCI_BUS); pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); |