diff options
Diffstat (limited to 'hw/pci-host')
| -rw-r--r-- | hw/pci-host/Makefile.objs | 2 | ||||
| -rw-r--r-- | hw/pci-host/sabre.c (renamed from hw/pci-host/apb.c) | 270 | ||||
| -rw-r--r-- | hw/pci-host/trace-events | 11 |
3 files changed, 111 insertions, 172 deletions
diff --git a/hw/pci-host/Makefile.objs b/hw/pci-host/Makefile.objs index 9c7909cf44..4b69f737b5 100644 --- a/hw/pci-host/Makefile.objs +++ b/hw/pci-host/Makefile.objs @@ -11,7 +11,7 @@ common-obj-$(CONFIG_PPCE500_PCI) += ppce500.o # ARM devices common-obj-$(CONFIG_VERSATILE_PCI) += versatile.o -common-obj-$(CONFIG_PCI_APB) += apb.o +common-obj-$(CONFIG_PCI_SABRE) += sabre.o common-obj-$(CONFIG_FULONG) += bonito.o common-obj-$(CONFIG_PCI_PIIX) += piix.o common-obj-$(CONFIG_PCI_Q35) += q35.o diff --git a/hw/pci-host/apb.c b/hw/pci-host/sabre.c index ec676f94b6..2268a41dd9 100644 --- a/hw/pci-host/apb.c +++ b/hw/pci-host/sabre.c @@ -1,8 +1,9 @@ /* - * QEMU Ultrasparc APB PCI host + * QEMU Ultrasparc Sabre PCI host (PBM) * * Copyright (c) 2006 Fabrice Bellard * Copyright (c) 2012,2013 Artyom Tarasenko + * Copyright (c) 2018 Mark Cave-Ayland * * Permission is hereby granted, free of charge, to any person obtaining a copy * of this software and associated documentation files (the "Software"), to deal @@ -23,39 +24,24 @@ * THE SOFTWARE. */ -/* XXX This file and most of its contents are somewhat misnamed. The - Ultrasparc PCI host is called the PCI Bus Module (PBM). The APB is - the secondary PCI bridge. */ - #include "qemu/osdep.h" #include "hw/sysbus.h" #include "hw/pci/pci.h" #include "hw/pci/pci_host.h" #include "hw/pci/pci_bridge.h" #include "hw/pci/pci_bus.h" -#include "hw/pci-host/apb.h" +#include "hw/pci-bridge/simba.h" +#include "hw/pci-host/sabre.h" #include "sysemu/sysemu.h" #include "exec/address-spaces.h" #include "qapi/error.h" #include "qemu/log.h" - -/* debug APB */ -//#define DEBUG_APB - -#ifdef DEBUG_APB -#define APB_DPRINTF(fmt, ...) \ -do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) -#else -#define APB_DPRINTF(fmt, ...) -#endif +#include "trace.h" /* * Chipset docs: * PBM: "UltraSPARC IIi User's Manual", * http://www.sun.com/processors/manuals/805-0087.pdf - * - * APB: "Advanced PCI Bridge (APB) User's Manual", - * http://www.sun.com/processors/manuals/805-1251.pdf */ #define PBM_PCI_IMR_MASK 0x7fffffff @@ -72,22 +58,20 @@ do { printf("APB: " fmt , ## __VA_ARGS__); } while (0) #define NO_IRQ_REQUEST (MAX_IVEC + 1) -static inline void pbm_set_request(APBState *s, unsigned int irq_num) +static inline void sabre_set_request(SabreState *s, unsigned int irq_num) { - APB_DPRINTF("%s: request irq %d\n", __func__, irq_num); - + trace_sabre_set_request(irq_num); s->irq_request = irq_num; qemu_set_irq(s->ivec_irqs[irq_num], 1); } -static inline void pbm_check_irqs(APBState *s) +static inline void sabre_check_irqs(SabreState *s) { - unsigned int i; /* Previous request is not acknowledged, resubmit */ if (s->irq_request != NO_IRQ_REQUEST) { - pbm_set_request(s, s->irq_request); + sabre_set_request(s, s->irq_request); return; } /* no request pending */ @@ -97,7 +81,7 @@ static inline void pbm_check_irqs(APBState *s) for (i = 0; i < 32; i++) { if (s->pci_irq_in & (1ULL << i)) { if (s->pci_irq_map[i >> 2] & PBM_PCI_IMR_ENABLED) { - pbm_set_request(s, i); + sabre_set_request(s, i); return; } } @@ -105,33 +89,33 @@ static inline void pbm_check_irqs(APBState *s) for (i = 32; i < 64; i++) { if (s->pci_irq_in & (1ULL << i)) { if (s->obio_irq_map[i - 32] & PBM_PCI_IMR_ENABLED) { - pbm_set_request(s, i); + sabre_set_request(s, i); break; } } } } -static inline void pbm_clear_request(APBState *s, unsigned int irq_num) +static inline void sabre_clear_request(SabreState *s, unsigned int irq_num) { - APB_DPRINTF("%s: clear request irq %d\n", __func__, irq_num); + trace_sabre_clear_request(irq_num); qemu_set_irq(s->ivec_irqs[irq_num], 0); s->irq_request = NO_IRQ_REQUEST; } -static AddressSpace *pbm_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) +static AddressSpace *sabre_pci_dma_iommu(PCIBus *bus, void *opaque, int devfn) { IOMMUState *is = opaque; return &is->iommu_as; } -static void apb_config_writel (void *opaque, hwaddr addr, +static void sabre_config_write(void *opaque, hwaddr addr, uint64_t val, unsigned size) { - APBState *s = opaque; + SabreState *s = opaque; - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val); + trace_sabre_config_write(addr, val); switch (addr & 0xffff) { case 0x30 ... 0x4f: /* DMA error registers */ @@ -143,9 +127,9 @@ static void apb_config_writel (void *opaque, hwaddr addr, s->pci_irq_map[ino] &= PBM_PCI_IMR_MASK; s->pci_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; if ((s->irq_request == ino) && !(val & ~PBM_PCI_IMR_MASK)) { - pbm_clear_request(s, ino); + sabre_clear_request(s, ino); } - pbm_check_irqs(s); + sabre_check_irqs(s); } break; case 0x1000 ... 0x107f: /* OBIO interrupt control */ @@ -155,17 +139,17 @@ static void apb_config_writel (void *opaque, hwaddr addr, s->obio_irq_map[ino] |= val & ~PBM_PCI_IMR_MASK; if ((s->irq_request == (ino | 0x20)) && !(val & ~PBM_PCI_IMR_MASK)) { - pbm_clear_request(s, ino | 0x20); + sabre_clear_request(s, ino | 0x20); } - pbm_check_irqs(s); + sabre_check_irqs(s); } break; case 0x1400 ... 0x14ff: /* PCI interrupt clear */ if (addr & 4) { unsigned int ino = (addr & 0xff) >> 5; if ((s->irq_request / 4) == ino) { - pbm_clear_request(s, s->irq_request); - pbm_check_irqs(s); + sabre_clear_request(s, s->irq_request); + sabre_check_irqs(s); } } break; @@ -173,8 +157,8 @@ static void apb_config_writel (void *opaque, hwaddr addr, if (addr & 4) { unsigned int ino = ((addr & 0xff) >> 3) | 0x20; if (s->irq_request == ino) { - pbm_clear_request(s, ino); - pbm_check_irqs(s); + sabre_clear_request(s, ino); + sabre_check_irqs(s); } } break; @@ -204,10 +188,10 @@ static void apb_config_writel (void *opaque, hwaddr addr, } } -static uint64_t apb_config_readl (void *opaque, +static uint64_t sabre_config_read(void *opaque, hwaddr addr, unsigned size) { - APBState *s = opaque; + SabreState *s = opaque; uint32_t val; switch (addr & 0xffff) { @@ -255,47 +239,47 @@ static uint64_t apb_config_readl (void *opaque, val = 0; break; } - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, val); + trace_sabre_config_read(addr, val); return val; } -static const MemoryRegionOps apb_config_ops = { - .read = apb_config_readl, - .write = apb_config_writel, +static const MemoryRegionOps sabre_config_ops = { + .read = sabre_config_read, + .write = sabre_config_write, .endianness = DEVICE_BIG_ENDIAN, }; -static void apb_pci_config_write(void *opaque, hwaddr addr, - uint64_t val, unsigned size) +static void sabre_pci_config_write(void *opaque, hwaddr addr, + uint64_t val, unsigned size) { - APBState *s = opaque; + SabreState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); - APB_DPRINTF("%s: addr " TARGET_FMT_plx " val %" PRIx64 "\n", __func__, addr, val); + trace_sabre_pci_config_write(addr, val); pci_data_write(phb->bus, addr, val, size); } -static uint64_t apb_pci_config_read(void *opaque, hwaddr addr, - unsigned size) +static uint64_t sabre_pci_config_read(void *opaque, hwaddr addr, + unsigned size) { uint32_t ret; - APBState *s = opaque; + SabreState *s = opaque; PCIHostState *phb = PCI_HOST_BRIDGE(s); ret = pci_data_read(phb->bus, addr, size); - APB_DPRINTF("%s: addr " TARGET_FMT_plx " -> %x\n", __func__, addr, ret); + trace_sabre_pci_config_read(addr, ret); return ret; } -/* The APB host has an IRQ line for each IRQ line of each slot. */ -static int pci_apb_map_irq(PCIDevice *pci_dev, int irq_num) +/* The sabre host has an IRQ line for each IRQ line of each slot. */ +static int pci_sabre_map_irq(PCIDevice *pci_dev, int irq_num) { /* Return the irq as swizzled by the PBM */ return irq_num; } -static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num) +static int pci_simbaA_map_irq(PCIDevice *pci_dev, int irq_num) { /* The on-board devices have fixed (legacy) OBIO intnos */ switch (PCI_SLOT(pci_dev->devfn)) { @@ -313,22 +297,23 @@ static int pci_pbmA_map_irq(PCIDevice *pci_dev, int irq_num) return ((PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; } -static int pci_pbmB_map_irq(PCIDevice *pci_dev, int irq_num) +static int pci_simbaB_map_irq(PCIDevice *pci_dev, int irq_num) { return (0x10 + (PCI_SLOT(pci_dev->devfn) << 2) + irq_num) & 0x1f; } -static void pci_apb_set_irq(void *opaque, int irq_num, int level) +static void pci_sabre_set_irq(void *opaque, int irq_num, int level) { - APBState *s = opaque; + SabreState *s = opaque; + + trace_sabre_pci_set_irq(irq_num, level); - APB_DPRINTF("%s: set irq_in %d level %d\n", __func__, irq_num, level); /* PCI IRQ map onto the first 32 INO. */ if (irq_num < 32) { if (level) { s->pci_irq_in |= 1ULL << irq_num; if (s->pci_irq_map[irq_num >> 2] & PBM_PCI_IMR_ENABLED) { - pbm_set_request(s, irq_num); + sabre_set_request(s, irq_num); } } else { s->pci_irq_in &= ~(1ULL << irq_num); @@ -336,11 +321,11 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level) } else { /* OBIO IRQ map onto the next 32 INO. */ if (level) { - APB_DPRINTF("%s: set irq %d level %d\n", __func__, irq_num, level); + trace_sabre_pci_set_obio_irq(irq_num, level); s->pci_irq_in |= 1ULL << irq_num; if ((s->irq_request == NO_IRQ_REQUEST) && (s->obio_irq_map[irq_num - 32] & PBM_PCI_IMR_ENABLED)) { - pbm_set_request(s, irq_num); + sabre_set_request(s, irq_num); } } else { s->pci_irq_in &= ~(1ULL << irq_num); @@ -348,38 +333,9 @@ static void pci_apb_set_irq(void *opaque, int irq_num, int level) } } -static void apb_pci_bridge_realize(PCIDevice *dev, Error **errp) +static void sabre_reset(DeviceState *d) { - /* - * command register: - * According to PCI bridge spec, after reset - * bus master bit is off - * memory space enable bit is off - * According to manual (805-1251.pdf). - * the reset value should be zero unless the boot pin is tied high - * (which is true) and thus it should be PCI_COMMAND_MEMORY. - */ - PBMPCIBridge *br = PBM_PCI_BRIDGE(dev); - - pci_bridge_initfn(dev, TYPE_PCI_BUS); - - pci_set_word(dev->config + PCI_COMMAND, PCI_COMMAND_MEMORY); - pci_set_word(dev->config + PCI_STATUS, - PCI_STATUS_FAST_BACK | PCI_STATUS_66MHZ | - PCI_STATUS_DEVSEL_MEDIUM); - - /* Allow 32-bit IO addresses */ - pci_set_word(dev->config + PCI_IO_BASE, PCI_IO_RANGE_TYPE_32); - pci_set_word(dev->config + PCI_IO_LIMIT, PCI_IO_RANGE_TYPE_32); - pci_set_word(dev->wmask + PCI_IO_BASE_UPPER16, 0xffff); - pci_set_word(dev->wmask + PCI_IO_LIMIT_UPPER16, 0xffff); - - pci_bridge_update_mappings(PCI_BRIDGE(br)); -} - -static void pci_pbm_reset(DeviceState *d) -{ - APBState *s = APB_DEVICE(d); + SabreState *s = SABRE_DEVICE(d); PCIDevice *pci_dev; unsigned int i; uint16_t cmd; @@ -410,19 +366,19 @@ static void pci_pbm_reset(DeviceState *d) } static const MemoryRegionOps pci_config_ops = { - .read = apb_pci_config_read, - .write = apb_pci_config_write, + .read = sabre_pci_config_read, + .write = sabre_pci_config_write, .endianness = DEVICE_LITTLE_ENDIAN, }; -static void pci_pbm_realize(DeviceState *dev, Error **errp) +static void sabre_realize(DeviceState *dev, Error **errp) { - APBState *s = APB_DEVICE(dev); + SabreState *s = SABRE_DEVICE(dev); PCIHostState *phb = PCI_HOST_BRIDGE(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(s); PCIDevice *pci_dev; - /* apb_config */ + /* sabre_config */ sysbus_mmio_map(sbd, 0, s->special_base); /* PCI configuration space */ sysbus_mmio_map(sbd, 1, s->special_base + 0x1000000ULL); @@ -434,35 +390,35 @@ static void pci_pbm_realize(DeviceState *dev, Error **errp) &s->pci_mmio); phb->bus = pci_register_root_bus(dev, "pci", - pci_apb_set_irq, pci_apb_map_irq, s, + pci_sabre_set_irq, pci_sabre_map_irq, s, &s->pci_mmio, &s->pci_ioport, 0, 32, TYPE_PCI_BUS); - pci_create_simple(phb->bus, 0, "pbm-pci"); + pci_create_simple(phb->bus, 0, TYPE_SABRE_PCI_DEVICE); - /* APB IOMMU */ - memory_region_add_subregion_overlap(&s->apb_config, 0x200, + /* IOMMU */ + memory_region_add_subregion_overlap(&s->sabre_config, 0x200, sysbus_mmio_get_region(SYS_BUS_DEVICE(s->iommu), 0), 1); - pci_setup_iommu(phb->bus, pbm_pci_dma_iommu, s->iommu); + pci_setup_iommu(phb->bus, sabre_pci_dma_iommu, s->iommu); /* APB secondary busses */ pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 0), true, - TYPE_PBM_PCI_BRIDGE); + TYPE_SIMBA_PCI_BRIDGE); s->bridgeB = PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(s->bridgeB, "pciB", pci_pbmB_map_irq); + pci_bridge_map_irq(s->bridgeB, "pciB", pci_simbaB_map_irq); qdev_init_nofail(&pci_dev->qdev); pci_dev = pci_create_multifunction(phb->bus, PCI_DEVFN(1, 1), true, - TYPE_PBM_PCI_BRIDGE); + TYPE_SIMBA_PCI_BRIDGE); s->bridgeA = PCI_BRIDGE(pci_dev); - pci_bridge_map_irq(s->bridgeA, "pciA", pci_pbmA_map_irq); + pci_bridge_map_irq(s->bridgeA, "pciA", pci_simbaA_map_irq); qdev_init_nofail(&pci_dev->qdev); } -static void pci_pbm_init(Object *obj) +static void sabre_init(Object *obj) { - APBState *s = APB_DEVICE(obj); + SabreState *s = SABRE_DEVICE(obj); SysBusDevice *sbd = SYS_BUS_DEVICE(obj); unsigned int i; @@ -475,7 +431,7 @@ static void pci_pbm_init(Object *obj) for (i = 0; i < 32; i++) { s->obio_irq_map[i] = ((0x1f << 6) | 0x20) + i; } - qdev_init_gpio_in_named(DEVICE(s), pci_apb_set_irq, "pbm-irq", MAX_IVEC); + qdev_init_gpio_in_named(DEVICE(s), pci_sabre_set_irq, "pbm-irq", MAX_IVEC); qdev_init_gpio_out_named(DEVICE(s), s->ivec_irqs, "ivec-irq", MAX_IVEC); s->irq_request = NO_IRQ_REQUEST; s->pci_irq_in = 0ULL; @@ -486,25 +442,26 @@ static void pci_pbm_init(Object *obj) qdev_prop_allow_set_link_before_realize, 0, NULL); - /* apb_config */ - memory_region_init_io(&s->apb_config, OBJECT(s), &apb_config_ops, s, - "apb-config", 0x10000); + /* sabre_config */ + memory_region_init_io(&s->sabre_config, OBJECT(s), &sabre_config_ops, s, + "sabre-config", 0x10000); /* at region 0 */ - sysbus_init_mmio(sbd, &s->apb_config); + sysbus_init_mmio(sbd, &s->sabre_config); memory_region_init_io(&s->pci_config, OBJECT(s), &pci_config_ops, s, - "apb-pci-config", 0x1000000); + "sabre-pci-config", 0x1000000); /* at region 1 */ sysbus_init_mmio(sbd, &s->pci_config); /* pci_ioport */ - memory_region_init(&s->pci_ioport, OBJECT(s), "apb-pci-ioport", 0x1000000); + memory_region_init(&s->pci_ioport, OBJECT(s), "sabre-pci-ioport", + 0x1000000); /* at region 2 */ sysbus_init_mmio(sbd, &s->pci_ioport); } -static void pbm_pci_host_realize(PCIDevice *d, Error **errp) +static void sabre_pci_realize(PCIDevice *d, Error **errp) { pci_set_word(d->config + PCI_COMMAND, PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); @@ -513,12 +470,12 @@ static void pbm_pci_host_realize(PCIDevice *d, Error **errp) PCI_STATUS_DEVSEL_MEDIUM); } -static void pbm_pci_host_class_init(ObjectClass *klass, void *data) +static void sabre_pci_class_init(ObjectClass *klass, void *data) { PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); DeviceClass *dc = DEVICE_CLASS(klass); - k->realize = pbm_pci_host_realize; + k->realize = sabre_pci_realize; k->vendor_id = PCI_VENDOR_ID_SUN; k->device_id = PCI_DEVICE_ID_SUN_SABRE; k->class_id = PCI_CLASS_BRIDGE_HOST; @@ -529,74 +486,45 @@ static void pbm_pci_host_class_init(ObjectClass *klass, void *data) dc->user_creatable = false; } -static const TypeInfo pbm_pci_host_info = { - .name = "pbm-pci", +static const TypeInfo sabre_pci_info = { + .name = TYPE_SABRE_PCI_DEVICE, .parent = TYPE_PCI_DEVICE, - .instance_size = sizeof(PCIDevice), - .class_init = pbm_pci_host_class_init, + .instance_size = sizeof(SabrePCIState), + .class_init = sabre_pci_class_init, .interfaces = (InterfaceInfo[]) { { INTERFACE_CONVENTIONAL_PCI_DEVICE }, { }, }, }; -static Property pbm_pci_host_properties[] = { - DEFINE_PROP_UINT64("special-base", APBState, special_base, 0), - DEFINE_PROP_UINT64("mem-base", APBState, mem_base, 0), +static Property sabre_properties[] = { + DEFINE_PROP_UINT64("special-base", SabreState, special_base, 0), + DEFINE_PROP_UINT64("mem-base", SabreState, mem_base, 0), DEFINE_PROP_END_OF_LIST(), }; -static void pbm_host_class_init(ObjectClass *klass, void *data) +static void sabre_class_init(ObjectClass *klass, void *data) { DeviceClass *dc = DEVICE_CLASS(klass); - dc->realize = pci_pbm_realize; - dc->reset = pci_pbm_reset; - dc->props = pbm_pci_host_properties; + dc->realize = sabre_realize; + dc->reset = sabre_reset; + dc->props = sabre_properties; set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); } -static const TypeInfo pbm_host_info = { - .name = TYPE_APB, +static const TypeInfo sabre_info = { + .name = TYPE_SABRE, .parent = TYPE_PCI_HOST_BRIDGE, - .instance_size = sizeof(APBState), - .instance_init = pci_pbm_init, - .class_init = pbm_host_class_init, -}; - -static void pbm_pci_bridge_class_init(ObjectClass *klass, void *data) -{ - DeviceClass *dc = DEVICE_CLASS(klass); - PCIDeviceClass *k = PCI_DEVICE_CLASS(klass); - - k->realize = apb_pci_bridge_realize; - k->exit = pci_bridge_exitfn; - k->vendor_id = PCI_VENDOR_ID_SUN; - k->device_id = PCI_DEVICE_ID_SUN_SIMBA; - k->revision = 0x11; - k->config_write = pci_bridge_write_config; - k->is_bridge = 1; - set_bit(DEVICE_CATEGORY_BRIDGE, dc->categories); - dc->reset = pci_bridge_reset; - dc->vmsd = &vmstate_pci_device; -} - -static const TypeInfo pbm_pci_bridge_info = { - .name = TYPE_PBM_PCI_BRIDGE, - .parent = TYPE_PCI_BRIDGE, - .class_init = pbm_pci_bridge_class_init, - .instance_size = sizeof(PBMPCIBridge), - .interfaces = (InterfaceInfo[]) { - { INTERFACE_CONVENTIONAL_PCI_DEVICE }, - { }, - }, + .instance_size = sizeof(SabreState), + .instance_init = sabre_init, + .class_init = sabre_class_init, }; -static void pbm_register_types(void) +static void sabre_register_types(void) { - type_register_static(&pbm_host_info); - type_register_static(&pbm_pci_host_info); - type_register_static(&pbm_pci_bridge_info); + type_register_static(&sabre_info); + type_register_static(&sabre_pci_info); } -type_init(pbm_register_types) +type_init(sabre_register_types) diff --git a/hw/pci-host/trace-events b/hw/pci-host/trace-events new file mode 100644 index 0000000000..32dfc84692 --- /dev/null +++ b/hw/pci-host/trace-events @@ -0,0 +1,11 @@ +# See docs/devel/tracing.txt for syntax documentation. + +# hw/pci-host/sabre.c +sabre_set_request(int irq_num) "request irq %d" +sabre_clear_request(int irq_num) "clear request irq %d" +sabre_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 +sabre_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 +sabre_pci_config_write(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 +sabre_pci_config_read(uint64_t addr, uint64_t val) "addr 0x%"PRIx64" val 0x%"PRIx64 +sabre_pci_set_irq(int irq_num, int level) "set irq_in %d level %d" +sabre_pci_set_obio_irq(int irq_num, int level) "set irq %d level %d" |