diff options
Diffstat (limited to 'hw/ppc')
| -rw-r--r-- | hw/ppc/pnv.c | 123 | ||||
| -rw-r--r-- | hw/ppc/pnv_bmc.c | 8 | ||||
| -rw-r--r-- | hw/ppc/pnv_pnor.c | 10 | ||||
| -rw-r--r-- | hw/ppc/pnv_psi.c | 41 | ||||
| -rw-r--r-- | hw/ppc/ppc440_bamboo.c | 8 | ||||
| -rw-r--r-- | hw/ppc/spapr.c | 18 | ||||
| -rw-r--r-- | hw/ppc/spapr_irq.c | 2 |
7 files changed, 94 insertions, 116 deletions
diff --git a/hw/ppc/pnv.c b/hw/ppc/pnv.c index f77e7ca84e..e2735bb8dd 100644 --- a/hw/ppc/pnv.c +++ b/hw/ppc/pnv.c @@ -561,7 +561,7 @@ static void *pnv_dt_create(MachineState *machine) static void pnv_powerdown_notify(Notifier *n, void *opaque) { - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); + PnvMachineState *pnv = container_of(n, PnvMachineState, powerdown_notifier); if (pnv->bmc) { pnv_bmc_powerdown(pnv->bmc); @@ -768,6 +768,18 @@ static void pnv_init(MachineState *machine) exit(1); } + pnv->num_chips = + machine->smp.max_cpus / (machine->smp.cores * machine->smp.threads); + /* + * TODO: should we decide on how many chips we can create based + * on #cores and Venice vs. Murano vs. Naples chip type etc..., + */ + if (!is_power_of_2(pnv->num_chips) || pnv->num_chips > 4) { + error_report("invalid number of chips: '%d'", pnv->num_chips); + error_printf("Try '-smp sockets=N'. Valid values are : 1, 2 or 4.\n"); + exit(1); + } + pnv->chips = g_new0(PnvChip *, pnv->num_chips); for (i = 0; i < pnv->num_chips; i++) { char chip_name[32]; @@ -790,12 +802,25 @@ static void pnv_init(MachineState *machine) &error_fatal); object_property_set_int(chip, machine->smp.cores, "nr-cores", &error_fatal); + object_property_set_int(chip, machine->smp.threads, + "nr-threads", &error_fatal); + /* + * The POWER8 machine use the XICS interrupt interface. + * Propagate the XICS fabric to the chip and its controllers. + */ + if (object_dynamic_cast(OBJECT(pnv), TYPE_XICS_FABRIC)) { + object_property_set_link(chip, OBJECT(pnv), "xics", &error_abort); + } + if (object_dynamic_cast(OBJECT(pnv), TYPE_XIVE_FABRIC)) { + object_property_set_link(chip, OBJECT(pnv), "xive-fabric", + &error_abort); + } object_property_set_bool(chip, true, "realized", &error_fatal); } g_free(chip_typename); /* Create the machine BMC simulator */ - pnv->bmc = pnv_bmc_create(); + pnv->bmc = pnv_bmc_create(pnv->pnor); /* Instantiate ISA bus on chip 0 */ pnv->isa_bus = pnv_isa_create(pnv->chips[0], &error_fatal); @@ -831,12 +856,12 @@ static uint32_t pnv_chip_core_pir_p8(PnvChip *chip, uint32_t core_id) static void pnv_chip_power8_intc_create(PnvChip *chip, PowerPCCPU *cpu, Error **errp) { + Pnv8Chip *chip8 = PNV8_CHIP(chip); Error *local_err = NULL; Object *obj; PnvCPUState *pnv_cpu = pnv_cpu_state(cpu); - obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, XICS_FABRIC(qdev_get_machine()), - &local_err); + obj = icp_create(OBJECT(cpu), TYPE_PNV_ICP, chip8->xics, &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -900,7 +925,8 @@ static void pnv_chip_power9_intc_create(PnvChip *chip, PowerPCCPU *cpu, * controller object is initialized afterwards. Hopefully, it's * only used at runtime. */ - obj = xive_tctx_create(OBJECT(cpu), XIVE_ROUTER(&chip9->xive), &local_err); + obj = xive_tctx_create(OBJECT(cpu), XIVE_PRESENTER(&chip9->xive), + &local_err); if (local_err) { error_propagate(errp, local_err); return; @@ -990,10 +1016,14 @@ static void pnv_chip_power8_instance_init(Object *obj) { Pnv8Chip *chip8 = PNV8_CHIP(obj); + object_property_add_link(obj, "xics", TYPE_XICS_FABRIC, + (Object **)&chip8->xics, + object_property_allow_set_link, + OBJ_PROP_LINK_STRONG, + &error_abort); + object_initialize_child(obj, "psi", &chip8->psi, sizeof(chip8->psi), TYPE_PNV8_PSI, &error_abort, NULL); - object_property_add_const_link(OBJECT(&chip8->psi), "xics", - OBJECT(qdev_get_machine()), &error_abort); object_initialize_child(obj, "lpc", &chip8->lpc, sizeof(chip8->lpc), TYPE_PNV8_LPC, &error_abort, NULL); @@ -1011,7 +1041,6 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); int i, j; char *name; - XICSFabric *xi = XICS_FABRIC(qdev_get_machine()); name = g_strdup_printf("icp-%x", chip->chip_id); memory_region_init(&chip8->icp_mmio, OBJECT(chip), name, PNV_ICP_SIZE); @@ -1027,7 +1056,7 @@ static void pnv_chip_icp_realize(Pnv8Chip *chip8, Error **errp) for (j = 0; j < CPU_CORE(pnv_core)->nr_threads; j++) { uint32_t pir = pcc->core_pir(chip, core_hwid) + j; - PnvICPState *icp = PNV_ICP(xics_icp_get(xi, pir)); + PnvICPState *icp = PNV_ICP(xics_icp_get(chip8->xics, pir)); memory_region_add_subregion(&chip8->icp_mmio, pir << 12, &icp->mmio); @@ -1043,6 +1072,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) Pnv8Psi *psi8 = &chip8->psi; Error *local_err = NULL; + assert(chip8->xics); + /* XSCOM bridge is first */ pnv_xscom_realize(chip, PNV_XSCOM_SIZE, &local_err); if (local_err) { @@ -1060,6 +1091,8 @@ static void pnv_chip_power8_realize(DeviceState *dev, Error **errp) /* Processor Service Interface (PSI) Host Bridge */ object_property_set_int(OBJECT(&chip8->psi), PNV_PSIHB_BASE(chip), "bar", &error_fatal); + object_property_set_link(OBJECT(&chip8->psi), OBJECT(chip8->xics), + ICS_PROP_XICS, &error_abort); object_property_set_bool(OBJECT(&chip8->psi), true, "realized", &local_err); if (local_err) { error_propagate(errp, local_err); @@ -1201,6 +1234,8 @@ static void pnv_chip_power9_instance_init(Object *obj) object_initialize_child(obj, "xive", &chip9->xive, sizeof(chip9->xive), TYPE_PNV_XIVE, &error_abort, NULL); + object_property_add_alias(obj, "xive-fabric", OBJECT(&chip9->xive), + "xive-fabric", &error_abort); object_initialize_child(obj, "psi", &chip9->psi, sizeof(chip9->psi), TYPE_PNV9_PSI, &error_abort, NULL); @@ -1494,7 +1529,6 @@ static void pnv_chip_core_sanitize(PnvChip *chip, Error **errp) static void pnv_chip_core_realize(PnvChip *chip, Error **errp) { - MachineState *ms = MACHINE(qdev_get_machine()); Error *error = NULL; PnvChipClass *pcc = PNV_CHIP_GET_CLASS(chip); const char *typename = pnv_chip_core_typename(chip); @@ -1530,8 +1564,8 @@ static void pnv_chip_core_realize(PnvChip *chip, Error **errp) object_property_add_child(OBJECT(chip), core_name, OBJECT(pnv_core), &error_abort); chip->cores[i] = pnv_core; - object_property_set_int(OBJECT(pnv_core), ms->smp.threads, "nr-threads", - &error_fatal); + object_property_set_int(OBJECT(pnv_core), chip->nr_threads, + "nr-threads", &error_fatal); object_property_set_int(OBJECT(pnv_core), core_hwid, CPU_CORE_PROP_CORE_ID, &error_fatal); object_property_set_int(OBJECT(pnv_core), @@ -1570,6 +1604,7 @@ static Property pnv_chip_properties[] = { DEFINE_PROP_UINT64("ram-size", PnvChip, ram_size, 0), DEFINE_PROP_UINT32("nr-cores", PnvChip, nr_cores, 1), DEFINE_PROP_UINT64("cores-mask", PnvChip, cores_mask, 0x0), + DEFINE_PROP_UINT32("nr-threads", PnvChip, nr_threads, 1), DEFINE_PROP_END_OF_LIST(), }; @@ -1682,67 +1717,6 @@ static int pnv_match_nvt(XiveFabric *xfb, uint8_t format, return total_count; } -PnvChip *pnv_get_chip(uint32_t chip_id) -{ - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); - int i; - - for (i = 0; i < pnv->num_chips; i++) { - PnvChip *chip = pnv->chips[i]; - if (chip->chip_id == chip_id) { - return chip; - } - } - return NULL; -} - -static void pnv_get_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - visit_type_uint32(v, name, &PNV_MACHINE(obj)->num_chips, errp); -} - -static void pnv_set_num_chips(Object *obj, Visitor *v, const char *name, - void *opaque, Error **errp) -{ - PnvMachineState *pnv = PNV_MACHINE(obj); - uint32_t num_chips; - Error *local_err = NULL; - - visit_type_uint32(v, name, &num_chips, &local_err); - if (local_err) { - error_propagate(errp, local_err); - return; - } - - /* - * TODO: should we decide on how many chips we can create based - * on #cores and Venice vs. Murano vs. Naples chip type etc..., - */ - if (!is_power_of_2(num_chips) || num_chips > 4) { - error_setg(errp, "invalid number of chips: '%d'", num_chips); - return; - } - - pnv->num_chips = num_chips; -} - -static void pnv_machine_instance_init(Object *obj) -{ - PnvMachineState *pnv = PNV_MACHINE(obj); - pnv->num_chips = 1; -} - -static void pnv_machine_class_props_init(ObjectClass *oc) -{ - object_class_property_add(oc, "num-chips", "uint32", - pnv_get_num_chips, pnv_set_num_chips, - NULL, NULL, NULL); - object_class_property_set_description(oc, "num-chips", - "Specifies the number of processor chips", - NULL); -} - static void pnv_machine_power8_class_init(ObjectClass *oc, void *data) { MachineClass *mc = MACHINE_CLASS(oc); @@ -1812,8 +1786,6 @@ static void pnv_machine_class_init(ObjectClass *oc, void *data) */ mc->default_ram_size = INITRD_LOAD_ADDR + INITRD_MAX_SIZE; ispc->print_info = pnv_pic_print_info; - - pnv_machine_class_props_init(oc); } #define DEFINE_PNV8_CHIP_TYPE(type, class_initfn) \ @@ -1866,7 +1838,6 @@ static const TypeInfo types[] = { .parent = TYPE_MACHINE, .abstract = true, .instance_size = sizeof(PnvMachineState), - .instance_init = pnv_machine_instance_init, .class_init = pnv_machine_class_init, .class_size = sizeof(PnvMachineClass), .interfaces = (InterfaceInfo[]) { diff --git a/hw/ppc/pnv_bmc.c b/hw/ppc/pnv_bmc.c index 07fa1e1c7e..8863354c1c 100644 --- a/hw/ppc/pnv_bmc.c +++ b/hw/ppc/pnv_bmc.c @@ -143,8 +143,8 @@ static uint16_t bytes_to_blocks(uint32_t bytes) static void hiomap_cmd(IPMIBmcSim *ibs, uint8_t *cmd, unsigned int cmd_len, RspBuffer *rsp) { - PnvMachineState *pnv = PNV_MACHINE(qdev_get_machine()); - PnvPnor *pnor = pnv->pnor; + PnvPnor *pnor = PNV_PNOR(object_property_get_link(OBJECT(ibs), "pnor", + &error_abort)); uint32_t pnor_size = pnor->size; uint32_t pnor_addr = PNOR_SPI_OFFSET; bool readonly = false; @@ -217,11 +217,13 @@ static const IPMINetfn hiomap_netfn = { * Instantiate the machine BMC. PowerNV uses the QEMU internal * simulator but it could also be external. */ -IPMIBmc *pnv_bmc_create(void) +IPMIBmc *pnv_bmc_create(PnvPnor *pnor) { Object *obj; obj = object_new(TYPE_IPMI_BMC_SIMULATOR); + object_ref(OBJECT(pnor)); + object_property_add_const_link(obj, "pnor", OBJECT(pnor), &error_abort); object_property_set_bool(obj, true, "realized", &error_fatal); /* Install the HIOMAP protocol handlers to access the PNOR */ diff --git a/hw/ppc/pnv_pnor.c b/hw/ppc/pnv_pnor.c index bfb1e92b03..b061106d1c 100644 --- a/hw/ppc/pnv_pnor.c +++ b/hw/ppc/pnv_pnor.c @@ -33,6 +33,7 @@ static uint64_t pnv_pnor_read(void *opaque, hwaddr addr, unsigned size) static void pnv_pnor_update(PnvPnor *s, int offset, int size) { int offset_end; + int ret; if (s->blk) { return; @@ -42,8 +43,11 @@ static void pnv_pnor_update(PnvPnor *s, int offset, int size) offset = QEMU_ALIGN_DOWN(offset, BDRV_SECTOR_SIZE); offset_end = QEMU_ALIGN_UP(offset_end, BDRV_SECTOR_SIZE); - blk_pwrite(s->blk, offset, s->storage + offset, - offset_end - offset, 0); + ret = blk_pwrite(s->blk, offset, s->storage + offset, + offset_end - offset, 0); + if (ret < 0) { + error_report("Could not update PNOR: %s", strerror(-ret)); + } } static void pnv_pnor_write(void *opaque, hwaddr addr, uint64_t data, @@ -107,7 +111,7 @@ static void pnv_pnor_realize(DeviceState *dev, Error **errp) } static Property pnv_pnor_properties[] = { - DEFINE_PROP_UINT32("size", PnvPnor, size, 128 << 20), + DEFINE_PROP_INT64("size", PnvPnor, size, 128 << 20), DEFINE_PROP_DRIVE("drive", PnvPnor, blk), DEFINE_PROP_END_OF_LIST(), }; diff --git a/hw/ppc/pnv_psi.c b/hw/ppc/pnv_psi.c index 75e20d9da0..1d8da31738 100644 --- a/hw/ppc/pnv_psi.c +++ b/hw/ppc/pnv_psi.c @@ -455,7 +455,7 @@ static const MemoryRegionOps pnv_psi_xscom_ops = { } }; -static void pnv_psi_reset(void *dev) +static void pnv_psi_reset(DeviceState *dev) { PnvPsi *psi = PNV_PSI(dev); @@ -464,12 +464,29 @@ static void pnv_psi_reset(void *dev) psi->regs[PSIHB_XSCOM_BAR] = psi->bar | PSIHB_BAR_EN; } +static void pnv_psi_reset_handler(void *dev) +{ + device_reset(DEVICE(dev)); +} + +static void pnv_psi_realize(DeviceState *dev, Error **errp) +{ + PnvPsi *psi = PNV_PSI(dev); + + /* Default BAR for MMIO region */ + pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); + + qemu_register_reset(pnv_psi_reset_handler, dev); +} + static void pnv_psi_power8_instance_init(Object *obj) { Pnv8Psi *psi8 = PNV8_PSI(obj); object_initialize_child(obj, "ics-psi", &psi8->ics, sizeof(psi8->ics), TYPE_ICS, &error_abort, NULL); + object_property_add_alias(obj, ICS_PROP_XICS, OBJECT(&psi8->ics), + ICS_PROP_XICS, &error_abort); } static const uint8_t irq_to_xivr[] = { @@ -485,19 +502,10 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) { PnvPsi *psi = PNV_PSI(dev); ICSState *ics = &PNV8_PSI(psi)->ics; - Object *obj; Error *err = NULL; unsigned int i; - obj = object_property_get_link(OBJECT(dev), "xics", &err); - if (!obj) { - error_setg(errp, "%s: required link 'xics' not found: %s", - __func__, error_get_pretty(err)); - return; - } - /* Create PSI interrupt control source */ - object_property_set_link(OBJECT(ics), obj, ICS_PROP_XICS, &error_abort); object_property_set_int(OBJECT(ics), PSI_NUM_INTERRUPTS, "nr-irqs", &err); if (err) { error_propagate(errp, err); @@ -523,9 +531,6 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) memory_region_init_io(&psi->regs_mr, OBJECT(dev), &psi_mmio_ops, psi, "psihb", PNV_PSIHB_SIZE); - /* Default BAR for MMIO region */ - pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); - /* Default sources in XIVR */ for (i = 0; i < PSI_NUM_INTERRUPTS; i++) { uint8_t xivr = irq_to_xivr[i]; @@ -533,7 +538,7 @@ static void pnv_psi_power8_realize(DeviceState *dev, Error **errp) ((uint64_t) i << PSIHB_XIVR_SRC_SH); } - qemu_register_reset(pnv_psi_reset, dev); + pnv_psi_realize(dev, errp); } static int pnv_psi_dt_xscom(PnvXScomInterface *dev, void *fdt, int xscom_offset) @@ -816,7 +821,7 @@ static void pnv_psi_power9_irq_set(PnvPsi *psi, int irq, bool state) qemu_set_irq(psi->qirqs[irq], state); } -static void pnv_psi_power9_reset(void *dev) +static void pnv_psi_power9_reset(DeviceState *dev) { Pnv9Psi *psi = PNV9_PSI(dev); @@ -868,9 +873,7 @@ static void pnv_psi_power9_realize(DeviceState *dev, Error **errp) memory_region_init_io(&psi->regs_mr, OBJECT(dev), &pnv_psi_p9_mmio_ops, psi, "psihb", PNV9_PSIHB_SIZE); - pnv_psi_set_bar(psi, psi->bar | PSIHB_BAR_EN); - - qemu_register_reset(pnv_psi_power9_reset, dev); + pnv_psi_realize(dev, errp); } static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) @@ -882,6 +885,7 @@ static void pnv_psi_power9_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV PSI Controller POWER9"; dc->realize = pnv_psi_power9_realize; + dc->reset = pnv_psi_power9_reset; ppc->xscom_pcba = PNV9_XSCOM_PSIHB_BASE; ppc->xscom_size = PNV9_XSCOM_PSIHB_SIZE; @@ -934,6 +938,7 @@ static void pnv_psi_class_init(ObjectClass *klass, void *data) dc->desc = "PowerNV PSI Controller"; dc->props = pnv_psi_properties; + dc->reset = pnv_psi_reset; } static const TypeInfo pnv_psi_info = { diff --git a/hw/ppc/ppc440_bamboo.c b/hw/ppc/ppc440_bamboo.c index 4d95c0f8a8..b782641b23 100644 --- a/hw/ppc/ppc440_bamboo.c +++ b/hw/ppc/ppc440_bamboo.c @@ -71,12 +71,12 @@ static int bamboo_load_device_tree(hwaddr addr, filename = qemu_find_file(QEMU_FILE_TYPE_BIOS, BINARY_DEVICE_TREE_FILE); if (!filename) { - goto out; + return -1; } fdt = load_device_tree(filename, &fdt_size); g_free(filename); if (fdt == NULL) { - goto out; + return -1; } /* Manipulate device tree in memory. */ @@ -117,10 +117,6 @@ static int bamboo_load_device_tree(hwaddr addr, rom_add_blob_fixed(BINARY_DEVICE_TREE_FILE, fdt, fdt_size, addr); g_free(fdt); return 0; - -out: - - return ret; } /* Create reset TLB entries for BookE, spanning the 32bit addr space. */ diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c index f11422fc41..30a5fbd3be 100644 --- a/hw/ppc/spapr.c +++ b/hw/ppc/spapr.c @@ -878,7 +878,7 @@ static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, g_assert(smc->dr_lmb_enabled); ret = spapr_populate_drconf_memory(spapr, fdt); if (ret) { - goto out; + return ret; } } @@ -889,11 +889,8 @@ static int spapr_dt_cas_updates(SpaprMachineState *spapr, void *fdt, return offset; } } - ret = spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, - "ibm,architecture-vec-5"); - -out: - return ret; + return spapr_ovec_populate_dt(fdt, offset, spapr->ov5_cas, + "ibm,architecture-vec-5"); } static void spapr_dt_rtas(SpaprMachineState *spapr, void *fdt) @@ -1597,6 +1594,7 @@ static void spapr_machine_reset(MachineState *machine) void *fdt; int rc; + kvmppc_svm_off(&error_fatal); spapr_caps_apply(spapr); first_ppc_cpu = POWERPC_CPU(first_cpu); @@ -4197,19 +4195,19 @@ static void spapr_pic_print_info(InterruptStatsProvider *obj, kvm_irqchip_in_kernel() ? "in-kernel" : "emulated"); } +/* + * This is a XIVE only operation + */ static int spapr_match_nvt(XiveFabric *xfb, uint8_t format, uint8_t nvt_blk, uint32_t nvt_idx, bool cam_ignore, uint8_t priority, uint32_t logic_serv, XiveTCTXMatch *match) { SpaprMachineState *spapr = SPAPR_MACHINE(xfb); - XivePresenter *xptr = XIVE_PRESENTER(spapr->xive); + XivePresenter *xptr = XIVE_PRESENTER(spapr->active_intc); XivePresenterClass *xpc = XIVE_PRESENTER_GET_CLASS(xptr); int count; - /* This is a XIVE only operation */ - assert(spapr->active_intc == SPAPR_INTC(spapr->xive)); - count = xpc->match_nvt(xptr, format, nvt_blk, nvt_idx, cam_ignore, priority, logic_serv, match); if (count < 0) { diff --git a/hw/ppc/spapr_irq.c b/hw/ppc/spapr_irq.c index 373505d28b..1f630f296b 100644 --- a/hw/ppc/spapr_irq.c +++ b/hw/ppc/spapr_irq.c @@ -332,6 +332,8 @@ void spapr_irq_init(SpaprMachineState *spapr, Error **errp) * priority */ qdev_prop_set_uint32(dev, "nr-ends", nr_servers << 3); + object_property_set_link(OBJECT(dev), OBJECT(spapr), "xive-fabric", + &error_abort); qdev_init_nofail(dev); spapr->xive = SPAPR_XIVE(dev); |