diff options
Diffstat (limited to 'hw/sd/ssi-sd.c')
| -rw-r--r-- | hw/sd/ssi-sd.c | 136 |
1 files changed, 116 insertions, 20 deletions
diff --git a/hw/sd/ssi-sd.c b/hw/sd/ssi-sd.c index be1bb10164..97ee58e20c 100644 --- a/hw/sd/ssi-sd.c +++ b/hw/sd/ssi-sd.c @@ -4,6 +4,11 @@ * Copyright (c) 2007-2009 CodeSourcery. * Written by Paul Brook * + * Copyright (c) 2021 Wind River Systems, Inc. + * Improved by Bin Meng <bin.meng@windriver.com> + * + * Validated with U-Boot v2021.01 and Linux v5.10 mmc_spi driver + * * This code is licensed under the GNU GPL v2. * * Contributions after 2012-01-13 are licensed under the terms of the @@ -43,6 +48,8 @@ typedef enum { SSI_SD_DATA_START, SSI_SD_DATA_READ, SSI_SD_DATA_CRC16, + SSI_SD_DATA_WRITE, + SSI_SD_SKIP_CRC16, } ssi_sd_mode; struct ssi_sd_state { @@ -52,6 +59,8 @@ struct ssi_sd_state { uint8_t cmdarg[4]; uint8_t response[5]; uint16_t crc16; + int32_t read_bytes; + int32_t write_bytes; int32_t arglen; int32_t response_pos; int32_t stopping; @@ -78,37 +87,86 @@ OBJECT_DECLARE_SIMPLE_TYPE(ssi_sd_state, SSI_SD) #define SSI_SDR_ADDRESS_ERROR 0x2000 #define SSI_SDR_PARAMETER_ERROR 0x4000 +/* multiple block write */ +#define SSI_TOKEN_MULTI_WRITE 0xfc +/* terminate multiple block write */ +#define SSI_TOKEN_STOP_TRAN 0xfd /* single block read/write, multiple block read */ #define SSI_TOKEN_SINGLE 0xfe /* dummy value - don't care */ #define SSI_DUMMY 0xff +/* data accepted */ +#define DATA_RESPONSE_ACCEPTED 0x05 + static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) { ssi_sd_state *s = SSI_SD(dev); + SDRequest request; + uint8_t longresp[16]; - /* Special case: allow CMD12 (STOP TRANSMISSION) while reading data. */ - if (s->mode == SSI_SD_DATA_READ && val == 0x4c) { - s->mode = SSI_SD_CMD; - /* There must be at least one byte delay before the card responds. */ - s->stopping = 1; + /* + * Special case: allow CMD12 (STOP TRANSMISSION) while reading data. + * + * See "Physical Layer Specification Version 8.00" chapter 7.5.2.2, + * to avoid conflict between CMD12 response and next data block, + * timing of CMD12 should be controlled as follows: + * + * - CMD12 issued at the timing that end bit of CMD12 and end bit of + * data block is overlapped + * - CMD12 issued after one clock cycle after host receives a token + * (either Start Block token or Data Error token) + * + * We need to catch CMD12 in all of the data read states. + */ + if (s->mode >= SSI_SD_PREP_DATA && s->mode <= SSI_SD_DATA_CRC16) { + if (val == 0x4c) { + s->mode = SSI_SD_CMD; + /* There must be at least one byte delay before the card responds */ + s->stopping = 1; + } } switch (s->mode) { case SSI_SD_CMD: - if (val == SSI_DUMMY) { + switch (val) { + case SSI_DUMMY: DPRINTF("NULL command\n"); return SSI_DUMMY; + break; + case SSI_TOKEN_SINGLE: + case SSI_TOKEN_MULTI_WRITE: + DPRINTF("Start write block\n"); + s->mode = SSI_SD_DATA_WRITE; + return SSI_DUMMY; + case SSI_TOKEN_STOP_TRAN: + DPRINTF("Stop multiple write\n"); + + /* manually issue cmd12 to stop the transfer */ + request.cmd = 12; + request.arg = 0; + s->arglen = sdbus_do_command(&s->sdbus, &request, longresp); + if (s->arglen <= 0) { + s->arglen = 1; + /* a zero value indicates the card is busy */ + s->response[0] = 0; + DPRINTF("SD card busy\n"); + } else { + s->arglen = 1; + /* a non-zero value indicates the card is ready */ + s->response[0] = SSI_DUMMY; + } + + return SSI_DUMMY; } + s->cmd = val & 0x3f; s->mode = SSI_SD_CMDARG; s->arglen = 0; return SSI_DUMMY; case SSI_SD_CMDARG: if (s->arglen == 4) { - SDRequest request; - uint8_t longresp[16]; /* FIXME: Check CRC. */ request.cmd = s->cmd; request.arg = ldl_be_p(s->cmdarg); @@ -118,9 +176,9 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) s->arglen = 1; s->response[0] = 4; DPRINTF("SD command failed\n"); - } else if (s->cmd == 58) { - /* CMD58 returns R3 response (OCR) */ - DPRINTF("Returned OCR\n"); + } else if (s->cmd == 8 || s->cmd == 58) { + /* CMD8/CMD58 returns R3/R7 response */ + DPRINTF("Returned R3/R7\n"); s->arglen = 5; s->response[0] = 1; memcpy(&s->response[1], longresp, 4); @@ -136,6 +194,12 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) /* CMD13 returns a 2-byte statuse work. Other commands only return the first byte. */ s->arglen = (s->cmd == 13) ? 2 : 1; + + /* handle R1b */ + if (s->cmd == 28 || s->cmd == 29 || s->cmd == 38) { + s->stopping = 1; + } + cardstatus = ldl_be_p(longresp); status = 0; if (((cardstatus >> 9) & 0xf) < 4) @@ -185,14 +249,15 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) s->mode = SSI_SD_RESPONSE; return SSI_DUMMY; case SSI_SD_RESPONSE: - if (s->stopping) { - s->stopping = 0; - return SSI_DUMMY; - } if (s->response_pos < s->arglen) { DPRINTF("Response 0x%02x\n", s->response[s->response_pos]); return s->response[s->response_pos++]; } + if (s->stopping) { + s->stopping = 0; + s->mode = SSI_SD_CMD; + return SSI_DUMMY; + } if (sdbus_data_ready(&s->sdbus)) { DPRINTF("Data read\n"); s->mode = SSI_SD_DATA_START; @@ -212,8 +277,9 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) return SSI_TOKEN_SINGLE; case SSI_SD_DATA_READ: val = sdbus_read_byte(&s->sdbus); + s->read_bytes++; s->crc16 = crc_ccitt_false(s->crc16, (uint8_t *)&val, 1); - if (!sdbus_data_ready(&s->sdbus)) { + if (!sdbus_data_ready(&s->sdbus) || s->read_bytes == 512) { DPRINTF("Data read end\n"); s->mode = SSI_SD_DATA_CRC16; } @@ -224,10 +290,36 @@ static uint32_t ssi_sd_transfer(SSIPeripheral *dev, uint32_t val) s->response_pos++; if (s->response_pos == 2) { DPRINTF("CRC16 read end\n"); - s->mode = SSI_SD_CMD; + if (s->read_bytes == 512 && s->cmd != 17) { + s->mode = SSI_SD_PREP_DATA; + } else { + s->mode = SSI_SD_CMD; + } + s->read_bytes = 0; s->response_pos = 0; } return val; + case SSI_SD_DATA_WRITE: + sdbus_write_byte(&s->sdbus, val); + s->write_bytes++; + if (!sdbus_receive_ready(&s->sdbus) || s->write_bytes == 512) { + DPRINTF("Data write end\n"); + s->mode = SSI_SD_SKIP_CRC16; + s->response_pos = 0; + } + return val; + case SSI_SD_SKIP_CRC16: + /* we don't verify the crc16 */ + s->response_pos++; + if (s->response_pos == 2) { + DPRINTF("CRC16 receive end\n"); + s->mode = SSI_SD_RESPONSE; + s->write_bytes = 0; + s->arglen = 1; + s->response[0] = DATA_RESPONSE_ACCEPTED; + s->response_pos = 0; + } + return SSI_DUMMY; } /* Should never happen. */ return SSI_DUMMY; @@ -237,7 +329,7 @@ static int ssi_sd_post_load(void *opaque, int version_id) { ssi_sd_state *s = (ssi_sd_state *)opaque; - if (s->mode > SSI_SD_DATA_CRC16) { + if (s->mode > SSI_SD_SKIP_CRC16) { return -EINVAL; } if (s->mode == SSI_SD_CMDARG && @@ -255,8 +347,8 @@ static int ssi_sd_post_load(void *opaque, int version_id) static const VMStateDescription vmstate_ssi_sd = { .name = "ssi_sd", - .version_id = 5, - .minimum_version_id = 5, + .version_id = 7, + .minimum_version_id = 7, .post_load = ssi_sd_post_load, .fields = (VMStateField []) { VMSTATE_UINT32(mode, ssi_sd_state), @@ -264,6 +356,8 @@ static const VMStateDescription vmstate_ssi_sd = { VMSTATE_UINT8_ARRAY(cmdarg, ssi_sd_state, 4), VMSTATE_UINT8_ARRAY(response, ssi_sd_state, 5), VMSTATE_UINT16(crc16, ssi_sd_state), + VMSTATE_INT32(read_bytes, ssi_sd_state), + VMSTATE_INT32(write_bytes, ssi_sd_state), VMSTATE_INT32(arglen, ssi_sd_state), VMSTATE_INT32(response_pos, ssi_sd_state), VMSTATE_INT32(stopping, ssi_sd_state), @@ -316,6 +410,8 @@ static void ssi_sd_reset(DeviceState *dev) memset(s->cmdarg, 0, sizeof(s->cmdarg)); memset(s->response, 0, sizeof(s->response)); s->crc16 = 0; + s->read_bytes = 0; + s->write_bytes = 0; s->arglen = 0; s->response_pos = 0; s->stopping = 0; |