diff options
Diffstat (limited to 'hw/sd')
| -rw-r--r-- | hw/sd/core.c | 61 | ||||
| -rw-r--r-- | hw/sd/sd.c | 29 | ||||
| -rw-r--r-- | hw/sd/sdhci-internal.h | 71 | ||||
| -rw-r--r-- | hw/sd/sdhci.c | 397 | ||||
| -rw-r--r-- | hw/sd/trace-events | 9 |
5 files changed, 444 insertions, 123 deletions
diff --git a/hw/sd/core.c b/hw/sd/core.c index 295dc44ab7..3c6eae6c88 100644 --- a/hw/sd/core.c +++ b/hw/sd/core.c @@ -23,6 +23,12 @@ #include "hw/qdev-core.h" #include "sysemu/block-backend.h" #include "hw/sd/sd.h" +#include "trace.h" + +static inline const char *sdbus_name(SDBus *sdbus) +{ + return sdbus->qbus.name; +} static SDState *get_card(SDBus *sdbus) { @@ -35,10 +41,58 @@ static SDState *get_card(SDBus *sdbus) return SD_CARD(kid->child); } +uint8_t sdbus_get_dat_lines(SDBus *sdbus) +{ + SDState *slave = get_card(sdbus); + uint8_t dat_lines = 0b1111; /* 4 bit bus width */ + + if (slave) { + SDCardClass *sc = SD_CARD_GET_CLASS(slave); + + if (sc->get_dat_lines) { + dat_lines = sc->get_dat_lines(slave); + } + } + trace_sdbus_get_dat_lines(sdbus_name(sdbus), dat_lines); + + return dat_lines; +} + +bool sdbus_get_cmd_line(SDBus *sdbus) +{ + SDState *slave = get_card(sdbus); + bool cmd_line = true; + + if (slave) { + SDCardClass *sc = SD_CARD_GET_CLASS(slave); + + if (sc->get_cmd_line) { + cmd_line = sc->get_cmd_line(slave); + } + } + trace_sdbus_get_cmd_line(sdbus_name(sdbus), cmd_line); + + return cmd_line; +} + +void sdbus_set_voltage(SDBus *sdbus, uint16_t millivolts) +{ + SDState *card = get_card(sdbus); + + trace_sdbus_set_voltage(sdbus_name(sdbus), millivolts); + if (card) { + SDCardClass *sc = SD_CARD_GET_CLASS(card); + + assert(sc->set_voltage); + sc->set_voltage(card, millivolts); + } +} + int sdbus_do_command(SDBus *sdbus, SDRequest *req, uint8_t *response) { SDState *card = get_card(sdbus); + trace_sdbus_command(sdbus_name(sdbus), req->cmd, req->arg, req->crc); if (card) { SDCardClass *sc = SD_CARD_GET_CLASS(card); @@ -52,6 +106,7 @@ void sdbus_write_data(SDBus *sdbus, uint8_t value) { SDState *card = get_card(sdbus); + trace_sdbus_write(sdbus_name(sdbus), value); if (card) { SDCardClass *sc = SD_CARD_GET_CLASS(card); @@ -62,14 +117,16 @@ void sdbus_write_data(SDBus *sdbus, uint8_t value) uint8_t sdbus_read_data(SDBus *sdbus) { SDState *card = get_card(sdbus); + uint8_t value = 0; if (card) { SDCardClass *sc = SD_CARD_GET_CLASS(card); - return sc->read_data(card); + value = sc->read_data(card); } + trace_sdbus_read(sdbus_name(sdbus), value); - return 0; + return value; } bool sdbus_data_ready(SDBus *sdbus) diff --git a/hw/sd/sd.c b/hw/sd/sd.c index 73e405a04f..9ac9b63ff8 100644 --- a/hw/sd/sd.c +++ b/hw/sd/sd.c @@ -126,8 +126,32 @@ struct SDState { BlockBackend *blk; bool enable; + uint8_t dat_lines; + bool cmd_line; }; +static uint8_t sd_get_dat_lines(SDState *sd) +{ + return sd->enable ? sd->dat_lines : 0; +} + +static bool sd_get_cmd_line(SDState *sd) +{ + return sd->enable ? sd->cmd_line : false; +} + +static void sd_set_voltage(SDState *sd, uint16_t millivolts) +{ + switch (millivolts) { + case 3001 ... 3600: /* SD_VOLTAGE_3_3V */ + case 2001 ... 3000: /* SD_VOLTAGE_3_0V */ + break; + default: + qemu_log_mask(LOG_GUEST_ERROR, "SD card voltage not supported: %.3fV", + millivolts / 1000.f); + } +} + static void sd_set_mode(SDState *sd) { switch (sd->state) { @@ -445,6 +469,8 @@ static void sd_reset(DeviceState *dev) sd->blk_len = 0x200; sd->pwd_len = 0; sd->expecting_acmd = false; + sd->dat_lines = 0xf; + sd->cmd_line = true; sd->multi_blk_cnt = 0; } @@ -1926,6 +1952,9 @@ static void sd_class_init(ObjectClass *klass, void *data) dc->reset = sd_reset; dc->bus_type = TYPE_SD_BUS; + sc->set_voltage = sd_set_voltage; + sc->get_dat_lines = sd_get_dat_lines; + sc->get_cmd_line = sd_get_cmd_line; sc->do_command = sd_do_command; sc->write_data = sd_write_data; sc->read_data = sd_read_data; diff --git a/hw/sd/sdhci-internal.h b/hw/sd/sdhci-internal.h index 0991acd724..756ef3f3c2 100644 --- a/hw/sd/sdhci-internal.h +++ b/hw/sd/sdhci-internal.h @@ -24,6 +24,8 @@ #ifndef SDHCI_INTERNAL_H #define SDHCI_INTERNAL_H +#include "hw/registerfields.h" + /* R/W SDMA System Address register 0x0 */ #define SDHC_SYSAD 0x00 @@ -41,6 +43,7 @@ #define SDHC_TRNS_DMA 0x0001 #define SDHC_TRNS_BLK_CNT_EN 0x0002 #define SDHC_TRNS_ACMD12 0x0004 +#define SDHC_TRNS_ACMD23 0x0008 /* since v3 */ #define SDHC_TRNS_READ 0x0010 #define SDHC_TRNS_MULTI 0x0020 #define SDHC_TRNMOD_MASK 0x0037 @@ -79,15 +82,19 @@ #define SDHC_CARD_PRESENT 0x00010000 #define SDHC_CARD_DETECT 0x00040000 #define SDHC_WRITE_PROTECT 0x00080000 +FIELD(SDHC_PRNSTS, DAT_LVL, 20, 4); +FIELD(SDHC_PRNSTS, CMD_LVL, 24, 1); #define TRANSFERRING_DATA(x) \ ((x) & (SDHC_DOING_READ | SDHC_DOING_WRITE)) /* R/W Host control Register 0x0 */ #define SDHC_HOSTCTL 0x28 #define SDHC_CTRL_LED 0x01 +#define SDHC_CTRL_DATATRANSFERWIDTH 0x02 /* SD mode only */ +#define SDHC_CTRL_HIGH_SPEED 0x04 #define SDHC_CTRL_DMA_CHECK_MASK 0x18 #define SDHC_CTRL_SDMA 0x00 -#define SDHC_CTRL_ADMA1_32 0x08 +#define SDHC_CTRL_ADMA1_32 0x08 /* NOT ALLOWED since v2 */ #define SDHC_CTRL_ADMA2_32 0x10 #define SDHC_CTRL_ADMA2_64 0x18 #define SDHC_DMA_TYPE(x) ((x) & SDHC_CTRL_DMA_CHECK_MASK) @@ -96,10 +103,10 @@ #define SDHC_CTRL_CDTEST_INS 0x40 #define SDHC_CTRL_CDTEST_EN 0x80 - /* R/W Power Control Register 0x0 */ #define SDHC_PWRCON 0x29 #define SDHC_POWER_ON (1 << 0) +FIELD(SDHC_PWRCON, BUS_VOLTAGE, 1, 3); /* R/W Block Gap Control Register 0x0 */ #define SDHC_BLKGAP 0x2A @@ -122,6 +129,7 @@ /* R/W Timeout Control Register 0x0 */ #define SDHC_TIMEOUTCON 0x2E +FIELD(SDHC_TIMEOUTCON, COUNTER, 0, 4); /* R/W Software Reset Register 0x0 */ #define SDHC_SWRST 0x2F @@ -178,17 +186,62 @@ /* ROC Auto CMD12 error status register 0x0 */ #define SDHC_ACMD12ERRSTS 0x3C +FIELD(SDHC_ACMD12ERRSTS, TIMEOUT_ERR, 1, 1); +FIELD(SDHC_ACMD12ERRSTS, CRC_ERR, 2, 1); +FIELD(SDHC_ACMD12ERRSTS, INDEX_ERR, 4, 1); + +/* Host Control Register 2 (since v3) */ +#define SDHC_HOSTCTL2 0x3E +FIELD(SDHC_HOSTCTL2, UHS_MODE_SEL, 0, 3); +FIELD(SDHC_HOSTCTL2, V18_ENA, 3, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, DRIVER_STRENGTH, 4, 2); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, EXECUTE_TUNING, 6, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, SAMPLING_CLKSEL, 7, 1); /* UHS-I only */ +FIELD(SDHC_HOSTCTL2, UHS_II_ENA, 8, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, ADMA2_LENGTH, 10, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, CMD23_ENA, 11, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, VERSION4, 12, 1); /* since v4 */ +FIELD(SDHC_HOSTCTL2, ASYNC_INT, 14, 1); +FIELD(SDHC_HOSTCTL2, PRESET_ENA, 15, 1); /* HWInit Capabilities Register 0x05E80080 */ #define SDHC_CAPAB 0x40 -#define SDHC_CAN_DO_DMA 0x00400000 -#define SDHC_CAN_DO_ADMA2 0x00080000 -#define SDHC_CAN_DO_ADMA1 0x00100000 -#define SDHC_64_BIT_BUS_SUPPORT (1 << 28) -#define SDHC_CAPAB_BLOCKSIZE(x) (((x) >> 16) & 0x3) +FIELD(SDHC_CAPAB, TOCLKFREQ, 0, 6); +FIELD(SDHC_CAPAB, TOUNIT, 7, 1); +FIELD(SDHC_CAPAB, BASECLKFREQ, 8, 8); +FIELD(SDHC_CAPAB, MAXBLOCKLENGTH, 16, 2); +FIELD(SDHC_CAPAB, EMBEDDED_8BIT, 18, 1); /* since v3 */ +FIELD(SDHC_CAPAB, ADMA2, 19, 1); /* since v2 */ +FIELD(SDHC_CAPAB, ADMA1, 20, 1); /* v1 only? */ +FIELD(SDHC_CAPAB, HIGHSPEED, 21, 1); +FIELD(SDHC_CAPAB, SDMA, 22, 1); +FIELD(SDHC_CAPAB, SUSPRESUME, 23, 1); +FIELD(SDHC_CAPAB, V33, 24, 1); +FIELD(SDHC_CAPAB, V30, 25, 1); +FIELD(SDHC_CAPAB, V18, 26, 1); +FIELD(SDHC_CAPAB, BUS64BIT_V4, 27, 1); /* since v4.10 */ +FIELD(SDHC_CAPAB, BUS64BIT, 28, 1); /* since v2 */ +FIELD(SDHC_CAPAB, ASYNC_INT, 29, 1); /* since v3 */ +FIELD(SDHC_CAPAB, SLOT_TYPE, 30, 2); /* since v3 */ +FIELD(SDHC_CAPAB, BUS_SPEED, 32, 3); /* since v3 */ +FIELD(SDHC_CAPAB, UHS_II, 35, 8); /* since v4.20 */ +FIELD(SDHC_CAPAB, DRIVER_STRENGTH, 36, 3); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_TYPE_A, 36, 1); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_TYPE_C, 37, 1); /* since v3 */ +FIELD(SDHC_CAPAB, DRIVER_TYPE_D, 38, 1); /* since v3 */ +FIELD(SDHC_CAPAB, TIMER_RETUNING, 40, 4); /* since v3 */ +FIELD(SDHC_CAPAB, SDR50_TUNING, 45, 1); /* since v3 */ +FIELD(SDHC_CAPAB, RETUNING_MODE, 46, 2); /* since v3 */ +FIELD(SDHC_CAPAB, CLOCK_MULT, 48, 8); /* since v3 */ +FIELD(SDHC_CAPAB, ADMA3, 59, 1); /* since v4.20 */ +FIELD(SDHC_CAPAB, V18_VDD2, 60, 1); /* since v4.20 */ /* HWInit Maximum Current Capabilities Register 0x0 */ #define SDHC_MAXCURR 0x48 +FIELD(SDHC_MAXCURR, V33_VDD1, 0, 8); +FIELD(SDHC_MAXCURR, V30_VDD1, 8, 8); +FIELD(SDHC_MAXCURR, V18_VDD1, 16, 8); +FIELD(SDHC_MAXCURR, V18_VDD2, 32, 8); /* since v4.20 */ /* W Force Event Auto CMD12 Error Interrupt Register 0x0000 */ #define SDHC_FEAER 0x50 @@ -216,9 +269,9 @@ /* Slot interrupt status */ #define SDHC_SLOT_INT_STATUS 0xFC -/* HWInit Host Controller Version Register 0x0401 */ +/* HWInit Host Controller Version Register */ #define SDHC_HCVER 0xFE -#define SD_HOST_SPECv2_VERS 0x2401 +#define SDHC_HCVER_VENDOR 0x24 #define SDHC_REGISTERS_MAP_SIZE 0x100 #define SDHC_INSERTION_DELAY (NANOSECONDS_PER_SECOND) diff --git a/hw/sd/sdhci.c b/hw/sd/sdhci.c index ee95e78aeb..97b4a473c8 100644 --- a/hw/sd/sdhci.c +++ b/hw/sd/sdhci.c @@ -23,6 +23,7 @@ */ #include "qemu/osdep.h" +#include "qemu/error-report.h" #include "qapi/error.h" #include "hw/hw.h" #include "sysemu/block-backend.h" @@ -33,72 +34,194 @@ #include "hw/sd/sdhci.h" #include "sdhci-internal.h" #include "qemu/log.h" +#include "qemu/cutils.h" #include "trace.h" #define TYPE_SDHCI_BUS "sdhci-bus" #define SDHCI_BUS(obj) OBJECT_CHECK(SDBus, (obj), TYPE_SDHCI_BUS) +#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) + /* Default SD/MMC host controller features information, which will be * presented in CAPABILITIES register of generic SD host controller at reset. - * If not stated otherwise: - * 0 - not supported, 1 - supported, other - prohibited. + * + * support: + * - 3.3v and 1.8v voltages + * - SDMA/ADMA1/ADMA2 + * - high-speed + * max host controller R/W buffers size: 512B + * max clock frequency for SDclock: 52 MHz + * timeout clock frequency: 52 MHz + * + * does not support: + * - 3.0v voltage + * - 64-bit system bus + * - suspend/resume */ -#define SDHC_CAPAB_64BITBUS 0ul /* 64-bit System Bus Support */ -#define SDHC_CAPAB_18V 1ul /* Voltage support 1.8v */ -#define SDHC_CAPAB_30V 0ul /* Voltage support 3.0v */ -#define SDHC_CAPAB_33V 1ul /* Voltage support 3.3v */ -#define SDHC_CAPAB_SUSPRESUME 0ul /* Suspend/resume support */ -#define SDHC_CAPAB_SDMA 1ul /* SDMA support */ -#define SDHC_CAPAB_HIGHSPEED 1ul /* High speed support */ -#define SDHC_CAPAB_ADMA1 1ul /* ADMA1 support */ -#define SDHC_CAPAB_ADMA2 1ul /* ADMA2 support */ -/* Maximum host controller R/W buffers size - * Possible values: 512, 1024, 2048 bytes */ -#define SDHC_CAPAB_MAXBLOCKLENGTH 512ul -/* Maximum clock frequency for SDclock in MHz - * value in range 10-63 MHz, 0 - not defined */ -#define SDHC_CAPAB_BASECLKFREQ 52ul -#define SDHC_CAPAB_TOUNIT 1ul /* Timeout clock unit 0 - kHz, 1 - MHz */ -/* Timeout clock frequency 1-63, 0 - not defined */ -#define SDHC_CAPAB_TOCLKFREQ 52ul - -/* Now check all parameters and calculate CAPABILITIES REGISTER value */ -#if SDHC_CAPAB_64BITBUS > 1 || SDHC_CAPAB_18V > 1 || SDHC_CAPAB_30V > 1 || \ - SDHC_CAPAB_33V > 1 || SDHC_CAPAB_SUSPRESUME > 1 || SDHC_CAPAB_SDMA > 1 || \ - SDHC_CAPAB_HIGHSPEED > 1 || SDHC_CAPAB_ADMA2 > 1 || SDHC_CAPAB_ADMA1 > 1 ||\ - SDHC_CAPAB_TOUNIT > 1 -#error Capabilities features can have value 0 or 1 only! -#endif - -#if SDHC_CAPAB_MAXBLOCKLENGTH == 512 -#define MAX_BLOCK_LENGTH 0ul -#elif SDHC_CAPAB_MAXBLOCKLENGTH == 1024 -#define MAX_BLOCK_LENGTH 1ul -#elif SDHC_CAPAB_MAXBLOCKLENGTH == 2048 -#define MAX_BLOCK_LENGTH 2ul -#else -#error Max host controller block size can have value 512, 1024 or 2048 only! -#endif - -#if (SDHC_CAPAB_BASECLKFREQ > 0 && SDHC_CAPAB_BASECLKFREQ < 10) || \ - SDHC_CAPAB_BASECLKFREQ > 63 -#error SDclock frequency can have value in range 0, 10-63 only! -#endif - -#if SDHC_CAPAB_TOCLKFREQ > 63 -#error Timeout clock frequency can have value in range 0-63 only! -#endif - -#define SDHC_CAPAB_REG_DEFAULT \ - ((SDHC_CAPAB_64BITBUS << 28) | (SDHC_CAPAB_18V << 26) | \ - (SDHC_CAPAB_30V << 25) | (SDHC_CAPAB_33V << 24) | \ - (SDHC_CAPAB_SUSPRESUME << 23) | (SDHC_CAPAB_SDMA << 22) | \ - (SDHC_CAPAB_HIGHSPEED << 21) | (SDHC_CAPAB_ADMA1 << 20) | \ - (SDHC_CAPAB_ADMA2 << 19) | (MAX_BLOCK_LENGTH << 16) | \ - (SDHC_CAPAB_BASECLKFREQ << 8) | (SDHC_CAPAB_TOUNIT << 7) | \ - (SDHC_CAPAB_TOCLKFREQ)) +#define SDHC_CAPAB_REG_DEFAULT 0x057834b4 -#define MASKED_WRITE(reg, mask, val) (reg = (reg & (mask)) | (val)) +static inline unsigned int sdhci_get_fifolen(SDHCIState *s) +{ + return 1 << (9 + FIELD_EX32(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH)); +} + +/* return true on error */ +static bool sdhci_check_capab_freq_range(SDHCIState *s, const char *desc, + uint8_t freq, Error **errp) +{ + if (s->sd_spec_version >= 3) { + return false; + } + switch (freq) { + case 0: + case 10 ... 63: + break; + default: + error_setg(errp, "SD %s clock frequency can have value" + "in range 0-63 only", desc); + return true; + } + return false; +} + +static void sdhci_check_capareg(SDHCIState *s, Error **errp) +{ + uint64_t msk = s->capareg; + uint32_t val; + bool y; + + switch (s->sd_spec_version) { + case 4: + val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT_V4); + trace_sdhci_capareg("64-bit system bus (v4)", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT_V4, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, UHS_II); + trace_sdhci_capareg("UHS-II", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, UHS_II, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA3); + trace_sdhci_capareg("ADMA3", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA3, 0); + + /* fallthrough */ + case 3: + val = FIELD_EX64(s->capareg, SDHC_CAPAB, ASYNC_INT); + trace_sdhci_capareg("async interrupt", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, ASYNC_INT, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, SLOT_TYPE); + if (val) { + error_setg(errp, "slot-type not supported"); + return; + } + trace_sdhci_capareg("slot type", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, SLOT_TYPE, 0); + + if (val != 2) { + val = FIELD_EX64(s->capareg, SDHC_CAPAB, EMBEDDED_8BIT); + trace_sdhci_capareg("8-bit bus", val); + } + msk = FIELD_DP64(msk, SDHC_CAPAB, EMBEDDED_8BIT, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS_SPEED); + trace_sdhci_capareg("bus speed mask", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, BUS_SPEED, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, DRIVER_STRENGTH); + trace_sdhci_capareg("driver strength mask", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, DRIVER_STRENGTH, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, TIMER_RETUNING); + trace_sdhci_capareg("timer re-tuning", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, TIMER_RETUNING, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDR50_TUNING); + trace_sdhci_capareg("use SDR50 tuning", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, SDR50_TUNING, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, RETUNING_MODE); + trace_sdhci_capareg("re-tuning mode", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, RETUNING_MODE, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, CLOCK_MULT); + trace_sdhci_capareg("clock multiplier", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, CLOCK_MULT, 0); + + /* fallthrough */ + case 2: /* default version */ + val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA2); + trace_sdhci_capareg("ADMA2", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA2, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, ADMA1); + trace_sdhci_capareg("ADMA1", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, ADMA1, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, BUS64BIT); + trace_sdhci_capareg("64-bit system bus (v3)", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, BUS64BIT, 0); + + /* fallthrough */ + case 1: + y = FIELD_EX64(s->capareg, SDHC_CAPAB, TOUNIT); + msk = FIELD_DP64(msk, SDHC_CAPAB, TOUNIT, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, TOCLKFREQ); + trace_sdhci_capareg(y ? "timeout (MHz)" : "Timeout (KHz)", val); + if (sdhci_check_capab_freq_range(s, "timeout", val, errp)) { + return; + } + msk = FIELD_DP64(msk, SDHC_CAPAB, TOCLKFREQ, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, BASECLKFREQ); + trace_sdhci_capareg(y ? "base (MHz)" : "Base (KHz)", val); + if (sdhci_check_capab_freq_range(s, "base", val, errp)) { + return; + } + msk = FIELD_DP64(msk, SDHC_CAPAB, BASECLKFREQ, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, MAXBLOCKLENGTH); + if (val >= 3) { + error_setg(errp, "block size can be 512, 1024 or 2048 only"); + return; + } + trace_sdhci_capareg("max block length", sdhci_get_fifolen(s)); + msk = FIELD_DP64(msk, SDHC_CAPAB, MAXBLOCKLENGTH, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, HIGHSPEED); + trace_sdhci_capareg("high speed", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, HIGHSPEED, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, SDMA); + trace_sdhci_capareg("SDMA", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, SDMA, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, SUSPRESUME); + trace_sdhci_capareg("suspend/resume", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, SUSPRESUME, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, V33); + trace_sdhci_capareg("3.3v", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, V33, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, V30); + trace_sdhci_capareg("3.0v", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, V30, 0); + + val = FIELD_EX64(s->capareg, SDHC_CAPAB, V18); + trace_sdhci_capareg("1.8v", val); + msk = FIELD_DP64(msk, SDHC_CAPAB, V18, 0); + break; + + default: + error_setg(errp, "Unsupported spec version: %u", s->sd_spec_version); + } + if (msk) { + qemu_log_mask(LOG_UNIMP, + "SDHCI: unknown CAPAB mask: 0x%016" PRIx64 "\n", msk); + } +} static uint8_t sdhci_slotint(SDHCIState *s) { @@ -173,7 +296,8 @@ static void sdhci_reset(SDHCIState *s) timer_del(s->insert_timer); timer_del(s->transfer_timer); - /* Set all registers to 0. Capabilities registers are not cleared + + /* Set all registers to 0. Capabilities/Version registers are not cleared * and assumed to always preserve their value, given to them during * initialization */ memset(&s->sdmasysad, 0, (uintptr_t)&s->capareg - (uintptr_t)&s->sdmasysad); @@ -292,19 +416,35 @@ static void sdhci_end_transfer(SDHCIState *s) /* * Programmed i/o data transfer */ +#define BLOCK_SIZE_MASK (4 * K_BYTE - 1) /* Fill host controller's read buffer with BLKSIZE bytes of data from card */ static void sdhci_read_block_from_card(SDHCIState *s) { int index = 0; + uint8_t data; + const uint16_t blk_size = s->blksize & BLOCK_SIZE_MASK; if ((s->trnmod & SDHC_TRNS_MULTI) && (s->trnmod & SDHC_TRNS_BLK_CNT_EN) && (s->blkcnt == 0)) { return; } - for (index = 0; index < (s->blksize & 0x0fff); index++) { - s->fifo_buffer[index] = sdbus_read_data(&s->sdbus); + for (index = 0; index < blk_size; index++) { + data = sdbus_read_data(&s->sdbus); + if (!FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { + /* Device is not in tunning */ + s->fifo_buffer[index] = data; + } + } + + if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, EXECUTE_TUNING)) { + /* Device is in tunning */ + s->hostctl2 &= ~R_SDHC_HOSTCTL2_EXECUTE_TUNING_MASK; + s->hostctl2 |= R_SDHC_HOSTCTL2_SAMPLING_CLKSEL_MASK; + s->prnsts &= ~(SDHC_DAT_LINE_ACTIVE | SDHC_DOING_READ | + SDHC_DATA_INHIBIT); + goto read_done; } /* New data now available for READ through Buffer Port Register */ @@ -329,6 +469,7 @@ static void sdhci_read_block_from_card(SDHCIState *s) } } +read_done: sdhci_update_irq(s); } @@ -348,7 +489,7 @@ static uint32_t sdhci_read_dataport(SDHCIState *s, unsigned size) value |= s->fifo_buffer[s->data_count] << i * 8; s->data_count++; /* check if we've read all valid data (blksize bytes) from buffer */ - if ((s->data_count) >= (s->blksize & 0x0fff)) { + if ((s->data_count) >= (s->blksize & BLOCK_SIZE_MASK)) { trace_sdhci_read_dataport(s->data_count); s->prnsts &= ~SDHC_DATA_AVAILABLE; /* no more data in a buffer */ s->data_count = 0; /* next buff read must start at position [0] */ @@ -395,7 +536,7 @@ static void sdhci_write_block_to_card(SDHCIState *s) } } - for (index = 0; index < (s->blksize & 0x0fff); index++) { + for (index = 0; index < (s->blksize & BLOCK_SIZE_MASK); index++) { sdbus_write_data(&s->sdbus, s->fifo_buffer[index]); } @@ -440,7 +581,7 @@ static void sdhci_write_dataport(SDHCIState *s, uint32_t value, unsigned size) s->fifo_buffer[s->data_count] = value & 0xFF; s->data_count++; value >>= 8; - if (s->data_count >= (s->blksize & 0x0fff)) { + if (s->data_count >= (s->blksize & BLOCK_SIZE_MASK)) { trace_sdhci_write_dataport(s->data_count); s->data_count = 0; s->prnsts &= ~SDHC_SPACE_AVAILABLE; @@ -460,8 +601,8 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) { bool page_aligned = false; unsigned int n, begin; - const uint16_t block_size = s->blksize & 0x0fff; - uint32_t boundary_chk = 1 << (((s->blksize & 0xf000) >> 12) + 12); + const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; + uint32_t boundary_chk = 1 << (((s->blksize & ~BLOCK_SIZE_MASK) >> 12) + 12); uint32_t boundary_count = boundary_chk - (s->sdmasysad % boundary_chk); if (!(s->trnmod & SDHC_TRNS_BLK_CNT_EN) || !s->blkcnt) { @@ -550,7 +691,7 @@ static void sdhci_sdma_transfer_multi_blocks(SDHCIState *s) static void sdhci_sdma_transfer_single_block(SDHCIState *s) { int n; - uint32_t datacnt = s->blksize & 0x0fff; + uint32_t datacnt = s->blksize & BLOCK_SIZE_MASK; if (s->trnmod & SDHC_TRNS_READ) { for (n = 0; n < datacnt; n++) { @@ -580,7 +721,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) uint32_t adma1 = 0; uint64_t adma2 = 0; hwaddr entry_addr = (hwaddr)s->admasysaddr; - switch (SDHC_DMA_TYPE(s->hostctl)) { + switch (SDHC_DMA_TYPE(s->hostctl1)) { case SDHC_CTRL_ADMA2_32: dma_memory_read(s->dma_as, entry_addr, (uint8_t *)&adma2, sizeof(adma2)); @@ -614,8 +755,8 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) dscr->length = le16_to_cpu(dscr->length); dma_memory_read(s->dma_as, entry_addr + 4, (uint8_t *)(&dscr->addr), 8); - dscr->attr = le64_to_cpu(dscr->attr); - dscr->attr &= 0xfffffff8; + dscr->addr = le64_to_cpu(dscr->addr); + dscr->attr &= (uint8_t) ~0xC0; dscr->incr = 12; break; } @@ -626,7 +767,7 @@ static void get_adma_description(SDHCIState *s, ADMADescr *dscr) static void sdhci_do_adma(SDHCIState *s) { unsigned int n, begin, length; - const uint16_t block_size = s->blksize & 0x0fff; + const uint16_t block_size = s->blksize & BLOCK_SIZE_MASK; ADMADescr dscr = {}; int i; @@ -769,7 +910,7 @@ static void sdhci_data_transfer(void *opaque) SDHCIState *s = (SDHCIState *)opaque; if (s->trnmod & SDHC_TRNS_DMA) { - switch (SDHC_DMA_TYPE(s->hostctl)) { + switch (SDHC_DMA_TYPE(s->hostctl1)) { case SDHC_CTRL_SDMA: if ((s->blkcnt == 1) || !(s->trnmod & SDHC_TRNS_MULTI)) { sdhci_sdma_transfer_single_block(s); @@ -779,7 +920,7 @@ static void sdhci_data_transfer(void *opaque) break; case SDHC_CTRL_ADMA1_32: - if (!(s->capareg & SDHC_CAN_DO_ADMA1)) { + if (!(s->capareg & R_SDHC_CAPAB_ADMA1_MASK)) { trace_sdhci_error("ADMA1 not supported"); break; } @@ -787,7 +928,7 @@ static void sdhci_data_transfer(void *opaque) sdhci_do_adma(s); break; case SDHC_CTRL_ADMA2_32: - if (!(s->capareg & SDHC_CAN_DO_ADMA2)) { + if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK)) { trace_sdhci_error("ADMA2 not supported"); break; } @@ -795,8 +936,8 @@ static void sdhci_data_transfer(void *opaque) sdhci_do_adma(s); break; case SDHC_CTRL_ADMA2_64: - if (!(s->capareg & SDHC_CAN_DO_ADMA2) || - !(s->capareg & SDHC_64_BIT_BUS_SUPPORT)) { + if (!(s->capareg & R_SDHC_CAPAB_ADMA2_MASK) || + !(s->capareg & R_SDHC_CAPAB_BUS64BIT_MASK)) { trace_sdhci_error("64 bit ADMA not supported"); break; } @@ -876,9 +1017,13 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) break; case SDHC_PRNSTS: ret = s->prnsts; + ret = FIELD_DP32(ret, SDHC_PRNSTS, DAT_LVL, + sdbus_get_dat_lines(&s->sdbus)); + ret = FIELD_DP32(ret, SDHC_PRNSTS, CMD_LVL, + sdbus_get_cmd_line(&s->sdbus)); break; case SDHC_HOSTCTL: - ret = s->hostctl | (s->pwrcon << 8) | (s->blkgap << 16) | + ret = s->hostctl1 | (s->pwrcon << 8) | (s->blkgap << 16) | (s->wakcon << 24); break; case SDHC_CLKCON: @@ -894,7 +1039,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) ret = s->norintsigen | (s->errintsigen << 16); break; case SDHC_ACMD12ERRSTS: - ret = s->acmd12errsts; + ret = s->acmd12errsts | (s->hostctl2 << 16); break; case SDHC_CAPAB: ret = (uint32_t)s->capareg; @@ -918,7 +1063,7 @@ static uint64_t sdhci_read(void *opaque, hwaddr offset, unsigned size) ret = (uint32_t)(s->admasysaddr >> 32); break; case SDHC_SLOT_INT_STATUS: - ret = (SD_HOST_SPECv2_VERS << 16) | sdhci_slotint(s); + ret = (s->version << 16) | sdhci_slotint(s); break; default: qemu_log_mask(LOG_UNIMP, "SDHC rd_%ub @0x%02" HWADDR_PRIx " " @@ -996,7 +1141,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) MASKED_WRITE(s->sdmasysad, mask, value); /* Writing to last byte of sdmasysad might trigger transfer */ if (!(mask & 0xFF000000) && TRANSFERRING_DATA(s->prnsts) && s->blkcnt && - s->blksize && SDHC_DMA_TYPE(s->hostctl) == SDHC_CTRL_SDMA) { + s->blksize && SDHC_DMA_TYPE(s->hostctl1) == SDHC_CTRL_SDMA) { if (s->trnmod & SDHC_TRNS_MULTI) { sdhci_sdma_transfer_multi_blocks(s); } else { @@ -1026,7 +1171,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) case SDHC_TRNMOD: /* DMA can be enabled only if it is supported as indicated by * capabilities register */ - if (!(s->capareg & SDHC_CAN_DO_DMA)) { + if (!(s->capareg & R_SDHC_CAPAB_SDMA_MASK)) { value &= ~SDHC_TRNS_DMA; } MASKED_WRITE(s->trnmod, mask, value & SDHC_TRNMOD_MASK); @@ -1048,7 +1193,7 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) if (!(mask & 0xFF0000)) { sdhci_blkgap_write(s, value >> 16); } - MASKED_WRITE(s->hostctl, mask, value); + MASKED_WRITE(s->hostctl1, mask, value); MASKED_WRITE(s->pwrcon, mask >> 8, value >> 8); MASKED_WRITE(s->wakcon, mask >> 24, value >> 24); if (!(s->prnsts & SDHC_CARD_PRESENT) || ((s->pwrcon >> 1) & 0x7) < 5 || @@ -1128,7 +1273,16 @@ sdhci_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) sdhci_update_irq(s); break; case SDHC_ACMD12ERRSTS: - MASKED_WRITE(s->acmd12errsts, mask, value); + MASKED_WRITE(s->acmd12errsts, mask, value & UINT16_MAX); + if (s->uhs_mode >= UHS_I) { + MASKED_WRITE(s->hostctl2, mask >> 16, value >> 16); + + if (FIELD_EX32(s->hostctl2, SDHC_HOSTCTL2, V18_ENA)) { + sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_1_8V); + } else { + sdbus_set_voltage(&s->sdbus, SD_VOLTAGE_3_3V); + } + } break; case SDHC_CAPAB: @@ -1159,26 +1313,34 @@ static const MemoryRegionOps sdhci_mmio_ops = { .endianness = DEVICE_LITTLE_ENDIAN, }; -static inline unsigned int sdhci_get_fifolen(SDHCIState *s) +static void sdhci_init_readonly_registers(SDHCIState *s, Error **errp) { - switch (SDHC_CAPAB_BLOCKSIZE(s->capareg)) { - case 0: - return 512; - case 1: - return 1024; - case 2: - return 2048; + Error *local_err = NULL; + + switch (s->sd_spec_version) { + case 2 ... 3: + break; default: - hw_error("SDHC: unsupported value for maximum block size\n"); - return 0; + error_setg(errp, "Only Spec v2/v3 are supported"); + return; + } + s->version = (SDHC_HCVER_VENDOR << 8) | (s->sd_spec_version - 1); + + sdhci_check_capareg(s, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; } } /* --- qdev common --- */ #define DEFINE_SDHCI_COMMON_PROPERTIES(_state) \ - /* Capabilities registers provide information on supported features - * of this specific host controller implementation */ \ + DEFINE_PROP_UINT8("sd-spec-version", _state, sd_spec_version, 2), \ + DEFINE_PROP_UINT8("uhs", _state, uhs_mode, UHS_NOT_SUPPORTED), \ + \ + /* Capabilities registers provide information on supported + * features of this specific host controller implementation */ \ DEFINE_PROP_UINT64("capareg", _state, capareg, SDHC_CAPAB_REG_DEFAULT), \ DEFINE_PROP_UINT64("maxcurr", _state, maxcurr, 0) @@ -1206,6 +1368,13 @@ static void sdhci_uninitfn(SDHCIState *s) static void sdhci_common_realize(SDHCIState *s, Error **errp) { + Error *local_err = NULL; + + sdhci_init_readonly_registers(s, &local_err); + if (local_err) { + error_propagate(errp, local_err); + return; + } s->buf_maxsz = sdhci_get_fifolen(s); s->fifo_buffer = g_malloc0(s->buf_maxsz); @@ -1255,7 +1424,7 @@ const VMStateDescription sdhci_vmstate = { VMSTATE_UINT16(cmdreg, SDHCIState), VMSTATE_UINT32_ARRAY(rspreg, SDHCIState, 4), VMSTATE_UINT32(prnsts, SDHCIState), - VMSTATE_UINT8(hostctl, SDHCIState), + VMSTATE_UINT8(hostctl1, SDHCIState), VMSTATE_UINT8(pwrcon, SDHCIState), VMSTATE_UINT8(blkgap, SDHCIState), VMSTATE_UINT8(wakcon, SDHCIState), @@ -1302,10 +1471,12 @@ static Property sdhci_pci_properties[] = { static void sdhci_pci_realize(PCIDevice *dev, Error **errp) { SDHCIState *s = PCI_SDHCI(dev); + Error *local_err = NULL; sdhci_initfn(s); sdhci_common_realize(s, errp); - if (errp && *errp) { + if (local_err) { + error_propagate(errp, local_err); return; } @@ -1383,9 +1554,11 @@ static void sdhci_sysbus_realize(DeviceState *dev, Error ** errp) { SDHCIState *s = SYSBUS_SDHCI(dev); SysBusDevice *sbd = SYS_BUS_DEVICE(dev); + Error *local_err = NULL; sdhci_common_realize(s, errp); - if (errp && *errp) { + if (local_err) { + error_propagate(errp, local_err); return; } @@ -1457,7 +1630,7 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) { SDHCIState *s = SYSBUS_SDHCI(opaque); uint32_t ret; - uint16_t hostctl; + uint16_t hostctl1; switch (offset) { default: @@ -1469,17 +1642,17 @@ static uint64_t usdhc_read(void *opaque, hwaddr offset, unsigned size) * manipulation code see comments in a similar part of * usdhc_write() */ - hostctl = SDHC_DMA_TYPE(s->hostctl) << (8 - 3); + hostctl1 = SDHC_DMA_TYPE(s->hostctl1) << (8 - 3); - if (s->hostctl & SDHC_CTRL_8BITBUS) { - hostctl |= ESDHC_CTRL_8BITBUS; + if (s->hostctl1 & SDHC_CTRL_8BITBUS) { + hostctl1 |= ESDHC_CTRL_8BITBUS; } - if (s->hostctl & SDHC_CTRL_4BITBUS) { - hostctl |= ESDHC_CTRL_4BITBUS; + if (s->hostctl1 & SDHC_CTRL_4BITBUS) { + hostctl1 |= ESDHC_CTRL_4BITBUS; } - ret = hostctl; + ret = hostctl1; ret |= (uint32_t)s->blkgap << 16; ret |= (uint32_t)s->wakcon << 24; @@ -1503,7 +1676,7 @@ static void usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) { SDHCIState *s = SYSBUS_SDHCI(opaque); - uint8_t hostctl; + uint8_t hostctl1; uint32_t value = (uint32_t)val; switch (offset) { @@ -1566,25 +1739,25 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) /* * First, save bits 7 6 and 0 since they are identical */ - hostctl = value & (SDHC_CTRL_LED | - SDHC_CTRL_CDTEST_INS | - SDHC_CTRL_CDTEST_EN); + hostctl1 = value & (SDHC_CTRL_LED | + SDHC_CTRL_CDTEST_INS | + SDHC_CTRL_CDTEST_EN); /* * Second, split "Data Transfer Width" from bits 2 and 1 in to * bits 5 and 1 */ if (value & ESDHC_CTRL_8BITBUS) { - hostctl |= SDHC_CTRL_8BITBUS; + hostctl1 |= SDHC_CTRL_8BITBUS; } if (value & ESDHC_CTRL_4BITBUS) { - hostctl |= ESDHC_CTRL_4BITBUS; + hostctl1 |= ESDHC_CTRL_4BITBUS; } /* * Third, move DMA select from bits 9 and 8 to bits 4 and 3 */ - hostctl |= SDHC_DMA_TYPE(value >> (8 - 3)); + hostctl1 |= SDHC_DMA_TYPE(value >> (8 - 3)); /* * Now place the corrected value into low 16-bit of the value @@ -1595,7 +1768,7 @@ usdhc_write(void *opaque, hwaddr offset, uint64_t val, unsigned size) * kernel */ value &= ~UINT16_MAX; - value |= hostctl; + value |= hostctl1; value |= (uint16_t)s->pwrcon << 8; sdhci_write(opaque, offset, value, size); diff --git a/hw/sd/trace-events b/hw/sd/trace-events index 0a121156a3..0f8536db32 100644 --- a/hw/sd/trace-events +++ b/hw/sd/trace-events @@ -1,5 +1,13 @@ # See docs/devel/tracing.txt for syntax documentation. +# hw/sd/core.c +sdbus_command(const char *bus_name, uint8_t cmd, uint32_t arg, uint8_t crc) "@%s CMD%02d arg 0x%08x crc 0x%02x" +sdbus_read(const char *bus_name, uint8_t value) "@%s value 0x%02x" +sdbus_write(const char *bus_name, uint8_t value) "@%s value 0x%02x" +sdbus_set_voltage(const char *bus_name, uint16_t millivolts) "@%s %u (mV)" +sdbus_get_dat_lines(const char *bus_name, uint8_t dat_lines) "@%s dat_lines: %u" +sdbus_get_cmd_line(const char *bus_name, bool cmd_line) "@%s cmd_line: %u" + # hw/sd/sdhci.c sdhci_set_inserted(const char *level) "card state changed: %s" sdhci_send_command(uint8_t cmd, uint32_t arg) "CMD%02u ARG[0x%08x]" @@ -13,6 +21,7 @@ sdhci_adma_transfer_completed(void) "" sdhci_access(const char *access, unsigned int size, uint64_t offset, const char *dir, uint64_t val, uint64_t val2) "%s%u: addr[0x%04" PRIx64 "] %s 0x%08" PRIx64 " (%" PRIu64 ")" sdhci_read_dataport(uint16_t data_count) "all %u bytes of data have been read from input buffer" sdhci_write_dataport(uint16_t data_count) "write buffer filled with %u bytes of data" +sdhci_capareg(const char *desc, uint16_t val) "%s: %u" # hw/sd/milkymist-memcard.c milkymist_memcard_memory_read(uint32_t addr, uint32_t value) "addr 0x%08x value 0x%08x" |